mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 14:13:01 -04:00
main drm pull request for 4.12 kernel
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZCTzvAAoJEAx081l5xIa+9kcQAJsQiija4/7QGx6IzakOMqjx WulJ3zYG/cU/HLwCBcuWRDF6wAj+7iWNeLCPmolHwEazcI8tQVdgMlWtbdMbDh8U ckzD3FBXsEVfIfab+u6tyoUkm3l/VDhMXbjkUK7NTo/+dkRqe5LuFfZPCGN09jft Y+5salkRXzDhXPSFsqmjfzhx1v7PTgf0a5HUenKWEWOv+sJQaW4/iPvcDSIcg5qR l9WjAqro1NpFYhUodnh6DkLeledL1U5whdtp/yvrUAck8y+WP/jwGYmQ7pZ0UkQm f0M3kV6K67ox9eqN++jsGX5o8sB1qF01Uh95kBAnyzYzsw4ZlMCx6pV7PDX+J88M UBNMEqX10hrLkNJA9lGjPWx+/6fudcwg9anKvTRO3Uyx7MbYoJAgjzAM+yBqqtV0 8Otxa4Bw0V2pmUD+0lqJDERRvE77VCXkLb8SaI5lQo0MHpQqT2cZA+GD+B+rZHO6 Ie5LDFY87vM2GG1IECufG+xOa3v6sn2FfQ1ouu1KNGKOAMBKcQCQyQx3kGVuNW2i HDACVXALJgXdRlVLm4jydOCZdRoguX7AWmRjtdwxgaO+lBcGfLhkXdjLQ7Ho+29p 32ArJfkZPfA53vMB6lHxAfbtrs1q2RzyVnPHj/KqeJnGZbABKTsF2HQ5BQc4Xq/J mqXoz6Oubdvk4Pwyx7Ne =UxFF -----END PGP SIGNATURE----- Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux Pull drm u pdates from Dave Airlie: "This is the main drm pull request for v4.12. Apart from two fixes pulls, everything should have been in drm-next for at least 2 weeks. The biggest thing in here is AMD released the public headers for their upcoming VEGA GPUs. These as always are quite a sizeable chunk of header files. They've also added initial non-display support for those GPUs, though they aren't available in production yet. Otherwise it's pretty much normal. New bridge drivers: - megachips-stdpxxxx-ge-b850v3-fw LVDS->DP++ - generic LVDS bridge support. Core: - Displayport link train failure reporting to userspace - debugfs interface cleaned up - subsystem TODO in kerneldoc now - Extended fbdev support (flipping and vblank wait) - drm_platform removed - EDP CRC support in helper - HF-VSDB SCDC support in EDID parser - Lots of code cleanups and header extraction - Thunderbolt external GPU awareness - Atomic helper improvements - Documentation improvements panel: - Sitronix and Samsung new panel support amdgpu: - Preliminary vega10 support - Multi-level page table support - GPU sensor support for userspace - PRT support for sparse buffers - SR-IOV improvements - Non-contig VRAM CPU mapping i915: - Atomic modesetting enabled by default on Gen5+ - LSPCON improvements - Atomic state handling for cdclk - GPU reset improvements - In-kernel unit tests - Geminilake improvements and color manager support - Designware i2c fixes - vblank evasion improvements - Hotplug safe connector iterators - GVT scheduler QoS support - GVT Kabylake support nouveau: - Acceleration support for Pascal (GP10x). - Rearchitecture of code handling proprietary signed firmware - Fix GTX 970 with odd MMU configuration - GP10B support - GP107 acceleration support vmwgfx: - Atomic modesetting support for vmwgfx omapdrm: - Support for render nodes - Refactor omapdss code - Fix some probe ordering issues - Fix too dark RGB565 rendering sunxi: - prelim rework for multiple pipes. mali-dp: - Color management support - Plane scaling - Power management improvements imx-drm: - Prefetch Resolve Engine/Gasket on i.MX6QP - Deferred plane disabling - Separate alpha support mediatek: - Mediatek SoC MT2701 support rcar-du: - Gen3 HDMI support msm: - 4k support for newer chips - OPP bindings for gpu - prep work for per-process pagetables vc4: - HDMI audio support - fixes qxl: - minor fixes. dw-hdmi: - PHY improvements - CSC fixes - Amlogic GX SoC support" * tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux: (1778 commits) drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr() drm/nouveau/kms: Increase max retries in scanout position queries. drm/nouveau/bios/bitP: check that table is long enough for optional pointers drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine drm: mali-dp: use div_u64 for expensive 64-bit divisions drm/i915: Confirm the request is still active before adding it to the await drm/i915: Avoid busy-spinning on VLV_GLTC_PW_STATUS mmio drm/i915/selftests: Allocate inode/file dynamically drm/i915: Fix system hang with EI UP masked on Haswell drm/i915: checking for NULL instead of IS_ERR() in mock selftests drm/i915: Perform link quality check unconditionally during long pulse drm/i915: Fix use after free in lpe_audio_platdev_destroy() drm/i915: Use the right mapping_gfp_mask for final shmem allocation drm/i915: Make legacy cursor updates more unsynced drm/i915: Apply a cond_resched() to the saturated signaler drm/i915: Park the signaler before sleeping drm: mali-dp: Check the mclk rate and allow up/down scaling drm: mali-dp: Enable image enhancement when scaling drm: mali-dp: Add plane upscaling support ...
This commit is contained in:
Linus Torvalds
commit
2f34c1231b
1060 changed files with 456334 additions and 27130 deletions
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@ -209,6 +209,7 @@ struct drm_amdgpu_gem_userptr {
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__u32 handle;
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};
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/* SI-CI-VI: */
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/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
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#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
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#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
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@ -227,10 +228,15 @@ struct drm_amdgpu_gem_userptr {
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#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
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#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
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/* GFX9 and later: */
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#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
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#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
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/* Set/Get helpers for tiling flags. */
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#define AMDGPU_TILING_SET(field, value) \
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(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
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(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
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#define AMDGPU_TILING_GET(value, field) \
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(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
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(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
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#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
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#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
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@ -350,6 +356,8 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VA_OP_MAP 1
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#define AMDGPU_VA_OP_UNMAP 2
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#define AMDGPU_VA_OP_CLEAR 3
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#define AMDGPU_VA_OP_REPLACE 4
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/* Delay the page table update till the next CS */
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#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
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@ -361,6 +369,20 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
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/* executable mapping, new for VI */
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#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
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/* partially resident texture */
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#define AMDGPU_VM_PAGE_PRT (1 << 4)
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/* MTYPE flags use bit 5 to 8 */
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#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
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/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
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#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
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/* Use NC MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_NC (1 << 5)
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/* Use WC MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_WC (2 << 5)
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/* Use CC MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_CC (3 << 5)
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/* Use UC MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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@ -383,7 +405,8 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_HW_IP_DMA 2
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#define AMDGPU_HW_IP_UVD 3
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#define AMDGPU_HW_IP_VCE 4
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#define AMDGPU_HW_IP_NUM 5
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#define AMDGPU_HW_IP_UVD_ENC 5
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#define AMDGPU_HW_IP_NUM 6
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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@ -422,9 +445,12 @@ union drm_amdgpu_cs {
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/* This IB should be submitted to CE */
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#define AMDGPU_IB_FLAG_CE (1<<0)
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/* CE Preamble */
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/* Preamble flag, which means the IB could be dropped if no context switch */
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#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
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/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
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#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@ -500,6 +526,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_SMC 0x0a
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/* Subquery id: Query SDMA firmware version */
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#define AMDGPU_INFO_FW_SDMA 0x0b
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/* Subquery id: Query PSP SOS firmware version */
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#define AMDGPU_INFO_FW_SOS 0x0c
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/* Subquery id: Query PSP ASD firmware version */
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#define AMDGPU_INFO_FW_ASD 0x0d
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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/* the used VRAM size */
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@ -530,6 +560,22 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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/* Query UVD handles */
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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/* Query sensor related information */
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#define AMDGPU_INFO_SENSOR 0x1D
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/* Subquery id: Query GPU shader clock */
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#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
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/* Subquery id: Query GPU memory clock */
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#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
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/* Subquery id: Query GPU temperature */
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#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
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/* Subquery id: Query GPU load */
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#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
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/* Subquery id: Query average GPU power */
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#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
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/* Subquery id: Query northbridge voltage */
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#define AMDGPU_INFO_SENSOR_VDDNB 0x6
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/* Subquery id: Query graphics voltage */
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#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@ -593,6 +639,10 @@ struct drm_amdgpu_info {
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__u32 type;
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__u32 offset;
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} vbios_info;
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struct {
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__u32 type;
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} sensor_info;
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};
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};
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@ -704,6 +754,16 @@ struct drm_amdgpu_info_device {
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__u32 vram_bit_width;
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/* vce harvesting instance */
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__u32 vce_harvest_config;
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/* gfx double offchip LDS buffers */
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__u32 gc_double_offchip_lds_buf;
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/* NGG Primitive Buffer */
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__u64 prim_buf_gpu_addr;
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/* NGG Position Buffer */
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__u64 pos_buf_gpu_addr;
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/* NGG Control Sideband */
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__u64 cntl_sb_buf_gpu_addr;
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/* NGG Parameter Cache */
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__u64 param_buf_gpu_addr;
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};
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struct drm_amdgpu_info_hw_ip {
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@ -755,6 +815,7 @@ struct drm_amdgpu_info_vce_clock_table {
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#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
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#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
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#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
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#define AMDGPU_FAMILY_AI 141 /* Vega10 */
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#if defined(__cplusplus)
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}
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@ -647,6 +647,7 @@ struct drm_gem_open {
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#define DRM_CAP_CURSOR_HEIGHT 0x9
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#define DRM_CAP_ADDFB2_MODIFIERS 0x10
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#define DRM_CAP_PAGE_FLIP_TARGET 0x11
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#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
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/** DRM_IOCTL_GET_CAP ioctl argument type */
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struct drm_get_cap {
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@ -851,7 +852,7 @@ struct drm_event_vblank {
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 sequence;
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__u32 reserved;
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__u32 crtc_id; /* 0 on older kernels that do not support this */
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};
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/* typedef area */
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@ -113,6 +113,20 @@ extern "C" {
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#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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/*
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* 2 plane RGB + A
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* index 0 = RGB plane, same format as the corresponding non _A8 format has
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* index 1 = A plane, [7:0] A
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*/
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#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
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#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
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#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
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#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
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#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
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#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
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#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
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#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [7:0] Y
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@ -123,6 +123,10 @@ extern "C" {
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#define DRM_MODE_DIRTY_ON 1
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#define DRM_MODE_DIRTY_ANNOTATE 2
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/* Link Status options */
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#define DRM_MODE_LINK_STATUS_GOOD 0
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#define DRM_MODE_LINK_STATUS_BAD 1
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struct drm_mode_modeinfo {
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__u32 clock;
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__u16 hdisplay;
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@ -154,6 +154,12 @@ struct drm_etnaviv_gem_submit_bo {
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
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#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
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#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
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#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
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ETNA_SUBMIT_FENCE_FD_IN | \
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ETNA_SUBMIT_FENCE_FD_OUT)
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#define ETNA_PIPE_3D 0x00
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#define ETNA_PIPE_2D 0x01
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#define ETNA_PIPE_VG 0x02
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@ -167,6 +173,8 @@ struct drm_etnaviv_gem_submit {
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__u64 bos; /* in, ptr to array of submit_bo's */
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__u64 relocs; /* in, ptr to array of submit_reloc's */
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__u64 stream; /* in, ptr to cmdstream */
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__u32 flags; /* in, mask of ETNA_SUBMIT_x */
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__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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@ -246,6 +246,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_I915_GEM_EXECBUFFER2 0x29
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#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
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#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
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#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
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#define DRM_I915_GEM_WAIT 0x2c
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@ -280,6 +281,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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@ -397,6 +399,19 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_SCHEDULER 41
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#define I915_PARAM_HUC_STATUS 42
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/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
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* synchronisation with implicit fencing on individual objects.
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* See EXEC_OBJECT_ASYNC.
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*/
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#define I915_PARAM_HAS_EXEC_ASYNC 43
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/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
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* both being able to pass in a sync_file fd to wait upon before executing,
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* and being able to return a new sync_file fd that is signaled when the
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* current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
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*/
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#define I915_PARAM_HAS_EXEC_FENCE 44
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typedef struct drm_i915_getparam {
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__s32 param;
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/*
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@ -737,8 +752,29 @@ struct drm_i915_gem_exec_object2 {
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#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
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#define EXEC_OBJECT_PINNED (1<<4)
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#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
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/* The kernel implicitly tracks GPU activity on all GEM objects, and
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* synchronises operations with outstanding rendering. This includes
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* rendering on other devices if exported via dma-buf. However, sometimes
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* this tracking is too coarse and the user knows better. For example,
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* if the object is split into non-overlapping ranges shared between different
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* clients or engines (i.e. suballocating objects), the implicit tracking
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* by kernel assumes that each operation affects the whole object rather
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* than an individual range, causing needless synchronisation between clients.
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* The kernel will also forgo any CPU cache flushes prior to rendering from
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* the object as the client is expected to be also handling such domain
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* tracking.
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*
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* The kernel maintains the implicit tracking in order to manage resources
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* used by the GPU - this flag only disables the synchronisation prior to
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* rendering with this object in this execbuf.
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*
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* Opting out of implicit synhronisation requires the user to do its own
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* explicit tracking to avoid rendering corruption. See, for example,
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* I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
|
||||
*/
|
||||
#define EXEC_OBJECT_ASYNC (1<<6)
|
||||
/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1)
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
|
||||
__u64 flags;
|
||||
|
||||
union {
|
||||
|
|
@ -828,7 +864,32 @@ struct drm_i915_gem_execbuffer2 {
|
|||
*/
|
||||
#define I915_EXEC_RESOURCE_STREAMER (1<<15)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
|
||||
/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
|
||||
* a sync_file fd to wait upon (in a nonblocking manner) prior to executing
|
||||
* the batch.
|
||||
*
|
||||
* Returns -EINVAL if the sync_file fd cannot be found.
|
||||
*/
|
||||
#define I915_EXEC_FENCE_IN (1<<16)
|
||||
|
||||
/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
|
||||
* in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
|
||||
* to the caller, and it should be close() after use. (The fd is a regular
|
||||
* file descriptor and will be cleaned up on process termination. It holds
|
||||
* a reference to the request, but nothing else.)
|
||||
*
|
||||
* The sync_file fd can be combined with other sync_file and passed either
|
||||
* to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
|
||||
* will only occur after this request completes), or to other devices.
|
||||
*
|
||||
* Using I915_EXEC_FENCE_OUT requires use of
|
||||
* DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
|
||||
* back to userspace. Failure to do so will cause the out-fence to always
|
||||
* be reported as zero, and the real fence fd to be leaked.
|
||||
*/
|
||||
#define I915_EXEC_FENCE_OUT (1<<17)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ struct drm_msm_timespec {
|
|||
#define MSM_PARAM_CHIP_ID 0x03
|
||||
#define MSM_PARAM_MAX_FREQ 0x04
|
||||
#define MSM_PARAM_TIMESTAMP 0x05
|
||||
#define MSM_PARAM_GMEM_BASE 0x06
|
||||
|
||||
struct drm_msm_param {
|
||||
__u32 pipe; /* in, MSM_PIPE_x */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ extern "C" {
|
|||
#define DRM_VMW_GET_PARAM 0
|
||||
#define DRM_VMW_ALLOC_DMABUF 1
|
||||
#define DRM_VMW_UNREF_DMABUF 2
|
||||
#define DRM_VMW_HANDLE_CLOSE 2
|
||||
#define DRM_VMW_CURSOR_BYPASS 3
|
||||
/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/
|
||||
#define DRM_VMW_CONTROL_STREAM 4
|
||||
|
|
@ -1092,6 +1093,29 @@ union drm_vmw_extended_context_arg {
|
|||
struct drm_vmw_context_arg rep;
|
||||
};
|
||||
|
||||
/*************************************************************************/
|
||||
/*
|
||||
* DRM_VMW_HANDLE_CLOSE - Close a user-space handle and release its
|
||||
* underlying resource.
|
||||
*
|
||||
* Note that this ioctl is overlaid on the DRM_VMW_UNREF_DMABUF Ioctl.
|
||||
* The ioctl arguments therefore need to be identical in layout.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct drm_vmw_handle_close_arg
|
||||
*
|
||||
* @handle: Handle to close.
|
||||
*
|
||||
* Argument to the DRM_VMW_HANDLE_CLOSE Ioctl.
|
||||
*/
|
||||
struct drm_vmw_handle_close_arg {
|
||||
__u32 handle;
|
||||
__u32 pad64;
|
||||
};
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
|
||||
#define MEDIA_BUS_FMT_FIXED 0x0001
|
||||
|
||||
/* RGB - next is 0x1018 */
|
||||
/* RGB - next is 0x101b */
|
||||
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
|
||||
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
|
||||
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
|
||||
|
|
@ -57,8 +57,11 @@
|
|||
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
|
||||
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
|
||||
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
|
||||
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
|
||||
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
|
||||
#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
|
||||
|
||||
/* YUV (including grey) - next is 0x2026 */
|
||||
/* YUV (including grey) - next is 0x202c */
|
||||
#define MEDIA_BUS_FMT_Y8_1X8 0x2001
|
||||
#define MEDIA_BUS_FMT_UV8_1X8 0x2015
|
||||
#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
|
||||
|
|
@ -90,12 +93,18 @@
|
|||
#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
|
||||
#define MEDIA_BUS_FMT_VUY8_1X24 0x2024
|
||||
#define MEDIA_BUS_FMT_YUV8_1X24 0x2025
|
||||
#define MEDIA_BUS_FMT_UYYVYY8_0_5X24 0x2026
|
||||
#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020
|
||||
#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021
|
||||
#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022
|
||||
#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023
|
||||
#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
|
||||
#define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027
|
||||
#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
|
||||
#define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028
|
||||
#define MEDIA_BUS_FMT_YUV12_1X36 0x2029
|
||||
#define MEDIA_BUS_FMT_YUV16_1X48 0x202a
|
||||
#define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b
|
||||
|
||||
/* Bayer - next is 0x3021 */
|
||||
#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001
|
||||
|
|
|
|||
Loading…
Reference in a new issue