From 2f3a90b47d7ad72aec08d5aaed1e7435997dea42 Mon Sep 17 00:00:00 2001
From: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Date: Tue, 30 Apr 2019 19:25:11 -0700
Subject: [PATCH] disp: pll: update SSC offset value

This change updates SSC offset value according to recent
hardware recommendation.

Change-Id: Ie822ed6ae8e383f93ca91615617dad4b4324b8a0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
---
 pll/dsi_pll_7nm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pll/dsi_pll_7nm.c b/pll/dsi_pll_7nm.c
index 17aa2bc892c9..d12fa86da0a0 100644
--- a/pll/dsi_pll_7nm.c
+++ b/pll/dsi_pll_7nm.c
@@ -483,7 +483,7 @@ static void dsi_pll_setup_config(struct dsi_pll_7nm *pll,
 	config->frac_bits = 18;
 	config->lock_timer = 64;
 	config->ssc_freq = 31500;
-	config->ssc_offset = 5000;
+	config->ssc_offset = 4800;
 	config->ssc_adj_per = 2;
 	config->thresh_cycles = 32;
 	config->refclk_cycles = 256;