From daa016e980ed4956bd9da7275728e40d97af456f Mon Sep 17 00:00:00 2001
From: Yuanfang Zhang <yuanfang@qti.qualcomm.com>
Date: Wed, 3 Mar 2021 19:04:24 +0800
Subject: [PATCH] ARM: dts: msm: correct dcc offset on sdxlemur

The first 2KB should be reserved for TZ, so correct the offset to
0x800.

Change-Id: I1f4b0ad01865e3374252a54074c5bd1f5fa02b7e
---
 qcom/sdxlemur.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 7c1f15927966..010f9865d0de 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -221,12 +221,12 @@
 	dcc: dcc_v2@117f000 {
 		compatible = "qcom,dcc-v2";
 		reg = <0x117f000 0x1000>,
-		      <0x1100000 0x2000>;
+		      <0x1100800 0x1800>;
 
 		qcom,transaction_timeout = <0>;
 
 		reg-names = "dcc-base", "dcc-ram-base";
-		dcc-ram-offset = <0x12000>;
+		dcc-ram-offset = <0x800>;
 
 		link_list1 {
 			qcom,curr-link-list = <2>;