mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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qcacld-3.0: Clean up legacy HE CAP Cfg items
Cleanup of HE caps cfg items from legacy path. Change-Id: I769601f4d0f1681cee7168069e63f3f7ceab0475 CRs-Fixed: 2353934
This commit is contained in:
Bala Venkatesh
nshrivas
parent
8647c72757
commit
2fae18aa35
6 changed files with 20 additions and 1305 deletions
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@ -699,6 +699,8 @@ struct wlan_mlme_qos {
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#ifdef WLAN_FEATURE_11AX
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#define MLME_HE_PPET_LEN 25
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#define WNI_CFG_HE_OPS_BSS_COLOR_MAX 0x3F
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/**
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* struct wlan_mlme_he_caps - HE Capabilities related config items
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*/
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@ -29,257 +29,14 @@
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#include "wlan_utility.h"
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#include "wlan_mlme_ucfg_api.h"
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/**
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* hdd_he_set_wni_cfg() - Update WNI CFG
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* @hdd_ctx: HDD context
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* @cfg_id: CFG to be updated
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* @new_value: Value to be updated
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*
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* Update WNI CFG with the value passed.
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*
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* Return: 0 on success and errno on failure
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*/
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static int hdd_he_set_wni_cfg(struct hdd_context *hdd_ctx,
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uint16_t cfg_id, uint32_t new_value)
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{
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QDF_STATUS status;
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status = sme_cfg_set_int(hdd_ctx->mac_handle, cfg_id, new_value);
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if (QDF_IS_STATUS_ERROR(status))
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hdd_err("could not set %s", cfg_get_string(cfg_id));
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return qdf_status_to_os_return(status);
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}
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void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
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struct wma_tgt_cfg *cfg)
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{
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uint8_t chan_width;
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QDF_STATUS status;
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tDot11fIEhe_cap *he_cap = &cfg->he_cap;
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tDot11fIEhe_cap he_cap_ini = {0};
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uint8_t value = 0;
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bool bval;
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ucfg_mlme_update_tgt_he_cap(hdd_ctx->psoc, cfg);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_CONTROL, he_cap->htc_he);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TWT_REQUESTOR,
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he_cap->twt_request);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TWT_RESPONDER,
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he_cap->twt_responder);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_FRAGMENTATION,
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QDF_MIN(he_cap->fragmentation,
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hdd_ctx->config->he_dynamic_frag_support));
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MAX_FRAG_MSDU,
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he_cap->max_num_frag_msdu_amsdu_exp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIN_FRAG_SIZE,
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he_cap->min_frag_size);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TRIG_PAD,
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he_cap->trigger_frm_mac_pad);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MTID_AGGR_RX,
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he_cap->multi_tid_aggr_rx_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MTID_AGGR_TX,
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he_cap->multi_tid_aggr_tx_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LINK_ADAPTATION,
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he_cap->he_link_adaptation);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ALL_ACK, he_cap->all_ack);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
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he_cap->trigd_rsp_sched);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BUFFER_STATUS_RPT,
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he_cap->a_bsr);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BCAST_TWT,
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he_cap->broadcast_twt);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BA_32BIT,
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he_cap->ba_32bit_bitmap);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MU_CASCADING,
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he_cap->mu_cascade);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MULTI_TID,
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he_cap->ack_enabled_multitid);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OMI, he_cap->omi_a_ctrl);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OFDMA_RA, he_cap->ofdma_ra);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MAX_AMPDU_LEN,
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he_cap->max_ampdu_len_exp_ext);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_AMSDU_FRAG, he_cap->amsdu_frag);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_FLEX_TWT_SCHED,
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he_cap->flex_twt_sched);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_CTRL, he_cap->rx_ctrl_frame);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BSRP_AMPDU_AGGR,
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he_cap->bsrp_ampdu_aggr);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_QTP, he_cap->qtp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_A_BQR, he_cap->a_bqr);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SR_RESPONDER,
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he_cap->spatial_reuse_param_rspder);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NDP_FEEDBACK_SUPP,
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he_cap->ndp_feedback_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OPS_SUPP,
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he_cap->ops_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_AMSDU_IN_AMPDU,
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he_cap->amsdu_in_ampdu);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SUB_CH_SEL_TX,
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he_cap->he_sub_ch_sel_tx_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_UL_2X996_RU,
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he_cap->ul_2x996_tone_ru_supp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
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he_cap->om_ctrl_ul_mu_data_dis_rx);
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chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0,
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he_cap->chan_width_1, he_cap->chan_width_2,
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he_cap->chan_width_3, he_cap->chan_width_4,
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he_cap->chan_width_5, he_cap->chan_width_6);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_CHAN_WIDTH, chan_width);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_PREAM_PUNC,
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he_cap->rx_pream_puncturing);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_CLASS_OF_DEVICE,
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he_cap->device_class);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LDPC, he_cap->ldpc_coding);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LTF_PPDU,
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he_cap->he_1x_ltf_800_gi_ppdu);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS,
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he_cap->midamble_tx_rx_max_nsts);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LTF_NDP,
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he_cap->he_4x_ltf_3200_gi_ndp);
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status = ucfg_mlme_cfg_get_vht_rx_stbc(hdd_ctx->psoc, &bval);
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if (QDF_IS_STATUS_ERROR(status))
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hdd_err("unable to get vht_enable_rx_su_beam");
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if (bval) {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_STBC_LT80,
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he_cap->rx_stbc_lt_80mhz);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_STBC_GT80,
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he_cap->rx_stbc_gt_80mhz);
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} else {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_STBC_LT80, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_STBC_GT80, 0);
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}
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status = ucfg_mlme_cfg_get_vht_tx_stbc(hdd_ctx->psoc,
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&bval);
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if (!QDF_IS_STATUS_SUCCESS(status))
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hdd_err("unable to get vht_enable_tx_su_beam");
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if (bval) {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_STBC_LT80,
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he_cap->tx_stbc_lt_80mhz);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_STBC_GT80,
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he_cap->tx_stbc_gt_80mhz);
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} else {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_STBC_LT80, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_STBC_GT80, 0);
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}
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DOPPLER, he_cap->doppler);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_UL_MUMIMO, he_cap->ul_mu);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DCM_TX, he_cap->dcm_enc_tx);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DCM_RX, he_cap->dcm_enc_rx);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MU_PPDU, he_cap->ul_he_mu);
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status = ucfg_mlme_get_vht_tx_su_beamformer(hdd_ctx->psoc, &bval);
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if (!QDF_IS_STATUS_SUCCESS(status))
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hdd_err("unable to get vht_enable_tx_su_beam");
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if (bval) {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SU_BEAMFORMER,
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he_cap->su_beamformer);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NUM_SOUND_LT80,
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he_cap->num_sounding_lt_80);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NUM_SOUND_GT80,
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he_cap->num_sounding_gt_80);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MU_BEAMFORMER,
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he_cap->mu_beamformer);
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} else {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SU_BEAMFORMER, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NUM_SOUND_LT80, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NUM_SOUND_GT80, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MU_BEAMFORMER, 0);
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}
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status = ucfg_mlme_get_vht_enable_tx_bf(hdd_ctx->psoc, &bval);
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if (!QDF_IS_STATUS_SUCCESS(status))
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hdd_err("unable to get vht_enable_tx_bf");
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if (bval) {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SU_BEAMFORMEE,
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he_cap->su_beamformee);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BFEE_STS_LT80,
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he_cap->bfee_sts_lt_80);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BFEE_STS_GT80,
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he_cap->bfee_sts_gt_80);
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} else {
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SU_BEAMFORMEE, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BFEE_STS_LT80, 0);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BFEE_STS_GT80, 0);
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}
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SU_FEED_TONE16,
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he_cap->su_feedback_tone16);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MU_FEED_TONE16,
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he_cap->mu_feedback_tone16);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_CODEBOOK_SU,
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he_cap->codebook_su);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_CODEBOOK_MU,
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he_cap->codebook_mu);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BFRM_FEED,
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he_cap->beamforming_feedback);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ER_SU_PPDU,
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he_cap->he_er_su_ppdu);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DL_PART_BW,
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he_cap->dl_mu_mimo_part_bw);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_PPET_PRESENT,
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he_cap->ppet_present);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SRP, he_cap->srp);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_POWER_BOOST,
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he_cap->power_boost);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_4x_LTF_GI,
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he_cap->he_ltf_800_gi_4x);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MAX_NC, he_cap->max_nc);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ER_4x_LTF_GI,
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he_cap->er_he_ltf_800_gi_4x);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_PPDU_20_IN_40MHZ_2G,
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he_cap->he_ppdu_20_in_40Mhz_2G);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ,
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he_cap->he_ppdu_20_in_160_80p80Mhz);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ,
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he_cap->he_ppdu_80_in_160_80p80Mhz);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ER_1X_HE_LTF_GI,
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he_cap->er_1x_he_ltf_gi);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
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he_cap->midamble_tx_rx_1x_he_ltf);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DCM_MAX_BW,
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he_cap->dcm_max_bw);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
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he_cap->longer_than_16_he_sigb_ofdm_sym);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
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he_cap->tx_1024_qam_lt_242_tone_ru);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
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he_cap->rx_1024_qam_lt_242_tone_ru);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
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he_cap->non_trig_cqi_feedback);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
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he_cap->rx_full_bw_su_he_mu_compress_sigb);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
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he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_MCS_MAP_LT_80,
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he_cap->rx_he_mcs_map_lt_80);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_MCS_MAP_LT_80,
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he_cap->tx_he_mcs_map_lt_80);
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_MCS_MAP_160,
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*((uint16_t *)he_cap->rx_he_mcs_map_160));
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_MCS_MAP_160,
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*((uint16_t *)he_cap->tx_he_mcs_map_160));
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_MCS_MAP_80_80,
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*((uint16_t *)he_cap->rx_he_mcs_map_80_80));
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hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_MCS_MAP_80_80,
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*((uint16_t *)he_cap->tx_he_mcs_map_80_80));
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/* PPET can not be configured by user - Set per band values from FW */
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status = sme_cfg_set_str(hdd_ctx->mac_handle, WNI_CFG_HE_PPET_2G,
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cfg->ppet_2g, HE_MAX_PPET_SIZE);
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if (status == QDF_STATUS_E_FAILURE)
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hdd_alert("could not set 2G HE PPET");
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status = sme_cfg_set_str(hdd_ctx->mac_handle, WNI_CFG_HE_PPET_5G,
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cfg->ppet_5g, HE_MAX_PPET_SIZE);
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if (status == QDF_STATUS_E_FAILURE)
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hdd_alert("could not set 5G HE PPET");
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status = ucfg_mlme_cfg_get_vht_tx_bfee_ant_supp(hdd_ctx->psoc,
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&value);
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@ -49,108 +49,7 @@ enum {
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WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED,
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WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP,
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WNI_CFG_IBSS_ATIM_WIN_SIZE,
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WNI_CFG_HE_CONTROL,
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WNI_CFG_HE_TWT_REQUESTOR,
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WNI_CFG_HE_TWT_RESPONDER,
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WNI_CFG_HE_FRAGMENTATION,
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WNI_CFG_HE_MAX_FRAG_MSDU,
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WNI_CFG_HE_MIN_FRAG_SIZE,
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WNI_CFG_HE_TRIG_PAD,
|
||||
WNI_CFG_HE_MTID_AGGR_RX,
|
||||
WNI_CFG_HE_LINK_ADAPTATION,
|
||||
WNI_CFG_HE_ALL_ACK,
|
||||
WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
|
||||
WNI_CFG_HE_BUFFER_STATUS_RPT,
|
||||
WNI_CFG_HE_BCAST_TWT,
|
||||
WNI_CFG_HE_BA_32BIT,
|
||||
WNI_CFG_HE_MU_CASCADING,
|
||||
WNI_CFG_HE_MULTI_TID,
|
||||
WNI_CFG_HE_DL_MU_BA,
|
||||
WNI_CFG_HE_OMI,
|
||||
WNI_CFG_HE_OFDMA_RA,
|
||||
WNI_CFG_HE_MAX_AMPDU_LEN,
|
||||
WNI_CFG_HE_AMSDU_FRAG,
|
||||
WNI_CFG_HE_FLEX_TWT_SCHED,
|
||||
WNI_CFG_HE_RX_CTRL,
|
||||
WNI_CFG_HE_BSRP_AMPDU_AGGR,
|
||||
WNI_CFG_HE_QTP,
|
||||
WNI_CFG_HE_A_BQR,
|
||||
WNI_CFG_HE_SR_RESPONDER,
|
||||
WNI_CFG_HE_NDP_FEEDBACK_SUPP,
|
||||
WNI_CFG_HE_OPS_SUPP,
|
||||
WNI_CFG_HE_AMSDU_IN_AMPDU,
|
||||
WNI_CFG_HE_MTID_AGGR_TX,
|
||||
WNI_CFG_HE_SUB_CH_SEL_TX,
|
||||
WNI_CFG_HE_UL_2X996_RU,
|
||||
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
|
||||
WNI_CFG_HE_CHAN_WIDTH,
|
||||
WNI_CFG_HE_RX_PREAM_PUNC,
|
||||
WNI_CFG_HE_CLASS_OF_DEVICE,
|
||||
WNI_CFG_HE_LDPC,
|
||||
WNI_CFG_HE_LTF_PPDU,
|
||||
WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS,
|
||||
WNI_CFG_HE_LTF_NDP,
|
||||
WNI_CFG_HE_TX_STBC_LT80,
|
||||
WNI_CFG_HE_RX_STBC_LT80,
|
||||
WNI_CFG_HE_DOPPLER,
|
||||
WNI_CFG_HE_UL_MUMIMO,
|
||||
WNI_CFG_HE_DCM_TX,
|
||||
WNI_CFG_HE_DCM_RX,
|
||||
WNI_CFG_HE_MU_PPDU,
|
||||
WNI_CFG_HE_SU_BEAMFORMER,
|
||||
WNI_CFG_HE_SU_BEAMFORMEE,
|
||||
WNI_CFG_HE_MU_BEAMFORMER,
|
||||
WNI_CFG_HE_BFEE_STS_LT80,
|
||||
WNI_CFG_HE_BFEE_STS_GT80,
|
||||
WNI_CFG_HE_NUM_SOUND_LT80,
|
||||
WNI_CFG_HE_NUM_SOUND_GT80,
|
||||
WNI_CFG_HE_SU_FEED_TONE16,
|
||||
WNI_CFG_HE_MU_FEED_TONE16,
|
||||
WNI_CFG_HE_CODEBOOK_SU,
|
||||
WNI_CFG_HE_CODEBOOK_MU,
|
||||
WNI_CFG_HE_BFRM_FEED,
|
||||
WNI_CFG_HE_ER_SU_PPDU,
|
||||
WNI_CFG_HE_DL_PART_BW,
|
||||
WNI_CFG_HE_PPET_PRESENT,
|
||||
WNI_CFG_HE_SRP,
|
||||
WNI_CFG_HE_POWER_BOOST,
|
||||
WNI_CFG_HE_4x_LTF_GI,
|
||||
WNI_CFG_HE_MAX_NC,
|
||||
WNI_CFG_HE_TX_STBC_GT80,
|
||||
WNI_CFG_HE_RX_STBC_GT80,
|
||||
WNI_CFG_HE_ER_4x_LTF_GI,
|
||||
WNI_CFG_HE_PPDU_20_IN_40MHZ_2G,
|
||||
WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ,
|
||||
WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ,
|
||||
WNI_CFG_HE_ER_1X_HE_LTF_GI,
|
||||
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
|
||||
WNI_CFG_HE_DCM_MAX_BW,
|
||||
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
|
||||
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
|
||||
WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
|
||||
WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
|
||||
WNI_CFG_HE_RX_MCS_MAP_LT_80,
|
||||
WNI_CFG_HE_TX_MCS_MAP_LT_80,
|
||||
WNI_CFG_HE_RX_MCS_MAP_160,
|
||||
WNI_CFG_HE_TX_MCS_MAP_160,
|
||||
WNI_CFG_HE_RX_MCS_MAP_80_80,
|
||||
WNI_CFG_HE_TX_MCS_MAP_80_80,
|
||||
WNI_CFG_HE_PPET_2G,
|
||||
WNI_CFG_HE_PPET_5G,
|
||||
WNI_CFG_HE_OPS_BSS_COLOR,
|
||||
WNI_CFG_HE_OPS_DEFAULT_PE,
|
||||
WNI_CFG_HE_OPS_TWT_REQUIRED,
|
||||
WNI_CFG_HE_OPS_RTS_THRESHOLD,
|
||||
WNI_CFG_HE_OPS_PARTIAL_BSS_COL,
|
||||
WNI_CFG_HE_OPS_VHT_OPER_PRESENT,
|
||||
WNI_CFG_HE_OPS_MBSSID_AP,
|
||||
WNI_CFG_HE_OPS_TX_BSSID_IND,
|
||||
WNI_CFG_HE_OPS_BSS_COL_DISABLED,
|
||||
WNI_CFG_HE_OPS_BASIC_MCS_NSS,
|
||||
WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT,
|
||||
WNI_CFG_HE_STA_OBSSPD,
|
||||
WNI_CFG_OBSS_DETECTION_OFFLOAD,
|
||||
WNI_CFG_OBSS_COLOR_COLLISION_OFFLOAD,
|
||||
WNI_CFG_TWT_REQUESTOR,
|
||||
|
|
@ -538,402 +437,6 @@ enum {
|
|||
#define WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMAX 100
|
||||
#define WNI_CFG_IBSS_ATIM_WIN_SIZE_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_CONTROL_STAMIN 0
|
||||
#define WNI_CFG_HE_CONTROL_STAMAX 1
|
||||
#define WNI_CFG_HE_CONTROL_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TWT_REQUESTOR_STAMIN 0
|
||||
#define WNI_CFG_HE_TWT_REQUESTOR_STAMAX 1
|
||||
#define WNI_CFG_HE_TWT_REQUESTOR_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TWT_RESPONDER_STAMIN 0
|
||||
#define WNI_CFG_HE_TWT_RESPONDER_STAMAX 1
|
||||
#define WNI_CFG_HE_TWT_RESPONDER_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_FRAGMENTATION_STAMIN 0
|
||||
#define WNI_CFG_HE_FRAGMENTATION_STAMAX 0x3
|
||||
#define WNI_CFG_HE_FRAGMENTATION_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MAX_FRAG_MSDU_STAMIN 0
|
||||
#define WNI_CFG_HE_MAX_FRAG_MSDU_STAMAX 0x7
|
||||
#define WNI_CFG_HE_MAX_FRAG_MSDU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MIN_FRAG_SIZE_STAMIN 0
|
||||
#define WNI_CFG_HE_MIN_FRAG_SIZE_STAMAX 0x3
|
||||
#define WNI_CFG_HE_MIN_FRAG_SIZE_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TRIG_PAD_STAMIN 0
|
||||
#define WNI_CFG_HE_TRIG_PAD_STAMAX 2
|
||||
#define WNI_CFG_HE_TRIG_PAD_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MTID_AGGR_RX_STAMIN 0
|
||||
#define WNI_CFG_HE_MTID_AGGR_RX_STAMAX 0x7
|
||||
#define WNI_CFG_HE_MTID_AGGR_RX_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_LINK_ADAPTATION_STAMIN 0
|
||||
#define WNI_CFG_HE_LINK_ADAPTATION_STAMAX 0x3
|
||||
#define WNI_CFG_HE_LINK_ADAPTATION_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_ALL_ACK_STAMIN 0
|
||||
#define WNI_CFG_HE_ALL_ACK_STAMAX 1
|
||||
#define WNI_CFG_HE_ALL_ACK_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMIN 0
|
||||
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMAX 1
|
||||
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN 0
|
||||
#define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMAX 1
|
||||
#define WNI_CFG_HE_BUFFER_STATUS_RPT_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BCAST_TWT_STAMIN 0
|
||||
#define WNI_CFG_HE_BCAST_TWT_STAMAX 1
|
||||
#define WNI_CFG_HE_BCAST_TWT_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BA_32BIT_STAMIN 0
|
||||
#define WNI_CFG_HE_BA_32BIT_STAMAX 1
|
||||
#define WNI_CFG_HE_BA_32BIT_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MU_CASCADING_STAMIN 0
|
||||
#define WNI_CFG_HE_MU_CASCADING_STAMAX 1
|
||||
#define WNI_CFG_HE_MU_CASCADING_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MULTI_TID_STAMIN 0
|
||||
#define WNI_CFG_HE_MULTI_TID_STAMAX 1
|
||||
#define WNI_CFG_HE_MULTI_TID_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_DL_MU_BA_STAMIN 0
|
||||
#define WNI_CFG_HE_DL_MU_BA_STAMAX 1
|
||||
#define WNI_CFG_HE_DL_MU_BA_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_OMI_STAMIN 0
|
||||
#define WNI_CFG_HE_OMI_STAMAX 1
|
||||
#define WNI_CFG_HE_OMI_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_OFDMA_RA_STAMIN 0
|
||||
#define WNI_CFG_HE_OFDMA_RA_STAMAX 1
|
||||
#define WNI_CFG_HE_OFDMA_RA_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MAX_AMPDU_LEN_STAMIN 0
|
||||
#define WNI_CFG_HE_MAX_AMPDU_LEN_STAMAX 0x3
|
||||
#define WNI_CFG_HE_MAX_AMPDU_LEN_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_AMSDU_FRAG_STAMIN 0
|
||||
#define WNI_CFG_HE_AMSDU_FRAG_STAMAX 1
|
||||
#define WNI_CFG_HE_AMSDU_FRAG_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_FLEX_TWT_SCHED_STAMIN 0
|
||||
#define WNI_CFG_HE_FLEX_TWT_SCHED_STAMAX 1
|
||||
#define WNI_CFG_HE_FLEX_TWT_SCHED_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_CTRL_STAMIN 0
|
||||
#define WNI_CFG_HE_RX_CTRL_STAMAX 1
|
||||
#define WNI_CFG_HE_RX_CTRL_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMIN 0
|
||||
#define WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMAX 1
|
||||
#define WNI_CFG_HE_BSRP_AMPDU_AGGR_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_QTP_STAMIN 0
|
||||
#define WNI_CFG_HE_QTP_STAMAX 1
|
||||
#define WNI_CFG_HE_QTP_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_A_BQR_STAMIN 0
|
||||
#define WNI_CFG_HE_A_BQR_STAMAX 1
|
||||
#define WNI_CFG_HE_A_BQR_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_SR_RESPONDER_STAMIN 0
|
||||
#define WNI_CFG_HE_SR_RESPONDER_STAMAX 1
|
||||
#define WNI_CFG_HE_SR_RESPONDER_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_NDP_FEEDBACK_SUPP_STAMIN 0
|
||||
#define WNI_CFG_HE_NDP_FEEDBACK_SUPP_STAMAX 1
|
||||
#define WNI_CFG_HE_NDP_FEEDBACK_SUPP_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_SUPP_STAMIN 0
|
||||
#define WNI_CFG_HE_OPS_SUPP_STAMAX 1
|
||||
#define WNI_CFG_HE_OPS_SUPP_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_AMSDU_IN_AMPDU_MIN 0
|
||||
#define WNI_CFG_HE_AMSDU_IN_AMPDU_MAX 1
|
||||
#define WNI_CFG_HE_AMSDU_IN_AMPDU_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_MTID_AGGR_TX_MIN 0
|
||||
#define WNI_CFG_HE_MTID_AGGR_TX_MAX 0x7
|
||||
#define WNI_CFG_HE_MTID_AGGR_TX_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_SUB_CH_SEL_TX_MIN 0
|
||||
#define WNI_CFG_HE_SUB_CH_SEL_TX_MAX 1
|
||||
#define WNI_CFG_HE_SUB_CH_SEL_TX_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_UL_2X996_RU_MIN 0
|
||||
#define WNI_CFG_HE_UL_2X996_RU_MAX 1
|
||||
#define WNI_CFG_HE_UL_2X996_RU_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MIN 0
|
||||
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MAX 1
|
||||
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_CHAN_WIDTH_STAMIN 0
|
||||
#define WNI_CFG_HE_CHAN_WIDTH_STAMAX 0x3F
|
||||
#define WNI_CFG_HE_CHAN_WIDTH_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_PREAM_PUNC_STAMIN 0
|
||||
#define WNI_CFG_HE_RX_PREAM_PUNC_STAMAX 0xF
|
||||
#define WNI_CFG_HE_RX_PREAM_PUNC_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_CLASS_OF_DEVICE_STAMIN 0
|
||||
#define WNI_CFG_HE_CLASS_OF_DEVICE_STAMAX 1
|
||||
#define WNI_CFG_HE_CLASS_OF_DEVICE_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_LDPC_STAMIN 0
|
||||
#define WNI_CFG_HE_LDPC_STAMAX 1
|
||||
#define WNI_CFG_HE_LDPC_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_LTF_PPDU_STAMIN 0
|
||||
#define WNI_CFG_HE_LTF_PPDU_STAMAX 0x3
|
||||
#define WNI_CFG_HE_LTF_PPDU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_MIN 0
|
||||
#define WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_MAX 0x3
|
||||
#define WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_LTF_NDP_STAMIN 0
|
||||
#define WNI_CFG_HE_LTF_NDP_STAMAX 0x3
|
||||
#define WNI_CFG_HE_LTF_NDP_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TX_STBC_LT80_STAMIN 0
|
||||
#define WNI_CFG_HE_TX_STBC_LT80_STAMAX 1
|
||||
#define WNI_CFG_HE_TX_STBC_LT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_STBC_LT80_STAMIN 0
|
||||
#define WNI_CFG_HE_RX_STBC_LT80_STAMAX 1
|
||||
#define WNI_CFG_HE_RX_STBC_LT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_DOPPLER_STAMIN 0
|
||||
#define WNI_CFG_HE_DOPPLER_STAMAX 0x3
|
||||
#define WNI_CFG_HE_DOPPLER_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_UL_MUMIMO_STAMIN 0
|
||||
#define WNI_CFG_HE_UL_MUMIMO_STAMAX 0x3
|
||||
#define WNI_CFG_HE_UL_MUMIMO_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_DCM_TX_STAMIN 0
|
||||
#define WNI_CFG_HE_DCM_TX_STAMAX 0x7
|
||||
#define WNI_CFG_HE_DCM_TX_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_DCM_RX_STAMIN 0
|
||||
#define WNI_CFG_HE_DCM_RX_STAMAX 0x7
|
||||
#define WNI_CFG_HE_DCM_RX_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MU_PPDU_STAMIN 0
|
||||
#define WNI_CFG_HE_MU_PPDU_STAMAX 1
|
||||
#define WNI_CFG_HE_MU_PPDU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_SU_BEAMFORMER_STAMIN 0
|
||||
#define WNI_CFG_HE_SU_BEAMFORMER_STAMAX 1
|
||||
#define WNI_CFG_HE_SU_BEAMFORMER_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_SU_BEAMFORMEE_STAMIN 0
|
||||
#define WNI_CFG_HE_SU_BEAMFORMEE_STAMAX 1
|
||||
#define WNI_CFG_HE_SU_BEAMFORMEE_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MU_BEAMFORMER_STAMIN 0
|
||||
#define WNI_CFG_HE_MU_BEAMFORMER_STAMAX 1
|
||||
#define WNI_CFG_HE_MU_BEAMFORMER_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BFEE_STS_LT80_STAMIN 0
|
||||
#define WNI_CFG_HE_BFEE_STS_LT80_STAMAX 0x7
|
||||
#define WNI_CFG_HE_BFEE_STS_LT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BFEE_STS_GT80_STAMIN 0
|
||||
#define WNI_CFG_HE_BFEE_STS_GT80_STAMAX 0x7
|
||||
#define WNI_CFG_HE_BFEE_STS_GT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_NUM_SOUND_LT80_STAMIN 0
|
||||
#define WNI_CFG_HE_NUM_SOUND_LT80_STAMAX 0x7
|
||||
#define WNI_CFG_HE_NUM_SOUND_LT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_NUM_SOUND_GT80_STAMIN 0
|
||||
#define WNI_CFG_HE_NUM_SOUND_GT80_STAMAX 0x7
|
||||
#define WNI_CFG_HE_NUM_SOUND_GT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_SU_FEED_TONE16_STAMIN 0
|
||||
#define WNI_CFG_HE_SU_FEED_TONE16_STAMAX 1
|
||||
#define WNI_CFG_HE_SU_FEED_TONE16_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MU_FEED_TONE16_STAMIN 0
|
||||
#define WNI_CFG_HE_MU_FEED_TONE16_STAMAX 1
|
||||
#define WNI_CFG_HE_MU_FEED_TONE16_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_CODEBOOK_SU_STAMIN 0
|
||||
#define WNI_CFG_HE_CODEBOOK_SU_STAMAX 1
|
||||
#define WNI_CFG_HE_CODEBOOK_SU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_CODEBOOK_MU_STAMIN 0
|
||||
#define WNI_CFG_HE_CODEBOOK_MU_STAMAX 1
|
||||
#define WNI_CFG_HE_CODEBOOK_MU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_BFRM_FEED_STAMIN 0
|
||||
#define WNI_CFG_HE_BFRM_FEED_STAMAX 0x7
|
||||
#define WNI_CFG_HE_BFRM_FEED_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_ER_SU_PPDU_STAMIN 0
|
||||
#define WNI_CFG_HE_ER_SU_PPDU_STAMAX 1
|
||||
#define WNI_CFG_HE_ER_SU_PPDU_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_DL_PART_BW_STAMIN 0
|
||||
#define WNI_CFG_HE_DL_PART_BW_STAMAX 1
|
||||
#define WNI_CFG_HE_DL_PART_BW_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_PPET_PRESENT_STAMIN 0
|
||||
#define WNI_CFG_HE_PPET_PRESENT_STAMAX 1
|
||||
#define WNI_CFG_HE_PPET_PRESENT_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_SRP_STAMIN 0
|
||||
#define WNI_CFG_HE_SRP_STAMAX 1
|
||||
#define WNI_CFG_HE_SRP_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_POWER_BOOST_STAMIN 0
|
||||
#define WNI_CFG_HE_POWER_BOOST_STAMAX 1
|
||||
#define WNI_CFG_HE_POWER_BOOST_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_4x_LTF_GI_STAMIN 0
|
||||
#define WNI_CFG_HE_4x_LTF_GI_STAMAX 1
|
||||
#define WNI_CFG_HE_4x_LTF_GI_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_MAX_NC_STAMIN 0
|
||||
#define WNI_CFG_HE_MAX_NC_STAMAX 0x7
|
||||
#define WNI_CFG_HE_MAX_NC_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_TX_STBC_GT80_STAMIN 0
|
||||
#define WNI_CFG_HE_TX_STBC_GT80_STAMAX 1
|
||||
#define WNI_CFG_HE_TX_STBC_GT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_STBC_GT80_STAMIN 0
|
||||
#define WNI_CFG_HE_RX_STBC_GT80_STAMAX 1
|
||||
#define WNI_CFG_HE_RX_STBC_GT80_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_ER_4x_LTF_GI_STAMIN 0
|
||||
#define WNI_CFG_HE_ER_4x_LTF_GI_STAMAX 1
|
||||
#define WNI_CFG_HE_ER_4x_LTF_GI_STADEF 0
|
||||
|
||||
#define WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_MIN 0
|
||||
#define WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_MAX 1
|
||||
#define WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_MIN 0
|
||||
#define WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_MAX 1
|
||||
#define WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_MIN 0
|
||||
#define WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_MAX 1
|
||||
#define WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_ER_1X_HE_LTF_GI_MIN 0
|
||||
#define WNI_CFG_HE_ER_1X_HE_LTF_GI_MAX 1
|
||||
#define WNI_CFG_HE_ER_1X_HE_LTF_GI_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MIN 0
|
||||
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MAX 1
|
||||
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_DCM_MAX_BW_MIN 0
|
||||
#define WNI_CFG_HE_DCM_MAX_BW_MAX 3
|
||||
#define WNI_CFG_HE_DCM_MAX_BW_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MIN 0
|
||||
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MAX 1
|
||||
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MIN 0
|
||||
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MAX 1
|
||||
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MIN 0
|
||||
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MAX 1
|
||||
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MIN 0
|
||||
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MAX 1
|
||||
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MIN 0
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MAX 1
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MIN 0
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MAX 1
|
||||
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_LT_80_MIN 0x0000
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_LT_80_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_LT_80_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_LT_80_MIN 0x0000
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_LT_80_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_LT_80_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_160_MIN 0x0000
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_160_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_160_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_160_MIN 0x0000
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_160_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_160_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_80_80_MIN 0x0000
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_80_80_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_RX_MCS_MAP_80_80_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_80_80_MIN 0x0000
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_80_80_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_TX_MCS_MAP_80_80_DEF 0xFFF0
|
||||
|
||||
#define WNI_CFG_HE_OPS_BSS_COLOR_MIN 0x01
|
||||
#define WNI_CFG_HE_OPS_BSS_COLOR_MAX 0x3F
|
||||
#define WNI_CFG_HE_OPS_BSS_COLOR_DEF 0x01
|
||||
|
||||
#define WNI_CFG_HE_OPS_DEFAULT_PE_MIN 0x0
|
||||
#define WNI_CFG_HE_OPS_DEFAULT_PE_MAX 0x7
|
||||
#define WNI_CFG_HE_OPS_DEFAULT_PE_DEF 0x0
|
||||
|
||||
#define WNI_CFG_HE_OPS_TWT_REQUIRED_MIN 0
|
||||
#define WNI_CFG_HE_OPS_TWT_REQUIRED_MAX 1
|
||||
#define WNI_CFG_HE_OPS_TWT_REQUIRED_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_RTS_THRESHOLD_MIN 0x000
|
||||
#define WNI_CFG_HE_OPS_RTS_THRESHOLD_MAX 0x3FF
|
||||
#define WNI_CFG_HE_OPS_RTS_THRESHOLD_DEF 0x000
|
||||
|
||||
#define WNI_CFG_HE_OPS_PARTIAL_BSS_COL_MIN 0
|
||||
#define WNI_CFG_HE_OPS_PARTIAL_BSS_COL_MAX 1
|
||||
#define WNI_CFG_HE_OPS_PARTIAL_BSS_COL_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_VHT_OPER_PRESENT_MIN 0
|
||||
#define WNI_CFG_HE_OPS_VHT_OPER_PRESENT_MAX 1
|
||||
#define WNI_CFG_HE_OPS_VHT_OPER_PRESENT_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_MBSSID_AP_MIN 0
|
||||
#define WNI_CFG_HE_OPS_MBSSID_AP_MAX 1
|
||||
#define WNI_CFG_HE_OPS_MBSSID_AP_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_TX_BSSID_IND_MIN 0
|
||||
#define WNI_CFG_HE_OPS_TX_BSSID_IND_MAX 1
|
||||
#define WNI_CFG_HE_OPS_TX_BSSID_IND_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_BSS_COL_DISABLED_MIN 0
|
||||
#define WNI_CFG_HE_OPS_BSS_COL_DISABLED_MAX 1
|
||||
#define WNI_CFG_HE_OPS_BSS_COL_DISABLED_DEF 0
|
||||
|
||||
#define WNI_CFG_HE_OPS_BASIC_MCS_NSS_MIN 0x0000
|
||||
#define WNI_CFG_HE_OPS_BASIC_MCS_NSS_MAX 0xFFFF
|
||||
#define WNI_CFG_HE_OPS_BASIC_MCS_NSS_DEF 0xFFFC
|
||||
|
||||
#define WNI_CFG_HE_STA_OBSSPD_STAMIN 0
|
||||
#define WNI_CFG_HE_STA_OBSSPD_STAMAX 0xffffffff
|
||||
#define WNI_CFG_HE_STA_OBSSPD_STADEF 0x15b8c2ae
|
||||
|
||||
#define WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STAMIN 1
|
||||
#define WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STAMAX 255
|
||||
#define WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STADEF 50
|
||||
|
|
|
|||
|
|
@ -63,101 +63,7 @@ const char *cfg_get_string(uint16_t cfg_id)
|
|||
CASE_RETURN_STRING(WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED);
|
||||
CASE_RETURN_STRING(WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP);
|
||||
CASE_RETURN_STRING(WNI_CFG_IBSS_ATIM_WIN_SIZE);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_CONTROL);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TWT_REQUESTOR);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TWT_RESPONDER);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_FRAGMENTATION);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MAX_FRAG_MSDU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MIN_FRAG_SIZE);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TRIG_PAD);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MTID_AGGR_RX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MTID_AGGR_TX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_LINK_ADAPTATION);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_ALL_ACK);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TRIGD_RSP_SCHEDULING);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BUFFER_STATUS_RPT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BCAST_TWT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BA_32BIT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MU_CASCADING);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MULTI_TID);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DL_MU_BA);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OMI);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OFDMA_RA);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MAX_AMPDU_LEN);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_AMSDU_FRAG);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_FLEX_TWT_SCHED);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_CTRL);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BSRP_AMPDU_AGGR);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_QTP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_A_BQR);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SR_RESPONDER);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_NDP_FEEDBACK_SUPP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_SUPP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SUB_CH_SEL_TX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_UL_2X996_RU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_CHAN_WIDTH);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_PREAM_PUNC);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_CLASS_OF_DEVICE);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_LDPC);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_LTF_PPDU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_LTF_NDP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_STBC_LT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_STBC_LT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DOPPLER);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_UL_MUMIMO);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DCM_TX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DCM_RX);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MU_PPDU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SU_BEAMFORMER);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SU_BEAMFORMEE);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MU_BEAMFORMER);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BFEE_STS_LT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BFEE_STS_GT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_NUM_SOUND_LT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_NUM_SOUND_GT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SU_FEED_TONE16);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MU_FEED_TONE16);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_CODEBOOK_SU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_CODEBOOK_MU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_BFRM_FEED);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_ER_SU_PPDU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DL_PART_BW);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_PPET_PRESENT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_SRP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_POWER_BOOST);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_4x_LTF_GI);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MAX_NC);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_STBC_GT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_STBC_GT80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_ER_4x_LTF_GI);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_DCM_MAX_BW);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_1024_QAM_LT_242_RU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_1024_QAM_LT_242_RU);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_MCS_MAP_LT_80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_MCS_MAP_LT_80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_MCS_MAP_160);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_MCS_MAP_160);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_RX_MCS_MAP_80_80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_TX_MCS_MAP_80_80);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_PPET_2G);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_PPET_5G);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_BSS_COLOR);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_DEFAULT_PE);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_TWT_REQUIRED);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_RTS_THRESHOLD);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_PARTIAL_BSS_COL);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_VHT_OPER_PRESENT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_MBSSID_AP);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_TX_BSSID_IND);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_BSS_COL_DISABLED);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_OPS_BASIC_MCS_NSS);
|
||||
CASE_RETURN_STRING(WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT);
|
||||
CASE_RETURN_STRING(WNI_CFG_HE_STA_OBSSPD);
|
||||
CASE_RETURN_STRING(WNI_CFG_OBSS_DETECTION_OFFLOAD);
|
||||
CASE_RETURN_STRING(WNI_CFG_OBSS_COLOR_COLLISION_OFFLOAD);
|
||||
CASE_RETURN_STRING(WNI_CFG_TWT_REQUESTOR);
|
||||
|
|
|
|||
|
|
@ -144,453 +144,11 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
|
|||
WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMIN,
|
||||
WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMAX,
|
||||
WNI_CFG_IBSS_ATIM_WIN_SIZE_STADEF},
|
||||
{WNI_CFG_HE_CONTROL,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_CONTROL_STAMIN, WNI_CFG_HE_CONTROL_STAMAX,
|
||||
WNI_CFG_HE_CONTROL_STADEF},
|
||||
{WNI_CFG_HE_TWT_REQUESTOR,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TWT_REQUESTOR_STAMIN, WNI_CFG_HE_TWT_REQUESTOR_STAMAX,
|
||||
WNI_CFG_HE_TWT_REQUESTOR_STADEF},
|
||||
{WNI_CFG_HE_TWT_RESPONDER,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TWT_RESPONDER_STAMIN, WNI_CFG_HE_TWT_RESPONDER_STAMAX,
|
||||
WNI_CFG_HE_TWT_RESPONDER_STADEF},
|
||||
{WNI_CFG_HE_FRAGMENTATION,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_FRAGMENTATION_STAMIN, WNI_CFG_HE_FRAGMENTATION_STAMAX,
|
||||
WNI_CFG_HE_FRAGMENTATION_STADEF},
|
||||
{WNI_CFG_HE_MAX_FRAG_MSDU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MAX_FRAG_MSDU_STAMIN, WNI_CFG_HE_MAX_FRAG_MSDU_STAMAX,
|
||||
WNI_CFG_HE_MAX_FRAG_MSDU_STADEF},
|
||||
{WNI_CFG_HE_MIN_FRAG_SIZE,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MIN_FRAG_SIZE_STAMIN, WNI_CFG_HE_MIN_FRAG_SIZE_STAMAX,
|
||||
WNI_CFG_HE_MIN_FRAG_SIZE_STADEF},
|
||||
{WNI_CFG_HE_TRIG_PAD,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TRIG_PAD_STAMIN, WNI_CFG_HE_TRIG_PAD_STAMAX,
|
||||
WNI_CFG_HE_TRIG_PAD_STADEF},
|
||||
{WNI_CFG_HE_MTID_AGGR_RX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MTID_AGGR_RX_STAMIN, WNI_CFG_HE_MTID_AGGR_RX_STAMAX,
|
||||
WNI_CFG_HE_MTID_AGGR_RX_STADEF},
|
||||
{WNI_CFG_HE_LINK_ADAPTATION,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_LINK_ADAPTATION_STAMIN, WNI_CFG_HE_LINK_ADAPTATION_STAMAX,
|
||||
WNI_CFG_HE_LINK_ADAPTATION_STADEF},
|
||||
{WNI_CFG_HE_ALL_ACK,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_ALL_ACK_STAMIN, WNI_CFG_HE_ALL_ACK_STAMAX,
|
||||
WNI_CFG_HE_ALL_ACK_STADEF},
|
||||
{WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMIN,
|
||||
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMAX,
|
||||
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STADEF},
|
||||
{WNI_CFG_HE_BUFFER_STATUS_RPT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN,
|
||||
WNI_CFG_HE_BUFFER_STATUS_RPT_STAMAX,
|
||||
WNI_CFG_HE_BUFFER_STATUS_RPT_STADEF},
|
||||
{WNI_CFG_HE_BCAST_TWT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BCAST_TWT_STAMIN, WNI_CFG_HE_BCAST_TWT_STAMAX,
|
||||
WNI_CFG_HE_BCAST_TWT_STADEF},
|
||||
{WNI_CFG_HE_BA_32BIT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BA_32BIT_STAMIN, WNI_CFG_HE_BA_32BIT_STAMAX,
|
||||
WNI_CFG_HE_BA_32BIT_STADEF},
|
||||
{WNI_CFG_HE_MU_CASCADING,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MU_CASCADING_STAMIN, WNI_CFG_HE_MU_CASCADING_STAMAX,
|
||||
WNI_CFG_HE_MU_CASCADING_STADEF},
|
||||
{WNI_CFG_HE_MULTI_TID,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MULTI_TID_STAMIN, WNI_CFG_HE_MULTI_TID_STAMAX,
|
||||
WNI_CFG_HE_MULTI_TID_STADEF},
|
||||
{WNI_CFG_HE_DL_MU_BA,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DL_MU_BA_STAMIN, WNI_CFG_HE_DL_MU_BA_STAMAX,
|
||||
WNI_CFG_HE_DL_MU_BA_STADEF},
|
||||
{WNI_CFG_HE_OMI,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OMI_STAMIN, WNI_CFG_HE_OMI_STAMAX,
|
||||
WNI_CFG_HE_OMI_STADEF},
|
||||
{WNI_CFG_HE_OFDMA_RA,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OFDMA_RA_STAMIN, WNI_CFG_HE_OFDMA_RA_STAMAX,
|
||||
WNI_CFG_HE_OFDMA_RA_STADEF},
|
||||
{WNI_CFG_HE_MAX_AMPDU_LEN,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MAX_AMPDU_LEN_STAMIN, WNI_CFG_HE_MAX_AMPDU_LEN_STAMAX,
|
||||
WNI_CFG_HE_MAX_AMPDU_LEN_STADEF},
|
||||
{WNI_CFG_HE_AMSDU_FRAG,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_AMSDU_FRAG_STAMIN, WNI_CFG_HE_AMSDU_FRAG_STAMAX,
|
||||
WNI_CFG_HE_AMSDU_FRAG_STADEF},
|
||||
{WNI_CFG_HE_FLEX_TWT_SCHED,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_FLEX_TWT_SCHED_STAMIN, WNI_CFG_HE_FLEX_TWT_SCHED_STAMAX,
|
||||
WNI_CFG_HE_FLEX_TWT_SCHED_STADEF},
|
||||
{WNI_CFG_HE_RX_CTRL,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_CTRL_STAMIN, WNI_CFG_HE_RX_CTRL_STAMAX,
|
||||
WNI_CFG_HE_RX_CTRL_STADEF},
|
||||
{WNI_CFG_HE_BSRP_AMPDU_AGGR,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMIN, WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMAX,
|
||||
WNI_CFG_HE_BSRP_AMPDU_AGGR_STADEF},
|
||||
{WNI_CFG_HE_QTP,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_QTP_STAMIN, WNI_CFG_HE_QTP_STAMAX,
|
||||
WNI_CFG_HE_QTP_STADEF},
|
||||
{WNI_CFG_HE_A_BQR,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_A_BQR_STAMIN, WNI_CFG_HE_A_BQR_STAMAX,
|
||||
WNI_CFG_HE_A_BQR_STADEF},
|
||||
{WNI_CFG_HE_SR_RESPONDER,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SR_RESPONDER_STAMIN, WNI_CFG_HE_SR_RESPONDER_STAMAX,
|
||||
WNI_CFG_HE_SR_RESPONDER_STADEF},
|
||||
{WNI_CFG_HE_NDP_FEEDBACK_SUPP,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_NDP_FEEDBACK_SUPP_STAMIN,
|
||||
WNI_CFG_HE_NDP_FEEDBACK_SUPP_STAMAX,
|
||||
WNI_CFG_HE_NDP_FEEDBACK_SUPP_STADEF},
|
||||
{WNI_CFG_HE_AMSDU_IN_AMPDU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_AMSDU_IN_AMPDU_MIN,
|
||||
WNI_CFG_HE_AMSDU_IN_AMPDU_MAX,
|
||||
WNI_CFG_HE_AMSDU_IN_AMPDU_DEF},
|
||||
{WNI_CFG_HE_MTID_AGGR_TX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MTID_AGGR_TX_MIN,
|
||||
WNI_CFG_HE_MTID_AGGR_TX_MAX,
|
||||
WNI_CFG_HE_MTID_AGGR_TX_DEF},
|
||||
{WNI_CFG_HE_SUB_CH_SEL_TX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SUB_CH_SEL_TX_MIN,
|
||||
WNI_CFG_HE_SUB_CH_SEL_TX_MAX,
|
||||
WNI_CFG_HE_SUB_CH_SEL_TX_DEF},
|
||||
{WNI_CFG_HE_UL_2X996_RU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_UL_2X996_RU_MIN,
|
||||
WNI_CFG_HE_UL_2X996_RU_MAX,
|
||||
WNI_CFG_HE_UL_2X996_RU_DEF},
|
||||
{WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MIN,
|
||||
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MAX,
|
||||
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_DEF},
|
||||
{WNI_CFG_HE_A_BQR,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_A_BQR_STAMIN, WNI_CFG_HE_A_BQR_STAMAX,
|
||||
WNI_CFG_HE_A_BQR_STADEF},
|
||||
{WNI_CFG_HE_CHAN_WIDTH,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_CHAN_WIDTH_STAMIN, WNI_CFG_HE_CHAN_WIDTH_STAMAX,
|
||||
WNI_CFG_HE_CHAN_WIDTH_STADEF},
|
||||
{WNI_CFG_HE_RX_PREAM_PUNC,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_PREAM_PUNC_STAMIN, WNI_CFG_HE_RX_PREAM_PUNC_STAMAX,
|
||||
WNI_CFG_HE_RX_PREAM_PUNC_STADEF},
|
||||
{WNI_CFG_HE_CLASS_OF_DEVICE,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_CLASS_OF_DEVICE_STAMIN, WNI_CFG_HE_CLASS_OF_DEVICE_STAMAX,
|
||||
WNI_CFG_HE_CLASS_OF_DEVICE_STADEF},
|
||||
{WNI_CFG_HE_LDPC,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_LDPC_STAMIN, WNI_CFG_HE_LDPC_STAMAX,
|
||||
WNI_CFG_HE_LDPC_STADEF},
|
||||
{WNI_CFG_HE_LTF_PPDU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_LTF_PPDU_STAMIN, WNI_CFG_HE_LTF_PPDU_STAMAX,
|
||||
WNI_CFG_HE_LTF_PPDU_STADEF},
|
||||
{WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_MIN,
|
||||
WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_MAX,
|
||||
WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS_DEF},
|
||||
{WNI_CFG_HE_LTF_NDP,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_LTF_NDP_STAMIN, WNI_CFG_HE_LTF_NDP_STAMAX,
|
||||
WNI_CFG_HE_LTF_NDP_STADEF},
|
||||
{WNI_CFG_HE_TX_STBC_LT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_STBC_LT80_STAMIN, WNI_CFG_HE_TX_STBC_LT80_STAMAX,
|
||||
WNI_CFG_HE_TX_STBC_LT80_STADEF},
|
||||
{WNI_CFG_HE_RX_STBC_LT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_STBC_LT80_STAMIN, WNI_CFG_HE_RX_STBC_LT80_STAMAX,
|
||||
WNI_CFG_HE_RX_STBC_LT80_STADEF},
|
||||
{WNI_CFG_HE_DOPPLER,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DOPPLER_STAMIN, WNI_CFG_HE_DOPPLER_STAMAX,
|
||||
WNI_CFG_HE_DOPPLER_STADEF},
|
||||
{WNI_CFG_HE_UL_MUMIMO,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_UL_MUMIMO_STAMIN, WNI_CFG_HE_UL_MUMIMO_STAMAX,
|
||||
WNI_CFG_HE_UL_MUMIMO_STADEF},
|
||||
{WNI_CFG_HE_DCM_TX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DCM_TX_STAMIN, WNI_CFG_HE_DCM_TX_STAMAX,
|
||||
WNI_CFG_HE_DCM_TX_STADEF},
|
||||
{WNI_CFG_HE_DCM_RX,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DCM_RX_STAMIN, WNI_CFG_HE_DCM_RX_STAMAX,
|
||||
WNI_CFG_HE_DCM_RX_STADEF},
|
||||
{WNI_CFG_HE_MU_PPDU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MU_PPDU_STAMIN, WNI_CFG_HE_MU_PPDU_STAMAX,
|
||||
WNI_CFG_HE_MU_PPDU_STADEF},
|
||||
{WNI_CFG_HE_SU_BEAMFORMER,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SU_BEAMFORMER_STAMIN, WNI_CFG_HE_SU_BEAMFORMER_STAMAX,
|
||||
WNI_CFG_HE_SU_BEAMFORMER_STADEF},
|
||||
{WNI_CFG_HE_SU_BEAMFORMEE,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SU_BEAMFORMEE_STAMIN, WNI_CFG_HE_SU_BEAMFORMEE_STAMAX,
|
||||
WNI_CFG_HE_SU_BEAMFORMEE_STADEF},
|
||||
{WNI_CFG_HE_MU_BEAMFORMER,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MU_BEAMFORMER_STAMIN, WNI_CFG_HE_MU_BEAMFORMER_STAMAX,
|
||||
WNI_CFG_HE_MU_BEAMFORMER_STADEF},
|
||||
{WNI_CFG_HE_BFEE_STS_LT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BFEE_STS_LT80_STAMIN, WNI_CFG_HE_BFEE_STS_LT80_STAMAX,
|
||||
WNI_CFG_HE_BFEE_STS_LT80_STADEF},
|
||||
{WNI_CFG_HE_BFEE_STS_GT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BFEE_STS_GT80_STAMIN, WNI_CFG_HE_BFEE_STS_GT80_STAMAX,
|
||||
WNI_CFG_HE_BFEE_STS_GT80_STADEF},
|
||||
{WNI_CFG_HE_NUM_SOUND_LT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_NUM_SOUND_LT80_STAMIN, WNI_CFG_HE_NUM_SOUND_LT80_STAMAX,
|
||||
WNI_CFG_HE_NUM_SOUND_LT80_STADEF},
|
||||
{WNI_CFG_HE_NUM_SOUND_GT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_NUM_SOUND_GT80_STAMIN, WNI_CFG_HE_NUM_SOUND_GT80_STAMAX,
|
||||
WNI_CFG_HE_NUM_SOUND_GT80_STADEF},
|
||||
{WNI_CFG_HE_SU_FEED_TONE16,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SU_FEED_TONE16_STAMIN, WNI_CFG_HE_SU_FEED_TONE16_STAMAX,
|
||||
WNI_CFG_HE_SU_FEED_TONE16_STADEF},
|
||||
{WNI_CFG_HE_MU_FEED_TONE16,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MU_FEED_TONE16_STAMIN, WNI_CFG_HE_MU_FEED_TONE16_STAMAX,
|
||||
WNI_CFG_HE_MU_FEED_TONE16_STADEF},
|
||||
{WNI_CFG_HE_CODEBOOK_SU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_CODEBOOK_SU_STAMIN, WNI_CFG_HE_CODEBOOK_SU_STAMAX,
|
||||
WNI_CFG_HE_CODEBOOK_SU_STADEF},
|
||||
{WNI_CFG_HE_CODEBOOK_MU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_CODEBOOK_MU_STAMIN, WNI_CFG_HE_CODEBOOK_MU_STAMAX,
|
||||
WNI_CFG_HE_CODEBOOK_MU_STADEF},
|
||||
{WNI_CFG_HE_BFRM_FEED,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_BFRM_FEED_STAMIN, WNI_CFG_HE_BFRM_FEED_STAMAX,
|
||||
WNI_CFG_HE_BFRM_FEED_STADEF},
|
||||
{WNI_CFG_HE_ER_SU_PPDU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_ER_SU_PPDU_STAMIN, WNI_CFG_HE_ER_SU_PPDU_STAMAX,
|
||||
WNI_CFG_HE_ER_SU_PPDU_STADEF},
|
||||
{WNI_CFG_HE_DL_PART_BW,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DL_PART_BW_STAMIN, WNI_CFG_HE_DL_PART_BW_STAMAX,
|
||||
WNI_CFG_HE_DL_PART_BW_STADEF},
|
||||
{WNI_CFG_HE_PPET_PRESENT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_PPET_PRESENT_STAMIN, WNI_CFG_HE_PPET_PRESENT_STAMAX,
|
||||
WNI_CFG_HE_PPET_PRESENT_STADEF},
|
||||
{WNI_CFG_HE_SRP,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_SRP_STAMIN, WNI_CFG_HE_SRP_STAMAX,
|
||||
WNI_CFG_HE_SRP_STADEF},
|
||||
{WNI_CFG_HE_POWER_BOOST,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_POWER_BOOST_STAMIN, WNI_CFG_HE_POWER_BOOST_STAMAX,
|
||||
WNI_CFG_HE_POWER_BOOST_STADEF},
|
||||
{WNI_CFG_HE_4x_LTF_GI,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_4x_LTF_GI_STAMIN, WNI_CFG_HE_4x_LTF_GI_STAMAX,
|
||||
WNI_CFG_HE_4x_LTF_GI_STADEF},
|
||||
{WNI_CFG_HE_MAX_NC,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MAX_NC_STAMIN, WNI_CFG_HE_MAX_NC_STAMAX,
|
||||
WNI_CFG_HE_MAX_NC_STADEF},
|
||||
{WNI_CFG_HE_TX_STBC_GT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_STBC_GT80_STAMIN, WNI_CFG_HE_TX_STBC_GT80_STAMAX,
|
||||
WNI_CFG_HE_TX_STBC_GT80_STADEF},
|
||||
{WNI_CFG_HE_RX_STBC_GT80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_STBC_GT80_STAMIN, WNI_CFG_HE_RX_STBC_GT80_STAMAX,
|
||||
WNI_CFG_HE_RX_STBC_GT80_STADEF},
|
||||
{WNI_CFG_HE_ER_4x_LTF_GI,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_ER_4x_LTF_GI_STAMIN, WNI_CFG_HE_ER_4x_LTF_GI_STAMAX,
|
||||
WNI_CFG_HE_ER_4x_LTF_GI_STADEF},
|
||||
|
||||
{WNI_CFG_HE_PPDU_20_IN_40MHZ_2G,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_MIN, WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_MAX,
|
||||
WNI_CFG_HE_PPDU_20_IN_40MHZ_2G_DEF},
|
||||
{WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_MIN,
|
||||
WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_MAX,
|
||||
WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ_DEF},
|
||||
{WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_MIN,
|
||||
WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_MAX,
|
||||
WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ_DEF},
|
||||
{WNI_CFG_HE_ER_1X_HE_LTF_GI,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_ER_1X_HE_LTF_GI_MIN, WNI_CFG_HE_ER_1X_HE_LTF_GI_MAX,
|
||||
WNI_CFG_HE_ER_1X_HE_LTF_GI_DEF},
|
||||
{WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MIN,
|
||||
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MAX,
|
||||
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_DEF},
|
||||
{WNI_CFG_HE_DCM_MAX_BW,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_DCM_MAX_BW_MIN,
|
||||
WNI_CFG_HE_DCM_MAX_BW_MAX,
|
||||
WNI_CFG_HE_DCM_MAX_BW_DEF},
|
||||
{WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MIN,
|
||||
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MAX,
|
||||
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_DEF},
|
||||
{WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MIN,
|
||||
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MAX,
|
||||
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_DEF},
|
||||
{WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MIN,
|
||||
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MAX,
|
||||
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_DEF},
|
||||
{WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MIN,
|
||||
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MAX,
|
||||
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_DEF},
|
||||
{WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MIN,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MAX,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_DEF},
|
||||
{WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MIN,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MAX,
|
||||
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_DEF},
|
||||
|
||||
{WNI_CFG_HE_RX_MCS_MAP_LT_80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_MCS_MAP_LT_80_MIN, WNI_CFG_HE_RX_MCS_MAP_LT_80_MAX,
|
||||
WNI_CFG_HE_RX_MCS_MAP_LT_80_DEF},
|
||||
|
||||
{WNI_CFG_HE_TX_MCS_MAP_LT_80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_MCS_MAP_LT_80_MIN, WNI_CFG_HE_TX_MCS_MAP_LT_80_MAX,
|
||||
WNI_CFG_HE_TX_MCS_MAP_LT_80_DEF},
|
||||
|
||||
{WNI_CFG_HE_RX_MCS_MAP_160,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_MCS_MAP_160_MIN, WNI_CFG_HE_RX_MCS_MAP_160_MAX,
|
||||
WNI_CFG_HE_RX_MCS_MAP_160_DEF},
|
||||
|
||||
{WNI_CFG_HE_TX_MCS_MAP_160,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_MCS_MAP_160_MIN, WNI_CFG_HE_TX_MCS_MAP_160_MAX,
|
||||
WNI_CFG_HE_TX_MCS_MAP_160_DEF},
|
||||
|
||||
{WNI_CFG_HE_RX_MCS_MAP_80_80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_RX_MCS_MAP_80_80_MIN, WNI_CFG_HE_RX_MCS_MAP_80_80_MAX,
|
||||
WNI_CFG_HE_RX_MCS_MAP_80_80_DEF},
|
||||
|
||||
{WNI_CFG_HE_TX_MCS_MAP_80_80,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_TX_MCS_MAP_80_80_MIN, WNI_CFG_HE_TX_MCS_MAP_80_80_MAX,
|
||||
WNI_CFG_HE_TX_MCS_MAP_80_80_DEF},
|
||||
|
||||
{WNI_CFG_HE_PPET_2G,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
|
||||
0, 0, 0},
|
||||
{WNI_CFG_HE_PPET_5G,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
|
||||
0, 0, 0},
|
||||
|
||||
{WNI_CFG_HE_OPS_BSS_COLOR,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_BSS_COLOR_MIN, WNI_CFG_HE_OPS_BSS_COLOR_MAX,
|
||||
WNI_CFG_HE_OPS_BSS_COLOR_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_DEFAULT_PE,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_DEFAULT_PE_MIN, WNI_CFG_HE_OPS_DEFAULT_PE_MAX,
|
||||
WNI_CFG_HE_OPS_DEFAULT_PE_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_TWT_REQUIRED,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_TWT_REQUIRED_MIN, WNI_CFG_HE_OPS_TWT_REQUIRED_MAX,
|
||||
WNI_CFG_HE_OPS_TWT_REQUIRED_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_RTS_THRESHOLD,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_RTS_THRESHOLD_MIN, WNI_CFG_HE_OPS_RTS_THRESHOLD_MAX,
|
||||
WNI_CFG_HE_OPS_RTS_THRESHOLD_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_PARTIAL_BSS_COL,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_PARTIAL_BSS_COL_MIN, WNI_CFG_HE_OPS_PARTIAL_BSS_COL_MAX,
|
||||
WNI_CFG_HE_OPS_PARTIAL_BSS_COL_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_VHT_OPER_PRESENT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_VHT_OPER_PRESENT_MIN,
|
||||
WNI_CFG_HE_OPS_VHT_OPER_PRESENT_MAX,
|
||||
WNI_CFG_HE_OPS_VHT_OPER_PRESENT_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_MBSSID_AP,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_MBSSID_AP_MIN, WNI_CFG_HE_OPS_MBSSID_AP_MAX,
|
||||
WNI_CFG_HE_OPS_MBSSID_AP_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_TX_BSSID_IND,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_TX_BSSID_IND_MIN, WNI_CFG_HE_OPS_TX_BSSID_IND_MAX,
|
||||
WNI_CFG_HE_OPS_TX_BSSID_IND_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_BSS_COL_DISABLED,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_BSS_COL_DISABLED_MIN,
|
||||
WNI_CFG_HE_OPS_BSS_COL_DISABLED_MAX,
|
||||
WNI_CFG_HE_OPS_BSS_COL_DISABLED_DEF},
|
||||
|
||||
{WNI_CFG_HE_OPS_BASIC_MCS_NSS,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_OPS_BASIC_MCS_NSS_MIN, WNI_CFG_HE_OPS_BASIC_MCS_NSS_MAX,
|
||||
WNI_CFG_HE_OPS_BASIC_MCS_NSS_DEF},
|
||||
|
||||
{WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STAMIN,
|
||||
WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STAMAX,
|
||||
WNI_CFG_PS_WOW_DATA_INACTIVITY_TIMEOUT_STADEF},
|
||||
{WNI_CFG_HE_STA_OBSSPD,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
WNI_CFG_HE_STA_OBSSPD_STAMIN, WNI_CFG_HE_STA_OBSSPD_STAMAX,
|
||||
WNI_CFG_HE_STA_OBSSPD_STADEF},
|
||||
{WNI_CFG_OBSS_DETECTION_OFFLOAD,
|
||||
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
|
||||
0, 1, 0},
|
||||
|
|
@ -657,16 +215,6 @@ cfgstatic_string cfg_static_string[CFG_MAX_STATIC_STRING] = {
|
|||
WNI_CFG_WPS_UUID_LEN,
|
||||
6,
|
||||
{0xa, 0xb, 0xc, 0xd, 0xe, 0xf} },
|
||||
{WNI_CFG_HE_PPET_2G,
|
||||
WNI_CFG_HE_PPET_LEN,
|
||||
WNI_CFG_HE_PPET_LEN,
|
||||
{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
|
||||
{WNI_CFG_HE_PPET_5G,
|
||||
WNI_CFG_HE_PPET_LEN,
|
||||
WNI_CFG_HE_PPET_LEN,
|
||||
{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
|
||||
};
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -13106,23 +13106,6 @@ int sme_update_he_mcs(mac_handle_t mac_handle, uint8_t session_id,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sme_update_he_cap(mac_handle_t mac_handle, uint8_t session_id,
|
||||
uint16_t he_cap, int value)
|
||||
{
|
||||
tpAniSirGlobal mac_ctx = PMAC_STRUCT(mac_handle);
|
||||
struct csr_roam_session *session;
|
||||
|
||||
session = CSR_GET_SESSION(mac_ctx, session_id);
|
||||
if (!session) {
|
||||
sme_err("No session for id %d", session_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
sme_cfg_set_int(mac_handle, he_cap, value);
|
||||
csr_update_session_he_cap(mac_ctx, session);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sme_set_usr_cfg_mu_edca(mac_handle_t mac_handle, bool val)
|
||||
{
|
||||
tpAniSirGlobal mac_ctx = PMAC_STRUCT(mac_handle);
|
||||
|
|
@ -13214,8 +13197,24 @@ int sme_update_he_trigger_frm_mac_pad(mac_handle_t mac_handle,
|
|||
int sme_update_he_om_ctrl_supp(mac_handle_t mac_handle, uint8_t session_id,
|
||||
uint8_t cfg_val)
|
||||
{
|
||||
return sme_update_he_cap(mac_handle, session_id, WNI_CFG_HE_OMI,
|
||||
cfg_val);
|
||||
|
||||
tpAniSirGlobal mac_ctx = PMAC_STRUCT(mac_handle);
|
||||
struct csr_roam_session *session;
|
||||
|
||||
session = CSR_GET_SESSION(mac_ctx, session_id);
|
||||
|
||||
if (!session) {
|
||||
sme_err("No session for id %d", session_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (cfg_in_range(CFG_HE_OMI, cfg_val))
|
||||
mac_ctx->mlme_cfg->he_caps.dot11_he_cap.omi_a_ctrl =
|
||||
cfg_val;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
csr_update_session_he_cap(mac_ctx, session);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sme_send_he_om_ctrl_bw_update(mac_handle_t mac_handle, uint8_t session_id,
|
||||
|
|
|
|||
Loading…
Reference in a new issue