From 3b2249f3cc878713e3f601272bdaa44d35287593 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 12:52:29 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add DPC property for SM8150 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I9cc9f97116b5aa9cdf9f3b6e250b30a170db910c --- qcom/sm8150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 012119a96c3a..5bde3d947bf8 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -54,6 +54,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { @@ -75,6 +76,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_1: l2-cache { @@ -91,6 +93,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_2: l2-cache { @@ -107,6 +110,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_3: l2-cache { @@ -123,6 +127,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_4: l2-cache { @@ -139,6 +144,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_5: l2-cache { @@ -155,6 +161,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_6: l2-cache { @@ -171,6 +178,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; L2_7: l2-cache { From 341d78c97813219a1482bf38536f80a10740f3d3 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 13:17:54 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add DPC property for SA8195 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I56f0f7bd6a623dcfd2cbf2dca370681011aa876b --- qcom/sdmshrike.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index b4ba25a47ad4..203300f196d1 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -50,6 +50,7 @@ reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -74,6 +75,7 @@ reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -92,6 +94,7 @@ reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -110,6 +113,7 @@ reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -128,6 +132,7 @@ reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -146,6 +151,7 @@ reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -164,6 +170,7 @@ reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -182,6 +189,7 @@ reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 1 4>; From 704b584258466bfb46b29cef710a8f0cc3f82795 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 13:20:26 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add DPC property for SM6150 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: Ieed91b03a482e3e23af6b63656bb52245f149379 --- qcom/sm6150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index d13d12a975e5..fea0881c7a01 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -49,6 +49,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -74,6 +75,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -94,6 +96,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -113,6 +116,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -132,6 +136,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -151,6 +156,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -170,6 +176,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1 2>; @@ -189,6 +196,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1 2>;