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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add USB dtsi nodes for monaco
Add USB dtsi nodes for monaco for USB functionality to work. Change-Id: I35aa0c455d410e8e24d0f811c94f5e47aa1dcec4
This commit is contained in:
Vijayavardhan Vennapusa
parent
1ec72c6a0d
commit
2fe1bca7ea
3 changed files with 166 additions and 0 deletions
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@ -11,6 +11,35 @@
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status = "disabled";
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};
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usb_emu_phy_0: usb_emu_phy@0x04f20000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x04e0e000 0x9500>;
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qcom,emu-init-seq = <0xfff0 0x4
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0xfff3 0x4
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0xfff0 0x4
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0x100000 0x20
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0x0 0x20
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0x1e0 0x20
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0x100000 0x3c
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0x0 0x3c
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0x4 0x3c
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0x0 0x4
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0x9 0x14>;
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};
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};
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&usb0 {
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dpdm-supply = <&usb_nop_phy>;
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dwc3@4e00000 {
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usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
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maximum-speed = "high-speed";
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dr_mode = "peripheral";
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};
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};
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&usb2_phy0 {
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status = "disabled";
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};
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&sdhc_1 {
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136
qcom/monaco-usb.dtsi
Normal file
136
qcom/monaco-usb.dtsi
Normal file
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@ -0,0 +1,136 @@
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#include <dt-bindings/clock/qcom,gcc-monaco.h>
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#include <dt-bindings/interconnect/qcom,monaco.h>
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&soc {
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/* Primary USB port related controller */
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usb0: hsusb@4e00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x4e00000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x120 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "hs_phy_irq";
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clocks = <&gcc GCC_USB20_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB2_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB20_SLEEP_CLK>,
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<&gcc GCC_USB20_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&gcc GCC_USB20_PRIM_BCR>;
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reset-names = "core_reset";
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USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
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qcom,usb-charger;
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qcom,core-clk-rate = <60000000>;
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qcom,default-bus-vote = <2>; /* use svs bus voting */
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
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qcom,interconnect-values-svs = /* SVS Votes */
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<30000 70000>,
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<0 2400>,
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<0 40000>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <10488>;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xcd00>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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tx-fifo-resize;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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qcom,usbbam@0x04f04000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0x04f04000 0x17000>;
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interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
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qcom,usb-bam-fifo-baseaddr = <0xc121000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "hsusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x08064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@1613000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x1613000 0x120>,
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<0x01612000 0x4>;
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reg-names = "hsusb_phy_base",
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"eud_enable_reg";
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vdd-supply = <&L12A>;
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vdda18-supply = <&L14A>;
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vdda33-supply = <&L25A>;
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qcom,vdd-voltage-level = <0 904000 904000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq =
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<0x63 0x6c /* override_x0 */
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0xC8 0x70 /* override_x1 */
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0x17 0x74>; /* override x2 */
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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@ -1235,6 +1235,7 @@
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#include "monaco-qupv3.dtsi"
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#include "monaco-pm.dtsi"
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#include "monaco-audio.dtsi"
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#include "monaco-usb.dtsi"
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&qupv3_se6_2uart {
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status = "ok"
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