From 300aa4043c8a321cf1fe5cdb9c5c5e8d97f24802 Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Fri, 5 Feb 2021 11:19:53 -0800
Subject: [PATCH] ARM: dts: msm: add pci DT nodes for PCIe switch for sdxlemur

If there is a switch connected to PCIe root complex, the
devicetree hierarchy needs to correctly reflect the physical
connection. Add pci DT nodes for each switch device such as
switch upstream and downstream ports.

Change-Id: Ic813867df68254b51ebdc365545058925fcff35d
---
 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
index d628e771162b..6511383a1fc6 100644
--- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
+++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
@@ -3,3 +3,28 @@
 &soc {
 
 };
+
+&pcie0_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	/* BDF 1.0.0 */
+	pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
+		reg = <0 0 0 0 0>;
+
+		/* BDF 2.1.0 */
+		pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
+			reg = <0x800 0x0 0x0 0x0 0x0>;
+		};
+
+		/* BDF 2.2.0 */
+		pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
+			reg = <0x1000 0x0 0x0 0x0 0x0>;
+		};
+
+		/* BDF 2.3.0 */
+		pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 {
+			reg = <0x1800 0x0 0x0 0x0 0x0>;
+		};
+	};
+};