From 7c1fabee8b2c3b7109365e324ee3c500832e6df4 Mon Sep 17 00:00:00 2001
From: priyankar <prigup@qti.qualcomm.com>
Date: Mon, 14 Dec 2020 13:48:44 +0530
Subject: [PATCH] ARM: dts: msm: Add support for Moselle (WCN6750)

This patch contains changes for supporting
moselle soc.

Change-Id: Ibf07457c242973e0f54bcbc466cd4ee79d744578
---
 bindings/bluetooth/btpower.txt |  1 +
 qcom/yupik-pinctrl.dtsi        | 14 ++++++++++++++
 qcom/yupik.dtsi                | 34 ++++++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+)

diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt
index 391361eef201..39c44d4ea365 100644
--- a/bindings/bluetooth/btpower.txt
+++ b/bindings/bluetooth/btpower.txt
@@ -10,6 +10,7 @@ Required properties:
 		qcom,wcn3990
 		qcom,qca6390
 		qcom,qca6490
+		qcom,wcn6750
 	- qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset
 	- qcom,wl-reset-gpio: GPIO pin for WL_EN toggle
 
diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi
index b887f34b852a..be642b025745 100644
--- a/qcom/yupik-pinctrl.dtsi
+++ b/qcom/yupik-pinctrl.dtsi
@@ -1103,6 +1103,20 @@
 			};
 		};
 
+		bt_en_sleep: bt_en_sleep {
+			mux {
+				pins = "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85";
+				drive-strength = <2>;
+				output-low;
+				bias-pull-down;
+			};
+		};
+
 		qupv3_se14_2uart_pins: qupv3_se14_2uart_pins {
 			qupv3_se14_default_txrx: qupv3_se14_default_txrx {
 				mux {
diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index 61e804c9b521..774145e4524a 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -1159,6 +1159,35 @@
 		};
 	};
 
+	bluetooth: bt_wcn6750 {
+		compatible = "qcom,wcn6750";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_en_sleep>;
+		qcom,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */
+		qcom,bt-sw-ctrl-gpio = <&tlmm 86 0>; /* SW_CTRL */
+		qcom,wl-reset-gpio = <&tlmm 84 0>; /* WL_EN */
+
+		qcom,bt-vdd-io-supply = <&L19B>;  /* IO */
+		qcom,bt-vdd-aon-supply = <&S7B>;
+		qcom,bt-vdd-dig-supply = <&S7B>;
+		qcom,bt-vdd-rfacmn-supply = <&S7B>;
+		qcom,bt-vdd-rfa-0p8-supply = <&S7B>;
+		qcom,bt-vdd-rfa1-supply = <&S1B>; /*RFA 1p7*/
+		qcom,bt-vdd-rfa2-supply = <&S8B>; /*RFA 1p2*/
+		qcom,bt-vdd-ipa-2p2-supply = <&S1C>; /*IPA 2p2*/
+		qcom,bt-vdd-asd-supply = <&L11C>;
+
+		qcom,bt-vdd-io-config = <1800000 1800000 0 1>;
+		qcom,bt-vdd-aon-config = <824000 952000 0 1>;
+		qcom,bt-vdd-dig-config = <824000 952000 0 1>;
+		qcom,bt-vdd-rfacmn-config  = <824000 952000 0 1>;
+		qcom,bt-vdd-rfa-0p8-config  = <824000 952000 0 1>;
+		qcom,bt-vdd-rfa1-config = <1872000 1872000 0 1>;
+		qcom,bt-vdd-rfa2-config = <1256000 1352000 0 1>;
+		qcom,bt-vdd-ipa-2p2-config = <2200000 2210000 0 1>;
+		qcom,bt-vdd-asd-config = <2800000 3544000 0 1>;
+	};
+
 	ufshc_mem: ufshc@1d84000 {
 		compatible = "qcom,ufshc";
 		reg = <0x1d84000 0x3000>,
@@ -3832,6 +3861,11 @@
 #include "yupik-gpu.dtsi"
 #include "yupik-thermal.dtsi"
 
+/* HS UART */
+&qupv3_se7_4uart {
+	status = "ok";
+};
+
 &qupv3_se1_i2c {
 	status = "ok";
 	nq@64 {