From 7404db6771fb8a106cf3888a7977582449640a00 Mon Sep 17 00:00:00 2001
From: Pranav Patel <pranavp@qti.qualcomm.com>
Date: Fri, 18 Dec 2020 19:19:48 +0530
Subject: [PATCH] ARM: dts: msm: Add apb_pclk to GMU clock list for Lahaina

apb_pclk is required to access QDSS registers. GMU need to add vote
before access can be made.

Change-Id: I36f27809824f1b3d09dd55f19080e9f40edb692a
---
 qcom/lahaina-gpu.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi
index 1fc038a7f72a..ceb8de50a6ba 100644
--- a/qcom/lahaina-gpu.dtsi
+++ b/qcom/lahaina-gpu.dtsi
@@ -270,10 +270,11 @@
 			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
 			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
 			<&clock_gpucc GPU_CC_AHB_CLK>,
-			<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>;
+			<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
+			<&clock_aop QDSS_CLK>;
 
 		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
-			"memnoc_clk", "ahb_clk", "hub_clk";
+			"memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk";
 
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";