From fc340212acca8eb02ccdb123544fba8abf10a140 Mon Sep 17 00:00:00 2001
From: Sarthak Garg <sartgarg@qti.qualcomm.com>
Date: Fri, 8 Jan 2021 10:42:18 +0530
Subject: [PATCH] ARM: dts: msm: Add iommu and h/w reset support for yupik

Add iommu devicetree property for eMMC and SD card.
Also add h/w reset support for eMMC.

Change-Id: I22e5a8d23f3edfc2c251cced8aced6f727a0b299
---
 qcom/yupik.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index 956f177295b5..8ff4ae741552 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -1910,6 +1910,10 @@
 		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",
 			    "cqhci_ice_hwkm";
 
+		iommus = <&apps_smmu 0xc0 0x0>;
+		dma-coherent;
+		qcom,iommu-dma = "bypass";
+
 		interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hc_irq", "pwr_irq";
@@ -1929,6 +1933,8 @@
 		mmc-hs400-1_8v;
 		mmc-hs400-enhanced-strobe;
 
+		cap-mmc-hw-reset;
+
 		bus-width = <8>;
 		non-removable;
 		supports-cqe;
@@ -1936,6 +1942,10 @@
 		qcom,devfreq,freq-table = <50000000 200000000>;
 		qcom,scaling-lower-bus-speed-mode = "DDR52";
 
+		/* Add dt entry for gcc hw reset */
+		resets = <&gcc GCC_SDCC1_BCR>;
+		reset-names = "core_reset";
+
 		status = "disabled";
 
 		qos0 {
@@ -1954,6 +1964,10 @@
 		reg = <0x08804000 0x1000>;
 		reg-names = "hc_mem";
 
+		iommus = <&apps_smmu 0x100 0x0>;
+		dma-coherent;
+		qcom,iommu-dma = "bypass";
+
 		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hc_irq", "pwr_irq";