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ARM: dts: msm: create sde-common device tree on lahaina target

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Separate and maintain common SDE bindings in sde-common dt file(s). It
avoids unwanted duplications between VM variants of the SDE files. It
also helps developers with single-dt update for bindings applicable to
all the VM's for Lahaina target.

For easy maintenance, the recommendation would be to add any VM specific
bindings in VM DT files instead of adding them to common DT and use
"delete-property" operator to update the VM DT file.

Change-Id: I8eaae7355b1c44138d6e032e3cf26f44069bc843
This commit is contained in:
Jeykumar Sankaran 2020-06-19 23:59:29 -07:00
commit 3104096ce8
4 changed files with 1291 additions and 1183 deletions
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370
display/lahaina-sde-common.dtsi Normal file
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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
mdss_mdp: qcom,mdss_mdp@ae00000 {
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x84000>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x800>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys";
clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>;
clock-max-rate = <0 0 0 0 460000000 19200000 460000000
460000000>;
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x494>;
qcom,sde-ctl-off = <0x16000 0x17000 0x18000
0x19000 0x1a000 0x1b000>;
qcom,sde-ctl-size = <0x1e8>;
qcom,sde-ctl-display-pref = "primary", "none", "none",
"none", "none", "none";
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
0x48000 0x49000 0x4a000>;
qcom,sde-mixer-size = <0x320>;
qcom,sde-mixer-display-pref = "primary", "primary", "none",
"none", "none", "none";
qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
"cwb", "cwb", "cwb";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x80>;
qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
qcom,sde-dspp-size = <0x1800>;
qcom,sde-dspp-rc-version = <0x00010000>;
qcom,sde-dspp-rc-off = <0x15800 0x14c00>;
qcom,sde-dspp-rc-size = <0x100>;
qcom,sde-dspp-rc-mem-size = <2720>;
qcom,sde-dest-scaler-top-off = <0x00061000>;
qcom,sde-dest-scaler-top-size = <0x1c>;
qcom,sde-dest-scaler-off = <0x800 0x1000>;
qcom,sde-dest-scaler-size = <0x800>;
qcom,sde-wb-off = <0x66000>;
qcom,sde-wb-size = <0x2c8>;
qcom,sde-wb-xin-id = <6>;
qcom,sde-wb-id = <2>;
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
qcom,sde-wb-clk-status = <0x3bc 20>;
qcom,sde-intf-off = <0x35000 0x36000
0x37000 0x38000>;
qcom,sde-intf-size = <0x2c0>;
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
qcom,sde-pp-off = <0x6a000 0x6b000
0x6c000 0x6d000 0x6e000 0x6f000>;
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,sde-pp-size = <0xd4>;
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>;
qcom,sde-merge-3d-size = <0x10>;
qcom,sde-cdm-off = <0x7a200>;
qcom,sde-cdm-size = <0x224>;
qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>;
qcom,sde-dsc-size = <0x10>;
qcom,sde-dsc-pair-mask = <2 1 4 3>;
qcom,sde-dsc-hw-rev = "dsc_1_2";
qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>;
qcom,sde-dsc-enc-size = <0x100>;
qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>;
qcom,sde-dsc-ctl-size = <0x10>;
qcom,sde-dsc-native422-supp = <0 0 1 1>;
qcom,sde-dsc-linewidth = <2048>;
qcom,sde-dither-off = <0xe0 0xe0 0xe0
0xe0 0xe0 0xe0>;
qcom,sde-dither-version = <0x00020000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-vdc-off = <0x7C000>;
qcom,sde-vdc-size = <0x10>;
qcom,sde-vdc-hw-rev = "vdc_1_2";
qcom,sde-vdc-enc = <0x200>;
qcom,sde-vdc-enc-size = <0x1C8>;
qcom,sde-vdc-ctl = <0xf00>;
qcom,sde-vdc-ctl-size = <0x10>;
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
"dma", "dma", "dma", "dma";
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
0x25000 0x27000 0x29000 0x2b000>;
qcom,sde-sspp-src-size = <0x1f8>;
qcom,sde-sspp-xin-id = <0 4 8 12
1 5 9 13>;
qcom,sde-sspp-excl-rect = <1 1 1 1
1 1 1 1>;
qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
0xb0 0xc8 0xe0 0xf8 0x110>;
qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000
3900000 3900000
3900000 3900000
3900000 3900000>;
qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000
5200000 5200000
5200000 5200000
5200000 5200000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl =
<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
qcom,sde-sspp-clk-status =
<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,
<0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;
qcom,sde-sspp-csc-off = <0x1a00>;
qcom,sde-csc-type = "csc-10bit";
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
qcom,sde-qseed-scalar-version = <0x3000>;
qcom,sde-sspp-qseed-off = <0xa00>;
qcom,sde-mixer-linewidth = <2560>;
qcom,sde-sspp-linewidth = <4096>;
qcom,sde-wb-linewidth = <4096>;
qcom,sde-wb-linewidth-linear = <5120>;
qcom,sde-mixer-blendstages = <0xb>;
qcom,sde-highest-bank-bit = <0x3>;
qcom,sde-ubwc-version = <0x400>;
qcom,sde-ubwc-swizzle = <0x6>;
qcom,sde-ubwc-bw-calc-version = <0x1>;
qcom,sde-ubwc-static = <0x1>;
qcom,sde-macrotile-mode = <0x1>;
qcom,sde-smart-panel-align-mode = <0xc>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
qcom,sde-pipe-order-version = <0x1>;
qcom,sde-has-dim-layer;
qcom,sde-has-dest-scaler;
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
qcom,sde-max-bw-low-kbps = <11800000>;
qcom,sde-max-bw-high-kbps = <15500000>;
qcom,sde-min-core-ib-kbps = <2500000>;
qcom,sde-min-llcc-ib-kbps = <0>;
qcom,sde-min-dram-ib-kbps = <800000>;
qcom,sde-dram-channels = <2>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-dspp-spr-off = <0x15400 0x14400>;
qcom,sde-dspp-spr-size = <0x200>;
qcom,sde-dspp-spr-version = <0x00010000>;
qcom,sde-dspp-demura-off = <0x15600 0x14800>;
qcom,sde-dspp-demura-size = <0x200>;
qcom,sde-dspp-demura-version = <0x00010000>;
qcom,sde-uidle-off = <0x80000>;
qcom,sde-uidle-size = <0x70>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x1040>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>;
qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;
qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>,
<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;
qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;
qcom,sde-qos-refresh-rates = <60 120>;
qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x400>;
qcom,sde-reg-dma-id = <0 1>;
qcom,sde-reg-dma-version = <0x00020000>;
qcom,sde-reg-dma-trigger-off = <0x119c>;
qcom,sde-reg-dma-xin-id = <7>;
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
qcom,sde-secure-sid-mask = <0x4000821>;
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 74000>,
<0 148000>,
<0 265000>;
qcom,sde-sspp-vig-blocks {
qcom,sde-vig-csc-off = <0x1a00>;
qcom,sde-vig-qseed-off = <0xa00>;
qcom,sde-vig-qseed-size = <0xa0>;
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
qcom,sde-vig-igc = <0x1d00 0x00060000>;
qcom,sde-vig-inverse-pma;
};
qcom,sde-sspp-dma-blocks {
dgm@0 {
qcom,sde-dma-igc = <0x400 0x00050000>;
qcom,sde-dma-gc = <0x600 0x00050000>;
qcom,sde-dma-inverse-pma;
qcom,sde-dma-csc-off = <0x200>;
};
dgm@1 {
qcom,sde-dma-igc = <0x1400 0x00050000>;
qcom,sde-dma-gc = <0x600 0x00050000>;
qcom,sde-dma-inverse-pma;
qcom,sde-dma-csc-off = <0x1200>;
};
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x1260 0x00040000>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
compatible = "qcom,dsi-ctrl-hw-v2.5";
label = "dsi-ctrl-0";
cell-index = <0>;
frame-threshold-time-us = <800>;
reg = <0xae94000 0x400>,
<0xaf08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
};
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
compatible = "qcom,dsi-ctrl-hw-v2.5";
label = "dsi-ctrl-1";
cell-index = <1>;
frame-threshold-time-us = <800>;
reg = <0xae96000 0x400>,
<0xaf08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <5 0>;
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
compatible = "qcom,dsi-phy-v4.2";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xae94400 0x800>,
<0xae94900 0x27c>,
<0xaf03000 0x8>,
<0xae94200 0x100>;
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
pll-label = "dsi_pll_5nm";
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <37550>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 {
compatible = "qcom,dsi-phy-v4.2";
label = "dsi-phy-1";
cell-index = <1>;
#clock-cells = <1>;
reg = <0xae96400 0x800>,
<0xae96900 0x27c>,
<0xaf03000 0x8>,
<0xae96200 0x100>;
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
pll-label = "dsi_pll_5nm";
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <37550>;
qcom,supply-disable-load = <0>;
};
};
};
};

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display/lahaina-sde-display-common.dtsi Normal file
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#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
#include "dsi-panel-sharp-1080p-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "dsi-panel-sim-cmd.dtsi"
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-sim-dsc375-cmd.dtsi"
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include "dsi-panel-sim-vdc-vid.dtsi"
#include "dsi-panel-sim-vdc-cmd.dtsi"
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <60700>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <10000>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <0>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
qcom,panel-supply-entry@3 {
reg = <3>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <182000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "avdd";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
qcom,mdp = <&mdss_mdp>;
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
};
sde_dsi1: qcom,dsi-display-secondary {
compatible = "qcom,dsi-display";
label = "secondary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
qcom,mdp = <&mdss_mdp>;
};
};
/* PHY TIMINGS REVISION YC with reduced margins*/
&dsi_sw43404_amoled_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
};
};
};
&dsi_sw43404_amoled_video {
qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
06 06 02 04 00 14 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
04 03 02 04 00 0e 09];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
06 06 02 04 00 14 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_cmd_cphy {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04
19 03 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_video_cphy {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04
19 03 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_4k_dsc_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_4k_dsc_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06
06 07 02 04 00 15 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_1080_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08
08 08 02 04 00 1a 0c];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
qcom,mdss-dsi-panel-clockrate = <900000000>;
};
};
};
&dsi_sharp_qsync_wqhd_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* WQHD 60FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03
03 02 02 04 00 0b 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* WQHD 60FPS VID */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* FHD 60FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
02 01 02 04 00 09 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@3 { /* WQHD 90FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04
04 03 02 04 00 0e 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@4 { /* WQHD 120FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@5 { /* WQHD 120FPS VID */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@6 { /* FHD 120FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03
03 02 02 04 00 0c 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@7 { /* FHD 90FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03
02 02 02 04 00 0a 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_qsync_wqhd_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_qhd_plus_dsc_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
06 06 02 04 00 13 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07
07 07 02 04 00 17 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_nt35597_truly_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
/* DPHY regular margins */
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06
06 07 02 04 00 17 16 ];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_nt35597_truly_video {
qcom,dsi-supported-dfps-list = <60 57 55>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-min-refresh-rate = <53>;
qcom,mdss-dsi-max-refresh-rate = <60>;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
07 08 02 04 00 18 0c];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt35695b_truly_fhd_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
/* DPHY regular margins */
qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07
07 07 02 04 00 18 16];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,poms-align-panel-vsync;
qcom,mdss-dsi-display-timings {
timing@0 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06
06 04 02 04 00 12 0a];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
timing@1 { /* WQHD 60FPS vid mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06
06 04 02 04 00 12 0a];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
timing@2 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06
06 04 02 04 00 12 0b];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
timing@3 { /* FHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08
08 05 02 04 00 17 0c];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
timing@4 { /* HD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a
0a 07 02 04 00 1d 0e];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
};
};
&dsi_sim_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <1 0 1>,
<2 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_vdc_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_vdc_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_dsc_375_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 1080p */
qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05
05 03 02 04 00 0e 09];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 { /* qhd */
qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02
02 01 02 04 00 08 07];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_dsc_10b_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* QHD 60fps */
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
07 05 02 04 00 18 17];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 1080 60fps */
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
08 05 02 04 00 19 18];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <0>;
};
timing@2 { /* QHD 90fps */
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
07 05 02 04 00 18 17];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 5K 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11
11 0c 02 04 00 30 15];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* FHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04
04 02 02 04 00 0c 08];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03
03 01 02 04 00 0a 08];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
timing@3 { /* 4K 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05
05 03 02 04 00 10 0a];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07
07 07 04 02 00 14 0b];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_dsc_375_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 4k 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 4k 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05
05 03 02 04 00 10 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* 4k 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08
08 05 02 04 00 16 0c];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@3 { /* 4k 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a
0a 07 02 04 00 1d 0e];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@4 { /* 1080 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01
01 01 02 04 00 05 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@5 { /* 1080 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02
02 01 02 04 00 08 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@6 { /* 1080 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@7 { /* 1080 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04
04 02 02 04 00 0c 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@8 { /* qhd 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02
01 00 02 04 00 06 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@9 { /* qhd 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@10 { /* qhd 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04
04 02 02 04 00 0c 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@11 { /* qhd 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05
05 03 02 04 00 0f 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@12 { /* 5k */
qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07
07 04 02 04 00 14 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@13 { /* 720p 30 FPS */
qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01
01 00 02 04 00 04 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@14 { /* 720p 60 FPS */
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@15 { /* 720p 90 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02
02 01 02 04 00 07 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@16 { /* 720 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03
03 01 02 04 00 08 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@17 { /* 1080 144FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
06 06 02 04 00 13 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_sec_hd_cmd {
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
08 08 05 02 04 00 19 17];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};

787
display/lahaina-sde-display.dtsi
View file

@ -1,32 +1,4 @@
#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
#include "dsi-panel-sharp-1080p-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "dsi-panel-sim-cmd.dtsi"
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-sim-dsc375-cmd.dtsi"
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include "dsi-panel-sim-vdc-vid.dtsi"
#include "dsi-panel-sim-vdc-cmd.dtsi"
#include "lahaina-sde-display-common.dtsi"
&tlmm {
display_panel_avdd_default: display_panel_avdd_default {
@ -45,74 +17,6 @@
};
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <60700>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <10000>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <0>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
qcom,panel-supply-entry@3 {
reg = <3>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <182000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "avdd";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
};
display_panel_avdd: display_gpio_regulator@1 {
compatible = "regulator-fixed";
regulator-name = "display_panel_avdd";
@ -128,89 +32,6 @@
pinctrl-0 = <&display_panel_avdd_default>;
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1",
"src_byte_clk1", "src_pixel_clk1",
"shadow_byte_clk1", "shadow_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 82 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&L12C>;
vdd-supply = <&L13C>;
avdd-supply = <&display_panel_avdd>;
lab-supply = <&ab_vreg>;
ibb-supply = <&ibb_vreg>;
qcom,mdp = <&mdss_mdp>;
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
};
sde_dsi1: qcom,dsi-display-secondary {
compatible = "qcom,dsi-display";
label = "secondary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
qcom,platform-te-gpio = <&tlmm 83 0>;
qcom,panel-te-source = <1>;
vddio-supply = <&L12C>;
vdd-supply = <&L13C>;
avdd-supply = <&display_panel_avdd>;
qcom,mdp = <&mdss_mdp>;
};
sde_wb: qcom,wb-display@0 {
compatible = "qcom,wb-display";
cell-index = <0>;
@ -218,30 +39,88 @@
};
};
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1",
"src_byte_clk1", "src_pixel_clk1",
"shadow_byte_clk1", "shadow_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 82 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&L12C>;
vdd-supply = <&L13C>;
avdd-supply = <&display_panel_avdd>;
lab-supply = <&ab_vreg>;
ibb-supply = <&ibb_vreg>;
};
&sde_dsi1 {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
qcom,platform-te-gpio = <&tlmm 83 0>;
qcom,panel-te-source = <1>;
vddio-supply = <&L12C>;
vdd-supply = <&L13C>;
avdd-supply = <&display_panel_avdd>;
};
&mdss_mdp {
connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi
&sde_dsi1 &sde_rscc>;
};
/* PHY TIMINGS REVISION YC with reduced margins*/
&dsi_sw43404_amoled_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>;
qcom,esd-check-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
};
@ -249,236 +128,86 @@
};
&dsi_sw43404_amoled_video {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
06 06 02 04 00 14 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_r66451_amoled_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x1c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
04 03 02 04 00 0e 09];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
06 06 02 04 00 14 0a];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_cmd_cphy {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04
19 03 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_r66451_amoled_video_cphy {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04
19 03 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_sharp_4k_dsc_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-status-value = <0x77>;
qcom,mdss-dsi-panel-on-check-value = <0x77>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_sharp_4k_dsc_video {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x77>;
qcom,mdss-dsi-panel-on-check-value = <0x77>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06
06 07 02 04 00 15 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_sharp_1080_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08
08 08 02 04 00 1a 0c];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
qcom,mdss-dsi-panel-clockrate = <900000000>;
};
};
qcom,esd-check-enabled;
};
&dsi_sharp_qsync_wqhd_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-display-timings {
timing@0 { /* WQHD 60FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03
03 02 02 04 00 0b 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
};
timing@1 { /* WQHD 60FPS VID */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* FHD 60FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
02 01 02 04 00 09 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
};
timing@3 { /* WQHD 90FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04
04 03 02 04 00 0e 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
};
timing@4 { /* WQHD 120FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
};
timing@5 { /* WQHD 120FPS VID */
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@6 { /* FHD 120FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03
03 02 02 04 00 0c 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
};
timing@7 { /* FHD 90FPS CMD */
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03
02 02 02 04 00 0a 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
};
@ -486,448 +215,88 @@
};
&dsi_sharp_qsync_wqhd_video {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_qhd_plus_dsc_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
06 06 02 04 00 13 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07
07 07 02 04 00 17 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_dual_nt35597_truly_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
/*
* DPHY regular margins
*/
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06
06 07 02 04 00 17 16 ];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_dual_nt35597_truly_video {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-supported-dfps-list = <60 57 55>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-min-refresh-rate = <53>;
qcom,mdss-dsi-max-refresh-rate = <60>;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
07 08 02 04 00 18 0c];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_nt35695b_truly_fhd_cmd {
qcom,ulps-enabled;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
/*
* DPHY regular margins
*/
qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07
07 07 02 04 00 18 16];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
qcom,esd-check-enabled;
};
&dsi_sim_cmd {
qcom,ulps-enabled;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,poms-align-panel-vsync;
qcom,mdss-dsi-display-timings {
timing@0 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06
06 04 02 04 00 12 0a];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
qcom,partial-update-enabled = "single_roi";
};
timing@1 { /* WQHD 60FPS vid mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06
06 04 02 04 00 12 0a];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
};
timing@2 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06
06 04 02 04 00 12 0b];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
qcom,partial-update-enabled = "single_roi";
};
timing@3 { /* FHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08
08 05 02 04 00 17 0c];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
qcom,panel-roi-alignment = <540 40 540 40 540 40>;
qcom,partial-update-enabled = "single_roi";
};
timing@4 { /* HD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a
0a 07 02 04 00 1d 0e];
qcom,display-topology = <1 1 1>,
<2 2 1>;
qcom,default-topology-index = <1>;
qcom,panel-roi-alignment = <360 40 360 40 360 40>;
qcom,partial-update-enabled = "single_roi";
};
};
};
&dsi_sim_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <1 0 1>,
<2 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_vdc_cmd {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_vdc_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_dsc_375_cmd {
qcom,ulps-enabled;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 1080p */
qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05
05 03 02 04 00 0e 09];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 { /* qhd */
qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02
02 01 02 04 00 08 07];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_dsc_10b_cmd {
qcom,ulps-enabled;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* QHD 60fps */
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
07 05 02 04 00 18 17];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 1080 60fps */
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
08 05 02 04 00 19 18];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <0>;
};
timing@2 { /* QHD 90fps */
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
07 05 02 04 00 18 17];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_cmd {
qcom,ulps-enabled;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 5K 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11
11 0c 02 04 00 30 15];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* FHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04
04 02 02 04 00 0c 08];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* WQHD 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03
03 01 02 04 00 0a 08];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
timing@3 { /* 4K 60FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05
05 03 02 04 00 10 0a];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_vid {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07
07 07 04 02 00 14 0b];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_dsc_375_cmd {
qcom,ulps-enabled;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 4k 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 4k 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05
05 03 02 04 00 10 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@2 { /* 4k 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08
08 05 02 04 00 16 0c];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@3 { /* 4k 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a
0a 07 02 04 00 1d 0e];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@4 { /* 1080 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01
01 01 02 04 00 05 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@5 { /* 1080 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02
02 01 02 04 00 08 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@6 { /* 1080 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@7 { /* 1080 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04
04 02 02 04 00 0c 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@8 { /* qhd 30 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02
01 00 02 04 00 06 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@9 { /* qhd 60 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03
03 01 02 04 00 09 08];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@10 { /* qhd 90 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04
04 02 02 04 00 0c 09];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@11 { /* qhd 120 FPS*/
qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05
05 03 02 04 00 0f 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@12 { /* 5k */
qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07
07 04 02 04 00 14 0b];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@13 { /* 720p 30 FPS */
qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01
01 00 02 04 00 04 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@14 { /* 720p 60 FPS */
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
01 01 02 04 00 06 06];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@15 { /* 720p 90 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02
02 01 02 04 00 07 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@16 { /* 720 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03
03 01 02 04 00 08 07];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@17 { /* 1080 144FPS cmd mode*/
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
06 06 02 04 00 13 0a];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_sec_hd_cmd {
qcom,ulps-enabled;
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
08 08 05 02 04 00 19 17];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
qcom,partial-update-enabled = "single_roi";
};

627
display/lahaina-sde.dtsi
View file

@ -1,3 +1,4 @@
#include "lahaina-sde-common.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
@ -6,316 +7,6 @@
label = "disp_rdump_region";
};
mdss_mdp: qcom,mdss_mdp@ae00000 {
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x84000>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x800>,
<0x0af50000 0x038>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"swfuse_phys";
clocks =
<&clock_gcc GCC_DISP_AHB_CLK>,
<&clock_gcc GCC_DISP_HF_AXI_CLK>,
<&clock_gcc GCC_DISP_SF_AXI_CLK>,
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>;
clock-max-rate = <0 0 0 0 460000000 19200000 460000000
460000000>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x494>;
qcom,sde-ctl-off = <0x16000 0x17000 0x18000
0x19000 0x1a000 0x1b000>;
qcom,sde-ctl-size = <0x1e8>;
qcom,sde-ctl-display-pref = "primary", "none", "none",
"none", "none", "none";
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
0x48000 0x49000 0x4a000>;
qcom,sde-mixer-size = <0x320>;
qcom,sde-mixer-display-pref = "primary", "primary", "none",
"none", "none", "none";
qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
"cwb", "cwb", "cwb";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x80>;
qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
qcom,sde-dspp-size = <0x1800>;
qcom,sde-dspp-rc-version = <0x00010000>;
qcom,sde-dspp-rc-off = <0x15800 0x14c00>;
qcom,sde-dspp-rc-size = <0x100>;
qcom,sde-dspp-rc-mem-size = <2720>;
qcom,sde-dest-scaler-top-off = <0x00061000>;
qcom,sde-dest-scaler-top-size = <0x1c>;
qcom,sde-dest-scaler-off = <0x800 0x1000>;
qcom,sde-dest-scaler-size = <0x800>;
qcom,sde-wb-off = <0x66000>;
qcom,sde-wb-size = <0x2c8>;
qcom,sde-wb-xin-id = <6>;
qcom,sde-wb-id = <2>;
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
qcom,sde-wb-clk-status = <0x3bc 20>;
qcom,sde-intf-off = <0x35000 0x36000
0x37000 0x38000>;
qcom,sde-intf-size = <0x2c0>;
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
qcom,sde-pp-off = <0x6a000 0x6b000
0x6c000 0x6d000 0x6e000 0x6f000>;
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,sde-pp-size = <0xd4>;
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>;
qcom,sde-merge-3d-size = <0x10>;
qcom,sde-cdm-off = <0x7a200>;
qcom,sde-cdm-size = <0x224>;
qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>;
qcom,sde-dsc-size = <0x10>;
qcom,sde-dsc-pair-mask = <2 1 4 3>;
qcom,sde-dsc-hw-rev = "dsc_1_2";
qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>;
qcom,sde-dsc-enc-size = <0x100>;
qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>;
qcom,sde-dsc-ctl-size = <0x10>;
qcom,sde-dsc-native422-supp = <0 0 1 1>;
qcom,sde-dsc-linewidth = <2048>;
qcom,sde-dither-off = <0xe0 0xe0 0xe0
0xe0 0xe0 0xe0>;
qcom,sde-dither-version = <0x00020000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-vdc-off = <0x7C000>;
qcom,sde-vdc-size = <0x10>;
qcom,sde-vdc-hw-rev = "vdc_1_2";
qcom,sde-vdc-enc = <0x200>;
qcom,sde-vdc-enc-size = <0x1C8>;
qcom,sde-vdc-ctl = <0xf00>;
qcom,sde-vdc-ctl-size = <0x10>;
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
"dma", "dma", "dma", "dma";
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
0x25000 0x27000 0x29000 0x2b000>;
qcom,sde-sspp-src-size = <0x1f8>;
qcom,sde-sspp-xin-id = <0 4 8 12
1 5 9 13>;
qcom,sde-sspp-excl-rect = <1 1 1 1
1 1 1 1>;
qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
0xb0 0xc8 0xe0 0xf8 0x110>;
qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000
3900000 3900000
3900000 3900000
3900000 3900000>;
qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000
5200000 5200000
5200000 5200000
5200000 5200000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl =
<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
qcom,sde-sspp-clk-status =
<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,
<0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;
qcom,sde-sspp-csc-off = <0x1a00>;
qcom,sde-csc-type = "csc-10bit";
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
qcom,sde-qseed-scalar-version = <0x3000>;
qcom,sde-sspp-qseed-off = <0xa00>;
qcom,sde-mixer-linewidth = <2560>;
qcom,sde-sspp-linewidth = <4096>;
qcom,sde-wb-linewidth = <4096>;
qcom,sde-wb-linewidth-linear = <5120>;
qcom,sde-mixer-blendstages = <0xb>;
qcom,sde-highest-bank-bit = <0x3>;
qcom,sde-ubwc-version = <0x400>;
qcom,sde-ubwc-swizzle = <0x6>;
qcom,sde-ubwc-bw-calc-version = <0x1>;
qcom,sde-ubwc-static = <0x1>;
qcom,sde-macrotile-mode = <0x1>;
qcom,sde-smart-panel-align-mode = <0xc>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
qcom,sde-pipe-order-version = <0x1>;
qcom,sde-has-dim-layer;
qcom,sde-has-dest-scaler;
qcom,sde-has-idle-pc;
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
qcom,sde-max-bw-low-kbps = <11800000>;
qcom,sde-max-bw-high-kbps = <15500000>;
qcom,sde-min-core-ib-kbps = <2500000>;
qcom,sde-min-llcc-ib-kbps = <0>;
qcom,sde-min-dram-ib-kbps = <800000>;
qcom,sde-dram-channels = <2>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-dspp-ltm-version = <0x00010001>;
/* offsets are based off dspp 0 and dspp 1 */
qcom,sde-dspp-ltm-off = <0x15300 0x14300>;
qcom,sde-dspp-spr-off = <0x15400 0x14400>;
qcom,sde-dspp-spr-size = <0x200>;
qcom,sde-dspp-spr-version = <0x00010000>;
qcom,sde-dspp-demura-off = <0x15600 0x14800>;
qcom,sde-dspp-demura-size = <0x200>;
qcom,sde-dspp-demura-version = <0x00010000>;
qcom,sde-uidle-off = <0x80000>;
qcom,sde-uidle-size = <0x70>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x1040>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>;
qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;
qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>,
<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;
qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;
qcom,sde-qos-refresh-rates = <60 120>;
qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x400>;
qcom,sde-reg-dma-id = <0 1>;
qcom,sde-reg-dma-version = <0x00020000>;
qcom,sde-reg-dma-trigger-off = <0x119c>;
qcom,sde-reg-dma-xin-id = <7>;
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
qcom,sde-secure-sid-mask = <0x4000821>;
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
"qcom,sde-reg-bus";
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 74000>,
<0 148000>,
<0 265000>;
qcom,sde-sspp-vig-blocks {
qcom,sde-vig-csc-off = <0x1a00>;
qcom,sde-vig-qseed-off = <0xa00>;
qcom,sde-vig-qseed-size = <0xa0>;
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
qcom,sde-vig-igc = <0x1d00 0x00060000>;
qcom,sde-vig-inverse-pma;
};
qcom,sde-sspp-dma-blocks {
dgm@0 {
qcom,sde-dma-igc = <0x400 0x00050000>;
qcom,sde-dma-gc = <0x600 0x00050000>;
qcom,sde-dma-inverse-pma;
qcom,sde-dma-csc-off = <0x200>;
};
dgm@1 {
qcom,sde-dma-igc = <0x1400 0x00050000>;
qcom,sde-dma-gc = <0x600 0x00050000>;
qcom,sde-dma-inverse-pma;
qcom,sde-dma-csc-off = <0x1200>;
};
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x1260 0x00040000>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "mmcx";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
@ -483,184 +174,6 @@
"qcom,sde-ebi-bus";
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
compatible = "qcom,dsi-ctrl-hw-v2.5";
label = "dsi-ctrl-0";
cell-index = <0>;
frame-threshold-time-us = <800>;
reg = <0xae94000 0x400>,
<0xaf08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
vdda-1p2-supply = <&L6B>;
refgen-supply = <&refgen>;
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <8350>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
compatible = "qcom,dsi-ctrl-hw-v2.5";
label = "dsi-ctrl-1";
cell-index = <1>;
frame-threshold-time-us = <800>;
reg = <0xae96000 0x400>,
<0xaf08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <5 0>;
vdda-1p2-supply = <&L6B>;
refgen-supply = <&refgen>;
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <8350>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
compatible = "qcom,dsi-phy-v4.2";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xae94400 0x800>,
<0xae94900 0x27c>,
<0xaf03000 0x8>,
<0xae94200 0x100>;
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
pll-label = "dsi_pll_5nm";
vdda-0p9-supply = <&L5B>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
memory-region = <&dfps_data_memory>;
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <37550>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 {
compatible = "qcom,dsi-phy-v4.2";
label = "dsi-phy-1";
cell-index = <1>;
#clock-cells = <1>;
reg = <0xae96400 0x800>,
<0xae96900 0x27c>,
<0xaf03000 0x8>,
<0xae96200 0x100>;
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
pll-label = "dsi_pll_5nm";
vdda-0p9-supply = <&L5B>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <37550>;
qcom,supply-disable-load = <0>;
};
};
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x820 0x402>;
@ -677,5 +190,143 @@
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
};
};
&mdss_mdp {
clocks =
<&clock_gcc GCC_DISP_AHB_CLK>,
<&clock_gcc GCC_DISP_HF_AXI_CLK>,
<&clock_gcc GCC_DISP_SF_AXI_CLK>,
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
mmcx-supply = <&VDD_MMCX_LEVEL>;
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
"qcom,sde-reg-bus";
qcom,sde-has-idle-pc;
qcom,sde-dspp-ltm-version = <0x00010001>;
/* offsets are based off dspp 0 and dspp 1 */
qcom,sde-dspp-ltm-off = <0x15300 0x14300>;
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "mmcx";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_dsi0 {
vdda-1p2-supply = <&L6B>;
refgen-supply = <&refgen>;
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <8350>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_dsi1 {
vdda-1p2-supply = <&L6B>;
refgen-supply = <&refgen>;
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <8350>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_dsi_phy0 {
vdda-0p9-supply = <&L5B>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
memory-region = <&dfps_data_memory>;
};
&mdss_dsi_phy1 {
vdda-0p9-supply = <&L5B>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
};