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arm/dts: Modify trip soc threshold from 10% to 5%

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Modify trip soc limiting cpu performance threshold
from 10% to 5% .

Change-Id: I9cd86e98b5f3297f0f28953bf4531dea6a64f70a
Signed-off-by: mahj8 <mahj8@lenovo.com>
Reviewed-on: https://gerrit.mot.com/2059866
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
mahj8 2021-09-06 10:02:15 +08:00 • committed by panyq6
commit 3127037660
2 changed files with 8 additions and 0 deletions
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4
qcom/holi-moto-common-overlay.dtsi
View file

@ -581,6 +581,10 @@
qcom,bcl-not-mitigate-icl = <2500>;
};
&socd_trip {
temperature = <95>;
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;

4
qcom/holi-pm6125-moto-common-overlay.dtsi
View file

@ -318,3 +318,7 @@
io-channel-names = "usb_hw_current_max";
qcom,bcl-not-mitigate-icl = <2500>;
};
&socd_trip {
temperature = <95>;
};