mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "ARM: dts: msm: Add CSIPHY/CCI devicetree support for shima" into camera-kernel.lnx.4.0
This commit is contained in:
Camera Software Integration
Gerrit - the friendly Code Review server
commit
314d22b080
1 changed files with 390 additions and 0 deletions
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@ -11,6 +11,396 @@
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status = "ok"
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};
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cam_csiphy0: qcom,csiphy0 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0x0ac6a000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x6a000>;
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interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy0";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY0_CLK>,
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<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csi0phytimer_clk_src",
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"csi0phytimer_clk";
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src-clock-name = "csi0phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy1: qcom,csiphy1 {
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cell-index = <1>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0xac6c000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x6c000>;
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interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy1";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY1_CLK>,
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<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy1_clk",
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"csi1phytimer_clk_src",
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"csi1phytimer_clk";
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src-clock-name = "csi1phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy2: qcom,csiphy2 {
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cell-index = <2>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0xac6e000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x6e000>;
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interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy2";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY2_CLK>,
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<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy2_clk",
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"csi2phytimer_clk_src",
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"csi2phytimer_clk";
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src-clock-name = "csi2phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy3: qcom,csiphy3 {
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cell-index = <3>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0xac70000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x70000>;
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interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy3";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY3_CLK>,
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<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy3_clk",
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"csi3phytimer_clk_src",
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"csi3phytimer_clk";
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src-clock-name = "csi3phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy4: qcom,csiphy4 {
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cell-index = <4>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0xac72000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x72000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy4";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY4_CLK>,
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<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy4_clk",
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"csi4phytimer_clk_src",
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"csi4phytimer_clk";
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src-clock-name = "csi4phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy5: qcom,csiphy5 {
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cell-index = <5>;
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compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
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reg = <0xac74000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x74000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy5";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-1p2-supply = <&L10C>;
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csi-vdd-0p9-supply = <&L6B>;
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regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
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"csi-vdd-0p9";
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 1200000 880000>;
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rgltr-max-voltage = <0 0 1260000 1050000>;
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rgltr-load-current = <0 0 54000 96400>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY5_CLK>,
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<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy5_clk",
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"csi5phytimer_clk_src",
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"csi5phytimer_clk";
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src-clock-name = "csi5phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs";
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clock-rates =
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<320000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_cci0: qcom,cci0 {
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cell-index = <0>;
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compatible = "qcom,cci", "simple-bus";
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reg = <0xac4f000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x4f000>;
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interrupt-names = "cci";
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interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
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status = "ok"
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
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<&clock_camcc CAM_CC_CCI_0_CLK>;
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clock-names = "cci_0_clk_src",
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"cci_0_clk";
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src-clock-name = "cci_0_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <37500000 0>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci0_active &cci1_active>;
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pinctrl-1 = <&cci0_suspend &cci1_suspend>;
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gpios = <&tlmm 107 0>,
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<&tlmm 108 0>,
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<&tlmm 109 0>,
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<&tlmm 110 0>;
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gpio-req-tbl-num = <0 1 2 3>;
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gpio-req-tbl-flags = <1 1 1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA0",
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"CCI_I2C_CLK0",
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"CCI_I2C_DATA1",
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"CCI_I2C_CLK1";
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i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_custom_cci0: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
|
||||
};
|
||||
};
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||||
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cam_cci1: qcom,cci1 {
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cell-index = <1>;
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compatible = "qcom,cci", "simple-bus";
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reg = <0xac50000 0x1000>;
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reg-names = "cci";
|
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reg-cam-base = <0x50000>;
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interrupt-names = "cci";
|
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interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
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status = "ok"
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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regulator-names = "gdscr";
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||||
clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
|
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<&clock_camcc CAM_CC_CCI_1_CLK>;
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clock-names = "cci_1_clk_src",
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"cci_1_clk";
|
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src-clock-name = "cci_1_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <37500000 0>;
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||||
pinctrl-names = "cam_default", "cam_suspend";
|
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pinctrl-0 = <&cci2_active &cci3_active>;
|
||||
pinctrl-1 = <&cci2_suspend &cci3_suspend>;
|
||||
gpios = <&tlmm 111 0>,
|
||||
<&tlmm 112 0>,
|
||||
<&tlmm 113 0>,
|
||||
<&tlmm 114 0>;
|
||||
gpio-req-tbl-num = <0 1 2 3>;
|
||||
gpio-req-tbl-flags = <1 1 1 1>;
|
||||
gpio-req-tbl-label = "CCI_I2C_DATA2",
|
||||
"CCI_I2C_CLK2",
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||||
"CCI_I2C_DATA3",
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||||
"CCI_I2C_CLK3";
|
||||
|
||||
i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
|
||||
hw-thigh = <201>;
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||||
hw-tlow = <174>;
|
||||
hw-tsu-sto = <204>;
|
||||
hw-tsu-sta = <231>;
|
||||
hw-thd-dat = <22>;
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||||
hw-thd-sta = <162>;
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||||
hw-tbuf = <227>;
|
||||
hw-scl-stretch-en = <0>;
|
||||
hw-trdhld = <6>;
|
||||
hw-tsp = <3>;
|
||||
cci-clk-src = <37500000>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
|
||||
hw-thigh = <38>;
|
||||
hw-tlow = <56>;
|
||||
hw-tsu-sto = <40>;
|
||||
hw-tsu-sta = <40>;
|
||||
hw-thd-dat = <22>;
|
||||
hw-thd-sta = <35>;
|
||||
hw-tbuf = <62>;
|
||||
hw-scl-stretch-en = <0>;
|
||||
hw-trdhld = <6>;
|
||||
hw-tsp = <3>;
|
||||
cci-clk-src = <37500000>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
i2c_freq_custom_cci1: qcom,i2c_custom_mode {
|
||||
hw-thigh = <38>;
|
||||
hw-tlow = <56>;
|
||||
hw-tsu-sto = <40>;
|
||||
hw-tsu-sta = <40>;
|
||||
hw-thd-dat = <22>;
|
||||
hw-thd-sta = <35>;
|
||||
hw-tbuf = <62>;
|
||||
hw-scl-stretch-en = <1>;
|
||||
hw-trdhld = <6>;
|
||||
hw-tsp = <3>;
|
||||
cci-clk-src = <37500000>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
|
||||
hw-thigh = <16>;
|
||||
hw-tlow = <22>;
|
||||
hw-tsu-sto = <17>;
|
||||
hw-tsu-sta = <18>;
|
||||
hw-thd-dat = <16>;
|
||||
hw-thd-sta = <15>;
|
||||
hw-tbuf = <24>;
|
||||
hw-scl-stretch-en = <0>;
|
||||
hw-trdhld = <3>;
|
||||
hw-tsp = <3>;
|
||||
cci-clk-src = <37500000>;
|
||||
status = "ok"
|
||||
};
|
||||
};
|
||||
|
||||
qcom,cam_smmu {
|
||||
compatible = "qcom,msm-cam-smmu", "simple-bus";
|
||||
status = "ok"
|
||||
|
|
|
|||
Loading…
Reference in a new issue