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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge branch 'pci/enumeration'
- add decoding for 16 GT/s link speed (Jay Fang)
- add interfaces to get max link speed and width (Tal Gilboa)
- add pcie_bandwidth_capable() to compute max supported link bandwidth
(Tal Gilboa)
- add pcie_bandwidth_available() to compute bandwidth available to device
(Tal Gilboa)
- add pcie_print_link_status() to log link speed and whether it's limited
(Tal Gilboa)
- use PCI core interfaces to report when device performance may be
limited by its slot instead of doing it in each driver (Tal Gilboa)
* pci/enumeration:
fm10k: Report PCIe link properties with pcie_print_link_status()
net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
net/mlx5: Report PCIe link properties with pcie_print_link_status()
net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
PCI: Add pcie_print_link_status() to log link speed and whether it's limited
PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
PCI: Add pcie_get_width_cap() to find max supported link width
PCI: Add pcie_get_speed_cap() to find max supported link speed
PCI: Add decoding for 16 GT/s link speed
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
commit
315271b0ff
11 changed files with 221 additions and 231 deletions
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@ -158,45 +158,18 @@ static DEVICE_ATTR_RO(resource);
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static ssize_t max_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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const char *speed;
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struct pci_dev *pdev = to_pci_dev(dev);
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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switch (linkcap & PCI_EXP_LNKCAP_SLS) {
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case PCI_EXP_LNKCAP_SLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
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}
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static DEVICE_ATTR_RO(max_link_speed);
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static ssize_t max_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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struct pci_dev *pdev = to_pci_dev(dev);
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);
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return sprintf(buf, "%u\n", pcie_get_width_cap(pdev));
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}
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static DEVICE_ATTR_RO(max_link_width);
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@ -213,6 +186,9 @@ static ssize_t current_link_speed_show(struct device *dev,
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return -EINVAL;
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switch (linkstat & PCI_EXP_LNKSTA_CLS) {
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case PCI_EXP_LNKSTA_CLS_16_0GB:
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speed = "16 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_8_0GB:
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speed = "8 GT/s";
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break;
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@ -5146,6 +5146,180 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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}
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EXPORT_SYMBOL(pcie_get_minimum_link);
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/**
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* pcie_bandwidth_available - determine minimum link settings of a PCIe
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* device and its bandwidth limitation
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* @dev: PCI device to query
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* @limiting_dev: storage for device causing the bandwidth limitation
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* @speed: storage for speed of limiting device
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* @width: storage for width of limiting device
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*
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* Walk up the PCI device chain and find the point where the minimum
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* bandwidth is available. Return the bandwidth available there and (if
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* limiting_dev, speed, and width pointers are supplied) information about
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* that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
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* raw bandwidth.
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*/
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u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
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enum pci_bus_speed *speed,
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enum pcie_link_width *width)
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{
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u16 lnksta;
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enum pci_bus_speed next_speed;
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enum pcie_link_width next_width;
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u32 bw, next_bw;
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if (speed)
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*speed = PCI_SPEED_UNKNOWN;
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if (width)
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*width = PCIE_LNK_WIDTH_UNKNOWN;
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bw = 0;
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while (dev) {
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
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next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
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next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
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PCI_EXP_LNKSTA_NLW_SHIFT;
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next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
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/* Check if current device limits the total bandwidth */
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if (!bw || next_bw <= bw) {
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bw = next_bw;
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if (limiting_dev)
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*limiting_dev = dev;
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if (speed)
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*speed = next_speed;
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if (width)
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*width = next_width;
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}
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dev = pci_upstream_bridge(dev);
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}
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return bw;
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}
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EXPORT_SYMBOL(pcie_bandwidth_available);
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/**
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* pcie_get_speed_cap - query for the PCI device's link speed capability
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* @dev: PCI device to query
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*
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* Query the PCI device speed capability. Return the maximum link speed
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* supported by the device.
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*/
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enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
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{
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u32 lnkcap2, lnkcap;
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/*
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* PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
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* Speeds Vector in Link Capabilities 2 when supported, falling
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* back to Max Link Speed in Link Capabilities otherwise.
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*/
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pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
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if (lnkcap2) { /* PCIe r3.0-compliant */
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if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
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return PCIE_SPEED_16_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
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return PCIE_SPEED_8_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
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return PCIE_SPEED_5_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
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return PCIE_SPEED_2_5GT;
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return PCI_SPEED_UNKNOWN;
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}
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pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
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if (lnkcap) {
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if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
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return PCIE_SPEED_16_0GT;
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else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
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return PCIE_SPEED_8_0GT;
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else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
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return PCIE_SPEED_5_0GT;
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else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
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return PCIE_SPEED_2_5GT;
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}
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return PCI_SPEED_UNKNOWN;
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}
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/**
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* pcie_get_width_cap - query for the PCI device's link width capability
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* @dev: PCI device to query
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*
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* Query the PCI device width capability. Return the maximum link width
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* supported by the device.
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*/
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
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{
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u32 lnkcap;
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pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
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if (lnkcap)
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return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
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return PCIE_LNK_WIDTH_UNKNOWN;
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}
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/**
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* pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
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* @dev: PCI device
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* @speed: storage for link speed
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* @width: storage for link width
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*
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* Calculate a PCI device's link bandwidth by querying for its link speed
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* and width, multiplying them, and applying encoding overhead. The result
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* is in Mb/s, i.e., megabits/second of raw bandwidth.
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*/
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width)
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{
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*speed = pcie_get_speed_cap(dev);
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*width = pcie_get_width_cap(dev);
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if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
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return 0;
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return *width * PCIE_SPEED2MBS_ENC(*speed);
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}
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/**
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* pcie_print_link_status - Report the PCI device's link speed and width
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* @dev: PCI device to query
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*
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* Report the available bandwidth at the device. If this is less than the
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* device is capable of, report the device's maximum possible bandwidth and
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* the upstream link that limits its performance to less than that.
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*/
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void pcie_print_link_status(struct pci_dev *dev)
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{
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enum pcie_link_width width, width_cap;
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enum pci_bus_speed speed, speed_cap;
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struct pci_dev *limiting_dev = NULL;
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u32 bw_avail, bw_cap;
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bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
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bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
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if (bw_avail >= bw_cap)
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pci_info(dev, "%u.%03u Gb/s available bandwidth (%s x%d link)\n",
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bw_cap / 1000, bw_cap % 1000,
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PCIE_SPEED2STR(speed_cap), width_cap);
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else
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pci_info(dev, "%u.%03u Gb/s available bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
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bw_avail / 1000, bw_avail % 1000,
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PCIE_SPEED2STR(speed), width,
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limiting_dev ? pci_name(limiting_dev) : "<unknown>",
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bw_cap / 1000, bw_cap % 1000,
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PCIE_SPEED2STR(speed_cap), width_cap);
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}
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EXPORT_SYMBOL(pcie_print_link_status);
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/**
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* pci_select_bars - Make BAR mask from the type of resource
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* @dev: the PCI device for which BAR mask is made
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@ -253,6 +253,27 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
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void pci_reassigndev_resource_alignment(struct pci_dev *dev);
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void pci_disable_bridge_window(struct pci_dev *dev);
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/* PCIe link information */
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#define PCIE_SPEED2STR(speed) \
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((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
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(speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
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(speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
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(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
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"Unknown speed")
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/* PCIe speed to Mb/s reduced by encoding overhead */
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#define PCIE_SPEED2MBS_ENC(speed) \
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((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
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(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
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(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
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(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
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0)
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enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* Capability position */
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@ -592,7 +592,7 @@ const unsigned char pcie_link_speed[] = {
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PCIE_SPEED_2_5GT, /* 1 */
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PCIE_SPEED_5_0GT, /* 2 */
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PCIE_SPEED_8_0GT, /* 3 */
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PCI_SPEED_UNKNOWN, /* 4 */
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PCIE_SPEED_16_0GT, /* 4 */
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PCI_SPEED_UNKNOWN, /* 5 */
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PCI_SPEED_UNKNOWN, /* 6 */
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PCI_SPEED_UNKNOWN, /* 7 */
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@ -76,6 +76,7 @@ static const char *pci_bus_speed_strings[] = {
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"2.5 GT/s PCIe", /* 0x14 */
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"5.0 GT/s PCIe", /* 0x15 */
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"8.0 GT/s PCIe", /* 0x16 */
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"16.0 GT/s PCIe", /* 0x17 */
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};
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static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
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