From 317169acd3996010d0bbffcc8a80d357581b4ab2 Mon Sep 17 00:00:00 2001
From: Harshdeep Dhatt <hdhatt@codeaurora.org>
Date: Fri, 27 Mar 2020 03:17:29 -0600
Subject: [PATCH] msm: kgsl: Remove any eCP references

As this is not enabled for any a6xx.

Change-Id: I9f44301885dfcd24c79d18c857267a4225cdb26b
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
---
 drivers/gpu/msm/adreno.h          | 8 +++-----
 drivers/gpu/msm/adreno_a6xx_gmu.c | 9 ---------
 drivers/gpu/msm/adreno_a6xx_hfi.c | 7 -------
 drivers/gpu/msm/adreno_a6xx_hfi.h | 2 +-
 4 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 1d5bacb851c5..f95a7dcdfd26 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -97,14 +97,12 @@
  * for droop mitigation
  */
 #define ADRENO_ACD BIT(17)
-/* ECP enabled GMU */
-#define ADRENO_ECP BIT(18)
 /* Cooperative reset enabled GMU */
-#define ADRENO_COOP_RESET BIT(19)
+#define ADRENO_COOP_RESET BIT(18)
 /* Indicates that the specific target is no longer supported */
-#define ADRENO_DEPRECATED BIT(20)
+#define ADRENO_DEPRECATED BIT(19)
 /* The target supports ringbuffer level APRIV */
-#define ADRENO_APRIV BIT(21)
+#define ADRENO_APRIV BIT(20)
 /*
  * Adreno GPU quirks - control bits for various workarounds
  */
diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c
index b4fd51a0a5b1..feaffb64675a 100644
--- a/drivers/gpu/msm/adreno_a6xx_gmu.c
+++ b/drivers/gpu/msm/adreno_a6xx_gmu.c
@@ -1416,15 +1416,6 @@ static int a6xx_gmu_cache_finalize(struct adreno_device *adreno_dev,
 	if (IS_ERR(md))
 		return PTR_ERR(md);
 
-	if (ADRENO_FEATURE(adreno_dev, ADRENO_ECP)) {
-		/* Allocation to account for future MEM_ALLOC buffers */
-		md = a6xx_gmu_kmem_allocate(gmu, GMU_NONCACHED_KERNEL,
-				0, SZ_32K,
-				(IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV));
-		if (IS_ERR(md))
-			return PTR_ERR(md);
-	}
-
 	gmu->preallocations = true;
 
 	return 0;
diff --git a/drivers/gpu/msm/adreno_a6xx_hfi.c b/drivers/gpu/msm/adreno_a6xx_hfi.c
index 68752897ddb9..1b1141093715 100644
--- a/drivers/gpu/msm/adreno_a6xx_hfi.c
+++ b/drivers/gpu/msm/adreno_a6xx_hfi.c
@@ -403,7 +403,6 @@ static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu_device *gmu)
 }
 
 static const char * const a6xx_hfi_features[] = {
-	[HFI_FEATURE_ECP] = "ECP",
 	[HFI_FEATURE_ACD] = "ACD",
 	[HFI_FEATURE_LM] = "LM",
 };
@@ -755,12 +754,6 @@ int a6xx_hfi_start(struct kgsl_device *device,
 	 * send H2F_MSG_CORE_FW_START and features for A640 devices
 	 */
 	if (GMU_VER_MAJOR(gmu->ver.hfi) >= 2) {
-		if (ADRENO_FEATURE(adreno_dev, ADRENO_ECP)) {
-			result = a6xx_hfi_send_feature_ctrl(gmu,
-					HFI_FEATURE_ECP, 1, 0);
-			if (result)
-				return result;
-		}
 
 		result = a6xx_hfi_send_acd_feature_ctrl(gmu, adreno_dev);
 		if (result)
diff --git a/drivers/gpu/msm/adreno_a6xx_hfi.h b/drivers/gpu/msm/adreno_a6xx_hfi.h
index ee1a25c15769..08b00020322a 100644
--- a/drivers/gpu/msm/adreno_a6xx_hfi.h
+++ b/drivers/gpu/msm/adreno_a6xx_hfi.h
@@ -67,7 +67,7 @@ struct hfi_queue_table;
 #define DCVS_ACK_BLOCK 1
 
 #define HFI_FEATURE_DCVS	0
-#define HFI_FEATURE_ECP		1
+#define HFI_FEATURE_HWSCHED	1
 #define HFI_FEATURE_PREEMPTION	2
 #define HFI_FEATURE_CLOCKS_ON	3
 #define HFI_FEATURE_BUS_ON	4