From 0c86eedd2114469a83a07950d5ce612cb269e21d Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Thu, 23 Apr 2020 14:54:29 -0400 Subject: [PATCH 1/2] Revert "disp: msm: sde: add support to handle mdp limits property" This reverts commit a4c2827a47fc68625e72c7d85722e5116b6a6e75. The change is not needed on 5.4 since BW limits have moved to user-space per-target based XML file, and there are already other properties for specifying the various linewidth parameters. Change-Id: I87d81047678869bba6f8ec98104dec17c7a9ace2 Signed-off-by: Steve Cohen --- msm/sde/sde_crtc.c | 32 -------- msm/sde/sde_hw_catalog.c | 169 --------------------------------------- msm/sde/sde_hw_catalog.h | 40 --------- 3 files changed, 241 deletions(-) diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 7cb0a5aebf17..c630b591509d 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -4930,8 +4930,6 @@ static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc, static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info, struct sde_mdss_cfg *catalog) { - int i, j; - sde_kms_info_reset(info); sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion); @@ -4978,36 +4976,6 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info, sde_kms_info_add_keyint(info, "has_uidle", true); - for (i = 0; i < catalog->limit_count; i++) { - sde_kms_info_add_keyint(info, - catalog->limit_cfg[i].name, - catalog->limit_cfg[i].lmt_case_cnt); - - for (j = 0; j < catalog->limit_cfg[i].lmt_case_cnt; j++) { - sde_kms_info_add_keyint(info, - catalog->limit_cfg[i].vector_cfg[j].usecase, - catalog->limit_cfg[i].vector_cfg[j].value); - } - - if (!strcmp(catalog->limit_cfg[i].name, - "sspp_linewidth_usecases")) - sde_kms_info_add_keyint(info, - "sspp_linewidth_values", - catalog->limit_cfg[i].lmt_vec_cnt); - else if (!strcmp(catalog->limit_cfg[i].name, - "sde_bwlimit_usecases")) - sde_kms_info_add_keyint(info, - "sde_bwlimit_values", - catalog->limit_cfg[i].lmt_vec_cnt); - - for (j = 0; j < catalog->limit_cfg[i].lmt_vec_cnt; j++) { - sde_kms_info_add_keyint(info, "limit_usecase", - catalog->limit_cfg[i].value_cfg[j].use_concur); - sde_kms_info_add_keyint(info, "limit_value", - catalog->limit_cfg[i].value_cfg[j].value); - } - } - sde_kms_info_add_keystr(info, "core_ib_ff", catalog->perf.core_ib_ff); sde_kms_info_add_keystr(info, "core_clk_ff", diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 7c3a724029aa..95139ea04d4d 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -194,7 +194,6 @@ enum sde_prop { UBWC_BW_CALC_VERSION, PIPE_ORDER_VERSION, SEC_SID_MASK, - SDE_LIMITS, BASE_LAYER, SDE_PROP_MAX, }; @@ -294,14 +293,6 @@ enum { INTF_PROP_MAX, }; -enum { - LIMIT_NAME, - LIMIT_USECASE, - LIMIT_ID, - LIMIT_VALUE, - LIMIT_PROP_MAX, -}; - enum { PP_OFF, PP_LEN, @@ -557,7 +548,6 @@ static struct sde_prop_type sde_prop[] = { {PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false, PROP_TYPE_U32}, {SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY}, - {SDE_LIMITS, "qcom,sde-limits", false, PROP_TYPE_NODE}, {BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL}, }; @@ -876,14 +866,6 @@ static struct sde_prop_type qdss_prop[] = { {HW_LEN, "qcom,sde-qdss-size", false, PROP_TYPE_U32}, }; -static struct sde_prop_type limit_usecase_prop[] = { - {LIMIT_NAME, "qcom,sde-limit-name", false, PROP_TYPE_STRING}, - {LIMIT_USECASE, "qcom,sde-limit-cases", false, PROP_TYPE_STRING_ARRAY}, - {LIMIT_ID, "qcom,sde-limit-ids", false, PROP_TYPE_U32_ARRAY}, - {LIMIT_VALUE, "qcom,sde-limit-values", false, - PROP_TYPE_BIT_OFFSET_ARRAY}, -}; - static struct sde_prop_type demura_prop[] = { [DEMURA_OFF] = {DEMURA_OFF, "qcom,sde-dspp-demura-off", false, PROP_TYPE_U32_ARRAY}, @@ -3659,149 +3641,6 @@ static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, return 0; } -static int sde_read_limit_node(struct device_node *snp, - struct sde_prop_value *lmt_val, struct sde_mdss_cfg *cfg) -{ - int j, i = 0, rc = 0; - const char *type = NULL; - struct device_node *node = NULL; - - for_each_child_of_node(snp, node) { - cfg->limit_cfg[i].vector_cfg = - kcalloc(cfg->limit_cfg[i].lmt_case_cnt, - sizeof(struct limit_vector_cfg), GFP_KERNEL); - if (!cfg->limit_cfg[i].vector_cfg) { - rc = -ENOMEM; - goto error; - } - - for (j = 0; j < cfg->limit_cfg[i].lmt_case_cnt; j++) { - of_property_read_string_index(node, - limit_usecase_prop[LIMIT_USECASE].prop_name, - j, &type); - cfg->limit_cfg[i].vector_cfg[j].usecase = type; - cfg->limit_cfg[i].vector_cfg[j].value = - PROP_VALUE_ACCESS(&lmt_val[i * LIMIT_PROP_MAX], - LIMIT_ID, j); - } - - cfg->limit_cfg[i].value_cfg = - kcalloc(cfg->limit_cfg[i].lmt_vec_cnt, - sizeof(struct limit_value_cfg), GFP_KERNEL); - - if (!cfg->limit_cfg[i].value_cfg) { - rc = -ENOMEM; - goto error; - } - - for (j = 0; j < cfg->limit_cfg[i].lmt_vec_cnt; j++) { - cfg->limit_cfg[i].value_cfg[j].use_concur = - PROP_BITVALUE_ACCESS( - &lmt_val[i * LIMIT_PROP_MAX], - LIMIT_VALUE, j, 0); - cfg->limit_cfg[i].value_cfg[j].value = - PROP_BITVALUE_ACCESS( - &lmt_val[i * LIMIT_PROP_MAX], - LIMIT_VALUE, j, 1); - - } - i++; - } - - return 0; -error: - for (j = 0; j < cfg->limit_count; j++) { - kfree(cfg->limit_cfg[j].vector_cfg); - kfree(cfg->limit_cfg[j].value_cfg); - } - - cfg->limit_count = 0; - return rc; -} - -static int sde_validate_limit_node(struct device_node *snp, - struct sde_prop_value *sde_limit_value, struct sde_mdss_cfg *cfg) -{ - int i = 0, rc = 0; - struct device_node *node = NULL; - int limit_value_count[LIMIT_PROP_MAX]; - bool limit_value_exists[LIMIT_SUBBLK_COUNT_MAX][LIMIT_PROP_MAX]; - const char *type = NULL; - - for_each_child_of_node(snp, node) { - rc = _validate_dt_entry(node, limit_usecase_prop, - ARRAY_SIZE(limit_usecase_prop), - limit_value_count, NULL); - if (rc) - goto end; - - rc = _read_dt_entry(node, limit_usecase_prop, - ARRAY_SIZE(limit_usecase_prop), limit_value_count, - &limit_value_exists[i][0], - &sde_limit_value[i * LIMIT_PROP_MAX]); - if (rc) - goto end; - - cfg->limit_cfg[i].lmt_case_cnt = - limit_value_count[LIMIT_ID]; - - cfg->limit_cfg[i].lmt_vec_cnt = - limit_value_count[LIMIT_VALUE]; - of_property_read_string(node, - limit_usecase_prop[LIMIT_NAME].prop_name, &type); - cfg->limit_cfg[i].name = type; - - if (!limit_value_count[LIMIT_ID] || - !limit_value_count[LIMIT_VALUE]) { - rc = -EINVAL; - goto end; - } - i++; - } - return 0; -end: - cfg->limit_count = 0; - return rc; -} - -static int sde_limit_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) -{ - struct device_node *snp = NULL; - struct sde_prop_value *sde_limit_value = NULL; - int rc = 0; - - snp = of_get_child_by_name(np, sde_prop[SDE_LIMITS].prop_name); - if (!snp) - goto end; - - cfg->limit_count = of_get_child_count(snp); - if (cfg->limit_count < 0) { - rc = -EINVAL; - goto end; - } - - sde_limit_value = kzalloc(cfg->limit_count * LIMIT_PROP_MAX * - sizeof(struct sde_prop_value), GFP_KERNEL); - if (!sde_limit_value) { - rc = -ENOMEM; - goto end; - } - - rc = sde_validate_limit_node(snp, sde_limit_value, cfg); - if (rc) { - SDE_ERROR("validating limit node failed\n"); - goto end; - } - - rc = sde_read_limit_node(snp, sde_limit_value, cfg); - if (rc) - SDE_ERROR("reading limit node failed\n"); - -end: - kfree(sde_limit_value); - return rc; -} - static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) { int rc, i, dma_rc, len, prop_count[SDE_PROP_MAX]; @@ -3929,9 +3768,6 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) PIPE_ORDER_VERSION, 0); cfg->has_base_layer = PROP_VALUE_ACCESS(prop_value, BASE_LAYER, 0); - rc = sde_limit_parse_dt(np, cfg); - if (rc) - SDE_DEBUG("parsing of sde limit failed\n"); end: kfree(prop_value); return rc; @@ -4897,11 +4733,6 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg) kfree(sde_cfg->vbif[i].qos_tbl[j].priority_lvl); } - for (i = 0; i < sde_cfg->limit_count; i++) { - kfree(sde_cfg->limit_cfg[i].vector_cfg); - kfree(sde_cfg->limit_cfg[i].value_cfg); - } - kfree(sde_cfg->perf.qos_refresh_rate); kfree(sde_cfg->perf.danger_lut); kfree(sde_cfg->perf.safe_lut); diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index d685238cc357..f544cc038ed9 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -81,7 +81,6 @@ #define MAX_XIN_COUNT 16 #define SSPP_SUBBLK_COUNT_MAX 2 -#define LIMIT_SUBBLK_COUNT_MAX 10 #define SDE_CTL_CFG_VERSION_1_0_0 0x100 #define MAX_INTF_PER_CTL_V1 2 @@ -1337,42 +1336,6 @@ struct sde_perf_cfg { u32 num_mnoc_ports; }; -/** - * struct limit_vector_cfg - information on the usecase for each limit - * @usecase: usecase for each limit - * @value: id corresponding to each usecase - */ -struct limit_vector_cfg { - const char *usecase; - u32 value; -}; - -/** - * struct limit_value_cfg - information on the value of usecase - * @use_concur: usecase for each limit - * @value: value corresponding to usecase for each limit - */ -struct limit_value_cfg { - u32 use_concur; - u32 value; -}; - -/** - * struct sde_limit_cfg - information om different mdp limits - * @name: name of the limit property - * @lmt_vec_cnt: number of vector values for each limit - * @lmt_case_cnt: number of usecases for each limit - * @vector_cfg: pointer to the vector entries containing info on usecase - * @value_cfg: pointer to the value of each vector entry - */ -struct sde_limit_cfg { - const char *name; - u32 lmt_vec_cnt; - u32 lmt_case_cnt; - struct limit_vector_cfg *vector_cfg; - struct limit_value_cfg *value_cfg; -}; - /** * struct sde_mdss_cfg - information of MDSS HW * This is the main catalog data structure representing @@ -1571,9 +1534,6 @@ struct sde_mdss_cfg { u32 qdss_count; struct sde_qdss_cfg qdss[MAX_BLOCKS]; - u32 limit_count; - struct sde_limit_cfg limit_cfg[LIMIT_SUBBLK_COUNT_MAX]; - /* Add additional block data structures here */ struct sde_perf_cfg perf; From 4d8c732c47ff506588975c2904de20210bc80420 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Sat, 11 Apr 2020 21:58:08 -0400 Subject: [PATCH 2/2] disp: msm: sde: use sde_dt_props for parsing TOP properties Use the new helper for parsing TOP device node properties and reduce the code complexity by re-arranging the ordering of some conditional branching which simplifies the logic. Change-Id: I222bff6d1311f988c57f5f43e677dac4167fb7b9 Signed-off-by: Steve Cohen --- msm/sde/sde_hw_catalog.c | 203 ++++++++++++++++++--------------------- 1 file changed, 96 insertions(+), 107 deletions(-) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 95139ea04d4d..ccc0f82d8f05 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -3571,106 +3571,104 @@ end: return rc; } -static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, - bool prop_exists[SDE_PROP_MAX], struct sde_prop_value *prop_value) +static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg, + struct sde_dt_props *props) { - cfg->max_sspp_linewidth = PROP_VALUE_ACCESS(prop_value, - SSPP_LINEWIDTH, 0); - if (!prop_exists[SSPP_LINEWIDTH]) - cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH; + int i; - cfg->vig_sspp_linewidth = PROP_VALUE_ACCESS(prop_value, - VIG_SSPP_LINEWIDTH, 0); - if (!prop_exists[VIG_SSPP_LINEWIDTH]) - cfg->vig_sspp_linewidth = cfg->max_sspp_linewidth; + cfg->max_sspp_linewidth = props->exists[SSPP_LINEWIDTH] ? + PROP_VALUE_ACCESS(props->values, SSPP_LINEWIDTH, 0) : + DEFAULT_SDE_LINE_WIDTH; - cfg->scaling_linewidth = PROP_VALUE_ACCESS(prop_value, - SCALING_LINEWIDTH, 0); - if (!prop_exists[SCALING_LINEWIDTH]) - cfg->scaling_linewidth = cfg->vig_sspp_linewidth; + cfg->vig_sspp_linewidth = props->exists[VIG_SSPP_LINEWIDTH] ? + PROP_VALUE_ACCESS(props->values, VIG_SSPP_LINEWIDTH, + 0) : cfg->max_sspp_linewidth; - cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value, - MIXER_LINEWIDTH, 0); - if (!prop_exists[MIXER_LINEWIDTH]) - cfg->max_mixer_width = DEFAULT_SDE_LINE_WIDTH; + cfg->scaling_linewidth = props->exists[SCALING_LINEWIDTH] ? + PROP_VALUE_ACCESS(props->values, SCALING_LINEWIDTH, + 0) : cfg->vig_sspp_linewidth; - cfg->max_mixer_blendstages = PROP_VALUE_ACCESS(prop_value, - MIXER_BLEND, 0); - if (!prop_exists[MIXER_BLEND]) - cfg->max_mixer_blendstages = DEFAULT_SDE_MIXER_BLENDSTAGES; + cfg->max_wb_linewidth = props->exists[WB_LINEWIDTH] ? + PROP_VALUE_ACCESS(props->values, WB_LINEWIDTH, 0) : + DEFAULT_SDE_LINE_WIDTH; - cfg->max_wb_linewidth = PROP_VALUE_ACCESS(prop_value, WB_LINEWIDTH, 0); - if (!prop_exists[WB_LINEWIDTH]) - cfg->max_wb_linewidth = DEFAULT_SDE_LINE_WIDTH; + cfg->max_mixer_width = props->exists[MIXER_LINEWIDTH] ? + PROP_VALUE_ACCESS(props->values, MIXER_LINEWIDTH, 0) : + DEFAULT_SDE_LINE_WIDTH; - cfg->ubwc_version = SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(prop_value, - UBWC_VERSION, 0)); - if (!prop_exists[UBWC_VERSION]) - cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION; + cfg->max_mixer_blendstages = props->exists[MIXER_BLEND] ? + PROP_VALUE_ACCESS(props->values, MIXER_BLEND, 0) : + DEFAULT_SDE_MIXER_BLENDSTAGES; - cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value, - BANK_BIT, 0); - if (!prop_exists[BANK_BIT]) - cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT; + cfg->ubwc_version = props->exists[UBWC_VERSION] ? + SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(props->values, + UBWC_VERSION, 0)) : DEFAULT_SDE_UBWC_VERSION; + + cfg->mdp[0].highest_bank_bit = props->exists[BANK_BIT] ? + PROP_VALUE_ACCESS(props->values, BANK_BIT, 0) : + DEFAULT_SDE_HIGHEST_BANK_BIT; if (cfg->ubwc_version == SDE_HW_UBWC_VER_40 && of_fdt_get_ddrtype() == LP_DDR4_TYPE) cfg->mdp[0].highest_bank_bit = 0x02; - cfg->macrotile_mode = PROP_VALUE_ACCESS(prop_value, MACROTILE_MODE, 0); - if (!prop_exists[MACROTILE_MODE]) - cfg->macrotile_mode = DEFAULT_SDE_UBWC_MACROTILE_MODE; + cfg->macrotile_mode = props->exists[MACROTILE_MODE] ? + PROP_VALUE_ACCESS(props->values, MACROTILE_MODE, 0) : + DEFAULT_SDE_UBWC_MACROTILE_MODE; cfg->ubwc_bw_calc_version = - PROP_VALUE_ACCESS(prop_value, UBWC_BW_CALC_VERSION, 0); + PROP_VALUE_ACCESS(props->values, UBWC_BW_CALC_VERSION, 0); - cfg->mdp[0].ubwc_static = PROP_VALUE_ACCESS(prop_value, UBWC_STATIC, 0); - if (!prop_exists[UBWC_STATIC]) - cfg->mdp[0].ubwc_static = DEFAULT_SDE_UBWC_STATIC; + cfg->mdp[0].ubwc_static = props->exists[UBWC_STATIC] ? + PROP_VALUE_ACCESS(props->values, UBWC_STATIC, 0) : + DEFAULT_SDE_UBWC_STATIC; - cfg->mdp[0].ubwc_swizzle = PROP_VALUE_ACCESS(prop_value, - UBWC_SWIZZLE, 0); - if (!prop_exists[UBWC_SWIZZLE]) - cfg->mdp[0].ubwc_swizzle = DEFAULT_SDE_UBWC_SWIZZLE; + cfg->mdp[0].ubwc_swizzle = props->exists[UBWC_SWIZZLE] ? + PROP_VALUE_ACCESS(props->values, UBWC_SWIZZLE, 0) : + DEFAULT_SDE_UBWC_SWIZZLE; cfg->mdp[0].has_dest_scaler = - PROP_VALUE_ACCESS(prop_value, DEST_SCALER, 0); + PROP_VALUE_ACCESS(props->values, DEST_SCALER, 0); cfg->mdp[0].smart_panel_align_mode = - PROP_VALUE_ACCESS(prop_value, SMART_PANEL_ALIGN_MODE, 0); - return 0; + PROP_VALUE_ACCESS(props->values, SMART_PANEL_ALIGN_MODE, 0); + + if (props->exists[SEC_SID_MASK]) { + cfg->sec_sid_mask_count = props->counts[SEC_SID_MASK]; + for (i = 0; i < cfg->sec_sid_mask_count; i++) + cfg->sec_sid_mask[i] = PROP_VALUE_ACCESS(props->values, + SEC_SID_MASK, i); + } + + cfg->has_src_split = PROP_VALUE_ACCESS(props->values, SRC_SPLIT, 0); + cfg->has_dim_layer = PROP_VALUE_ACCESS(props->values, DIM_LAYER, 0); + cfg->has_idle_pc = PROP_VALUE_ACCESS(props->values, IDLE_PC, 0); + cfg->pipe_order_type = PROP_VALUE_ACCESS(props->values, + PIPE_ORDER_VERSION, 0); + cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0); } static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) { - int rc, i, dma_rc, len, prop_count[SDE_PROP_MAX]; - struct sde_prop_value *prop_value = NULL; - bool prop_exists[SDE_PROP_MAX]; + int rc = 0, dma_rc, len; + struct sde_dt_props *props; const char *type; u32 major_version; - if (!cfg) { - SDE_ERROR("invalid argument\n"); - return -EINVAL; - } - - prop_value = kzalloc(SDE_PROP_MAX * - sizeof(struct sde_prop_value), GFP_KERNEL); - if (!prop_value) - return -ENOMEM; - - rc = _validate_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count, - &len); - if (rc) - goto end; + props = sde_get_dt_props(np, SDE_PROP_MAX, sde_prop, + ARRAY_SIZE(sde_prop), &len); + if (IS_ERR(props)) + return PTR_ERR(props); + /* revalidate arrays not bound to off_count elements */ rc = _validate_dt_entry(np, &sde_prop[SEC_SID_MASK], 1, - &prop_count[SEC_SID_MASK], NULL); + &props->counts[SEC_SID_MASK], NULL); if (rc) goto end; - rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count, - prop_exists, prop_value); + /* update props with newly validated arrays */ + rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), props->counts, + props->exists, props->values); if (rc) goto end; @@ -3683,15 +3681,12 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) cfg->mdp_count = 1; cfg->mdp[0].id = MDP_TOP; snprintf(cfg->mdp[0].name, SDE_HW_BLK_NAME_LEN, "top_%u", - cfg->mdp[0].id - MDP_TOP); - cfg->mdp[0].base = PROP_VALUE_ACCESS(prop_value, SDE_OFF, 0); - cfg->mdp[0].len = PROP_VALUE_ACCESS(prop_value, SDE_LEN, 0); - if (!prop_exists[SDE_LEN]) - cfg->mdp[0].len = DEFAULT_SDE_HW_BLOCK_LEN; + cfg->mdp[0].id - MDP_TOP); + cfg->mdp[0].base = PROP_VALUE_ACCESS(props->values, SDE_OFF, 0); + cfg->mdp[0].len = props->exists[SDE_LEN] ? PROP_VALUE_ACCESS( + props->values, SDE_LEN, 0) : DEFAULT_SDE_HW_BLOCK_LEN; - rc = _sde_parse_prop_check(cfg, prop_exists, prop_value); - if (rc) - SDE_ERROR("sde parse property check failed\n"); + _sde_top_parse_dt_helper(cfg, props); major_version = SDE_HW_MAJOR(cfg->hwversion); if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500)) @@ -3712,33 +3707,34 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) if (rc) goto end; - if (prop_exists[SEC_SID_MASK]) { - cfg->sec_sid_mask_count = prop_count[SEC_SID_MASK]; - for (i = 0; i < cfg->sec_sid_mask_count; i++) - cfg->sec_sid_mask[i] = - PROP_VALUE_ACCESS(prop_value, SEC_SID_MASK, i); - } - rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type); - if (!rc && !strcmp(type, "qseedv3")) { - cfg->qseed_type = SDE_SSPP_SCALER_QSEED3; - } else if (!rc && !strcmp(type, "qseedv3lite")) { - cfg->qseed_type = SDE_SSPP_SCALER_QSEED3LITE; - } else if (!rc && !strcmp(type, "qseedv2")) { - cfg->qseed_type = SDE_SSPP_SCALER_QSEED2; - } else if (rc) { - SDE_DEBUG("invalid QSEED configuration\n"); + if (rc) { + SDE_DEBUG("invalid %s node in device tree: %d\n", + sde_prop[QSEED_TYPE].prop_name, rc); rc = 0; + } else if (!strcmp(type, "qseedv3")) { + cfg->qseed_type = SDE_SSPP_SCALER_QSEED3; + } else if (!strcmp(type, "qseedv3lite")) { + cfg->qseed_type = SDE_SSPP_SCALER_QSEED3LITE; + } else if (!strcmp(type, "qseedv2")) { + cfg->qseed_type = SDE_SSPP_SCALER_QSEED2; + } else { + SDE_DEBUG("Unknown type %s for property %s\n", type, + sde_prop[QSEED_TYPE].prop_name); } rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type); - if (!rc && !strcmp(type, "csc")) { - cfg->csc_type = SDE_SSPP_CSC; - } else if (!rc && !strcmp(type, "csc-10bit")) { - cfg->csc_type = SDE_SSPP_CSC_10BIT; - } else if (rc) { - SDE_DEBUG("invalid csc configuration\n"); + if (rc) { + SDE_DEBUG("invalid %s node in device tree: %d\n", + sde_prop[CSC_TYPE].prop_name, rc); rc = 0; + } else if (!strcmp(type, "csc")) { + cfg->csc_type = SDE_SSPP_CSC; + } else if (!strcmp(type, "csc-10bit")) { + cfg->csc_type = SDE_SSPP_CSC_10BIT; + } else { + SDE_DEBUG("Unknown type %s for property %s\n", type, + sde_prop[CSC_TYPE].prop_name); } /* @@ -3749,8 +3745,8 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) dma_rc = of_property_read_string(np, sde_prop[SMART_DMA_REV].prop_name, &type); if (dma_rc) { - SDE_DEBUG("invalid SMART_DMA_REV node in device tree: %d\n", - dma_rc); + SDE_DEBUG("invalid %s node in device tree: %d\n", + sde_prop[SMART_DMA_REV].prop_name, dma_rc); } else if (!strcmp(type, "smart_dma_v2p5")) { cfg->smart_dma_rev = SDE_SSPP_SMART_DMA_V2p5; } else if (!strcmp(type, "smart_dma_v2")) { @@ -3758,18 +3754,11 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) } else if (!strcmp(type, "smart_dma_v1")) { SDE_ERROR("smart dma 1.0 is not supported in SDE\n"); } else { - SDE_DEBUG("unknown smart dma version\n"); + SDE_DEBUG("unknown smart dma version %s\n", type); } - cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0); - cfg->has_dim_layer = PROP_VALUE_ACCESS(prop_value, DIM_LAYER, 0); - cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0); - cfg->pipe_order_type = PROP_VALUE_ACCESS(prop_value, - PIPE_ORDER_VERSION, 0); - cfg->has_base_layer = PROP_VALUE_ACCESS(prop_value, BASE_LAYER, 0); - end: - kfree(prop_value); + sde_put_dt_props(props); return rc; }