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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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sh: Add support for SH7721 CPU subtype.
Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
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commit
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19 changed files with 68 additions and 29 deletions
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@ -33,7 +33,8 @@
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720)
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define CCR3 0xa40000b4
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#define CCR_CACHE_16KB 0x00010000
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#define CCR_CACHE_32KB 0x00020000
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@ -2,7 +2,9 @@
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#define __ASM_CPU_SH3_DMA_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define SH_DMAC_BASE 0xa4010020
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#define DMTE0_IRQ 48
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@ -12,7 +12,8 @@
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#ifndef _CPU_SH3_GPIO_H
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#define _CPU_SH3_GPIO_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7720)
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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/* Control registers */
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#define PORT_PACR 0xA4050100UL
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@ -33,7 +33,8 @@
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defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7712) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720)
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
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#else
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#define INTEVT 0xffffffd8
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@ -23,12 +23,13 @@
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* ---------------------------------------------------------------------------
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*/
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_TOCR 0xfffffe90 /* Byte access */
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720)
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_012_TSTR 0xa412fe92 /* Byte access */
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#define TMU0_TCOR 0xa412fe94 /* Long access */
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@ -57,7 +58,7 @@
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#define TMU2_TCOR 0xfffffeac /* Long access */
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#define TMU2_TCNT 0xfffffeb0 /* Long access */
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#define TMU2_TCR 0xfffffeb4 /* Word access */
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU2_TCPR2 0xfffffeb8 /* Long access */
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#endif
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#endif
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@ -12,7 +12,8 @@
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#define __ASM_CPU_SH3_UBC_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720)
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define UBC_BARA 0xa4ffffb0
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#define UBC_BAMRA 0xa4ffffb4
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#define UBC_BBRA 0xa4ffffb8
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@ -23,7 +23,7 @@ enum cpu_type {
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
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CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
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CPU_SH7720, CPU_SH7729,
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CPU_SH7720, CPU_SH7721, CPU_SH7729,
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/* SH-4 types */
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CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
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