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ARM: dts: msm: Enable io-coherency for camera devices on Yupik
Enable io-coherency to avoid cache flush operations when a buffer generated by CPU module is given to a HW as input. CRs-Fixed: 2882101 Change-Id: Ib8720070cd7e907a077241d5f0ad72fb4df538dd
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1 changed files with 5 additions and 0 deletions
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@ -391,6 +391,7 @@
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<&apps_smmu 0xCE0 0x4E0>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
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dma-coherent-hint-cached;
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cam-smmu-label = "ife";
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multiple-client-devices;
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ife_iova_mem_map: iova-mem-map {
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@ -412,6 +413,7 @@
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cam-smmu-label = "jpeg";
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
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dma-coherent-hint-cached;
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jpeg_iova_mem_map: iova-mem-map {
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/* IO region is approximately 3.4 GB */
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iova-mem-region-io {
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@ -441,6 +443,7 @@
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cam-smmu-label = "icp";
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
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dma-coherent-hint-cached;
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iova-region-discard = <0xdff00000 0x300000>;
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icp_iova_mem_map: iova-mem-map {
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iova-mem-region-firmware {
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@ -498,6 +501,7 @@
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cam-smmu-label = "cpas-cdm";
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
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dma-coherent-hint-cached;
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cpas_cdm_iova_mem_map: iova-mem-map {
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iova-mem-region-io {
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/* IO region is approximately 3.4 GB */
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@ -523,6 +527,7 @@
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cam-smmu-label = "lrme";
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
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dma-coherent-hint-cached;
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lrme_iova_mem_map: iova-mem-map {
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iova-mem-region-shared {
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/* Shared region is 100MB long */
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