mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
ARM: SoC: driver updates for v4.2
Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses Conflicts: arch/arm64/boot/dts/arm/juno-motherboard.dtsi Trivial add/add conflict with our dt branch. Resolution: take both sides. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVi4RRAAoJEFk3GJrT+8ZljIcQAIsqxM/o0drd90xTJ6ex9h0B RmqVLTDgesHmBacJ+SBsa9/ybFIM1uErByftc1dmKankEQVXW3wcH7keQnoStPT2 zTEjadHgZ/ARYjV/oG5oohjfDZpO1kECVHL8O8RmcWxgzRB3az1IW2eD+dzrga/Y R7K6D8rDHMADIUmv0e0DzvQEbSUYdCx3rBND1qZznwZDP3NoivLkOG5MTraccLbQ ouCRoZtyNYD5Lxk+BHLBepnxAa0Ggc6IjEmiUv8fF2OYdu0OruMliT4rcAtOSmzg 2Y7pP85h8u0CxbJDkOyc+2BELyKo7Hv97XtDNNbRYABTMXdskRIadXt4Sh4mwFtM nvlhB4ovbIX7noECJToEkSAgmStLSUwA3R6+DVdLbeQY4uSuXuTRhiWHMyQB6va9 CdjJDk2RE0dZ77c5ZoUnUDtBe4cULU/n4agpYkKMf/HcpnqMUwZzP4KZbbPMBpgL 0CVTt3YrEcjoU7g0SFHhOGPSgl4yIXKU2eHEscokyFYLrS5zRWepmUEmlSoaWn+W p7pJE65TvOGf2xbaWI+UBeK/3ZG7XAP8qUfhsi7NS4bV6oFCk/foqsWAuru0H7OW 2Gk8fuF0qLgE1eFWQp8BHZ4IUeytoWbnGhhHXh8zH39SKAVncOiAGDNfuEP9CyXJ fZFfruYrnz2emOwj2v9m =02Gm -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' into test-merge ARM: SoC: driver updates for v4.2 Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses Conflicts: arch/arm64/boot/dts/arm/juno-motherboard.dtsi Trivial add/add conflict with our dt branch. Resolution: take both sides. # gpg: Signature made Wed Jun 24 21:32:17 2015 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <[email protected]>" # gpg: aka "Kevin Hilman <[email protected]>" # gpg: aka "Kevin Hilman <[email protected]>" # Conflicts: # arch/arm64/boot/dts/arm/juno-motherboard.dtsi
This commit is contained in:
Kevin Hilman
commit
32270e805a
57 changed files with 4966 additions and 1067 deletions
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@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
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source "drivers/soc/mediatek/Kconfig"
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source "drivers/soc/qcom/Kconfig"
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source "drivers/soc/sunxi/Kconfig"
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source "drivers/soc/ti/Kconfig"
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source "drivers/soc/versatile/Kconfig"
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@ -4,6 +4,7 @@
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_QCOM) += qcom/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_SOC_TI) += ti/
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obj-$(CONFIG_PLAT_VERSATILE) += versatile/
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@ -10,3 +10,10 @@ config QCOM_GSBI
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functions for connecting the underlying serial UART, SPI, and I2C
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devices to the output pins.
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config QCOM_PM
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bool "Qualcomm Power Management"
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depends on ARCH_QCOM && !ARM64
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help
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QCOM Platform specific power driver to manage cores and L2 low power
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modes. It interface with various system drivers to put the cores in
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low power modes.
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@ -1 +1,2 @@
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obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
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obj-$(CONFIG_QCOM_PM) += spm.o
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385
drivers/soc/qcom/spm.c
Normal file
385
drivers/soc/qcom/spm.c
Normal file
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@ -0,0 +1,385 @@
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/*
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* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2015, Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/qcom_scm.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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enum pm_sleep_mode {
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PM_SLEEP_MODE_STBY,
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PM_SLEEP_MODE_RET,
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PM_SLEEP_MODE_SPC,
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PM_SLEEP_MODE_PC,
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PM_SLEEP_MODE_NR,
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};
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_SPM_STS,
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SPM_REG_PMIC_STS,
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SPM_REG_NR,
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};
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struct spm_reg_data {
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const u8 *reg_offset;
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u32 spm_cfg;
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u32 spm_dly;
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u32 pmic_dly;
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u32 pmic_data[MAX_PMIC_DATA];
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u8 seq[MAX_SEQ_DATA];
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u8 start_index[PM_SLEEP_MODE_NR];
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};
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struct spm_driver_data {
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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};
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static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8064 */
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
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typedef int (*idle_fn)(int);
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static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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static void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static int qcom_pm_collapse(unsigned long int unused)
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{
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qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
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/*
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* Returns here only if there was a pending interrupt and we did not
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* power down as a result.
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*/
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return -1;
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}
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static int qcom_cpu_spc(int cpu)
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{
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int ret;
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struct spm_driver_data *drv = per_cpu(cpu_spm_drv, cpu);
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
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ret = cpu_suspend(0, qcom_pm_collapse);
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/*
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* ARM common code executes WFI without calling into our driver and
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* if the SPM mode is not reset, then we may accidently power down the
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* cpu when we intended only to gate the cpu clock.
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* Ensure the state is set to standby before returning.
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*/
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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return ret;
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}
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static int qcom_idle_enter(int cpu, unsigned long index)
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{
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return per_cpu(qcom_idle_ops, cpu)[index](cpu);
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}
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static const struct of_device_id qcom_idle_state_match[] __initconst = {
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{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
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{ },
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};
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static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
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{
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const struct of_device_id *match_id;
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struct device_node *state_node;
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int i;
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int state_count = 1;
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idle_fn idle_fns[CPUIDLE_STATE_MAX];
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idle_fn *fns;
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cpumask_t mask;
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bool use_scm_power_down = false;
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for (i = 0; ; i++) {
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state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
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if (!state_node)
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break;
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if (!of_device_is_available(state_node))
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continue;
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if (i == CPUIDLE_STATE_MAX) {
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pr_warn("%s: cpuidle states reached max possible\n",
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__func__);
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break;
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}
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match_id = of_match_node(qcom_idle_state_match, state_node);
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if (!match_id)
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return -ENODEV;
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idle_fns[state_count] = match_id->data;
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/* Check if any of the states allow power down */
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if (match_id->data == qcom_cpu_spc)
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use_scm_power_down = true;
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state_count++;
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}
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if (state_count == 1)
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goto check_spm;
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fns = devm_kcalloc(get_cpu_device(cpu), state_count, sizeof(*fns),
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GFP_KERNEL);
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if (!fns)
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return -ENOMEM;
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for (i = 1; i < state_count; i++)
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fns[i] = idle_fns[i];
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if (use_scm_power_down) {
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/* We have atleast one power down mode */
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cpumask_clear(&mask);
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cpumask_set_cpu(cpu, &mask);
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qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
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}
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per_cpu(qcom_idle_ops, cpu) = fns;
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/*
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* SPM probe for the cpu should have happened by now, if the
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* SPM device does not exist, return -ENXIO to indicate that the
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* cpu does not support idle states.
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*/
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check_spm:
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return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
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}
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static struct cpuidle_ops qcom_cpuidle_ops __initdata = {
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.suspend = qcom_idle_enter,
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.init = qcom_cpuidle_init,
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};
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
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static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
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int *spm_cpu)
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{
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struct spm_driver_data *drv = NULL;
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struct device_node *cpu_node, *saw_node;
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int cpu;
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bool found;
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for_each_possible_cpu(cpu) {
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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found = (saw_node == pdev->dev.of_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (found)
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break;
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}
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if (found) {
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
|
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if (drv)
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*spm_cpu = cpu;
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}
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return drv;
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}
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static const struct of_device_id spm_match_table[] = {
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{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
|
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.data = &spm_reg_8064_cpu },
|
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{ },
|
||||
};
|
||||
|
||||
static int spm_dev_probe(struct platform_device *pdev)
|
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{
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struct spm_driver_data *drv;
|
||||
struct resource *res;
|
||||
const struct of_device_id *match_id;
|
||||
void __iomem *addr;
|
||||
int cpu;
|
||||
|
||||
drv = spm_get_drv(pdev, &cpu);
|
||||
if (!drv)
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(drv->reg_base))
|
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return PTR_ERR(drv->reg_base);
|
||||
|
||||
match_id = of_match_node(spm_match_table, pdev->dev.of_node);
|
||||
if (!match_id)
|
||||
return -ENODEV;
|
||||
|
||||
drv->reg_data = match_id->data;
|
||||
|
||||
/* Write the SPM sequences first.. */
|
||||
addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
|
||||
__iowrite32_copy(addr, drv->reg_data->seq,
|
||||
ARRAY_SIZE(drv->reg_data->seq) / 4);
|
||||
|
||||
/*
|
||||
* ..and then the control registers.
|
||||
* On some SoC if the control registers are written first and if the
|
||||
* CPU was held in reset, the reset signal could trigger the SPM state
|
||||
* machine, before the sequences are completely written.
|
||||
*/
|
||||
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
|
||||
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
|
||||
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
|
||||
spm_register_write(drv, SPM_REG_PMIC_DATA_0,
|
||||
drv->reg_data->pmic_data[0]);
|
||||
spm_register_write(drv, SPM_REG_PMIC_DATA_1,
|
||||
drv->reg_data->pmic_data[1]);
|
||||
|
||||
/* Set up Standby as the default low power mode */
|
||||
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
||||
|
||||
per_cpu(cpu_spm_drv, cpu) = drv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver spm_driver = {
|
||||
.probe = spm_dev_probe,
|
||||
.driver = {
|
||||
.name = "saw",
|
||||
.of_match_table = spm_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(spm_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("SAW power controller driver");
|
||||
MODULE_ALIAS("platform:saw");
|
||||
10
drivers/soc/sunxi/Kconfig
Normal file
10
drivers/soc/sunxi/Kconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# Allwinner sunXi SoC drivers
|
||||
#
|
||||
config SUNXI_SRAM
|
||||
bool
|
||||
default ARCH_SUNXI
|
||||
help
|
||||
Say y here to enable the SRAM controller support. This
|
||||
device is responsible on mapping the SRAM in the sunXi SoCs
|
||||
whether to the CPU/DMA, or to the devices.
|
||||
1
drivers/soc/sunxi/Makefile
Normal file
1
drivers/soc/sunxi/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o
|
||||
284
drivers/soc/sunxi/sunxi_sram.c
Normal file
284
drivers/soc/sunxi/sunxi_sram.c
Normal file
|
|
@ -0,0 +1,284 @@
|
|||
/*
|
||||
* Allwinner SoCs SRAM Controller Driver
|
||||
*
|
||||
* Copyright (C) 2015 Maxime Ripard
|
||||
*
|
||||
* Author: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/soc/sunxi/sunxi_sram.h>
|
||||
|
||||
struct sunxi_sram_func {
|
||||
char *func;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
struct sunxi_sram_data {
|
||||
char *name;
|
||||
u8 reg;
|
||||
u8 offset;
|
||||
u8 width;
|
||||
struct sunxi_sram_func *func;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct sunxi_sram_desc {
|
||||
struct sunxi_sram_data data;
|
||||
bool claimed;
|
||||
};
|
||||
|
||||
#define SUNXI_SRAM_MAP(_val, _func) \
|
||||
{ \
|
||||
.func = _func, \
|
||||
.val = _val, \
|
||||
}
|
||||
|
||||
#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.offset = _off, \
|
||||
.width = _width, \
|
||||
.func = (struct sunxi_sram_func[]){ \
|
||||
__VA_ARGS__, { } }, \
|
||||
}
|
||||
|
||||
static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
|
||||
.data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
|
||||
SUNXI_SRAM_MAP(0, "cpu"),
|
||||
SUNXI_SRAM_MAP(1, "emac")),
|
||||
};
|
||||
|
||||
static struct sunxi_sram_desc sun4i_a10_sram_d = {
|
||||
.data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
|
||||
SUNXI_SRAM_MAP(0, "cpu"),
|
||||
SUNXI_SRAM_MAP(1, "usb-otg")),
|
||||
};
|
||||
|
||||
static const struct of_device_id sunxi_sram_dt_ids[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun4i-a10-sram-a3-a4",
|
||||
.data = &sun4i_a10_sram_a3_a4.data,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun4i-a10-sram-d",
|
||||
.data = &sun4i_a10_sram_d.data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct device *sram_dev;
|
||||
static LIST_HEAD(claimed_sram);
|
||||
static DEFINE_SPINLOCK(sram_lock);
|
||||
static void __iomem *base;
|
||||
|
||||
static int sunxi_sram_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct device_node *sram_node, *section_node;
|
||||
const struct sunxi_sram_data *sram_data;
|
||||
const struct of_device_id *match;
|
||||
struct sunxi_sram_func *func;
|
||||
const __be32 *sram_addr_p, *section_addr_p;
|
||||
u32 val;
|
||||
|
||||
seq_puts(s, "Allwinner sunXi SRAM\n");
|
||||
seq_puts(s, "--------------------\n\n");
|
||||
|
||||
for_each_child_of_node(sram_dev->of_node, sram_node) {
|
||||
sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
|
||||
|
||||
seq_printf(s, "sram@%08x\n",
|
||||
be32_to_cpu(*sram_addr_p));
|
||||
|
||||
for_each_child_of_node(sram_node, section_node) {
|
||||
match = of_match_node(sunxi_sram_dt_ids, section_node);
|
||||
if (!match)
|
||||
continue;
|
||||
sram_data = match->data;
|
||||
|
||||
section_addr_p = of_get_address(section_node, 0,
|
||||
NULL, NULL);
|
||||
|
||||
seq_printf(s, "\tsection@%04x\t(%s)\n",
|
||||
be32_to_cpu(*section_addr_p),
|
||||
sram_data->name);
|
||||
|
||||
val = readl(base + sram_data->reg);
|
||||
val >>= sram_data->offset;
|
||||
val &= sram_data->width;
|
||||
|
||||
for (func = sram_data->func; func->func; func++) {
|
||||
seq_printf(s, "\t\t%s%c\n", func->func,
|
||||
func->val == val ? '*' : ' ');
|
||||
}
|
||||
}
|
||||
|
||||
seq_puts(s, "\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sunxi_sram_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, sunxi_sram_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations sunxi_sram_fops = {
|
||||
.open = sunxi_sram_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
|
||||
{
|
||||
return container_of(data, struct sunxi_sram_desc, data);
|
||||
}
|
||||
|
||||
static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
|
||||
unsigned int *value)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct of_phandle_args args;
|
||||
int ret;
|
||||
|
||||
ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
|
||||
&args);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
if (!of_device_is_available(args.np)) {
|
||||
ret = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (value)
|
||||
*value = args.args[0];
|
||||
|
||||
match = of_match_node(sunxi_sram_dt_ids, args.np);
|
||||
if (!match) {
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
of_node_put(args.np);
|
||||
return match->data;
|
||||
|
||||
err:
|
||||
of_node_put(args.np);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
int sunxi_sram_claim(struct device *dev)
|
||||
{
|
||||
const struct sunxi_sram_data *sram_data;
|
||||
struct sunxi_sram_desc *sram_desc;
|
||||
unsigned int device;
|
||||
u32 val, mask;
|
||||
|
||||
if (IS_ERR(base))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
if (!dev || !dev->of_node)
|
||||
return -EINVAL;
|
||||
|
||||
sram_data = sunxi_sram_of_parse(dev->of_node, &device);
|
||||
if (IS_ERR(sram_data))
|
||||
return PTR_ERR(sram_data);
|
||||
|
||||
sram_desc = to_sram_desc(sram_data);
|
||||
|
||||
spin_lock(&sram_lock);
|
||||
|
||||
if (sram_desc->claimed) {
|
||||
spin_unlock(&sram_lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
mask = GENMASK(sram_data->offset + sram_data->width, sram_data->offset);
|
||||
val = readl(base + sram_data->reg);
|
||||
val &= ~mask;
|
||||
writel(val | ((device << sram_data->offset) & mask),
|
||||
base + sram_data->reg);
|
||||
|
||||
spin_unlock(&sram_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(sunxi_sram_claim);
|
||||
|
||||
int sunxi_sram_release(struct device *dev)
|
||||
{
|
||||
const struct sunxi_sram_data *sram_data;
|
||||
struct sunxi_sram_desc *sram_desc;
|
||||
|
||||
if (!dev || !dev->of_node)
|
||||
return -EINVAL;
|
||||
|
||||
sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
|
||||
if (IS_ERR(sram_data))
|
||||
return -EINVAL;
|
||||
|
||||
sram_desc = to_sram_desc(sram_data);
|
||||
|
||||
spin_lock(&sram_lock);
|
||||
sram_desc->claimed = false;
|
||||
spin_unlock(&sram_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(sunxi_sram_release);
|
||||
|
||||
static int sunxi_sram_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct dentry *d;
|
||||
|
||||
sram_dev = &pdev->dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
||||
|
||||
d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
|
||||
&sunxi_sram_fops);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id sunxi_sram_dt_match[] = {
|
||||
{ .compatible = "allwinner,sun4i-a10-sram-controller" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
|
||||
|
||||
static struct platform_driver sunxi_sram_driver = {
|
||||
.driver = {
|
||||
.name = "sunxi-sram",
|
||||
.of_match_table = sunxi_sram_dt_match,
|
||||
},
|
||||
.probe = sunxi_sram_probe,
|
||||
};
|
||||
module_platform_driver(sunxi_sram_driver);
|
||||
|
||||
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
|
||||
MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -28,8 +28,15 @@
|
|||
#define APBMISC_SIZE 0x64
|
||||
#define FUSE_SKU_INFO 0x10
|
||||
|
||||
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
|
||||
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
|
||||
(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
|
||||
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
|
||||
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
|
||||
|
||||
static void __iomem *apbmisc_base;
|
||||
static void __iomem *strapping_base;
|
||||
static bool long_ram_code;
|
||||
|
||||
u32 tegra_read_chipid(void)
|
||||
{
|
||||
|
|
@ -54,6 +61,18 @@ u32 tegra_read_straps(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
u32 tegra_read_ram_code(void)
|
||||
{
|
||||
u32 straps = tegra_read_straps();
|
||||
|
||||
if (long_ram_code)
|
||||
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
|
||||
else
|
||||
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
|
||||
|
||||
return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
|
||||
}
|
||||
|
||||
static const struct of_device_id apbmisc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-apbmisc", },
|
||||
{},
|
||||
|
|
@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void)
|
|||
strapping_base = of_iomap(np, 1);
|
||||
if (!strapping_base)
|
||||
pr_err("ioremap tegra strapping_base failed\n");
|
||||
|
||||
long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue