From 327a03e9f9e0aee9a12ed046ed22fb989fbe58ae Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 7 May 2021 15:09:54 +0530 Subject: [PATCH] ARM: dts: msm: Update clock handles for PCIE nodes GCC_PCIE_REF_CLK_EN is not applicable to PCIe 2nd instance and hence update it correctly. Also update missing clock handle for PCIe 1st instance. Change-Id: I8303e80c0dda09a51dca4a99fa57923a874d8c8f --- qcom/yupik-pcie.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 557d9d49725f..83133d79f313 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -79,10 +79,11 @@ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, <&pcie_0_pipe_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", @@ -92,6 +93,7 @@ "pcie_ddrss_sf_tbu_clk", "pcie_aggre_noc_0_axi_clk", "pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_pipe_clk_ext_src"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>, @@ -347,7 +349,7 @@ <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,