From 51e6d361f3d0e270ce8aff49027eb030a2f58866 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 19 Nov 2020 18:53:11 -0800 Subject: [PATCH 1/4] ARM: dts: msm: add number of PARF testbus selectors for lahaina When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on lahaina. Change-Id: I6026679298f0be09dbf9871129dc329731febeb5 --- qcom/lahaina-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..4bf919cc1da9 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -109,6 +109,7 @@ qcom,l1-2-th-value = <70>; qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <10100>; qcom,phy-status-offset = <0x214>; @@ -335,6 +336,7 @@ qcom,no-l0s-supported; qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <1106>; qcom,phy-status-offset = <0x214>; From 31f85250156b78daeca5c6e0421144de50cdf507 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:28:40 -0800 Subject: [PATCH 2/4] ARM: dts: msm: add number of PARF testbus selectors for sdxlemur When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on sdxlemur. Change-Id: I5e903983830bb5a51ebde2606d37a8dc2ad80d8a --- qcom/sdxlemur-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 8df0c684343a..c625387e4b4f 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -94,6 +94,7 @@ qcom,aux-clk-freq = <17>; /* 16.6 MHz */ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <1102>; qcom,phy-status-offset = <0x1214>; From e8c94dac6247f968ee7f1c0fb6b56cfb115b2813 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:29:59 -0800 Subject: [PATCH 3/4] ARM: dts: msm: add number of PARF testbus selectors for shima When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on shima. Change-Id: Iadd31d7e2fadd1c55655d40e35eb3caa4c055cd8 --- qcom/shima-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fce90dee366f..b6f3875e59fe 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -105,6 +105,7 @@ qcom,l1-2-th-value = <70>; qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; From 4fcbaf710b5ab2ff2b1542874fbe1d244f8f0956 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:37:15 -0800 Subject: [PATCH 4/4] dt-bindings: arm: msm: add entry for number of PARF testbus selectors The number of PCIe PARF testbus signals available varies for each PCIe controller version. Add entry to specify how many PCIe PARF testbus selectors are available. Change-Id: I58d94c99f65c1b9fb7e37ca102a60e71a9f0c1aa --- bindings/pci/pci-msm.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 6c6285f4e714..359461341214 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -341,6 +341,12 @@ interconnects: de-asserted. This guarantees the 100MHz clock is available for the PCIe devices +- qcom,num-parf-testbus-sel: + Usage: optional + Value type: + Definition: Defines the number of testbus selectors available for PARF + for a given PCIe controller. + - qcom,switch-latency: Usage: optional Definition: The latency(ms) between when PCIe link is up and before @@ -526,6 +532,7 @@ Example qcom,perst-delay-us-min = <10>; qcom,perst-delay-us-max = <15>; qcom,ep-latency = <20>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,switch-latency = <25>; qcom,eq-pset-req-vec = <0>;