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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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The i.MX SoC update for 3.19:
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
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Merge tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Pull "The i.MX SoC update for 3.19" from Shawn Guo
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
* tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
ARM: imx: clk-vf610: get input clocks from assigned clocks
ARM: imx: Add Freescale LS1021A SMP support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx53: add cpufreq support
ARM: imx53: clk: add ARM clock
ARM: imx: add CPU clock type
ARM: imx5: add step clock, used when reprogramming PLL1
ARM: imx: add enet init for i.mx6sx
ARM: imx6sx: add imx6sx iomux-gpr field define
ARM: vf610: Add ARM Global Timer clocksource option
ARM: imx: add anatop settings for LPDDR2 when enter DSM mode
ARM: imx: replace cpu type check with ddr type check
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
Signed-off-by; Arnd Bergmann <[email protected]>
This commit is contained in:
Arnd Bergmann
commit
32e049ad79
25 changed files with 611 additions and 75 deletions
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@ -198,6 +198,9 @@
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#define IMX5_CLK_OCRAM 186
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#define IMX5_CLK_SAHARA_IPG_GATE 187
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#define IMX5_CLK_SATA_REF 188
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#define IMX5_CLK_END 189
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#define IMX5_CLK_STEP_SEL 189
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#define IMX5_CLK_CPU_PODF_SEL 190
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#define IMX5_CLK_ARM 191
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#define IMX5_CLK_END 192
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#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
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@ -21,24 +21,24 @@
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#define VF610_CLK_FASK_CLK_SEL 8
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#define VF610_CLK_AUDIO_EXT 9
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#define VF610_CLK_ENET_EXT 10
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#define VF610_CLK_PLL1_MAIN 11
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#define VF610_CLK_PLL1_SYS 11
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#define VF610_CLK_PLL1_PFD1 12
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#define VF610_CLK_PLL1_PFD2 13
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#define VF610_CLK_PLL1_PFD3 14
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#define VF610_CLK_PLL1_PFD4 15
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#define VF610_CLK_PLL2_MAIN 16
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#define VF610_CLK_PLL2_BUS 16
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#define VF610_CLK_PLL2_PFD1 17
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#define VF610_CLK_PLL2_PFD2 18
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#define VF610_CLK_PLL2_PFD3 19
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#define VF610_CLK_PLL2_PFD4 20
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#define VF610_CLK_PLL3_MAIN 21
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#define VF610_CLK_PLL3_USB_OTG 21
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#define VF610_CLK_PLL3_PFD1 22
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#define VF610_CLK_PLL3_PFD2 23
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#define VF610_CLK_PLL3_PFD3 24
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#define VF610_CLK_PLL3_PFD4 25
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#define VF610_CLK_PLL4_MAIN 26
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#define VF610_CLK_PLL5_MAIN 27
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#define VF610_CLK_PLL6_MAIN 28
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#define VF610_CLK_PLL4_AUDIO 26
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#define VF610_CLK_PLL5_ENET 27
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#define VF610_CLK_PLL6_VIDEO 28
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#define VF610_CLK_PLL3_MAIN_DIV 29
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#define VF610_CLK_PLL4_MAIN_DIV 30
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#define VF610_CLK_PLL6_MAIN_DIV 31
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@ -166,9 +166,32 @@
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#define VF610_CLK_DMAMUX3 153
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#define VF610_CLK_FLEXCAN0_EN 154
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#define VF610_CLK_FLEXCAN1_EN 155
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#define VF610_CLK_PLL7_MAIN 156
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#define VF610_CLK_PLL7_USB_HOST 156
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#define VF610_CLK_USBPHY0 157
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#define VF610_CLK_USBPHY1 158
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#define VF610_CLK_END 159
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#define VF610_CLK_LVDS1_IN 159
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#define VF610_CLK_ANACLK1 160
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#define VF610_CLK_PLL1_BYPASS_SRC 161
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#define VF610_CLK_PLL2_BYPASS_SRC 162
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#define VF610_CLK_PLL3_BYPASS_SRC 163
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#define VF610_CLK_PLL4_BYPASS_SRC 164
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#define VF610_CLK_PLL5_BYPASS_SRC 165
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#define VF610_CLK_PLL6_BYPASS_SRC 166
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#define VF610_CLK_PLL7_BYPASS_SRC 167
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#define VF610_CLK_PLL1 168
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#define VF610_CLK_PLL2 169
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#define VF610_CLK_PLL3 170
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#define VF610_CLK_PLL4 171
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#define VF610_CLK_PLL5 172
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#define VF610_CLK_PLL6 173
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#define VF610_CLK_PLL7 174
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#define VF610_PLL1_BYPASS 175
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#define VF610_PLL2_BYPASS 176
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#define VF610_PLL3_BYPASS 177
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#define VF610_PLL4_BYPASS 178
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#define VF610_PLL5_BYPASS 179
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#define VF610_PLL6_BYPASS 180
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#define VF610_PLL7_BYPASS 181
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#define VF610_CLK_END 182
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#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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