From e7c6b736ca2d6ac0be947702a75fc7439f046950 Mon Sep 17 00:00:00 2001 From: Raghu Ananya Arabolu Date: Tue, 14 Apr 2020 13:14:17 -0700 Subject: [PATCH] msm: kgsl: Modify CP_LPAC_PROG_FIFO_SIZE register value for A660 Set the memPoolSize field of CP_LPAC_PROG_FIFO_SIZE register to 32. memPoolSize is the number of entries in the LPAC Programming Fifo which replaces the MVC in the CP AC subsystem. Change-Id: I0d52a07309ce28c231ee3c06f1347a99d3b0391d Signed-off-by: Raghu Ananya Arabolu --- drivers/gpu/msm/adreno_a6xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index e6b5b2de34fc..a318f24fa751 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -482,7 +482,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 0x00800060); kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_1, 0x40202016); - kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000080); + kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); } if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {