diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index 0ffe65234e1b..371f618c038d 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -145,7 +145,7 @@ /* GDSCs in DISPCC */ disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0xaf03000 0x4>; regulator-name = "disp_cc_mdss_core_gdsc"; proxy-supply = <&disp_cc_mdss_core_gdsc>; diff --git a/qcom/shima-rumi.dtsi b/qcom/shima-rumi.dtsi index 396729b5d2b6..e202c0d85389 100644 --- a/qcom/shima-rumi.dtsi +++ b/qcom/shima-rumi.dtsi @@ -155,7 +155,7 @@ }; &camcc { - clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; }; &debugcc { @@ -163,10 +163,15 @@ }; &videocc { - clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; }; &gpucc { clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; +}; + +&dispcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index a274fc669376..62d65690afad 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -695,15 +695,21 @@ vdd_mx-supply = <&VDD_MXA_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; - dispcc: qcom,dispcc@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + dispcc: clock-controller@af00000 { + compatible = "qcom,shima-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "gcc_disp_gpll0_clk_src", + "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -715,9 +721,9 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; + "gcc_gpu_gpll0_div_clk_src", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -729,18 +735,31 @@ vdd_mx-supply = <&VDD_MXA_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90ba000 { + compatible = "syscon"; + reg = <0x90ba000 0x54>; + }; + debugcc: debug-clock-controller@0 { compatible = "qcom,shima-debugcc"; qcom,gcc = <&gcc>; qcom,videocc = <&videocc>; qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; qcom,gpucc = <&gpucc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo_clk_src"; #clock-cells = <1>; @@ -2342,12 +2361,16 @@ }; &cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_bps_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; @@ -2355,24 +2378,32 @@ }; &cam_cc_ife_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; @@ -2380,6 +2411,8 @@ }; &disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; @@ -2387,18 +2420,24 @@ }; &gpu_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gpu_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_GFX_LEVEL>; vdd_parent-supply = <&VDD_GFX_LEVEL>; status = "ok"; }; &video_cc_mvs0_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; @@ -2406,12 +2445,16 @@ }; &video_cc_mvs0c_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &video_cc_mvs1_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; @@ -2419,6 +2462,8 @@ }; &video_cc_mvs1c_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; status = "ok";