From 6d9ab208c5e3b95d7219a527952def213963e041 Mon Sep 17 00:00:00 2001 From: Chris Ye Date: Thu, 29 Oct 2020 12:38:00 -0700 Subject: [PATCH 01/12] FROMGIT: Input: Add devices for HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE Kernel 5.4 introduces HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE, devices need to be set explicitly with this flag. Bug: 170072925 Bug: 170126889 Tests: atest android.hardware.input.cts.tests (cherry picked from commit f59ee399de4a8ca4d7d19cdcabb4b63e94867f09 https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git for-5.10/upstream-fixes) Signed-off-by: Chris Ye Change-Id: I65742e96babc59adde0ab32656850ef4f164ac3e --- drivers/hid/hid-ids.h | 4 ++++ drivers/hid/hid-quirks.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index bd1dc3194a51..8e2b155d5d24 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -449,6 +449,10 @@ #define USB_VENDOR_ID_FRUCTEL 0x25B6 #define USB_DEVICE_ID_GAMETEL_MT_MODE 0x0002 +#define USB_VENDOR_ID_GAMEVICE 0x27F8 +#define USB_DEVICE_ID_GAMEVICE_GV186 0x0BBE +#define USB_DEVICE_ID_GAMEVICE_KISHI 0x0BBF + #define USB_VENDOR_ID_GAMERON 0x0810 #define USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR 0x0001 #define USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR 0x0002 diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index a49fa2b047cb..d34c31721713 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -84,6 +84,10 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_FREESCALE, USB_DEVICE_ID_FREESCALE_MX28), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_FUTABA, USB_DEVICE_ID_LED_DISPLAY), HID_QUIRK_NO_INIT_REPORTS }, { HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, USB_DEVICE_ID_GREENASIA_DUAL_USB_JOYPAD), HID_QUIRK_MULTI_INPUT }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_GAMEVICE, USB_DEVICE_ID_GAMEVICE_GV186), + HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, + { HID_USB_DEVICE(USB_VENDOR_ID_GAMEVICE, USB_DEVICE_ID_GAMEVICE_KISHI), + HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, { HID_USB_DEVICE(USB_VENDOR_ID_HAPP, USB_DEVICE_ID_UGCI_DRIVING), HID_QUIRK_BADPAD | HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_HAPP, USB_DEVICE_ID_UGCI_FIGHTING), HID_QUIRK_BADPAD | HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_HAPP, USB_DEVICE_ID_UGCI_FLYING), HID_QUIRK_BADPAD | HID_QUIRK_MULTI_INPUT }, From 37201331c48dc7071c3366a216ecd114a836bd74 Mon Sep 17 00:00:00 2001 From: Deeksha Gupta Date: Wed, 18 Nov 2020 10:53:08 +0530 Subject: [PATCH 02/12] ANDROID: ABI: Update allowed list for QCOM Leaf changes summary: 1 artifact changed Changed leaf types summary: 0 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 1 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 1 Added function: [A] 'function void cfg80211_stop_iface(wiphy*, wireless_dev*, gfp_t)' Bug: 173561495 Signed-off-by: Deeksha Gupta Change-Id: I8197af49fd23443631b8845859f88e6bfa363ad1 --- android/abi_gki_aarch64.xml | 289 +++++++++++++++++------------------ android/abi_gki_aarch64_qcom | 1 + 2 files changed, 143 insertions(+), 147 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 23ebcfe434ba..599c5c28ba4c 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -566,6 +566,7 @@ + @@ -4687,7 +4688,6 @@ - @@ -15459,6 +15459,20 @@ + + + + + + + + + + + + + + @@ -23257,6 +23271,14 @@ + + + + + + + + @@ -31610,6 +31632,7 @@ + @@ -31665,7 +31688,7 @@ - + @@ -31898,7 +31921,7 @@ - + @@ -32196,7 +32219,7 @@ - + @@ -34809,7 +34832,7 @@ - + @@ -35321,7 +35344,7 @@ - + @@ -35593,7 +35616,7 @@ - + @@ -36689,7 +36712,7 @@ - + @@ -37089,7 +37112,7 @@ - + @@ -37151,7 +37174,6 @@ - @@ -37260,6 +37282,14 @@ + + + + + + + + @@ -37728,7 +37758,7 @@ - + @@ -38266,14 +38296,6 @@ - - - - - - - - @@ -48808,7 +48830,7 @@ - + @@ -49321,7 +49343,7 @@ - + @@ -49445,7 +49467,7 @@ - + @@ -49954,7 +49976,7 @@ - + @@ -50018,7 +50040,7 @@ - + @@ -50075,7 +50097,7 @@ - + @@ -50214,7 +50236,7 @@ - + @@ -50245,7 +50267,7 @@ - + @@ -50256,7 +50278,7 @@ - + @@ -50515,7 +50537,7 @@ - + @@ -50534,7 +50556,7 @@ - + @@ -50571,7 +50593,7 @@ - + @@ -50695,7 +50717,7 @@ - + @@ -50716,7 +50738,7 @@ - + @@ -50753,7 +50775,7 @@ - + @@ -50847,7 +50869,7 @@ - + @@ -50906,7 +50928,7 @@ - + @@ -57244,17 +57266,6 @@ - - - - - - - - - - - @@ -72165,6 +72176,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -78104,14 +78139,6 @@ - - - - - - - - @@ -80595,17 +80622,6 @@ - - - - - - - - - - - @@ -89447,6 +89463,17 @@ + + + + + + + + + + + @@ -89662,16 +89689,6 @@ - - - - - - - - - - @@ -90918,7 +90935,7 @@ - + @@ -90932,7 +90949,7 @@ - + @@ -90944,17 +90961,16 @@ - + - + - + - - - + + @@ -100708,13 +100724,13 @@ - + - + - + @@ -100756,7 +100772,7 @@ - + @@ -104919,7 +104935,7 @@ - + @@ -104935,7 +104951,7 @@ - + @@ -104943,7 +104959,7 @@ - + @@ -104957,7 +104973,7 @@ - + @@ -116281,6 +116297,14 @@ + + + + + + + + @@ -117798,6 +117822,17 @@ + + + + + + + + + + + @@ -122486,6 +122521,12 @@ + + + + + + @@ -123195,15 +123236,7 @@ - - - - - - - - - + @@ -124673,44 +124706,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -129955,6 +129950,14 @@ + + + + + + + + @@ -130153,14 +130156,6 @@ - - - - - - - - diff --git a/android/abi_gki_aarch64_qcom b/android/abi_gki_aarch64_qcom index 1e6e35d4f546..238eb7c8331e 100644 --- a/android/abi_gki_aarch64_qcom +++ b/android/abi_gki_aarch64_qcom @@ -164,6 +164,7 @@ cfg80211_scan_done cfg80211_sched_scan_results __cfg80211_send_event_skb + cfg80211_stop_iface cfg80211_tdls_oper_request cfg80211_unlink_bss cfg80211_update_owe_info_event From 12212948153062facf7bfbeda27e0dca4f1dddb9 Mon Sep 17 00:00:00 2001 From: Chenggang Wang Date: Wed, 18 Nov 2020 20:45:16 +0800 Subject: [PATCH 03/12] UPSTREAM: block: fix get_max_io_size() commit e4b469c66f3cbb81c2e94d31123d7bcdf3c1dabd upstream. A previous commit aligning splits to physical block sizes inadvertently modified one return case such that that it now returns 0 length splits when the number of sectors doesn't exceed the physical offset. This later hits a BUG in bio_split(). Restore the previous working behavior. Bug: 173583534 Fixes: 9cc5169cd478b ("block: Improve physical block alignment of split bios") Reported-by: Eric Deal Signed-off-by: Keith Busch Cc: Bart Van Assche Cc: stable@vger.kernel.org Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman Bug: 173583534 (cherry picked from commit f09dbec9c0c68f354eef157c0fe7aa1c6704ecd2) Signed-off-by: Chenggang Wang Signed-off-by: Greg Kroah-Hartman Change-Id: I5f4708059f106b6ded162cbe096e45bae7a7fca4 --- block/blk-merge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/blk-merge.c b/block/blk-merge.c index 8a226eb0c291..897169440a68 100644 --- a/block/blk-merge.c +++ b/block/blk-merge.c @@ -154,7 +154,7 @@ static inline unsigned get_max_io_size(struct request_queue *q, if (max_sectors > start_offset) return max_sectors - start_offset; - return sectors & (lbs - 1); + return sectors & ~(lbs - 1); } static inline unsigned get_max_segment_size(const struct request_queue *q, From 30bf0431f1362f57c993d69b070e6aa637805dcd Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 5 Mar 2020 09:06:21 +0000 Subject: [PATCH 04/12] BACKPORT: arm64: add support for the AMU extension v1 The activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture. This implements basic support for version 1 of the activity monitors architecture, AMUv1. This support includes: - Extension detection on each CPU (boot, secondary, hotplugged) - Register interface for AMU aarch64 registers Bug: 172781912 Change-Id: I8fa585dd992213d8042e6f9ddec2cb3bcefade05 Signed-off-by: Ionela Voinescu Reviewed-by: Valentin Schneider Cc: Mark Rutland Cc: Marc Zyngier Cc: Suzuki K Poulose Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Catalin Marinas (cherry picked from commit 2c9d45b43c39e26fd2a73f2203321cdaee98b58b) [neeraju: Resolved minor conflicts in Kconfig, cpucaps.h, cpufeature.h] Signed-off-by: Neeraj Upadhyay --- arch/arm64/Kconfig | 27 ++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cpufeature.h | 6 +++ arch/arm64/include/asm/sysreg.h | 38 +++++++++++++++++ arch/arm64/kernel/cpufeature.c | 66 +++++++++++++++++++++++++++++ 5 files changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 71d23b5d10d4..fc78b77e6393 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1462,6 +1462,33 @@ config ARM64_PTR_AUTH endmenu +menu "ARMv8.4 architectural features" + +config ARM64_AMU_EXTN + bool "Enable support for the Activity Monitors Unit CPU extension" + default y + help + The activity monitors extension is an optional extension introduced + by the ARMv8.4 CPU architecture. This enables support for version 1 + of the activity monitors architecture, AMUv1. + + To enable the use of this extension on CPUs that implement it, say Y. + + Note that for architectural reasons, firmware _must_ implement AMU + support when running on CPUs that present the activity monitors + extension. The required support is present in: + * Version 1.5 and later of the ARM Trusted Firmware + + For kernels that have this configuration enabled but boot with broken + firmware, you may need to say N here until the firmware is fixed. + Otherwise you may experience firmware panics or lockups when + accessing the counter registers. Even if you are not observing these + symptoms, the values returned by the register reads might not + correctly reflect reality. Most commonly, the value read will be 0, + indicating that the counter is not enabled. + +endmenu + config ARM64_SVE bool "ARM Scalable Vector Extension support" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 2bbf17419a40..9f6894df8592 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -55,8 +55,9 @@ #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 #define ARM64_WORKAROUND_1542419 47 +#define ARM64_HAS_AMU_EXTN 48 -/* kabi: reserve 48 - 62 for future cpu capabilities */ +/* kabi: reserve 49 - 62 for future cpu capabilities */ #define ARM64_NCAPS 62 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 10d3048dec7c..119f2eea7f44 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -659,6 +659,12 @@ static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) default: return CONFIG_ARM64_PA_BITS; } } + +#ifdef CONFIG_ARM64_AMU_EXTN +/* Check whether the cpu supports the Activity Monitors Unit (AMU) */ +extern bool cpu_has_amu_feat(int cpu); +#endif + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9b68f1b3915e..dd885ba6171b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -384,6 +384,42 @@ #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) +/* Definitions for system register interface to AMU for ARMv8.4 onwards */ +#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) +#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) +#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) +#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) +#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) +#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) +#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) +#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) +#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) + +/* + * Group 0 of activity monitors (architected): + * op0 op1 CRn CRm op2 + * Counter: 11 011 1101 010:n<3> n<2:0> + * Type: 11 011 1101 011:n<3> n<2:0> + * n: 0-15 + * + * Group 1 of activity monitors (auxiliary): + * op0 op1 CRn CRm op2 + * Counter: 11 011 1101 110:n<3> n<2:0> + * Type: 11 011 1101 111:n<3> n<2:0> + * n: 0-15 + */ + +#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) +#define SYS_AMEVTYPE0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) +#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) +#define SYS_AMEVTYPE1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) + +/* AMU v1: Fixed (architecturally defined) activity monitors */ +#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) +#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) +#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) +#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) + #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) @@ -579,6 +615,7 @@ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_DIT_SHIFT 48 +#define ID_AA64PFR0_AMU_SHIFT 44 #define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_GIC_SHIFT 24 @@ -589,6 +626,7 @@ #define ID_AA64PFR0_EL1_SHIFT 4 #define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_AMU 0x1 #define ID_AA64PFR0_SVE 0x1 #define ID_AA64PFR0_RAS_V1 0x1 #define ID_AA64PFR0_FP_NI 0xf diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index da92693b202c..63efa52dea67 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -154,6 +154,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), @@ -1147,6 +1148,53 @@ static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, #endif +#ifdef CONFIG_ARM64_AMU_EXTN + +/* + * The "amu_cpus" cpumask only signals that the CPU implementation for the + * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide + * information regarding all the events that it supports. When a CPU bit is + * set in the cpumask, the user of this feature can only rely on the presence + * of the 4 fixed counters for that CPU. But this does not guarantee that the + * counters are enabled or access to these counters is enabled by code + * executed at higher exception levels (firmware). + */ +static struct cpumask amu_cpus __read_mostly; + +bool cpu_has_amu_feat(int cpu) +{ + return cpumask_test_cpu(cpu, &amu_cpus); +} + +static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) +{ + if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { + pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", + smp_processor_id()); + cpumask_set_cpu(smp_processor_id(), &amu_cpus); + } +} + +static bool has_amu(const struct arm64_cpu_capabilities *cap, + int __unused) +{ + /* + * The AMU extension is a non-conflicting feature: the kernel can + * safely run a mix of CPUs with and without support for the + * activity monitors extension. Therefore, unconditionally enable + * the capability to allow any late CPU to use the feature. + * + * With this feature unconditionally enabled, the cpu_enable + * function will be called for all CPUs that match the criteria, + * including secondary and hotplugged, marking this feature as + * present on that respective CPU. The enable function will also + * print a detection message. + */ + + return true; +} +#endif + #ifdef CONFIG_ARM64_VHE static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) { @@ -1416,6 +1464,24 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .cpu_enable = cpu_clear_disr, }, #endif /* CONFIG_ARM64_RAS_EXTN */ +#ifdef CONFIG_ARM64_AMU_EXTN + { + /* + * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. + * Therefore, don't provide .desc as we don't want the detection + * message to be shown until at least one CPU is detected to + * support the feature. + */ + .capability = ARM64_HAS_AMU_EXTN, + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, + .matches = has_amu, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64PFR0_AMU_SHIFT, + .min_field_value = ID_AA64PFR0_AMU, + .cpu_enable = cpu_amu_enable, + }, +#endif /* CONFIG_ARM64_AMU_EXTN */ { .desc = "Data cache clean to the PoU not required for I/D coherence", .capability = ARM64_HAS_CACHE_IDC, From 0611858d57c40e51413c7a111bca3d823e3ada6b Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 5 Mar 2020 09:06:22 +0000 Subject: [PATCH 05/12] UPSTREAM: arm64: trap to EL1 accesses to AMU counters from EL0 The activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture. In order to access the activity monitors counters safely, if desired, the kernel should detect the presence of the extension through the feature register, and mediate the access. Therefore, disable direct accesses to activity monitors counters from EL0 (userspace) and trap them to EL1 (kernel). To be noted that the ARM64_AMU_EXTN kernel config does not have an effect on this code. Given that the amuserenr_el0 resets to an UNKNOWN value, setting the trap of EL0 accesses to EL1 is always attempted for safety and security considerations. Therefore firmware should still ensure accesses to AMU registers are not trapped in EL2/EL3 as this code cannot be bypassed if the CPU implements the Activity Monitors Unit. Bug: 172781912 Change-Id: I231595cd2d1e36bfc6abd24559c9c3d13e7eab03 Signed-off-by: Ionela Voinescu Reviewed-by: James Morse Reviewed-by: Valentin Schneider Reviewed-by: Suzuki K Poulose Cc: Steve Capper Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Catalin Marinas (cherry picked from commit 87a1f063464afd934f0f22aac710ca65bef77af3) Signed-off-by: Neeraj Upadhyay --- arch/arm64/include/asm/assembler.h | 10 ++++++++++ arch/arm64/mm/proc.S | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index b8cf7c85ffa2..bf7a83e47145 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -443,6 +443,16 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 9000: .endm +/* + * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present + */ + .macro reset_amuserenr_el0, tmpreg + mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 + ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4 + cbz \tmpreg, .Lskip_\@ // Skip if no AMU present + msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 +.Lskip_\@: + .endm /* * copy_page - copy src to dest using temp registers t1-t8 */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 5c8219c55948..bf6fc35df30f 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -138,6 +138,7 @@ alternative_endif ubfx x11, x11, #1, #1 msr oslar_el1, x11 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 + reset_amuserenr_el0 x0 // Disable AMU access from EL0 alternative_if ARM64_HAS_RAS_EXTN msr_s SYS_DISR_EL1, xzr @@ -430,6 +431,8 @@ ENTRY(__cpu_setup) isb // Unmask debug exceptions now, enable_dbg // since this is per-cpu reset_pmuserenr_el0 x0 // Disable PMU access from EL0 + reset_amuserenr_el0 x0 // Disable AMU access from EL0 + /* * Memory region attributes for LPAE: * From 57ab64893e8df10e675134c19c9e8c4ce723cb2f Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 5 Mar 2020 09:06:23 +0000 Subject: [PATCH 06/12] UPSTREAM: arm64/kvm: disable access to AMU registers from kvm guests Access to the AMU counters should be disabled by default in kvm guests, as information from the counters might reveal activity in other guests or activity on the host. Therefore, disable access to AMU registers from EL0 and EL1 in kvm guests by: - Hiding the presence of the extension in the feature register (SYS_ID_AA64PFR0_EL1) on the VCPU. - Disabling access to the AMU registers before switching to the guest. - Trapping accesses and injecting an undefined instruction into the guest. Bug: 172781912 Change-Id: Ie8048574431dfe00e9d8f59ecbcf51b4c1167000 Signed-off-by: Ionela Voinescu Reviewed-by: Suzuki K Poulose Reviewed-by: Valentin Schneider Acked-by: Marc Zyngier Cc: Will Deacon Cc: Catalin Marinas Cc: Suzuki K Poulose Cc: Julien Thierry Cc: James Morse Cc: Marc Zyngier Signed-off-by: Catalin Marinas (cherry picked from commit 4fcdf106a4330bb5c2306a1efbb3af3b7c0db537) Signed-off-by: Neeraj Upadhyay --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kvm/hyp/switch.c | 14 ++++- arch/arm64/kvm/sys_regs.c | 93 +++++++++++++++++++++++++++++++- 3 files changed, 105 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index ddf9d762ac62..71f3f40a155e 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -268,6 +268,7 @@ /* Hyp Coprocessor Trap Register */ #define CPTR_EL2_TCPAC (1 << 31) +#define CPTR_EL2_TAM (1 << 30) #define CPTR_EL2_TTA (1 << 20) #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) #define CPTR_EL2_TZ (1 << 8) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index d76a3d39b269..967e04d93ec6 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -98,6 +98,18 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) val = read_sysreg(cpacr_el1); val |= CPACR_EL1_TTA; val &= ~CPACR_EL1_ZEN; + + /* + * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to + * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, + * except for some missing controls, such as TAM. + * In this case, CPTR_EL2.TAM has the same position with or without + * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM + * shift value for trapping the AMU accesses. + */ + + val |= CPTR_EL2_TAM; + if (update_fp_enabled(vcpu)) { if (vcpu_has_sve(vcpu)) val |= CPACR_EL1_ZEN; @@ -119,7 +131,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) __activate_traps_common(vcpu); val = CPTR_EL2_DEFAULT; - val |= CPTR_EL2_TTA | CPTR_EL2_TZ; + val |= CPTR_EL2_TTA | CPTR_EL2_TZ | CPTR_EL2_TAM; if (!update_fp_enabled(vcpu)) { val |= CPTR_EL2_TFP; __activate_traps_fpsimd32(vcpu); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d43f44b3377e..d85a9c803054 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1003,6 +1003,20 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } +static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + kvm_inject_undefined(vcpu); + + return false; +} + +/* Macro to expand the AMU counter and type registers*/ +#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu } +#define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)), access_amu } +#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu } +#define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)), access_amu } + static bool trap_ptrauth(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd) @@ -1078,8 +1092,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); u64 val = raz ? 0 : read_sanitised_ftr_reg(id); - if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) { - val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); + if (id == SYS_ID_AA64PFR0_EL1) { + if (!vcpu_has_sve(vcpu)) + val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); + val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | (0xfUL << ID_AA64ISAR1_API_SHIFT) | @@ -1571,6 +1587,79 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, + { SYS_DESC(SYS_AMCR_EL0), access_amu }, + { SYS_DESC(SYS_AMCFGR_EL0), access_amu }, + { SYS_DESC(SYS_AMCGCR_EL0), access_amu }, + { SYS_DESC(SYS_AMUSERENR_EL0), access_amu }, + { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu }, + { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu }, + { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu }, + { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu }, + AMU_AMEVCNTR0_EL0(0), + AMU_AMEVCNTR0_EL0(1), + AMU_AMEVCNTR0_EL0(2), + AMU_AMEVCNTR0_EL0(3), + AMU_AMEVCNTR0_EL0(4), + AMU_AMEVCNTR0_EL0(5), + AMU_AMEVCNTR0_EL0(6), + AMU_AMEVCNTR0_EL0(7), + AMU_AMEVCNTR0_EL0(8), + AMU_AMEVCNTR0_EL0(9), + AMU_AMEVCNTR0_EL0(10), + AMU_AMEVCNTR0_EL0(11), + AMU_AMEVCNTR0_EL0(12), + AMU_AMEVCNTR0_EL0(13), + AMU_AMEVCNTR0_EL0(14), + AMU_AMEVCNTR0_EL0(15), + AMU_AMEVTYPE0_EL0(0), + AMU_AMEVTYPE0_EL0(1), + AMU_AMEVTYPE0_EL0(2), + AMU_AMEVTYPE0_EL0(3), + AMU_AMEVTYPE0_EL0(4), + AMU_AMEVTYPE0_EL0(5), + AMU_AMEVTYPE0_EL0(6), + AMU_AMEVTYPE0_EL0(7), + AMU_AMEVTYPE0_EL0(8), + AMU_AMEVTYPE0_EL0(9), + AMU_AMEVTYPE0_EL0(10), + AMU_AMEVTYPE0_EL0(11), + AMU_AMEVTYPE0_EL0(12), + AMU_AMEVTYPE0_EL0(13), + AMU_AMEVTYPE0_EL0(14), + AMU_AMEVTYPE0_EL0(15), + AMU_AMEVCNTR1_EL0(0), + AMU_AMEVCNTR1_EL0(1), + AMU_AMEVCNTR1_EL0(2), + AMU_AMEVCNTR1_EL0(3), + AMU_AMEVCNTR1_EL0(4), + AMU_AMEVCNTR1_EL0(5), + AMU_AMEVCNTR1_EL0(6), + AMU_AMEVCNTR1_EL0(7), + AMU_AMEVCNTR1_EL0(8), + AMU_AMEVCNTR1_EL0(9), + AMU_AMEVCNTR1_EL0(10), + AMU_AMEVCNTR1_EL0(11), + AMU_AMEVCNTR1_EL0(12), + AMU_AMEVCNTR1_EL0(13), + AMU_AMEVCNTR1_EL0(14), + AMU_AMEVCNTR1_EL0(15), + AMU_AMEVTYPE1_EL0(0), + AMU_AMEVTYPE1_EL0(1), + AMU_AMEVTYPE1_EL0(2), + AMU_AMEVTYPE1_EL0(3), + AMU_AMEVTYPE1_EL0(4), + AMU_AMEVTYPE1_EL0(5), + AMU_AMEVTYPE1_EL0(6), + AMU_AMEVTYPE1_EL0(7), + AMU_AMEVTYPE1_EL0(8), + AMU_AMEVTYPE1_EL0(9), + AMU_AMEVTYPE1_EL0(10), + AMU_AMEVTYPE1_EL0(11), + AMU_AMEVTYPE1_EL0(12), + AMU_AMEVTYPE1_EL0(13), + AMU_AMEVTYPE1_EL0(14), + AMU_AMEVTYPE1_EL0(15), + { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, From b7b866b3aa451b472b679d40171bc8eb1744c69c Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 5 Mar 2020 09:06:24 +0000 Subject: [PATCH 07/12] UPSTREAM: Documentation: arm64: document support for the AMU extension The activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture. Add initial documentation for the AMUv1 extension: - arm64/amu.txt: AMUv1 documentation - arm64/booting.txt: system registers initialisation Bug: 172781912 Change-Id: I1a892d7aa98ff545a3fe326f5a827337f41ddf19 Signed-off-by: Ionela Voinescu Reviewed-by: Valentin Schneider Cc: Jonathan Corbet Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Catalin Marinas (cherry picked from commit 6abde90881a5ea3a383c0959fdd7f575f95db4b3) Signed-off-by: Neeraj Upadhyay --- Documentation/arm64/amu.rst | 112 ++++++++++++++++++++++++++++++++ Documentation/arm64/booting.rst | 14 ++++ Documentation/arm64/index.rst | 1 + 3 files changed, 127 insertions(+) create mode 100644 Documentation/arm64/amu.rst diff --git a/Documentation/arm64/amu.rst b/Documentation/arm64/amu.rst new file mode 100644 index 000000000000..5057b11100ed --- /dev/null +++ b/Documentation/arm64/amu.rst @@ -0,0 +1,112 @@ +======================================================= +Activity Monitors Unit (AMU) extension in AArch64 Linux +======================================================= + +Author: Ionela Voinescu + +Date: 2019-09-10 + +This document briefly describes the provision of Activity Monitors Unit +support in AArch64 Linux. + + +Architecture overview +--------------------- + +The activity monitors extension is an optional extension introduced by the +ARMv8.4 CPU architecture. + +The activity monitors unit, implemented in each CPU, provides performance +counters intended for system management use. The AMU extension provides a +system register interface to the counter registers and also supports an +optional external memory-mapped interface. + +Version 1 of the Activity Monitors architecture implements a counter group +of four fixed and architecturally defined 64-bit event counters. + - CPU cycle counter: increments at the frequency of the CPU. + - Constant counter: increments at the fixed frequency of the system + clock. + - Instructions retired: increments with every architecturally executed + instruction. + - Memory stall cycles: counts instruction dispatch stall cycles caused by + misses in the last level cache within the clock domain. + +When in WFI or WFE these counters do not increment. + +The Activity Monitors architecture provides space for up to 16 architected +event counters. Future versions of the architecture may use this space to +implement additional architected event counters. + +Additionally, version 1 implements a counter group of up to 16 auxiliary +64-bit event counters. + +On cold reset all counters reset to 0. + + +Basic support +------------- + +The kernel can safely run a mix of CPUs with and without support for the +activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is +selected we unconditionally enable the capability to allow any late CPU +(secondary or hotplugged) to detect and use the feature. + +When the feature is detected on a CPU, we flag the availability of the +feature but this does not guarantee the correct functionality of the +counters, only the presence of the extension. + +Firmware (code running at higher exception levels, e.g. arm-tf) support is +needed to: + - Enable access for lower exception levels (EL2 and EL1) to the AMU + registers. + - Enable the counters. If not enabled these will read as 0. + - Save/restore the counters before/after the CPU is being put/brought up + from the 'off' power state. + +When using kernels that have this feature enabled but boot with broken +firmware the user may experience panics or lockups when accessing the +counter registers. Even if these symptoms are not observed, the values +returned by the register reads might not correctly reflect reality. Most +commonly, the counters will read as 0, indicating that they are not +enabled. + +If proper support is not provided in firmware it's best to disable +CONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not +bypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to +EL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers +are not trapped in EL2/EL3. + +The fixed counters of AMUv1 are accessible though the following system +register definitions: + - SYS_AMEVCNTR0_CORE_EL0 + - SYS_AMEVCNTR0_CONST_EL0 + - SYS_AMEVCNTR0_INST_RET_EL0 + - SYS_AMEVCNTR0_MEM_STALL_EL0 + +Auxiliary platform specific counters can be accessed using +SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15. + +Details can be found in: arch/arm64/include/asm/sysreg.h. + + +Userspace access +---------------- + +Currently, access from userspace to the AMU registers is disabled due to: + - Security reasons: they might expose information about code executed in + secure mode. + - Purpose: AMU counters are intended for system management use. + +Also, the presence of the feature is not visible to userspace. + + +Virtualization +-------------- + +Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM +guest side is disabled due to: + - Security reasons: they might expose information about code executed + by other guests or the host. + +Any attempt to access the AMU registers will result in an UNDEFINED +exception being injected into the guest. diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index d3f3a60fbf25..a17f427990d6 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -245,6 +245,20 @@ Before jumping into the kernel, the following conditions must be met: - HCR_EL2.APK (bit 40) must be initialised to 0b1 - HCR_EL2.API (bit 41) must be initialised to 0b1 + For CPUs with Activity Monitors Unit v1 (AMUv1) extension present: + - If EL3 is present: + CPTR_EL3.TAM (bit 30) must be initialised to 0b0 + CPTR_EL2.TAM (bit 30) must be initialised to 0b0 + AMCNTENSET0_EL0 must be initialised to 0b1111 + AMCNTENSET1_EL0 must be initialised to a platform specific value + having 0b1 set for the corresponding bit for each of the auxiliary + counters present. + - If the kernel is entered at EL1: + AMCNTENSET0_EL0 must be initialised to 0b1111 + AMCNTENSET1_EL0 must be initialised to a platform specific value + having 0b1 set for the corresponding bit for each of the auxiliary + counters present. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst index 5c0c69dc58aa..09cbb4ed2237 100644 --- a/Documentation/arm64/index.rst +++ b/Documentation/arm64/index.rst @@ -6,6 +6,7 @@ ARM64 Architecture :maxdepth: 1 acpi_object_usage + amu arm-acpi booting cpu-feature-registers From 068c7df5db0606e1c4f0e65c31f04ffd935a5303 Mon Sep 17 00:00:00 2001 From: Sudarsan Ramesh Date: Mon, 16 Nov 2020 19:37:00 -0500 Subject: [PATCH 08/12] ANDROID: ABI: Update allowed list for QCOM Leaf changes summary: 1 artifact changed Changed leaf types summary: 0 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 1 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 1 Added function: [A] 'function bool drm_edid_is_valid(edid*)' Bug: 173583550 Change-Id: I64a212304a4988257c370206adb34c8cfe4a0ab5 Signed-off-by: Sudarsan Ramesh --- android/abi_gki_aarch64.xml | 188 +++++++++++++++++++---------------- android/abi_gki_aarch64_qcom | 1 + 2 files changed, 102 insertions(+), 87 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 599c5c28ba4c..86f4cd63f348 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -1309,6 +1309,7 @@ + @@ -23271,14 +23272,6 @@ - - - - - - - - @@ -31632,7 +31625,6 @@ - @@ -31688,7 +31680,7 @@ - + @@ -31921,7 +31913,7 @@ - + @@ -32219,7 +32211,7 @@ - + @@ -34832,7 +34824,7 @@ - + @@ -35344,7 +35336,7 @@ - + @@ -35616,7 +35608,7 @@ - + @@ -36712,7 +36704,7 @@ - + @@ -37030,6 +37022,10 @@ + + + + @@ -37112,7 +37108,7 @@ - + @@ -37174,6 +37170,7 @@ + @@ -37282,14 +37279,6 @@ - - - - - - - - @@ -37758,7 +37747,7 @@ - + @@ -38296,6 +38285,14 @@ + + + + + + + + @@ -60599,17 +60596,6 @@ - - - - - - - - - - - @@ -65157,6 +65143,17 @@ + + + + + + + + + + + @@ -72056,7 +72053,6 @@ - @@ -72260,7 +72256,6 @@ - @@ -72779,7 +72774,7 @@ - + @@ -74642,7 +74637,7 @@ - + @@ -78139,6 +78134,14 @@ + + + + + + + + @@ -89499,14 +89502,6 @@ - - - - - - - - @@ -94884,7 +94879,7 @@ - + @@ -104981,7 +104976,7 @@ - + @@ -113496,22 +113491,6 @@ - - - - - - - - - - - - - - - - @@ -115343,6 +115322,17 @@ + + + + + + + + + + + @@ -115481,7 +115471,31 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + @@ -115489,7 +115503,7 @@ - + @@ -116297,14 +116311,6 @@ - - - - - - - - @@ -123236,7 +123242,15 @@ - + + + + + + + + + @@ -129950,14 +129964,6 @@ - - - - - - - - @@ -130156,6 +130162,14 @@ + + + + + + + + @@ -130860,6 +130874,6 @@ diff --git a/android/abi_gki_aarch64_qcom b/android/abi_gki_aarch64_qcom index 238eb7c8331e..ada95f2e71ac 100644 --- a/android/abi_gki_aarch64_qcom +++ b/android/abi_gki_aarch64_qcom @@ -725,6 +725,7 @@ drm_dp_update_payload_part1 drm_dp_update_payload_part2 drm_edid_duplicate + drm_edid_is_valid drm_encoder_cleanup drm_encoder_init drm_err From 034d5a95c1374b75370fc01576bac1fb054bc6de Mon Sep 17 00:00:00 2001 From: Connor O'Brien Date: Wed, 22 May 2019 14:32:49 -0700 Subject: [PATCH 09/12] ANDROID: uid_sys_stats: report uid_cputime stats in microseconds A porting error in commit 0ae8088521d9 ("ANDROID: uid_cputime: Adds accounting for the cputimes per uid.") caused /proc/uid_cputime/show_uid_stat to report times in milliseconds instead of microseconds. Restore the expected behavior. Bug: 133273154 Bug: 146339763 Signed-off-by: Ed Savage-Jones Signed-off-by: Connor O'Brien Change-Id: I203919d1d44b300dab91810b16626a6950b063f8 (cherry picked from commit 305d5c197508b80a8dec0ab506de309e5d85fd26) --- drivers/misc/uid_sys_stats.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/uid_sys_stats.c b/drivers/misc/uid_sys_stats.c index 1f49abe3df15..6f17a3c8aa2c 100644 --- a/drivers/misc/uid_sys_stats.c +++ b/drivers/misc/uid_sys_stats.c @@ -372,7 +372,7 @@ static int uid_cputime_show(struct seq_file *m, void *v) u64 total_stime = uid_entry->stime + uid_entry->active_stime; seq_printf(m, "%d: %llu %llu\n", uid_entry->uid, - ktime_to_ms(total_utime), ktime_to_ms(total_stime)); + ktime_to_us(total_utime), ktime_to_us(total_stime)); } rt_mutex_unlock(&uid_lock); From fa50448d977fb03570f355571acd4e3dd1dcd994 Mon Sep 17 00:00:00 2001 From: Martin Wu Date: Fri, 13 Nov 2020 17:45:09 +0800 Subject: [PATCH 10/12] ANDROID: GKI: enable CONFIG_SUN4I_TIMER Allwinner's SoC timer driver (timer-sun4i.c) has to be built-in rather than modularized for the following limitations in linux timer framework: 1. tick broadcast installed by insmod cannot switch to oneshot mode correctly 2. cpus cannot enter cpuidle state due to the issue above. 3. rcu warnings will appear if we forcibly re-enable tick-broadcast for each cpu when new tick broadcast device is installed by insmod (timer-sun4i.c in our case) Bug: 173667601 Change-Id: If077db348c027ec02549e25eee3e17c2cc429644 Signed-off-by: Martin Wu --- arch/arm64/configs/gki_defconfig | 1 + drivers/clocksource/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/configs/gki_defconfig b/arch/arm64/configs/gki_defconfig index 1da021deabe0..3078e6744bda 100644 --- a/arch/arm64/configs/gki_defconfig +++ b/arch/arm64/configs/gki_defconfig @@ -445,6 +445,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_CLK_SUNXI is not set # CONFIG_SUNXI_CCU is not set CONFIG_HWSPINLOCK=y +CONFIG_SUN4I_TIMER=y # CONFIG_SUN50I_ERRATUM_UNKNOWN1 is not set CONFIG_MTK_TIMER=y CONFIG_MAILBOX=y diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 49821314dd54..080f05b740b8 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -127,7 +127,7 @@ config RDA_TIMER Enables the support for the RDA Micro timer driver. config SUN4I_TIMER - bool "Sun4i timer driver" if COMPILE_TEST + bool "Sun4i timer driver" depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF From 5b622f9fc013fbac5f050f3648e386f31be90961 Mon Sep 17 00:00:00 2001 From: "hajun.sung" Date: Fri, 13 Nov 2020 22:22:41 +0900 Subject: [PATCH 11/12] ANDROID: GKI: Update abi_gki_aarch64_exynos Leaf changes summary: 0 artifact changed Changed leaf types summary: 0 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 0 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable Added pci_find_ext_capability symbol Bug: 173187552 Change-Id: I419ab952f69f1da2b1867ab743da3830238a1912 Signed-off-by: hajun.sung Signed-off-by: Greg Kroah-Hartman --- android/abi_gki_aarch64_exynos | 1 + 1 file changed, 1 insertion(+) diff --git a/android/abi_gki_aarch64_exynos b/android/abi_gki_aarch64_exynos index 4222e5233d9d..ac98ae3dd488 100644 --- a/android/abi_gki_aarch64_exynos +++ b/android/abi_gki_aarch64_exynos @@ -985,6 +985,7 @@ pci_bus_type pci_d3cold_disable pci_find_bus + pci_find_ext_capability pci_free_irq_vectors pci_get_device pci_irq_vector From 274fdbe87ff31b3650f9293edba2ce0ac2dc3a11 Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Thu, 19 Nov 2020 21:51:42 +0530 Subject: [PATCH 12/12] ANDROID: ABI: Update allowed list for QCOM Leaf changes summary: 1 artifact changed Changed leaf types summary: 0 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 1 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 1 Added function: [A] 'function bool bio_crypt_should_process(request*)' Bug: 173684180 Signed-off-by: Neeraj Soni Change-Id: I0c4b63609d08a11aa6ca38c7afc3327832f31894 --- android/abi_gki_aarch64.xml | 500 +++++++++++++++++++++-------------- android/abi_gki_aarch64_qcom | 1 + 2 files changed, 308 insertions(+), 193 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 86f4cd63f348..aa21b52c0c34 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -14626,7 +14626,7 @@ - + @@ -14945,7 +14945,7 @@ - + @@ -15460,20 +15460,6 @@ - - - - - - - - - - - - - - @@ -23686,6 +23672,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -23892,6 +23898,17 @@ + + + + + + + + + + + @@ -28149,7 +28166,7 @@ - + @@ -28327,6 +28344,10 @@ + + + + @@ -30978,6 +30999,17 @@ + + + + + + + + + + + @@ -31625,6 +31657,7 @@ + @@ -31680,7 +31713,7 @@ - + @@ -31913,7 +31946,7 @@ - + @@ -32211,7 +32244,7 @@ - + @@ -33458,7 +33491,7 @@ - + @@ -34824,7 +34857,7 @@ - + @@ -35336,7 +35369,7 @@ - + @@ -35608,7 +35641,7 @@ - + @@ -35714,7 +35747,7 @@ - + @@ -36704,7 +36737,7 @@ - + @@ -37108,7 +37141,7 @@ - + @@ -37168,9 +37201,8 @@ - + - @@ -37196,7 +37228,7 @@ - + @@ -37210,6 +37242,12 @@ + + + + + + @@ -37279,6 +37317,14 @@ + + + + + + + + @@ -38285,14 +38331,6 @@ - - - - - - - - @@ -39020,17 +39058,6 @@ - - - - - - - - - - - @@ -54514,7 +54541,6 @@ - @@ -54538,7 +54564,7 @@ - + @@ -54546,7 +54572,7 @@ - + @@ -56016,14 +56042,6 @@ - - - - - - - - @@ -57263,6 +57281,17 @@ + + + + + + + + + + + @@ -60596,6 +60625,17 @@ + + + + + + + + + + + @@ -65143,17 +65183,6 @@ - - - - - - - - - - - @@ -65547,10 +65576,6 @@ - - - - @@ -72053,6 +72078,7 @@ + @@ -72172,30 +72198,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -72256,6 +72258,7 @@ + @@ -72774,7 +72777,7 @@ - + @@ -74637,7 +74640,7 @@ - + @@ -80625,6 +80628,17 @@ + + + + + + + + + + + @@ -89466,17 +89480,6 @@ - - - - - - - - - - - @@ -89502,6 +89505,14 @@ + + + + + + + + @@ -93721,17 +93732,6 @@ - - - - - - - - - - - @@ -94484,7 +94484,7 @@ - + @@ -94879,7 +94879,7 @@ - + @@ -95345,7 +95345,7 @@ - + @@ -100719,13 +100719,13 @@ - + - + - + @@ -100767,7 +100767,7 @@ - + @@ -103789,7 +103789,7 @@ - + @@ -104930,7 +104930,7 @@ - + @@ -104946,7 +104946,7 @@ - + @@ -104954,7 +104954,7 @@ - + @@ -104968,7 +104968,7 @@ - + @@ -104976,7 +104976,7 @@ - + @@ -110203,6 +110203,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -110211,8 +110306,9 @@ + - + @@ -113491,6 +113587,22 @@ + + + + + + + + + + + + + + + + @@ -115322,17 +115434,6 @@ - - - - - - - - - - - @@ -115471,31 +115572,7 @@ - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -115503,7 +115580,7 @@ - + @@ -115752,6 +115829,17 @@ + + + + + + + + + + + @@ -115821,7 +115909,7 @@ - + @@ -116033,7 +116121,7 @@ - + @@ -116165,7 +116253,7 @@ - + @@ -116216,13 +116304,13 @@ - + - + @@ -116234,7 +116322,7 @@ - + @@ -117033,7 +117121,6 @@ - @@ -117828,17 +117915,6 @@ - - - - - - - - - - - @@ -124720,6 +124796,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -130874,6 +130988,6 @@ diff --git a/android/abi_gki_aarch64_qcom b/android/abi_gki_aarch64_qcom index ada95f2e71ac..6b057e26e11e 100644 --- a/android/abi_gki_aarch64_qcom +++ b/android/abi_gki_aarch64_qcom @@ -1234,6 +1234,7 @@ keyslot_manager_set_max_dun_bytes keyslot_manager_reprogram_all_keys keyslot_manager_destroy + bio_crypt_should_process __kfifo_in __kfifo_out kfree