From f506fa55a8f4f9d6cc2eff26e5a53a5f6572c30c Mon Sep 17 00:00:00 2001
From: Ram Prakash Gupta <rampraka@qti.qualcomm.com>
Date: Tue, 18 Aug 2020 02:30:24 +0530
Subject: [PATCH] ARM: dts: msm: Add hw gcc reset for sdcc on holi

Add hw gcc reset support for sdcc on holi.

Change-Id: Ibe1d2180f86b7df331968154f5d4c989d0cb563a
---
 qcom/holi.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi
index 1d8a294b6fd4..aaa777bd39ec 100644
--- a/qcom/holi.dtsi
+++ b/qcom/holi.dtsi
@@ -2170,6 +2170,8 @@
 		mmc-hs400-1_8v;
 		mmc-hs400-enhanced-strobe;
 
+		cap-mmc-hw-reset;
+
 		bus-width = <8>;
 		non-removable;
 		supports-cqe;
@@ -2177,6 +2179,10 @@
 		qcom,devfreq,freq-table = <50000000 200000000>;
 		qcom,scaling-lower-bus-speed-mode = "DDR52";
 
+		/* Add dt entry for gcc hw reset */
+		resets = <&gcc GCC_SDCC1_BCR>;
+		reset-names = "core_reset";
+
 		status = "disabled";
 
 		qos0 {