From 33cd3c657a1bbe39d30c5702efa1444ed81c65e5 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Thu, 12 Sep 2019 17:06:48 -0700 Subject: [PATCH] clk: dt-bindings: gcc: Update gcc clock driver header for Lahaina Update header file for gcc clocks and its reset constants. Change-Id: I2e8302ddd40450cfdd80d9cf57cfc03993a000b6 Signed-off-by: Vivek Aknurwar --- include/dt-bindings/clock/qcom,gcc-lahaina.h | 452 +++++++++---------- 1 file changed, 221 insertions(+), 231 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gcc-lahaina.h b/include/dt-bindings/clock/qcom,gcc-lahaina.h index a56a7c447cf5..b229a6fad1ab 100644 --- a/include/dt-bindings/clock/qcom,gcc-lahaina.h +++ b/include/dt-bindings/clock/qcom,gcc-lahaina.h @@ -7,240 +7,230 @@ #define _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H /* GCC clocks */ -#define CORE_BI_PLL_TEST_SE 0 -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 1 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 2 -#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 3 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 4 -#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 5 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 7 -#define GCC_BOOT_ROM_AHB_CLK 8 -#define GCC_CAMERA_AHB_CLK 9 -#define GCC_CAMERA_HF_AXI_CLK 10 -#define GCC_CAMERA_SF_AXI_CLK 11 -#define GCC_CAMERA_XO_CLK 12 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 13 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 14 -#define GCC_CPUSS_AHB_CLK 15 -#define GCC_CPUSS_AHB_CLK_SRC 16 -#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DDRSS_PCIE_SF_TBU_CLK 19 -#define GCC_DISP_AHB_CLK 20 -#define GCC_DISP_HF_AXI_CLK 21 -#define GCC_DISP_SF_AXI_CLK 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_DPM_CB_CLK 24 -#define GCC_DPM_CLK 25 -#define GCC_DPM_CLK_SRC 26 -#define GCC_DPM_CX_AHB_CLK 27 -#define GCC_DPM_MX_AHB_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP1_CLK_SRC 30 -#define GCC_GP2_CLK 31 -#define GCC_GP2_CLK_SRC 32 -#define GCC_GP3_CLK 33 -#define GCC_GP3_CLK_SRC 34 -#define GCC_GPLL0 35 -#define GCC_GPLL0_OUT_EVEN 36 -#define GCC_GPLL9 37 -#define GCC_GPU_CFG_AHB_CLK 38 -#define GCC_GPU_GPLL0_CLK_SRC 39 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 40 -#define GCC_GPU_IREF_EN 41 -#define GCC_GPU_MEMNOC_GFX_CLK 42 -#define GCC_GPU_SNOC_DVM_GFX_CLK 43 -#define GCC_PCIE0_PHY_RCHNG_CLK 44 -#define GCC_PCIE1_PHY_RCHNG_CLK 45 -#define GCC_PCIE_0_AUX_CLK 46 -#define GCC_PCIE_0_AUX_CLK_SRC 47 -#define GCC_PCIE_0_CFG_AHB_CLK 48 -#define GCC_PCIE_0_CLKREF_EN 49 -#define GCC_PCIE_0_MSTR_AXI_CLK 50 -#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 -#define GCC_PCIE_0_PIPE_CLK 52 -#define GCC_PCIE_0_SLV_AXI_CLK 53 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 54 -#define GCC_PCIE_1_AUX_CLK 55 -#define GCC_PCIE_1_AUX_CLK_SRC 56 -#define GCC_PCIE_1_CFG_AHB_CLK 57 -#define GCC_PCIE_1_CLKREF_EN 58 -#define GCC_PCIE_1_MSTR_AXI_CLK 59 -#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 60 -#define GCC_PCIE_1_PIPE_CLK 61 -#define GCC_PCIE_1_SLV_AXI_CLK 62 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 -#define GCC_PDM2_CLK 64 -#define GCC_PDM2_CLK_SRC 65 -#define GCC_PDM_AHB_CLK 66 -#define GCC_PDM_XO4_CLK 67 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 68 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 69 -#define GCC_QMIP_DISP_AHB_CLK 70 -#define GCC_QMIP_VIDEO_CVP_AHB_CLK 71 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 72 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73 -#define GCC_QUPV3_WRAP0_CORE_CLK 74 -#define GCC_QUPV3_WRAP0_S0_CLK 75 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76 -#define GCC_QUPV3_WRAP0_S1_CLK 77 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78 -#define GCC_QUPV3_WRAP0_S2_CLK 79 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80 -#define GCC_QUPV3_WRAP0_S3_CLK 81 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82 -#define GCC_QUPV3_WRAP0_S4_CLK 83 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84 -#define GCC_QUPV3_WRAP0_S5_CLK 85 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86 -#define GCC_QUPV3_WRAP0_S6_CLK 87 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 88 -#define GCC_QUPV3_WRAP0_S7_CLK 89 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 90 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91 -#define GCC_QUPV3_WRAP1_CORE_CLK 92 -#define GCC_QUPV3_WRAP1_S0_CLK 93 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94 -#define GCC_QUPV3_WRAP1_S1_CLK 95 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96 -#define GCC_QUPV3_WRAP1_S2_CLK 97 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98 -#define GCC_QUPV3_WRAP1_S3_CLK 99 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100 -#define GCC_QUPV3_WRAP1_S4_CLK 101 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102 -#define GCC_QUPV3_WRAP1_S5_CLK 103 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104 -#define GCC_QUPV3_WRAP2_CORE_2X_CLK 105 -#define GCC_QUPV3_WRAP2_CORE_CLK 106 -#define GCC_QUPV3_WRAP2_S0_CLK 107 -#define GCC_QUPV3_WRAP2_S0_CLK_SRC 108 -#define GCC_QUPV3_WRAP2_S1_CLK 109 -#define GCC_QUPV3_WRAP2_S1_CLK_SRC 110 -#define GCC_QUPV3_WRAP2_S2_CLK 111 -#define GCC_QUPV3_WRAP2_S2_CLK_SRC 112 -#define GCC_QUPV3_WRAP2_S3_CLK 113 -#define GCC_QUPV3_WRAP2_S3_CLK_SRC 114 -#define GCC_QUPV3_WRAP2_S4_CLK 115 -#define GCC_QUPV3_WRAP2_S4_CLK_SRC 116 -#define GCC_QUPV3_WRAP2_S5_CLK 117 -#define GCC_QUPV3_WRAP2_S5_CLK_SRC 118 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 121 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 122 -#define GCC_QUPV3_WRAP_2_M_AHB_CLK 123 -#define GCC_QUPV3_WRAP_2_S_AHB_CLK 124 -#define GCC_SDCC2_AHB_CLK 125 -#define GCC_SDCC2_APPS_CLK 126 -#define GCC_SDCC2_APPS_CLK_SRC 127 -#define GCC_SDCC4_AHB_CLK 128 -#define GCC_SDCC4_APPS_CLK 129 -#define GCC_SDCC4_APPS_CLK_SRC 130 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 131 -#define GCC_UFS_1_CLKREF_EN 132 -#define GCC_UFS_CARD_AHB_CLK 133 -#define GCC_UFS_CARD_AXI_CLK 134 -#define GCC_UFS_CARD_AXI_CLK_SRC 135 -#define GCC_UFS_CARD_AXI_HW_CTL_CLK 136 -#define GCC_UFS_CARD_ICE_CORE_CLK 137 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 138 -#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 139 -#define GCC_UFS_CARD_PHY_AUX_CLK 140 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 141 -#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 142 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 143 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 144 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 145 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 146 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 147 -#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 148 -#define GCC_UFS_PHY_AHB_CLK 149 -#define GCC_UFS_PHY_AXI_CLK 150 -#define GCC_UFS_PHY_AXI_CLK_SRC 151 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 152 -#define GCC_UFS_PHY_ICE_CORE_CLK 153 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 154 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 155 -#define GCC_UFS_PHY_PHY_AUX_CLK 156 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 157 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 158 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 159 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 160 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 161 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 162 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 163 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 164 -#define GCC_USB30_PRIM_MASTER_CLK 165 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 166 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 167 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 168 -#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 169 -#define GCC_USB30_PRIM_SLEEP_CLK 170 -#define GCC_USB30_SEC_MASTER_CLK 171 -#define GCC_USB30_SEC_MASTER_CLK_SRC 172 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 173 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 174 -#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 175 -#define GCC_USB30_SEC_SLEEP_CLK 176 -#define GCC_USB3_PRIM_PHY_AUX_CLK 177 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 178 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 179 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 180 -#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 181 -#define GCC_USB3_SEC_CLKREF_EN 182 -#define GCC_USB3_SEC_PHY_AUX_CLK 183 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 184 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 185 -#define GCC_USB3_SEC_PHY_PIPE_CLK 186 -#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 187 -#define GCC_VIDEO_AHB_CLK 188 -#define GCC_VIDEO_AXI0_CLK 189 -#define GCC_VIDEO_AXI1_CLK 190 -#define GCC_VIDEO_XO_CLK 191 -#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 192 -#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 193 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_CAMERA_AHB_CLK 8 +#define GCC_CAMERA_HF_AXI_CLK 9 +#define GCC_CAMERA_SF_AXI_CLK 10 +#define GCC_CAMERA_XO_CLK 11 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +#define GCC_CPUSS_AHB_CLK 14 +#define GCC_CPUSS_AHB_CLK_SRC 15 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 16 +#define GCC_DDRSS_GPU_AXI_CLK 17 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 18 +#define GCC_DISP_AHB_CLK 19 +#define GCC_DISP_HF_AXI_CLK 20 +#define GCC_DISP_SF_AXI_CLK 21 +#define GCC_DISP_XO_CLK 22 +#define GCC_GP1_CLK 23 +#define GCC_GP1_CLK_SRC 24 +#define GCC_GP2_CLK 25 +#define GCC_GP2_CLK_SRC 26 +#define GCC_GP3_CLK 27 +#define GCC_GP3_CLK_SRC 28 +#define GCC_GPLL0 29 +#define GCC_GPLL0_OUT_EVEN 30 +#define GCC_GPLL4 31 +#define GCC_GPLL9 32 +#define GCC_GPU_CFG_AHB_CLK 33 +#define GCC_GPU_GPLL0_CLK_SRC 34 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +#define GCC_GPU_IREF_EN 36 +#define GCC_GPU_MEMNOC_GFX_CLK 37 +#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +#define GCC_PCIE0_PHY_RCHNG_CLK 39 +#define GCC_PCIE1_PHY_RCHNG_CLK 40 +#define GCC_PCIE_0_AUX_CLK 41 +#define GCC_PCIE_0_AUX_CLK_SRC 42 +#define GCC_PCIE_0_CFG_AHB_CLK 43 +#define GCC_PCIE_0_CLKREF_EN 44 +#define GCC_PCIE_0_MSTR_AXI_CLK 45 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 46 +#define GCC_PCIE_0_PIPE_CLK 47 +#define GCC_PCIE_0_SLV_AXI_CLK 48 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 +#define GCC_PCIE_1_AUX_CLK 50 +#define GCC_PCIE_1_AUX_CLK_SRC 51 +#define GCC_PCIE_1_CFG_AHB_CLK 52 +#define GCC_PCIE_1_CLKREF_EN 53 +#define GCC_PCIE_1_MSTR_AXI_CLK 54 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 55 +#define GCC_PCIE_1_PIPE_CLK 56 +#define GCC_PCIE_1_SLV_AXI_CLK 57 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58 +#define GCC_PDM2_CLK 59 +#define GCC_PDM2_CLK_SRC 60 +#define GCC_PDM_AHB_CLK 61 +#define GCC_PDM_XO4_CLK 62 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 63 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 64 +#define GCC_QMIP_DISP_AHB_CLK 65 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 66 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68 +#define GCC_QUPV3_WRAP0_CORE_CLK 69 +#define GCC_QUPV3_WRAP0_S0_CLK 70 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S1_CLK 72 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S2_CLK 74 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S3_CLK 76 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77 +#define GCC_QUPV3_WRAP0_S4_CLK 78 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S5_CLK 80 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S6_CLK 82 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83 +#define GCC_QUPV3_WRAP0_S7_CLK 84 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86 +#define GCC_QUPV3_WRAP1_CORE_CLK 87 +#define GCC_QUPV3_WRAP1_S0_CLK 88 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S1_CLK 90 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S2_CLK 92 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S3_CLK 94 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S4_CLK 96 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S5_CLK 98 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 100 +#define GCC_QUPV3_WRAP2_CORE_CLK 101 +#define GCC_QUPV3_WRAP2_S0_CLK 102 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 103 +#define GCC_QUPV3_WRAP2_S1_CLK 104 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 105 +#define GCC_QUPV3_WRAP2_S2_CLK 106 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 107 +#define GCC_QUPV3_WRAP2_S3_CLK 108 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 109 +#define GCC_QUPV3_WRAP2_S4_CLK 110 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 111 +#define GCC_QUPV3_WRAP2_S5_CLK 112 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 113 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 114 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 115 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 116 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 117 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 118 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 119 +#define GCC_SDCC2_AHB_CLK 120 +#define GCC_SDCC2_APPS_CLK 121 +#define GCC_SDCC2_APPS_CLK_SRC 122 +#define GCC_SDCC4_AHB_CLK 123 +#define GCC_SDCC4_APPS_CLK 124 +#define GCC_SDCC4_APPS_CLK_SRC 125 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 126 +#define GCC_UFS_1_CLKREF_EN 127 +#define GCC_UFS_CARD_AHB_CLK 128 +#define GCC_UFS_CARD_AXI_CLK 129 +#define GCC_UFS_CARD_AXI_CLK_SRC 130 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 131 +#define GCC_UFS_CARD_ICE_CORE_CLK 132 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 133 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 134 +#define GCC_UFS_CARD_PHY_AUX_CLK 135 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 136 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 137 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 138 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 139 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 140 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 141 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 142 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 143 +#define GCC_UFS_PHY_AHB_CLK 144 +#define GCC_UFS_PHY_AXI_CLK 145 +#define GCC_UFS_PHY_AXI_CLK_SRC 146 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 147 +#define GCC_UFS_PHY_ICE_CORE_CLK 148 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 150 +#define GCC_UFS_PHY_PHY_AUX_CLK 151 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 152 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 153 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 154 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 155 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 157 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 158 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 159 +#define GCC_USB30_PRIM_MASTER_CLK 160 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 161 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 162 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164 +#define GCC_USB30_PRIM_SLEEP_CLK 165 +#define GCC_USB30_SEC_MASTER_CLK 166 +#define GCC_USB30_SEC_MASTER_CLK_SRC 167 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 168 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 169 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 170 +#define GCC_USB30_SEC_SLEEP_CLK 171 +#define GCC_USB3_PRIM_PHY_AUX_CLK 172 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 173 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 174 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 175 +#define GCC_USB3_SEC_CLKREF_EN 176 +#define GCC_USB3_SEC_PHY_AUX_CLK 177 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 178 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 179 +#define GCC_USB3_SEC_PHY_PIPE_CLK 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_AXI1_CLK 183 +#define GCC_VIDEO_XO_CLK 184 /* GCC resets */ #define GCC_CAMERA_BCR 0 #define GCC_DISPLAY_BCR 1 -#define GCC_DPM_BCR 2 -#define GCC_GPU_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PCIE_0_BCR 5 -#define GCC_PCIE_0_LINK_DOWN_BCR 6 -#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7 -#define GCC_PCIE_0_PHY_BCR 8 -#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9 -#define GCC_PCIE_1_BCR 10 -#define GCC_PCIE_1_LINK_DOWN_BCR 11 -#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12 -#define GCC_PCIE_1_PHY_BCR 13 -#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14 -#define GCC_PCIE_PHY_CFG_AHB_BCR 15 -#define GCC_PCIE_PHY_COM_BCR 16 -#define GCC_PDM_BCR 17 -#define GCC_QUPV3_WRAPPER_0_BCR 18 -#define GCC_QUPV3_WRAPPER_1_BCR 19 -#define GCC_QUPV3_WRAPPER_2_BCR 20 -#define GCC_QUSB2PHY_PRIM_BCR 21 -#define GCC_QUSB2PHY_SEC_BCR 22 -#define GCC_SDCC2_BCR 23 -#define GCC_SDCC4_BCR 24 -#define GCC_UFS_CARD_BCR 25 -#define GCC_UFS_PHY_BCR 26 -#define GCC_USB30_PRIM_BCR 27 -#define GCC_USB30_SEC_BCR 28 -#define GCC_USB3_DP_PHY_PRIM_BCR 29 -#define GCC_USB3_DP_PHY_SEC_BCR 30 -#define GCC_USB3_PHY_PRIM_BCR 31 -#define GCC_USB3_PHY_SEC_BCR 32 -#define GCC_USB3PHY_PHY_PRIM_BCR 33 -#define GCC_USB3PHY_PHY_SEC_BCR 34 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 35 -#define GCC_VIDEO_AXI0_CLK_ARES 36 -#define GCC_VIDEO_AXI1_CLK_ARES 37 -#define GCC_VIDEO_BCR 38 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PDM_BCR 16 +#define GCC_QUPV3_WRAPPER_0_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC2_BCR 22 +#define GCC_SDCC4_BCR 23 +#define GCC_UFS_CARD_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB30_SEC_BCR 27 +#define GCC_USB3_DP_PHY_PRIM_BCR 28 +#define GCC_USB3_DP_PHY_SEC_BCR 29 +#define GCC_USB3_PHY_PRIM_BCR 30 +#define GCC_USB3_PHY_SEC_BCR 31 +#define GCC_USB3PHY_PHY_PRIM_BCR 32 +#define GCC_USB3PHY_PHY_SEC_BCR 33 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34 +#define GCC_VIDEO_AXI0_CLK_ARES 35 +#define GCC_VIDEO_AXI1_CLK_ARES 36 +#define GCC_VIDEO_BCR 37 #endif