From 84a4f0a0e2f4c8f897629bedbce41eb8f6efb6c5 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 31 Mar 2020 14:06:46 -0700 Subject: [PATCH 1/2] ARM: dts: msm: Enable CPU voltage cooling device for lahaina Enable CPU voltage cooling device for APC1 cluster including cpu 4 and 7 for lahaina. This will enable thermal framework to achieve voltage reduction in APC1 rail by bringing down both gold and gold+ frequency based on voltage. Change-Id: I61b8767bb4c3999358d05e37903caaf144f46005 --- qcom/lahaina-thermal.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 44007fbc7d8e..313216d406ec 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -52,6 +52,14 @@ isens_vref_1p8-supply = <&pm8350c_l1_ao>; isens-vref-1p8-settings = <1800000 1800000 20000>; }; + + qcom,cpu-voltage-cdev { + compatible = "qcom,cc-cooling-devices"; + apc1_cluster: qcom,apc1-cluster { + qcom,cpus = <&CPU4 &CPU7>; + #cooling-cells = <2>; + }; + }; }; &msm_gpu { From efb4dcff49c81c832d9eb000d02932b6592170db Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 31 Mar 2020 14:13:27 -0700 Subject: [PATCH 2/2] ARM: dts: msm: use voltage mitigation for pop mem in lahaina Pop mem rule right now mitigates gold and gold+ CPUs separately based on frequency. Use the voltage mitigation device instead to bring the APC1 voltage for lahaina. Change-Id: I62103a825a8b6675104777ad0735f9d3515192c1 --- qcom/lahaina-thermal.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 313216d406ec..061a91350676 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -661,17 +661,10 @@ }; cooling-maps { - pop_cdev4 { + pop_cdev { trip = <&pop_trip>; cooling-device = - <&CPU4 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - pop_cdev7 { - trip = <&pop_trip>; - cooling-device = - <&CPU7 THERMAL_NO_LIMIT + <&apc1_cluster THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; };