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drm/i915/skl: Disable coarse power gating up until F0

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There is conflicting info between E0 and F0 steppings
for this workarounds. Trust more authoritative source and
be conservative and extend also for F0.

This prevents numerous (>50) gpu hangs with SKL GT4e
during piglit run.

References: HSD: gen9lp/2134184
Cc: Sagar Arun Kamble <[email protected]>
Signed-off-by: Mika Kuoppala <[email protected]>
Reviewed-by: Sagar Arun Kamble <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 6686ece19f)
Cc: [email protected] # v4.3+
Signed-off-by: Jani Nikula <[email protected]>
This commit is contained in:
Mika Kuoppala 2015-12-07 18:29:44 +02:00 • committed by Jani Nikula
commit 344df9809f
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -4825,7 +4825,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
*/
if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
I915_WRITE(GEN9_PG_ENABLE, 0);
else
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?