diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index abb25ed73c71..5cf831e71439 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -859,9 +859,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_0_smmu_clk", 0, false, false},
 	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_0_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -879,9 +879,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_1_smmu_clk", 0, false, false},
 	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_1_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -899,9 +899,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_2_smmu_clk", 0, false, false},
 	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_2_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},