From 34e5e7dbf38d87875c35f3aea15c5d3a473211cd Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Fri, 31 Jul 2020 18:37:07 +0530 Subject: [PATCH] ARM: dts: msm: update dp dt properties for shima Update the DP DT node properties for Shima target. Change-Id: I7eaea8148756d39f67491a418432173fa2f8b758 --- display/shima-sde.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 0b991af1c804..8705b8ab8a46 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -288,8 +288,8 @@ cell-index = <0>; compatible = "qcom,dp-display"; - /* usb-phy = <&usb_qmp_dp_phy>; */ - /* qcom,dp-aux-switch = <&fsa4480>; */ + usb-phy = <&usb_qmp_dp_phy>; + qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; @@ -316,16 +316,16 @@ interrupts = <12 0>; #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",