qcacld-3.0: Remove obsolete "TX Power Control" configuration

Currently cfg.ini supports a "gEnableAutomaticTxPowerControl"
configuration item, and this is used to override the
WNI_CFG_TX_PWR_CTRL_ENABLE entry in the MAC CFG database.  However
this MAC CFG database entry is no longer in use, so remove the
obsolete support for this configuration item.

Change-Id: I8ca653bc75c18692519ff1d88f52441e7f0375f5
CRs-Fixed: 1060597
This commit is contained in:
Jeff Johnson 2016-08-29 10:40:38 -07:00
commit 3507908a02
5 changed files with 0 additions and 33 deletions

View file

@ -1470,11 +1470,6 @@ typedef enum {
#define CFG_IGNORE_DYNAMIC_DTIM_IN_P2P_MODE_MAX (1)
#define CFG_IGNORE_DYNAMIC_DTIM_IN_P2P_MODE_DEFAULT (0)
#define CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_NAME "gEnableAutomaticTxPowerControl"
#define CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_MIN (0)
#define CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_MAX (1)
#define CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_DEFAULT (1)
#define CFG_SHORT_GI_40MHZ_NAME "gShortGI40Mhz"
#define CFG_SHORT_GI_40MHZ_MIN 0
#define CFG_SHORT_GI_40MHZ_MAX 1
@ -3775,7 +3770,6 @@ struct hdd_config {
uint8_t enableDFSChnlScan;
uint8_t enable_dfs_pno_chnl_scan;
uint8_t enableDynamicDTIM;
uint8_t enableAutomaticTxPowerControl;
uint8_t ShortGI40MhzEnable;
eHddLinkSpeedReportType reportMaxLinkSpeed;
int32_t linkSpeedRssiHigh;

View file

@ -1868,14 +1868,6 @@ REG_TABLE_ENTRY g_registry_table[] = {
CFG_ENABLE_DYNAMIC_DTIM_MIN,
CFG_ENABLE_DYNAMIC_DTIM_MAX),
REG_VARIABLE(CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_NAME,
WLAN_PARAM_Integer,
struct hdd_config, enableAutomaticTxPowerControl,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_DEFAULT,
CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_MIN,
CFG_ENABLE_AUTOMATIC_TX_POWER_CONTROL_MAX),
REG_VARIABLE(CFG_SHORT_GI_40MHZ_NAME, WLAN_PARAM_Integer,
struct hdd_config, ShortGI40MhzEnable,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
@ -6595,14 +6587,6 @@ bool hdd_update_config_dat(hdd_context_t *pHddCtx)
"Could not pass on WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD to CFG");
}
if (sme_cfg_set_int(pHddCtx->hHal, WNI_CFG_TX_PWR_CTRL_ENABLE,
pConfig->enableAutomaticTxPowerControl)
== QDF_STATUS_E_FAILURE) {
fStatus = false;
hddLog(LOGE,
"Could not pass on WNI_CFG_TX_PWR_CTRL_ENABLE to CFG");
}
if (sme_cfg_set_int
(pHddCtx->hHal, WNI_CFG_ENABLE_MC_ADDR_LIST,
pConfig->fEnableMCAddrList) == QDF_STATUS_E_FAILURE) {

View file

@ -208,7 +208,6 @@ enum {
WNI_CFG_LOW_GAIN_OVERRIDE,
WNI_CFG_ENABLE_PHY_AGC_LISTEN_MODE,
WNI_CFG_SINGLE_TID_RC,
WNI_CFG_TX_PWR_CTRL_ENABLE,
WNI_CFG_MCAST_BCAST_FILTER_SETTING,
WNI_CFG_DYNAMIC_PS_POLL_VALUE,
WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT,
@ -1091,10 +1090,6 @@ enum {
#define WNI_CFG_SINGLE_TID_RC_STAMAX 1
#define WNI_CFG_SINGLE_TID_RC_STADEF 1
#define WNI_CFG_TX_PWR_CTRL_ENABLE_STAMIN 0
#define WNI_CFG_TX_PWR_CTRL_ENABLE_STAMAX 1
#define WNI_CFG_TX_PWR_CTRL_ENABLE_STADEF 1
#define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMIN 0
#define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMAX 3
#define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STADEF 0

View file

@ -274,7 +274,6 @@ unsigned char *g_cfg_param_name[] = {
(unsigned char *)"RPE_AGING_THRESHOLD_FOR_AC3_REG",
(unsigned char *)"NO_OF_ONCHIP_REORDER_SESSIONS",
(unsigned char *)"SINGLE_TID_RC",
(unsigned char *)"TX_PWR_CTRL_ENABLE",
(unsigned char *)"MCAST_BCAST_FILTER_SETTING",
(unsigned char *)"BTC_DHCP_BT_SLOTS_TO_BLOCK",
(unsigned char *)"DYNAMIC_PS_POLL_VALUE",

View file

@ -933,11 +933,6 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
WNI_CFG_SINGLE_TID_RC_STAMIN,
WNI_CFG_SINGLE_TID_RC_STAMAX,
WNI_CFG_SINGLE_TID_RC_STADEF},
{WNI_CFG_TX_PWR_CTRL_ENABLE,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_TX_PWR_CTRL_ENABLE_STAMIN,
WNI_CFG_TX_PWR_CTRL_ENABLE_STAMAX,
WNI_CFG_TX_PWR_CTRL_ENABLE_STADEF},
{WNI_CFG_MCAST_BCAST_FILTER_SETTING,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
CFG_CTL_NTF_HAL,