mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
dmaengine updates for 4.3-rc1
This time we have aded a new capability for scatter-gathered memset using
dmaengine APIs. This is supported in xdmac & hdmac drivers
We have added support for reusing descriptors for examples like video
buffers etc. Driver will follow
The behaviour of descriptor ack has been clarified and documented
New devices added are:
- dma controller in sun[457]i SoCs
- lpc18xx dmamux
- ZTE ZX296702 dma controller
- Analog Devices AXI-DMAC DMA controller
- eDMA support for dma-crossbar
- imx6sx support in imx-sdma driver
- imx-sdma device to device support
Others
- jz4780 fixes
- ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is
deprecated and fixes
- ACPI support in X-Gene DMA engine driver
- ipu irq fixes
- mvxor fixes
- minor fixes spread thru drivers
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Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This time we have aded a new capability for scatter-gathered memset
using dmaengine APIs. This is supported in xdmac & hdmac drivers
We have added support for reusing descriptors for examples like video
buffers etc. Driver will follow
The behaviour of descriptor ack has been clarified and documented
New devices added are:
- dma controller in sun[457]i SoCs
- lpc18xx dmamux
- ZTE ZX296702 dma controller
- Analog Devices AXI-DMAC DMA controller
- eDMA support for dma-crossbar
- imx6sx support in imx-sdma driver
- imx-sdma device to device support
Other:
- jz4780 fixes
- ioatdma large refactor and cleanup for removal of ioat v1 and v2
which is deprecated and fixes
- ACPI support in X-Gene DMA engine driver
- ipu irq fixes
- mvxor fixes
- minor fixes spread thru drivers"
[ The Kconfig and Makefile entries got re-sorted alphabetically, and I
handled the conflict with the new Intel integrated IDMA driver by
slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in
order to keep the Intel entries together. I think it might be a good
idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make
the sorting be a true sort, not this mismash.
Also, this merge disables the COMPILE_TEST for the sun4i DMA
controller, because it does not compile cleanly at all. - Linus ]
* tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs
dmaengine :ipu: change ipu_irq_handler() to remove compile warning
dmaengine: ioatdma: Fix variable array length
dmaengine: ioatdma: fix sparse "error" with prep lock
dmaengine: hdmac: Add memset capabilities
dmaengine: sort the sh Makefile
dmaengine: sort the sh Kconfig
dmaengine: sort the dw Kconfig
dmaengine: sort the Kconfig
dmaengine: sort the makefile
drivers/dma: make mv_xor.c driver explicitly non-modular
dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller
devicetree: Add bindings documentation for Analog Devices AXI-DMAC
dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
dmaengine: ioatdma: fix coccinelle warning
dmaengine: ioatdma: fix zero day warning on incompatible pointer type
dmaengine: tegra-apb: Simplify locking for device using global pause
dmaengine: tegra-apb: Remove unnecessary return statements and variables
dmaengine: tegra-apb: Avoid unnecessary channel base address calculation
dmaengine: tegra-apb: Remove unused variables
...
This commit is contained in:
Linus Torvalds
commit
3527122745
61 changed files with 8012 additions and 5235 deletions
61
Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
Normal file
61
Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
Normal file
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@ -0,0 +1,61 @@
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Analog Device AXI-DMAC DMA controller
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Required properties:
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- compatible: Must be "adi,axi-dmac-1.00.a".
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- reg: Specification for the controllers memory mapped register map.
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- interrupts: Specification for the controllers interrupt.
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- clocks: Phandle and specifier to the controllers AXI interface clock
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- #dma-cells: Must be 1.
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Required sub-nodes:
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- adi,channels: This sub-node must contain a sub-node for each DMA channel. For
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the channel sub-nodes the following bindings apply. They must match the
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configuration options of the peripheral as it was instantiated.
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Required properties for adi,channels sub-node:
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- #size-cells: Must be 0
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- #address-cells: Must be 1
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Required channel sub-node properties:
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- reg: Which channel this node refers to.
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- adi,length-width: Width of the DMA transfer length register.
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- adi,source-bus-width,
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adi,destination-bus-width: Width of the source or destination bus in bits.
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- adi,source-bus-type,
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adi,destination-bus-type: Type of the source or destination bus. Must be one
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of the following:
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0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
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1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
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2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
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Optional channel properties:
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- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
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transfers.
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- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
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DMA clients connected to the AXI-DMAC DMA controller must use the format
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described in the dma.txt file using a one-cell specifier. The value of the
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specifier refers to the DMA channel index.
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Example:
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dma: dma@7c420000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x7c420000 0x10000>;
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interrupts = <0 57 0>;
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clocks = <&clkc 16>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-width = <32>;
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adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
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adi,destination-bus-width = <64>;
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adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
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};
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};
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};
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54
Documentation/devicetree/bindings/dma/arm-pl08x.txt
Normal file
54
Documentation/devicetree/bindings/dma/arm-pl08x.txt
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@ -0,0 +1,54 @@
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* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
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Required properties:
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- compatible: "arm,pl080", "arm,primecell";
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"arm,pl081", "arm,primecell";
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- reg: Address range of the PL08x registers
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- interrupt: The PL08x interrupt number
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- clocks: The clock running the IP core clock
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- clock-names: Must contain "apb_pclk"
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- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
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- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
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- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
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- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
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- #dma-cells: must be <2>. First cell should contain the DMA request,
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second cell should contain either 1 or 2 depending on
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which AHB master that is used.
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Optional properties:
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- dma-channels: contains the total number of DMA channels supported by the DMAC
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- dma-requests: contains the total number of DMA requests supported by the DMAC
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- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
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64, 128 or 256 bytes are legal values
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- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
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values
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Clients
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Required properties:
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- dmas: List of DMA controller phandle, request channel and AHB master id
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- dma-names: Names of the aforementioned requested channels
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Example:
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dmac0: dma-controller@10130000 {
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compatible = "arm,pl080", "arm,primecell";
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reg = <0x10130000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <15>;
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clocks = <&hclkdma0>;
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clock-names = "apb_pclk";
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lli-bus-interface-ahb1;
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lli-bus-interface-ahb2;
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mem-bus-interface-ahb2;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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#dma-cells = <2>;
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};
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device@40008000 {
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...
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dmas = <&dmac0 0 2
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&dmac0 1 2>;
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dma-names = "tx", "rx";
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...
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};
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54
Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt
Normal file
54
Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt
Normal file
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@ -0,0 +1,54 @@
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NXP LPC18xx/43xx DMA MUX (DMA request router)
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Required properties:
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- compatible: "nxp,lpc1850-dmamux"
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- reg: Memory map for accessing module
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- #dma-cells: Should be set to <3>.
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* 1st cell contain the master dma request signal
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* 2nd cell contain the mux value (0-3) for the peripheral
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* 3rd cell contain either 1 or 2 depending on the AHB
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master used.
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- dma-requests: Number of DMA requests for the mux
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- dma-masters: phandle pointing to the DMA controller
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The DMA controller node need to have the following poroperties:
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- dma-requests: Number of DMA requests the controller can handle
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Example:
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dmac: dma@40002000 {
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compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
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arm,primecell-periphid = <0x00041080>;
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reg = <0x40002000 0x1000>;
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interrupts = <2>;
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clocks = <&ccu1 CLK_CPU_DMA>;
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clock-names = "apb_pclk";
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#dma-cells = <2>;
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dma-channels = <8>;
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dma-requests = <16>;
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lli-bus-interface-ahb1;
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lli-bus-interface-ahb2;
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mem-bus-interface-ahb1;
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mem-bus-interface-ahb2;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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};
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dmamux: dma-mux {
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compatible = "nxp,lpc1850-dmamux";
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#dma-cells = <3>;
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dma-requests = <64>;
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dma-masters = <&dmac>;
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};
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uart0: serial@40081000 {
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compatible = "nxp,lpc1850-uart", "ns16550a";
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reg = <0x40081000 0x1000>;
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reg-shift = <2>;
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interrupts = <24>;
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clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
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clock-names = "uartclk", "reg";
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dmas = <&dmamux 1 1 2
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&dmamux 2 1 2>;
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dma-names = "tx", "rx";
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};
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@ -12,10 +12,13 @@ XOR engine has. Those sub-nodes have the following required
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properties:
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- interrupts: interrupt of the XOR channel
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And the following optional properties:
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The sub-nodes used to contain one or several of the following
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properties, but they are now deprecated:
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- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
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- dmacap,memset to indicate that the XOR channel is capable of memset operations
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- dmacap,xor to indicate that the XOR channel is capable of xor operations
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- dmacap,interrupt to indicate that the XOR channel is capable of
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generating interrupts
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Example:
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@ -28,13 +31,8 @@ xor@d0060900 {
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xor00 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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46
Documentation/devicetree/bindings/dma/sun4i-dma.txt
Normal file
46
Documentation/devicetree/bindings/dma/sun4i-dma.txt
Normal file
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@ -0,0 +1,46 @@
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Allwinner A10 DMA Controller
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This driver follows the generic DMA bindings defined in dma.txt.
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Required properties:
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- compatible: Must be "allwinner,sun4i-a10-dma"
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- reg: Should contain the registers base address and length
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- interrupts: Should contain a reference to the interrupt used by this device
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- clocks: Should contain a reference to the parent AHB clock
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- #dma-cells : Should be 2, first cell denoting normal or dedicated dma,
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second cell holding the request line number.
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Example:
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ahb_gates 6>;
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#dma-cells = <2>;
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};
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Clients:
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DMA clients connected to the Allwinner A10 DMA controller must use the
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format described in the dma.txt file, using a three-cell specifier for
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each channel: a phandle plus two integer cells.
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The three cells in order are:
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1. A phandle pointing to the DMA controller.
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2. Whether it is using normal (0) or dedicated (1) channels
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3. The port ID as specified in the datasheet
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Example:
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spi2: spi@01c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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interrupts = <0 12 4>;
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clocks = <&ahb_gates 22>, <&spi2_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 1 29>, <&dma 1 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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38
Documentation/devicetree/bindings/dma/zxdma.txt
Normal file
38
Documentation/devicetree/bindings/dma/zxdma.txt
Normal file
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@ -0,0 +1,38 @@
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* ZTE ZX296702 DMA controller
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Required properties:
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- compatible: Should be "zte,zx296702-dma"
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain one interrupt shared by all channel
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- #dma-cells: see dma.txt, should be 1, para number
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- dma-channels: physical channels supported
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- dma-requests: virtual channels supported, each virtual channel
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have specific request line
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- clocks: clock required
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Example:
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Controller:
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dma: dma-controller@0x09c00000{
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compatible = "zte,zx296702-dma";
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reg = <0x09c00000 0x1000>;
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clocks = <&topclk ZX296702_DMA_ACLK>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <24>;
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dma-requests = <24>;
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};
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Client:
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Use specific request line passing from dmax
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For example, spdif0 tx channel request line is 4
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spdif0: spdif0@0b004000 {
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#sound-dai-cells = <0>;
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compatible = "zte,zx296702-spdif";
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reg = <0x0b004000 0x1000>;
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clocks = <&lsp0clk ZX296702_SPDIF0_DIV>;
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clock-names = "tx";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 4>;
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dma-names = "tx";
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}
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Loading…
Reference in a new issue