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clk: exynos-audss: add support for Exynos 5420

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The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Acked-by: Kukjin Kim <[email protected]>
Signed-off-by: Tomasz Figa <[email protected]>
This commit is contained in:
Andrew Bresticker 2013-09-25 14:12:51 -07:00 • committed by Tomasz Figa
commit 3538a2cf0e
3 changed files with 40 additions and 10 deletions
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3
include/dt-bindings/clk/exynos-audss-clk.h
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@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S 7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM 9
#define EXYNOS_ADMA 10
#define EXYNOS_AUDSS_MAX_CLKS 10
#define EXYNOS_AUDSS_MAX_CLKS 11
#endif