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clk: exynos5250: add clock ID for div_pcm0

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There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.

Signed-off-by: Andrew Bresticker <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Acked-by: Kukjin Kim <[email protected]>
Signed-off-by: Tomasz Figa <[email protected]>
This commit is contained in:
Andrew Bresticker 2013-09-25 14:12:49 -07:00 • committed by Tomasz Figa
commit 35399dda01
3 changed files with 3 additions and 1 deletions
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1
include/dt-bindings/clock/exynos5250.h
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@ -55,6 +55,7 @@
#define CLK_DIV_I2S1 157
#define CLK_DIV_I2S2 158
#define CLK_SCLK_HDMIPHY 159
#define CLK_DIV_PCM0 160
/* gate clocks */
#define CLK_GSCL0 256