diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi
index 8b540370ae41..443762b291b8 100644
--- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi
+++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi
@@ -60,7 +60,7 @@
 					39 01 00 00 00 00 02 b0 80
 					39 01 00 00 00 00 02 e6 00
 					39 01 00 00 00 00 02 b0 00
-					39 01 00 00 00 00 06 B6 6c 00 06 23 a6
+					39 01 00 00 00 00 06 B6 6c 00 06 23 af
 					39 01 00 00 00 00 02 B4 20
 					39 01 00 00 00 00 19 cf 64 0b 00 00 00
 					   00 00 00 08 00 0b 77 01 01 01 01 01
diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi
index 27325abd1380..7006dffcdd0b 100644
--- a/display/shima-sde-display-common.dtsi
+++ b/display/shima-sde-display-common.dtsi
@@ -5,6 +5,7 @@
 #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
 #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi"
 #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi"
 #include "dsi-panel-sim-video.dtsi"
 #include <dt-bindings/clock/mdss-5nm-pll-clk.h>
 
@@ -171,6 +172,19 @@
 	};
 };
 
+&dsi_r66451_amoled_cmd_cphy {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"cphy_byte_clk0", "cphy_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04
+					19 03 02 04 00 00 00];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
 &dsi_r66451_amoled_cmd {
 	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
 	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi
index 3c07eaa27ac0..54c0f4fa4349 100644
--- a/display/shima-sde-display-idp.dtsi
+++ b/display/shima-sde-display-idp.dtsi
@@ -80,6 +80,16 @@
 	qcom,platform-en-gpio = <&tlmm 47 0>;
 };
 
+&dsi_r66451_amoled_cmd_cphy {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 24 0>;
+};
+
 &dsi_sim_vid {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";