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[MIPS] PMC MSP71xx core platform
Patch to add core platform support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Marc St-Jean
Ralf Baechle
parent
a4b156d47d
commit
35832e26f9
16 changed files with 3083 additions and 0 deletions
151
include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
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151
include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
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@ -0,0 +1,151 @@
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/*
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* Defines for the MSP interrupt controller.
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*
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* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
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* Author: Carsten Langgaard, carstenl@mips.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#ifndef _MSP_CIC_INT_H
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#define _MSP_CIC_INT_H
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/*
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* The PMC-Sierra CIC interrupts are all centrally managed by the
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* CIC sub-system.
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* We attempt to keep the interrupt numbers as consistent as possible
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* across all of the MSP devices, but some differences will creep in ...
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* The interrupts which are directly forwarded to the MIPS core interrupts
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* are assigned interrupts in the range 0-7, interrupts cascaded through
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* the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
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* (MSP_INT_CIC). Currently we don't really distinguish between VPE1
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* and VPE0 (or thread contexts for that matter). Will have to fix.
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* The PER interrupts are assigned interrupts in the range 40-71.
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*/
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/*
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* IRQs directly forwarded to the CPU
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*/
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#define MSP_MIPS_INTBASE 0
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#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
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#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
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#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
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#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
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#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
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#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
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#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
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#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
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/*
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* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
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* These defines should be tied to the register definitions for the CIC
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* interrupt routine. For now, just use hard-coded values.
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*/
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#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
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#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
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/* External interrupt 0 */
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#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
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/* External interrupt 1 */
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#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
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/* External interrupt 2 */
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#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
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/* External interrupt 3 */
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#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
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/* CPU interface interrupt */
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#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
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/* External interrupt 4 */
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#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
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/* Cascaded IRQ for USB */
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#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
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/* Sec engine mailbox IRQ */
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#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
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/* External interrupt 5 */
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#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
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/* TDM interrupt */
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#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
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/* Cascaded IRQ for MAC 0 */
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#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
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/* Cascaded IRQ for MAC 1 */
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#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
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/* Cascaded IRQ for sec engine */
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#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
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/* Peripheral interrupt */
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#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
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/* SLP timer 0 */
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#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
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/* SLP timer 1 */
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#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
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/* SLP timer 2 */
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#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
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/* VPE0 MIPS timer */
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#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
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/* Block Copy */
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#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
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/* UART 0 */
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#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
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/* PCI subsystem */
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#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
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/* External interrupt 5 */
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#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
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/* PCI Message Signal */
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#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
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/* Cascaded ADSL2+ SAR IRQ */
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#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
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/* ADSL2+ IRQ */
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#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
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/* SLP error condition */
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#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
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/* VPE1 MIPS timer */
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#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
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/* VPE0 Performance counter */
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#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
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/* VPE1 Performance counter */
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#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
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/* External interrupt 5 */
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#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
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/* VPE0 Software interrupt */
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#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
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/* VPE0 Software interrupt */
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/*
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* IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
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*/
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#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
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/* Reserved 0-1 */
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#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
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/* UART 1 */
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/* Reserved 3-5 */
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#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
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/* 2-wire */
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#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
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/* Peripheral timer block out 0 */
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#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
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/* Peripheral timer block out 1 */
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/* Reserved 9 */
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#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
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/* SPI RX complete */
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#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
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/* SPI TX complete */
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#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
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/* GPIO */
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#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
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/* Peripheral error */
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/* Reserved 14-31 */
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#endif /* !_MSP_CIC_INT_H */
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43
include/asm-mips/pmc-sierra/msp71xx/msp_int.h
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43
include/asm-mips/pmc-sierra/msp71xx/msp_int.h
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/*
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* Defines for the MSP interrupt handlers.
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*
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* Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
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* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#ifndef _MSP_INT_H
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#define _MSP_INT_H
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/*
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* The PMC-Sierra MSP product line has at least two different interrupt
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* controllers, the SLP register based scheme and the CIC interrupt
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* controller block mechanism. This file distinguishes between them
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* so that devices see a uniform interface.
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*/
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#if defined(CONFIG_IRQ_MSP_SLP)
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#include "msp_slp_int.h"
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#elif defined(CONFIG_IRQ_MSP_CIC)
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#include "msp_cic_int.h"
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#else
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#error "What sort of interrupt controller does *your* MSP have?"
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#endif
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#endif /* !_MSP_INT_H */
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176
include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
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176
include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
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/*
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* MIPS boards bootprom interface for the Linux kernel.
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*
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Author: Carsten Langgaard, carstenl@mips.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#ifndef _ASM_MSP_PROM_H
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#define _ASM_MSP_PROM_H
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#include <linux/types.h>
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#define DEVICEID "deviceid"
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#define FEATURES "features"
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#define PROM_ENV "prom_env"
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#define PROM_ENV_FILE "/proc/"PROM_ENV
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#define PROM_ENV_SIZE 256
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#define CPU_DEVID_FAMILY 0x0000ff00
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#define CPU_DEVID_REVISION 0x000000ff
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#define FPGA_IS_POLO(revision) \
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(((revision >= 0xb0) && (revision < 0xd0)))
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#define FPGA_IS_5000(revision) \
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((revision >= 0x80) && (revision <= 0x90))
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#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
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#define FPGA_IS_DUET(revision) \
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(((revision >= 0xa0) && (revision < 0xb0)))
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#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
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#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
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#define MACHINE_TYPE_POLO "POLO"
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#define MACHINE_TYPE_DUET "DUET"
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#define MACHINE_TYPE_ZEUS "ZEUS"
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#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
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#define MACHINE_TYPE_MSP5000 "MSP5000"
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#define MACHINE_TYPE_MSP4200 "MSP4200"
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#define MACHINE_TYPE_MSP7120 "MSP7120"
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#define MACHINE_TYPE_MSP7130 "MSP7130"
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#define MACHINE_TYPE_OTHER "OTHER"
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#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
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#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
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#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
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#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
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#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
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#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
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#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
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#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
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/* Device Family definitions */
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#define FAMILY_FPGA 0x0000
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#define FAMILY_ZEUS 0x1000
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#define FAMILY_POLO 0x2000
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#define FAMILY_DUET 0x4000
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#define FAMILY_TRIAD 0x5000
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#define FAMILY_MSP4200 0x4200
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#define FAMILY_MSP4200_FPGA 0x4f00
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#define FAMILY_MSP7100 0x7100
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#define FAMILY_MSP7100_FPGA 0x7f00
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/* Device Type definitions */
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#define TYPE_MSP7120 0x7120
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#define TYPE_MSP7130 0x7130
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#define ENET_KEY 'E'
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#define ENETTXD_KEY 'e'
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#define PCI_KEY 'P'
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#define PCIMUX_KEY 'p'
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#define SEC_KEY 'S'
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#define SPAD_KEY 'D'
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#define TDM_KEY 'T'
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#define ZSP_KEY 'Z'
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#define FEATURE_NOEXIST '-'
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#define FEATURE_EXIST '+'
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#define ENET_MII 'M'
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#define ENET_RMII 'R'
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#define ENETTXD_FALLING 'F'
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#define ENETTXD_RISING 'R'
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#define PCI_HOST 'H'
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#define PCI_PERIPHERAL 'P'
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#define PCIMUX_FULL 'F'
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#define PCIMUX_SINGLE 'S'
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#define SEC_DUET 'D'
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#define SEC_POLO 'P'
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#define SEC_SLOW 'S'
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#define SEC_TRIAD 'T'
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#define SPAD_POLO 'P'
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#define TDM_DUET 'D' /* DUET TDMs might exist */
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#define TDM_POLO 'P' /* POLO TDMs might exist */
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#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
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#define ZSP_DUET 'D' /* one DUET zsp engine */
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#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
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extern char *prom_getcmdline(void);
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extern char *prom_getenv(char *name);
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extern void prom_init_cmdline(void);
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extern void prom_meminit(void);
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extern void prom_fixup_mem_map(unsigned long start_mem,
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unsigned long end_mem);
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#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
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extern bool get_ramroot(void **start, unsigned long *size);
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#endif
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extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
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extern unsigned long get_deviceid(void);
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extern char identify_enet(unsigned long interface_num);
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extern char identify_enetTxD(unsigned long interface_num);
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extern char identify_pci(void);
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extern char identify_sec(void);
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extern char identify_spad(void);
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extern char identify_sec(void);
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extern char identify_tdm(void);
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extern char identify_zsp(void);
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extern unsigned long identify_family(void);
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extern unsigned long identify_revision(void);
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/*
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* The following macro calls prom_printf and puts the format string
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* into an init section so it can be reclaimed.
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*/
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#define ppfinit(f, x...) \
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do { \
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static char _f[] __initdata = KERN_INFO f; \
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printk(_f, ## x); \
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} while (0)
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/* Memory descriptor management. */
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#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
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enum yamon_memtypes {
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yamon_dontuse,
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yamon_prom,
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yamon_free,
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};
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struct prom_pmemblock {
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unsigned long base; /* Within KSEG0. */
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unsigned int size; /* In bytes. */
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unsigned int type; /* free or prom memory */
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};
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extern int prom_argc;
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extern char **prom_argv;
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extern char **prom_envp;
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extern int *prom_vec;
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extern struct prom_pmemblock *prom_getmdesc(void);
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#endif /* !_ASM_MSP_PROM_H */
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236
include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
Normal file
236
include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
Normal file
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/*
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* SMP/VPE-safe functions to access "registers" (see note).
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*
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* NOTES:
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* - These macros use ll/sc instructions, so it is your responsibility to
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* ensure these are available on your platform before including this file.
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* - The MIPS32 spec states that ll/sc results are undefined for uncached
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* accesses. This means they can't be used on HW registers accessed
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* through kseg1. Code which requires these macros for this purpose must
|
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* front-end the registers with cached memory "registers" and have a single
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* thread update the actual HW registers.
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* - A maximum of 2k of code can be inserted between ll and sc. Every
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* memory accesses between the instructions will increase the chance of
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* sc failing and having to loop.
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* - When using custom_read_reg32/custom_write_reg32 only perform the
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* necessary logical operations on the register value in between these
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* two calls. All other logic should be performed before the first call.
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* - There is a bug on the R10000 chips which has a workaround. If you
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* are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
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* to be non-zero. If you are using this header from within linux, you may
|
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* include <asm/war.h> before including this file to have this defined
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* appropriately for you.
|
||||
*
|
||||
* Copyright 2005-2007 PMC-Sierra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., 675
|
||||
* Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_REGOPS_H__
|
||||
#define __ASM_REGOPS_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/war.h>
|
||||
|
||||
#ifndef R10000_LLSC_WAR
|
||||
#define R10000_LLSC_WAR 0
|
||||
#endif
|
||||
|
||||
#if R10000_LLSC_WAR == 1
|
||||
#define __beqz "beqzl "
|
||||
#else
|
||||
#define __beqz "beqz "
|
||||
#endif
|
||||
|
||||
#ifndef _LINUX_TYPES_H
|
||||
typedef unsigned int u32;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Sets all the masked bits to the corresponding value bits
|
||||
*/
|
||||
static inline void set_value_reg32(volatile u32 *const addr,
|
||||
u32 const mask,
|
||||
u32 const value)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set mips3 \n"
|
||||
"1: ll %0, %1 # set_value_reg32 \n"
|
||||
" and %0, %2 \n"
|
||||
" or %0, %3 \n"
|
||||
" sc %0, %1 \n"
|
||||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=m" (*addr)
|
||||
: "ir" (~mask), "ir" (value), "m" (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets all the masked bits to '1'
|
||||
*/
|
||||
static inline void set_reg32(volatile u32 *const addr,
|
||||
u32 const mask)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set mips3 \n"
|
||||
"1: ll %0, %1 # set_reg32 \n"
|
||||
" or %0, %2 \n"
|
||||
" sc %0, %1 \n"
|
||||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=m" (*addr)
|
||||
: "ir" (mask), "m" (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets all the masked bits to '0'
|
||||
*/
|
||||
static inline void clear_reg32(volatile u32 *const addr,
|
||||
u32 const mask)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set mips3 \n"
|
||||
"1: ll %0, %1 # clear_reg32 \n"
|
||||
" and %0, %2 \n"
|
||||
" sc %0, %1 \n"
|
||||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=m" (*addr)
|
||||
: "ir" (~mask), "m" (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
* Toggles all masked bits from '0' to '1' and '1' to '0'
|
||||
*/
|
||||
static inline void toggle_reg32(volatile u32 *const addr,
|
||||
u32 const mask)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set mips3 \n"
|
||||
"1: ll %0, %1 # toggle_reg32 \n"
|
||||
" xor %0, %2 \n"
|
||||
" sc %0, %1 \n"
|
||||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=m" (*addr)
|
||||
: "ir" (mask), "m" (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
* Read all masked bits others are returned as '0'
|
||||
*/
|
||||
static inline u32 read_reg32(volatile u32 *const addr,
|
||||
u32 const mask)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" lw %0, %1 # read \n"
|
||||
" and %0, %2 # mask \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp)
|
||||
: "m" (*addr), "ir" (mask));
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
/*
|
||||
* blocking_read_reg32 - Read address with blocking load
|
||||
*
|
||||
* Uncached writes need to be read back to ensure they reach RAM.
|
||||
* The returned value must be 'used' to prevent from becoming a
|
||||
* non-blocking load.
|
||||
*/
|
||||
static inline u32 blocking_read_reg32(volatile u32 *const addr)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" lw %0, %1 # read \n"
|
||||
" move %0, %0 # block \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp)
|
||||
: "m" (*addr));
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
/*
|
||||
* For special strange cases only:
|
||||
*
|
||||
* If you need custom processing within a ll/sc loop, use the following macros
|
||||
* VERY CAREFULLY:
|
||||
*
|
||||
* u32 tmp; <-- Define a variable to hold the data
|
||||
*
|
||||
* custom_read_reg32(address, tmp); <-- Reads the address and put the value
|
||||
* in the 'tmp' variable given
|
||||
*
|
||||
* From here on out, you are (basicly) atomic, so don't do anything too
|
||||
* fancy!
|
||||
* Also, this code may loop if the end of this block fails to write
|
||||
* everything back safely due do the other CPU, so do NOT do anything
|
||||
* with side-effects!
|
||||
*
|
||||
* custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
|
||||
*/
|
||||
#define custom_read_reg32(address, tmp) \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set mips3 \n" \
|
||||
"1: ll %0, %1 #custom_read_reg32 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (tmp), "=m" (*address) \
|
||||
: "m" (*address))
|
||||
|
||||
#define custom_write_reg32(address, tmp) \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set mips3 \n" \
|
||||
" sc %0, %1 #custom_write_reg32 \n" \
|
||||
" "__beqz"%0, 1b \n" \
|
||||
" nop \n" \
|
||||
" .set pop \n" \
|
||||
: "=&r" (tmp), "=m" (*address) \
|
||||
: "0" (tmp), "m" (*address))
|
||||
|
||||
#endif /* __ASM_REGOPS_H__ */
|
||||
667
include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
Normal file
667
include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
Normal file
|
|
@ -0,0 +1,667 @@
|
|||
/*
|
||||
* Defines for the address space, registers and register configuration
|
||||
* (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
|
||||
* This file contains addess maps for all the devices in the line of
|
||||
* products but only has register definitions and configuration masks for
|
||||
* registers which aren't definitely associated with any device. Things
|
||||
* like clock settings, reset access, the ELB etc. Individual device
|
||||
* drivers will reference the appropriate XXX_BASE value defined here
|
||||
* and have individual registers offset from that.
|
||||
*
|
||||
* Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
|
||||
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* ########################################################################
|
||||
*/
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifndef _ASM_MSP_REGS_H
|
||||
#define _ASM_MSP_REGS_H
|
||||
|
||||
/*
|
||||
########################################################################
|
||||
# Address space and device base definitions #
|
||||
########################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* System Logic and Peripherals (ELB, UART0, etc) device address space *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MSP_SLP_BASE 0x1c000000
|
||||
/* System Logic and Peripherals */
|
||||
#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
|
||||
/* System reset register base */
|
||||
#define MSP_RST_SIZE 0x0C /* System reset register space */
|
||||
|
||||
#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
|
||||
/* watchdog timer base */
|
||||
#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
|
||||
/* internal timer base */
|
||||
#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
|
||||
/* UART0 controller base */
|
||||
#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
|
||||
/* Block Copy controller base */
|
||||
#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
|
||||
/* Block Copy descriptor base */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* PCI address space *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MSP_PCI_BASE 0x19000000
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* MSbus device address space *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MSP_MSB_BASE 0x18000000
|
||||
/* MSbus address start */
|
||||
#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
|
||||
/* Peripheral device registers */
|
||||
#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
|
||||
/* MAC A device registers */
|
||||
#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
|
||||
/* MAC B device registers */
|
||||
#define MSP_MAC_SIZE 0xE0 /* MAC register space */
|
||||
|
||||
#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
|
||||
/* Security Engine registers */
|
||||
#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
|
||||
/* MAC C device registers */
|
||||
#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
|
||||
/* ADSL2 device registers */
|
||||
#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000)
|
||||
/* USB device registers */
|
||||
#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100)
|
||||
/* USB device registers */
|
||||
#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
|
||||
/* USB device registers */
|
||||
#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
|
||||
/* CPU interface registers */
|
||||
|
||||
/* Devices within the MSbus peripheral block */
|
||||
#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
|
||||
/* UART1 controller base */
|
||||
#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
|
||||
/* SPI/MPI control registers */
|
||||
#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
|
||||
/* Two-wire control registers */
|
||||
#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
|
||||
/* Programmable timer control */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* Physical Memory configuration address space *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MSP_MEM_CFG_BASE 0x17f00000
|
||||
|
||||
#define MSP_MEM_INDIRECT_CTL_10 0x10
|
||||
|
||||
/*
|
||||
* Notes:
|
||||
* 1) The SPI registers are split into two blocks, one offset from the
|
||||
* MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
|
||||
* 0x68. The SPI driver definitions for the register must be aware
|
||||
* of this.
|
||||
* 2) The block copy engine register are divided into two regions, one
|
||||
* for the control/configuration of the engine proper and one for the
|
||||
* values of the descriptors used in the copy process. These have
|
||||
* different base defines (CTRL_BASE vs DESC_BASE)
|
||||
* 3) These constants are for physical addresses which means that they
|
||||
* work correctly with "ioremap" and friends. This means that device
|
||||
* drivers will need to remap these addresses using ioremap and perhaps
|
||||
* the readw/writew macros. Or they could use the regptr() macro
|
||||
* defined below, but the readw/writew calls are the correct thing.
|
||||
* 4) The UARTs have an additional status register offset from the base
|
||||
* address. This register isn't used in the standard 8250 driver but
|
||||
* may be used in other software. Consult the hardware datasheet for
|
||||
* offset details.
|
||||
* 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
|
||||
* start at an offset of 0x84 from the base address but the block of
|
||||
* registers before this is reserved for the security engine. The
|
||||
* driver will have to be aware of this but it makes the register
|
||||
* definitions line up better with the documentation.
|
||||
*/
|
||||
|
||||
/*
|
||||
########################################################################
|
||||
# System register definitions. Not associated with a specific device #
|
||||
########################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* This macro maps the physical register number into uncached space
|
||||
* and (for C code) casts it into a u32 pointer so it can be dereferenced
|
||||
* Normally these would be accessed with ioremap and readX/writeX, but
|
||||
* these are convenient for a lot of internal kernel code.
|
||||
*/
|
||||
#ifdef __ASSEMBLER__
|
||||
#define regptr(addr) (KSEG1ADDR(addr))
|
||||
#else
|
||||
#define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* System Logic and Peripherals (RESET, ELB, etc) registers *
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* System Control register definitions */
|
||||
#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
|
||||
/* Device-ID RO */
|
||||
#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
|
||||
/* Firmware-ID Register RW */
|
||||
#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
|
||||
/* System-ID Register-0 RW */
|
||||
#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
|
||||
/* System-ID Register-1 RW */
|
||||
|
||||
/* System Reset register definitions */
|
||||
#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
|
||||
/* System Reset Status RO */
|
||||
#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
|
||||
/* System Set Reset WO */
|
||||
#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
|
||||
/* System Clear Reset WO */
|
||||
|
||||
/* System Clock Registers */
|
||||
#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
|
||||
/* PCI clock generator RW */
|
||||
#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
|
||||
/* UART clock generator RW */
|
||||
/* reserved (MSP_SLP_BASE + 0x24) */
|
||||
/* reserved (MSP_SLP_BASE + 0x28) */
|
||||
#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
|
||||
/* PLL1 clock generator RW */
|
||||
#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
|
||||
/* PLL0 clock generator RW */
|
||||
#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
|
||||
/* MIPS clock generator RW */
|
||||
#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
|
||||
/* Voice Eng clock generator RW */
|
||||
/* reserved (MSP_SLP_BASE + 0x3C) */
|
||||
#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
|
||||
/* MS-Bus clock generator RW */
|
||||
#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
|
||||
/* Sec & MAC clock generator RW */
|
||||
#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
|
||||
/* Per & TDM clock generator RW */
|
||||
|
||||
/* Interrupt Controller Registers */
|
||||
#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
|
||||
/* Interrupt status register RW */
|
||||
#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
|
||||
/* Interrupt enable/mask RW */
|
||||
#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
|
||||
/* Security Engine mailbox RW */
|
||||
#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
|
||||
/* Voice Engine mailbox RW */
|
||||
|
||||
/* ELB Controller Registers */
|
||||
#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
|
||||
/* ELB CS0 Configuration Reg */
|
||||
#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
|
||||
/* ELB CS0 Base Address Reg */
|
||||
#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
|
||||
/* ELB CS0 Mask Register */
|
||||
#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
|
||||
/* ELB CS0 access register */
|
||||
|
||||
#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
|
||||
/* ELB CS1 Configuration Reg */
|
||||
#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
|
||||
/* ELB CS1 Base Address Reg */
|
||||
#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
|
||||
/* ELB CS1 Mask Register */
|
||||
#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
|
||||
/* ELB CS1 access register */
|
||||
|
||||
#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
|
||||
/* ELB CS2 Configuration Reg */
|
||||
#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
|
||||
/* ELB CS2 Base Address Reg */
|
||||
#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
|
||||
/* ELB CS2 Mask Register */
|
||||
#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
|
||||
/* ELB CS2 access register */
|
||||
|
||||
#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
|
||||
/* ELB CS3 Configuration Reg */
|
||||
#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
|
||||
/* ELB CS3 Base Address Reg */
|
||||
#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
|
||||
/* ELB CS3 Mask Register */
|
||||
#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
|
||||
/* ELB CS3 access register */
|
||||
|
||||
#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
|
||||
/* ELB CS4 Configuration Reg */
|
||||
#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
|
||||
/* ELB CS4 Base Address Reg */
|
||||
#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
|
||||
/* ELB CS4 Mask Register */
|
||||
#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
|
||||
/* ELB CS4 access register */
|
||||
|
||||
#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
|
||||
/* ELB CS5 Configuration Reg */
|
||||
#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
|
||||
/* ELB CS5 Base Address Reg */
|
||||
#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
|
||||
/* ELB CS5 Mask Register */
|
||||
#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
|
||||
/* ELB CS5 access register */
|
||||
|
||||
/* reserved 0xE0 - 0xE8 */
|
||||
#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
|
||||
/* ELB single PC card detect */
|
||||
|
||||
/* reserved 0xF0 - 0xF8 */
|
||||
#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
|
||||
/* SDRAM read/ELB timing Reg */
|
||||
|
||||
/* Extended UART status registers */
|
||||
#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
|
||||
/* UART Status Register 0 */
|
||||
#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
|
||||
/* UART Status Register 1 */
|
||||
|
||||
/* Performance monitoring registers */
|
||||
#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
|
||||
/* Performance monitor control */
|
||||
#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
|
||||
/* Performance monitor clear */
|
||||
#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
|
||||
/* Perf monitor counter high */
|
||||
#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
|
||||
/* Perf monitor counter low */
|
||||
|
||||
/* System control registers */
|
||||
#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
|
||||
/* System control register */
|
||||
#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
|
||||
/* System Error status 1 */
|
||||
#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
|
||||
/* System Error status 2 */
|
||||
#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
|
||||
/* System Interrupt config */
|
||||
|
||||
/* Voice Engine Memory configuration */
|
||||
#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
|
||||
/* Voice engine memory config */
|
||||
|
||||
/* CPU/SLP Error Status registers */
|
||||
#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
|
||||
/* CPU/SLP Error status 1 */
|
||||
#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
|
||||
/* CPU/SLP Error status 1 */
|
||||
|
||||
#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188)
|
||||
/* Extended GPIO register */
|
||||
|
||||
/* System Error registers */
|
||||
#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
|
||||
/* Int status for SLP errors */
|
||||
#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
|
||||
/* Int mask for SLP errors */
|
||||
#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
|
||||
/* External ELB reset */
|
||||
#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
|
||||
/* Boot Status */
|
||||
|
||||
/* Extended ELB addressing */
|
||||
#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
|
||||
/* CS0 Extended address */
|
||||
#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
|
||||
/* CS1 Extended address */
|
||||
#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
|
||||
/* CS2 Extended address */
|
||||
#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
|
||||
/* CS3 Extended address */
|
||||
/* reserved 0x1B0 */
|
||||
#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
|
||||
/* CS5 Extended address */
|
||||
|
||||
/* PLL Adjustment registers */
|
||||
#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
|
||||
/* PLL0 lock status */
|
||||
#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
|
||||
/* PLL Analog reset status */
|
||||
#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
|
||||
/* PLL0 Adjustment value */
|
||||
#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
|
||||
/* PLL1 Adjustment value */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* Peripheral Register definitions *
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* Peripheral status */
|
||||
#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
|
||||
/* Peripheral control register */
|
||||
#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
|
||||
/* Peripheral status register */
|
||||
|
||||
/* SPI/MPI Registers */
|
||||
#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
|
||||
/* SPI/MPI Tx Size register */
|
||||
#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
|
||||
/* SPI/MPI Rx Size register */
|
||||
#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
|
||||
/* SPI/MPI Control register */
|
||||
#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
|
||||
/* SPI/MPI Chip Select reg */
|
||||
#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
|
||||
/* SPI/MPI Core Data reg */
|
||||
#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
|
||||
/* SPI/MPI Core Control reg */
|
||||
#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
|
||||
/* SPI/MPI Core Status reg */
|
||||
#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
|
||||
/* SPI/MPI Core Ssel reg */
|
||||
#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
|
||||
/* SPI/MPI Data FIFO reg */
|
||||
|
||||
/* Peripheral Block Error Registers */
|
||||
#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
|
||||
/* Error Bit Status Register */
|
||||
#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
|
||||
/* Error Bit Mask Register */
|
||||
#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
|
||||
/* Error Header 1 Register */
|
||||
#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
|
||||
/* Error Header 2 Register */
|
||||
|
||||
/* Peripheral Block Interrupt Registers */
|
||||
#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
|
||||
/* Interrupt status register */
|
||||
#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
|
||||
/* Interrupt Mask Register */
|
||||
#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
|
||||
/* GPIO interrupt status reg */
|
||||
#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
|
||||
/* GPIO interrupt MASK Reg */
|
||||
|
||||
/* POLO GPIO registers */
|
||||
#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
|
||||
/* Polo GPIO[8:0] data reg */
|
||||
#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
|
||||
/* Polo GPIO[7:0] config reg */
|
||||
#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
|
||||
/* Polo GPIO[15:8] config reg */
|
||||
#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
|
||||
/* Polo GPIO[31:0] output drive */
|
||||
#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
|
||||
/* Polo GPIO[23:16] config reg */
|
||||
#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
|
||||
/* Polo GPIO[15:9] data reg */
|
||||
#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
|
||||
/* Polo GPIO[23:16] data reg */
|
||||
#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
|
||||
/* Polo GPIO[31:24] data reg */
|
||||
#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
|
||||
/* Polo GPIO[39:32] data reg */
|
||||
#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
|
||||
/* Polo GPIO[47:40] data reg */
|
||||
#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
|
||||
/* Polo GPIO[54:48] data reg */
|
||||
#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
|
||||
/* Polo GPIO[31:24] config reg */
|
||||
#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
|
||||
/* Polo GPIO[39:32] config reg */
|
||||
#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
|
||||
/* Polo GPIO[47:40] config reg */
|
||||
#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
|
||||
/* Polo GPIO[54:48] config reg */
|
||||
#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
|
||||
/* Polo GPIO[54:32] output drive */
|
||||
|
||||
/* Generic GPIO registers */
|
||||
#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
|
||||
/* GPIO[1:0] data register */
|
||||
#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
|
||||
/* GPIO[5:2] data register */
|
||||
#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
|
||||
/* GPIO[9:6] data register */
|
||||
#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
|
||||
/* GPIO[15:10] data register */
|
||||
#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
|
||||
/* GPIO[1:0] config register */
|
||||
#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
|
||||
/* GPIO[5:2] config register */
|
||||
#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
|
||||
/* GPIO[9:6] config register */
|
||||
#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
|
||||
/* GPIO[15:10] config register */
|
||||
#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
|
||||
/* GPIO[15:0] output drive */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* CPU Interface register definitions *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
|
||||
/* PCI-SDRAM queue flush trigger */
|
||||
#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
|
||||
/* OCP Error Attribute 1 */
|
||||
#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
|
||||
/* OCP Error Attribute 2 */
|
||||
#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
|
||||
/* OCP Error Status */
|
||||
#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
|
||||
/* CPU policy configuration */
|
||||
#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
|
||||
/* Misc configuration options */
|
||||
|
||||
/* Central Interrupt Controller Registers */
|
||||
#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
|
||||
/* Central Interrupt registers */
|
||||
#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
|
||||
/* External interrupt config */
|
||||
#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
|
||||
/* CIC Interrupt Status */
|
||||
#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
|
||||
/* VPE0 Interrupt Mask */
|
||||
#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
|
||||
/* VPE1 Interrupt Mask */
|
||||
#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
|
||||
/* Thread Context 0 Int Mask */
|
||||
#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
|
||||
/* Thread Context 1 Int Mask */
|
||||
#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
/* Thread Context 2 Int Mask */
|
||||
#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
/* Thread Context 3 Int Mask */
|
||||
#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
/* Thread Context 4 Int Mask */
|
||||
#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
|
||||
#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
|
||||
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* Memory controller registers *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
|
||||
#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
|
||||
#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
|
||||
#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* PCI controller registers *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
|
||||
#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
|
||||
#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
|
||||
|
||||
/*
|
||||
########################################################################
|
||||
# Register content & macro definitions #
|
||||
########################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* DEV_ID defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
|
||||
#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
|
||||
#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
|
||||
#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
|
||||
#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
|
||||
|
||||
#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
|
||||
#define MSP5000_ID (0x50 << 8)
|
||||
#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
|
||||
#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
|
||||
#define MSP4200_ID (0x42 << 8)
|
||||
#define MSP4000_ID (0x40 << 8)
|
||||
#define MSP2XXX_ID (0x20 << 8)
|
||||
#define MSPZEUS_ID (0x10 << 8)
|
||||
|
||||
#define MSP2004_SUB_ID (0x0 << 16)
|
||||
#define MSP2005_SUB_ID (0x1 << 16)
|
||||
#define MSP2006_SUB_ID (0x1 << 16)
|
||||
#define MSP2007_SUB_ID (0x2 << 16)
|
||||
#define MSP2010_SUB_ID (0x3 << 16)
|
||||
#define MSP2015_SUB_ID (0x4 << 16)
|
||||
#define MSP2020_SUB_ID (0x5 << 16)
|
||||
#define MSP2100_SUB_ID (0x6 << 16)
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* RESET defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
|
||||
#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
|
||||
#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
|
||||
#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
|
||||
/* reserved */
|
||||
#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
|
||||
#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
|
||||
#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
|
||||
#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
|
||||
#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
|
||||
#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
|
||||
#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
|
||||
#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
|
||||
#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* UART defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
#ifndef CONFIG_MSP_FPGA
|
||||
#define MSP_BASE_BAUD 25000000
|
||||
#else
|
||||
#define MSP_BASE_BAUD 6000000
|
||||
#endif
|
||||
#define MSP_UART_REG_LEN 0x20
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* ELB defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
|
||||
#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* CIC defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* CIC_EXT_CFG_REG */
|
||||
#define EXT_INT_POL(eirq) (1 << (eirq + 8))
|
||||
#define EXT_INT_EDGE(eirq) (1 << eirq)
|
||||
|
||||
#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
|
||||
#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
|
||||
#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
|
||||
#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
|
||||
#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
|
||||
#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
|
||||
|
||||
#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
|
||||
((reg & EXT_INT_EDGE(eirq)) == 0)
|
||||
#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
|
||||
#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
|
||||
#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
|
||||
((reg & EXT_INT_POL(eirq)) == 0)
|
||||
#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
|
||||
#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* Memory Controller defines *
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* Indirect memory controller registers */
|
||||
#define DDRC_CFG(n) (n)
|
||||
#define DDRC_DEBUG(n) (0x04 + n)
|
||||
#define DDRC_CTL(n) (0x40 + n)
|
||||
|
||||
/* Macro to perform DDRC indirect write */
|
||||
#define DDRC_INDIRECT_WRITE(reg, mask, value) \
|
||||
({ \
|
||||
*MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
|
||||
*MEM_SS_DATA = (value); \
|
||||
*MEM_SS_WRITE = 1; \
|
||||
})
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* SPI/MPI Mode *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
|
||||
#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
|
||||
#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
|
||||
#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
* SPI/MPI Control Register *
|
||||
***************************************************************************
|
||||
*/
|
||||
#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
|
||||
#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
|
||||
#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
|
||||
|
||||
#endif /* !_ASM_MSP_REGS_H */
|
||||
141
include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
Normal file
141
include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Defines for the MSP interrupt controller.
|
||||
*
|
||||
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
|
||||
* Author: Carsten Langgaard, carstenl@mips.com
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* ########################################################################
|
||||
*/
|
||||
|
||||
#ifndef _MSP_SLP_INT_H
|
||||
#define _MSP_SLP_INT_H
|
||||
|
||||
/*
|
||||
* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
|
||||
* hierarchical system. The first level are the direct MIPS interrupts
|
||||
* and are assigned the interrupt range 0-7. The second level is the SLM
|
||||
* interrupt controller and is assigned the range 8-39. The third level
|
||||
* comprises the Peripherial block, the PCI block, the PCI MSI block and
|
||||
* the SLP. The PCI interrupts and the SLP errors are handled by the
|
||||
* relevant subsystems so the core interrupt code needs only concern
|
||||
* itself with the Peripheral block. These are assigned interrupts in
|
||||
* the range 40-71.
|
||||
*/
|
||||
|
||||
/*
|
||||
* IRQs directly connected to CPU
|
||||
*/
|
||||
#define MSP_MIPS_INTBASE 0
|
||||
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
|
||||
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
|
||||
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
|
||||
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
|
||||
#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
|
||||
#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
|
||||
#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
|
||||
#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
|
||||
|
||||
/*
|
||||
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
|
||||
* These defines should be tied to the register definition for the SLM
|
||||
* interrupt routine. For now, just use hard-coded values.
|
||||
*/
|
||||
#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
|
||||
#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
|
||||
/* External interrupt 0 */
|
||||
#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
|
||||
/* External interrupt 1 */
|
||||
#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
|
||||
/* External interrupt 2 */
|
||||
#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
|
||||
/* External interrupt 3 */
|
||||
/* Reserved 4-7 */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
|
||||
* Some MSP produces have this interrupt labelled as Voice and some are *
|
||||
* SEC mbox ... *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
|
||||
/* Cascaded IRQ for Voice Engine*/
|
||||
#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
|
||||
/* TDM interrupt */
|
||||
#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
|
||||
/* Cascaded IRQ for MAC 0 */
|
||||
#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
|
||||
/* Cascaded IRQ for MAC 1 */
|
||||
#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
|
||||
/* IRQ for security engine */
|
||||
#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
|
||||
/* Peripheral interrupt */
|
||||
#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
|
||||
/* SLP timer 0 */
|
||||
#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
|
||||
/* SLP timer 1 */
|
||||
#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
|
||||
/* SLP timer 2 */
|
||||
#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
|
||||
/* Cascaded MIPS timer */
|
||||
#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
|
||||
/* Block Copy */
|
||||
#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
|
||||
/* UART 0 */
|
||||
#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
|
||||
/* PCI subsystem */
|
||||
#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
|
||||
/* PCI doorbell */
|
||||
#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
|
||||
/* PCI Message Signal */
|
||||
#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
|
||||
/* PCI Block Copy 0 */
|
||||
#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
|
||||
/* PCI Block Copy 1 */
|
||||
#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
|
||||
/* SLP error condition */
|
||||
#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
|
||||
/* IRQ for MAC2 */
|
||||
/* Reserved 26-31 */
|
||||
|
||||
/*
|
||||
* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
|
||||
*/
|
||||
#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
|
||||
/* Reserved 0-1 */
|
||||
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
|
||||
/* UART 1 */
|
||||
/* Reserved 3-5 */
|
||||
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
|
||||
/* 2-wire */
|
||||
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
|
||||
/* Peripheral timer block out 0 */
|
||||
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
|
||||
/* Peripheral timer block out 1 */
|
||||
/* Reserved 9 */
|
||||
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
|
||||
/* SPI RX complete */
|
||||
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
|
||||
/* SPI TX complete */
|
||||
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
|
||||
/* GPIO */
|
||||
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
|
||||
/* Peripheral error */
|
||||
/* Reserved 14-31 */
|
||||
|
||||
#endif /* !_MSP_SLP_INT_H */
|
||||
Loading…
Reference in a new issue