From 41dbff419ed50224e74b35070aae5a5b8d4b4866 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Sat, 1 Aug 2020 16:49:08 +0530 Subject: [PATCH 0001/1809] arm: msm: dts: Disable rimps access till rimps brought up Disable rimps access from HLOS till rimps enabled in bu. Change-Id: I66b0d55b06596ae17a11397cc67d600d3f39abc1 --- qcom/holi-pm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/holi-pm.dtsi b/qcom/holi-pm.dtsi index 4ed3dba882d1..f8b2e0944b6e 100644 --- a/qcom/holi-pm.dtsi +++ b/qcom/holi-pm.dtsi @@ -1,7 +1,6 @@ &soc { qcom,lpm-levels { compatible = "qcom,lpm-levels"; - reg = <0xfd91060 0x20>, <0xfd92060 0x20>; #address-cells = <1>; #size-cells = <0>; From d3804a26b8b4638f0d48e9eb078d375d767264d7 Mon Sep 17 00:00:00 2001 From: yuleiy Date: Thu, 30 Jul 2020 14:12:27 +0800 Subject: [PATCH 0002/1809] ARM: dts: qcom: Add camera dts into holi QRD Add camera dtsi nodes into holi QRD root file. CRs-Fixed: 2749290 External Impact: No. Change-Id: I412c8b1ca799a491efac06a757fd92d51717fcca --- qcom/holi-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index fde20a6d3a43..0c3d7946aa18 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay.dtsi" #include "holi-thermal-overlay.dtsi" +#include "camera/holi-camera-sensor-qrd.dtsi" &sdhc_1 { status = "ok"; From 6a8cde9ac4899bae7f6c283cce4a0439b08b745a Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 15:22:40 +0800 Subject: [PATCH 0003/1809] ARM: dts: msm: add display support for qrd holi Add qrd display support for holi. Change-Id: I74998b2474a8ba2b129ebf0d37bec5911999dbd1 --- qcom/holi-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 0c3d7946aa18..ed3277af6295 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -4,6 +4,7 @@ #include "holi-pmic-overlay.dtsi" #include "holi-thermal-overlay.dtsi" #include "camera/holi-camera-sensor-qrd.dtsi" +#include "display/holi-sde-display-qrd.dtsi" &sdhc_1 { status = "ok"; From f3d274d8c8ef9a39d696adf22fcb77a57bfb9d72 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 31 Jul 2020 16:07:44 +0800 Subject: [PATCH 0004/1809] ARM: dts: msm: Add touchscreen device node for QRD holi Enable new touchscreen for QRD holi devices. Change-Id: Ifb8d5dc1470d2a4c11566687ae25628f8c9f2869 --- qcom/holi-qrd.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index ed3277af6295..5fb49d020c1d 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -91,6 +91,35 @@ }; }; +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L6A>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; +}; + &wsa881x_analog_reset_gpio { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; From 3bc3a93af6c9cdbdb5c514005f01e14dc1d1cc16 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 12 Aug 2020 18:26:18 +0530 Subject: [PATCH 0005/1809] ARM: dts: qcom: add support for backlight cooling device on Holi This change adds support for backlight cooling device on Holi target. Change-Id: I0a13a8ed6a4549918f8cf682dbc99922f75b52d7 --- qcom/holi-thermal-overlay.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi-thermal-overlay.dtsi b/qcom/holi-thermal-overlay.dtsi index a5affe121cb1..f9c2e39e0dec 100644 --- a/qcom/holi-thermal-overlay.dtsi +++ b/qcom/holi-thermal-overlay.dtsi @@ -1,5 +1,9 @@ #include +&mdss_mdp { + #cooling-cells = <2>; +}; + &thermal_zones { socd { cooling-maps { From 24a17fca7c210a4ee3f961a313e615ed9a11b70d Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Fri, 14 Aug 2020 12:31:56 +0530 Subject: [PATCH 0006/1809] ARM: dts: msm: Add support for SCM PAS for holi The PIL drivers need to vote for bandwidth across DDR and crypto subsytem, such that the secure world can perform initialization and authorization of the firmware blobs. Hence add a device-tree node indicating the corresponding interconnect. Change-Id: I9a0537930a246705382dc727f1014b397b982ec3 --- qcom/holi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 436cc02c0d47..7f5ad18e0d1a 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -868,6 +868,11 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 1be24ccf8105b792f15c3dc9d26a4d33ae4c1c84 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Sat, 15 Aug 2020 20:09:36 +0800 Subject: [PATCH 0007/1809] ARM: dts: msm: disable wcss cti on holi Wcss cti need be disabled on holi. Change-Id: I0b79eb9a092ec9d442377a7d0cc72708710e0e49 --- qcom/holi-coresight.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index a98522c5c24d..66b53eeec2bf 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -2349,7 +2349,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti0"; - + status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; @@ -2360,6 +2360,7 @@ reg = <0x89a5000 0x1000>; reg-names = "cti-base"; + status = "disabled"; coresight-name = "coresight-cti-wcss_cti1"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; @@ -2375,6 +2376,7 @@ coresight-name = "coresight-cti-wcss_cti2"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + status = "disabled"; clock-names = "apb_pclk"; }; From 09cb182376f5267144ef26640c812118f0f7d294 Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Sat, 15 Aug 2020 17:05:27 +0530 Subject: [PATCH 0008/1809] ARM: dts: msm: Define console before other QUP devices QUP core clock is shared among all the SE drivers, during earlybootup if any SE driver turn off the clock before real console gets probe, the device will crash because of unclocked access by earlycon. In order to fix this move the console device definition up in DT file this ensures that console probe is called before other SE drivers. Change-Id: I341940fd56890b9c6b316fd767eb79d384948efd --- qcom/holi-qupv3.dtsi | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index ee0331614cc4..a24f54a1d308 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -56,6 +56,23 @@ status = "ok"; }; + /* Debug UART Instance */ + qupv3_se9_2uart: qcom,qup_uart@4c8c000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4c8c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_2uart_active>; + pinctrl-1 = <&qupv3_se9_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + qupv3_se0_i2c: i2c@4a80000 { compatible = "qcom,i2c-geni"; reg = <0x4a80000 0x4000>; @@ -285,23 +302,6 @@ status = "disabled"; }; - /* Debug UART Instance */ - qupv3_se9_2uart: qcom,qup_uart@4c8c000 { - compatible = "qcom,msm-geni-console"; - reg = <0x4c8c000 0x4000>; - reg-names = "se_phys"; - interrupts = ; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, - <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se9_2uart_active>; - pinctrl-1 = <&qupv3_se9_2uart_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - qupv3_se10_i2c: i2c@4c90000 { compatible = "qcom,i2c-geni"; reg = <0x4c90000 0x4000>; From 6444cd6ba0440d2b8922ec57bb0a1dc8ed1a074b Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 17 Aug 2020 16:20:47 +0800 Subject: [PATCH 0009/1809] ARM: dts: msm: correct the audio etm name Modify audio etm name to coresight-audio-etm0. Change-Id: Ib380a7162e6403eeb0d8c3f7707a42e17f87522b --- qcom/holi-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 66b53eeec2bf..201a31415979 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -267,7 +267,7 @@ audio_etm { compatible = "qcom,coresight-remote-etm"; - coresight-name = "coresight-audio-etm"; + coresight-name = "coresight-audio-etm0"; qcom,inst-id = <5>; From 219f182e0e7a578a2fad164096e6b52ed5ae87de Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 17 Aug 2020 13:35:42 +0530 Subject: [PATCH 0010/1809] ARM: dts: msm: Add notification edge for glink ssr Edges to notify on ssr are missing for adsp and cdsp glink dt entries. Adding ssr notify edge entries to adsp and cdsp glink dt nodes. Change-Id: Ia5aa92ea0656aa94a73de322ac717e129da2a98a --- qcom/holi.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 7f5ad18e0d1a..d806420df23f 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1644,7 +1644,8 @@ qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; - qcom,notify-edges = <&glink_modem>; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; }; qcom,pmic_glink_rpmsg { @@ -1678,6 +1679,11 @@ 0x2000 3 0x4400 2>; }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; }; }; From 6e7275432d78d044efd90a27b873bddc12117c5d Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 18 Aug 2020 18:12:27 +0530 Subject: [PATCH 0011/1809] ARM: dts: msm: Add command mode touch support on holi This change adds command mode panel touch support on holi platform. Change-Id: I5ce1ef886ee0393aadbb8041159463bbc0cfe008 --- qcom/holi-atp.dtsi | 3 ++- qcom/holi-cdp.dtsi | 3 ++- qcom/holi-mtp.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index 002dd8bca4fa..73ea0bcb4b86 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -154,6 +154,7 @@ synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; - panel = <&dsi_rm69299_visionox_amoled_video>; + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; }; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 27fe936f99be..80790f30e271 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -143,7 +143,8 @@ synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; - panel = <&dsi_rm69299_visionox_amoled_video>; + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 36fa9acb6cd5..6f26219570d6 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -143,7 +143,8 @@ synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; - panel = <&dsi_rm69299_visionox_amoled_video>; + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; }; From d61c1517481403458c241faba4421a3d0271ce14 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Wed, 19 Aug 2020 03:04:49 +0530 Subject: [PATCH 0012/1809] ARM: dts: msm: dtsi changes for holi 1. correct entry for swr wakeup interrupt. 2. lpass audio hw vote entry for lpi_tlmm. Change-Id: I1e859aa0a35f9c25191a1c60a889a484e2a43e08 --- qcom/holi-audio-overlay.dtsi | 10 +-- qcom/holi-audio.dtsi | 2 + qcom/holi-cdp-overlay.dts | 16 ----- qcom/holi-qrd.dtsi | 121 +++++++++++++---------------------- qcom/holi.dtsi | 2 + 5 files changed, 53 insertions(+), 98 deletions(-) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index a046d799ed63..95269a2f5d44 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include &bolero { qcom,num-macros = <3>; @@ -13,7 +14,7 @@ qcom,fs-gen-sequence = <0x3000 0x1>, <0x3004 0x1>, <0x3080 0x2>; qcom,rx_mclk_mode_muxsel = <0x0A5640D8>; - qcom,va_mclk_mode_muxsel = <0x0A730000>; + qcom,va_mclk_mode_muxsel = <0x0A7A0000>; clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", "va_core_clk", "va_npl_clk"; clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, @@ -42,7 +43,7 @@ swrm-io-base = <0xA740000 0x0>; interrupts-extended = <&wakegic 5 IRQ_TYPE_LEVEL_HIGH>, - <&wakegic 66 IRQ_TYPE_LEVEL_HIGH>; + <&tlmm 128 GPIO_ACTIVE_HIGH>; interrupt-names = "swr_master_irq", "swr_wake_irq"; qcom,swr-num-ports = <3>; qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>, @@ -89,7 +90,7 @@ qcom,rx_mclk_mode_muxsel = <0xA5640D8>; qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>; qcom,default-clk-id = ; - swri: rx_swr_master { + swr1: rx_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; #size-cells = <0>; @@ -230,7 +231,7 @@ &holi_snd { qcom,model = "holi-mtp-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; - qcom,wcn-btfm = <0>; + qcom,wcn-btfm = <1>; qcom,tdm-max-slots = <4>; qcom,audio-routing = "AMIC1", "Analog Mic1", @@ -346,6 +347,7 @@ pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&spkr_2_sd_n_active>; pinctrl-1 = <&spkr_2_sd_n_sleep>; + #gpio-cells = <0>; }; wsa881x_analog_clk: wsa_ana_clk { diff --git a/qcom/holi-audio.dtsi b/qcom/holi-audio.dtsi index fb761d2c4fc8..4014574b45ee 100644 --- a/qcom/holi-audio.dtsi +++ b/qcom/holi-audio.dtsi @@ -22,6 +22,8 @@ compatible = "qcom,lpi-pinctrl"; reg = <0xa7c0000 0x0>; qcom,slew-reg = <0x0a95a000 0x0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; qcom,gpios-count = <19>; gpio-controller; #gpio-cells = <2>; diff --git a/qcom/holi-cdp-overlay.dts b/qcom/holi-cdp-overlay.dts index 5d8735e10822..6e7e36f39217 100644 --- a/qcom/holi-cdp-overlay.dts +++ b/qcom/holi-cdp-overlay.dts @@ -10,22 +10,6 @@ qcom,board-id = <1 0>; }; -&wsa881x_i2c_e { - status = "disabled"; -}; - -&wsa881x_i2c_44 { - status = "disabled"; -}; - -&wsa881x_i2c_f { - status = "ok"; -}; - -&wsa881x_i2c_45 { - status = "ok"; -}; - &wsa881x_analog_reset_gpio { pinctrl-0 = <&spkr_1_sd_n_active>; pinctrl-1 = <&spkr_1_sd_n_sleep>; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 5fb49d020c1d..27910adb00bc 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -142,96 +142,61 @@ &holi_snd { qcom,model = "holi-qrd-snd-card"; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; qcom,audio-routing = - "AMIC1", "MIC BIAS1", - "MIC BIAS1", "Analog Mic1", - "AMIC2", "MIC BIAS2", - "MIC BIAS2", "Analog Mic2", - "AMIC3", "MIC BIAS3", - "MIC BIAS3", "Analog Mic3", - "AMIC4", "MIC BIAS1", - "MIC BIAS1", "Analog Mic4", - "TX DMIC0", "MIC BIAS3", - "MIC BIAS3", "Digital Mic0", - "TX DMIC1", "MIC BIAS3", - "MIC BIAS3", "Digital Mic1", - "TX DMIC2", "MIC BIAS1", - "MIC BIAS1", "Digital Mic2", - "TX DMIC3", "MIC BIAS1", - "MIC BIAS1", "Digital Mic3", - "TX DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", - "TX DMIC5", "MIC BIAS4", - "MIC BIAS4", "Digital Mic5", + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS3", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC2", "ADC2_OUTPUT", - "TX SWR_ADC3", "ADC3_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT", - "WSA SRC0_INP", "SRC0", - "WSA_TX DEC0_INP", "TX DEC0 MUX", - "WSA_TX DEC1_INP", "TX DEC1 MUX", "RX_TX DEC0_INP", "TX DEC0 MUX", "RX_TX DEC1_INP", "TX DEC1 MUX", "RX_TX DEC2_INP", "TX DEC2 MUX", "RX_TX DEC3_INP", "TX DEC3 MUX", - "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrMono WSA_IN", "AUX", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", "VA_AIF1 CAP", "VA_SWR_CLK", "VA_AIF2 CAP", "VA_SWR_CLK", "VA_AIF3 CAP", "VA_SWR_CLK", - "VA MIC BIAS3", "Digital Mic0", - "VA MIC BIAS3", "Digital Mic1", - "VA MIC BIAS1", "Digital Mic2", - "VA MIC BIAS1", "Digital Mic3", - "VA MIC BIAS4", "Digital Mic4", - "VA MIC BIAS4", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS4", - "VA DMIC5", "VA MIC BIAS4", - "VA SWR_ADC0", "VA_SWR_CLK", - "VA SWR_ADC1", "VA_SWR_CLK", - "VA SWR_ADC2", "VA_SWR_CLK", - "VA SWR_ADC3", "VA_SWR_CLK", - "VA SWR_MIC0", "VA_SWR_CLK", - "VA SWR_MIC1", "VA_SWR_CLK", - "VA SWR_MIC2", "VA_SWR_CLK", - "VA SWR_MIC3", "VA_SWR_CLK", - "VA SWR_MIC4", "VA_SWR_CLK", - "VA SWR_MIC5", "VA_SWR_CLK", - "VA SWR_MIC6", "VA_SWR_CLK", - "VA SWR_MIC7", "VA_SWR_CLK", - "VA SWR_ADC0", "ADC1_OUTPUT", - "VA SWR_ADC2", "ADC2_OUTPUT", - "VA SWR_ADC3", "ADC3_OUTPUT", - "VA SWR_MIC0", "DMIC1_OUTPUT", - "VA SWR_MIC1", "DMIC2_OUTPUT", - "VA SWR_MIC2", "DMIC3_OUTPUT", - "VA SWR_MIC3", "DMIC4_OUTPUT", - "VA SWR_MIC4", "DMIC5_OUTPUT", - "VA SWR_MIC5", "DMIC6_OUTPUT", - "VA SWR_MIC6", "DMIC7_OUTPUT", - "VA SWR_MIC7", "DMIC8_OUTPUT"; - qcom,msm-mbhc-hphl-swh = <0>; - qcom,msm-mbhc-gnd-swh = <0>; - qcom,wsa-devs = <&wsa881x_i2c_e>; - qcom,wsa-aux-dev-prefix = "SpkrLeft"; - qcom,codec-aux-devs = <&wcd937x_codec>; - qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, - <&lpi_tlmm>, <&bolero>; + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd937x_codec>, <&wsa881x_i2c_e>, + <&wsa881x_i2c_f>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd937x_codec", "wsa-codec0", + "wsa-codec1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; }; &soc { diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index d806420df23f..bc8c53289ce5 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -410,6 +410,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; compatible = "simple-bus"; psci { @@ -463,6 +464,7 @@ reg = <0xf200000 0x10000>, /* GICD */ <0xf240000 0x100000>; /* GICR * 8 */ interrupts = ; + #gpio-cells = <0>; }; spmi_bus: qcom,spmi@1c40000 { From c55b520cec90ee294f5eb5c6bc6520333e855fdd Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 19 Aug 2020 13:25:50 +0800 Subject: [PATCH 0013/1809] ARM: dts: msm: enable dcc on holi Now that SDI has enabled, DCC can be enabled. Change-Id: Ibd4545e48db6f92fc94935b9e7027b1d158c5ab5 --- qcom/holi.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index bc8c53289ce5..3df8cd96bf28 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1480,7 +1480,6 @@ <0x1662000 0x2000>; qcom,transaction_timeout = <0>; - status = "disabled"; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x6000>; }; From e18544c58873f247fb6a0d99a2f99f28394b4d28 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Wed, 19 Aug 2020 13:09:12 +0530 Subject: [PATCH 0014/1809] ARM: dts: msm: Enable SMMU S1 for AP on Holi Enable SMMU S1 for AP on Holi. Change-Id: I7f8e3eb9f6404057317b0becca38f73c100e6571 --- qcom/holi.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 3df8cd96bf28..92aaf2115efb 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2518,21 +2518,19 @@ qcom,additional-mapping = /* modem tables in IMEM */ <0x0C123000 0x0C123000 0x2000>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; qcom,ipa-q6-smem-size = <36864>; }; ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x04A1 0x0>; - qcom,iommu-dma = "bypass"; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x04A2 0x0>; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; - qcom,iommu-dma = "bypass"; }; ipa_smmu_11ad: ipa_smmu_11ad { From d452bd3bc164b0bf1b3bd2b4ff613c0e8e40f37b Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Fri, 24 Apr 2020 14:40:11 +0530 Subject: [PATCH 0015/1809] ARM: dts: msm: Enable SMMU S1 for USB on Holi Enable SMMU S1 for USB on Holi. Change-Id: I751ab733f48b430811ee782607baf84c5f9ff03a --- qcom/holi-usb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index c65f56ad8dd5..573bcff31175 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -8,9 +8,13 @@ reg = <0x4e00000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xe0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; + dma-ranges; interrupts = , , From 35da3ce74a04649073879a576e326bfd05dd9906 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 12 Aug 2020 18:02:39 +0530 Subject: [PATCH 0016/1809] ARM: dts: msm: Update wlan configuration for holi Update regulator properties and smmu sids for holi. Change-Id: I1da89ffaeef43dea69e8ab4293d6466ad0638b37 --- qcom/holi.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 92aaf2115efb..5c6479cf7827 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2397,10 +2397,11 @@ }; icnss: qcom,icnss@C800000 { - status = "disabled"; compatible = "qcom,icnss"; - reg = <0xC800000 0x800000>; - reg-names = "membase"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; interrupts = , , , @@ -2415,6 +2416,15 @@ ; qcom,iommu-dma = "bypass"; qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + vdd-cx-mx-supply = <&L4A>; + vdd-1.8-xo-supply = <&L7A>; + vdd-1.3-rfa-supply = <&L2E>; + vdd-3.3-ch1-supply = <&L11E>; + vdd-3.3-ch0-supply = <&L10E>; + qcom,vdd-cx-mx-config = <0 0>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; From c196b4f85693131586b51154b6d69497bc4857a9 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 3 Aug 2020 10:30:33 +0530 Subject: [PATCH 0017/1809] ARM: dts: msm: Add gpu gaming bin support for holi Add provider bindings in qfprom and consumer bindings for enabling support to read the gaming bin fuse bit for holi gpu. Change-Id: I29ced8173b5a0262efadca5fe0ea90fc152c0932 --- qcom/holi-gpu.dtsi | 3 +++ qcom/holi.dtsi | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index bcfe85951a0f..61f8273c784c 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -32,6 +32,9 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vdd-supply = <&gpu_gx_gdsc>; qcom,chipid = <0x06010900>; + nvmem-cells = <&gpu_gaming_bin>; + nvmem-cell-names = "gaming_bin"; + qcom,initial-pwrlevel = <4>; qcom,gpu-quirk-secvid-set-once; qcom,min-access-length = <32>; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 5c6479cf7827..ec9cff9f069f 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2568,6 +2568,11 @@ reg = <0x6024 0x2>; bits = <21 1>; }; + + gpu_gaming_bin: gpu_gaming_bin@6026 { + reg = <0x6026 0x1>; + bits = <5 1>; + }; }; }; From 3ec04fed372cf9710f9017abe7c23c4127711e14 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Fri, 21 Aug 2020 17:47:05 +0530 Subject: [PATCH 0018/1809] ARM: dts: msm: Add gpu speed bin property for holi Add gpu_speed_bin property in qfprom device node for holi. Change-Id: Ia7e2ba73ebcd1b5a17da786f5394769e6e907833 --- qcom/holi-gpu.dtsi | 4 ++-- qcom/holi.dtsi | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index 61f8273c784c..969737edfde3 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -32,8 +32,8 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vdd-supply = <&gpu_gx_gdsc>; qcom,chipid = <0x06010900>; - nvmem-cells = <&gpu_gaming_bin>; - nvmem-cell-names = "gaming_bin"; + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin"; qcom,initial-pwrlevel = <4>; qcom,gpu-quirk-secvid-set-once; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index ec9cff9f069f..a3992ade8c01 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2559,6 +2559,11 @@ read-only; ranges; + gpu_speed_bin: gpu_speed_bin@6015 { + reg = <0x6015 0x1>; + bits = <0 8>; + }; + adsp_variant: adsp_variant@1E6 { reg = <0x1E6 0x2>; bits = <6 9>; From ff1f9d1a18be2c5270f571a512ff7e0484154f4c Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Thu, 20 Aug 2020 21:31:49 +0530 Subject: [PATCH 0019/1809] ARM: dts: msm: Enable smmu s1 from wlan side This change enables smmu stage s1 from wlan side for holi. Change-Id: I4526de0a8c83e5e1bb41ce3887163c52fe79e123 --- qcom/holi.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a3992ade8c01..75f25dc999a6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2414,7 +2414,8 @@ , , ; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; vdd-cx-mx-supply = <&L4A>; From a4b2ad809f1d9d075cc8428e479129767c8b6831 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Sun, 23 Aug 2020 11:31:48 +0530 Subject: [PATCH 0020/1809] ARM: dts: msm: fix to indetify proper adsp variant correct the fuse value read to identify the adsp SKU. Change-Id: Ib100712ece632d09d43f9047a7e3ddd474170f29 --- qcom/holi-audio-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 95269a2f5d44..63ff9a5c50e8 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -411,5 +411,5 @@ nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; adsp-fw-names = "adsp2"; - adsp-fw-bit-values = <0xE>; + adsp-fw-bit-values = <0x1>; }; From 6f0dad37129f359be2f37cb125563a80ec4a4983 Mon Sep 17 00:00:00 2001 From: Niranjan Dumbala Date: Thu, 3 Sep 2020 01:53:44 -0700 Subject: [PATCH 0021/1809] Revert "arm: msm: dts: Disable rimps access till rimps brought up" This reverts commit 41dbff419ed50224e74b35070aae5a5b8d4b4866. Change-Id: I624104ac06c262f01511edd157df6514aab3ee94 --- qcom/holi-pm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-pm.dtsi b/qcom/holi-pm.dtsi index f8b2e0944b6e..4ed3dba882d1 100644 --- a/qcom/holi-pm.dtsi +++ b/qcom/holi-pm.dtsi @@ -1,6 +1,7 @@ &soc { qcom,lpm-levels { compatible = "qcom,lpm-levels"; + reg = <0xfd91060 0x20>, <0xfd92060 0x20>; #address-cells = <1>; #size-cells = <0>; From fb743fd80755af69651f0e540b059a76558dc880 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Fri, 28 Aug 2020 15:43:17 +0530 Subject: [PATCH 0022/1809] ARM: dts: msm: correction to adsp variant read entry. Correction to the number of bits read for adsp variant identification. Include adsp_variant read entry for holi-atp variant. Update dtsi for ATP variant. Change-Id: I6b95d9f7b1e9a7196195b2e9cc29eae0567ba716 --- qcom/holi-atp-overlay.dts | 39 +++++++++++++++++++++++++++++++++++++++ qcom/holi-atp.dtsi | 1 + qcom/holi.dtsi | 2 +- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/qcom/holi-atp-overlay.dts b/qcom/holi-atp-overlay.dts index a2d3433c67a0..8062ff331274 100644 --- a/qcom/holi-atp-overlay.dts +++ b/qcom/holi-atp-overlay.dts @@ -9,3 +9,42 @@ qcom,msm-id = <454 0x10000>, <472 0x10000>; qcom,board-id = <33 0>; }; + +&wsa881x_i2c_e { + status = "disabled"; +}; + +&wsa881x_i2c_44 { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&holi_snd { + qcom,wcd-disabled = <1>; + qcom,audio-routing = + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5"; +}; diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index ab7daf265da5..d6a7f5516163 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -1,3 +1,4 @@ +#include "holi-audio-overlay.dtsi" #include #include #include "holi-pmic-overlay.dtsi" diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f9b21403897d..bf7f2a59aaa5 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2705,7 +2705,7 @@ adsp_variant: adsp_variant@1E6 { reg = <0x1E6 0x2>; - bits = <6 9>; + bits = <6 4>; }; feat_conf8: feat_conf8@6024 { From 3e56148280d59f7a9477637fde14432747bb94e2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 1 Sep 2020 17:59:06 +0530 Subject: [PATCH 0023/1809] bindings: clock: rpmcc: Add clk handoff property. Add this optional property in the case where the driver needs to send initial high votes to RPM. Change-Id: Ic08dec9a8ff440816389fc7c7548365c72dced42 --- bindings/clock/qcom,rpmcc.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index 3fba2772a36d..498c5389a4a8 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -30,6 +30,10 @@ suspended or in deep idle. If it is important that the clock keeps running during system suspend, you need to specify the non-active clock, the one not containing *_A_* in the enumerator name. +Optional properties: +- qcom,hw-clk-handoff : Add this property to support initial high votes on the + to be sent to RPM as proxy votes. + Example: smd { compatible = "qcom,smd"; From 2531bfb3eaf8f5f3a26d1df4ece059d75bc356f5 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 1 Sep 2020 16:50:39 +0530 Subject: [PATCH 0024/1809] ARM: dts: msm: Add dpdm supply for PM7250b for holi. Add dpdm supply for PM7250b for holi. Change-Id: Id860c355a7d92a6ac607e041eaece5e2e0dde1c9 --- qcom/holi-atp.dtsi | 2 ++ qcom/holi-cdp.dtsi | 2 ++ qcom/holi-mtp-usbc.dtsi | 2 ++ qcom/holi-mtp.dtsi | 2 ++ qcom/holi-qrd.dtsi | 2 ++ 5 files changed, 10 insertions(+) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index d6a7f5516163..21a7b42a5cd8 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -247,6 +247,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index d7e950570492..b1379debf603 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -237,6 +237,8 @@ #include "camera/holi-camera-sensor-cdp.dtsi" &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index ede4c9f9c84b..bfb99171157a 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -201,6 +201,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 23e65b9e01d7..1bf80cf75004 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -256,6 +256,8 @@ #include "camera/holi-camera-sensor-mtp.dtsi" &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index ff21d1605104..e8ac31401e88 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -330,6 +330,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; From e066ff5afc0caa736cbf92e83ad9efae68433bec Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Wed, 2 Sep 2020 16:37:55 +0530 Subject: [PATCH 0025/1809] ARM: dts: msm: update low SVS clock corner for holi. Update low SVS corner from 133.33 to 133.00 for core clock and vcodec clock. Change-Id: I0e5eb6540573e041409a6937e8a4bcf2217d99b9 --- qcom/holi-vidc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-vidc.dtsi b/qcom/holi-vidc.dtsi index abc6b40d33c5..5b3aa57de254 100644 --- a/qcom/holi-vidc.dtsi +++ b/qcom/holi-vidc.dtsi @@ -25,7 +25,7 @@ qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "core0_clk", "core0_bus_clk", "throttle_clk"; qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; - qcom,allowed-clock-rates = <133330000 240000000 300000000 + qcom,allowed-clock-rates = <133000000 240000000 300000000 384000000>; /* Bus Interconnects */ From 312652b85fdd1c7d5d8dd7509681d1923e616842 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Tue, 25 Aug 2020 19:53:30 +0530 Subject: [PATCH 0026/1809] ARM: dts: msm: Enable ep delay for holi. Add support for enabling endpoint delay for holi target. Change-Id: Icdafab5a24b8cc3bb7042e7abc81195bec71aef3 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index bf7f2a59aaa5..708afb627a02 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2612,6 +2612,7 @@ qcom,lan-rx-napi; qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; + qcom,ipa-endp-delay-wa; qcom,tx-wrapper-cache-max-size = <400>; clock-names = "core_clk"; clocks = <&rpmcc RPM_SMD_IPA_CLK>; From 71f2887408a53ee1a95c0457aa9c6c71b699ecd7 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 31 Aug 2020 22:30:30 +0530 Subject: [PATCH 0027/1809] ARM: dts: msm: Add WLED support on PM6150l for holi. Add WLED support on PM6150l for holi. Also add QG IIO channels required by WLED. Change-Id: Ia43387d875abf0365e68f77afb5775c25d2d9f9d --- qcom/holi-pmic-overlay.dtsi | 9 +++++++++ qcom/pm6150l.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index fdea52c3dee0..7935292f7f9c 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -259,6 +259,15 @@ "flash_active"; }; +&pm6150l_wled { + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>; + io-channel-names = "rbatt", + "voltage_ocv", + "current_now"; +}; + &thermal_zones { chg-skin-therm-usr { polling-delay-passive = <0>; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index c5028363e7e9..428097af9fdc 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -281,6 +281,36 @@ }; }; + pm6150l_wled: qcom,wled@d800 { + compatible = "qcom,pm6150l-spmi-wled"; + reg = <0xd800>, <0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,auto-calibration; + status = "disabled"; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; + pm6150l_lpg: qcom,pwms@b100 { compatible = "qcom,pwm-lpg"; reg = <0xb100>, <0xb000>; From af8b6b4f2abff266e0fef3bb6d4d2c143f116108 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 11 Sep 2020 18:02:23 +0530 Subject: [PATCH 0028/1809] dt-bindings: Add snapshot of batterydata devicetree bindings Add snapshot of batterydata bindings as of devicetree-4.19 'commit 6d9f3e267754 ("ARM: dts: msm: Add snd node for orchid")'. Change-Id: Ib5b30add8245b62886556be6185e5d668fbfd9e9 --- bindings/batterydata/batterydata.txt | 321 +++++++++++++++++++++++++++ 1 file changed, 321 insertions(+) create mode 100644 bindings/batterydata/batterydata.txt diff --git a/bindings/batterydata/batterydata.txt b/bindings/batterydata/batterydata.txt new file mode 100644 index 000000000000..29b75cd47b57 --- /dev/null +++ b/bindings/batterydata/batterydata.txt @@ -0,0 +1,321 @@ +Battery Profile Data + +Battery Data is a collection of battery profile data made available to +the QPNP Charger and BMS drivers via device tree. + +qcom,battery-data node required properties: +- qcom,rpull-up-kohm : The vadc pullup resistor's resistance value in kOhms. +- qcom,vref-batt-therm-uv : The vadc voltage used to make readings. + For Qualcomm Technologies, Inc. VADCs, this should be + 1800000uV. + +qcom,battery-data node optional properties: +- qcom,batt-id-range-pct : The area of variation between upper and lower bound + for which a given battery ID resistance is valid. This + value is expressed as a percentage of the specified kohm + resistance provided by qcom,batt-id-kohm. + +qcom,battery-data can also include any number of children nodes. These children +nodes will be treated as battery profile data nodes. + +Profile data node required properties: +- qcom,fcc-mah : Full charge count of the battery in milliamp-hours +- qcom,default-rbatt-mohm : The nominal battery resistance value +- qcom,rbatt-capacitive-mohm : The capacitive resistance of the battery. +- qcom,flat-ocv-threshold-uv : The threshold under which the battery can be + considered to be in the flat portion of the discharge + curve. +- qcom,max-voltage-uv : The maximum rated voltage of the battery +- qcom,v-cutoff-uv : The cutoff voltage of the battery at which the device + should shutdown gracefully. +- qcom,chg-term-ua : The termination charging current of the battery. +- qcom,batt-id-kohm : The battery id resistance of the battery. It can be + used as an array which could support multiple IDs for one battery + module when the ID resistance of some battery modules goes across + several ranges. +- qcom,battery-type : A string indicating the type of battery. +- qcom,fg-profile-data : An array of hexadecimal values used to configure more + complex fuel gauge peripherals which have a large amount + of coefficients used in hardware state machines and thus + influencing the final output of the state of charge read + by software. + +Profile data node optional properties: +- qcom,chg-rslow-comp-c1 : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rslow-comp-c2 : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rslow-comp-thr : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rs-to-rslow: A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,fastchg-current-ma: Specifies the maximum fastcharge current. +- qcom,fg-cc-cv-threshold-mv: Voltage threshold in mV for transition from constant + charge (CC) to constant voltage (CV). This value should + be 10 mV less than the float voltage. + This property should only be specified if + "qcom,autoadjust-vfloat" property is specified in the + charger driver to ensure a proper operation. +- qcom,thermal-coefficients: Byte array of thermal coefficients for reading + battery thermistor. This should be exactly 6 bytes + in length. + Example: [01 02 03 04 05 06] +- qcom,therm-coefficients: Array of thermal coefficients that will be used in + battery profile for GEN4 FG. This should be exactly of + size 5. +- qcom,therm-center-offset: Specifies the resistor divide ratio between pull-up + resistor and the thermistor for GEN4 FG. +- qcom,therm-pull-up: Specifies the thermistor pull-up resistor value in + KOhms. +- qcom,rslow-normal-coeffs: Array of Rslow coefficients that will be applied + when the battery temperature is greater than 0 degree + Celsius for GEN4 FG. This should be exactly of size 4. +- qcom,rslow-low-coeffs: Array of Rslow coefficients that will be applied + when the battery temperature is lower than 0 degree + Celsius for GEN4 FG. This should be exactly of size 4. +- qcom,soc-based-step-chg: A bool property to indicate if the battery will + perform SoC (State of Charge) based step charging. + If yes, the low and high thresholds defined in + "qcom,step-chg-ranges" tuples should be assigned as + SoC values in percentage. +- qcom,ocv-based-step-chg: A bool property to indicate if the battery will + perform OCV (Open Circuit Voltage) based step charging. + If yes, the low and high thresholds defined in + "qcom,step-chg-ranges" tuples should be assigned as + OCV values in microvolts. +- qcom,step-chg-ranges: Array of tuples in which a tuple describes a range + data of step charging setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery voltage in uV + or SoC (State of Charge) in percentage when + SoC based step charge is used; + [1]: the high threshold of battery voltage in uV + or SoC in percentage when SoC based step charge + is used; + [2]: the FCC (full charging current) in uA when battery + voltage or SoC falls between the low and high + thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-fcc-ranges: Array of tuples in which a tuple describes a range + data of sw-jeita FCC (full charging current) setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery temperature in deci-degree; + [1]: the high threshold of battery temperature in deci-degree; + [2]: the FCC in uA when battery temperature falls between + the low and high thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-fv-ranges: Array of tuples in which a tuple describes a range + data of sw-jeita FV (float voltage) setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery temperature in deci-degree; + [1]: the high threshold of battery temperature in deci-degree; + [3]: the FV in uV when battery temperature falls between + the low and high thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-soft-thresholds: A tuple entry to specify ADC code for battery's soft JEITA + threshold. . +- qcom,jeita-hard-thresholds: A tuple entry to specify ADC code for battery's hard JEITA + threshold. . +- qcom,jeita-soft-hys-thresholds: A tuple entry to specify ADC code for battery's soft JEITA + threshold with hysteresis adjustment. + . + These "hysteresis" values should be specified if + "qcom,jeita-soft-thresholds" are specified. Without which SW JEITA + compensation won't function properly. +- qcom,jeita-soft-fcc-ua: A tuple entry to specify the values of Fast + charging current (in uA) that needs to be applied during + soft JEITA conditions (cool/warm). + Element 0 - FCC value for soft cool. + Element 1 - FCC value for soft warm. +- qcom,jeita-soft-fv-uv: A tuple entry to specify the values of Float + voltage (in uV) that needs to be applied during soft + JEITA conditions (cool/warm). + Element 0 - FV value for soft cool. + Element 1 - FV value for soft warm. +- qcom,batt-age-level: Battery age level. This is used only when multiple + profile loading is supported. +- qcom,soh-range: A tuple entry to specify the values of SOH range that + the battery profile has to be used for. This needs to + be specified along with "qcom,batt-age-level" for the + proper functionality. + Element 0 - SOH minimum level. + Element 1 - SOH maximum level. +- qcom,step-jeita-hysteresis: A tuple entry to allow configuring the rising + and falling hysteresis for better fine tuning of the + charge current across battery temperature thresholds. + This should be in decidegree and if not specified + default select value is 10 DeciDegC. + +Profile data node required subnodes: +- qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes + temperature to fcc lookup. The units for this lookup + table should be degrees celsius to milliamp-hours. +- qcom,pc-temp-ocv-lut : A 2-dimensional lookup table node that encodes + temperature and percent charge to open circuit voltage + lookup. The units for this lookup table should be + degrees celsius and percent to millivolts. +- qcom,rbatt-sf-lut : A 2-dimentional lookup table node that encodes + temperature and percent charge to battery internal + resistance lookup. The units for this lookup table + should be degrees celsius and percent to milliohms. + +Profile data node optional subnodes: +- qcom,ibat-acc-luit: A 2-dimentional lookup table that encodes temperature + and battery current to battery ACC (apparent charge + capacity). The units for this lookup table should be + temperature in degrees celsius, ibat in milli-amps + and ACC in milli-ampere-hour. + +Lookup table required properties: +- qcom,lut-col-legend : An array that encodes the legend of the lookup table's + columns. The length of this array will determine the + lookup table's width. +- qcom,lut-data : An array that encodes the lookup table's data. The size of this + array should be equal to the size of qcom,lut-col-legend + multiplied by 1 if it's a 1-dimensional table, or + the size of qcom,lut-row-legend if it's a 2-dimensional + table. The data should be in a flattened row-major + representation. + +Lookup table optional properties: +- qcom,lut-row-legend : An array that encodes the legend of the lookup table's rows. + If this property exists, then it is assumed that the + lookup table is a 2-dimensional table. + +Example: + +In msm8974-mtp.dtsi: + +mtp_batterydata: qcom,battery-data { + qcom,rpull-up-kohm = <100>; + qcom,vref-batt-therm-uv = <1800000>; + + /include/ "batterydata-palladium.dtsi" + /include/ "batterydata-mtp-3000mah.dtsi" +}; + +&pm8941_bms { + qcom,battery-data = <&mtp_batterydata>; +}; + +In batterydata-palladium.dtsi: + +qcom,palladium-batterydata { + qcom,fcc-mah = <1500>; + qcom,default-rbatt-mohm = <236>; + qcom,rbatt-capacitive-mohm = <50>; + qcom,flat-ocv-threshold-uv = <3800000>; + qcom,max-voltage-uv = <4200000>; + qcom,v-cutoff-uv = <3400000>; + qcom,chg-term-ua = <100000>; + qcom,batt-id-kohm = <75>; + qcom,jeita-soft-thresholds = <0x3ecc 0x1bff>; + qcom,jeita-hard-thresholds = <0x4aff 0x15aa>; + qcom,step-chg-ranges = <3600000 4000000 3000000 + 4001000 4200000 2800000 + 4201000 4400000 2000000>; + qcom,jeita-fcc-ranges = <0 100 600000 + 101 200 2000000 + 201 450 3000000 + 451 550 600000>; + qcom,jeita-fv-ranges = <0 100 4200000 + 101 450 4350000 + 451 550 4200000>; + qcom,battery-type = "palladium_1500mah"; + + qcom,fcc-temp-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-data = <1492 1492 1493 1483 1502>; + }; + + qcom,pc-temp-ocv-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-row-legend = <100 95 90 85 80 75 70>, + <65 60 55 50 45 40 35>, + <30 25 20 15 10 9 8>, + <7 6 5 4 3 2 1 0>; + qcom,lut-data = <4173 4167 4163 4156 4154>, + <4104 4107 4108 4102 4104>, + <4057 4072 4069 4061 4060>, + <3973 4009 4019 4016 4020>, + <3932 3959 3981 3982 3983>, + <3899 3928 3954 3950 3950>, + <3868 3895 3925 3921 3920>, + <3837 3866 3898 3894 3892>, + <3812 3841 3853 3856 3862>, + <3794 3818 3825 3823 3822>, + <3780 3799 3804 3804 3803>, + <3768 3787 3790 3788 3788>, + <3757 3779 3778 3775 3776>, + <3747 3772 3771 3766 3765>, + <3736 3763 3766 3760 3746>, + <3725 3749 3756 3747 3729>, + <3714 3718 3734 3724 3706>, + <3701 3703 3696 3689 3668>, + <3675 3695 3682 3675 3662>, + <3670 3691 3680 3673 3661>, + <3661 3686 3679 3672 3656>, + <3649 3680 3676 3669 3641>, + <3633 3669 3667 3655 3606>, + <3610 3647 3640 3620 3560>, + <3580 3607 3596 3572 3501>, + <3533 3548 3537 3512 3425>, + <3457 3468 3459 3429 3324>, + <3328 3348 3340 3297 3172>, + <3000 3000 3000 3000 3000>; + }; + + qcom,rbatt-sf-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-row-legend = <100 95 90 85 80 75 70>, + <65 60 55 50 45 40 35>, + <30 25 20 15 10 9 8>, + <7 6 5 4 3 2 1 0>; + qcom,lut-data = <357 187 100 91 91>, + <400 208 105 94 94>, + <390 204 106 95 96>, + <391 201 108 98 98>, + <391 202 110 98 100>, + <390 200 110 99 102>, + <389 200 110 99 102>, + <393 202 101 93 100>, + <407 205 99 89 94>, + <428 208 100 91 96>, + <455 212 102 92 98>, + <495 220 104 93 101>, + <561 232 107 95 102>, + <634 245 112 98 98>, + <714 258 114 98 98>, + <791 266 114 97 100>, + <871 289 108 95 97>, + <973 340 124 108 105>, + <489 241 109 96 99>, + <511 246 110 96 99>, + <534 252 111 95 98>, + <579 263 112 96 96>, + <636 276 111 95 97>, + <730 294 109 96 99>, + <868 328 112 98 104>, + <1089 374 119 101 115>, + <1559 457 128 105 213>, + <12886 1026 637 422 3269>, + <170899 127211 98968 88907 77102>; + }; + + qcom,ibat-acc-lut { + qcom,lut-col-legend = <(-20) 0 25>; + qcom,lut-row-legend = <0 250 500 1000>; + qcom,lut-data = <1470 1470 1473>, + <1406 1406 1430>, + <1247 1247 1414>, + <764 764 1338>; + }; +}; + From ae50d3916fef0f154ed6f5694c83fd73fd9b326c Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 20 Aug 2020 16:15:46 +0530 Subject: [PATCH 0029/1809] ARM: dts: qcom: Optimize jeita-fcc-step thresholds With the current jeita-fcc-step thresholds observing multiple frequent JEITA entry-exit event while charging with higher charge current for longer time, When the JEITA condition is hit, the charge-current is reduced significantly until the battery temperature drops below sw-jeita-hys threshold which causes the overall charge time to increase. Optimize Optimize this by adding some intermediate steps between 10.00A and 1.89A. While at it also change the hysteresis for the same. Change-Id: I8812dfbad10c6cbb0726077106653b9bc27a576d --- qcom/qg-batterydata-atl436186020H_3780mAh.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi index 389a2743a930..e9a359822f57 100644 --- a/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi +++ b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi @@ -12,12 +12,16 @@ qcom,ATL436186_020H_3780mAh { qcom,jeita-fcc-ranges = <0 100 1890000 101 200 3780000 - 201 450 10000000 + 201 420 10000000 + 421 434 8000000 + 435 450 7000000 451 550 1890000>; qcom,jeita-fv-ranges = <0 100 4400000 101 200 4400000 - 201 450 4400000 + 201 420 4400000 + 421 434 4400000 + 435 450 4400000 451 550 4050000>; qcom,step-chg-ranges = <3500000 4000000 10000000 @@ -25,6 +29,8 @@ qcom,ATL436186_020H_3780mAh { 4200001 4400000 6000000>; qcom,ocv-based-step-chg; + /* Rise-Hys = 1 DeciDegC, Fall-Hys=10 deciDegC */ + qcom,qcom,step-jeita-hysteresis = <1 10>; /* COOL = 10 degc, WARM = 45 degC */ qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; /* COLD = 0 degC, HOT = 55 degC*/ From f63ec84c514887844b7a5eb1a62b6dbcdf64bf1f Mon Sep 17 00:00:00 2001 From: Amarnath Vangala Date: Wed, 16 Sep 2020 15:49:57 +0530 Subject: [PATCH 0030/1809] ARM: dts: msm: add mclk lpi gpio entry to all wsa881x entries Add mclk lpi gpio dependency to all wsa881x ananlog entries, to enable the probing at same time. Change-Id: I38293ec98fddc6217fdfb49e95021df04559c97c --- qcom/holi-audio-overlay.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 9075c50d7352..45e1fa8d6686 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -312,6 +312,7 @@ wsa881x_i2c_44: wsa881x-i2c-codec@44 { compatible = "qcom,wsa881x-i2c-codec"; reg = <0x044>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; }; wsa881x_i2c_f: wsa881x-i2c-codec@f { @@ -333,6 +334,7 @@ status = "disabled"; compatible = "qcom,wsa881x-i2c-codec"; reg = <0x045>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; }; }; From 1b0749018564967cd6b07f6ba26d64bbad36cd40 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 16 Sep 2020 12:58:15 +0530 Subject: [PATCH 0031/1809] ARM: dts: msm: Configure WLAN smmu node in atomic context Configure WLAN smmu node in atomic context for holi target. Change-Id: Ia1f6cc75f41d529f6e14f9fb58ea1bfae4db9a42 --- qcom/holi.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 182484754a78..7a08e1cc7921 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2723,12 +2723,14 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x04A1 0x0>; + qcom,iommu-dma = "atomic"; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x04A2 0x0>; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "atomic"; }; ipa_smmu_11ad: ipa_smmu_11ad { From 69107673a831ac24767f5c7b4a295556e0a44bc6 Mon Sep 17 00:00:00 2001 From: Niranjan Dumbala Date: Thu, 17 Sep 2020 09:06:33 -0700 Subject: [PATCH 0032/1809] Revert "ARM: dts: msm: Add GPU SMMU clocks for holi" This reverts commit e125a334037fc4364d9d85e57f25b6e67eb8aaa5. Change-Id: Iae262255b0df2e4664c0ffefd0e79e132999295b --- qcom/holi-gpu.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index 404da3cd5f04..c0728369bff4 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -314,13 +314,6 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; - clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - - clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb", - "gcc_gpu_memnoc_gfx"; - gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; iommus = <&kgsl_smmu 0x0>; From e5aa7edbfe3e0004c7b6bd62e6ca525e4ae35f71 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 11 Sep 2020 10:24:56 +0800 Subject: [PATCH 0033/1809] ARM: dts: msm: add touch for Holi 90hz panel Add touch part with new 90Hz panel for QRD Holi devices. Change-Id: I846d18217128c7ab691fc216cf8003e226df0817 --- qcom/holi-qrd.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index f82bf2910819..f5bfb0d20175 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -120,7 +120,9 @@ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; From 97175c72a58424a9d6f45b0ef965c3cb408c42c6 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 21 Sep 2020 11:25:05 +0530 Subject: [PATCH 0034/1809] ARM: dts: msm: Add pmesg reserved memory for holi Add pmesg reserved memory to enable the function to collect user-space log in pstore. And the mem-type is set to 2 for better performance. Change-Id: I6243e129288cfcf2f6ac73e6ae816a2c47a40515 --- qcom/holi.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index b381eb1cd692..e4f9ed939795 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -348,6 +348,13 @@ label = "dfps_data_region"; }; + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From 4185055aed4bac8648204c4470bed236f15e1891 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Mon, 21 Sep 2020 15:00:25 -0700 Subject: [PATCH 0035/1809] ARM: dts: msm: Remove PM7250B from sdxlemur pmic overlay PM7250B is not present on all sdxlemur platforms; therefore, add it only for the boards on which it is present, in subsequent patches. Change-Id: I945f8b77783afe1fd020189baca79d602b51e4c1 --- qcom/sdxlemur-pmic-overlay.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 67995251e247..62c32d93d892 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -1,8 +1,2 @@ #include "pmk8350.dtsi" #include "pmx65.dtsi" -#include "pm7250b.dtsi" - -&pm7250b_clkdiv { - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; -}; From 457fa54d37fdc8948299714431be3b999896911c Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 9 Sep 2020 15:28:10 -0700 Subject: [PATCH 0036/1809] ARM: dts: msm: Add ADC channels and thermal zones to sdxlemur SDXLemur has five thermal zones that utilize as many ADC channels, all on PMX65. Change-Id: Iabfcbe6edf761c9858a841a6853cc0bddc7e6b80 --- qcom/sdxlemur-pmic-overlay.dtsi | 208 ++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 62c32d93d892..67d96971500f 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -1,2 +1,210 @@ +#include + #include "pmk8350.dtsi" #include "pmx65.dtsi" + +&pmk8350_vadc { + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735a_ref_gnd; + /delete-node/ pmr735a_vref_1p25; + /delete-node/ pmr735a_die_temp; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + pmx65_pa_therm1 { + reg = ; + label = "pmx65_pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_pa_therm2 { + reg = ; + label = "pmx65_pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_mdm_case_therm { + reg = ; + label = "pmx65_mdm_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_ambient_therm { + reg = ; + label = "pmx65_ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_qtm_skin_therm { + reg = ; + label = "pmx65_qtm_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PMX65_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM6_100K_PU>; + + pmx65_pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_mdm_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_qtm_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + modem-lte-sub6-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-lte-sub6-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-skin-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-ambient-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-beamer-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM6_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; From 11475c9f323e79dc16b4c077c516da225e22062f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 12 Aug 2020 11:54:47 +0530 Subject: [PATCH 0037/1809] ARM: dts: msm: Add dummy clock nodes for clock controllers for YUPIK Dummy clock nodes are required for clocks client to request, so add support for the same. Also add the dummy GDSCs required by clients. Change-Id: I2e36c960b4d2e94a492a74f17e5423f73d5adf74 --- qcom/shima-gdsc.dtsi | 14 +++ qcom/yupik.dtsi | 227 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 241 insertions(+) diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index 4b08898def04..d6d058295306 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -32,6 +32,13 @@ status = "disabled"; }; + gcc_usb30_sec_gdsc: qcom,gdsc@19e004 { + compatible = "qcom,gdsc"; + reg = <0x19e004 0x4>; + regulator-name = "gcc_usb30_sec_gdsc"; + status = "disabled"; + }; + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { compatible = "qcom,gdsc"; reg = <0x17d05c 0x4>; @@ -220,4 +227,11 @@ regulator-name = "video_cc_mvs1c_gdsc"; status = "disabled"; }; + + video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 { + compatible = "qcom,gdsc"; + reg = <0xaaf2004 0x4>; + regulator-name = "video_cc_mvsc_gdsc"; + status = "disabled"; + }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 74b1ab864224..103ef0178a48 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1,3 +1,10 @@ +#include +#include +#include +#include +#include +#include +#include #include / { @@ -263,7 +270,227 @@ status = "disabled"; }; }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie-0-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie-1-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + aopcc: qcom,aopcc { + compatible = "qcom,dummycc"; + clock-output-names = "aopcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rpmhcc: qcom,rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +#include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-stub-regulator.dtsi" + +&gcc_pcie_0_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb30_sec_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_titan_top_gdsc { + compatible = "regulator-fixed"; + reg = <0xad0c194 0x4>; + status = "ok"; +}; + +&cam_cc_bps_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&cam_cc_ife_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ife_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ife_2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ipe_0_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + reg = <0xaf01004 0x4>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gpu_gx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + compatible = "regulator-fixed"; + reg = <0xaaf3004 0x4>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&video_cc_mvsc_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; From 436dcfe2614314fa9c6e8d14bb30c9196b2cf7f0 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Tue, 22 Sep 2020 12:28:52 +0530 Subject: [PATCH 0038/1809] ARM: dts: msm: Add entry for non secure display heap memory Add entry to use non secure display heap memory for TUI usecase for shima target. Allocated buffers from this heap will be exported to the secondary VM to use it for composition during TUI session. Change-Id: I86387eb36a5babce9a3d53a2ca15ab4deff40117 --- qcom/shima-ion.dtsi | 5 +++++ qcom/shima.dtsi | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/qcom/shima-ion.dtsi b/qcom/shima-ion.dtsi index fc45b51bedde..2b67df9f2277 100644 --- a/qcom/shima-ion.dtsi +++ b/qcom/shima-ion.dtsi @@ -53,5 +53,10 @@ memory-region = <&audio_cma_mem>; qcom,ion-heap-type = "DMA"; }; + qcom,ion-heap@3 { /* NON SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&non_secure_display_memory>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 798ef30db12d..c82806ce3634 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -469,6 +469,14 @@ reg = <0x0 0xe3300000 0x0 0x0100000>; label = "dfps_data_memory"; }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; + }; }; chosen { From 4fe8ee1b6a1e411925f23858c64e1c1c96080107 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 22 Sep 2020 15:49:07 +0530 Subject: [PATCH 0039/1809] ARM: dts: msm: define new sound card for holi wcd938x with aatc variant Add new sound card to support new mixer path xml for wcd938x with AATC variant of holi. Change-Id: I1caf0fbc9c3471ea4a278f43fda618a7a6df4373 --- qcom/holi-mtp-usbc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index cd6ef96fb833..31d159ac82f7 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -95,6 +95,7 @@ }; &holi_snd { + qcom,model = "holi-mtp-usbc-snd-card"; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; From 09a68ad8b2f1914e4ac03ac15de00bfc59bb222e Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 11 Sep 2020 13:05:35 +0530 Subject: [PATCH 0040/1809] ARM: dts: msm: Enable 747MHz GPU Fmax for Shima Enable 747MHz GPU Fmax as per SKU definitions. Change-Id: I2f38e8399ddda1aa30d5e1ef5fc56ffffc8d5b2b --- qcom/shima-gpu.dtsi | 68 ++++++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index d33fbbcaf1ae..54bd3a552e1c 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -143,10 +143,24 @@ #size-cells = <0>; qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <747000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -154,13 +168,13 @@ qcom,bus-min-ddr7 = <10>; qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; + qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -173,8 +187,8 @@ qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -187,8 +201,8 @@ qcom,bus-max-ddr8 = <10>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -201,8 +215,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -307,10 +321,24 @@ #size-cells = <0>; qcom,speed-bin = <158>; - qcom,initial-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <747000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -318,13 +346,13 @@ qcom,bus-min-ddr7 = <10>; qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; + qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -337,8 +365,8 @@ qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -351,8 +379,8 @@ qcom,bus-max-ddr8 = <10>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -365,8 +393,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <285000000>; qcom,level = ; From ecb995c591a5bf79d1d29b2e7ac40665f675fec8 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 22 Sep 2020 23:26:50 +0800 Subject: [PATCH 0041/1809] ARM: dts: msm: Extend pmic dump size for holi Extend pmic dump size to 2MB for holi. Change-Id: I46b8ac544d4575202a4c0ee6e1828a85c1324fb3 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e4f9ed939795..165d453efd75 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -814,7 +814,7 @@ }; pmic { - qcom,dump-size = <0x40000>; + qcom,dump-size = <0x200000>; qcom,dump-id = <0xe4>; }; From 24232aa76a9648f76782306e20e8165c99f5d860 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 17 Sep 2020 17:59:13 -0700 Subject: [PATCH 0042/1809] ARM: dts: msm: Add PCIe0 PHY settings v1.01 for sdxlemur Add initial PCIe0 PHY setting version 1.01 based on hardware recommendation for sdxlemur. Change-Id: I977b744f7affb74dada2f7be1857caace628b06e --- qcom/sdxlemur-pcie.dtsi | 144 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 753019979959..11ef2356d6b2 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -96,10 +96,152 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <0>; + qcom,pcie-phy-ver = <1101>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x01 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xde 0x0 + 0x1028 0x07 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x14 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x0a 0x0 + 0x10b0 0x1a 0x0 + 0x10b4 0x14 0x0 + 0x10b8 0x34 0x0 + 0x10bc 0x82 0x0 + 0x10c4 0xd0 0x0 + 0x10cc 0x55 0x0 + 0x10d0 0x55 0x0 + 0x10d4 0x03 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x20 0x0 + 0x117c 0x06 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0364 0xcc 0x0 + 0x036c 0xcc 0x0 + 0x0378 0x31 0x0 + 0x037c 0xc5 0x0 + 0x0380 0xcc 0x0 + 0x0384 0xb6 0x0 + 0x0388 0xc2 0x0 + 0x038c 0x17 0x0 + 0x0390 0xfb 0x0 + 0x0394 0x0f 0x0 + 0x039c 0xee 0x0 + 0x03a0 0xbf 0x0 + 0x03a4 0x80 0x0 + 0x03a8 0x81 0x0 + 0x03ac 0xdf 0x0 + 0x03b0 0x5f 0x0 + 0x0b64 0xcc 0x0 + 0x0b6c 0xcc 0x0 + 0x0b78 0x31 0x0 + 0x0b7c 0xc5 0x0 + 0x0b80 0xcc 0x0 + 0x0b84 0xb6 0x0 + 0x0b88 0xc2 0x0 + 0x0b8c 0x17 0x0 + 0x0b90 0xfb 0x0 + 0x0b94 0x0f 0x0 + 0x0b9c 0xee 0x0 + 0x0ba0 0xbf 0x0 + 0x0ba4 0x80 0x0 + 0x0ba8 0x81 0x0 + 0x0bac 0xdf 0x0 + 0x0bb0 0x5f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x2d 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x2d 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x1f 0x0 + 0x0a7c 0x1f 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0d 0x0 + 0x0aec 0x0d 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x141c 0xc1 0x0 + 0x1490 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; From 5913f15c0120a50d5c4988fdf647c5c1cd2189f2 Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Wed, 9 Sep 2020 16:13:54 -0700 Subject: [PATCH 0043/1809] ARM: dts: qcom: disable panic on single corruption Disable panic on the single bit corruptions on lahaina_v1 and enable for lahiana_v2 devices. Change-Id: I259b1723a291ffd72a25aa5e3560f7fad69e6257 --- qcom/lahaina-v2.dtsi | 5 +++++ qcom/lahaina.dtsi | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 1391441bb5d8..a390fd1bf7e1 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -22,6 +22,11 @@ dynamic-power-coefficient = <760>; }; +&kryo_erp { + + /delete-property/ qcom,disable-panic-on-ce; +}; + &sde_dp { /delete-node/ qcom,pll-supply-entries; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..f734b77a1be6 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3240,11 +3240,12 @@ }; }; - kryo-erp { + kryo_erp: erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , ; interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + qcom,disable-panic-on-ce; }; tcsr_mutex_block: syscon@1f40000 { From 0012c033a287818135b4b6ac0b23650026d99a53 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 10 Jun 2020 01:00:12 -0700 Subject: [PATCH 0044/1809] ARM: dts: msm: new vdd power rail of USB QMP PHY for lahaina-v2 The (secondary) USB QMP PHY uses a different power rail for its VDD supply on lahaina-v2. Update it to &pm8350_l5. Change-Id: I29d133cacd12a1108370230dcc1c2f80385ad77e --- qcom/lahaina-v2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 1391441bb5d8..f089e5cd052f 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -126,6 +126,11 @@ compatible = "qcom,lahaina-camcc-v2", "syscon"; }; +&usb_qmp_phy { + vdd-supply = <&pm8350_l5>; + qcom,vdd-voltage-level = <0 880000 888000>; +}; + #include "lahaina-v2-gpu.dtsi" &cpu0_cpu_l3_tbl { From 3ddab065bfebbeb67aeb9707a47c623d79ef63f1 Mon Sep 17 00:00:00 2001 From: Aasir Rasheed Date: Wed, 23 Sep 2020 14:47:59 +0530 Subject: [PATCH 0045/1809] ARM: dts: msm: Update cnss dt node for holi Configure voting parameter for vdd-cx-mx-config. Change-Id: Ib6aa4a541da297f4b3405ea6a7dd6a1d1c07eeed --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 165d453efd75..e7c69f529ce4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2624,7 +2624,7 @@ vdd-1.3-rfa-supply = <&L2E>; vdd-3.3-ch1-supply = <&L11E>; vdd-3.3-ch0-supply = <&L10E>; - qcom,vdd-cx-mx-config = <0 0>; + qcom,vdd-cx-mx-config = <640000 640000>; qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; qcom,smp2p_map_wlan_1_in { From 3dad1a1c0c912713b6ab7aea8c8bdf270d13e1b0 Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Thu, 10 Sep 2020 12:08:14 +0530 Subject: [PATCH 0046/1809] ARM: dts: msm: switch off kpti on holi Switch off kpti on holi as target is not vulnerable. Change-Id: Ica232c595152e0cd40303bb2ab6f92231441a684 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e4f9ed939795..e643db7aa791 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -435,7 +435,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1 kpti=off"; }; }; From ea8649d729ca774297b0e3137254a973fa7ebc97 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Wed, 23 Sep 2020 18:19:28 +0530 Subject: [PATCH 0047/1809] ARM: dts: msm: Add cnss-enable-self-recovery flag for lahaina Add cnss-enable-self-recovery flag for lahaina. It enables self recovery on link down. Update the documentation for the cnss-enable-self-recovery flag. Change-Id: Ifd9f3c23ec8e6c56874f6964cd8134520c2e9c6d --- bindings/cnss/cnss-wlan.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index f047adc4b3f4..02d983d74138 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -85,6 +85,8 @@ Optional properties: - qcom,bus-bw-cfg: Bus bandwidth voting data - qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage regulator used in internal power amplifier for QCA6490 + - cnss-enable-self-recovery: Boolean property to enable self recovery when + recovery is trigeered with reason link down. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..2f48611e3666 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5364,6 +5364,7 @@ /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>; use-pm-domain; + cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S2E>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From af16f9ab870e1b902fe7152b743a723bb9ecb7e4 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 14 Aug 2020 01:31:04 +0530 Subject: [PATCH 0048/1809] dt-bindings: interconnect: add interconnect bindings Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: Icf836295d471a2ee661f772dea883d0bf07ede9c --- bindings/interconnect/qcom,epss-l3.txt | 1 + bindings/interconnect/qcom,yupik.txt | 31 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 bindings/interconnect/qcom,yupik.txt diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index 8bd41c0a753e..d3a31ad4e6df 100644 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -10,6 +10,7 @@ Required properties : "qcom,lahaina-epss-l3-cpu", "qcom,shima-epss-l3-cpu", "qcom,shima-epss-l3-shared"; + "qcom,yupik-epss-l3-cpu", - reg : Address and length of the register set for the device - clock-names: should contain "xo", "alternate" - clocks: list of phandle and clock specifier pairs corresponding to diff --git a/bindings/interconnect/qcom,yupik.txt b/bindings/interconnect/qcom,yupik.txt new file mode 100644 index 000000000000..f60a0b12fe7e --- /dev/null +++ b/bindings/interconnect/qcom,yupik.txt @@ -0,0 +1,31 @@ +Qualcomm Technologies, Inc. Yupik Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Yupik interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,yupik-aggre1_noc", + "qcom,yupik-aggre2_noc", + "qcom,yupik-clk_virt", + "qcom,yupik-config_noc", + "qcom,yupik-dc_noc", + "qcom,yupik-gem_noc", + "qcom,yupik-lpass_ag_noc", + "qcom,yupik-mc_virt", + "qcom,yupik-mmss_noc", + "qcom,yupik-nsp_noc", + "qcom,yupik-system_noc", +- #interconnect-cells : should contain 1 + +Examples: + +aggre1_noc: interconnect@16e0000 { + compatible = "qcom,yupik-aggre1_noc"; + interconnect-cells = <1>; +}; From babd671c62e0c2ee9b58a663fe7d9e6f70b3bae3 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 23 Sep 2020 11:14:38 -0700 Subject: [PATCH 0049/1809] dt-bindings: arm: msm: update documentation for PCIe internal AUX CLK PCIe internal AUX clock frequency used to be either 1MHz or 19.2MHz. The devicetree entry was a boolean type to determine which frequency to program in PCIe controller. Newer chipsets may support other frequencies such as 16.6MHz. Update the devicetree entry so that it accepts a decimal value for the desired frequency to be programmed in PCIe controller. Change-Id: I5818f5973ddbbce4268eafb6e99202daeba4234a --- bindings/pci/pci-msm.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index a864094c6b12..8a9fa1e1c6fe 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -229,10 +229,12 @@ interconnects: link into l1ss sleep while idle in l1ss. If this is omitted, the default timeout is 100ms. -- qcom,use-19p2mhz-aux-clk: +- qcom,aux-clk-freq: Usage: optional - Value type: - Definition: Set PCIe AUX clock frequency to 19.2MHz + Value type: + Definition: Override reset value for PCIe internal aux clock frequency. + Value will be the actual frequency rounded up to the nearest + decimal. For example, use 17 for 16.6MHz. - qcom,common-clk-en: Usage: optional @@ -504,7 +506,6 @@ Example qcom,link-check-max-count = <40> /* 200ms */ qcom,boot-option = <0x1>; qcom,drv-supported; - qcom,use-19p2mhz-aux-clk; qcom,common-clk-en; qcom,clk-power-manage-en; qcom,n-fts = <0x50>; From 2b01efc315a7ddd1bc0b914d58fac4d9df2d5a1b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 23 Sep 2020 11:21:33 -0700 Subject: [PATCH 0050/1809] ARM: dts: msm: remove deprecated PCIe AUX CLK frequency for lahaina PCIe internal AUX clock frequency setting has been change from boolean to u32. On Lahaina, the reset value of this settings is correct and does not need the new devicetree entry to override it. Therefore, remove the deprecated entry for Lahaina. Change-Id: I4b0eb9f3e98ffdf894d4245212e64af618ac80e0 --- qcom/lahaina-pcie.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 451f2627764f..f15c2e4eda1b 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -103,7 +103,6 @@ qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <5000>; - qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; qcom,l1-2-th-scale = <2>; qcom,l1-2-th-value = <70>; @@ -330,7 +329,6 @@ qcom,boot-option = <0x1>; qcom,drv-supported; - qcom,use-19p2mhz-aux-clk; qcom,wr-halt-size = <0x8>; qcom,no-l0s-supported; qcom,slv-addr-space-size = <0x20000000>; From ed8e10b20c2b37033fa207c9ba6f74a21871b744 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 23 Sep 2020 23:39:51 +0530 Subject: [PATCH 0051/1809] ARM: dts: msm: Add device tree for Shima IDP/IDPS with 120fps platform Add device tree support for 1. Shima IDP with 120fps. 2. Shima IDPS digital mics support with 120fps. Change-Id: I7f2e820e2a2b6245b7377bc6432bbcf9e2f9607a --- qcom/Makefile | 12 +++++++++--- qcom/shima-idp-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idp-120fps.dts | 10 ++++++++++ qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idps-digital-mics-120fps.dts | 10 ++++++++++ qcom/shima-idps-digital-mics-120fps.dtsi | 6 ++++++ 7 files changed, 61 insertions(+), 3 deletions(-) create mode 100644 qcom/shima-idp-120fps-overlay.dts create mode 100644 qcom/shima-idp-120fps.dts create mode 100644 qcom/shima-idp-120fps.dtsi create mode 100644 qcom/shima-idps-digital-mics-120fps-overlay.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..7ed2de109fca 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -104,22 +104,28 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ - shima-idp-overlay.dtbo \ + shima-idp-overlay.dtbo \ + shima-idp-120fps-overlay.dtbo \ shima-atp-overlay.dtbo \ shima-qrd-overlay.dtbo \ - shima-idps-digital-mics-overlay.dtbo + shima-idps-digital-mics-overlay.dtbo \ + shima-idps-digital-mics-120fps-overlay.dtbo shima-rumi-overlay.dtbo-base := shima.dtb shima-idp-overlay.dtbo-base := shima.dtb +shima-idp-120fps-overlay.dtbo-base := shima.dtb shima-atp-overlay.dtbo-base := shima.dtb shima-qrd-overlay.dtbo-base := shima.dtb shima-idps-digital-mics-overlay.dtbo-base := shima.dtb +shima-idps-digital-mics-120fps-overlay.dtbo-base := shima.dtb else dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idp.dtb \ + shima-idp-120fps.dtb \ shima-atp.dtb \ shima-qrd.dtb \ - shima-idps-digital-mics.dtb + shima-idps-digital-mics.dtb \ + shima-idps-digital-mics-120fps.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/shima-idp-120fps-overlay.dts b/qcom/shima-idp-120fps-overlay.dts new file mode 100644 index 000000000000..ef17b34fcdb7 --- /dev/null +++ b/qcom/shima-idp-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dts b/qcom/shima-idp-120fps.dts new file mode 100644 index 000000000000..75ea5988bc79 --- /dev/null +++ b/qcom/shima-idp-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi new file mode 100644 index 000000000000..4f6732d3b955 --- /dev/null +++ b/qcom/shima-idp-120fps.dtsi @@ -0,0 +1,4 @@ +#include "shima-idp.dtsi" + +&soc { +}; diff --git a/qcom/shima-idps-digital-mics-120fps-overlay.dts b/qcom/shima-idps-digital-mics-120fps-overlay.dts new file mode 100644 index 000000000000..b5c784b62fb4 --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dts b/qcom/shima-idps-digital-mics-120fps.dts new file mode 100644 index 000000000000..f6773a9471eb --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi new file mode 100644 index 000000000000..51ccf2dd48fd --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -0,0 +1,6 @@ +#include "shima-idps-digital-mics.dtsi" + +&soc { +}; + + From e57572252768c3f3965fcb4df71ade35693bcb26 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 24 Sep 2020 12:13:18 +0530 Subject: [PATCH 0052/1809] dt-bindings: input: touchscren: add description for synaptics_dsx Add new file for synaptics_dsx touchscreen drive IC. Change-Id: I92e089bfad8736e286fd308e98b5b5daf5fefeed --- .../input/touchscreen/synaptics_dsx_i2c.txt | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 bindings/input/touchscreen/synaptics_dsx_i2c.txt diff --git a/bindings/input/touchscreen/synaptics_dsx_i2c.txt b/bindings/input/touchscreen/synaptics_dsx_i2c.txt new file mode 100644 index 000000000000..131942dd0ae9 --- /dev/null +++ b/bindings/input/touchscreen/synaptics_dsx_i2c.txt @@ -0,0 +1,62 @@ +Synaptics DSXV27 touch controller + +Please add this description here: The Synaptics Touch controller is connected to the +host processor via I2C. The controller generates interrupts when the user touches +the panel. The host controller is expected to read the touch coordinates over I2C and +pass the coordinates to the rest of the system. + +Required properties: + + - compatible : should be "synaptics,dsx-i2c". + - reg : i2c slave address of the device. + - interrupt-parent : parent of interrupt. + - synaptics,irq-gpio : irq gpio. + - synaptics,reset-gpio : reset gpio. + - vdd_supply : digital voltage power supply needed to power device. + - avdd_supply : analog voltage power supply needed to power device. + - synaptics,pwr-reg-name : power reg name of digital voltage. + - synaptics,bus-reg-name : bus reg name of analog voltage. + +Optional property: + - synaptics,ub-i2c-addr : addr of ub-i2c. + - synaptics,irq-on-state : status of irq gpio. + - synaptics,cap-button-codes : virtual key code mappings to be used. + - synaptics,vir-button-codes : virtual key code and the response region on panel. + - synaptics,x-flip : modify orientation of the x axis. + - synaptics,y-flip : modify orientation of the y axis. + - synaptics,reset-delay-ms : reset delay for controller (ms), default 100. + - synaptics,power-delay-ms : power delay for controller (ms), default 100. + - synaptics,reset-active-ms : reset active time for controller (ms), default 20. + - synaptics,max-y-for-2d : maximal y value of the panel. + - clock-names : Clock names used for secure touch. They are: "iface_clk", "core_clk" + - clocks : Defined if 'clock-names' DT property is defined. These clocks + are associated with the underlying I2C bus. + +Example: + i2c@78b7000 { + status = "ok"; + synaptics@4b { + compatible = "synaptics,dsx-i2c"; + reg = <0x4b>; + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + vdd_supply = <&pmtitanium_l17>; + avdd_supply = <&pmtitanium_l6>; + synaptics,pwr-reg-name = "vdd"; + synaptics,bus-reg-name = "avdd"; + synaptics,ub-i2c-addr = <0x2c>; + synaptics,irq-gpio = <&tlmm 65 0x2008>; + synaptics,reset-gpio = <&tlmm 99 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-active-ms = <20>; + synaptics,max-y-for-2d = <1919>; /* remove if no virtual buttons */ + synaptics,cap-button-codes = <139 172 158>; + synaptics,vir-button-codes = <139 180 2000 320 160 172 540 2000 320 160 158 900 2000 320 160>; + /* Underlying clocks used by secure touch */ + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + }; + }; From 8572f0b491a8afdb7238a30eaf553ffa41f74b1d Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 24 Sep 2020 10:16:30 -0700 Subject: [PATCH 0053/1809] ARM: dts: msm: Enable USB AHB reset on sdxlemur Rumi AHB reset was disabled as USB enumeration was failing on sdxlemur Rumi due to a RTL related issue. The issue is fixed on RTL version>=E3.9. Hence enable AHB reset as part of PHY reset on Rumi. Change-Id: I2838ac4d624f55901a62d5ee74c1ad7b709f1ab8 --- qcom/sdxlemur-rumi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-rumi.dtsi b/qcom/sdxlemur-rumi.dtsi index f7394765df36..d0967c1dacf5 100644 --- a/qcom/sdxlemur-rumi.dtsi +++ b/qcom/sdxlemur-rumi.dtsi @@ -13,8 +13,8 @@ compatible = "qcom,usb-emu-phy"; reg = <0x0a720000 0x9500>; - qcom,emu-init-seq = <0xfffdf 0x4 - 0xfffd0 0x4 + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 0x100000 0x20 0x0 0x20 0x101f0 0x20 From ae6ad3a83902b23df56e868ea63efcd8ad7dda3b Mon Sep 17 00:00:00 2001 From: Arun Menon Date: Thu, 24 Sep 2020 16:01:21 -0700 Subject: [PATCH 0054/1809] ARM: dts: msm: Change prng dtsi config from 32 bit to 64 bits Set PRNG TPDM to 64 bits for entropy collection to work. Acked-by : Yin Ling Liong Change-Id: I3857164e8bc00fd531083b9c0354d91a895b3f63 --- qcom/lahaina-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index fbe7d8b89e88..3342e9e9e0f5 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -1007,7 +1007,7 @@ <15 64>, <20 64>, <22 32>, - <23 32>, + <23 64>, <24 32>, <27 32>, <28 32>, From dafef6833197d9d2ca539f65804abfc2de03019d Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Thu, 24 Sep 2020 17:33:55 -0700 Subject: [PATCH 0055/1809] ARM: dts: msm: Update USB3 DP QMP Phy sequence for Lahaina to v1.10 Update the QMP USB3 DP PHY init sequence to v1.10 of the HSR. This is a minor update with only two register updates which addresses USB SuperSpeedPlus Gen2 RX compliance testing. Change-Id: I1f4de5c2657bb65861c94eadcde83a2cbe9be9ef --- qcom/lahaina-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..919d251063d6 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -232,7 +232,7 @@ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0 USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0 - USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0 + USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0 USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 @@ -278,7 +278,7 @@ USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0 USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0 - USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0 + USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0 USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0 USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0 USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 From ed3930673281f69e3be79a15b7062c70c5160f1d Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 25 Sep 2020 10:47:40 +0800 Subject: [PATCH 0056/1809] ARM: dts: msm: add touch for Holi 90hz panel Add touch node associated with new 90Hz panel for QRD Holi devices. Change-Id: I846d18217128c7ab691fc216cf8003e226df0817 --- qcom/holi-qrd.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 7ff5d15c5ea8..a9d92ea08dcb 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -120,7 +120,9 @@ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; From 2daf19cb131a0b2a097ef3a0784bd809746ba138 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Mon, 21 Sep 2020 14:17:44 +0530 Subject: [PATCH 0057/1809] ARM: dts: msm: Add lcd display support on holi Add Qsync FHD display support on holi lcd cdp. Change-Id: Ic407db2f1465dbf8e2285d648d605a055d1219d0 --- qcom/holi-cdp-lcd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index b5e20250c0b9..6e5685c7b540 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -14,3 +14,8 @@ qcom,leds-per-string = <4>; }; +&sde_dsi { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; +}; From e9bbb1233ac9939b65615011b3757e1e50649bbf Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 25 Sep 2020 14:05:39 +0530 Subject: [PATCH 0058/1809] ARM: dts: msm: Update L12C min and init voltage on shima Update init voltage and min voltage of L12C LDO to 1.82V on shima platform. Change-Id: I35b641b8ddecf93a5d6443b7861b3f3f0b5c2efa --- qcom/shima-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index e592f7a5df8e..063c7ff9bbe3 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -678,9 +678,9 @@ pm8350c_l12: regulator-pm8350c-l12 { regulator-name = "pm8350c_l12"; qcom,set = ; - regulator-min-microvolt = <1920000>; + regulator-min-microvolt = <1820000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1920000>; + qcom,init-voltage = <1820000>; qcom,init-mode = ; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <60700>; From b607012878fe3b8ccbdde09ca04c235303df0364 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 25 Sep 2020 12:03:32 -0700 Subject: [PATCH 0059/1809] ARM: dts: msm: Remove interconnect phandles from clock nodes Clock optionally votes for interconnect in runtime_resume and runtime_suspend to ensure access to its configuration registers. However, interconnect also votes for clocks when configuring QoS. This can lead to deadlocks between the clock and interconnect frameworks. Voting for interconnects isn't strictly necessary for register access currently, since the required bus (CNOC) is always on when HLOS is running. Voting may become necessary in the future, but until then remove the interconnect phandles to prevent the deadlocks. Change-Id: If4392361a394b7ace52cb95a0ac2184bf64a7882 --- qcom/lahaina.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..7d3ebada79b5 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2347,7 +2347,6 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2360,7 +2359,6 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2372,7 +2370,6 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; From 2362bf12bcde3a15ab40614ab1a8222ea3565c40 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 14 Aug 2020 01:29:41 +0530 Subject: [PATCH 0060/1809] ARM: dts: msm: add stub interconnect devices for YUPIK Add stub interconnect devices for aggre1_noc, aggre2_noc, config_noc, dc_noc, gem_noc, lpass_ag_noc, mc_virt_noc, mmss_noc, nsp_noc, system_noc, This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I3dc8f90709f3db9f7e901e8a00876efe9ceecde0 --- qcom/yupik.dtsi | 62 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 103ef0178a48..6e62ea188e5e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -5,6 +5,9 @@ #include #include #include +#include +#include +#include #include / { @@ -373,6 +376,65 @@ #reset-cells = <1>; }; + clk_virt: interconnect { + compatible = "qcom,yupik-clk_virt"; + #interconnect-cells = <1>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,yupik-config_noc"; + #interconnect-cells = <1>; + }; + + mc_virt: interconnect@1580000 { + compatible = "qcom,yupik-mc_virt"; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,yupik-system_noc"; + #interconnect-cells = <1>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,yupik-aggre1_noc"; + #interconnect-cells = <1>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,yupik-aggre2_noc"; + #interconnect-cells = <1>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,yupik-mmss_noc"; + #interconnect-cells = <1>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,yupik-lpass_ag_noc"; + #interconnect-cells = <1>; + }; + + dc_noc: interconnect@90e0000 { + compatible = "qcom,yupik-dc_noc"; + #interconnect-cells = <1>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,yupik-gem_noc"; + #interconnect-cells = <1>; + }; + + nsp_noc: interconnect@a0c0000 { + compatible = "qcom,yupik-nsp_noc"; + #interconnect-cells = <1>; + }; + + epss_l3_cpu: l3_cpu@18590000 { + compatible = "qcom,yupik-epss-l3-cpu"; + #interconnect-cells = <1>; + }; }; #include "shima-gdsc.dtsi" From dd31ba30eb4d0ac32ebfade3877e8e16a4b840e2 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 7 Aug 2020 13:42:56 +0800 Subject: [PATCH 0061/1809] ARM: dts: msm: enable lt9611uxc for hdk8350 Add lt9611uxc pincttl and dts configure. Change-Id: I9c559051a4779e3b41c6cdc941c3f7fa00765e24 --- qcom/lahaina-hdk.dtsi | 103 ++++++++++++++++++++++++++++++++++++++ qcom/lahaina-pinctrl.dtsi | 13 +++++ 2 files changed, 116 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 5b02c6e0b39f..005e4ff816c5 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -81,3 +81,106 @@ &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; }; + +&qupv3_se15_i2c { + status = "ok"; + + lt9611: lt,lt9611@2b { + compatible = "lt,lt9611uxc"; + reg = <0x2b>; + interrupt-parent = <&tlmm>; + interrupts = <50 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 50 0x0>; + lt,reset-gpio = <&tlmm 48 0x0>; + lt,hdmi-3p3-en = <&tlmm 47 0x0>; + lt,hdmi-1p2-en = <&tlmm 49 0x0>; + lt,non-pluggable; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_pins>; + + lt,preferred-mode = "1920x1080"; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <148500>; + }; + + lt,customize-mode-id@1 { + lt,mode-h-active = <3840>; + lt,mode-h-front-porch = <176>; + lt,mode-h-pulse-width = <88>; + lt,mode-h-back-porch = <400>; + lt,mode-h-active-high; + lt,mode-v-active = <2160>; + lt,mode-v-front-porch = <8>; + lt,mode-v-pulse-width = <10>; + lt,mode-v-back-porch = <72>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <608040>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in_0: endpoint { + remote-endpoint = <&ext_dsi_0_out>; + }; + }; + + port@1 { + reg = <1>; + lt9611_in_1: endpoint { + remote-endpoint = <&ext_dsi_1_out>; + }; + }; + }; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_0_out: endpoint { + remote-endpoint = <<9611_in_0>; + }; + }; + }; +}; + +&sde_dsi1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + ext_dsi_1_out: endpoint { + remote-endpoint = <<9611_in_1>; + }; + }; + }; +}; diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi index 4da16fb2cccb..3c81288625d9 100644 --- a/qcom/lahaina-pinctrl.dtsi +++ b/qcom/lahaina-pinctrl.dtsi @@ -380,6 +380,19 @@ }; }; + lt9611_pins: lt9611_pins { + mux { + pins = "gpio47", "gpio48", "gpio49", "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", "gpio50"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + nfc { nfc_int_active: nfc_int_active { /* active state */ From fd0c05ce1af0e4e34f102c2b103695eb431c499b Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 16 Sep 2020 17:25:55 +0530 Subject: [PATCH 0062/1809] ARM: dts: msm: Add touch support for holi Add Synaptics dsx touch support for qsync fhd panel on holi cdp. Change-Id: I8969d9599a2998a508089874519f5ca4630d99c7 --- qcom/holi-cdp-lcd.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 6e5685c7b540..057607ce47a3 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -19,3 +19,34 @@ ibb-supply = <&lcdb_ncp_vreg>; qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; }; + +&qupv3_se8_i2c { + qcom,i2c-touch-active="synaptics,dsx-i2c"; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,reset-gpio = <&tlmm 21 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + + panel = <&dsi_sharp_qsync_fhd_video>; + }; +}; From 690d106d3d544e9c979c8b33135f934a446d23df Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Tue, 1 Sep 2020 20:21:57 +0530 Subject: [PATCH 0063/1809] ARM: dts: msm: add initial support for hw memlat devices Add initial support for RIMPS memlat devices, it votes for L3 clock based on the IPM ratio falling below set_threshold. Change-Id: I2d2a5f8688513dd4fac23f16dc4e140f4fce0b0f --- qcom/holi.dtsi | 266 ++++++++++++++++++------------------------------- 1 file changed, 98 insertions(+), 168 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 165d453efd75..e5a0ef6954b8 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -434,6 +434,19 @@ }; }; + sram: sram@fd04480 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x0fd04480 0x0 0x80>; + ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x80>; + }; + }; + chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; }; @@ -1315,66 +1328,6 @@ qcom,count-unit = <0x10000>; }; - cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; - }; - - cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; - }; - - cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; - }; - - cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; - }; - - cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; - }; - - cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; - }; - cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devfreq-icc"; governor = "compute"; @@ -1383,26 +1336,6 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; - cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; - }; - - cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; - }; - cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -1427,78 +1360,10 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; - cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { - qcom,core-dev-table = - < 710400 300000000 >, - < 940800 518400000 >, - < 1190400 748800000 >, - < 1478400 921600000 >, - < 1574400 1305600000 >, - < 1804800 1459000000 >; - }; - - cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { - qcom,core-dev-table = - < 1017600 518400000 >, - < 1248000 748800000 >, - < 1536000 921600000 >, - < 1651200 1171200000 >, - < 1804800 1305600000 >, - < 2035200 1459000000 >; - }; - cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0>; - qcom,target-dev = <&cpu0_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU1>; - qcom,target-dev = <&cpu1_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU2>; - qcom,target-dev = <&cpu2_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU3>; - qcom,target-dev = <&cpu3_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4>; - qcom,target-dev = <&cpu4_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU5>; - qcom,target-dev = <&cpu5_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; @@ -1527,26 +1392,6 @@ compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU6 &CPU7>; - cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6>; - qcom,target-dev = <&cpu6_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; - }; - - cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu7_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; - }; - cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; @@ -1573,6 +1418,91 @@ }; }; + rimps: qcom,rimps@0f400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps"; + reg = <0x0f400000 0x10>, + <0x0fd90000 0x2000>; + #mbox-cells = <1>; + interrupts = <0 22 4>; + }; + + cpu0_grp: qcom,cpu0_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0fd04980 0x300>; + reg-names = "pmu-base"; + + cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cachemiss-ev = <0x17>; + reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + }; + + cpu6_grp: qcom,cpu6_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0fd04980 0x300>; + reg-names = "pmu-base"; + + cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cachemiss-ev = <0x17>; + qcom,wb-ev = <0x18>; + qcom,access-ev = <0x2B>; + reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&rimps 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_memlat: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + rimps_log: qcom,rimps_log@fd04780 { + compatible = "qcom,rimps-log"; + reg = <0x0fd04580 0x200>, + <0x0fd04780 0x200>; + mboxes = <&rimps 1>; + }; + tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; From f53721e040fe5d5d09cf3f31f4798212b602485a Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Mon, 17 Aug 2020 15:52:56 +0530 Subject: [PATCH 0064/1809] ARM: dts: msm: reserved memory for yupik Add carveout memory regions for yupik. This carveout memory is used by various subsystems for their purpose. Change-Id: I67d4224a4e2452b1c7645f76883f5e40a6ecc3d3 --- qcom/yupik.dtsi | 117 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6e62ea188e5e..7c8173cfd526 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -177,6 +177,123 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: cmd_db@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + secdata_apss_mem: secdata_apss@808ff000 { + no-map; + reg = <0x0 0x808ff000 0x0 0x1000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + wlan_fw_mem: wlan_fw@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0xc00000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap@81800000 { + no-map; + reg = <0x0 0x81800000 0x0 0x1e00000>; + }; + + pil_cvp_mem: camera@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: video@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: cvp@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_mem: mpss@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0xf600000>; + }; + + pil_wpss_mem: wlan@9ae00000 { + no-map; + reg = <0x0 0x9ae00000 0x0 0x1900000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + soc: soc { }; chosen { }; From 492e6cc84259e924cff67bfdc3d0b2402d5894c8 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 24 Sep 2020 09:57:30 +0530 Subject: [PATCH 0065/1809] ARM: dts: msm: Add 144 fps touch support on shima target Add 144 fps panel touch support on shima target. Change-Id: I67d8a042a66c157acbeed0ed1452ed36e0e4c9f7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index d0a694ca961b..a4be84ba4aee 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -180,7 +180,8 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video - &dsi_r66451_amoled_60hz_cmd>; + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 6019f2707aea4483b7085ebd2de78276ad157810 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 28 Sep 2020 18:54:28 +0530 Subject: [PATCH 0066/1809] ARM: dts: msm: Update focaltech enteries on shima trustedvm Add display-coords and max-touch focaltech touch enteries on trusted vm for shima platform. Change-Id: I760f5e7c23527243320ac438173a0de35ded7cb6 --- qcom/shima-vm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 2ef350f4a81f..03d7359ab920 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -276,6 +276,8 @@ focaltech@38 { compatible = "focaltech,fts_ts"; reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "tvm"; focaltech,trusted-touch-spi-irq = <566>; From 58dced493dbf42f19ac1527532700627342e8159 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 28 Sep 2020 19:59:20 +0530 Subject: [PATCH 0067/1809] ARM: dts: msm: Update focaltech enteries on lahaina qrd trustedvm Add display-coords and max-touch focaltech touch enteries on trusted vm for lahaina QRD platform. Change-Id: Id3b9029f35462f9af9a6a657e401ed9fdf3c21cb --- qcom/lahaina-vm-qrd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-vm-qrd.dtsi b/qcom/lahaina-vm-qrd.dtsi index f2010601c08b..863f06638c78 100644 --- a/qcom/lahaina-vm-qrd.dtsi +++ b/qcom/lahaina-vm-qrd.dtsi @@ -5,6 +5,8 @@ focaltech@38 { compatible = "focaltech,fts_ts"; reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "tvm"; focaltech,trusted-touch-spi-irq = <566>; From e913d2e227badd475cb311c587749904bb0a963c Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 28 Sep 2020 11:47:52 -0700 Subject: [PATCH 0068/1809] ARM: dts: msm: Add modem mitigation for policy engine in lahaina Add Modem mitigation for both CX and MX policy engine violation in lahaina. Change-Id: I1486e167ca4168d835191c8a18d91c4ef5fd8a96 --- qcom/lahaina-thermal.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 3ed3d6eaac4b..933fdf203ac5 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -1218,6 +1218,12 @@ hysteresis = <1>; type = "passive"; }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; }; cooling-maps { @@ -1230,6 +1236,11 @@ trip = <&mx_pe_config2>; cooling-device = <&msm_gpu 1 1>; }; + + mx_pe_cdev_3 { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 1 1>; + }; }; }; @@ -1258,6 +1269,12 @@ }; cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config5: cx-pe-config5 { temperature = <5>; hysteresis = <2>; type = "passive"; @@ -1282,6 +1299,11 @@ cx_pe_cdev_4 { trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 1 1>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config5>; cooling-device = <&cdsp_sw 4 4>; }; }; From 8fd1f5ec43991e0eb8c4cd34b72e8a4d0ea39784 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 18 Sep 2020 17:01:13 -0700 Subject: [PATCH 0069/1809] ARM: dts: msm: Add emergency skin rule for lahaina Add emergency skin rule based on xo-therm to trigger frequency mitigation and core isolation at 78C and hotplug at 80C. Change-Id: I9fef2b9bdf827f9b660d7c1e34d55607cbd4b97b --- qcom/lahaina-pmic-overlay.dtsi | 21 ++++++++++++ qcom/lahaina-thermal-overlay.dtsi | 56 +++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 052c892cc915..5bb23e5950e5 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -607,6 +607,27 @@ }; }; }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + + trips { + xo_config0: active-config0 { + temperature = <78000>; + hysteresis = <8000>; + type = "passive"; + }; + + xo_config1: active-config1 { + temperature = <80000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; }; &soc { diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index 2889f53abedb..15a3f166fc78 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -296,4 +296,60 @@ }; }; }; + + xo-therm-step { + cooling-maps { + cpu4_freq_cdev { + trip = <&xo_config0>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu7_freq_cdev { + trip = <&xo_config0>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu4_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu5_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu6_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu7_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu4_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + + cpu5_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + + cpu6_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + + cpu7_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; }; From b7e3313c0c981eab7be798fa121dd4c6bf67f3a9 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 10 Sep 2020 16:12:06 -0700 Subject: [PATCH 0070/1809] ARM: dts: msm: Update core isolation and hotplug threshold for lahaina Update core isolation and hotplug threshold for silver CPUs to 110C and 112C. Update core isolation and hotplug threshold for gold and gold plus to 108C and 110C. Change-Id: Id7d883e751a773869dea9f320e7f055da7584a69 --- qcom/lahaina-thermal.dtsi | 168 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 933fdf203ac5..8be59cb4c62e 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -778,6 +778,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -785,6 +791,17 @@ trip = <&cpu00_config>; cooling-device = <&cpu0_isolate 1 1>; }; + + cpu00_cdev1 { + trip = <&cpu00_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; }; }; @@ -799,6 +816,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -806,6 +829,17 @@ trip = <&cpu01_config>; cooling-device = <&cpu1_isolate 1 1>; }; + + cpu01_cdev1 { + trip = <&cpu01_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; }; }; @@ -820,6 +854,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -827,6 +867,17 @@ trip = <&cpu02_config>; cooling-device = <&cpu2_isolate 1 1>; }; + + cpu02_cdev1 { + trip = <&cpu02_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; }; }; @@ -841,6 +892,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -848,6 +905,17 @@ trip = <&cpu03_config>; cooling-device = <&cpu3_isolate 1 1>; }; + + cpu03_cdev1 { + trip = <&cpu03_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; }; }; @@ -858,6 +926,12 @@ thermal-governor = "step_wise"; trips { cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -875,6 +949,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -885,6 +964,12 @@ thermal-governor = "step_wise"; trips { cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -902,6 +987,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -912,6 +1002,12 @@ thermal-governor = "step_wise"; trips { cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -929,6 +1025,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -939,6 +1040,12 @@ thermal-governor = "step_wise"; trips { cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -956,6 +1063,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -966,6 +1078,12 @@ thermal-governor = "step_wise"; trips { cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -983,6 +1101,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -993,6 +1116,12 @@ thermal-governor = "step_wise"; trips { cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1010,6 +1139,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -1020,6 +1154,12 @@ thermal-governor = "step_wise"; trips { cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1031,6 +1171,17 @@ trip = <&cpu16_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu16_cdev1 { + trip = <&cpu16_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; @@ -1041,6 +1192,12 @@ thermal-governor = "step_wise"; trips { cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1052,6 +1209,17 @@ trip = <&cpu17_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu17_cdev1 { + trip = <&cpu17_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; From b69712d471e1cf4e4b2e98ada10ee7972c047cb8 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 29 Sep 2020 10:32:14 +0530 Subject: [PATCH 0071/1809] ARM: dts: msm: Disable wakeup capability for soundwire gpio Disable wakeup capability for soundwire gpio to avoid frequent wakeup during power collapse. Also register wakeup event listener as part of tx macro. Change-Id: I20367d0c7798a76eaebfaf3a5e00db78abca72fa --- qcom/shima-audio-overlay.dtsi | 2 +- qcom/shima-audio.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 46490d3e67a6..5c44652dd529 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -33,7 +33,6 @@ qcom,va-dmic-sample-rate = <600000>; qcom,default-clk-id = ; qcom,is-used-swr-gpio = <0>; - qcom,disable-afe-wakeup-event-listener = <1>; }; tx_macro: tx-macro@3220000 { @@ -44,6 +43,7 @@ <&clock_audio_tx_2 0>; qcom,tx-swr-gpios = <&tx_swr_gpios>; qcom,tx-dmic-sample-rate = <2400000>; + qcom,disable-afe-wakeup-event-listener = <1>; swr2: tx_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; diff --git a/qcom/shima-audio.dtsi b/qcom/shima-audio.dtsi index 752938f13ecf..10ee18cc06de 100644 --- a/qcom/shima-audio.dtsi +++ b/qcom/shima-audio.dtsi @@ -109,6 +109,7 @@ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep &rx_swr_data1_sleep>; qcom,lpi-gpios; + qcom,tlmm-pins = <172>; #gpio-cells = <0>; }; From 24076fd7c4e619ccab338181ebe05f426f8fa05c Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Mon, 28 Sep 2020 12:40:48 +0800 Subject: [PATCH 0072/1809] ARM: dts: msm: New touch node for Lahaina CDP Add Synaptics touch node for qsync wqhd panel on Lahaina devices. Change-Id: I0fb7c9cdbcedb0ddd693fd62cd0b64a928327e77 --- qcom/lahaina-cdp.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 744c2ed73802..5bee66f2ef19 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -124,6 +124,32 @@ atmel,display-coords = <0 0 339 729>; panel = <&dsi_sharp_qhd_plus_dsc_cmd>; }; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + vdd-supply = <&L8C>; + avdd-supply = <&L3C>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 23 0x2008>; + synaptics,reset-gpio = <&tlmm 22 0x00>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + + panel = <&dsi_sharp_qsync_wqhd_cmd &dsi_sharp_qsync_wqhd_video>; + }; }; &sdhc_2 { From 2af32db2474b746eb0860938357e0519558348a1 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 29 Sep 2020 12:11:12 +0530 Subject: [PATCH 0073/1809] ARM: dts: msm: add is-always-on flag to fix HS LPI issue for holi Added is-always-on flag to skip the audio_hm vote during bootup and to vote/unvote during swrm_runtime_suspend and swrm_runtime_resume. Change-Id: Ifce00a198056590a3de7076c17b3c9f45a30fbc7 --- qcom/holi-audio-overlay.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 45e1fa8d6686..987572a7db74 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -57,6 +57,7 @@ qcom,swr-num-dev = <1>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; + qcom,is-always-on = <1>; wcd937x_tx_slave: wcd937x-tx-slave { compatible = "qcom,wcd937x-slave"; reg = <0x0A 0x01170223>; From 2c77fff619eafb24bfb5c328d4e7afdd0137243a Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 29 Sep 2020 15:31:37 +0800 Subject: [PATCH 0074/1809] ARM: dts: msm: Correct name of funnel merg on holi Correct name of funnel merg to "coresight-funnel-merg" on holi. Change-Id: If4c7d688f333f6b2d75e6570f40a1b401fefe55a --- qcom/holi-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index bb43ec947b84..95a7723749e2 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1906,13 +1906,13 @@ }; }; - funnel_merge: funnel@8045000 { + funnel_merg: funnel@8045000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb908>; reg = <0x08045000 0x1000>; reg-names = "funnel-base"; - coresight-name = "coresight-funnel-merge"; + coresight-name = "coresight-funnel-merg"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; From 8e5996c2ef9170805f371c7856726f7c87edaa28 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 18 Aug 2020 12:47:51 +0530 Subject: [PATCH 0075/1809] ARM: dts: msm: Add Qpic Nand support for sdxlemur Add QPIC NAND Controller support for sdxlemur in device tree. Change-Id: I411d63c2b0c9aed2f43dcdc5a05d6527ca97d01b --- qcom/sdxlemur-cdp.dtsi | 3 +++ qcom/sdxlemur-mtp.dtsi | 3 +++ qcom/sdxlemur-rumi.dtsi | 4 ++++ qcom/sdxlemur.dtsi | 17 +++++++++++++++++ 4 files changed, 27 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 768d9aaa521c..0439a942f1ec 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -4,3 +4,6 @@ }; +&qnand_1 { + status = "ok"; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 768d9aaa521c..0439a942f1ec 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -4,3 +4,6 @@ }; +&qnand_1 { + status = "ok"; +}; diff --git a/qcom/sdxlemur-rumi.dtsi b/qcom/sdxlemur-rumi.dtsi index f7394765df36..ec2a407bd2fa 100644 --- a/qcom/sdxlemur-rumi.dtsi +++ b/qcom/sdxlemur-rumi.dtsi @@ -26,6 +26,10 @@ }; +&qnand_1 { + status = "ok"; +}; + &usb { dwc3@a600000 { usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a9a6ec23a414..de55954f16c2 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -386,6 +386,23 @@ status = "ok"; }; + qnand_1: nand@1b00000 { + compatible = "qcom,msm-nand"; + reg = <0x01b00000 0x1000>, + <0x01b04000 0x1c000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = ; + interrupt-names = "bam_irq"; + + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + + status = "disabled"; + }; + apsscc: clock-controller@17808000 { compatible = "qcom,dummycc"; clock-output-names = "apsscc_clocks"; From 77750f931fae97bc18b07e3995b3030ec6e2d5ac Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 24 Sep 2020 15:26:58 +0530 Subject: [PATCH 0076/1809] ARM: dts: qcom: Update cp channel names for holi Update cp channel names for holi Change-Id: Ibe008356432ca4ab445ae152e585e951c5509746 --- qcom/holi-mtp-usbc.dtsi | 6 +++--- qcom/holi-mtp.dtsi | 6 +++--- qcom/holi-qrd.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index fddd4d338dda..99073ba1061c 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -236,9 +236,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 25c4885ccb47..77dcb6330af0 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -217,9 +217,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index a9d92ea08dcb..48e5127acab5 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -294,9 +294,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", From c991dea0858fda959ad35479ab9c9474329859ac Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 30 Sep 2020 08:46:07 +0530 Subject: [PATCH 0077/1809] dt-bindings: Add DT bindings for BLSP UART drivers Add dt-bindings for UART BLSP driver. This change adds a snapshot of BLSP UART driver bindings from the 4.14 branch. kernel-4.14 baseline: 'commit 5b51cb0c0e2c474f1f ("serial: msm_serial_hs: Add snapshot of serial highspeed driver")'. Removed ICB bus voting properties and replaced them with new ICC framework properties. Change-Id: I8316c36375ed34d008e6d6e456e807ecc5814b39 --- bindings/serial/msm_serial_hs.txt | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 bindings/serial/msm_serial_hs.txt diff --git a/bindings/serial/msm_serial_hs.txt b/bindings/serial/msm_serial_hs.txt new file mode 100644 index 000000000000..fa2e664fafa8 --- /dev/null +++ b/bindings/serial/msm_serial_hs.txt @@ -0,0 +1,120 @@ +* Qualcomm Technologies Inc, BLSP MSM HSUART + +Required properties: +- compatible : + - "qcom,msm-hsuart-v14" to be used for UARTDM Core v1.4 +- reg : offset and length of the register set for both the device, + uart core and bam core +- reg-names : + - "core_mem" to be used as name of the uart core + - "bam_mem" to be used as name of the bam core +- interrupts : interrupts for both the device,uart core and bam core +- interrupt-names : + - "core_irq" to be used as uart irq + - "bam irq" to be used as bam irq +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt + source. The type shall be a and the value shall be 1 +- #address-cells: Specifies the number of cells needed to encode an address. + The type shall be and the value shall be 0 +- interrupt-parent = It is needed for interrupt mapping +- bam-tx-ep-pipe-index : BAM TX Endpoint Pipe Index for HSUART +- bam-rx-ep-pipe-index : BAM RX Endpoint Pipe Index for HSUART + +BLSP has a static pipe allocation and assumes a pair-pipe for each uart core. +Pipes [2*i : 2*i+1] are allocated for UART cores where i = [0 : 5]. +Hence, Minimum and Maximum permitted value of endpoint pipe index to be used +with uart core is 0 and 11 respectively. + +There is one HSUART block used in MSM devices, +"qcom,msm-hsuart-v14". The msm-serial-hs driver is +able to handle this, and matches against the "qcom,msm-hsuart-v14" +as the compatibility. + +The registers for the "qcom,msm-hsuart-v14" device need to specify both +register blocks - uart core and bam core. + +Example: + + uart7: uart@f995d000 { + compatible = "qcom,msm-hsuart-v14"; + reg = <0xf995d000 0x1000>, + <0xf9944000 0x5000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq"; + #address-cells = <0>; + interrupt-parent = <&uart7>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map = <0 &intc 0 113 0 + 1 &intc 0 239 0> + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + }; + +Optional properties: +- qcom,-gpio : handle to the GPIO node, see "gpios property" in +Documentation/devicetree/bindings/gpio/gpio.txt. +"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs +need to configured. +Gpio's are optional if it is required to be not configured by UART driver or +case where there is nothing connected and we want to use internal loopback mode +for uart. +- qcom, wakeup_irq : UART RX GPIO IRQ line to be configured as wakeup source. +- qcom,inject-rx-on-wakeup : inject_rx_on_wakeup enables feature where on +receiving interrupt with UART RX GPIO IRQ line (i.e. above wakeup_irq property), +HSUART driver injects provided character with property rx_to_inject. +- qcom, rx-char-to-inject : The character to be inserted on wakeup. +- qcom, no-suspend-delay : This decides system to go to suspend immediately +or not + +- interconnects: pairs of phandles and interconnect provider specifier + to denote the edge source and destination ports of + the interconnect path. Please refer to + Documentation/devicetree/bindings/interconnect/ + for more details. +- interconnect-names: List of interconnect path name strings sorted in the same + order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect + specifiers. Please refer to Documentation/devicetree/bindings/ + interconnect/ for more details. + +Aliases : +An alias may be optionally used to bind the UART device to a TTY device +(ttyHS) with a given alias number. Aliases are of the form +uart where is an integer representing the alias number to use. +On systems with multiple UART devices present, an alias may optionally be +defined for such devices. The alias value should be from 0 to 255. + +Example: + + aliases { + uart4 = &uart7; // This device will be enumerated as ttyHS4 + }; + + uart7: uart@f995d000 { + compatible = "qcom,msm-hsuart-v14" + reg = <0x19c40000 0x1000">, + <0xf9944000 0x5000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&uart7>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 113 0 + 1 &intc 0 239 0 + 2 &msmgpio 42 0>; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; + qcom,inject-rx-on-wakeup = <1>; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + }; From ec9f758a19b5fae404045dea451449f476864b90 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Mon, 28 Sep 2020 15:46:14 +0530 Subject: [PATCH 0078/1809] dt-bindings: qcom-sps-dma: Add snapshot of SPS DMA driver This change adds a snapshot of SPS DMA driver from the 4.19 branch. kernel-4.19 baseline: 'commit b159d5da02b7 ("dt-bindings: Add documentation for SDM660")'. Change-Id: I1997961ee887e0657602e3456cee7f1ff88ae368 --- bindings/dma/qcom-sps-dma.txt | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/dma/qcom-sps-dma.txt diff --git a/bindings/dma/qcom-sps-dma.txt b/bindings/dma/qcom-sps-dma.txt new file mode 100644 index 000000000000..c6c8726dac26 --- /dev/null +++ b/bindings/dma/qcom-sps-dma.txt @@ -0,0 +1,42 @@ +* Qualcomm technologies inc, DMA engine driver for BAM (Bus Access Manager). + +Required properties: +- compatible: Should be "qcom,sps-dma". +- reg: Should contain DMA registers location and length. This should include + all of the per-channel registers. +- interrupts: Should contain the BAM interrupt number. +- qcom,summing-threshold: Should contain the BAM event threshold of + the sum of descriptors' sizes in bytes. + +Optional properties: +- qcom,managed-locally : Use when BAM global device control is managed locally + by the application processor. + +Example: + + dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xf9904000 0x19000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <10>; + }; + +DMA clients connected to the qcom-sps-dma DMA controller must use the format +described in the dma.txt file, using a five-cell specifier for each channel, +a phandle plus four integer cells, as shown below: + +dmas = <[phandle of the dma controller] [pipe index] [number of descriptors] + [sps_connect flags] [sps_register_event flags]>; + +Example: + +i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ + . + . + . + /* <&phandle pipe-idx n-descs connect-flags event-flags> */ + dmas = <&dma_blsp1 14 32 0x20000020 0x20>, + <&dma_blsp1 15 64 0x20000020 0x20>; + dma-names = "tx", "rx"; +}; From 6f5e4071818ba5f5c7dfae6062d063335bb55ed3 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Thu, 24 Sep 2020 14:09:36 +0530 Subject: [PATCH 0079/1809] dt-bindings: i2c-msm-v2: Add snapshot of I2C MSM V2 driver This change adds a snapshot of I2C MSM V2 driver from the 4.14 branch. kernel-4.14 baseline: 'commit 2aa77f468a3d ("i2c-msm-v2: Replace HW recovery mechanism with SW bit-banging")'. Change-Id: Ia0604ce27bdf29018b911d7ab2baa3e70d70b31f --- bindings/i2c/i2c-msm-v2.txt | 59 +++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 bindings/i2c/i2c-msm-v2.txt diff --git a/bindings/i2c/i2c-msm-v2.txt b/bindings/i2c/i2c-msm-v2.txt new file mode 100644 index 000000000000..7c0ec7dba150 --- /dev/null +++ b/bindings/i2c/i2c-msm-v2.txt @@ -0,0 +1,59 @@ +Qualcomm Technologies, Inc. I2C controller + +Required properties: + - reg : Offset and length of the register region for the device named in + reg-names and has the same index. + - reg-names : Register region name(s) referenced in reg above + "qup_phys_addr" : Physical address of QUP register space. + - compatible : should be "qcom,i2c-msm-v2" + - interrupts : Interrupt number which correspond to the entry with the same + index in interrupt-names. + - interrupt-names: QUP core interrupt name(s) referenced in interrupts above + "qup_irq" : QUP interrupt used by the controller. + - dmas : DMA engine API's parameters for blsp. + <[phandle of the dma controller] [pipe index] [number of descriptors] + [sps_connect flags] [sps_register_event flags]>; + - dma-names : dma channel names. + - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz + - qcom,clk-freq-in : Supplied core clock frequency in Hz. + - qcom,i2c-dat : specifies GPIO which corresponds to the I2C data line. + - qcom,i2c-clk : specifies GPIO which corresponds to the I2C clock line. + +Required alias: + - The desired bus-number is specified by an alias with the following format: + 'i2c{n}' where n is the bus number. + +Optional property: + - qcom,noise-rjct-scl : number of low samples on clock line to consider it low. + When missing default to 0. + - qcom,noise-rjct-sda : number of low samples on data line to consider it low. + When missing default to 0. + - qcom,disable-dma : disables DMA transfer mode. + - qcom,master-id : Master-port value used on voting for the clock path. + - qcom,high-time-clk-div : high time divider value to configure clk-ctl + register. When missing, default to the value given in driver. + - qcom,fs-clk-div: fs divider value to configure clk-ctl register. When + missing, default to the value given in driver. + +Example: + aliases { + i2c10 = &i2c_10; + }; + + i2c_10: i2c@f9966000 { + compatible = "qcom,i2c-msm-v2"; + reg-names = "qup_phys_addr", "dma_phys_addr"; + reg = <0xf9966000 0x1000>; + interrupt-names = "qup_irq"; + interrupts = <0 104 0>; + dmas = <&dma_blsp1 14 32 0x20000020 0x20>, + <&dma_blsp1 15 64 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,clk-freq-out = <100000>; + qcom,clk-freq-in = <24000000>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,i2c-dat = <&tlmm 67 0x00>; + qcom,i2c-clk = <&tlmm 68 0x00>; + + }; From 81a0a04825de2f5fab0fd9a62766cb4200833537 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Wed, 30 Sep 2020 09:50:48 +0530 Subject: [PATCH 0080/1809] ARM: dts: msm: Enable U1 and U2 on Holi The USB Gen1 DWC3 controller supports the U1 and U2 in USB3.0 mode. Hence enable the same on Holi. Change-Id: Ic6a84900803f8dc12aef6e3eba56b06e4a4487d2 --- qcom/holi-usb.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index beca47439f58..d7859b6330c5 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -66,8 +66,6 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,is-utmi-l1-suspend; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; From c9d559494c4733c2be2705a503ed03cfc9d50caa Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 17 Sep 2020 18:01:52 +0530 Subject: [PATCH 0081/1809] ARM: dts: msm: Add BLSP DTSI nodes on sdxlemur Add BLSP(I2C, SPI and UART) DTSI nodes on sdxlemur Change-Id: I7f6b1ce3ec27421500a5b52072b202c56fcdd618 --- qcom/sdxlemur-blsp.dtsi | 545 ++++++++++++++++++++++ qcom/sdxlemur-pinctrl.dtsi | 903 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 3 +- 3 files changed, 1450 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-blsp.dtsi diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi new file mode 100644 index 000000000000..997db6b37078 --- /dev/null +++ b/qcom/sdxlemur-blsp.dtsi @@ -0,0 +1,545 @@ +#include "sdxlemur-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@804000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x804000 0x23000>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x837000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 84,85 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@835000 { /* BLSP1 QUP1: GPIO: 82,83 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@836000 { /* BLSP1 QUP2: GPIO: 65,66 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@838000 { /* BLSP1 QUP4 GPIO: 18,19 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x835000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x836000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x837000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x838000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 1 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1a_tx_sleep>, + <&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1a_tx_active>, + <&blsp1_uart1a_rxcts_active>, + <&blsp1_uart1a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 48,49,80,81 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1b_tx_sleep>, + <&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1b_tx_active>, + <&blsp1_uart1b_rxcts_active>, + <&blsp1_uart1b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2: GPIO: 4,5,6,7 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 5 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2a_tx_sleep>, + <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2a_tx_active>, + <&blsp1_uart2a_rxcts_active>, + <&blsp1_uart2a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2: GPIO: 63,64,65,66 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 64 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>, + <&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2b_tx_active>, + <&blsp1_uart2b_rxcts_active>, + <&blsp1_uart2b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x831000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 26 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, + <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, + <&blsp1_uart3_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4: GPIO: 22,23,48,49 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4a_tx_sleep>, + <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4a_tx_active>, + <&blsp1_uart4a_rxcts_active>, + <&blsp1_uart4a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4: GPIO: 16,17,18,19 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_tx_sleep>, + <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4b_tx_active>, + <&blsp1_uart4b_rxcts_active>, + <&blsp1_uart4b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 771cf1df3a0f..fde920065f0b 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -93,5 +93,908 @@ }; }; }; + + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio84", "gpio85"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio65", "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + blsp1_uart1a: blsp1_uart1a { + blsp1_uart1a_tx_active: blsp1_uart1a_tx_active { + mux { + pins = "gpio0"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active { + mux { + pins = "gpio1", "gpio2"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active { + mux { + pins = "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + + blsp1_uart1b: blsp1_uart1b { + blsp1_uart1b_tx_active: blsp1b_uart1_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_active: blsp1b_uart1_rxcts_active { + mux { + pins = "gpio49", "gpio80"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active { + mux { + pins = "gpio81"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep { + mux { + pins = "gpio49", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_sleep: blsp1b_uart1_rfr_sleep { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2a: blsp1_uart2a { + blsp1_uart2a_tx_active: blsp1_uart2a_tx_active { + mux { + pins = "gpio4"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active { + mux { + pins = "gpio5", "gpio6"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active { + mux { + pins = "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep { + mux { + pins = "gpio5", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2b: blsp1_uart2b { + blsp1_uart2b_tx_active: blsp1_uart2b_tx_active { + mux { + pins = "gpio63"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active { + mux { + pins = "gpio64", "gpio65"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active { + mux { + pins = "gpio66"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + blsp1_uart2b_rx_sleep: blsp1_uart2b_rx_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + blsp1_uart2b_cts_sleep: blsp1_uart2b_cts_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + + blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio8"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio9", "gpio10"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4a: blsp1_uart4a { + blsp1_uart4a_tx_active: blsp1_uart4a_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active { + mux { + pins = "gpio49", "gpio22"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep { + mux { + pins = "gpio49", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4b: blsp1_uart4b { + blsp1_uart4b_tx_active: blsp1_uart4b_tx_active { + mux { + pins = "gpio16"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active { + mux { + pins = "gpio17", "gpio18"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active { + mux { + pins = "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a9a6ec23a414..93f175cfad5c 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -376,7 +376,7 @@ serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; - interrupts = <0 26 0>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -678,3 +678,4 @@ #include "sdxlemur-usb.dtsi" #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" +#include "sdxlemur-blsp.dtsi" From db96ff8891453758c05591c58cba1a7ccca26eaf Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 11:27:03 +0530 Subject: [PATCH 0082/1809] ARM: dts: qcom: enable display on trusted vm for shima Enable display on trusted vm for shima target by including display dt files. Change-Id: I5fd30dd9c84f8f8c640eaa9e2b64039f14811d32 --- qcom/shima-vm.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 03d7359ab920..242012055766 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -1,4 +1,7 @@ #include +#include +#include +#include / { #address-cells = <0x2>; @@ -288,3 +291,5 @@ }; #include "lahaina-vm-ion.dtsi" +#include "display/trustedvm-shima-sde.dtsi" +#include "display/trustedvm-shima-sde-display.dtsi" From 4a7b1c3334439c010cb4e9f91d51b429e7b6b7fe Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Wed, 30 Sep 2020 11:46:08 +0530 Subject: [PATCH 0083/1809] dt-bindings: spi_qsd: Add documentation of SPI BLSP driver This change adds a documentation of SPI BLSP driver from the 4.19 branch. kernel-4.19 baseline: 'commit b159d5da02b7 ("dt-bindings: Add documentation for SDM660")'. Change-Id: I64177a6323a14aad4269f7825a8258b7ab1c4389 --- bindings/spi/spi_qsd.txt | 106 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 bindings/spi/spi_qsd.txt diff --git a/bindings/spi/spi_qsd.txt b/bindings/spi/spi_qsd.txt new file mode 100644 index 000000000000..8d50dbbc7917 --- /dev/null +++ b/bindings/spi/spi_qsd.txt @@ -0,0 +1,106 @@ +Qualcomm Technologies, Inc. Serial Peripheral Interface (SPI) + +Required properties: +- compatible : Should be "qcom,spi-qup-v2". +- reg : Offset and length of the register regions for the device +- reg-names : Register region names referenced in reg above. + Required register resource entries are: + "spi_physical" : Physical address of controller register blocks. +- interrupts : Interrupt numbers used by this controller +- interrupt-names : Interrupt resource names referenced in interrupts above. + Required interrupt resource entries are: + "spi_irq" : QUP-core interrupt. +- spi-max-frequency : Specifies maximum SPI clock frequency, Units - Hz. + +Required alias: +- The desired bus-number is specified via an alias with the following format + 'spi{n}' where n is the bus number. + +Optional properties: +- qcom,gpio-mosi : GPIO pin number of the MOSI bus line. +- qcom,gpio-miso : GPIO pin number of the MISO bus line. +- qcom,gpio-clk : GPIO pin number of the CLK bus line. +- qcom,gpio-cs0 : GPIO pin number of the chipselect0 bus line. +- qcom,gpio-cs1 : GPIO pin number of the chipselect1 bus line. +- qcom,gpio-cs2 : GPIO pin number of the chipselect2 bus line. +- qcom,gpio-cs3 : GPIO pin number of the chipselect3 bus line. +- qcom,infinite-mode: When missing or set to zero, QUP uses infinite-mode. When + value is non-zero, the value is the number of words in maximum transfer + length. + - qcom,active-only : Vote for core clock when the application processor goes + to active state and remove that vote when it goes to idle state. This flag may + improve service time of first spi request at the expense of power consumption. + When this entry is not present, voting is done by the runtime-pm callbacks. + - qcom,master-id : Master endpoint number used for voting on clocks using the + bus-scaling driver. + - qcom,rt-priority : whether spi message queue is set to run as a realtime task. + With this spi transaction message pump with high (realtime) priority to reduce + the transfer latency on the bus by minimising the delay between a transfer request + - qcom,shared : whether this qup is shared with other ee's + +Optional properties which are required for support of BAM-mode: +- qcom,ver-reg-exists : Boolean. When present, allows driver to verify if HW + version support latest features (e.g. BAM) and then enable them. Should be + removed for legacy HW. +- qcom,use-bam : Boolean. When present, enables BAM-mode. +- qcom,use-pinctrl : Boolean. When present, enables pinctrl frame work to configure GPIO's + instead of existing gpio mux hence gpio entries are no more required if present. +- pinctrl-names : Property must contain "spi_default" and "spi_sleep" if + pinctrl is to be used. + instead of existing gpio mux hence gpio entries are no more required if present. +- qcom,bam-consumer-pipe-index : BAM consumer-pipe index. +- qcom,bam-producer-pipe-index : BAM producer-pipe index. +- reg-names : register region names referenced in reg. + Required register resource for BAM are: + "spi_bam_physical" : Physical address of BAM for this controller. +- interrupt-names : interrupt resource names referenced in interrupts. + Required interrupt resource from BAM are: + "spi_bam_irq" : BAM interrupt used by the controller. + +Optional SPI slave nodes must be children of the SPI master node and contain +the following properties. +- reg: (required) chip-select address of the device. +- compatible : (required) Name of SPI device following generic names. +- spi-max-frequency : (required) Maximum SPI clocking speed of device in Hz +- interrupts : (recommended) Should contain the SPI slave interrupt number + encoded depending on the type of the interrupt controller. +- interrupt-parent : (recommended) The phandle for the interrupt controller + that services interrupts for this device. +- spi-cpol : (optional) Empty property indicating device requires inverse + clock polarity (CPOL) mode +- spi-cpha : (optional) Empty property indicating device requires shifted + clock phase (CPHA) mode +- spi-cs-high : (optional) Empty property indicating device requires + chip select active high + +Example: + aliases { + spi0 = &spi_0; + }; + + spi_0: spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9923000 0x1000>, + <0xf9904000 0x10000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + qcom,gpio-mosi = <&msmgpio 0 0>; + qcom,gpio-miso = <&msmgpio 1 0>; + qcom,gpio-clk = <&msmgpio 3 0>; + qcom,gpio-cs2 = <&msmgpio 9 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,ver-reg-exists; + qcom,master-id = <86>; + qcom,rt-priority; + }; From 0562eef50365b70fce1aa3999576a21abcedd1f8 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Tue, 22 Sep 2020 10:50:23 +0530 Subject: [PATCH 0084/1809] ARM: dts: msm: Add psci and scm nodes for Yupik Add scm and psci device nodes for Yupic SoC. Change-Id: Iae18d127d2e01234330f77c52b62a051404fd27b --- qcom/yupik.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b63c9164c569..6fed717806ee 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -23,6 +23,12 @@ aliases { }; + firmware: firmware { + scm { + compatible = "qcom,scm"; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -207,6 +213,11 @@ interrupts = ; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; From 02ea70bb21f8e17b314f456640dacadbcf1b1ce0 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 30 Sep 2020 12:58:31 +0800 Subject: [PATCH 0085/1809] ARM: dts: msm: Add wireless-fw-name property for Shima platforms Add qcom,wireless-fw-name property for Shima platforms to upgrade wireless charger chip firmware correctly. Change-Id: I761592f9c9e53e7b7b1e351d81a8d4be27baa875 --- qcom/shima-idp.dtsi | 1 + qcom/shima-qrd.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index d0a694ca961b..2b369e508e07 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -150,6 +150,7 @@ &battery_charger { qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; }; &qupv3_se10_i2c { diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..d3f8f9815750 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -190,6 +190,7 @@ 7500000 7000000 6500000 6000000 5500000 5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; }; &qupv3_se10_i2c { From 0ca570d4870e42ea11d4f584792e3fc152d7091a Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Thu, 24 Sep 2020 12:29:13 -0700 Subject: [PATCH 0086/1809] ARM: dts: msm: Vote for DDR BW for MPSS PIL on Lahaina It is possible that the DDR bandwidth requirements are not met during modem SSR. Hence, explicitly vote for DDR turbo frequency during modem PIL. Change-Id: I5134feaf593673beb8bbdafc416814a5d41fb47b --- qcom/lahaina.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 2f48611e3666..c95a6dfe9c44 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4425,6 +4425,8 @@ qcom,vdd_mss-uV-uA = ; qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; From 12f00961f388955b99f68e4de1e2ba7dff257fc8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 24 Sep 2020 17:12:58 +0530 Subject: [PATCH 0087/1809] ARM: dts: msm: Select 120Hz panel as default on 120Hz shima dts This change adds support to select 120Hz command mode panel as default panel on shima 120Hz IDP/IDPS platform. Change-Id: I2ca4fb9f181ad3b721ce05a4740cf18f4127bddc --- qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps.dtsi | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi index 4f6732d3b955..f110f793bbeb 100644 --- a/qcom/shima-idp-120fps.dtsi +++ b/qcom/shima-idp-120fps.dtsi @@ -2,3 +2,7 @@ &soc { }; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi index 51ccf2dd48fd..976bee956cd7 100644 --- a/qcom/shima-idps-digital-mics-120fps.dtsi +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -3,4 +3,6 @@ &soc { }; - +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From ec587be585ef895079a86eeed7580ee2711e39b3 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 1 Oct 2020 11:19:31 -0700 Subject: [PATCH 0088/1809] ARM: dts: msm: Update modem mitigation threshold for lahaina Update modem mitigation threshold and hysteresis for lahaina as per recommendation. sensor mdmss-1-step/mdmss-2-step algo_type step_wise polling_delay 0 passive_delay 0 trip 0 2 set_temp 95000 98000 105000 clr_temp 3000 2000 5000 device modem_tj modem_tj modem_tj upper_limit 1 2 3 lower_limit 1 2 3 Above is the new updated configuration. Change-Id: I6eddbe2ab29fb9942cdd608b1bd507fd9aa1c910 --- qcom/lahaina-thermal-modem.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/lahaina-thermal-modem.dtsi b/qcom/lahaina-thermal-modem.dtsi index 35b1ab87bc54..c13e66fa1abb 100644 --- a/qcom/lahaina-thermal-modem.dtsi +++ b/qcom/lahaina-thermal-modem.dtsi @@ -465,13 +465,13 @@ trips { mdmss10_config: active-config0 { temperature = <95000>; - hysteresis = <5000>; + hysteresis = <3000>; type = "passive"; }; mdmss11_config: active-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <98000>; + hysteresis = <2000>; type = "passive"; }; @@ -508,13 +508,13 @@ trips { mdmss20_config: active-config0 { temperature = <95000>; - hysteresis = <5000>; + hysteresis = <3000>; type = "passive"; }; mdmss21_config: active-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <98000>; + hysteresis = <2000>; type = "passive"; }; From d0326a2063dac14bd2502b5c98ede67635da6d4b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 14:46:57 +0530 Subject: [PATCH 0089/1809] ARM: dts: msm: update modem qmi sennor list for SHIMA Update modem qmi sensor list for SHIMA. Add msm_skin_therm sensor and remove sys_therm2,sdr_mmw_therm in qmi_sensor list for SHIMA. Change-Id: Ia788efd2289cd485210e92e395f29aba14485046 --- qcom/shima-thermal.dtsi | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 400c81e2b65a..fc97b1dddafa 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -2,6 +2,23 @@ #include "lahaina-thermal-modem.dtsi" &qmi_tmd { + modem { + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; + #cooling-cells = <2>; + }; + + modem_wlan_bw: modem_wlan_bw { + qcom,qmi-dev-name = "wlan_bw"; + #cooling-cells = <2>; + }; + }; + cdsp { qcom,instance-id = ; @@ -17,6 +34,38 @@ }; }; +&soc { + qmi-ts-sensors { + modem { + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_wtr0", + "modem_tsens", + "qfe_mmw0", + "qfe_mmw1", + "qfe_mmw2", + "qfe_mmw3", + "xo_therm", + "qfe_mmw_streamer0", + "qfe_mmw0_mod", + "qfe_mmw1_mod", + "qfe_mmw2_mod", + "qfe_mmw3_mod", + "qfe_ret_pa0", + "qfe_wtr_pa0", + "qfe_wtr_pa1", + "qfe_wtr_pa2", + "qfe_wtr_pa3", + "sys_therm1", + "modem_tsens1", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", + "msm_skin_therm"; + }; + }; +}; + &cpufreq_hw { qcom,cpu-isolation { compatible = "qcom,cpu-isolate"; @@ -75,6 +124,24 @@ }; &thermal_zones { + /delete-node/ modem-sdr-mmw-usr; + /delete-node/ modem-ambient-usr; + + msm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MSM_SKIN)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; From 8c4d819e50522b88094e229186f4d9002e1efb86 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 15:01:01 +0530 Subject: [PATCH 0090/1809] dt-bindings: thermal: Add support for bandwidth cooling devices Add support for modem_bw_backoff and wlan_bw cooling devices. Change-Id: I71fd52e7e1e26ab5b9c8ab7e10ca3da3f14734e1 --- bindings/thermal/qti-qmi-cdev.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/thermal/qti-qmi-cdev.txt b/bindings/thermal/qti-qmi-cdev.txt index 127a9d8caecf..d22547641936 100644 --- a/bindings/thermal/qti-qmi-cdev.txt +++ b/bindings/thermal/qti-qmi-cdev.txt @@ -41,6 +41,9 @@ Subsystem properties: "modem" -> for processor passive cooling device, "modem_current" -> for current limiting device, "modem_bw" -> for bus bandwidth limiting device, + "modem_bw_backoff" -> for bus bandwidth limit device with + absolute bandwidth reduction from max bandwidth + in 100mbbs resolution, "vbatt_low" -> BCL vbat mitigation device, "mmw0" -> Millimeter wave limiting device 0, "mmw1" -> Millimeter wave limiting device 1, @@ -53,6 +56,7 @@ Subsystem properties: "mmw_skin3" -> MMW skin mitigation device3, "cpr_cold" -> for cpr restriction, "wlan" -> for modem wlan mitigation device, + "wlan_bw" -> for bus bandwidth limiting device, "cdsp_sw" -> for CDSP DCVS mitigation device, "cdsp_hw" -> for CDSP hardware mitigation device, "mmw_skin0_dsc" -> DSC based MMW skin mitigation From adbcb4d69ee738e2699d9287bef8dea4d956a974 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 15:10:13 +0530 Subject: [PATCH 0091/1809] dt-bindings: thermal: Add support for modem skin sensor via QMI Add support to expose msm_skin_therm sensor via QMI. Change-Id: I3ee24239314fb25d19267b4199fa2c137a51ffb7 --- bindings/thermal/qti-qmi-sensor.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index 5c8f0bfc7e80..b9a703cf1a14 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -61,6 +61,7 @@ Subsystem properties: 28. mmw_pa2 29. mmw_pa3 30. sdr_mmw_therm + 31. msm_skin_therm Example: From 4d515a168df4dbbe20715782c6e1fc75bf37da6a Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Fri, 25 Sep 2020 22:26:57 -0700 Subject: [PATCH 0092/1809] ARM: dts: msm: Update CNSS node for BT GPIO config QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: I0cd7050dad499378ec6d2bcfbe9d78f4a79a3384 --- bindings/cnss/cnss-wlan.txt | 3 +++ qcom/lahaina.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 02d983d74138..c1de42da51fb 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -87,6 +87,9 @@ Optional properties: regulator used in internal power amplifier for QCA6490 - cnss-enable-self-recovery: Boolean property to enable self recovery when recovery is trigeered with reason link down. + - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO + enable to resolve PMU power up issues. Provide BT GPIO using + this config param. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 182e5335c125..adae4ce8f80d 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5352,6 +5352,7 @@ <0xb2e5510 0x690>; reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; + qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From 4bd7a12e8e0bfda12dbaf88b1aff1bf8f2d93a38 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Wed, 30 Sep 2020 17:43:03 +0530 Subject: [PATCH 0093/1809] ARM: dts: msm: Add debugcc and APSSCC clock nodes for sdxlemur Add debug clock controller node to use the debug clock controller driver for measuring the clocks, also add MCCC and CPUCC device phandle reference to debugcc node to map register space for the apcs diag register. Update apsscc clock node to enable cpu driver for sdxlemur. Change-Id: Iba7b60463462ab8e121b6a72323f1d9a116fe411 --- qcom/sdxlemur.dtsi | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..e0304362d09d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -373,6 +374,26 @@ #reset-cells = <1>; }; + clock_apsscc: syscon@17811000 { + compatible = "syscon"; + reg = <0x17811000 0x20>; + }; + + clock_mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,sdxlemur-debugcc"; + qcom,gcc = <&gcc>; + qcom,apsscc = <&clock_apsscc>; + qcom,mccc = <&clock_mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; @@ -403,10 +424,20 @@ status = "disabled"; }; - apsscc: clock-controller@17808000 { - compatible = "qcom,dummycc"; - clock-output-names = "apsscc_clocks"; - #clock-cells = <1>; + apsscc: clock-controller@17808100 { + compatible = "qcom,sdxlemur-apsscc"; + clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>; + clock-names = "bi_tcxo_ao", "gpll0_out_even"; + reg = <0x17810008 0x16>, + <0x17808100 0x100>; + reg-names = "apcs_cmd", "apcs_pll"; + vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>; + cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; + qcom,speed0-bin-v0 = + < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + < 576000000 RPMH_REGULATOR_LEVEL_SVS>, + < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, + < 1497600000 RPMH_REGULATOR_LEVEL_TURBO>; #reset-cells = <1>; }; From 1821f82015638579535f5ad297e6de3c02e66551 Mon Sep 17 00:00:00 2001 From: Mahesh Kumar Sharma Date: Thu, 24 Sep 2020 15:13:50 -0700 Subject: [PATCH 0094/1809] ARM: dts: msm: add WL_EN entry in BT node Add WL_EN GPIO entry in BT device tree node to handle AON LDO fully discharge issue. Change-Id: I526d42fb58fef7942280c4fc06ded5a47f7277dd --- bindings/bluetooth/btpower.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 8b7d10bda475..391361eef201 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -11,6 +11,7 @@ Required properties: qcom,qca6390 qcom,qca6490 - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset + - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle Optional properties: - qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle @@ -38,6 +39,7 @@ Example: pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-aon-supply = <&pm8150_s6>; qcom,bt-vdd-dig-supply = <&pm8009_s2>; qcom,bt-vdd-rfa1-supply = <&pm8150_s5>; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 182e5335c125..fcf628bce58b 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5615,6 +5615,7 @@ /* offset=(0xC8*6) + (0x10*2) */ qcom,tcs_offset_ipa = <0x4D0>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */ qcom,bt-vdd-aon-supply = <&S11B>; qcom,bt-vdd-dig-supply = <&S11B>; From 830398b379d8efe26ad233746ae832fb553081b8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 5 Oct 2020 13:10:23 +0530 Subject: [PATCH 0095/1809] ARM: dts: msm: Add focaltech touch support on holi cdp This change adds focaltech touch support on holi cdp which is needed for 120Hz video and command mode panels. Change-Id: I03cb8927faeec77cf0af9268d3000f5b3ff75fc3 --- qcom/holi-cdp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 5aba97afae07..7cbc0ae32d3c 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -232,6 +232,27 @@ panel = <&dsi_rm69299_visionox_amoled_video &dsi_rm69299_visionox_amoled_cmd>; }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L6A>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; }; #include "camera/holi-camera-sensor-cdp.dtsi" From fc3b5de115288ee4a86a41e09f9abcbd1ed7631d Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 2 Oct 2020 01:13:41 +0530 Subject: [PATCH 0096/1809] ARM: dts: msm: remove cpu7 llcc-ddr lat device node Remove cpu7 llcc-ddr lat device node which is similar to latfloor defined already. Change-Id: I7b1102b1e739b9f5325a561e0e122ae2a30f88f8 --- qcom/shima.dtsi | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..14911740621e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2596,7 +2596,7 @@ cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { @@ -2623,26 +2623,6 @@ }; }; - cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu4_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - ddr4-map { - qcom,ddr-type = ; - qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(2133, 4) >; - }; - - ddr5-map { - qcom,ddr-type = ; - qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(3196, 4) >; - }; - }; - cpu4_computemon: qcom,cpu4-computemon { compatible = "qcom,arm-compute-mon"; qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; From b7b2a7094851f6c484b8f5b24beab57b058c6a92 Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Mon, 5 Oct 2020 21:06:06 +0300 Subject: [PATCH 0097/1809] ARM: dts: msm: Add ipa_hw support for SDXLEMUR Add gsi and ipa_hw support to SDXLEMUR device tree. Change-Id: I763072bebe62be18a70ea92118596d5d59cf6261 --- qcom/sdxlemur.dtsi | 126 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..dab380a836bb 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -665,6 +665,132 @@ compatible = "qcom,secure-buffer"; }; + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + }; + + ipa_hw: qcom,ipa@03e00000 { + compatible = "qcom,ipa"; + mboxes = <&qmp_aop 0>; + reg = + <0x3e00000 0x84000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-base", "gsi-base"; + qcom,ipa-cfg-offset = <0x0140000>; + interrupts = + <0 241 IRQ_TYPE_LEVEL_HIGH>, + <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <21>; /* IPA core version = IPAv5.0 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <0>; /* MDM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ + qcom,modem-cfg-emb-pipe-flt; + qcom,use-xbl-boot; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,ipa-wdi3-over-gsi; + qcom,lan-rx-napi; + qcom,wan-use-skb-page; + qcom,tx-wrapper-cache-max-size = <400>; + qcom,ipa-gpi-event-rp-ddr; + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <4>; + interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&system_noc MASTER_IPA &system_noc SLAVE_IMEM>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; + + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <150000 600000 150000 1804000 75000 300000 0 76800>; + + /* SVS */ + qcom,svs = + <625000 1200000 625000 3072000 312500 700000 0 150000>; + + /* NOMINAL */ + qcom,nominal = + <1250000 2400000 1250000 6220800 625000 1500000 0 400000>; + + /* TURBO */ + qcom,turbo = + <2000000 3500000 2000000 7219200 1000000 1920000 0 400000>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x5E0 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x14688000 0x14688000 0x3000>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + qcom,ipa-q6-smem-size = <36864>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x5E1 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x5E2 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_11ad: ipa_smmu_11ad { + compatible = "qcom,ipa-smmu-11ad-cb"; + iommus = <&apps_smmu 0x5E3 0x0>; + dma-coherent; + qcom,shared-cb; + qcom,iommu-group = <>; + }; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, From 18fa948509f843ee7fafe8058100e3f41f9f4218 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 25 Sep 2020 21:59:43 +0530 Subject: [PATCH 0098/1809] ARM: dts: msm: Add handles for USB3 interface clocks USB3 AXI cocks need to be enabled for QoS settings programming, so add USB3 AXI clock handles. Change-Id: I4ae6c49a8fc8859345bae24f00eeb0a2b0301288 --- qcom/holi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..bd7dd2432165 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1033,7 +1033,9 @@ qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; + <&rpmcc RPM_SMD_SNOC_A_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; }; config_noc: interconnect@1900000 { From a8f227ac88fc6cde317c904295775de92d19711d Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Tue, 29 Sep 2020 17:00:18 +0530 Subject: [PATCH 0099/1809] ARM: dts: msm: Add touch support for Command Mode on holi Add Synaptics dsx touch support for qsync fhd command mode panel on holi cdp. Change-Id: If44229045eb4d81d8bd22e40ab80bd95dafe337f --- qcom/holi-cdp-lcd.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 057607ce47a3..064ec76ea645 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -47,6 +47,8 @@ synaptics,reset-on-state = <0>; synaptics,reset-active-ms = <20>; - panel = <&dsi_sharp_qsync_fhd_video>; + panel = <&dsi_sharp_qsync_fhd_video + &dsi_sharp_qsync_fhd_cmd + &dsi_sharp_qsync_fhd_60hz_cmd>; }; }; From 8bfb55bada068d97584c93ed9a95322f0df9720a Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Mon, 28 Sep 2020 16:47:06 +0530 Subject: [PATCH 0100/1809] ARM: dts: msm: Add new DT entry for wan agg pkt size Add new DT entry for wan agg pkt size. Change-Id: I492d8f770df5c5b5d8aef2c27e31e526bbf666f1 --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..ca7fbbd667ae 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3725,6 +3725,8 @@ qcom,ipa-holb-monitor-max-cnt-usb = <10>; qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; + /* Entry will be removed once shadow stack changes checked-in */ + qcom,ipa-wan-aggr-pkt-cnt = <2>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From 1861fc66f09cbf6d0854ecee732f6b4d84db069a Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Fri, 18 Sep 2020 13:30:46 -0700 Subject: [PATCH 0101/1809] ARM: dts: qcom: add physical addr for swr tx slaves Add dt property to read physical addresses of TX soundwire master slaves. Change-Id: Id37178b6a919d0cb00d56e8639110199d3593bc2 --- qcom/lahaina-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index fe10fbdf88e0..4908e26696d8 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -72,6 +72,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <5>; + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; wcd938x_tx_slave: wcd938x-tx-slave { From 33a634427c19ed23361a2b7e3c476b45073abc39 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Wed, 7 Oct 2020 10:04:35 +0530 Subject: [PATCH 0102/1809] ARM: dts: msm: Enable qcom,vmid-cp-camera-preview-ro on Shima The secure camera preview pipeline on Shima has buffers that are shared by the display and secure camera hardware. On older architecture, the buffers were not shareable, as the display hardware needed write-access to the buffer, which could compromise the integrity of the data populated by the secure camera hardware. The display hardware on Shima has been upgraded, such that it no longer needs write-access to the buffer, which allows the buffer to be shared between both peripherals. Thus, ensure that the mappings for the display hardware on Shima are read-only, so that the integrity of the contents of the buffer cannot be compromised. Change-Id: I8c254262b53051f4f2bb9cb477ad70bba2d8ed20 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..ad3ab7adbb47 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -779,6 +779,7 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; }; qcom-mem-buf { From d1b9ca00cc22ece8d077630c2fa6d9a7ebf2914f Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Mon, 28 Sep 2020 12:28:47 +0530 Subject: [PATCH 0103/1809] ARM: dts: msm: Add IMEM entry for Yupik Add entry for system IMEM to read or write various system level configurations. Change-Id: I3e412851c4e86483c6c1968e2463fe6710cd53eb --- qcom/yupik.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1d399e531df..0e497e60369b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -401,6 +401,54 @@ }; }; + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From a6f736aacaf61ce835076b8668b3a17623c23a6b Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 7 Oct 2020 10:37:56 +0530 Subject: [PATCH 0104/1809] ARM: dts: msm: Enable smcinvoke and shmbridge on shima Add the device tree entries for smcinvoke and shmbridge on shima vm. Change-Id: Ied6246edcdd957e18678e18c375fa11ccf4ca135 --- qcom/shima-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 242012055766..f2651706963a 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -228,6 +228,15 @@ ; }; + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,support-hypervisor; + }; + /* * QUPv3 Instances * Qup0 2: SE 10 From 4fc6531b64650815177f88f5db17ba14011499c2 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 10 Sep 2020 12:50:29 +0530 Subject: [PATCH 0105/1809] ARM: dts: msm: Change to auto-specific config for SA8155 Change to auto-specific config for SA8155. Change-Id: Ia13ef5ac78757a3548f7b02493d067685c1e824d --- qcom/Makefile | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..778cf0fcf1d6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -132,12 +132,12 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) - dtbo-$(CONFIG_ARCH_SM8150) += \ - sm8150-cdp-overlay.dtbo \ - sa8155-adp-star-overlay.dtbo \ - sa8155p-adp-star-overlay.dtbo \ - sa8155-v2-adp-air-overlay.dtbo \ - sa8155p-v2-adp-air-overlay.dtbo + dtbo-$(CONFIG_ARCH_SA8155) += \ + sm8150-cdp-overlay.dtbo \ + sa8155-adp-star-overlay.dtbo \ + sa8155p-adp-star-overlay.dtbo \ + sa8155-v2-adp-air-overlay.dtbo \ + sa8155p-v2-adp-air-overlay.dtbo sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb @@ -145,13 +145,13 @@ sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else -dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \ - sa8155-adp-star.dtb \ - sa8155p-adp-star.dtb \ - sa8155-v2-adp-star.dtb \ - sa8155p-v2-adp-star.dtb \ - sa8155-v2-adp-air.dtb \ - sa8155p-v2-adp-air.dtb +dtb-$(CONFIG_ARCH_SA8155) += sm8150-cdp.dtb \ + sa8155-adp-star.dtb \ + sa8155p-adp-star.dtb \ + sa8155-v2-adp-star.dtb \ + sa8155p-v2-adp-star.dtb \ + sa8155-v2-adp-air.dtb \ + sa8155p-v2-adp-air.dtb endif endif From 96512cbc99755d07b8556f2ea82c3b52ec64d245 Mon Sep 17 00:00:00 2001 From: yuleiy Date: Fri, 25 Sep 2020 11:40:36 +0800 Subject: [PATCH 0106/1809] ARM: dts: qcom: Change L4P's max output voltage Change L4P's max output voltage from 2800000 to 2880000 to match holi QRD rear camera0's AVDD requirement. CRs-Fixed: 2792547 External Impact: No. Change-Id: Id9a65b541e7c3d391ff82d25dde73151cb297e24 --- qcom/holi-pmic-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 7935292f7f9c..2cc337167393 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -482,7 +482,7 @@ reg = <0x4300>; regulator-name = "pm8008_l4"; regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; + regulator-max-microvolt = <2880000>; qcom,min-dropout-voltage = <160000>; qcom,hpm-min-load = <10000>; }; From 62b18b73ea7674be94ca8253acf09b15d8b36e00 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 24 Sep 2020 23:15:31 +0530 Subject: [PATCH 0107/1809] ARM: dts: msm: Enable smmu for shima ufs Enable smmu for shima ufs. Change-Id: Ib642a274cb1c285aa58a464a3de649a5510e8992 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..6fdf629dc43a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1711,7 +1711,7 @@ reset-names = "rst"; iommus = <&apps_smmu 0x80 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; dma-coherent; rpm-level = <3>; From 947798dfdc4b199294ace780a6d0820dac30c784 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 5 Oct 2020 10:13:52 -0700 Subject: [PATCH 0108/1809] ARM: dts: msm: Add board device-tree files for SDXLEMUR target Add devicetree files for various boards available on SDXLEMUR target. Change-Id: Iacd1cbd4260e978387101f95954776fab7e3f042 --- bindings/arm/msm/msm.txt | 1 + qcom/Makefile | 11 ++++++++++- qcom/sdxlemur-mtp-cpe.dts | 11 +++++++++++ qcom/sdxlemur-mtp-cpe.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 5 +++++ qcom/sdxlemur-rcm-pcie-ep.dts | 11 +++++++++++ qcom/sdxlemur-rcm-pcie-ep.dtsi | 5 +++++ qcom/sdxlemur-rcm-rc.dts | 11 +++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 5 +++++ 16 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-mtp-cpe.dts create mode 100644 qcom/sdxlemur-mtp-cpe.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts create mode 100644 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep.dts create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb.dts create mode 100644 qcom/sdxlemur-mtp-mbb.dtsi create mode 100644 qcom/sdxlemur-rcm-pcie-ep.dts create mode 100644 qcom/sdxlemur-rcm-pcie-ep.dtsi create mode 100644 qcom/sdxlemur-rcm-rc.dts create mode 100644 qcom/sdxlemur-rcm-rc.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 93709ab8e29b..16b9fbede6b4 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -235,6 +235,7 @@ compatible = "qcom,sdxprairie-cdp" compatible = "qcom,sdxlemur-rumi" compatible = "qcom,sdxlemur-mtp" compatible = "qcom,sdxlemur-cdp" +compatible = "qcom,sdxlemur-rcm" compatible = "qcom,sdmmagpie-rumi" compatible = "qcom,sdmmagpie-idp" compatible = "qcom,sdmmagpie-qrd" diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..0655369c6682 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -165,7 +165,16 @@ endif dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-cdp.dtb \ - sdxlemur-mtp.dtb + sdxlemur-mtp.dtb \ + sdxlemur-mtp-mbb.dtb \ + sdxlemur-mtp-cpe.dtb \ + sdxlemur-mtp-mbb-ntn3-pcie.dtb \ + sdxlemur-mtp-mbb-pcie-ep.dtb \ + sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ + sdxlemur-mtp-mbb.dtb \ + sdxlemur-rcm-pcie-ep.dtb \ + sdxlemur-rcm-rc.dtb + ifeq ($(CONFIG_ARCH_SHIMA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts new file mode 100644 index 000000000000..696b1ab58713 --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x6010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts new file mode 100644 index 000000000000..ead998c52e3c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x5010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts new file mode 100644 index 000000000000..615f5c59659c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x4010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts new file mode 100644 index 000000000000..c849ed133087 --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x3010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts new file mode 100644 index 000000000000..117c1bb3719b --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts new file mode 100644 index 000000000000..11a14dc88bef --- /dev/null +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-pcie-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x1010015 0>; +}; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts new file mode 100644 index 000000000000..f061c22ed532 --- /dev/null +++ b/qcom/sdxlemur-rcm-rc.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-rc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x1010015 0>; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + From 4ed98c6d4ca06c06f4540c4f4239aff1ca1c0120 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Wed, 16 Sep 2020 01:54:42 +0530 Subject: [PATCH 0109/1809] ARM: dts: msm: Add ufs dt node for yupik Add ufs dt node support for yupik. Change-Id: I4585ba80587f7c3e668621d98e4603008dd17f0c --- qcom/yupik-rumi.dtsi | 34 +++++++++++ qcom/yupik.dtsi | 140 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 173 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 0987448b8be5..3d00135b89f8 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -11,3 +11,37 @@ status = "disabled"; }; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97100>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1d399e531df..6d02b2177e66 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Yupik"; @@ -21,7 +22,9 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; - aliases { }; + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + }; cpus { #address-cells = <2>; @@ -503,6 +506,141 @@ #reset-cells = <1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + rpm-level = <3>; + spm-level = <3>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <59>; + }; + + qos1 { + mask = <0x0f>; + vote = <65>; + }; + }; + clk_virt: interconnect { compatible = "qcom,yupik-clk_virt"; #interconnect-cells = <1>; From f0104dcca4c819fdaee6161bfa1d767328f8d123 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 29 Sep 2020 13:36:41 -0700 Subject: [PATCH 0110/1809] ARM: dts: msm: Added pil nodes for sdxlemur Added entries for pil modem nodes on sdxlemur. Change-Id: I9d211a0b0b6d319066bcef5b567ef4122b6c7712 --- qcom/sdxlemur.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..806d7a85c6c8 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -386,6 +387,47 @@ status = "ok"; }; + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MSS_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&mpss_adsp_mem>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x22>; + + interrupts-extended = <&intc 0 250 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + status = "ok"; + }; + qnand_1: nand@1b00000 { compatible = "qcom,msm-nand"; reg = <0x01b00000 0x1000>, From 9236449ef7061dbc0816dda77ada3ec2daf286e6 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Oct 2020 10:18:30 +0530 Subject: [PATCH 0111/1809] bindings: leds: vibrator: Move vibrator LDO documentation to correct folder Move vibrator LDO documentation to bindings folder. Change-Id: I81f873ede92e25797f0f7a1d7aa40c2af382e1c9 --- {qcom => bindings/leds}/leds-qpnp-vibrator-ldo.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {qcom => bindings/leds}/leds-qpnp-vibrator-ldo.txt (100%) diff --git a/qcom/leds-qpnp-vibrator-ldo.txt b/bindings/leds/leds-qpnp-vibrator-ldo.txt similarity index 100% rename from qcom/leds-qpnp-vibrator-ldo.txt rename to bindings/leds/leds-qpnp-vibrator-ldo.txt From 2ae24ea0e9af2a9bce545b381ccce04236f59a4a Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 8 Oct 2020 15:10:54 +0530 Subject: [PATCH 0112/1809] ARM: dts: msm: Add Bus voting support Add bus voting support for sdxlemur nand node. Change-Id: I2fc4e0aab98125353f49855fab9fffa7a014bae5 --- qcom/sdxlemur.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index dab380a836bb..1b50a41d8d5d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -400,6 +400,16 @@ clock-names = "core_clk"; clocks = <&rpmhcc RPMH_QPIC_CLK>; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 400000>; + status = "disabled"; }; From 6a4ddcf7bb9bb6eb625b4ea2ff2a4d769d120e38 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 7 Oct 2020 15:43:11 +0530 Subject: [PATCH 0113/1809] ARM: dts: msm: Remove bi_tcxo_ao clock and vdd_cx_ao handles from GCC Remove bi_tcxo_ao clock handle and vdd_cx_ao handle from GCC node as they are currently unused. Change-Id: I5b444e7dc2260d269f08fdbe6a85c319e5e5e60c --- qcom/shima.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..19c14121de92 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -929,10 +929,8 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; From 81f0e49d1fee1cdc0468c8de28b2caa7a3a3c783 Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Thu, 8 Oct 2020 19:05:59 +0300 Subject: [PATCH 0114/1809] ARM: dts: msm: Disable fastmap for IPA CBs on SDXLEMUR The WLAN CB and UC CB SMMUs on the sdxlemur intended to be atomic. Change-Id: If74e9021719086c27eb313017368e427a3b3f330 --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index dab380a836bb..06dcaf8c5ba6 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -759,14 +759,14 @@ compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x5E1 0x0>; dma-coherent; - qcom,iommu-dma = "fastmap"; + qcom,iommu-dma = "atomic"; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x5E2 0x0>; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; - qcom,iommu-dma = "fastmap"; + qcom,iommu-dma = "atomic"; }; ipa_smmu_11ad: ipa_smmu_11ad { From 012012e3f2c40c0857d91819714a76bb1045cedf Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Thu, 8 Oct 2020 22:20:50 +0530 Subject: [PATCH 0115/1809] ARM: dts: msm: update sound card name for holi usbc variant update sound card name for usbc variant. Change-Id: I776830ca6f369e710b1bb8b3e237012e1db7454e --- qcom/holi-mtp-usbc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index fddd4d338dda..8e7a4528580b 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -95,7 +95,7 @@ }; &holi_snd { - qcom,model = "holi-mtp-usbc-snd-card"; + qcom,model = "holi-usbc-snd-card"; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; From e3cf6147147f504395795cb1870198f457443850 Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Thu, 8 Oct 2020 22:32:08 +0530 Subject: [PATCH 0116/1809] bindings: Documentation: add SDK audio properties Add audio documentation for SDX target. Change-Id: I49da28bfa0dacb3cde4fdf68b58528d3da8bdec8 --- bindings/sound/qcom-audio-dev.txt | 89 +++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index be5d91b5c748..1c9bc157da29 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -2398,3 +2398,92 @@ Example: }; }; +Required properties: +- compatible : "qcom,spf-core-platform" + +Required properties: +- compatible : "qcom,audio-pkt-core-platform" + +Required properties: +- compatible : "qcom,swr-wcd" + +Required properties: +- compatible : "qcom,tavil-i2c" + +Required properties: +- compatible : "qcom,wcd-pinctrl" + +Required properties: +- compatible : "qcom,gpr" + +Required properties: +- compatible : "qcom,spf_core" + +Required properties: +- compatible : "qcom,audio-pkt" + +Required properties: +- compatible : "qcom,audio_prm" + + + +* SDX ASoC Machine driver + +Required properties: +- compatible : "qcom,sdx-asoc-snd-tavil" +- qcom,model : The user-visible name of this sound card. +- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations +- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations +- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations +- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order give + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +Example: + + sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_sec_auxpcm>, <&incall2_record_rx>, + <&incall_music_2_rx>, <&incall_music_dl_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; + }; From 23c3661bdced1ce38ff9c3e2813e5efb1125db69 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 7 Oct 2020 13:35:30 +0530 Subject: [PATCH 0117/1809] ARM: dts: msm: Remove CDP DT for SA8155 Auto targets do not use CDP boards. Remove CDP device tree for ARCH_SA8155. Change-Id: Ia5495f62770b5f81fb30de0993dbca66d1b897e7 --- qcom/Makefile | 5 +---- qcom/sm8150-cdp-overlay.dts | 14 -------------- qcom/sm8150-cdp.dts | 10 ---------- qcom/sm8150-cdp.dtsi | 2 -- 4 files changed, 1 insertion(+), 30 deletions(-) delete mode 100644 qcom/sm8150-cdp-overlay.dts delete mode 100644 qcom/sm8150-cdp.dts delete mode 100644 qcom/sm8150-cdp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 778cf0fcf1d6..572f4f02fb0c 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -133,20 +133,17 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SA8155) += \ - sm8150-cdp-overlay.dtbo \ sa8155-adp-star-overlay.dtbo \ sa8155p-adp-star-overlay.dtbo \ sa8155-v2-adp-air-overlay.dtbo \ sa8155p-v2-adp-air-overlay.dtbo -sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else -dtb-$(CONFIG_ARCH_SA8155) += sm8150-cdp.dtb \ - sa8155-adp-star.dtb \ +dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155p-adp-star.dtb \ sa8155-v2-adp-star.dtb \ sa8155p-v2-adp-star.dtb \ diff --git a/qcom/sm8150-cdp-overlay.dts b/qcom/sm8150-cdp-overlay.dts deleted file mode 100644 index c4665280aa59..000000000000 --- a/qcom/sm8150-cdp-overlay.dts +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -#include "sm8150-cdp.dtsi" - -/ { - model = "CDP"; - compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; - qcom,board-id = <1 0>; -}; diff --git a/qcom/sm8150-cdp.dts b/qcom/sm8150-cdp.dts deleted file mode 100644 index ece66075cd39..000000000000 --- a/qcom/sm8150-cdp.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "sm8150.dtsi" -#include "sm8150-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8150 CDP"; - compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; - qcom,board-id = <1 0>; -}; diff --git a/qcom/sm8150-cdp.dtsi b/qcom/sm8150-cdp.dtsi deleted file mode 100644 index 44b2ac0d79b8..000000000000 --- a/qcom/sm8150-cdp.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include From e7746b39c973c36816b66d30b9dc4fd3f695048c Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 1 Jul 2020 13:40:53 +0530 Subject: [PATCH 0118/1809] ARM: dts: msm: Add initial device tree for SA8195 Add initial device tree to support SA8195 chipset on automotive platforms. Change-Id: I30e73ea78334bbe7cd247a8f3fa556e44a722606 --- bindings/arm/msm/msm.txt | 3 + qcom/Makefile | 12 + qcom/sa8195p-adp-common.dtsi | 5 + qcom/sa8195p-adp-star-overlay.dts | 12 + qcom/sa8195p-adp-star.dts | 11 + qcom/sa8195p-adp-star.dtsi | 1 + qcom/sa8195p-v2-adp-air-overlay.dts | 13 + qcom/sa8195p-v2-adp-air.dts | 10 + qcom/sa8195p-v2-adp-air.dtsi | 1 + qcom/sa8195p.dts | 10 + qcom/sa8195p.dtsi | 8 + qcom/sdmshrike-v2.dts | 10 + qcom/sdmshrike-v2.dtsi | 8 + qcom/sdmshrike.dts | 10 + qcom/sdmshrike.dtsi | 655 ++++++++++++++++++++++++++++ 15 files changed, 769 insertions(+) create mode 100644 qcom/sa8195p-adp-common.dtsi create mode 100644 qcom/sa8195p-adp-star-overlay.dts create mode 100644 qcom/sa8195p-adp-star.dts create mode 100644 qcom/sa8195p-adp-star.dtsi create mode 100644 qcom/sa8195p-v2-adp-air-overlay.dts create mode 100644 qcom/sa8195p-v2-adp-air.dts create mode 100644 qcom/sa8195p-v2-adp-air.dtsi create mode 100644 qcom/sa8195p.dts create mode 100644 qcom/sa8195p.dtsi create mode 100644 qcom/sdmshrike-v2.dts create mode 100644 qcom/sdmshrike-v2.dtsi create mode 100644 qcom/sdmshrike.dts create mode 100644 qcom/sdmshrike.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 93709ab8e29b..259059b7f344 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -189,6 +189,9 @@ compatible = "qcom,sa8155p-adp-star" compatible = "qcom,sa8155-adp-air" compatible = "qcom,sa8155-v2-adp-air" compatible = "qcom,sa8155p-v2-adp-air" +compatible = "qcom,sa8195p-adp-star" +compatible = "qcom,sa8195p-v2-adp-air" +compatible = "qcom,sa8195p" compatible = "qcom,adp-air" compatible = "qcom,kona-rumi" compatible = "qcom,kona-mtp" diff --git a/qcom/Makefile b/qcom/Makefile index 572f4f02fb0c..02eb8a08e588 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -150,6 +150,18 @@ dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155-v2-adp-air.dtb \ sa8155p-v2-adp-air.dtb endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SA8195) += \ + sa8195p-adp-star-overlay.dtbo \ + sa8195p-v2-adp-air-overlay.dtbo + +sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb +sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb +else +dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \ + sa8195p-v2-adp-air.dtb +endif endif ifeq ($(CONFIG_ARCH_LAHAINA), y) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi new file mode 100644 index 000000000000..195d8d5a96dc --- /dev/null +++ b/qcom/sa8195p-adp-common.dtsi @@ -0,0 +1,5 @@ +#include + +&qupv3_id_1 { + status = "ok"; +}; diff --git a/qcom/sa8195p-adp-star-overlay.dts b/qcom/sa8195p-adp-star-overlay.dts new file mode 100644 index 000000000000..e6ae85d95bf7 --- /dev/null +++ b/qcom/sa8195p-adp-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,msm-id = <405 0x20000>; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa8195p-adp-star.dts b/qcom/sa8195p-adp-star.dts new file mode 100644 index 000000000000..6183b7cb3c68 --- /dev/null +++ b/qcom/sa8195p-adp-star.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195p.dtsi" +#include "sa8195p-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8195p-adp-star.dtsi b/qcom/sa8195p-adp-star.dtsi new file mode 100644 index 000000000000..ec4afde21db4 --- /dev/null +++ b/qcom/sa8195p-adp-star.dtsi @@ -0,0 +1 @@ +#include "sa8195p-adp-common.dtsi" diff --git a/qcom/sa8195p-v2-adp-air-overlay.dts b/qcom/sa8195p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..dd8060574532 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-v2-adp-air.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", + "qcom,adp-air"; + qcom,msm-id = <405 0x20000>; + qcom,board-id = <0x02010019 0>; +}; + diff --git a/qcom/sa8195p-v2-adp-air.dts b/qcom/sa8195p-v2-adp-air.dts new file mode 100644 index 000000000000..398606ccb6e2 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8195p.dtsi" +#include "sa8195p-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR"; + compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", "qcom,adp-air"; + qcom,board-id = <0x02010019 0>; +}; diff --git a/qcom/sa8195p-v2-adp-air.dtsi b/qcom/sa8195p-v2-adp-air.dtsi new file mode 100644 index 000000000000..ec4afde21db4 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air.dtsi @@ -0,0 +1 @@ +#include "sa8195p-adp-common.dtsi" diff --git a/qcom/sa8195p.dts b/qcom/sa8195p.dts new file mode 100644 index 000000000000..baf7d97a3691 --- /dev/null +++ b/qcom/sa8195p.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8195p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P AU SoC"; + compatible = "qcom,sa8195"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi new file mode 100644 index 000000000000..0032ea7d78af --- /dev/null +++ b/qcom/sa8195p.dtsi @@ -0,0 +1,8 @@ +#include "sdmshrike-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; +}; + diff --git a/qcom/sdmshrike-v2.dts b/qcom/sdmshrike-v2.dts new file mode 100644 index 000000000000..39ff556db0ec --- /dev/null +++ b/qcom/sdmshrike-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdmshrike-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 v2 SoC"; + compatible = "qcom,sa8195"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi new file mode 100644 index 000000000000..863f841f4398 --- /dev/null +++ b/qcom/sdmshrike-v2.dtsi @@ -0,0 +1,8 @@ + +#include "sdmshrike.dtsi" +/ { + model = "Qualcomm Technologies, Inc. SA8195 V2"; + qcom,msm-name = "SA8195 V2"; + qcom,msm-id = <340 0x20000>; +}; + diff --git a/qcom/sdmshrike.dts b/qcom/sdmshrike.dts new file mode 100644 index 000000000000..7a80770520b2 --- /dev/null +++ b/qcom/sdmshrike.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdmshrike.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC"; + compatible = "qcom,sdmshrike"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi new file mode 100644 index 000000000000..a2722edeb2e9 --- /dev/null +++ b/qcom/sdmshrike.dtsi @@ -0,0 +1,655 @@ +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE"; + compatible = "qcom,sdmshrike"; + qcom,msm-name = "SDMSHRIKE"; + qcom,msm-id = <340 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { + serial0 = &uart2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x400000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_5>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_6>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_7>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware: firmware { + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_mem@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 { + no-map; + reg = <0x0 0x85ffd000 0x0 0x3000>; + }; + + smem_region: smem@86000000 { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_regions: removed_regions@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x5500000>; + }; + + pil_camera_mem: camera_region@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 { + no-map; + reg = <0x0 0x8bc00000 0x0 0x180000>; + }; + + pil_npu_mem: pil_npu_region@0x8bd80000 { + no-map; + reg = <0x0 0x8bd80000 0x0 0x80000>; + }; + + pil_adsp_mem: pil_adsp_region@0x8be00000 { + no-map; + reg = <0x0 0x8be00000 0x0 0x1a00000>; + }; + + pil_modem_mem: modem_region@0x8d800000 { + no-map; + reg = <0x0 0x8d800000 0x0 0x9600000>; + }; + + pil_video_mem: pil_video_region@0x96e00000 { + no-map; + reg = <0x0 0x96e00000 0x0 0x500000>; + }; + + pil_slpi_mem: pil_slpi_region@0x97300000 { + no-map; + reg = <0x0 0x97300000 0x0 0x1400000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { + no-map; + reg = <0x0 0x98710000 0x0 0x5000>; + }; + + pil_gpu_mem: pil_gpu_region@0x98715000 { + no-map; + reg = <0x0 0x98715000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region@0x98800000 { + no-map; + reg = <0x0 0x98800000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions@0x98900000 { + no-map; + reg = <0x0 0x98900000 0x0 0x1400000>; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + + cont_splash_memory: cont_splash_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "disp_rdump_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + linux,cma-default; + }; + }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x00ac0000 0x6000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + uart2: serial@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + status = "ok"; + }; + }; + +}; + From 766b8be48c227cbe8fde02c29add83009a6f6ac2 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 1 Jul 2020 08:33:50 +0530 Subject: [PATCH 0119/1809] ARM: dts: msm: Add tlmm pinctrl support for SA8195 Add support for pinctrl node for SA8195 platform. Change-Id: Ie23e29845ecaad9588b32d67ed7d47b9bbcf5062 --- bindings/pinctrl/qcom,sdmshrike-pinctrl.txt | 185 + qcom/sdmshrike-pinctrl.dtsi | 5155 +++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + 3 files changed, 5341 insertions(+) create mode 100644 bindings/pinctrl/qcom,sdmshrike-pinctrl.txt create mode 100644 qcom/sdmshrike-pinctrl.dtsi diff --git a/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt b/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt new file mode 100644 index 000000000000..4fdbfe177a33 --- /dev/null +++ b/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt @@ -0,0 +1,185 @@ +Qualcomm Technologies, Inc. SDMSHRIKE TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +sdmshrike platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdmshrike-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the north, south, west + and east TLMM tiles. + +- reg-names: + Usage: required + Value type: + Defintiion: names for the cells of reg, must contain "north", "south" + "west" and "east". + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-ranges: + Usage: required + Value type: + Definition: see ../gpio/gpio.txt + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: see ../gpio/gpio.txt + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + ufs_reset + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, + audio_ref, atest_usb1, atest_usb2, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb20, + atest_usb21, atest_usb22, atest_usb2, atest_usb23, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, + emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist, + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, + pa_indicator, pci_e0, phase_flag, pll_bypassnl, + pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws, + prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s, + qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, + qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, + sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s, + tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, + usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3000000 { + compatible = "qcom,sdmshrike-pinctrl"; + reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi new file mode 100644 index 000000000000..e4af602e1c7a --- /dev/null +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -0,0 +1,5155 @@ +&soc { + tlmm: pinctrl@3000000 { + compatible = "qcom,sdmshrike-pinctrl"; + reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts =; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + ufs0_dev_reset_assert: ufs0_dev_reset_assert { + config { + pins = "ufs0_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs0_dev_reset_deassert: ufs0_dev_reset_deassert { + config { + pins = "ufs0_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + aqt_intr { + aqt_intr_default: aqt_intr_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm { + quin_aux_pcm_sleep: quin_aux_pcm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_active: quin_aux_pcm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_aux_pcm_din { + quin_aux_pcm_din_sleep: quin_aux_pcm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_din_active: quin_aux_pcm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm_dout { + quin_aux_pcm_dout_sleep: quin_aux_pcm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_dout_active: quin_aux_pcm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sec_tdm { + sec_tdm_sleep: sec_tdm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_active: sec_tdm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_sleep: tert_tdm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_active: tert_tdm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm { + quat_tdm_sleep: quat_tdm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_active: quat_tdm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_din { + quat_tdm_din_sleep: quat_tdm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_din_active: quat_tdm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm_dout { + quat_tdm_dout_sleep: quat_tdm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_dout_active: quat_tdm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm { + quin_tdm_sleep: quin_tdm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_active: quin_tdm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_tdm_din { + quin_tdm_din_sleep: quin_tdm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_din_active: quin_tdm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm_dout { + quin_tdm_dout_sleep: quin_tdm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_dout_active: quin_tdm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio130"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio130"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio132"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio132"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio136"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio136"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio136"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio141"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio142"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio143"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_mclk { + quin_mi2s_mclk_sleep: quin_mi2s_mclk_sleep { + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + quin_mi2s_mclk_active: quin_mi2s_mclk_active { + mux { + pins = "gpio148"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio148"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s { + quin_mi2s_sleep: quin_mi2s_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_active: quin_mi2s_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd0 { + quin_mi2s_sd0_sleep: quin_mi2s_sd0_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd0_active: quin_mi2s_sd0_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_sd1 { + quin_mi2s_sd1_sleep: quin_mi2s_sd1_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd1_active: quin_mi2s_sd1_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* add pins for DisplayPort */ + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + ap2mdm { + ap2mdm_active: ap2mdm_active { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio139"; + drive-strength = <16>; + bias-disable; + }; + }; + + ap2mdm_sleep: ap2mdm_sleep { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio139"; + drive-strength = <8>; + bias-disable; + }; + + }; + }; + + mdm2ap { + mdm2ap_active: mdm2ap_active { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio81", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdm2ap_sleep: mdm2ap_sleep { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio81", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_active: cam_sensor0_active { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_suspend: cam_sensor0_suspend { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_active: cam_sensor1_active { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_suspend: cam_sensor1_suspend { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_active: cam_sensor2_active { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_suspend: cam_sensor2_suspend { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_active: cam_sensor3_active { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_suspend: cam_sensor3_suspend { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_eldo2_default: cam_sensor_eldo2_default { + /* AVDD ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* NO PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vaf_en_default: camera_vaf_en_default { + /* VAF ELDO1 */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vana_en_default: camera_vana_en_default { + /* VANA ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rear: cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear: cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_iris: cam_sensor_active_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_iris: cam_sensor_suspend_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear: cam_sensor_active_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear: cam_sensor_suspend_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux: + cam_sensor_active_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux: + cam_sensor_suspend_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux2: + cam_sensor_active_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux2: + cam_sensor_suspend_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci4_active: cci4_active { + mux { + /* CLK, DATA */ + pins = "gpio0","gpio1"; + function = "cci_i2c"; + }; + + config { + pins = "gpio0","gpio1"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci4_suspend: cci4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio0","gpio1"; + function = "cci_i2c"; + }; + + config { + pins = "gpio0","gpio1"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci5_active: cci5_active { + mux { + /* CLK, DATA */ + pins = "gpio2","gpio3"; + function = "cci_i2c"; + }; + + config { + pins = "gpio2","gpio3"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci5_suspend: cci5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio2","gpio3"; + function = "cci_i2c"; + }; + + config { + pins = "gpio2","gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci6_active: cci6_active { + mux { + /* CLK, DATA */ + pins = "gpio39","gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39","gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci6_suspend: cci6_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39","gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39","gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci7_active: cci7_active { + mux { + /* CLK, DATA */ + pins = "gpio41","gpio42"; + function = "cci_i2c"; + }; + + config { + pins = "gpio41","gpio42"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci7_suspend: cci7_suspend { + mux { + /* CLK, DATA */ + pins = "gpio41","gpio42"; + function = "cci_i2c"; + }; + + config { + pins = "gpio41","gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + fsa_usbc_ana_en_n@100 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio96"; /* sdcard_det */ + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio175"; + function = "gpio"; + }; + + config { + pins = "gpio175"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio177"; + function = "gpio"; + }; + + config { + pins = "gpio177"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio176"; + function = "pci_e2"; + }; + + config { + pins = "gpio176"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie3 { + pcie3_clkreq_default: pcie3_clkreq_default { + mux { + pins = "gpio179"; + function = "pci_e3"; + }; + + config { + pins = "gpio179"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3_perst_default: pcie3_perst_default { + mux { + pins = "gpio178"; + function = "gpio"; + }; + + config { + pins = "gpio178"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie3_wake_default: pcie3_wake_default { + mux { + pins = "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio176"; + function = "pci_e1"; + }; + + config { + pins = "gpio176"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + hs1_i2s_mclk { + hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { + mux { + pins = "gpio155"; + function = "gpio"; + }; + + config { + pins = "gpio155"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_mclk_active: hs1_i2s_mclk_active { + mux { + pins = "gpio155"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio155"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_sck { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio156"; + function = "gpio"; + }; + + config { + pins = "gpio156"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio156"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio156"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_ws { + hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { + mux { + pins = "gpio157"; + function = "gpio"; + }; + + config { + pins = "gpio157"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_ws_active: hs1_i2s_ws_active { + mux { + pins = "gpio157"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio157"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio158"; + function = "sleep"; + }; + + config { + pins = "gpio158"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio158"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio158"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio159"; + function = "gpio"; + }; + + config { + pins = "gpio159"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio159"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio159"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + hs2_i2s_mclk { + hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { + mux { + pins = "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio160"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_mclk_active: hs2_i2s_mclk_active { + mux { + pins = "gpio160"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio160"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_sck { + hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { + mux { + pins = "gpio161"; + function = "gpio"; + }; + + config { + pins = "gpio161"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_sck_active: hs2_i2s_sck_active { + mux { + pins = "gpio161"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio161"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_ws { + hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { + mux { + pins = "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio162"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_ws_active: hs2_i2s_ws_active { + mux { + pins = "gpio162"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio162"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data0 { + hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { + mux { + pins = "gpio163"; + function = "gpio"; + }; + + config { + pins = "gpio163"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data0_active: hs2_i2s_data0_active { + mux { + pins = "gpio163"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio163"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data1 { + hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data1_active: hs2_i2s_data1_active { + mux { + pins = "gpio164"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio164"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + hs3_i2s_mclk { + hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_mclk_active: hs3_i2s_mclk_active { + mux { + pins = "gpio125"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_sck { + hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { + mux { + pins = "gpio165"; + function = "gpio"; + }; + + config { + pins = "gpio165"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_sck_active: hs3_i2s_sck_active { + mux { + pins = "gpio165"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio165"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_ws { + hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { + mux { + pins = "gpio166"; + function = "gpio"; + }; + + config { + pins = "gpio166"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_ws_active: hs3_i2s_ws_active { + mux { + pins = "gpio166"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio166"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_data0 { + hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { + mux { + pins = "gpio167"; + function = "gpio"; + }; + + config { + pins = "gpio167"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_data0_active: hs3_i2s_data0_active { + mux { + pins = "gpio167"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio167"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_data1 { + hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { + mux { + pins = "gpio168"; + function = "gpio"; + }; + + config { + pins = "gpio168"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_data1_active: hs3_i2s_data1_active { + mux { + pins = "gpio168"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio168"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio7"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio7"; + bias-pull-up; + }; + }; + + emac_mdio: emac_mdio { + mux { + pins = "gpio59"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio59"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio122"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio122"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio4"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio4"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio5"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio5"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio6"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio6"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio114"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio121"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio121"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio117"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio117"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio118"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio118"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio119"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio119"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio120"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio120"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio115"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio115"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio116"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio116"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio124"; + function = "emac_phy"; + }; + + config { + pins = "gpio124"; + bias-disable; /* NO pull */ + drive-strength = <8>; + }; + }; + + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio81"; + function = "emac_pps"; + }; + + config { + pins = "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + usb2phy_ac_en1_default: usb2phy_ac_en1_default { + mux { + pins = "gpio113"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb2phy_ac_en2_default: usb2phy_ac_en2_default { + mux { + pins = "gpio123"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-disable; + }; + }; + + audio_ioexp_reset_active: audio_ioexp_reset_active { + mux { + pins = "gpio166"; + function = "gpio"; + }; + + config { + pins = "gpio166"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio88"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + + tsif1_en { + pins = "gpio89"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + + tsif1_data { + pins = "gpio90"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + + signals_cfg { + pins = "gpio88", "gpio89", "gpio90"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio91"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio92"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + + tsif2_en { + pins = "gpio93"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + + tsif2_data { + pins = "gpio94"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + + signals_cfg { + pins = "gpio92", "gpio93", "gpio94"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio95"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + conn_power_1p8_active: conn_power_1p8_active { + mux { + pins = "gpio173"; + function = "gpio"; + }; + + config { + pins = "gpio173"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + conn_power_pa_active: conn_power_pa_active { + mux { + pins = "gpio174"; + function = "gpio"; + }; + + config { + pins = "gpio174"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio172"; + function = "gpio"; + }; + + config { + pins = "gpio172"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + /* SE0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio114", "gpio115"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio126", "gpio127"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio144", "gpio145"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio144", "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio51", "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio121", "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio121", "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio98", "gpio99"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3 East instances */ + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio88", "gpio89"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio39", "gpio40"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio39", "gpio40"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio9", "gpio10"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio94", "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio94", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 12 pin mappings */ + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio47", "gpio48"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio85"; + function = "qup16"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio23", "gpio24"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio181", "gpio182"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio181", "gpio182"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE12 UART-2wire pin mappings */ + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio85", "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio141"; + function = "qdss_cti"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio11", "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio11", "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_2uart_pins: qupv3_se16_2uart_pins { + qupv3_se16_2uart_active: qupv3_se16_2uart_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 13 UART 4-Wire pin mappings */ + qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { + qupv3_se13_default_ctsrtsrx: + qupv3_se13_default_ctsrtsrx { + mux { + pins = "gpio43", "gpio44", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_default_tx: qupv3_se13_default_tx { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_ctsrx: qupv3_se13_ctsrx { + mux { + pins = "gpio43", "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_rts: qupv3_se13_rts { + mux { + pins = "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_tx: qupv3_se13_tx { + mux { + pins = "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index a2722edeb2e9..c1079ca2028a 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -653,3 +653,4 @@ }; +#include "sdmshrike-pinctrl.dtsi" From ccc3d7329b8e1c3843f5a272d39c12ffa752311b Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Fri, 9 Oct 2020 07:32:01 -0700 Subject: [PATCH 0120/1809] ARM: dts: msm: Add interconnect entries for USB on sdxlemur Add interconnect paths for USB peripheral which is required to perform bus voting and related bandwidth constraints for USB functionality and throughput on sdxlemur. Change-Id: Id9e9843c2aad7da4d523f1e4e66d92add60a6b43 --- qcom/sdxlemur-usb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d11cad741801..75246348e3cb 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -40,6 +40,11 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, + <&system_noc MASTER_USB3 &system_noc SLAVE_IPA_CFG>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3>; + dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; From 9cf313fc677809e3d50692fd5c33b232b906c2a4 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 8 Oct 2020 12:06:45 -0700 Subject: [PATCH 0121/1809] ARM: dts: msm: Enable board specific USB detection on sdxlemur Add USB detection through extcon based notification for sdxlemur MTP/CDP. Change-Id: I31ebe73e40dabafea6caa764e887ebf022fcc64f --- qcom/sdxlemur-cdp.dtsi | 4 ++++ qcom/sdxlemur-mtp.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 0439a942f1ec..0b6dc2969cd6 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -7,3 +7,7 @@ &qnand_1 { status = "ok"; }; + +&usb { + extcon = <&vbus_detect>; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 0439a942f1ec..0b6dc2969cd6 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -7,3 +7,7 @@ &qnand_1 { status = "ok"; }; + +&usb { + extcon = <&vbus_detect>; +}; From d93309e766182a2789007c53ef6346f57da62e53 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 18 Sep 2020 12:57:41 +0530 Subject: [PATCH 0122/1809] ARM: dts: msm: Add PDC and RSC devices for yupik Add PDC interrupt controller along with apps and display RSC devices. Change-Id: If262200942bf8937dba7f04ee90f2683918da35d --- qcom/yupik-pinctrl.dtsi | 1 + qcom/yupik.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index f878cb95d247..baa6f7f738b5 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -7,5 +7,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..b94c29bff362 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include / { @@ -326,6 +327,19 @@ interrupts = ; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,yupik-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, + <55 306 4>, <59 312 3>, <62 374 2>, + <64 434 2>, <66 438 3>, <69 86 1>, + <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -759,6 +773,42 @@ compatible = "qcom,yupik-epss-l3-cpu"; #interconnect-cells = <1>; }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + system_pm { + compatible = "qcom,system-pm"; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; }; #include "shima-gdsc.dtsi" From 483746e4ea894b1e2f4eb3fcd53b2c2a7acc3be8 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 18 Sep 2020 13:55:50 +0530 Subject: [PATCH 0123/1809] ARM: dts: msm: Add idle states and stats devices for yupik Add idle states for low power modes along with stats devices. Change-Id: I3d2accba322674fc6688a3b174c94701490c74d4 --- qcom/yupik-pm.dtsi | 185 +++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 9 +++ 2 files changed, 194 insertions(+) create mode 100644 qcom/yupik-pm.dtsi diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi new file mode 100644 index 000000000000..cfd438443c3c --- /dev/null +++ b/qcom/yupik-pm.dtsi @@ -0,0 +1,185 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L3"; + qcom,clstr-tmr-add = <1000>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l3-wfi"; + entry-latency-us = <660>; + exit-latency-us = <600>; + min-residency-us = <1260>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,is-reset; + qcom,min-child-idx = <2>; + }; + + CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "cx-off"; + entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + arm,psci-suspend-param = <0x2240>; + qcom,psci-mode = <0x224>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */ + reg = <3>; + compatible = "arm,idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3638>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + arm,psci-suspend-param = <0xc340>; + qcom,psci-mode = <0xc34>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <61>; + exit-latency-us = <60>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <55>; + exit-latency-us = <66>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; + + ddr-stats@c300000 { + compatible = "qcom,ddr-stats"; + reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b94c29bff362..6ccf7a17fccf 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -42,6 +42,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -60,6 +61,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -73,6 +75,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -86,6 +89,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -99,6 +103,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -112,6 +117,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -125,6 +131,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -138,6 +145,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -813,6 +821,7 @@ #include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" +#include "yupik-pm.dtsi" #include "yupik-stub-regulator.dtsi" &gcc_pcie_0_gdsc { From a5fa3d76462e432bfa20f0f5de33b4049b3055cc Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Sun, 30 Aug 2020 16:06:52 +0530 Subject: [PATCH 0124/1809] ARM: dts: msm: Add USB nodes for Yupik Add USB nodes to support USB in peripheral mode on simulation platforms for Yupik. Change-Id: I5d73cde0fbcfb20eaa4fe578d9a65770c53965dc --- qcom/yupik-rumi.dtsi | 25 ++++++++++++++++ qcom/yupik-usb.dtsi | 68 ++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 2 ++ 3 files changed, 95 insertions(+) create mode 100644 qcom/yupik-usb.dtsi diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 3d00135b89f8..a7544916452f 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -10,6 +10,31 @@ wdog: qcom,wdt@17c10000 { status = "disabled"; }; + + usb_emu_phy_0: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>; + + qcom,emu-init-seq = <0xffff 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + +}; + +&usb0 { + /delete-property/ extcon; + dwc3@a600000 { + usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; }; &ufsphy_mem { diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi new file mode 100644 index 000000000000..0d8f7d16b223 --- /dev/null +++ b/qcom/yupik-usb.dtsi @@ -0,0 +1,68 @@ +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = ; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b94c29bff362..838e6ceccece 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -930,3 +930,5 @@ compatible = "regulator-fixed"; status = "ok"; }; + +#include "yupik-usb.dtsi" From be36d7ba01835ec8c57907b92e171804bec98248 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 4 Sep 2020 14:28:47 +0530 Subject: [PATCH 0125/1809] ARM: dts: msm: Update S3A min and init voltages for holi Update SMPS regulator S3A's minimum voltage to RPM_SMD_REGULATOR_LEVEL_NONE and init voltage to RPM_SMD_REGULATOR_LEVEL_LOW_SVS to enable GFX rail collapse for RBSC. Change-Id: Ia768244b267af223ca57f441d80395dd295fc8a8 --- qcom/holi-regulators.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index 7d2ca92fd40e..d0913902e2a3 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -32,9 +32,11 @@ regulator-name = "pm6350_s3_level"; qcom,set = <3>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; qcom,use-voltage-level; }; @@ -44,9 +46,11 @@ regulator-name = "pm6350_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; qcom,use-voltage-level; }; From de5b7cd71fc6102d4d62c489120613c1220ab406 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Mon, 21 Sep 2020 14:17:44 +0530 Subject: [PATCH 0126/1809] ARM: dts: msm: Add lcd display support on holi Add Qsync FHD display support on holi lcd cdp. Change-Id: Ic407db2f1465dbf8e2285d648d605a055d1219d0 --- qcom/holi-cdp-lcd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index b5e20250c0b9..6e5685c7b540 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -14,3 +14,8 @@ qcom,leds-per-string = <4>; }; +&sde_dsi { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; +}; From d834ae889e348558648710e0bd3ad8a121119c77 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 16 Sep 2020 17:25:55 +0530 Subject: [PATCH 0127/1809] ARM: dts: msm: Add touch support for holi Add Synaptics dsx touch support for qsync fhd panel on holi cdp. Change-Id: I8969d9599a2998a508089874519f5ca4630d99c7 --- qcom/holi-cdp-lcd.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 6e5685c7b540..057607ce47a3 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -19,3 +19,34 @@ ibb-supply = <&lcdb_ncp_vreg>; qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; }; + +&qupv3_se8_i2c { + qcom,i2c-touch-active="synaptics,dsx-i2c"; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,reset-gpio = <&tlmm 21 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + + panel = <&dsi_sharp_qsync_fhd_video>; + }; +}; From 2dd5d6184f695e62efcb413f94020d0563f648b2 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 25 Sep 2020 21:59:43 +0530 Subject: [PATCH 0128/1809] ARM: dts: msm: Add handles for USB3 interface clocks USB3 AXI cocks need to be enabled for QoS settings programming, so add USB3 AXI clock handles. Change-Id: I4ae6c49a8fc8859345bae24f00eeb0a2b0301288 --- qcom/holi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..bd7dd2432165 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1033,7 +1033,9 @@ qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; + <&rpmcc RPM_SMD_SNOC_A_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; }; config_noc: interconnect@1900000 { From 3e7e84fa3cff311ebcae335e1ceff501b47d0e2e Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 5 Oct 2020 13:13:18 +0530 Subject: [PATCH 0129/1809] ARM: dts: msm: disable mem-offline node Disable mem-offline node. Change-Id: Icea16aa19639a0b41f94640fafe10474fd4eded4 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..2e5ea84bf307 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -30,6 +30,7 @@ <0x1 0xc0000000 0x0 0x80000000>, <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; + status = "disabled"; }; aliases { From 1ab049179256656cdb8324d4e534a05891f3dc76 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 5 Oct 2020 13:10:23 +0530 Subject: [PATCH 0130/1809] ARM: dts: msm: Add focaltech touch support on holi cdp This change adds focaltech touch support on holi cdp which is needed for 120Hz video and command mode panels. Change-Id: I03cb8927faeec77cf0af9268d3000f5b3ff75fc3 --- qcom/holi-cdp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 5aba97afae07..7cbc0ae32d3c 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -232,6 +232,27 @@ panel = <&dsi_rm69299_visionox_amoled_video &dsi_rm69299_visionox_amoled_cmd>; }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L6A>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; }; #include "camera/holi-camera-sensor-cdp.dtsi" From 6323c2618c18cd3cbd438e23fb3f43de866726cf Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Mon, 12 Oct 2020 17:06:13 +0530 Subject: [PATCH 0131/1809] dt-bindings: media: Add video driver bindings for Yupik Add the video driver device tree bindings for Yupik. Change-Id: I2e71f1985d7a4a44d41fa1dd3303109826bc4c8b --- bindings/media/video/msm-vidc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index e5a9c64a7d52..80f10e86fbe2 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -9,6 +9,7 @@ Required properties: - "qcom,lahaina-vidc" : Invokes driver-specific data for LAHAINA. - "qcom,shima-vidc" : Invokes driver-specific data for SHIMA. - "qcom,holi-vidc" : Invokes driver-specific data for HOLI. + - "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL From c626705f1f18b6e9f866c5cdeb3b4c7495c92098 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Mon, 12 Oct 2020 18:04:47 +0530 Subject: [PATCH 0132/1809] ARM: dts: msm: Update CNSS node for BT GPIO config for shima QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: I124eb63c2298ca6c1770021943b5998679cfbdad --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..a1ac1e1b6e00 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3456,6 +3456,7 @@ reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; wlan-en-gpio = <&tlmm 64 0>; + qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From b4f346531e16476be1a692bb308673e3d12625ae Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 4 Sep 2020 14:28:47 +0530 Subject: [PATCH 0133/1809] ARM: dts: msm: Update S3A min and init voltages for holi Update SMPS regulator S3A's minimum voltage to RPM_SMD_REGULATOR_LEVEL_NONE and init voltage to RPM_SMD_REGULATOR_LEVEL_LOW_SVS to enable GFX rail collapse for RBSC. Change-Id: Ia768244b267af223ca57f441d80395dd295fc8a8 --- qcom/holi-regulators.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index 7d2ca92fd40e..df74687f3251 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -32,9 +32,11 @@ regulator-name = "pm6350_s3_level"; qcom,set = <3>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; qcom,use-voltage-level; }; From 624a78e9e352a31a4b26e809b3864bbb4cca58dd Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 12 Oct 2020 17:49:15 +0530 Subject: [PATCH 0134/1809] ARM: dts: msm: update ddr mapping table for shima target Update ddr mapping table for cpu7 latfloor and cpu0-llcc-ddr-lat voting device. Change-Id: I9f2249bb7ae44665627379bb887a2490d2882d01 --- qcom/shima.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..650f05e7da66 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2550,7 +2550,6 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 4) >, < 940800 MHZ_TO_MBPS( 451, 4) >, < 1171200 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, @@ -2560,7 +2559,6 @@ ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 4) >, < 940800 MHZ_TO_MBPS( 451, 4) >, < 1171200 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, @@ -2667,14 +2665,14 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, + < 2361600 MHZ_TO_MBPS( 451, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, + < 2361600 MHZ_TO_MBPS( 451, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; }; }; From cec50a1874601f45b968dbd452320f60abc8a61a Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Sun, 11 Oct 2020 12:24:52 +0530 Subject: [PATCH 0135/1809] ARM: dts: msm: Fix command DB address for sdxlemur This changes the command DB address to correct value. Change-Id: I43bbeae4c6283f6cc3f4dbba382fe76c474fef70 --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d876a6473abb..7ede38d6815d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -31,10 +31,10 @@ #size-cells = <1>; ranges; - cmd_db: reserved-memory@8fe20000 { + cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; no-map; - reg = <0x8fe20000 0x20000>; + reg = <0x8fee0000 0x20000>; }; mpss_adsp_mem: mpss_adsp_region@90800000 { From 78d5e84a022c55f540fb37008d5dd0d68742b46f Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 5 Oct 2020 16:21:14 +0530 Subject: [PATCH 0136/1809] dt-bindings: Add qfprom-sys documentation qfprom-sys can be used to export nvmem cell values as sysfs entries to user space. Change-Id: I2bcbf1bbfc0ac187e6f2b7c177b0f2bc14ca654e --- bindings/arm/msm/qcom,qfprom-sys.yaml | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 bindings/arm/msm/qcom,qfprom-sys.yaml diff --git a/bindings/arm/msm/qcom,qfprom-sys.yaml b/bindings/arm/msm/qcom,qfprom-sys.yaml new file mode 100644 index 000000000000..e0da6ada6ff7 --- /dev/null +++ b/bindings/arm/msm/qcom,qfprom-sys.yaml @@ -0,0 +1,36 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/msm/qcom,qfprom-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QFPROM_SYS driver binding + +maintainers: + +description: |+ + QFPROM_SYS provides access to the nvmem cells to the user space. + The driver exports the cell values as sysfs entries. + +properties: + compatible: + const: qcom,qfprom-sys + + nvmem-cell-name: + description: array of strings for cell names + + nvmem-cells: + description: phandle to particular cell from provider + +required: + - compatible + - nvmem-cell-name + - nvmem-cells + +example: + - | + qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&tsens_calibration1>, <&tsens_calibration2>; + nvmem-cell-names = "calibration1", "calibration2"; + }; +... From f023fb6a0f1979fe1793f5c3f07805177f3a2279 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 5 Oct 2020 15:49:43 +0530 Subject: [PATCH 0137/1809] ARM: dts: msm: Export qfprom cell to userspace Add support to export qfprom cell values as sysfs entries to userspace. Change-Id: Id4ab00e095c23d195fe017c023099dd100a6eb76 --- qcom/holi.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..2798bc18d4f9 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2719,6 +2719,21 @@ reg = <0x6028 0x4>; }; }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&adsp_variant>, + <&feat_conf8>, + <&gpu_gaming_bin>, + <&feat_conf9>; + nvmem-cell-names = "gpu_speed_bin", + "adsp_variant", + "feat_conf8", + "gpu_gaming_bin", + "feat_conf9"; + }; }; #include "holi-gpu.dtsi" From 9cb3a6ad060807ce13ef17555a9708f7bc90a119 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Mon, 28 Sep 2020 11:09:33 +0530 Subject: [PATCH 0138/1809] ARM: dts: msm: add audio routings sdxlemur Add device tree entries for sdxlemur Change-Id: I8a89a2248d6957d8a7445750e27259d3940785e5 --- qcom/sdx-audio-lpass.dtsi | 336 +++++++++++++++++++++++++++++ qcom/sdx-wsa881x.dtsi | 36 ++++ qcom/sdxlemur-audio-overlay.dtsi | 130 +++++++++++ qcom/sdxlemur-audio.dtsi | 43 ++++ qcom/sdxlemur-pinctrl.dtsi | 356 +++++++++++++++++++++++++++++++ qcom/sdxlemur-wcd.dtsi | 68 ++++++ qcom/sdxlemur.dtsi | 31 +++ 7 files changed, 1000 insertions(+) create mode 100644 qcom/sdx-audio-lpass.dtsi create mode 100644 qcom/sdx-wsa881x.dtsi create mode 100644 qcom/sdxlemur-audio-overlay.dtsi create mode 100644 qcom/sdxlemur-audio.dtsi create mode 100644 qcom/sdxlemur-wcd.dtsi diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi new file mode 100644 index 000000000000..8a5b8374ea3f --- /dev/null +++ b/qcom/sdx-audio-lpass.dtsi @@ -0,0 +1,336 @@ +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; + + audio_pkt_core_platform: audio-pkt-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + memory-region = <&audio_mem>; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_modem"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 1.2"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + }; + + prim_master: prim_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_master + &pri_sck_active_master + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + prim_slave: prim_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_slave + &pri_sck_active_slave + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_master: sec_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_master + &sec_sck_active_master + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_slave: sec_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; +}; diff --git a/qcom/sdx-wsa881x.dtsi b/qcom/sdx-wsa881x.dtsi new file mode 100644 index 000000000000..4cf0330514ff --- /dev/null +++ b/qcom/sdx-wsa881x.dtsi @@ -0,0 +1,36 @@ +&soc { + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; diff --git a/qcom/sdxlemur-audio-overlay.dtsi b/qcom/sdxlemur-audio-overlay.dtsi new file mode 100644 index 000000000000..950bc2e383a5 --- /dev/null +++ b/qcom/sdxlemur-audio-overlay.dtsi @@ -0,0 +1,130 @@ +#include "sdxlemur-wcd.dtsi" +#include "sdx-wsa881x.dtsi" +#include + +&snd_934x { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,cdc-ext-clk-rate = <19200000>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 96 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio_up: audio_ext_clk_up { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,use-pinctrl = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&i2s_mclk_sleep>; + pinctrl-1 = <&i2s_mclk_active>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@92 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 92 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; +}; + +&soc { + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-i2c"; + reg = <0x0d>; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_up 0>; + + cdc-vdd-buck-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pmxprairie_l6>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmxprairie_l6>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-dmic-sample-rate = <4800000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + }; +}; diff --git a/qcom/sdxlemur-audio.dtsi b/qcom/sdxlemur-audio.dtsi new file mode 100644 index 000000000000..30535b3a51d6 --- /dev/null +++ b/qcom/sdxlemur-audio.dtsi @@ -0,0 +1,43 @@ +#include "sdx-audio-lpass.dtsi" + +&soc { + snd_934x: sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_auxpcm>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-auxpcm.2"; + }; +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index fde920065f0b..ef506863a580 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -996,5 +996,361 @@ }; }; }; + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; }; }; diff --git a/qcom/sdxlemur-wcd.dtsi b/qcom/sdxlemur-wcd.dtsi new file mode 100644 index 000000000000..512253fd0ddd --- /dev/null +++ b/qcom/sdxlemur-wcd.dtsi @@ -0,0 +1,68 @@ +&soc { + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d876a6473abb..d7395e099654 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,12 @@ size = <0xC00000>; linux,cma-default; }; + + audio_mem: audio_region@0 { + compatible = "shared-dma-pool"; + no-map; + size = <0x400000>; + }; }; cpus { @@ -648,6 +655,29 @@ 0x2000 3 0x4400 2>; }; + + qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "modem_apps"; + qcom,intents = <0x200 20>; + reg = ; + + spf_core { + compatible = "qcom,spf_core"; + reg = ; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = ; + }; + + audio_prm { + compatible = "qcom,audio_prm"; + reg = ; + }; + }; }; }; @@ -895,3 +925,4 @@ #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" #include "sdxlemur-blsp.dtsi" +#include "sdxlemur-audio.dtsi" From 1c594332d7c33b1ff25bd60f41992684a7541352 Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Wed, 9 Sep 2020 13:18:47 +0530 Subject: [PATCH 0139/1809] ARM: dts: msm: Add scuba-iot files on 5.4 Add initial scuba iot device tree files for kernel 5.4. Change-Id: Ic891ffc3cd2608571082aa473770b4067f3934c3 --- bindings/arm/msm/msm.txt | 4 + bindings/pinctrl/qcom,scuba-pinctrl.yaml | 195 ++++ qcom/Makefile | 6 + qcom/msm-arm-smmu-scuba.dtsi | 198 ++++ qcom/pm2250-rpm-regulator.dtsi | 439 +++++++++ qcom/pm2250.dtsi | 380 ++++++++ qcom/scuba-ion.dtsi | 35 + qcom/scuba-iot-idp-overlay.dts | 12 + qcom/scuba-iot-idp.dtsi | 40 + qcom/scuba-iot-pinctrl.dtsi | 1096 ++++++++++++++++++++++ qcom/scuba-iot.dts | 9 + qcom/scuba-iot.dtsi | 707 ++++++++++++++ qcom/scuba-regulator.dtsi | 348 +++++++ 13 files changed, 3469 insertions(+) create mode 100644 bindings/pinctrl/qcom,scuba-pinctrl.yaml create mode 100644 qcom/msm-arm-smmu-scuba.dtsi create mode 100644 qcom/pm2250-rpm-regulator.dtsi create mode 100644 qcom/pm2250.dtsi create mode 100644 qcom/scuba-ion.dtsi create mode 100644 qcom/scuba-iot-idp-overlay.dts create mode 100644 qcom/scuba-iot-idp.dtsi create mode 100644 qcom/scuba-iot-pinctrl.dtsi create mode 100644 qcom/scuba-iot.dts create mode 100644 qcom/scuba-iot.dtsi create mode 100644 qcom/scuba-regulator.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 16b9fbede6b4..be6b315b994e 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -83,6 +83,9 @@ SoCs: - SDXLEMUR compatible = "qcom,sdxlemur" +- SCUBA + compatible = "qcom,scuba-iot" + - SDMMAGPIE compatible = "qcom,sdmmagpie" @@ -244,3 +247,4 @@ compatible = "qcom,holi-mtp" compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" +compatible = "qcom,scuba-idp" diff --git a/bindings/pinctrl/qcom,scuba-pinctrl.yaml b/bindings/pinctrl/qcom,scuba-pinctrl.yaml new file mode 100644 index 000000000000..803943900173 --- /dev/null +++ b/bindings/pinctrl/qcom,scuba-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,scuba-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SCUBA TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SCUBA platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,scuba-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@400000 { + compatible = "qcom,scuba-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 4ff651cd60c3..212ca73f81f0 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -75,6 +75,12 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-mtp-v2.1.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_SCUBA) += scuba-iot-idp-overlay.dtbo + +scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-mtp-overlay.dtbo \ diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi new file mode 100644 index 000000000000..2876f6370a71 --- /dev/null +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -0,0 +1,198 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x59a0000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0x59a0000 0x10000>, + <0x59c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,no-dynamic-asid; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + #size-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* ALL CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x30B>; + + gfx_0_tbu: gfx_0_tbu@0x59c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x59c5000 0x1000>, + <0x59c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + }; + }; + + apps_smmu: apps-smmu@0xc600000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc782000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + + qcom,actlr = + /* For rt TBU +3 deep PF */ + <0x400 0x3ff 0x103>, + /* For nrt TBU +3 deep PF */ + <0x800 0x3ff 0x103>; + + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc785000 0x1000>, + <0xc782200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc789000 0x1000>, + <0xc782208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc78d000 0x1000>, + <0xc782210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&kgsl_smmu 0x7 0x0>; + status = "disabled"; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E0 0x0>; + status = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E1 0x0>; + dma-coherent; + status = "disabled"; + }; +}; diff --git a/qcom/pm2250-rpm-regulator.dtsi b/qcom/pm2250-rpm-regulator.dtsi new file mode 100644 index 000000000000..ed8a655d621f --- /dev/null +++ b/qcom/pm2250-rpm-regulator.dtsi @@ -0,0 +1,439 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi new file mode 100644 index 000000000000..c7125e133d60 --- /dev/null +++ b/qcom/pm2250.dtsi @@ -0,0 +1,380 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm2250@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2250_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm2250_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm2250_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm2250_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100 0x100>; + reg-names = "adc5-usr-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + + pm2250_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + + interrupt-names = "pm2250_gpio1", "pm2250_gpio2", + "pm2250_gpio3", "pm2250_gpio4", + "pm2250_gpio5", "pm2250_gpio6", + "pm2250_gpio7", "pm2250_gpio8", + "pm2250_gpio9", "pm2250_gpio10"; + + gpio-controller; + #gpio-cells = <2>; + }; + + pm2250_rtc: qcom,pm2250_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm2250_qg: qpnp,qg { + compatible = "qcom,qpnp-qg-lite"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + qcom,pmic-revid = <&pm2250_revid>; + io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>, + <&pm2250_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600 0x100>; + }; + }; + + pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pm2250_revid>; + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-fault", + "skip-mode", + "input-current-limiting", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; + + qcom,schgm-flashlite@a600 { + reg = <0xa600 0x100>; + interrupts = + <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + }; + + pm2250_1: qcom,pm2250@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2250_vib: qcom,vibrator@5600 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5600 0x100>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pm2250_pwm1: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm2: qcom,pwms@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm3: qcom,pwms@be00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbe00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; diff --git a/qcom/scuba-ion.dtsi b/qcom/scuba-ion.dtsi new file mode 100644 index 000000000000..cba6f834d9d9 --- /dev/null +++ b/qcom/scuba-ion.dtsi @@ -0,0 +1,35 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/scuba-iot-idp-overlay.dts b/qcom/scuba-iot-idp-overlay.dts new file mode 100644 index 000000000000..7f356c2e6abf --- /dev/null +++ b/qcom/scuba-iot-idp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "scuba-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IDP"; + compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp"; + qcom,msm-id = <441 0x10000>, <471 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi new file mode 100644 index 000000000000..d0b147079ba0 --- /dev/null +++ b/qcom/scuba-iot-idp.dtsi @@ -0,0 +1,40 @@ +#include +#include + +&soc { + scuba_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm2250_qg { + qcom,battery-data = <&scuba_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; +}; + +&pm2250_charger { + interrupts-extended = <&tlmm 89 0>; + interrupt-names = "usb_id_irq"; + qcom,usb-id-gpio = <&tlmm 89 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_interrupt>; + + qcom,auto-recharge-soc = <98>; + qcom,suspend-input-on-debug-batt; + qcom,battery-data = <&scuba_batterydata>; + io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>, + <&pm2250_vadc ADC5_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "chg_temp"; + qcom,thermal-mitigation = <2000000 1500000 1000000 500000>; +}; diff --git a/qcom/scuba-iot-pinctrl.dtsi b/qcom/scuba-iot-pinctrl.dtsi new file mode 100644 index 000000000000..d141c10c703b --- /dev/null +++ b/qcom/scuba-iot-pinctrl.dtsi @@ -0,0 +1,1096 @@ +&soc { + tlmm: pinctrl@500000 { + compatible = "qcom,scuba-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + irqdomain-map-pass-thru = <0 0xff>; + irqdomain-map-mask = <0xff 0>; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup4"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* WSA speaker reset pin1 */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + fsa_usbc_ana_en_n@102 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_ctsrtsrx: + qupv3_se3_default_ctsrtsrx { + mux { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: + qupv3_se3_default_tx { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_ctsrx: qupv3_se3_ctsrx { + mux { + pins = "gpio8", "gpio11"; + function = "qup3"; + }; + + config { + pins = "gpio8", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio9"; + function = "qup3"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio10"; + function = "qup3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio80", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pm8008_interrupt: pm8008_interrupt { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; + input-enable; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active { + /*CSIMUX_OE*/ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend { + /* CSIMUX_OE */ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active { + /*CSIMUX_SEL*/ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend { + /* CSIMUX_SEL */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + gpio_vol_up: gpio_vol_up { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + usb_id_interrupt: usb_id_interrupt { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + bias-pull-up; + input-enable; + }; + }; + }; +}; diff --git a/qcom/scuba-iot.dts b/qcom/scuba-iot.dts new file mode 100644 index 000000000000..804c12bd9c93 --- /dev/null +++ b/qcom/scuba-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "scuba-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IOT SoC"; + compatible = "qcom,scuba-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi new file mode 100644 index 000000000000..c07dcefb4820 --- /dev/null +++ b/qcom/scuba-iot.dtsi @@ -0,0 +1,707 @@ +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SCUBA"; + compatible = "qcom,scuba"; + qcom,msm-id = <441 0x10000>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x100000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_adsp_mem: adsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1c00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@53600000 { + no-map; + reg = <0x0 0x53600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + no-map; + reg = <0x0 0x53610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@53615000 { + no-map; + reg = <0x0 0x53615000 0x0 0x2000>; + }; + + removed_region: removed_region@60000000 { + no-map; + reg = <0x0 0x60000000 0x0 0x3900000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + status="disabled"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + status="disabled"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + status="disabled"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + + status="disabled"; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + status="disabled"; + feat_conf5: feat_conf5@6018 { + reg = <0x6018 0x4>; + }; + + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + status = "disabled"; + }; + +dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bee000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x2000>; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +}; + +#include "pm2250.dtsi" +#include "pm2250-rpm-regulator.dtsi" +#include "scuba-regulator.dtsi" +#include "scuba-iot-pinctrl.dtsi" +#include "scuba-ion.dtsi" +#include "msm-arm-smmu-scuba.dtsi" + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm2250_vadc ADC5_GPIO3_100K_PU>, + <&pm2250_vadc ADC5_GPIO4_100K_PU>, + <&pm2250_vadc ADC5_SBUx>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + s3_die_temp { + reg = ; + }; + }; + }; +}; diff --git a/qcom/scuba-regulator.dtsi b/qcom/scuba-regulator.dtsi new file mode 100644 index 000000000000..a1344d005c24 --- /dev/null +++ b/qcom/scuba-regulator.dtsi @@ -0,0 +1,348 @@ +#include +#include + +&rpm_bus { + /* PM2250 S2 - VDD_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + + VDD_CX_LEVEL: + VDD_GFX_LEVEL: + VDD_MSS_LEVEL: + S2A_LEVEL: pm2250_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + VDD_MSS_FLOOR_LEVEL: + S2A_FLOOR_LEVEL: + pm2250_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + VDD_MSS_LEVEL_AO: + S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* PM2250 L1 - VDD_MX/WCSS_MX supply */ + rpm-regulator-ldoa1 { + status = "okay"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + + VDD_MX_LEVEL: + L1A_LEVEL: pm2250_l1_level: regulator-l1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + L1A_FLOOR_LEVEL: + pm2250_l1_floor_level: regulator-l1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + S3A: pm2250_s3: regulator-s3 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1662500>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + S4A: pm2250_s4: regulator-s4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2350000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa8 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + + VDD_LPI_CX_LEVEL: + L8A_LEVEL: pm2250_l8_level: regulator-l8-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l8_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + + VDD_LPI_MX_LEVEL: + L9A_LEVEL: pm2250_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm2250_l2: regulator-l2 { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1060000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + L3A: pm2250_l3: regulator-l3 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <570000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm2250_l4: regulator-l4 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm2250_l5: regulator-l5 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1312000>; + qcom,init-voltage = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm2250_l6: regulator-l6 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + /* WCSS_CX */ + rpm-regulator-ldoa7 { + status = "okay"; + WCSS_CX: + L7A: pm2250_l7: regulator-l7 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm2250_l10: regulator-l10 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + qcom,init-voltage = <1150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm2250_l11: regulator-l11 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm2250_l12: regulator-l12 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm2250_l13: regulator-l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm2250_l14: regulator-l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm2250_l15: regulator-l15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm2250_l16: regulator-l16 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1500000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm2250_l17: regulator-l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm2250_l18: regulator-l18 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm2250_l19: regulator-l19 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm2250_l20: regulator-l20 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm2250_l21: regulator-l21 { + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2921000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm2250_l22: regulator-l22 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; +}; From 7ff766a2eff619d278f2e85a71a71de62c17a662 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 31 Aug 2020 17:16:43 +0530 Subject: [PATCH 0140/1809] ARM: dts: msm: Update UFS VCC regulator min voltage for shima Update UFS VCC regulator min voltage for shima. Change-Id: I4d578084a83b9bcfb7a2b2e6d62b05c7e5ab2778 --- qcom/shima-idp.dtsi | 2 +- qcom/shima-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..bc2af6b9abc1 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -98,7 +98,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..ac9acf7b55a4 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -99,7 +99,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; From 677d5936a1bc57aa87b80e827d9475af2624cac5 Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Tue, 13 Oct 2020 09:09:54 +0800 Subject: [PATCH 0141/1809] ARM: dts: msm: Change the node location for optimise Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Change-Id: I2e26f72531c8a3037aa6d6e0973b00d24389335e --- qcom/lahaina.dtsi | 510 +++++++++++++++++++++++----------------------- 1 file changed, 256 insertions(+), 254 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c57b755b6524..b9827601ded2 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -32,7 +32,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -289,264 +295,260 @@ }; }; }; +}; - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - hyp_mem: hyp_region@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_region@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 { - no-map; - reg = <0x0 0x80880000 0x0 0x14000>; - }; - - smem_mem: smem_region@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - cpucp_fw_mem: cpucp_fw_region@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap: cdsp_secure_heap@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_camera_mem: pil_camera_region@85200000 { - no-map; - reg = <0x0 0x85200000 0x0 0x500000>; - }; - - pil_video_mem: pil_video_region@85700000 { - no-map; - reg = <0x0 0x85700000 0x0 0x500000>; - }; - - pil_cvp_mem: pil_cvp_region@85c00000 { - no-map; - reg = <0x0 0x85c00000 0x0 0x500000>; - }; - - pil_adsp_mem: pil_adsp_region@86100000 { - no-map; - reg = <0x0 0x86100000 0x0 0x2100000>; - }; - - pil_slpi_mem: pil_slpi_region@88200000 { - no-map; - reg = <0x0 0x88200000 0x0 0x1500000>; - }; - - pil_cdsp_mem: pil_cdsp_region@89700000 { - no-map; - reg = <0x0 0x89700000 0x0 0x1e00000>; - }; - - pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 { - no-map; - reg = <0x0 0x8b500000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 { - no-map; - reg = <0x0 0x8b510000 0x0 0xa000>; - }; - - pil_gpu_mem: pil_gpu_region@8b51a000 { - no-map; - reg = <0x0 0x8b51a000 0x0 0x2000>; - }; - - pil_spss_mem: pil_spss_region@8b600000 { - no-map; - reg = <0x0 0x8b600000 0x0 0x100000>; - }; - - pil_modem_mem: modem_region@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 { - no-map; - reg = <0x0 0xd0000000 0x0 0x800000>; - }; - - pil_trustedvm_mem: pil_trustedvm_region@d0800000 { - no-map; - reg = <0x0 0xd0800000 0x0 0x76f7000>; - }; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0xd7ef7000 0x0 0x9000>; - }; - - chan0_shbuf: neuron_block@0 { - no-map; - reg = <0x0 0xd7f00000 0x0 0x80000>; - }; - - chan1_shbuf: neuron_block@1 { - no-map; - reg = <0x0 0xd7f80000 0x0 0x80000>; - }; - - removed_mem: removed_region@d8800000 { - no-map; - reg = <0x0 0xd8800000 0x0 0x6800000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xC00000>; - }; - - sdsp_mem: sdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x800000>; - }; - - cdsp_mem: cdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x400000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - secure_display_memory: secure_display_region { /* Secure UI */ - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xA400000>; - }; - - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x3000000>; - }; - - sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - audio_cma_mem: audio_cma_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1C00000>; - }; - - splash_memory:splash_region { - reg = <0x0 0xe1000000 0x0 0x02300000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region { - reg = <0x0 0xe3300000 0x0 0x0100000>; - label = "dfps_data_region"; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - /* - * Memory shared with modem needs to be outside of - * the CLADE address space, which begins at - * 0xE0000000 and spans 512 MB. - */ - alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - - non_secure_display_memory: non_secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x6400000>; - }; + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; }; - chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + xbl_aop_mem: xbl_aop_region@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw_mem: cpucp_fw_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap: cdsp_secure_heap@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_camera_mem: pil_camera_region@85200000 { + no-map; + reg = <0x0 0x85200000 0x0 0x500000>; + }; + + pil_video_mem: pil_video_region@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x500000>; + }; + + pil_cvp_mem: pil_cvp_region@85c00000 { + no-map; + reg = <0x0 0x85c00000 0x0 0x500000>; + }; + + pil_adsp_mem: pil_adsp_region@86100000 { + no-map; + reg = <0x0 0x86100000 0x0 0x2100000>; + }; + + pil_slpi_mem: pil_slpi_region@88200000 { + no-map; + reg = <0x0 0x88200000 0x0 0x1500000>; + }; + + pil_cdsp_mem: pil_cdsp_region@89700000 { + no-map; + reg = <0x0 0x89700000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 { + no-map; + reg = <0x0 0x8b500000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 { + no-map; + reg = <0x0 0x8b510000 0x0 0xa000>; + }; + + pil_gpu_mem: pil_gpu_region@8b51a000 { + no-map; + reg = <0x0 0x8b51a000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region@8b600000 { + no-map; + reg = <0x0 0x8b600000 0x0 0x100000>; + }; + + pil_modem_mem: modem_region@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 { + no-map; + reg = <0x0 0xd0000000 0x0 0x800000>; + }; + + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + + removed_mem: removed_region@d8800000 { + no-map; + reg = <0x0 0xd8800000 0x0 0x6800000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA400000>; + }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x3000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + splash_memory:splash_region { + reg = <0x0 0xe1000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + /* + * Memory shared with modem needs to be outside of + * the CLADE address space, which begins at + * 0xE0000000 and spans 512 MB. + */ + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; }; }; From 0d20299e32d0aaf83127a25c36e9e9159c26d8a5 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 18 Aug 2020 02:17:25 +0530 Subject: [PATCH 0142/1809] ARM: dts: msm: Add hw gcc reset support for eMMC on shima Add hw gcc reset support for eMMC on shima. Change-Id: Icf62ee290c28d128bf1afc32520f8f08f9befd26 --- qcom/shima.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..05e191168fdd 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1791,6 +1791,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + bus-width = <8>; non-removable; supports-cqe; @@ -1798,6 +1800,10 @@ qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { From 9334593032d564043b66dbc0d12e4af81a6b4b00 Mon Sep 17 00:00:00 2001 From: priyankar Date: Mon, 12 Oct 2020 12:04:49 +0530 Subject: [PATCH 0143/1809] ARM: dts: msm: add WL_EN entry in BT node Add WLAN_EN GPIO entry for shima BT device tree node to handle AON LDO fully discharge issue. Change-Id: I4c471ca3f3eaaf1da38c298560930da123a87811 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..09d41282e38a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3630,6 +3630,7 @@ pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 91 0>; /* SW_CTRL */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-io-supply = <&S10B>; qcom,bt-vdd-aon-supply = <&S2C>; From f506fa55a8f4f9d6cc2eff26e5a53a5f6572c30c Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 18 Aug 2020 02:30:24 +0530 Subject: [PATCH 0144/1809] ARM: dts: msm: Add hw gcc reset for sdcc on holi Add hw gcc reset support for sdcc on holi. Change-Id: Ibe1d2180f86b7df331968154f5d4c989d0cb563a --- qcom/holi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..aaa777bd39ec 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2170,6 +2170,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + bus-width = <8>; non-removable; supports-cqe; @@ -2177,6 +2179,10 @@ qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { From fb9ed3827fd94da2035e7872d3fd8db2078274d3 Mon Sep 17 00:00:00 2001 From: Vaibhav Agrawal Date: Tue, 13 Oct 2020 20:47:25 +0530 Subject: [PATCH 0145/1809] ARM: dts: msm: Add cqhci_ice and sdcc_ice_slave regions Add the cqhci_ice in cqhci node and sdcc_ice_slave region in hwkm node to support file based encryption on holi emmc device. Change-Id: Ic9f3486f1fe3f572c444dc327e121f7b20c69129 --- qcom/holi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..8dc92e087030 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2119,8 +2119,8 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; @@ -2491,8 +2491,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; - reg = <0x4440000 0x9000>, <0x04810000 0x9000>; - reg-names = "km_master", "ice_slave"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; + reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; From f08804195c395d6e2c62b96232a8019036c1d5e0 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Tue, 13 Oct 2020 18:54:09 +0530 Subject: [PATCH 0146/1809] ARM: dts: msm: remove low voltage VCC support entry from DT Remove Low Vcc voltage support entry from DT. Change-Id: Ief37d864891bf44e71636fc4f84d58b56e6f7d36 --- qcom/lahaina-cdp.dtsi | 1 - qcom/lahaina-mtp.dtsi | 1 - qcom/lahaina-qrd-common.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 5bee66f2ef19..c9b2da960900 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -189,7 +189,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 98ff6a6a3903..b896ca9f97d0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -144,7 +144,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index a25037a3d397..935146de871d 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -24,7 +24,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; From e7187632a8cfb4b25eaff17663e6597c3a37e1fd Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 8 Oct 2020 17:16:46 -0700 Subject: [PATCH 0147/1809] ARM: dts: msm: Convert sdxlemur stub regulators to RPMh Convert stub regulator nodes to RPMh nodes by adding the correct voltage limits and correcting the labels to use the right PMIC suffix (B). Change-Id: Ie4aed5599663274d2f6db2516203db9f137968b2 --- qcom/sdxlemur-regulators.dtsi | 493 ++++++++++++++++++++++++++++++ qcom/sdxlemur-stub-regulator.dtsi | 265 ---------------- qcom/sdxlemur.dtsi | 2 +- 3 files changed, 494 insertions(+), 266 deletions(-) create mode 100644 qcom/sdxlemur-regulators.dtsi delete mode 100644 qcom/sdxlemur-stub-regulator.dtsi diff --git a/qcom/sdxlemur-regulators.dtsi b/qcom/sdxlemur-regulators.dtsi new file mode 100644 index 000000000000..f9bc61470178 --- /dev/null +++ b/qcom/sdxlemur-regulators.dtsi @@ -0,0 +1,493 @@ +#include + +/* RPMh regulators: */ +&apps_rsc { + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + VDD_MSS_LEVEL: + S1B_LEVEL: pmx65_s1_level: regulator-pmx65-s1-level { + regulator-name = "pmx65_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb2"; + S2B: pmx65_s2: regulator-pmx65-s2 { + regulator-name = "pmx65_s2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1224000>; + }; + }; + + rpmh-regulator-smpb3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb3"; + S3B: pmx65_s3: regulator-pmx65-s3 { + regulator-name = "pmx65_s3"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <776000>; + }; + }; + + rpmh-regulator-smpb4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb4"; + S4B: pmx65_s4: regulator-pmx65-s4 { + regulator-name = "pmx65_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: VDD_MX_LEVEL: + L19B_LEVEL: pmx65_l19_level: regulator-pmx65-l19-level { + regulator-name = "pmx65_l19_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: VDD_MX_LEVEL_AO: L19B_LEVEL_AO: + pmx65_l19_level_ao: regulator-pmx65-l19-level_ao { + regulator-name = "pmx65_l19_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: + S5B_LEVEL: pmx65_s5_level: regulator-pmx65-s5-level { + regulator-name = "pmx65_s5_level"; + qcom,set = ; + pmx65_s5_level-parent-supply = <&VDD_MXA_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S5B_LEVEL_AO: pmx65_s5_level_ao: regulator-pmx65-s5-level_ao { + regulator-name = "pmx65_s5_level_ao"; + qcom,set = ; + vin-supply = <&VDD_MXA_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: pmx65_s7: regulator-pmx65-s7 { + regulator-name = "pmx65_s7"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <936000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: pmx65_s8: regulator-pmx65-s8 { + regulator-name = "pmx65_s8"; + qcom,set = ; + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <824000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1B: pmx65_l1: regulator-pmx65-l1 { + regulator-name = "pmx65_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2B: pmx65_l2: regulator-pmx65-l2 { + regulator-name = "pmx65_l2"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3B: pmx65_l3: regulator-pmx65-l3 { + regulator-name = "pmx65_l3"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4B: pmx65_l4: regulator-pmx65-l4 { + regulator-name = "pmx65_l4"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5B: pmx65_l5: regulator-pmx65-l5 { + regulator-name = "pmx65_l5"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6B: pmx65_l6: regulator-pmx65-l6 { + regulator-name = "pmx65_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + VDD_MXC_LEVEL: + L7B_LEVEL: pmx65_l7_level: regulator-pmx65-l7-level { + regulator-name = "pmx65_l7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8B: pmx65_l8: regulator-pmx65-l8 { + regulator-name = "pmx65_l8"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9B: pmx65_l9: regulator-pmx65-l9 { + regulator-name = "pmx65_l9"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10B: pmx65_l10: regulator-pmx65-l10 { + regulator-name = "pmx65_l10"; + qcom,set = ; + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3088000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11B: pmx65_l11: regulator-pmx65-l11 { + regulator-name = "pmx65_l11"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12B: pmx65_l12: regulator-pmx65-l12 { + regulator-name = "pmx65_l12"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L13B: pmx65_l13: regulator-pmx65-l13 { + regulator-name = "pmx65_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L14B: pmx65_l14: regulator-pmx65-l14 { + regulator-name = "pmx65_l14"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <624000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L15B: pmx65_l15: regulator-pmx65-l15 { + regulator-name = "pmx65_l15"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16B: pmx65_l16: regulator-pmx65-l16 { + regulator-name = "pmx65_l16"; + qcom,set = ; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + qcom,init-voltage = <1776000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L17B: pmx65_l17: regulator-pmx65-l17 { + regulator-name = "pmx65_l17"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <744000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L20B: pmx65_l20: regulator-pmx65-l20 { + regulator-name = "pmx65_l20"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L21B: pmx65_l21: regulator-pmx65-l21 { + regulator-name = "pmx65_l21"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/sdxlemur-stub-regulator.dtsi b/qcom/sdxlemur-stub-regulator.dtsi deleted file mode 100644 index 3e0e649882a5..000000000000 --- a/qcom/sdxlemur-stub-regulator.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -#include - -&soc { - VDD_MSS_LEVEL: - S1E_LEVEL: - pmx65_s1_level: regulator-pmx65-s1-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s1_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - S2E: - pmx65_s2: regulator-pmx65-s2 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s2"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1560000>; - }; - - S4E: - pmx65_s4: regulator-pmx65-s4 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s4"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <2040000>; - }; - - VDD_CX_LEVEL: - S5E_LEVEL: - pmx65_s5_level: regulator-pmx65-s5-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s5_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - VDD_CX_LEVEL_AO: - S5E_LEVEL_AO: - pmx65_s5_level_ao: regulator-pmx65-s5-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s5_level_ao"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - S7E: - pmx65_s7: regulator-pmx65-s7 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s7"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1150000>; - }; - - L1E: - pmx65_l1: regulator-pmx65-l1 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l1"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - }; - - L2E: - pmx65_l2: regulator-pmx65-l2 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l2"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <1170000>; - }; - - L3E: - pmx65_l3: regulator-pmx65-l3 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l3"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <530000>; - regulator-max-microvolt = <800000>; - }; - - L4E: - pmx65_l4: regulator-pmx65-l4 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l4"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - L5E: - pmx65_l5: regulator-pmx65-l5 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l5"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1615000>; - regulator-max-microvolt = <1980000>; - }; - - L6E: - pmx65_l6: regulator-pmx65-l6 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l6"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <2000000>; - }; - - VDD_MX_LEVEL: - L7E_LEVEL: - pmx65_l7_level: regulator-pmx65-l7-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l7_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - VDD_MX_LEVEL_AO: - L7E_LEVEL_AO: - pmx65_l7_level_ao: regulator-pmx65-l7-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l7_level_ao"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - L8E: - pmx65_l8: regulator-pmx65-l8 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l8"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <751000>; - regulator-max-microvolt = <824000>; - }; - - L9E: - pmx65_l9: regulator-pmx65-l9 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l9"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <760000>; - regulator-max-microvolt = <840000>; - }; - - L10E: - pmx65_l10: regulator-pmx65-l10 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l10"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - }; - - L11E: - pmx65_l11: regulator-pmx65-l11 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l11"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - }; - - L12E: - pmx65_l12: regulator-pmx65-l12 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l12"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1260000>; - }; - - L13E: - pmx65_l13: regulator-pmx65-l13 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l13"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - }; - - L14E: - pmx65_l14: regulator-pmx65-l14 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l14"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <515000>; - regulator-max-microvolt = <1050000>; - }; - - L15E: - pmx65_l15: regulator-pmx65-l15 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l15"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1304000>; - }; - - L16E: - pmx65_l16: regulator-pmx65-l16 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l16"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1698000>; - regulator-max-microvolt = <1957000>; - }; - - L17E: - pmx65_l17: regulator-pmx65-l17 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l17"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <536000>; - regulator-max-microvolt = <888000>; - }; - - L18E: - pmx65_l18: regulator-pmx65-l18 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l18"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1304000>; - }; - - L19E: - pmx65_l19: regulator-pmx65-l19 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l19"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <880000>; - }; - - L20E: - pmx65_l20: regulator-pmx65-l20 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l20"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <826000>; - regulator-max-microvolt = <898000>; - }; - - L21E: - pmx65_l21: regulator-pmx65-l21 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l21"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <530000>; - regulator-max-microvolt = <800000>; - }; -}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c2dad689e452..b2124cb671ef 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -918,7 +918,7 @@ }; #include "sdxlemur-pinctrl.dtsi" -#include "sdxlemur-stub-regulator.dtsi" +#include "sdxlemur-regulators.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" From f6b1b9d2a3b8928ce47592b7f4f5f1c82201f6da Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Mon, 12 Oct 2020 15:58:12 -0700 Subject: [PATCH 0148/1809] ARM: dts: msm: Add SD card regulator devices for sdxlemur Add regulator devices for the external gpio-controlled regulators which power the SD Card slot on sdxlemur boards. Change-Id: I242680740f6f211ed25e70716fdb1c93512c70fe --- qcom/sdxlemur-regulators.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sdxlemur-regulators.dtsi b/qcom/sdxlemur-regulators.dtsi index f9bc61470178..2fc8aaf2362f 100644 --- a/qcom/sdxlemur-regulators.dtsi +++ b/qcom/sdxlemur-regulators.dtsi @@ -1,4 +1,5 @@ #include +#include /* RPMh regulators: */ &apps_rsc { @@ -490,4 +491,25 @@ qcom,init-mode = ; }; }; + + vreg_vddpx_2: vddpx2-gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpio = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, + <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + }; + + vreg_sd_vdd: sd-vdd-fixed-regulator { + compatible = "qcom,stub-regulator"; + regulator-name = "sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + parent-supply = <&vreg_vddpx_2>; + }; }; From b0acca421ff37e5782fd45f0ff8361465982698a Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 15 Jul 2020 09:03:49 -0600 Subject: [PATCH 0149/1809] ARM: dts: msm: Add RDPM register map for Lahaina GPU Add the RDPM register ranges so the graphics driver can share the current GPU frequency across drivers. Change-Id: I87e8f15ef4876fc030f37bfc72bc36df277cd03f --- qcom/lahaina-gpu.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 305d9f3b348f..69b7ad4292ea 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -14,9 +14,10 @@ status = "ok"; reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>; + <0x06900000 0x80000>, <0x0634000 0x1000>, + <0x0636000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx"; + "isense_cntl", "qdss_gfx", "rdpm_cx", "rdpm_mx"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; From 08267086f13e06ebad5197038aaadf3e4677793d Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Tue, 13 Oct 2020 18:41:52 +0530 Subject: [PATCH 0150/1809] ARM: dts: msm: Add GPU_CPR register space for Shima Extend the GMU register space to include the GPU_CPR registers. Change-Id: I171e18ce3bd05def1326dfd0ece8b53fb19ee62d --- qcom/shima-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 57672d085707..f7808d3470d0 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -438,7 +438,7 @@ gmu: qcom,gmu@3d69000 { compatible = "qcom,gpu-gmu"; - reg = <0x3d6a000 0x30000>, + reg = <0x3d6a000 0x34000>, <0xb290000 0x10000>; reg-names = "kgsl_gmu_reg", From b9878c46ffbe43412f17688bb557b087794eb8d4 Mon Sep 17 00:00:00 2001 From: Bavyasritha Alahari Date: Tue, 13 Oct 2020 19:04:47 +0530 Subject: [PATCH 0151/1809] ARM: dts: msm: Add cdsp rpmsg entry in holi and shima CDSPRM module relies on the rpmsg node to create a communication channel with CDSP. CDSPRM module implements a RPMSG interface to communicate with CDSP while provoding a way for CPU QoS to benefit CDSP applications performance. Change-Id: I8e151744db6943544a8b05e864b9c8e39e87291f --- qcom/holi.dtsi | 12 ++++++++++++ qcom/lahaina.dtsi | 2 +- qcom/shima.dtsi | 12 ++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..3e77d7072bf0 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1786,6 +1786,18 @@ qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; }; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c57b755b6524..5a1ef7f0b987 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4337,7 +4337,7 @@ msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; - qcom,qos-latency-us = <60>; + qcom,qos-latency-us = <70>; qcom,qos-maxhold-ms = <20>; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..db4053736c2c 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1460,6 +1460,18 @@ qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; }; }; From 1be676de59a1cc0a559a720945cfea45ef65b454 Mon Sep 17 00:00:00 2001 From: Abhishek Bohra Date: Tue, 22 Sep 2020 21:31:35 +0530 Subject: [PATCH 0152/1809] ARM: dts: msm: Add firmware node for yupik Add firmware node for vendor partition for yupik soc. Change-Id: Ifb8e21f5da45d66e9843301a3b0ece6501f14511 --- qcom/yupik.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 838e6ceccece..d9fd237a7c4c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -31,6 +31,26 @@ scm { compatible = "qcom,scm"; }; + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; }; cpus { From 11503499edcf50f1f5500bd5344de4dea541f0bd Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 13 Oct 2020 19:24:15 +0530 Subject: [PATCH 0153/1809] ARM: dts: msm: Add beamer ADC and RF sensors for HOLI Add QMI beamer ADC, RF sensors to QMI supported sensors list and beamer ADC sensors thermal config. Add modem_bw_backoff cooling device support. Change-Id: I4d1dbfd0a4cae8887deb3a258a6e2e4b09da58dc --- qcom/holi-thermal-modem.dtsi | 92 ++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/qcom/holi-thermal-modem.dtsi b/qcom/holi-thermal-modem.dtsi index 4d5b8f51b9a1..c0a9ba602c1d 100644 --- a/qcom/holi-thermal-modem.dtsi +++ b/qcom/holi-thermal-modem.dtsi @@ -20,8 +20,8 @@ #cooling-cells = <2>; }; - modem_bw: modem_bw { - qcom,qmi-dev-name = "modem_bw"; + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <2>; }; @@ -127,9 +127,16 @@ "qfe_wtr_pa1", "qfe_wtr_pa2", "qfe_wtr_pa3", - "sys_therm1", - "sys_therm2", - "modem_tsens1"; + "modem_tsens1", + "beamer_n_therm", + "beamer_e_therm", + "beamer_w_therm", + "qfe_ret_pa0_fr1", + "qfe_wtr_pa0_fr1", + "qfe_wtr_pa1_fr1", + "qfe_wtr_pa2_fr1", + "qfe_wtr_pa3_fr1", + "qfe_wtr0_fr1"; }; }; }; @@ -240,36 +247,6 @@ }; }; - modem-wifi-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - modem-ambient-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - modem-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -374,4 +351,49 @@ }; }; }; + + beamer-n-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_N_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + beamer-e-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_E_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + beamer-w-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_W_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; From 1a296131e5b7d300d1d78efe45ffd97d35248499 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 14 Oct 2020 15:58:12 +0530 Subject: [PATCH 0154/1809] ARM: dts: msm: Export qfprom cell to userspace for Shima Add support to export qfprom cell values as sysfs entries to userspace. Change-Id: Iedc3fbdffeb1992323e514628961567479c0ed35 --- qcom/shima.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..3ef5da0e77b3 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3451,6 +3451,21 @@ }; }; + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&gpu_gaming_bin>, + <&adsp_variant>, + <&feat_conf_m7>, + <&feat_conf_qc_spare_20_lsb>; + nvmem-cell-names = "gpu_speed_bin", + "gpu_gaming_bin", + "adsp_variant", + "feat_conf_m7", + "feat_conf_qc_spare_20_lsb"; + }; + wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; reg = <0xb0000000 0x10000>; From cd42f7bceff3846f0e23e6d79b095708e85be476 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 8 Oct 2020 15:48:37 -0700 Subject: [PATCH 0155/1809] ARM: dts: msm: Add QMP PHY dt entries on sdxlemur Add hsphy and ssphy related dt nodes and the phy init sequence on sdxlemur. Change-Id: I89177fecd76f5a9ace051e118f304698e9d1e636 --- qcom/sdxlemur-usb.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d11cad741801..c80dc7e4b561 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -1,3 +1,5 @@ +#include + &soc { usb: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -44,6 +46,7 @@ compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = ; + usb-phy = <&usb2_phy>, <&usb_qmp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -60,4 +63,155 @@ usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + + usb2_phy: hsphy@ff4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0xff4000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pmx65_l4>; + qcom,vdd-voltage-level = <0 912000 912000>; + vdda18-supply = <&pmx65_l5>; + vdda33-supply = <&pmx65_l10>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_BCR>; + reset-names = "phy_reset"; + qcom,no-rext-present; + }; + + usb_qmp_phy: ssphy@ff6000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0xff6000 0x2000>, + <0xff628c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pmx65_l4>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47900>; + core-supply = <&pmx65_l1>; + qcom,core-max-load-uA = <15000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + + }; }; From fd35c6b3ec1eafedd33e3f7605d8df8ae773bbd3 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Mon, 12 Oct 2020 19:21:45 -0700 Subject: [PATCH 0156/1809] ARM: dts: msm: Update the qmp register macro file name for Lahaina Update the qmp register macro definition file name from target specific to generic 5nm combo and uni file. Change-Id: I58da7126a19985e1fa26a71bff90fd83f0c2fcbb --- qcom/lahaina-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..9a0515fb941c 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -1,5 +1,6 @@ #include -#include +#include +#include &soc { usb0: ssusb@a600000 { From 15b27cfd0ae9aac4ddfa031d331daf10a73a604f Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Wed, 14 Oct 2020 21:03:42 +0530 Subject: [PATCH 0157/1809] ARM: dts: msm: Add cnss config for internal power amp for shima QCA6490 requires additional voltage regulator for internal power amplifier. Add config for TCS CMD offset to enable this regulator. Change-Id: Iea43e40b95f7bf36ab2bf0dd36039fd21f213be5 --- qcom/shima.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 3e2dd664a680..488876e47603 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3463,8 +3463,9 @@ wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; - reg = <0xb0000000 0x10000>; - reg-names = "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>, + <0xb2e5510 0x690>; + reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; @@ -3473,6 +3474,8 @@ qcom,wlan-rc-num = <0>; qcom,wlan-ramdump-dynamic = <0x420000>; qcom,wlan-cbc-enabled; + /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ + qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; vdd-wlan-aon-supply = <&S2C>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 2ab5c5ffbefd6e681965ee76472ced2a7462977c Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Wed, 14 Oct 2020 22:40:24 +0530 Subject: [PATCH 0158/1809] ARM: dts: msm: Configure L9B from retention mode to LPM on shima L9B supply won't really support retention mode on shima, so move it from RM to LPM by increasing the load to 10mA. Change-Id: Ie3f10de1c63a123dae2c5dc2bf7a3ea5a6decc5a --- qcom/shima-idp.dtsi | 5 ++--- qcom/shima-qrd.dtsi | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..6f22c8274d7a 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -104,15 +104,14 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; - vccq-min-microamp = <0>; + vccq-min-microamp = <10000>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; vccq2-max-microamp = <800000>; qcom,vddp-ref-clk-supply = <&L9B>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vddp-ref-clk-min-microamp = <0>; + qcom,vddp-ref-clk-max-microamp = <10000>; status = "ok"; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..0adde33e1398 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -105,14 +105,13 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; - vccq-min-microamp = <0>; + vccq-min-microamp = <10000>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; qcom,vddp-ref-clk-supply = <&L9B>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vddp-ref-clk-min-microamp = <0>; + qcom,vddp-ref-clk-max-microamp = <10000>; status = "ok"; }; From 812302f3d21fcce100e5d75e4ed441a778f7b173 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 24 Sep 2020 18:37:45 -0700 Subject: [PATCH 0159/1809] ARM: dts: msm: add display message queue to trusted vm for lahaina Add a bidirectional message queue in trusted vm for display. This message queue will be used to send display custom data across the vm's. Change-Id: I0e6bb8116acc126642a5bb57fe90fee011acab19 --- qcom/lahaina-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 566dcd1074bd..46d744d95235 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -167,6 +167,15 @@ qcom,label = <0x0000001>; }; + display-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/display-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000002>; + }; + neuron-ch1-shm { vdevice-type = "shm-doorbell"; generate = "/hypervisor/neuron-ch1-shm"; From 6b298addf1c7788a6b9c449f20eb64a2397607de Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Thu, 15 Oct 2020 10:37:48 +0800 Subject: [PATCH 0160/1809] ARM: dts: msm: update PLL_BIAS_CONTROL_2 for holi QRD change PLL_BIAS_CONTROL_2 from 0x15 to 0x17. Change-Id: Ibad85b6ede20016c40ea0c84d96a6e1e799e0d90 --- qcom/holi-qrd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 48e5127acab5..35c761d75f92 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -414,7 +414,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ @@ -435,7 +435,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ From d9780a09566a760e382b5907d29a5738b01ee348 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 14 Oct 2020 16:55:57 +0800 Subject: [PATCH 0161/1809] ARM: dts: msm: Add panel information to amoled-ecm for Shima platforms Add panel information for amoled-ecm device so that the driver can get display off/on notification from the DRM for the active panel and disable/re-enable ECM accordingly. Change-Id: I5dc22cd1b669e92991325f7be8ef4536a140277c --- qcom/shima-idp.dtsi | 8 ++++++++ qcom/shima-qrd.dtsi | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..855c9a746bac 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -148,6 +148,14 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; +}; + &battery_charger { qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..0b6dff79f200 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -185,6 +185,11 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; +}; + &battery_charger { qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 7500000 7000000 6500000 6000000 5500000 From c39aebbf55cc97674fc45aec145e9b013a038012 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Mon, 12 Oct 2020 14:16:16 +0530 Subject: [PATCH 0162/1809] ARM: dts: msm: Add rmtfs_sharedmem support for sdxlemur Add shared memory support to enable rmt_storage service in userspace that allows other processor to access the primary storage device to store its data. Change-Id: I531df175ed7af586f29e274f174b1e7e6508b84c --- qcom/sdxlemur.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c2dad689e452..3c50979bd76e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -915,6 +915,14 @@ thermal_zones: thermal-zones { }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x400000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; }; #include "sdxlemur-pinctrl.dtsi" From b51f076234c2f627bc23819ec6da28979a702f48 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Mon, 12 Oct 2020 13:17:35 +0800 Subject: [PATCH 0163/1809] ARM: dts: msm: add USB3_DP_COM_TYPEC_STATUS register Add USB3_DP_COM_TYPEC_STATUS register for Lahaina and Shima, this register's bit0 is used indicates the type-c orientation. Change-Id: I42e35da3074497f24858a313ad4d9235b4729423 --- qcom/lahaina-usb.dtsi | 3 ++- qcom/shima-usb.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..0f901b4857d9 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -177,7 +177,8 @@ USB3_DP_COM_RESET_OVRD_CTRL USB3_DP_COM_PHY_MODE_CTRL USB3_DP_COM_TYPEC_CTRL - USB3_DP_PCS_CLAMP_ENABLE>; + USB3_DP_PCS_CLAMP_ENABLE + USB3_DP_COM_TYPEC_STATUS>; qcom,qmp-phy-init-seq = /* */ diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi index 48b5d3839b21..6e1d3e73b03a 100644 --- a/qcom/shima-usb.dtsi +++ b/qcom/shima-usb.dtsi @@ -148,7 +148,8 @@ USB3_DP_COM_RESET_OVRD_CTRL USB3_DP_COM_PHY_MODE_CTRL USB3_DP_COM_TYPEC_CTRL - USB3_DP_PCS_CLAMP_ENABLE>; + USB3_DP_PCS_CLAMP_ENABLE + USB3_DP_COM_TYPEC_STATUS>; qcom,qmp-phy-init-seq = /* */ From c86be42f33c9f212b3692b91f91ac0e2564857fe Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 15 Oct 2020 16:50:08 +0530 Subject: [PATCH 0164/1809] ARM: dts: msm: Change IPA bandwidth threshold value for holi target Change IPA bandwidth threshold value for holi target. Change-Id: I85e67351f544fe0eb6689257e4d15190b454a9cd --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..58f58f86e357 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2638,7 +2638,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <310 600 1000>; + qcom,throughput-threshold = <600 2500 5000>; qcom,scaling-exceptions = <>; /* smp2p information */ From 1e09bb15e1e6e8066078be8274f27061fd67b6e8 Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Thu, 15 Oct 2020 19:28:37 +0800 Subject: [PATCH 0165/1809] ARM: dts: msm: Move firmware node ahead Bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: Id04bf9b8544cf43e33c0fc30aaef4b9bf5eb093d --- qcom/lahaina.dtsi | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index b9827601ded2..9b7ee550cea5 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -63,6 +63,8 @@ usb1 = &usb1; }; + firmware: firmware {}; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -267,31 +269,31 @@ }; soc: soc { }; +}; - firmware: firmware { - scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; }; }; }; From e085c9cda36cbf8bab7ffcd11639021579dbaec4 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 22 Sep 2020 19:57:27 +0800 Subject: [PATCH 0166/1809] bindings: pinctrl: Add device-tree bindings for SDNIGHTJAR pinctrl driver Add documentation describing the device-tree properties for the nightjar pinctrl driver. Change-Id: Ibb21c577b3672364247cfdf5b98154948ea03444 --- bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt | 139 ++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt diff --git a/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt b/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt new file mode 100644 index 000000000000..73b73620978a --- /dev/null +++ b/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt @@ -0,0 +1,139 @@ +QTI SDXNIGHTJAR TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDXNIGHTJAR platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdxnightjar-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + +Example: + + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,mdm9650-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_console_active: uart1_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; From 411a3dba3b425b7db34771b0ce4fcd9c20871457 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 12:20:10 +0530 Subject: [PATCH 0167/1809] ARM: dts: msm: Enable LCD_REG_EN gpio and LCD_BKLT_PWM on shima Enabling LCD_REG_EN gpio on shima pinctrls and LCD_BKLT_PWM on shima pmic overlays on shima target. Change-Id: If02438f5c28160b643248e3b403c65083e9b6e56 --- qcom/shima-pinctrl.dtsi | 8 ++++---- qcom/shima-pmic-overlay.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 91e3b21c26af..eeb47a49d145 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -2872,12 +2872,12 @@ pmx_sde: pmx_sde { sde_dsi_active: sde_dsi_active { mux { - pins = "gpio24"; + pins = "gpio24", "gpio47"; function = "gpio"; }; config { - pins = "gpio24"; + pins = "gpio24", "gpio47"; drive-strength = <8>; /* 8 mA */ bias-disable = <0>; /* no pull */ }; @@ -2885,12 +2885,12 @@ sde_dsi_suspend: sde_dsi_suspend { mux { - pins = "gpio24"; + pins = "gpio24", "gpio47"; function = "gpio"; }; config { - pins = "gpio24"; + pins = "gpio24", "gpio47"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* PULL DOWN */ }; diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index de365f79de68..d83e6fa3b45c 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -47,6 +47,18 @@ power-source = <1>; }; }; + + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio9"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; }; &pmk8350_vadc { From ea2569f0b365fbf99a1a98a66ca10e42794c6f8b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 13 Oct 2020 21:06:22 +0530 Subject: [PATCH 0168/1809] ARM: dts: msm: Update GPU, core isolation and hotplug threshold for SHIMA Update core isolation and hotplug threshold for silver CPUs to 110C and 112C. Update core isolation and hotplug threshold for gold and gold plus to 108C and 110C. GPU thermal mitigation configuration uses a virtual sensor, which will estimate the max of two GPU sensors. Change the GPU thermal rule to directly use these individual sensors in two separate rule to achieve a better thermal control. Change-Id: I8ee76573e9bef956ca7833d34c8f8aecf3adaa7e --- qcom/shima-thermal.dtsi | 232 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 226 insertions(+), 6 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index fc97b1dddafa..abf3371998fc 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -110,6 +110,49 @@ }; }; + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; apc1_cluster: qcom,apc1-cluster { @@ -733,6 +776,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -740,6 +789,17 @@ trip = <&cpu00_config>; cooling-device = <&cpu0_isolate 1 1>; }; + + cpu00_cdev1 { + trip = <&cpu00_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; }; }; @@ -754,6 +814,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -761,6 +827,17 @@ trip = <&cpu01_config>; cooling-device = <&cpu1_isolate 1 1>; }; + + cpu01_cdev1 { + trip = <&cpu01_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; }; }; @@ -775,6 +852,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -782,6 +865,17 @@ trip = <&cpu02_config>; cooling-device = <&cpu2_isolate 1 1>; }; + + cpu02_cdev1 { + trip = <&cpu02_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; }; }; @@ -796,6 +890,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -803,6 +903,17 @@ trip = <&cpu03_config>; cooling-device = <&cpu3_isolate 1 1>; }; + + cpu03_cdev1 { + trip = <&cpu03_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; }; }; @@ -813,6 +924,12 @@ thermal-governor = "step_wise"; trips { cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -830,6 +947,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -840,6 +962,12 @@ thermal-governor = "step_wise"; trips { cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -857,6 +985,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -867,6 +1000,12 @@ thermal-governor = "step_wise"; trips { cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -884,6 +1023,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -894,6 +1038,12 @@ thermal-governor = "step_wise"; trips { cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -911,6 +1061,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -921,6 +1076,12 @@ thermal-governor = "step_wise"; trips { cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -938,6 +1099,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -948,6 +1114,12 @@ thermal-governor = "step_wise"; trips { cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -965,6 +1137,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -975,6 +1152,12 @@ thermal-governor = "step_wise"; trips { cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -986,6 +1169,11 @@ trip = <&cpu16_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; @@ -996,6 +1184,12 @@ thermal-governor = "step_wise"; trips { cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1007,17 +1201,21 @@ trip = <&cpu17_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; - gpuss-max-step { + gpuss-0-step { polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 1>, <&tsens1 2>; - sensor-aggregation = ; + thermal-sensors = <&tsens1 1>; trips { - gpuss_config: active-config0 { + gpuss0_config: active-config0 { temperature = <95000>; hysteresis = <0>; type = "passive"; @@ -1026,7 +1224,29 @@ cooling-maps { gpu_cdev { - trip = <&gpuss_config>; + trip = <&gpuss0_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 2>; + trips { + gpuss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss1_config>; cooling-device = <&msm_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; From 8ceaeb345ea43c89f7ba79c38dd4dbc972d3affd Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 1 Oct 2020 16:47:12 -0700 Subject: [PATCH 0169/1809] ARM: dts: qcom: Fix watchdog entry for sdxlemur The old watchdog entry did not account for the new watchdog changes. This changes it to be compatible with the new watchdog driver. Change-Id: I18542ea7803e5ac2d32b8c41c876957fb2c9f592 --- qcom/sdxlemur.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 3c50979bd76e..dd2376f371ed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -232,11 +232,12 @@ dcc-ram-offset = <0x800>; }; - watchdog: qcom,wdt@17817000 { + wdog: qcom,wdt@17817000 { compatible = "qcom,msm-watchdog"; reg = <0x17817000 0x1000>; reg-names = "wdt-base"; - interrupts = <1 3 0>, <1 2 0>; + interrupts = , + ; qcom,bark-time = <11000>; qcom,pet-time = <10000>; qcom,wakeup-enable; From e52c882a4cd2f243ea4f8c87104aa8ee383c6297 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 16 Oct 2020 16:27:15 +0530 Subject: [PATCH 0170/1809] dt-bindings: thermal: Add support for QMI beamer ADC and RF sensors Add support for QMI beamer ADC and RF sensors to apps. It enables these sensors as thermal zone sensors so that we can read and set trip thresholds via thermal zone. Change-Id: I000d335dc2ee82afd4b3f41425ff296205e6f922 --- bindings/thermal/qti-qmi-sensor.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index b9a703cf1a14..319329676034 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -62,6 +62,15 @@ Subsystem properties: 29. mmw_pa3 30. sdr_mmw_therm 31. msm_skin_therm + 32. beamer_n_therm + 33. beamer_e_therm + 34. beamer_w_therm + 35. qfe_ret_pa0_fr1 + 36. qfe_wtr_pa0_fr1 + 37. qfe_wtr_pa1_fr1 + 38. qfe_wtr_pa2_fr1 + 39. qfe_wtr_pa3_fr1 + 40. qfe_wtr0_fr1 Example: From 2689aa15563fe8023e1c664a09d8431db6afde75 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 28 Sep 2020 12:00:33 +0530 Subject: [PATCH 0171/1809] ARM: dts: msm: Add HWSPINLOCK, SMEM and SMP2P for yupik Add the device tree nodes to enable smp2p communication to remote processors. Change-Id: I09caa7bfc86231a8b1abdbe2141404081a0f1174 --- qcom/yupik.dtsi | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 63494e9684f3..d3e179d55f4c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -837,6 +837,117 @@ , ; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-nsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "shima-gdsc.dtsi" From 1d91bdadb78b43f93390ed8456def479582aed91 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 28 Sep 2020 20:01:14 +0530 Subject: [PATCH 0172/1809] ARM: dts: msm: Add glink entries for yupik Add the device tree entries for glink driver and glink packet driver to provide the communication with remote peripherals. Change-Id: Ibe804ad78b57a7eabc764227e40316e8d9f16fe3 --- qcom/yupik.dtsi | 167 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d3e179d55f4c..dec328452df7 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -948,6 +948,173 @@ #interrupt-cells = <2>; }; }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_wpss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>, + <&glink_wpss>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "dsps_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_wpss>; + }; + }; + + glink_wpss: wpss { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,wpss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; }; #include "shima-gdsc.dtsi" From a1b66c7137a138a54833ee3028f2bb7af80aff03 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 29 Sep 2020 12:55:56 +0530 Subject: [PATCH 0173/1809] ARM: dts: msm: Add AOP QMP nodes for yupik Add the QMP and QMP DEBUGFS node to facilitiate communication with AOP. The QMP driver sends messages using the AOP msgram with a mailbox like protocol. Change-Id: I71d3fe058ff98d2000c61d91b3601c3d6217ed34 --- qcom/yupik.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index dec328452df7..c07780c7eed8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1115,6 +1115,31 @@ qcom,glinkpkt-dev-name = "smd11"; }; }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "aop_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + reg = <0xc300000 0x400>; + reg-names = "msgram"; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; #include "shima-gdsc.dtsi" From 68909502f4d209717c4ed7433f12391a492f41a2 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sun, 18 Oct 2020 22:23:06 +0530 Subject: [PATCH 0174/1809] ARM: dts: qcom: Add quiet-therm thermal zone mitigation for HOLI Add quiet-therm skin thermal zone mitigation rule with gpu, cdsp and modem_skin as cooling devices based on latest recommendations. Change-Id: I25e18a1a693f3107be823ea6dd666084e4f84a2c --- qcom/holi-qrd.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 35c761d75f92..51c11a11dd60 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -320,6 +320,70 @@ 500000>; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; + + trips { + quiet_modem_trip0: quiet-modem-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_modem_trip1: quiet-modem-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_modem_trip2: quiet-modem-trip2 { + temperature = <56000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev { + trip = <&quiet_cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + cdsp-cdev0 { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + modem-skin-cdev0 { + trip = <&quiet_modem_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&quiet_modem_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&quiet_modem_trip2>; + cooling-device = <&modem_skin 3 3>; + }; + }; + }; +}; + &pm7250b_qg { status = "ok"; #io-channel-cells = <1>; From c12341fa846cbdae3b4899d126681a84ac6d5b81 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 19 Oct 2020 15:42:49 +0530 Subject: [PATCH 0175/1809] ARM: dts: msm: Update the PSCI mode id for yupik Cx-off mode is not supported for yupik. Update the mode id to exercise cx-ret mode instead of cx-off. Change-Id: I685d2869c58d99edc4c3631c0c74ae08877ee03a --- qcom/yupik-pm.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi index cfd438443c3c..5019d0da8c8c 100644 --- a/qcom/yupik-pm.dtsi +++ b/qcom/yupik-pm.dtsi @@ -37,15 +37,15 @@ qcom,min-child-idx = <2>; }; - CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */ + CX_RET: qcom,pm-cluster-level@2 { /* Cx Ret */ reg = <2>; compatible = "arm,idle-state"; - idle-state-name = "cx-off"; + idle-state-name = "cx-ret"; entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x2240>; - qcom,psci-mode = <0x224>; + arm,psci-suspend-param = <0x1240>; + qcom,psci-mode = <0x124>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; @@ -58,8 +58,8 @@ entry-latency-us = <3638>; exit-latency-us = <6562>; min-residency-us = <9826>; - arm,psci-suspend-param = <0xc340>; - qcom,psci-mode = <0xc34>; + arm,psci-suspend-param = <0xb340>; + qcom,psci-mode = <0xb34>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From 6df8cf02ab25b0df4c3b1a0791e8f17bf3514148 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 19 Oct 2020 19:32:44 +0530 Subject: [PATCH 0176/1809] ARM: dts: msm: Update PSCI state id for shima The wakeup value needs to be programmed for cx-off mode as well. Update the state id to 0x234 to indicate trustzone to program wakeup value. Change-Id: I3fcb7c66b4d796b121fce4059574d467f61f91a9 --- qcom/shima-pm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-pm.dtsi b/qcom/shima-pm.dtsi index cfd438443c3c..73a3de7dbd79 100644 --- a/qcom/shima-pm.dtsi +++ b/qcom/shima-pm.dtsi @@ -44,8 +44,8 @@ entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x2240>; - qcom,psci-mode = <0x224>; + arm,psci-suspend-param = <0x2340>; + qcom,psci-mode = <0x234>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From 00b3cbb697558c79ef788a5de6a43b2f573fb4a1 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 20 Oct 2020 00:12:55 +0530 Subject: [PATCH 0177/1809] ARM: dts: qcom: add physical addr for swr tx slaves of Shima Add dt property to read physical addresses of TX soundwire master slaves of Shima. Change-Id: I00d4c7c7c7c6c4c59b792fbea48e8cf4ae44bbb8 --- qcom/shima-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 5c44652dd529..69e699119b63 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -69,6 +69,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <1>; + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; wcd938x_tx_slave: wcd938x-tx-slave { From 9c0aa378c748225ad4d78a8c9406447576f3e342 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Wed, 30 Sep 2020 16:24:49 -0700 Subject: [PATCH 0178/1809] ARM: dts: msm: Update memory-map for sdxlemur Select a different memory map depending on board file. Change-Id: I5ed751eac765363a064edf8069428e4290a0648d --- qcom/sdxlemur-1024mb.dtsi | 9 +++++ qcom/sdxlemur-512mb.dtsi | 53 ++++++++++++++++++++++++++++ qcom/sdxlemur-cdp.dts | 2 +- qcom/sdxlemur-mtp-cpe.dts | 1 + qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 1 + qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 1 + qcom/sdxlemur-mtp-mbb.dts | 1 + qcom/sdxlemur-mtp.dts | 1 + qcom/sdxlemur-rcm-pcie-ep.dts | 1 + qcom/sdxlemur-rcm-rc.dts | 1 + qcom/sdxlemur-rumi.dts | 1 + qcom/sdxlemur.dtsi | 42 ---------------------- 13 files changed, 72 insertions(+), 43 deletions(-) create mode 100644 qcom/sdxlemur-1024mb.dtsi create mode 100644 qcom/sdxlemur-512mb.dtsi diff --git a/qcom/sdxlemur-1024mb.dtsi b/qcom/sdxlemur-1024mb.dtsi new file mode 100644 index 000000000000..86fae265cfbd --- /dev/null +++ b/qcom/sdxlemur-1024mb.dtsi @@ -0,0 +1,9 @@ +#include "sdxlemur-512mb.dtsi" + +&mpss_adsp_mem { + reg = <0x90800000 0x10000000>; +}; + +&access_control_mem { + reg = <0x8fd80000 0x80000>; +}; diff --git a/qcom/sdxlemur-512mb.dtsi b/qcom/sdxlemur-512mb.dtsi new file mode 100644 index 000000000000..4e48c97523d0 --- /dev/null +++ b/qcom/sdxlemur-512mb.dtsi @@ -0,0 +1,53 @@ +&reserved_memory { + mpss_adsp_mem: mpss_adsp_region@90800000 { + no-map; + reg = <0x90800000 0xF800000>; + }; + + tz_mem: tz_mem_region@8ff00000 { + no-map; + reg = <0x8ff00000 0x600000>; + }; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x8fee0000 0x20000>; + }; + + smem_mem: smem_region@8fe20000 { + no-map; + reg = <0x8fe20000 0xc0000>; + label = "smem_mem"; + }; + + aop_mem: aop_regions@0x8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + access_control_mem: access_control_region@8fd80000 { + no-map; + reg = <0x8fd80000 0x40000>; + }; + + hyp_mem: hyp_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + secdata_mem: secdata_region@0x8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + ipa_fw_mem: ipa_fw_region@0x8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_dsm: mpss_dsm_region@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; +}; diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 963cb1d1f502..93cd0f92dd66 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -2,7 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" - +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 696b1ab58713..0e48eebc0c2f 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts index ead998c52e3c..e8afacb3c415 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts index 615f5c59659c..eb4521abbe69 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts index c849ed133087..ac65ac0913e2 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index 117c1bb3719b..e9bc21eb4200 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; diff --git a/qcom/sdxlemur-mtp.dts b/qcom/sdxlemur-mtp.dts index f826463910c2..dfbdf23171f0 100644 --- a/qcom/sdxlemur-mtp.dts +++ b/qcom/sdxlemur-mtp.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP"; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts index 11a14dc88bef..43e60bca2eca 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dts +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index f061c22ed532..990224dd464a 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; diff --git a/qcom/sdxlemur-rumi.dts b/qcom/sdxlemur-rumi.dts index 59a28ebbef55..d0b471e1379f 100644 --- a/qcom/sdxlemur-rumi.dts +++ b/qcom/sdxlemur-rumi.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rumi.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RUMI"; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f7026ee36267..a3294e016f86 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -32,48 +32,6 @@ #size-cells = <1>; ranges; - cmd_db: reserved-memory@8fee0000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x8fee0000 0x20000>; - }; - - mpss_adsp_mem: mpss_adsp_region@90800000 { - no-map; - reg = <0x90800000 0x10000000>; - }; - - tz_mem: tz_mem_region@8ff00000 { - no-map; - reg = <0x8ff00000 0x600000>; - }; - - smem_mem: smem_region@8fe40000 { - no-map; - reg = <0x8fe40000 0xc0000>; - label = "smem_mem"; - }; - - peripheral_mem: peripheral_region@8fd00000 { - no-map; - reg = <0x8fd00000 0x140000>; - }; - - /* - * The exact size of this region may vary based on DDR size. - * 0x100000 will be valid for all DDR sizes at the cost of - * slightly reducing the memory available for HLOS. - */ - peripheral_mem2: peripheral_region2@8fb00000 { - no-map; - reg = <0x8fb00000 0x100000>; - }; - - mpss_dsm: mpss_dsm_region@8c400000 { - no-map; - reg = <0x8c400000 0x3200000>; - }; - dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; From 0b6c0a5d70c102e9838af6be28be9113c70a6f3e Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Tue, 20 Oct 2020 10:00:52 +0530 Subject: [PATCH 0179/1809] ARM: dts: msm: Add cnss-enable-self-recovery flag for shima Add cnss-enable-self-recovery flag for shima. It enables self recovery on link down detected by host driver. Change-Id: I2c66bcc0d9359dbb972b7180aa40eba404cb08d8 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..4e0d2f39ab72 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3497,6 +3497,7 @@ qcom,wlan-cbc-enabled; /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; + cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S2C>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 9e2e1a059b39fecd22926d93f9f78edf9c34dbc9 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 20 Oct 2020 13:38:53 +0530 Subject: [PATCH 0180/1809] ARM: dts: msm: Add bootargs for Yupik Add bootargs earlycon boot parameters for Yupik SOC. Change-Id: I8019e2d2cc86de5ab51c850af8e4b43cf7365cad --- qcom/yupik.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..4ae827c5a3bc 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -306,7 +306,9 @@ soc: soc { }; - chosen { }; + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; }; &soc { From 9419db1f2aad66429f96c5735c7eda97f5462f11 Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Tue, 20 Oct 2020 13:21:19 +0530 Subject: [PATCH 0181/1809] bindings: mproc: Add support for scuba and monaco mailbox strings Update bindings of mailbox for scuba and monaco device. Change-Id: Ie35d098cb7bce110597c84e34e6eb498d3a170a9 --- bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/mailbox/qcom,apcs-kpss-global.txt b/bindings/mailbox/qcom,apcs-kpss-global.txt index 63cd9385a136..833c68a150c1 100644 --- a/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -17,6 +17,8 @@ platforms. "qcom,sm8150-apss-shared" "qcom,ipq8074-apcs-apps-global" "qcom,sdxlemur-apcs-gcc" + "qcom,scuba-apcs-hmss-global" + "qcom,monaco-apcs-hmss-global" - reg: Usage: required From 09a059f435aa12ab46215c534897cc398a17e10c Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 20 Oct 2020 14:53:20 +0530 Subject: [PATCH 0182/1809] ARM: dts: msm: Update PSCI state id for yupik The wakeup value needs to be programmed for cx-ret mode as well. Update the state id to 0x134 to indicate trustzone to program wakeup value. Change-Id: I25143ff78842c7d415f46d0295cfce30b5727f96 --- qcom/yupik-pm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi index 5019d0da8c8c..e3d1ff43d709 100644 --- a/qcom/yupik-pm.dtsi +++ b/qcom/yupik-pm.dtsi @@ -44,8 +44,8 @@ entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x1240>; - qcom,psci-mode = <0x124>; + arm,psci-suspend-param = <0x1340>; + qcom,psci-mode = <0x134>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From de5649249b05846dfca0bbbd82ce4d9f6e65ef75 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 20 Oct 2020 11:44:58 -0700 Subject: [PATCH 0183/1809] ARM: dts: msm: Update silver core mitigation for Lahaina Update silver core mitigation in Lahaina to ensure minimum operating performance. Change-Id: I06adfe3bdeddf6f68c013816e408532b44f1afcf --- qcom/lahaina-thermal-overlay.dtsi | 21 --------------------- qcom/lahaina-thermal.dtsi | 24 ------------------------ 2 files changed, 45 deletions(-) diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index 15a3f166fc78..ce48bd0436ae 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -184,12 +184,6 @@ THERMAL_MAX_LIMIT>; }; - pm8350_cpu0_freq { - trip = <&pm8350_trip0>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - pm8350_cpu4_freq { trip = <&pm8350_trip0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT @@ -202,21 +196,6 @@ THERMAL_MAX_LIMIT>; }; - pm8350_cpu1 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm8350_cpu2 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm8350_cpu3 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm8350_cpu4 { trip = <&pm8350_trip0>; cooling-device = <&cpu4_isolate 1 1>; diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 8be59cb4c62e..27210b21b047 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -792,12 +792,6 @@ cooling-device = <&cpu0_isolate 1 1>; }; - cpu00_cdev1 { - trip = <&cpu00_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu00_cdev2 { trip = <&cpu00_config1>; cooling-device = <&cpu0_hotplug 1 1>; @@ -830,12 +824,6 @@ cooling-device = <&cpu1_isolate 1 1>; }; - cpu01_cdev1 { - trip = <&cpu01_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu01_cdev2 { trip = <&cpu01_config1>; cooling-device = <&cpu1_hotplug 1 1>; @@ -868,12 +856,6 @@ cooling-device = <&cpu2_isolate 1 1>; }; - cpu02_cdev1 { - trip = <&cpu02_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu02_cdev2 { trip = <&cpu02_config1>; cooling-device = <&cpu2_hotplug 1 1>; @@ -906,12 +888,6 @@ cooling-device = <&cpu3_isolate 1 1>; }; - cpu03_cdev1 { - trip = <&cpu03_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu03_cdev2 { trip = <&cpu03_config1>; cooling-device = <&cpu3_hotplug 1 1>; From 6dd2c343bfa5eb1a4059f3644b61cca2a2bbf11d Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Fri, 9 Oct 2020 11:46:45 +0530 Subject: [PATCH 0184/1809] ARM: dts: msm: Add v2.1 MTP VM device tree file for Lahaina VM Add v2.1 MTP device tree files, for Lahaina SVM. Change-Id: Iab0595866114801ed11a7f64196ae608919c61a9 --- qcom/Makefile | 3 ++- qcom/lahaina-vm-mtp-v2.1.dts | 10 ++++++++++ qcom/lahaina-vm-mtp-v2.1.dtsi | 1 + qcom/lahaina-vm-v2.dtsi | 7 +++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 qcom/lahaina-vm-mtp-v2.1.dts create mode 100644 qcom/lahaina-vm-mtp-v2.1.dtsi create mode 100644 qcom/lahaina-vm-v2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 212ca73f81f0..462f5883bb27 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -171,7 +171,8 @@ ifeq ($(CONFIG_ARCH_LAHAINA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ lahaina-vm-cdp.dtb \ - lahaina-vm-qrd.dtb + lahaina-vm-qrd.dtb \ + lahaina-vm-mtp-v2.1.dtb endif endif diff --git a/qcom/lahaina-vm-mtp-v2.1.dts b/qcom/lahaina-vm-mtp-v2.1.dts new file mode 100644 index 000000000000..c656317eac0d --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm-v2.dtsi" +#include "lahaina-vm-mtp-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM MTP V2.1"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20108 0>; +}; diff --git a/qcom/lahaina-vm-mtp-v2.1.dtsi b/qcom/lahaina-vm-mtp-v2.1.dtsi new file mode 100644 index 000000000000..2a76b5241e44 --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.1.dtsi @@ -0,0 +1 @@ +#include "lahaina-vm-mtp.dtsi" diff --git a/qcom/lahaina-vm-v2.dtsi b/qcom/lahaina-vm-v2.dtsi new file mode 100644 index 000000000000..6c5494ed784f --- /dev/null +++ b/qcom/lahaina-vm-v2.dtsi @@ -0,0 +1,7 @@ +#include "lahaina-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina VM v2"; + compatible = "qcom,lahaina"; + qcom,msm-id = <415 0x20000>; +}; From 0830671588e12a4936e6938f6584087f3ae69367 Mon Sep 17 00:00:00 2001 From: Niranjan Dumbala Date: Wed, 21 Oct 2020 01:24:51 -0700 Subject: [PATCH 0185/1809] Revert "ARM: dts: msm: disable mem-offline node" This reverts commit 3e7e84fa3cff311ebcae335e1ceff501b47d0e2e. Change-Id: I0a1c2833d095283fb12c9b1eacfe7b02e7160278 --- qcom/holi-regulators.dtsi | 4 +--- qcom/holi.dtsi | 1 - 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index d0913902e2a3..df74687f3251 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -46,11 +46,9 @@ regulator-name = "pm6350_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; - qcom,init-voltage-level = - ; qcom,use-voltage-level; }; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 3a0ebab3e7f2..bd7dd2432165 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -30,7 +30,6 @@ <0x1 0xc0000000 0x0 0x80000000>, <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; - status = "disabled"; }; aliases { From cd5fd8cbf775e4f95f23ee44fe7fef017f776a65 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 20 Oct 2020 18:49:53 +0530 Subject: [PATCH 0186/1809] ARM: dts: qcom: Update skin and cx thermal mitigation config for SHIMA Add quiet-therm skin sensor thermal config for SHIMA with modem, cdsp and gpu as cooling devices based on latest recomondations. Update nspss-2 tsens sensor thermal config mitigation for SHIMA with cdsp, gpu and modem as cooling devices based on latest recomondations. Change-Id: I6a8cf412b80a6d071bd669fafed61aa72ba41b24 --- qcom/shima-qrd.dtsi | 93 ++++++++++++++++++++++++++++++++++++ qcom/shima-thermal.dtsi | 103 +++++++++++++--------------------------- 2 files changed, 126 insertions(+), 70 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index ea9a65cd8f39..3c4d58ff97f2 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -197,6 +197,99 @@ qcom,wireless-fw-name = "idt9412.bin"; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>; + + trips { + quiet_gpu_trip: quiet-gpu-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu4_trip: quiet-cpu4-trip { + temperature = <46000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu7_trip: quiet-cpu7-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu0_trip: quiet-cpu0-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev0 { + trip = <&quiet_gpu_trip>; + /* throttle to 443000000Hz */ + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + gpu-cdev1 { + trip = <&quiet_cx_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpufreq0-cdev { + trip = <&quiet_cpu0_trip>; + /* throttle to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + + cpufreq4-cdev { + trip = <&quiet_cpu4_trip>; + /* throttle to 1651200KHz */ + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cpufreq7-cdev { + trip = <&quiet_cpu7_trip>; + /* throttle to 1862400KHz */ + cooling-device = <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cdsp-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 5 5>; + }; + + modem-pa-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; +}; + &qupv3_se10_i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index abf3371998fc..73aa20666ae0 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1254,18 +1254,12 @@ }; nspss-0-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 3>; trips { - nspss0_trip0: nspss0-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss0_trip1: nspss0-trip1 { + nspss0_trip: nspss0-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1273,49 +1267,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss0_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss0_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss0_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss0_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss0_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-1-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 4>; trips { - nspss1_trip0: nspss1-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss1_trip1: nspss1-trip1 { + nspss1_trip: nspss1-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1323,49 +1305,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss1_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss1_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss1_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss1_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss1_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-2-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 5>; trips { - nspss2_trip0: nspss2-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss2_trip1: nspss2-trip1 { + nspss2_trip: nspss2-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1373,34 +1343,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss2_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss2_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss2_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss2_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss2_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; }; - From 10a6c2d43182f7fb93e3ad13c02d6d10515bc043 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 14:55:15 +0530 Subject: [PATCH 0187/1809] dt-bindings: LLCC: Add compatible property for Yupik Add "qcom,yupik-llcc" compatible property which matches the driver for Yupik platform. Change-Id: Ie95d00496deeab35bfe42c5c4f9b14b9daee70ce --- bindings/arm/msm/qcom,llcc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 9d722dcf4c72..64e1fe37e270 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -13,6 +13,7 @@ Properties: Value type: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" + or "qcom,yupik-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: From a979112191b747d9fa5df3c341721a90dd23918d Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Wed, 21 Oct 2020 18:13:27 +0530 Subject: [PATCH 0188/1809] ARM: dts: msm: Add MPROC device nodes for scuba Add SMEM, TCSR Mutex, Glink and SMP2P devices for enabling interprocessor communication with MPSS, LPASS and RPM. Change-Id: Idaf5abb3a4a3f6f25ff3c219531bfe8985209418 --- qcom/scuba-iot.dtsi | 183 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index c07dcefb4820..bb28d23102ff 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -567,6 +567,189 @@ dcc: dcc_v2@1be2000 { #interrupt-cells = <4>; cell-index = <0>; }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,scuba-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "pm2250.dtsi" From 2a61ae11a60e8436a9154699cb9eb1910a5d5476 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 15:10:49 +0530 Subject: [PATCH 0189/1809] ARM: dts: msm: Add LLCC entry for Yupik Add Last Level Cache Controller (LLCC) device tree node for Yupik. Change-Id: Ic6cda9514922f004dc1f8225c03ed0e3f8150855 --- qcom/yupik.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..080c7c5bd909 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,15 @@ }; }; + cache-controller@9200000 { + compatible = "qcom,yupik-llcc","qcom,llcc-v2"; + reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; + }; + clk_virt: interconnect { compatible = "qcom,yupik-clk_virt"; #interconnect-cells = <1>; From 40a71ca76575c9c2534dd1a1d3369415f321a110 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Fri, 16 Oct 2020 15:24:16 -0400 Subject: [PATCH 0190/1809] ARM: dts: msm: select visionox panel and touch controller for TVM Select visionox default panel and focaltech touch controller for Lahaina MTP V2.1 trusted VM. Change-Id: I78eb1dcbd20c342d1db9857abcb710bb60832e82 --- qcom/lahaina-vm-mtp-v2.1.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-vm-mtp-v2.1.dtsi b/qcom/lahaina-vm-mtp-v2.1.dtsi index 2a76b5241e44..a15cbce6a7d7 100644 --- a/qcom/lahaina-vm-mtp-v2.1.dtsi +++ b/qcom/lahaina-vm-mtp-v2.1.dtsi @@ -1 +1,19 @@ -#include "lahaina-vm-mtp.dtsi" + +&qupv3_se4_i2c { + status = "ok"; + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 0883d0ce61866a3ec7f115729acc8569a2de3212 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 19:33:12 +0530 Subject: [PATCH 0191/1809] ARM: dts: msm: Add ipcc test nodes for Yupik Add IPCC test nodes for adsp, cdsp for Yupik. This allows testing IPCC ping from APPS to these subsystems. Change-Id: Id7a9f5be7d827cf41fbf69d72aa28f4b50c14b79 --- qcom/ipcc-test-yupik.dtsi | 5 +++++ qcom/yupik.dtsi | 1 + 2 files changed, 6 insertions(+) create mode 100644 qcom/ipcc-test-yupik.dtsi diff --git a/qcom/ipcc-test-yupik.dtsi b/qcom/ipcc-test-yupik.dtsi new file mode 100644 index 000000000000..9809b5abf881 --- /dev/null +++ b/qcom/ipcc-test-yupik.dtsi @@ -0,0 +1,5 @@ +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 080c7c5bd909..b12fe24ad080 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -773,6 +773,7 @@ #include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-stub-regulator.dtsi" +#include "ipcc-test-yupik.dtsi" &gcc_pcie_0_gdsc { compatible = "regulator-fixed"; From a986821e2562b51c88ba1be50ca37edec93b3c4f Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 21 Oct 2020 20:53:23 +0530 Subject: [PATCH 0192/1809] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit e506b909ef43f6464f97201f193f2197bc827346. Commit e506b909ef43f6 ("ARM: dts: msm: Use PCIe_MSI for Shima") There is MSI interrupts in PCIe DRV suspend state from device, which caused NOC error when host try to read MSI status register. Change-Id: Ia0393a2005bac508c0b4a43e41341507070ea3cd --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fbe74ebfb44d..32573d6def76 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -194,15 +194,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From 0fe1fb06058644710b63e6b5659b72a522f00382 Mon Sep 17 00:00:00 2001 From: NITHEESH MUTHURAJ Date: Tue, 13 Oct 2020 16:45:17 -0700 Subject: [PATCH 0193/1809] ARM: dts: msm: Add a new power level for supported devices Add speed bin node for efuse check and create speed bins to include TURBO_L2 on supported devices. Change-Id: I9ae248a599d53134b5e7b8a71ad109a34f1dfa0d --- qcom/lahaina-gpu.dtsi | 3 + qcom/lahaina-v2-gpu.dtsi | 435 ++++++++++++++++++++++++++++----------- qcom/lahaina.dtsi | 14 ++ 3 files changed, 330 insertions(+), 122 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 305d9f3b348f..34caf29704f3 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -51,6 +51,9 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 46b86a1604f0..194a286726f2 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -1,173 +1,364 @@ &msm_gpu { qcom,chipid = <0x06060001>; - qcom,initial-pwrlevel = <9>; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; - /* Power levels */ - qcom,gpu-pwrlevels { + /* Power levels bins */ + qcom,gpu-pwrlevel-bins { + compatible="qcom,gpu-pwrlevel-bins"; #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <9>; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <840000000>; - qcom,level = ; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; - qcom,acd-level = <0x882a5ffd>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <778000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <10>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <738000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <676000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <778000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <10>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0x882b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <608000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <738000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <540000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <676000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <9>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <491000000>; - qcom,level = ; + qcom,acd-level = <0x882b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <608000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <443000000>; - qcom,level = ; + qcom,acd-level = <0xa82b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <540000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0xa82d5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <379000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <491000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <6>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882e5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <315000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <2>; - qcom,bus-min-ddr7 = <2>; - qcom,bus-max-ddr7 = <9>; + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <2>; - qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882f5ffd>; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; }; }; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 5a1ef7f0b987..87178b02c004 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5657,6 +5657,20 @@ qcom,use-ap-power-save; status = "disabled"; }; + + qfprom: qfprom@784000 { + compatible = "qcom,qfprom"; + reg = <0x784000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@17b { + reg = <0x17b 0x1>; + bits = <5 3>; + }; + }; }; #include "ipcc-test.dtsi" From e431f8f76936a51a8350e49f3ed1d00bcb6de961 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Wed, 21 Oct 2020 11:20:27 -0700 Subject: [PATCH 0194/1809] ARM: dts: msm: Add usb bam dt node on sdxlemur Add the usb bam related device tree entries on sdxlemur. Change-Id: I238791a84f035091a8ecc80b0a642033ff6feeaa --- qcom/sdxlemur-usb.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a7121b5fd80c..683efa443925 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -63,6 +63,35 @@ dr_mode = "otg"; snps,xhci-imod-value = <4000>; }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x1468b000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; }; usb_nop_phy: usb_nop_phy { From 42f6e16aeb970a8f0e88623d89130c746129ebed Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 19 Oct 2020 14:08:31 -0700 Subject: [PATCH 0195/1809] ARM: dts: msm: move qcom,boot-option to HSP dedicated DTSI for sdxlemur Having qcom,boot-option set to 0x1 on main sdxlemur devicetree prevents other connects from being automatically enumerated. Most connects do not require manual enumeration like Hastings Prime (HSP) does. Therefore, move qcom,boot-option with 0x1 for PCIe to HSP dedicated devicetree. Change-Id: Ib344311c968fc610df474c5eadc693b45eed3dba --- qcom/sdxlemur-cdp.dtsi | 4 ++++ qcom/sdxlemur-mtp-mbb.dtsi | 3 +++ qcom/sdxlemur-pcie.dtsi | 1 - qcom/sdxlemur-rcm-rc.dtsi | 3 +++ 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 0b6dc2969cd6..aad992261b6a 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -11,3 +11,7 @@ &usb { extcon = <&vbus_detect>; }; + +&pcie0 { + qcom,boot-option = <0x1>; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index cc3a833f430e..7b1f8063b8e6 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -3,3 +3,6 @@ }; +&pcie0 { + qcom,boot-option = <0x1>; +}; diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 11ef2356d6b2..df3f98564a8c 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -91,7 +91,6 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>; - qcom,boot-option = <0x1>; qcom,use-19p2mhz-aux-clk; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index cc3a833f430e..7b1f8063b8e6 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -3,3 +3,6 @@ }; +&pcie0 { + qcom,boot-option = <0x1>; +}; From 89ead7ab037685f37d37310f0f56d4521365f689 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 20 Oct 2020 16:38:32 -0700 Subject: [PATCH 0196/1809] ARM: dts: msm: add PCIe AUX clk freq for controller for sdxlemur Replace deprecated PCIe DT entry for PCIe AUX clock controller setting with the correct entry and value. PCIe core controller requires AUX clock to be 16.6MHz for sdxlemur. Change-Id: I2fa8d8c819bfd06f80b2e274f97b282caa90eb70 --- qcom/sdxlemur-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index df3f98564a8c..35e34a9c4b2d 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -91,7 +91,7 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <17>; /* 16.6 MHz */ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From 95191f2f9d09de66cb90629680a88b502194f028 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 09:59:35 +0530 Subject: [PATCH 0197/1809] ARM: dts: msm: Add core hang detection for Yupik Add qcom,core-hang-detect to device tree to enable MSM Core Hang Detection for all cores. Change-Id: I90907ab37a8c90512dd99b36c4f6e7b28ec60d08 --- qcom/yupik.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b12fe24ad080..f3308be53bd5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,15 @@ }; }; + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 + 0x18040058 0x18050058 0x18060058 0x18070058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 + 0x18040060 0x18050060 0x18060060 0x18070060>; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From 373317c434752c7235cca3dba536644d9c342ea6 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 10:19:37 +0530 Subject: [PATCH 0198/1809] ARM: dts: msm: Enable Kryo erp driver for Yupik Add Kryo error reporting device tree node for Yupik SOC. Change-Id: I34247cf9cfe69c3096ce583c4036dc6bc0295832 --- qcom/yupik.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f3308be53bd5..1b351a0b7cf8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -709,6 +709,13 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From 7c7cb1bae557b972bb4b4f495c8d01d7a6fff488 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 10:40:50 +0530 Subject: [PATCH 0199/1809] ARM: dts: msm: Add ARM PMU node for Yupik Add ARM Performance Monitor Unit (PMU) device tree node for Yupik SOC. Change-Id: I8813c4cbaec2a4f58ae1ab48c80c866c4f38c7dc --- qcom/yupik.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 1b351a0b7cf8..386322742738 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,12 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; From 2f8632e5758758c1051040898c328bc4e8fd7f4b Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Thu, 22 Oct 2020 14:28:25 +0800 Subject: [PATCH 0200/1809] ARM: dts: msm: Add cti trigger number to device tree for shima Add cti trigger number to device tree for shima. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I52d53848cf23d25b8b8f5dc2ed6bb6175743d3d8 --- qcom/shima-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index e6b90830fa55..4536aeb7d154 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; From cc20e145aa308a0ea2f767700e2e0c0ab2833f4b Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Mon, 19 Oct 2020 13:37:52 +0800 Subject: [PATCH 0201/1809] ARM: dts: msm: Update masks in codec Fs clock sequence Update masks in codec Fs clock sequence on lahaina target. Change-Id: Ideae266d2c4b1f629dfdd8dbf149e4cae02f102a --- qcom/holi-audio-overlay.dtsi | 4 ++-- qcom/lahaina-audio-overlay.dtsi | 4 ++-- qcom/shima-audio-overlay.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 987572a7db74..acdac6359715 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x0A5640D8>; qcom,va_mclk_mode_muxsel = <0x0A7A0000>; clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index 4908e26696d8..1b50e92a9651 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 5c44652dd529..b47233eb69e5 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -10,8 +10,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; From c6722d8be1374e4088a6d93eb9f1159b981a3eb5 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 22 Oct 2020 21:01:22 +0530 Subject: [PATCH 0202/1809] ARM: dts: msm: Reduce the IOVA range for QUP usecase This change enables SMMU page table memory savings for QUP. No functional change but helps saving memory table space. Change-Id: Ie56582683eb594a1f8c3e6f746e7d7a0691598ef --- qcom/holi-qupv3.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index 530d54e635a3..2d2975b0c717 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -26,7 +26,8 @@ ; qcom,vote-for-bw; iommus = <&apps_smmu 0x0003 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; @@ -190,7 +191,8 @@ ; qcom,vote-for-bw; iommus = <&apps_smmu 0x00c3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; From 0b9756a23eb57a0403194790491df5fe32ce1ebd Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 22 Oct 2020 21:06:38 +0530 Subject: [PATCH 0203/1809] ARM: dts: msm: Reduce the IOVA range for slimbus and QUP usecases This change enables SMMU page table memory savings for qup and slim_aud. No functional change but helps saving memory table space. Change-Id: I094d0a18d6b5a0aab1ab5ac4f05dd183392f2e17 --- qcom/shima-qupv3.dtsi | 6 ++++-- qcom/shima.dtsi | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index aa158a9189e4..a4c05936d55c 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -29,7 +29,8 @@ , ; iommus = <&apps_smmu 0x4c3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; @@ -362,7 +363,8 @@ , ; iommus = <&apps_smmu 0x43 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..71796e666482 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -537,7 +537,8 @@ qcom,apps-ch-pipes = <0x0>; qcom,ea-pc = <0x3d0>; iommus = <&apps_smmu 0x2026 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; From eb33b85feccdd48914a0fee20f4729f75055200d Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 22 Oct 2020 09:18:48 -0700 Subject: [PATCH 0204/1809] ARM: dts: msm: Remove modem tsens QMI thermal zone for Lahaina Modem tsens sensors are directly accessible by APSS. So remove the QMI tsens thermal zones which will not be enabled for Lahaina. Change-Id: I7844ac68c3a723abafa1f43db6a853a98426dbe0 --- qcom/lahaina-thermal-modem.dtsi | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/qcom/lahaina-thermal-modem.dtsi b/qcom/lahaina-thermal-modem.dtsi index c13e66fa1abb..65c9a70346f0 100644 --- a/qcom/lahaina-thermal-modem.dtsi +++ b/qcom/lahaina-thermal-modem.dtsi @@ -292,36 +292,6 @@ }; }; - modem-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_MODEM_TSENS)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - modem-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_MODEM_TSENS_1)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - modem-streamer-usr { polling-delay-passive = <0>; polling-delay = <0>; From bc71a4b4ad7ec85d680e6fe624940b2c5a47da62 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Mon, 19 Oct 2020 12:52:06 -0400 Subject: [PATCH 0205/1809] ARM: dts: msm: add trusted touch support in PVM for Lahaina Add trusted nodes to focaltech touch controller in primary VM. This will allow PVM to enable/disable secure touch when starting/stopping a TUI session. Change-Id: Ia977e8e5269b874a0ad685926d02aa5f3f8054bc --- qcom/lahaina-cdp.dtsi | 6 ++++++ qcom/lahaina-mtp.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index c9b2da960900..4989e97dd77e 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -102,6 +102,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; atmel_mxt_ts@4a { diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index b896ca9f97d0..39f56296aed0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -104,6 +104,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From b7e1214a3f8212c5a6f1f4bc66a41c9b0d4c872b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sun, 18 Oct 2020 22:23:06 +0530 Subject: [PATCH 0206/1809] ARM: dts: qcom: Add quiet-therm thermal zone mitigation for HOLI Add quiet-therm skin thermal zone mitigation rule with gpu, cdsp and modem_skin as cooling devices based on latest recommendations. Change-Id: I25e18a1a693f3107be823ea6dd666084e4f84a2c --- qcom/holi-qrd.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 35c761d75f92..51c11a11dd60 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -320,6 +320,70 @@ 500000>; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; + + trips { + quiet_modem_trip0: quiet-modem-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_modem_trip1: quiet-modem-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_modem_trip2: quiet-modem-trip2 { + temperature = <56000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev { + trip = <&quiet_cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + cdsp-cdev0 { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + modem-skin-cdev0 { + trip = <&quiet_modem_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&quiet_modem_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&quiet_modem_trip2>; + cooling-device = <&modem_skin 3 3>; + }; + }; + }; +}; + &pm7250b_qg { status = "ok"; #io-channel-cells = <1>; From 5415535466cd3423bd59b0854d54f9f42c60c4af Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 17 Sep 2020 21:02:12 +0530 Subject: [PATCH 0207/1809] ARM: dts: msm: Add interconnect bus voting values to Holi Currently the driver has bus voting hard coded. Adding interconnect vote values and interconnect names to do bus voting with dtsi file. Change-Id: I96cd119fdba17b7c46fc8c1642a3c28d44197c14 --- qcom/holi-usb.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index 80ce1db4f91c..cb7ee84ebdc2 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -39,13 +39,21 @@ qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; - qcom,default-bus-vote = <2>; /* use svs bus voting */ interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&system_noc MASTER_USB3_0 &bimc SLAVE_EBI>, <&system_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + qcom,num-gsi-evt-buffs = <0x3>; qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = From 4cbc62a2c324fafb75656c6ab8ce9600c795e7a8 Mon Sep 17 00:00:00 2001 From: Gaurav Singh Date: Tue, 20 Oct 2020 16:58:12 +0530 Subject: [PATCH 0208/1809] ARM: dts: msm: Enable SCMI PLH protocol Enable SCMI PLH protocol for communicating with RIMPS PLH module. Change-Id: I8a2a8f033239580830120b2225f11522c84223fc --- qcom/holi.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 987c74ed483b..76255b11cbca 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1496,6 +1496,10 @@ reg = <0x80>; #clock-cells = <1>; }; + scmi_perf_lock: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; }; rimps_log: qcom,rimps_log@fd04780 { From 438de49b8d28c7128cd0ad8596af8ebc800e543d Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 15 Oct 2020 16:50:08 +0530 Subject: [PATCH 0209/1809] ARM: dts: msm: Change IPA bandwidth threshold value for holi target Change IPA bandwidth threshold value for holi target. Change-Id: I85e67351f544fe0eb6689257e4d15190b454a9cd --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 987c74ed483b..91fc66d6c294 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2658,7 +2658,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <310 600 1000>; + qcom,throughput-threshold = <600 2500 5000>; qcom,scaling-exceptions = <>; /* smp2p information */ From 2176da4f3f2b13302156e4c264ee39a64492425a Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 23 Oct 2020 15:17:11 +0800 Subject: [PATCH 0210/1809] ARM: dts: msm: disable IPA TPDM IPA TPDM is not supported on sdxlemur V1, so disable it. Change-Id: I3c85ebb33630bd07600761e7b1901cb1b342b090 --- qcom/sdxlemur-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index c95b7bfa8bba..2e977b84e52b 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -1015,7 +1015,7 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-ipa"; - + status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; From 4c279b6998d68be58699e9c4556fb7d6b3476ce0 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 23 Oct 2020 13:59:08 +0530 Subject: [PATCH 0211/1809] ARM: dts: msm: add l3 latfloor in shima target Add cpu7-l3 latfloor dcvs node to scale l3 based onthe prime core frequency in shima target. Change-Id: Ia9e1642b9a4fe38ee1c51a0a2da8df8d94d15b7e --- qcom/shima.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..87ec75a4bedb 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2373,6 +2373,16 @@ &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; }; + cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "compute"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -2549,6 +2559,15 @@ qcom,core-dev-table = <&cpu7_cpu_l3_tbl>; }; + cpu7_l3_computemon: qcom,cpu7-l3-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_latfloor>; + qcom,core-dev-table = + < 2169600 300000000 >, + < 2707200 1420800000 >; + }; + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,target-dev = <&cpu0_cpu_llcc_lat>; From 6e9f894884e2a32c2e1e2cc0f17f1cf135160e40 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 23 Oct 2020 14:11:28 +0530 Subject: [PATCH 0212/1809] ARM: dts: msm: Update S2C min voltage for shima Update SMPS regulator S2C's minimum voltage to 550mV to match with corresponding AOP constraint value, for WLAN use case. Change-Id: I4beb27c5691100abdb28ba77e93d384ae10e9714 --- qcom/shima-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index e592f7a5df8e..1dcabd3c06b6 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -382,9 +382,9 @@ pm8350c_s2: regulator-pm8350c-s2 { regulator-name = "pm8350c_s2"; qcom,set = ; - regulator-min-microvolt = <722000>; + regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; - qcom,init-voltage = <722000>; + qcom,init-voltage = <550000>; }; }; From e5ffd6c671beb7d9db5c267a470ba0703670c3d1 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 24 Sep 2020 12:20:26 +0530 Subject: [PATCH 0213/1809] ARM: dts: msm: Add eMMC, SD card support for sdxlemur Add eMMC/SD card support for sdxlemur. Change-Id: If86007c079cf36382b65515976a3e82e9c6eba8f --- qcom/sdxlemur-cdp.dtsi | 18 ++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 28 ++++++++++++ qcom/sdxlemur-mtp.dtsi | 18 ++++++++ qcom/sdxlemur-pinctrl.dtsi | 92 ++++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 28 ++++++++++++ 5 files changed, 184 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index aad992261b6a..6b6ff3fc2a0c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -8,6 +8,24 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &usb { extcon = <&vbus_detect>; }; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7b1f8063b8e6..00c959d6e75b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -6,3 +6,31 @@ &pcie0 { qcom,boot-option = <0x1>; }; + +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 0b6dc2969cd6..7213eb337afb 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -8,6 +8,24 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &usb { extcon = <&vbus_detect>; }; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index ef506863a580..7acc8527e1b9 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -40,6 +40,98 @@ }; }; + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio99"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio99"; + bias-disable; + drive-strength = <2>; + }; + }; + pcie0 { pcie0_clkreq_default: pcie0_clkreq_default { mux { diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a3294e016f86..4bbf2a3f6d1e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -432,6 +432,34 @@ status = "disabled"; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + status = "disabled"; + + qos0 { + mask = <0x1>; + vote = <44>; + }; + }; + apsscc: clock-controller@17808100 { compatible = "qcom,sdxlemur-apsscc"; clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>; From 1959266810774ec04abc9dd8ad56a961ce5bd0d2 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 23 Oct 2020 13:19:48 -0700 Subject: [PATCH 0214/1809] ARM: dts: msm: add PCIe AUX CLK freq entry for PCIe0 and PCIe1 for lahaina Have both PCIe0 and PCIe1 explicitly program their respective controller PCIe AUX CLK frequency setting with 19.2MHz on lahaina. Change-Id: If1c2508f64aa2167d93d99d0248cfbd3d8ce27b6 --- qcom/lahaina-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index f15c2e4eda1b..9c106f0bd059 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -100,6 +100,7 @@ <0x100 &apps_smmu 0x1c01 0x1>; qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <5000>; @@ -328,6 +329,7 @@ <0x100 &apps_smmu 0x1c81 0x1>; qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,drv-supported; qcom,wr-halt-size = <0x8>; qcom,no-l0s-supported; From bb67dd74828bfb20334913bdc51e37d5447ef3b5 Mon Sep 17 00:00:00 2001 From: Nadav Levintov Date: Mon, 26 Oct 2020 19:12:33 +0200 Subject: [PATCH 0215/1809] ARM: dts: msm: Increase MHI event rings number for SDXLEMUR Add support for two additional MHI event rings Change-Id: If7bd16c49293773a7de5679a41dcdcb26c7c6a54 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..8f01c252c531 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -788,7 +788,7 @@ qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; qcom,use-ipa-tethering-bridge; - qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ + qcom,mhi-event-ring-id-limits = <9 15>; /* start and end */ qcom,modem-cfg-emb-pipe-flt; qcom,use-xbl-boot; qcom,arm-smmu; From 697814b394b15dc53eb52fbaec9e2d811fdbce0f Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 27 Oct 2020 11:06:42 +0800 Subject: [PATCH 0216/1809] ARM: dts: msm: Add cti trigger number to device tree for lahaina Add cti trigger number to device tree for lahaina. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I5ae1cc25210218f249ea8b34ee493e0b27fef237 --- qcom/lahaina-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index 3342e9e9e0f5..ff7750e6f034 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; From c9a7ad232a9ea6df4312d2ba8a702d3ae0d8d4bf Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 27 Oct 2020 11:15:45 +0800 Subject: [PATCH 0217/1809] ARM: dts: msm: Add cti trigger number to device tree for holi Add cti trigger number to device tree for holi. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: Ibb96b02f966c765f8744a278bb6b6f18da2edd4c --- qcom/holi-coresight.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 95a7723749e2..817a8365d552 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1959,6 +1959,9 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <5>; + cti-flush-trig-num = <1>; + in-ports { port { tmc_etf_in_funnel_merge: endpoint { @@ -2039,6 +2042,8 @@ qcom,sw-usb; coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <5>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; interrupts = ; interrupt-names = "byte-cntr-irq"; From a949b458eaaf0afa4d2eaa1faf8c8f5a11607902 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Tue, 27 Oct 2020 11:59:33 +0530 Subject: [PATCH 0218/1809] ARM: dts: msm: Add slimbus dtsi node for scuba Add slimbus dtsi node for scuba. Change-Id: I0ea801a7ac0fb697d45a32c015aeb32036eee864 --- qcom/scuba-iot.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index bb28d23102ff..7ea545d63717 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -750,6 +750,21 @@ dcc: dcc_v2@1be2000 { #interrupt-cells = <2>; }; }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical","slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x360>; + status = "ok"; + }; }; #include "pm2250.dtsi" From 44150e9089d3d119d79189f479f9ae60d5541707 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Fri, 23 Oct 2020 14:51:18 +0530 Subject: [PATCH 0219/1809] ARM: dts: msm: Set emmc vdd-io regulator in NPM mode during sleep Set emmc vdd-io regulator in NPM mode during sleep to avoid OCP issue. This is done only for ATP platform. Change-Id: I32573627314dff29ef67d3bf3a8337c17f87d4db --- qcom/holi-atp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index e16ecfc75980..974b08da18ae 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -21,7 +21,7 @@ qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; + qcom,vdd-io-current-level = <325000 325000>; }; &sdhc_2 { From 0bfa3e7d2065a1a5a03d4b48e09cac5570acf160 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Tue, 20 Oct 2020 00:04:37 +0530 Subject: [PATCH 0220/1809] ARM: dts: qcom: add physical addr for swr tx slaves of Holi Add dt property to read physical addresses of TX soundwire master slaves of Holi. Change-Id: Id584ba30e2e62230dfb77f75958b7239b77a652f --- qcom/holi-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 987572a7db74..238ccb951cd9 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -55,6 +55,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <1>; + qcom,swr-phy-dev-addr = <0x0A 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; qcom,is-always-on = <1>; From e7a7ffd220373eef563f7d54ec5b4e4a1c7a6d42 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Tue, 27 Oct 2020 10:07:28 -0700 Subject: [PATCH 0221/1809] ARM: dts: msm: Configure USB SMMU in atomic mode on sdxlemur Enable usb smmu in atomic mode by configuring the device tree setting on sdxlemur. Change-Id: Id5745e605eb242b1cb829e04de7bcb66af1958d0 --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 683efa443925..007c96f3e20f 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -7,7 +7,7 @@ reg-names = "core_base"; iommus = <&apps_smmu 0x1a0 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; From ca2905c68e0fbdd43536c6905f562f02f90b7b2a Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:27:56 -0700 Subject: [PATCH 0222/1809] dt-bindings: arm: msm: add MX entries for PCIe There are chipsets which require explicit votes for MX rails and its corners based on PCIe Gen speed. Add a entries for MX in DT so PCIe bus driver can properly vote and scale corners for MX. Change-Id: Ib7891ab528594f4f8a81568daafbe6297fcb60be --- bindings/pci/pci-msm.txt | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 8a9fa1e1c6fe..8d64a0fc0b9c 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -123,6 +123,7 @@ Main node - "vreg-1.8-supply" power supply for PCIe PHY - "vreg-0.9-supply" power supply for PCIe PHY - "vreg-cx-supply" power supply for PCIe core + - "vreg-mx-supply" power supply for PCIe core/PHY - "vreg-3.3-supply" (opt) power supply for PCIe endpoint - qcom,-voltage-level: @@ -134,8 +135,10 @@ Main node - qcom,bw-scale: Usage: optional Value type: - Definition: List of CX voltage corner and rate change clock frequency - pair for each PCIe GEN speed + Definition: Tuple consisting of CX and MX voltage corners, and rate + change clock frequencies for each supported PCIe Gen speed. + ex: + <[min CX voltage] [min MX voltage] [Rate change clk frequency]> interconnect-names: Usage: optional @@ -461,14 +464,30 @@ Example vreg-1.8-supply = <&pm8150l_l3>; vreg-0.9-supply = <&pm8150_l5>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; vreg-3.3-supply = <&pm8150_l1>; qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; qcom,vreg-0.9-voltage-level = <950000 950000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; /* Gen3 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From c64a98fe4e5df1407f156119c449db750a2716dc Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:39:06 -0700 Subject: [PATCH 0223/1809] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on lahaina Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on lahaina does not need to explicitly vote for MX, updates to lahaina PCIe DT nodes are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for both PCIe nodes on lahaina. Change-Id: If707f61f78e4d99df118ebbfb516d639e5b4f851 --- qcom/lahaina-pcie.dtsi | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..c72e6031377f 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; @@ -284,10 +292,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 99000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; From d2ee6936a7cd5b083152847f2939bb43bf3b68c9 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 11:25:58 -0700 Subject: [PATCH 0224/1809] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on shima does not need to explicitly vote for MX, updates to shima PCIe DT node are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for PCIe on shima. Change-Id: I4b93b92ee8e401c554e17e769432d3c22998ad98 --- qcom/shima-pcie.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..eb3c0f409669 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From 0bd22990a564dd5b7da3c8087a8f91ea663ba253 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 18 Aug 2020 17:55:30 +0530 Subject: [PATCH 0225/1809] ARM: dts: msm: add smmu nodes on yupik Add SMMU device tree nodes, which is used by the clients for virtual to physical address transaltions, on yupik. Change-Id: Ia88dc0e18b530e364314f8468022519dd5dcf5e2 --- qcom/msm-arm-smmu-yupik.dtsi | 246 +++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 5 + 2 files changed, 251 insertions(+) create mode 100644 qcom/msm-arm-smmu-yupik.dtsi diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi new file mode 100644 index 000000000000..22ee8245eb6e --- /dev/null +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -0,0 +1,246 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0x3da0000 0x20000>, + <0x3dd6000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dd9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dd9000 0x1000>, + <0x3dd6200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@3ddd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3ddd000 0x1000>, + <0x3dd6208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151da000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_tbu: anoc_1_tbu@151dd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151dd000 0x1000>, + <0x151da200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + anoc_2_tbu: anoc_2_tbu@151e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e1000 0x1000>, + <0x151da208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e5000 0x1000>, + <0x151da210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e9000 0x1000>, + <0x151da218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@151ed000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151ed000 0x1000>, + <0x151da220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f1000 0x1000>, + <0x151da228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + }; + + adsp_tbu: adsp_tbu@151f5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f5000 0x1000>, + <0x151da230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f9000 0x1000>, + <0x151da238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151fd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151fd000 0x1000>, + <0x151da240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + }; + }; + + kgsl_iommu_test_device { + status = "disabled"; + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + qcom,iommu-dma = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + status = "disabled"; + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x407 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x0 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x1 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c07780c7eed8..f76e4684ff16 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1140,6 +1140,10 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; }; #include "shima-gdsc.dtsi" @@ -1264,3 +1268,4 @@ }; #include "yupik-usb.dtsi" +#include "msm-arm-smmu-yupik.dtsi" From a574bcce71ec80aab53f1907c538743ad27dc0ec Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 23 Oct 2020 17:02:28 +0800 Subject: [PATCH 0226/1809] dt-bindings: arm: Add reset/flush CTI trigger number support Add binding document for configuring reset/flush CTI trigger number in device tree. Change-Id: I4052810ab6b31fb336d5d75bc88f349892fdf050 --- bindings/arm/coresight.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 1fadc1b562cc..8b5ff04914a5 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -137,6 +137,12 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * cti-reset-trig-num: Specifies the reset CTI trigger number for TMC + ETR and TMC ETF. + + * cti-flush-trig-num: Specifies the flush CTI trigger number for TMC + ETR and TMC ETF. + * Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address error for CATU and four interrupts for TGU to get trigger from four From ae7e54c0587be49920fa337dddee5f9c5811150f Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 28 Oct 2020 16:09:32 +0530 Subject: [PATCH 0227/1809] ARM: dts: msm: Add change for smmu memory optimizations This change enables smmu memory optimizations during smmu s1 enable for holi. Change-Id: Ie921ffd9b8df91474563d5171ad22df333a87a46 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a44459a09fe8..34fd9f97a15b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2569,6 +2569,7 @@ qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; vdd-cx-mx-supply = <&L4A>; vdd-1.8-xo-supply = <&L7A>; vdd-1.3-rfa-supply = <&L2E>; From f954a0cb57ae3307d0ea94047dab473a5345c012 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 22 Oct 2020 15:57:45 -0700 Subject: [PATCH 0228/1809] ARM: dts: msm: Add PMIC overlay to all sdxlemur platforms Add PMIC overlay to the board files of the complete range of sdxlemur platforms. Change-Id: Id7926f1b8c8cd77442f1afc3777bf7436ef95af8 --- qcom/sdxlemur-mtp-cpe.dtsi | 1 + qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-rcm-pcie-ep.dtsi | 1 + qcom/sdxlemur-rcm-rc.dtsi | 1 + 6 files changed, 6 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7b1f8063b8e6..7bfdc0e951d3 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7b1f8063b8e6..7bfdc0e951d3 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { From 826180ecb6bcce2522cabe0026a231218ad4da06 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 22 Oct 2020 16:48:30 -0700 Subject: [PATCH 0229/1809] ARM: dts: msm: Add PM7250B to select sdxlemur boards Add PM7250B to MBB and RCM-RC boards. Change-Id: I5ea24325a31c6ed89b1f90f12a332ba26d7ffc17 --- qcom/sdxlemur-mtp-mbb.dtsi | 6 ++++++ qcom/sdxlemur-rcm-rc.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7bfdc0e951d3..7e5f6471cab7 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,4 +1,10 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; &soc { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7bfdc0e951d3..7e5f6471cab7 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,4 +1,10 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; &soc { From f9297920c0014b5cafa095b040273ea7c8afde98 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 29 Oct 2020 11:58:40 +0530 Subject: [PATCH 0230/1809] ARM: dts: msm: Remove touch vote for L8C on shima L8C is always on regulator on shima platform. Touch driver currently votes for L8C leading to leakage. So, remove touch vote for L8C. Change-Id: Icf3c2f0a2b62e82b2784b52c7b35ea2406e59b02 --- qcom/shima-idp.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index b02db7983bda..fa083f6b556f 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -178,7 +178,6 @@ focaltech,display-coords = <0 0 1080 2340>; vdd-supply = <&L3C>; - vcc_i2c-supply = <&L8C>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; pinctrl-0 = <&ts_active>; From 504fe96b700c5f96007e5a0fc214073029f9eda7 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Mon, 21 Sep 2020 12:38:24 +0530 Subject: [PATCH 0231/1809] ARM: dts: msm: Add QUPv3_0 and SE5 dt nodes for YUPIK Add QUPv3_0 device tree change for console UART on yupik. Change-Id: I9d0af197eda7c784aea127a5cc8848674d3c81fa --- qcom/yupik-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ qcom/yupik-qupv3.dtsi | 35 +++++++++++++++++++++++++++++++++++ qcom/yupik-rumi.dtsi | 5 +++++ qcom/yupik.dtsi | 1 + 4 files changed, 69 insertions(+) create mode 100644 qcom/yupik-qupv3.dtsi diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index baa6f7f738b5..01404eb41ded 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -8,5 +8,33 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { + qupv3_se5_2uart_active: qupv3_se5_2uart_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup05"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi new file mode 100644 index 000000000000..a593d4406eda --- /dev/null +++ b/qcom/yupik-qupv3.dtsi @@ -0,0 +1,35 @@ +#include + +&soc { + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x9c0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x123 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se5_2uart: qcom,qup_uart@994000 { + compatible = "qcom,msm-geni-console"; + reg = <0x994000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_2uart_active>; + pinctrl-1 = <&qupv3_se5_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "ok"; + }; +}; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index a7544916452f..1efb6b32bfaa 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -70,3 +70,8 @@ status = "ok"; }; + +/* Debug UART console */ +&qupv3_se5_2uart { + qcom,rumi_platform; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f76e4684ff16..8b749d15d51f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1269,3 +1269,4 @@ #include "yupik-usb.dtsi" #include "msm-arm-smmu-yupik.dtsi" +#include "yupik-qupv3.dtsi" From 713fb502ade8fc525bc0477e20c3aaf76fb4d83f Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 8 Oct 2020 16:38:04 +0530 Subject: [PATCH 0232/1809] Revert "ARM: dts: msm: Add new DT entry for wan agg pkt size" This reverts commit 8bfb55bada068d97584c93ed9a95322f0df9720a. Change-Id: Ia33a38ba96893ca6c08d27c0f40852256b474aca --- qcom/shima.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..4ff893da146a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3725,8 +3725,6 @@ qcom,ipa-holb-monitor-max-cnt-usb = <10>; qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; - /* Entry will be removed once shadow stack changes checked-in */ - qcom,ipa-wan-aggr-pkt-cnt = <2>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From 3561926fd4d5c7f7508edae10a2a622ce1998da6 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 29 Oct 2020 17:52:42 +0530 Subject: [PATCH 0233/1809] ARM: dts: msm: Add vdd parent supply for holi GPU Add vdd parent supply for holi GPU to vote it from gfx driver during GPU wakeup and collapse sequence. Change-Id: I6de177b8c1e9e89a8bfe0123f4f3d51a084a983a --- bindings/gpu/adreno.txt | 4 ++++ qcom/holi-gpu.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index de91a4ee875e..12de7124472c 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -66,6 +66,8 @@ GDSC Oxili Regulators: - regulator-names: List of regulator name strings sorted in power-on order - vddcx-supply: Phandle for vddcx regulator device node. - vdd-supply: Phandle for vdd regulator device node. +- vdd-parent-supply: Phandle for vdd parent regulator device node. +- vdd-parent-min-corner: Minimum voltage corner value to set vdd parent supply. IOMMU Data: - iommu: Phandle for the KGSL IOMMU device node @@ -355,6 +357,8 @@ Example of A330 GPU in MSM8916: /* GDSC oxili regulators */ vdd-supply = <&gdsc_oxili_gx>; + vdd-parent-supply = <&VDD_GFX_LEVEL>; + vdd-parent-min-corner = ; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index c0728369bff4..d18c1771c956 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -1,3 +1,5 @@ +#include + #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) &soc { pil_gpu: qcom,kgsl-hyp { @@ -30,6 +32,8 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; + vdd-parent-supply = <&VDD_GFX_LEVEL>; + vdd-parent-min-corner = ; qcom,chipid = <0x06010900>; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; From 7a3fc916988500b12cc25e51ef5b12b06e1fc0bb Mon Sep 17 00:00:00 2001 From: Siddartha Mohanadoss Date: Thu, 29 Oct 2020 13:13:20 -0700 Subject: [PATCH 0234/1809] ARM: dts: msm: Add bindings for PCIe end point driver Add initial bindings for PCIe end point driver and MHI device end point. Change-Id: I67a969b21de5eebc7b2fcc6a715d2d9baee4929f --- bindings/msm_mhi_dev.txt | 63 +++++++++++++++ bindings/pci/msm_ep_pcie.txt | 153 +++++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+) create mode 100644 bindings/msm_mhi_dev.txt create mode 100644 bindings/pci/msm_ep_pcie.txt diff --git a/bindings/msm_mhi_dev.txt b/bindings/msm_mhi_dev.txt new file mode 100644 index 000000000000..c46a176a2615 --- /dev/null +++ b/bindings/msm_mhi_dev.txt @@ -0,0 +1,63 @@ +MSM MHI DEV + +MSM MHI DEV enables communication with the host over a PCIe link using the +Modem Host Interface protocol. The driver interfaces with the IPA for +enabling the HW acceleration channel path and provides interface for +software channels to communicate between Host and device. + +Required properties: + - compatible: should be "qcom,msm-mhi-dev" for MHI device driver. + - reg: MHI MMIO physical register space. + - reg-names: resource names used for the MHI MMIO physical address region, + IPA uC command and event ring doorbell mail box address. + Should be "mhi_mmio_base" for MHI MMIO physical address, + "ipa_uc_mbox_crdb" for IPA uC Command Ring doorbell, + "ipa_uc_mbox_erdb" for IPA uC Event Ring doorbell passed to + the IPA driver. + - qcom,mhi-ifc-id: ID of HW interface via which MHI on device side + communicates with host side. + - qcom,mhi-ep-msi: End point MSI number. + - qcom,mhi-version: MHI specification version supported by the device. + +Optional property: + - qcom,use-ipa-software-channel: If property is present use IPA hardware + accelerated path for MHI software channel data transfers + between host and device. + - qcom,mhi-config-iatu: If property is present map the control and data region + between host and device using iatu. + - qcom,mhi-interrupt: If property is present register for mhi interrupt. + - qcom,mhi-local-pa-base: The physical base address on the device used by the + MHI device driver to map the control and data region with the + MHI driver on the host. This property is required if iatu + property qcom,mhi-config-iatu is present. + - qcom,enable-m2: If property is present M2 autonomous is enabled. + +MSM MHI DEV NET + +MSM MHI DEV enables communication with the host over a PCIe link using the +Network Interface. + +Required properties: + - compatible: should be "qcom,msm-mhi-dev-net" for MHI net device driver. + +Optional property: + - qcom,mhi-ethernet-interface;: If property is present use ethernet packet + parsing support. + +Example: + mhi: qcom,msm-mhi-dev { + compatible = "qcom,msm-mhi-dev"; + reg = <0xfc527000 0x1000>, + <0xfd4fa000 0x1>, + <0xfd4fa080 0x1>; + reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", + "ipa_uc_mbox_erdb"; + qcom,mhi-ifc-id = <0x030017cb>; + qcom,mhi-ep-msi = <1>; + qcom,mhi-version = <0x1000000>; + }; + + qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + qcom,mhi-ethernet-interface; + }; diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt new file mode 100644 index 000000000000..c364f472cc0b --- /dev/null +++ b/bindings/pci/msm_ep_pcie.txt @@ -0,0 +1,153 @@ +MSM PCI express endpoint + +Required properties: + - compatible: should be "qcom,pcie-ep". + - reg: should contain PCIe register maps. + - reg-names: indicates various resources passed to driver by name. + Should be "msi", "dm_core", "elbi", "parf", "phy", "mmio", + "tcsr_pcie_perst_en". + These correspond to different modules within the PCIe domain. + - #address-cells: Should provide a value of 0. + - interrupt-parent: Should be the PCIe device node itself here. + - interrupts: Should be in the format <0 1 2> and it is an index to the + interrupt-map that contains PCIe related interrupts. + - #interrupt-cells: Should provide a value of 1. + - #interrupt-map-mask: should provide a value of 0xffffffff. + - interrupt-map: Must create mapping for the number of interrupts + that are defined in above interrupts property. + For PCIe device node, it should define 6 mappings for + the corresponding PCIe interrupts supporting the + specification. + - interrupt-names: indicates interrupts passed to driver by name. + Should be "int_pm_turnoff", "int_dstate_change", + "int_l1sub_timeout", "int_link_up", + "int_link_down", "int_bridge_flush_n". + - perst-gpio: PERST GPIO specified by PCIe spec. + - wake-gpio: WAKE GPIO specified by PCIe spec. + - clkreq-gpio: CLKREQ GPIO specified by PCIe spec. + - -supply: phandle to the regulator device tree node. + Refer to the schematics for the corresponding voltage regulators. + vreg-1.8-supply: phandle to the analog supply for the PCIe controller. + vreg-0.9-supply: phandle to the analog supply for the PCIe controller. + +Optional Properties: + - qcom,-voltage-level: specifies voltage levels for supply. + Should be specified in pairs (max, min, optimal), units uV. + - clock-names: list of names of clock inputs. + Should be "pcie_pipe_clk", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_ldo"; + - max-clock-frequency-hz: list of the maximum operating frequencies stored + in the same order of clock names; + - resets: reset specifier pair consists of phandle for the reset controller + and reset lines used by this controller. + - reset-names: reset signal names sorted in the same order as the property + of resets. + - qcom,pcie-phy-ver: version of PCIe PHY. + - qcom,phy-init: The initialization sequence to bring up the PCIe PHY. + Should be specified in groups (offset, value, delay, direction). + - qcom,phy-status-reg: Register offset for PHY status. + - qcom,phy-status-reg2: For sdxprairie and above use only + qcom,phy-status-reg2 as register offset for PHY status. + - qcom,dbi-base-reg: Register offset for DBI base address. + - qcom,slv-space-reg: Register offset for slave address space size. + - qcom,pcie-vendor-id: Vendor id to be written to the Vendor ID register. + - qcom,pcie-device-id: Device id to be written to the Device ID register. + - qcom,pcie-link-speed: generation of PCIe link speed. The value could be + 1, 2 or 3. + - qcom,pcie-active-config: boolean type; active configuration of PCIe + addressing. + - qcom,pcie-edma: boolean type; edma usage for PCIe. + - qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated. + - qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq. + - qcom,pcie-perst-enum: Link enumeration will be triggered by PERST + deassertion. + - qcom,tcsr-not-supported: TCSR pcie perst is not supported. + - mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side. + - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for + below optional properties: + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode. + - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset. + +Example: + + pcie_ep: qcom,pcie@bfffd000 { + compatible = "qcom,pcie-ep"; + + reg = <0xbfffd000 0x1000>, + <0xbfffe000 0x1000>, + <0xbffff000 0x1000>, + <0xfc520000 0x2000>, + <0xfc526000 0x1000>, + <0xfc527000 0x1000>, + <0x01fcb000 0x1000>; + + reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio", + "tcsr_pcie_perst"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0 1 2 3 4 5>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 44 0 + 1 &intc 0 46 0 + 2 &intc 0 47 0 + 3 &intc 0 50 0 + 4 &intc 0 51 0 + 5 &intc 0 52 0>; + interrupt-names = "int_pm_turnoff", "int_dstate_change", + "int_l1sub_timeout", "int_link_up", + "int_link_down", "int_bridge_flush_n"; + + perst-gpio = <&msmgpio 65 0>; + wake-gpio = <&msmgpio 61 0>; + clkreq-gpio = <&msmgpio 64 0>; + mdm2apstatus-gpio = <&tlmm_pinmux 16 0>; + + gdsc-vdd-supply = <&gdsc_pcie_0>; + vreg-1.8-supply = <&pmd9635_l8>; + vreg-0.9-supply = <&pmd9635_l4>; + + qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; + qcom,vreg-0.9-voltage-level = <950000 950000 24000>; + + clock-names = "pcie_pipe_clk", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_ldo"; + max-clock-frequency-hz = <62500000>, <1000000>, + <0>, <0>, <0>, <0>; + + resets = <&clock_gcc GCC_PCIE_BCR>, + <&clock_gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", "pcie_phy_reset"; + + qcom,msm-bus,name = "pcie-ep"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + qcom,pcie-link-speed = <1>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,pcie-perst-enum; + qcom,phy-status-reg = <0x728>; + qcom,dbi-base-reg = <0x168>; + qcom,slv-space-reg = <0x16c>; + + qcom,phy-init = <0x604 0x03 0x0 0x1 + 0x048 0x08 0x0 0x1 + 0x64c 0x4d 0x0 0x1 + 0x600 0x00 0x0 0x1 + 0x608 0x03 0x0 0x1>; + }; From 12d8efb1bcdfcee57b78fd26dbae88998229bdac Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 27 Oct 2020 15:03:42 +0530 Subject: [PATCH 0235/1809] ARM: dts: msm: add system ion heaps on yupik Add the system and system secure ion heaps on yupik. Change-Id: Icb1b6ebfbb92627b411d8404f60c4d101dba5ffa --- qcom/yupik-ion.dtsi | 20 ++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 21 insertions(+) create mode 100644 qcom/yupik-ion.dtsi diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi new file mode 100644 index 000000000000..c10aa1385e0e --- /dev/null +++ b/qcom/yupik-ion.dtsi @@ -0,0 +1,20 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f76e4684ff16..decd47425e54 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1268,4 +1268,5 @@ }; #include "yupik-usb.dtsi" +#include "yupik-ion.dtsi" #include "msm-arm-smmu-yupik.dtsi" From 3d0a4b8de232f6b0c765f76e2285d4731f1e7e44 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 16 Oct 2020 11:19:06 +0530 Subject: [PATCH 0236/1809] ARM: dts: msm: Update regulator S3A for holi Set the min_voltage of S3A to collapse and set always-wait-for-ack property to follow HW recommendation. Change-Id: I4d01d650b2acaf124d18ee775abae0b5bfad54e5 --- qcom/holi-regulators.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index df74687f3251..69c448d82979 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -26,6 +26,7 @@ status = "okay"; qcom,resource-name = "rwgx"; qcom,resource-id = <0>; + qcom,always-wait-for-ack; VDD_GFX_LEVEL: S3A_LEVEL: pm6350_s3_level: regulator-s3-level { compatible = "qcom,rpm-smd-regulator"; @@ -46,7 +47,7 @@ regulator-name = "pm6350_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; qcom,use-voltage-level; From a72b061a3b34a29f7d66afad8588e028f0185187 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Fri, 30 Oct 2020 15:42:04 +0530 Subject: [PATCH 0237/1809] ARM: dts: msm: Update PCIe LDO clock from CXO to CXO_A LDO votes CXO clock in WLAN IMPS mode which causes CXO clock is always turned on, So changing PCIe LDO clock from CXO to CXO_A. Change-Id: I6b0ad98be2017e58e133751baa3febd69c77e83d --- qcom/shima-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..fce90dee366f 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -67,7 +67,7 @@ <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, From ccdcabbb381169377b87ee77b20bfe7ddf9c71ef Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 28 Oct 2020 17:21:50 +0800 Subject: [PATCH 0238/1809] ARM: dts: msm: disable GPU funnel The GPU funnel related clk cannot be voted on from kernel side, so disable it. Change-Id: I82914c8f9d37187943854822cac50b77df4632a7 --- qcom/holi-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 817a8365d552..75f31bf5d45e 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1134,7 +1134,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; - + status = "disabled"; out-ports { port { funnel_gpu_out_tpda_center2: endpoint { From 26695258093b6eacba9ed761c3a8edb96411fa9c Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 21 Oct 2020 23:17:22 +0530 Subject: [PATCH 0239/1809] ARM: dts: qcom: Enable TSENS driver support for sdxlemur Enable TSENS devicetree details and user_space thermal zone configurations for all TSENS for sdxlemur. Change-Id: I992d4836cccc1d30cfb6fd2c9887a4083729c868 --- qcom/sdxlemur-thermal.dtsi | 155 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 156 insertions(+) create mode 100644 qcom/sdxlemur-thermal.dtsi diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi new file mode 100644 index 000000000000..3aed3255d650 --- /dev/null +++ b/qcom/sdxlemur-thermal.dtsi @@ -0,0 +1,155 @@ +&soc { + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x152>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; +}; + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmq6-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..b89428868f9a 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -921,3 +921,4 @@ #include "sdxlemur-pcie.dtsi" #include "sdxlemur-blsp.dtsi" #include "sdxlemur-audio.dtsi" +#include "sdxlemur-thermal.dtsi" From 846a2721e68bfb0b6aa6a2ea98f8bda8ffd7e5fe Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Tue, 13 Oct 2020 11:11:32 +0800 Subject: [PATCH 0240/1809] bindings: qcom-hv-haptics: add properties to support non-HBoost regulator Haptics module can be configured to get power from non-HBoost regulator, add properties to specify the regulator device and voltage level. Change-Id: I8aea15c812c2e7cb5e45df90d5c2464582867bc6 --- bindings/input/qcom-hv-haptics.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bindings/input/qcom-hv-haptics.txt b/bindings/input/qcom-hv-haptics.txt index 128e9266baac..805b3baedf70 100644 --- a/bindings/input/qcom-hv-haptics.txt +++ b/bindings/input/qcom-hv-haptics.txt @@ -119,6 +119,20 @@ Properties: haptics ISC (short circuit current) config during LRA impedance detection. +- qcom,hpwr-supply: + Usage: optional + Value type: + Definition: Phandle of the regulator device that supplies power for haptics + module. This is needed when haptics module is supplied by + non-HBoost regulator. + +- qcom,hpwr-voltage-mv: + Usage: optional + Value type: + Definition: Specify the voltage level in mv unit requested from the + non-HBoost regulator. When BoB regulator is used, the + requested voltage shouldn't be higher than 4000 mV. + The following properties are only required when LRA actuator is used: - qcom,lra-period-us: From eb3c1b3847a5c0e806249c77f5bf3bd5f9fa2f53 Mon Sep 17 00:00:00 2001 From: Srinivas Rao L Date: Fri, 30 Oct 2020 20:38:31 +0530 Subject: [PATCH 0241/1809] ARM: dts: msm: Add Wakeup interrupt controller for scuba-iot Add wakeup interrupt controller node to support wakeup- capabale interrupts. Change-Id: Ibf4edc60adcdbeaf976cfb2eb97e689978d099d2 --- bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/scuba-iot.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index 1d5997bfb61c..257f2a7da9fc 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -24,6 +24,7 @@ Properties: Definition: Should contain "qcom,mpm-gic" and the respective target compatible flag from below ones. "qcom,mpm-gic-holi" + "qcom,mpm-gic-scuba" - interrupts: Usage: required diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 7ea545d63717..b9cb3f478e69 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -276,6 +276,17 @@ interrupts = <1 9 4>; }; + wakegic: wake-gic { + compatible = "qcom,mpm-gic-scuba", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; timer { compatible = "arm,armv8-timer"; From 55d3df1c6075665b6e9feb65d648edcd575d4614 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Oct 2020 15:32:48 +0530 Subject: [PATCH 0242/1809] ARM: dts: msm: Add acd registers for HOLI The GPU GX GDSC requires the ACD block/misc resets during GDSC power-up/down sequence, thus add the register offsets. Change-Id: Ica77fa0a270186ecdbafb4e8d0888ef0b81613bf --- qcom/holi-gdsc.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/holi-gdsc.dtsi b/qcom/holi-gdsc.dtsi index 5e2346aab191..14ad80e17363 100644 --- a/qcom/holi-gdsc.dtsi +++ b/qcom/holi-gdsc.dtsi @@ -97,6 +97,16 @@ reg = <0x5991008 0x4>; }; + gpu_gx_acd_reset: syscon@5991160 { + compatible = "syscon"; + reg = <0x5991160 0x4>; + }; + + gpu_gx_acd_misc_reset: syscon@5998004 { + compatible = "syscon"; + reg = <0x5998004 0x4>; + }; + gpu_cx_gdsc: qcom,gdsc@599106c { compatible = "qcom,gdsc"; reg = <0x599106c 0x4>; @@ -113,6 +123,8 @@ reg = <0x599100c 0x4>; regulator-name = "gpu_gx_gdsc"; sw-reset = <&gpu_gx_sw_reset>; + acd-reset = <&gpu_gx_acd_reset>; + acd-misc-reset = <&gpu_gx_acd_misc_reset>; domain-addr = <&gpu_gx_domain_addr>; qcom,reset-aon-logic; status = "disabled"; From 7c14214d5c229abde58166d42c1a439f5995fa5a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 2 Nov 2020 22:12:33 +0530 Subject: [PATCH 0243/1809] ARM: dts: msm: Add missing changes to shima-atp dtsi Add ATP target specific changes to take care booting on Shima ATP platform. Change-Id: I13a0e8492510dc963bf34d9d997ae91865f40a42 --- qcom/shima-atp.dtsi | 210 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 1 deletion(-) diff --git a/qcom/shima-atp.dtsi b/qcom/shima-atp.dtsi index 6ae9ea2b9643..3fc75973a822 100644 --- a/qcom/shima-atp.dtsi +++ b/qcom/shima-atp.dtsi @@ -1,4 +1,212 @@ -#include "shima-idp.dtsi" +#include +#include +#include "shima-pmic-overlay.dtsi" +#include "display/shima-sde-display-idp.dtsi" +#include "shima-thermal-overlay.dtsi" +#include "shima-audio-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 87 0x00>; + qcom,sn-ven = <&tlmm 62 0x00>; + qcom,sn-firm = <&tlmm 86 0x00>; + qcom,sn-clkreq = <&tlmm 63 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <87 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&S10B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 30000>; + + cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97100>; + vdda-pll-max-microamp = <19600>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2960000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + vccq2-supply = <&S10B>; + vccq2-voltage-level = <1800000 1800000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <10000>; + + status = "ok"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350b_haptics { + status = "ok"; +}; + +&pm8350c_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8350c_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8350c_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8350c_flash { + status = "ok"; +}; + +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; +}; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + focaltech,reset-gpio = <&tlmm 22 0x00>; + focaltech,irq-gpio = <&tlmm 23 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L3C>; + vcc_i2c-supply = <&L8C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +&dai_mi2s2 { + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; +}; &pm8008i_chip { status = "disabled"; From 323a118d1d50f3dd133d2849f3218509265bf0c0 Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Mon, 2 Nov 2020 15:33:37 -0800 Subject: [PATCH 0244/1809] ARM: dts: msm: Keep default PM level setting for Lahaina The default settings are rpm-level = spm-level = 3. This translates to UFS_SLEEP_PWR_MODE & UIC_LINK_HIBERN8_STATE. Change-Id: I9c08875d193fbefe0846f53e8b95dd6e840485de --- qcom/lahaina.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 5a1ef7f0b987..692570e8d2bf 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3148,9 +3148,6 @@ qcom,iommu-dma = "fastmap"; dma-coherent; - rpm-level = <3>; - spm-level = <5>; - status = "disabled"; qos0 { mask = <0xf0>; From 71f731976857104ebdec4c7cc42ada08d05eb3e0 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 28 Oct 2020 12:59:31 -0700 Subject: [PATCH 0245/1809] ARM: dts: qcom: Added msm-id entry for single-die sdxlemur Added an entry for sdxlemur single-die to allow for dt detection to work properly. Change-Id: I6bae742d0530e71967cf01f1629106b6e5dc76fe --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..25323f80bd29 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -16,7 +16,7 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR"; compatible = "qcom,sdxlemur"; - qcom,msm-id = <458 0x10000>; + qcom,msm-id = <458 0x10000>, <483 0x10000>; interrupt-parent = <&intc>; aliases { From 2c849413fa52991c25dbb38ea6f10644fc42aaed Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Mon, 2 Nov 2020 16:20:26 -0800 Subject: [PATCH 0246/1809] ARM: dts: msm: Disable dma-coherent for IPA CBs on SDXLEMUR DMA coherent is not required for MDM target. Change-Id: I9c115bbab9bdecc5573dbc2a264faff7da5f9e77 --- qcom/sdxlemur.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 06dcaf8c5ba6..e76f65c09b46 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -750,7 +750,6 @@ qcom,additional-mapping = /* modem tables in IMEM */ <0x14688000 0x14688000 0x3000>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,ipa-q6-smem-size = <36864>; }; @@ -758,7 +757,6 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x5E1 0x0>; - dma-coherent; qcom,iommu-dma = "atomic"; }; @@ -772,7 +770,6 @@ ipa_smmu_11ad: ipa_smmu_11ad { compatible = "qcom,ipa-smmu-11ad-cb"; iommus = <&apps_smmu 0x5E3 0x0>; - dma-coherent; qcom,shared-cb; qcom,iommu-group = <>; }; From 973e31a21325835c2d263b80094d1f2afa0ae6f5 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Tue, 3 Nov 2020 12:05:34 +0530 Subject: [PATCH 0247/1809] Revert "ARM: dts: msm: enable mem_offline.bypass_send_msg for holi" This reverts commit a0fb9e8113ceaab3e5576fb6bf3fd951ea5986fc. Change-Id: Ie81129defd4fa5b91fb0043fe9f2644dde5f8173 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a44459a09fe8..b8c90d19d456 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -448,7 +448,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1 kpti=off"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; }; From f12c2970e81baf3916d155b6f0b676476b2f8610 Mon Sep 17 00:00:00 2001 From: Sridhar Arra Date: Tue, 3 Nov 2020 14:46:43 +0530 Subject: [PATCH 0248/1809] ARM: dts: msm: Add rmtfs_sharedmem support for scuba-iot Add shared memory support to enable rmt_storage service in userspace that allows other processor to access the primary storage device to store its data. Change-Id: I019faa2b75b937fc56fbc7819de61e54a618e70c --- qcom/scuba-iot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 7ea545d63717..cd431074d371 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -421,6 +421,14 @@ status="disabled"; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; From 75d2c9ac76ef682404f1f3f4cb73007d0d4639e4 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 23 Oct 2020 16:16:35 +0530 Subject: [PATCH 0249/1809] ARM: dts: msm: Add CX and MX SDPM configuration for SHIMA Add CX SDPM configuration to monitor Camera, UFS clocks for SHIMA. Add MX SDPM configuration to monitor Camera, Video, and other misc clocks for SHIMA. Change-Id: I2d38c7d48cf4b05198f924dccb7b2858d679e6a6 --- qcom/shima-thermal.dtsi | 146 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 73aa20666ae0..25d67c087505 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -64,6 +64,44 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "video_cc_mvs0"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + csr-id = <1 3>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; + csr-id = <0 2 5>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &cpufreq_hw { @@ -1366,4 +1404,112 @@ }; }; }; + + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_1 { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_2 { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_3 { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config5: cx-pe-config5 { + temperature = <5>; + hysteresis = <2>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config5>; + cooling-device = <&cdsp_sw 0 0>; + }; + }; + }; }; From 5e679a8be0020455b6b8a0d34dd82c1bd9173729 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 3 Nov 2020 17:50:55 +0530 Subject: [PATCH 0250/1809] ARM: dts: msm: Add configuration for vref regulator vote for SHIMA Add regulator configuration for vref regulators so that LMH driver can place a active only vote for shima. Change-Id: I67ffdf7cac820ddcc81b901d4652c4f44aa8fdaf --- qcom/shima-thermal.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 25d67c087505..0568cabd69b5 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -191,6 +191,14 @@ }; }; + qcom,limits-dcvs { + compatible = "qcom,msm-hw-limits"; + isens_vref_0p8-supply = <&pm8350c_l10_ao>; + isens-vref-0p8-settings = <880000 880000 30000>; + isens_vref_1p8-supply = <&pm8350c_l1_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; + qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; apc1_cluster: qcom,apc1-cluster { From 91c737ada2aa41881e124c95cb16364abc37232f Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 12:06:50 +0530 Subject: [PATCH 0251/1809] ARM: dts: msm: Add cphy video/cmd mode touch support on shima Add cphy video/cmd mode touch support on shima target. Change-Id: I7a089bc246b428c79adb3e09cf94c357e8447a65 --- qcom/shima-idp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index b02db7983bda..61ac7628134b 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -189,7 +189,9 @@ &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video &dsi_r66451_amoled_60hz_cmd - &dsi_r66451_amoled_144hz_cmd>; + &dsi_r66451_amoled_144hz_cmd + &dsi_r66451_amoled_video_cphy + &dsi_r66451_amoled_cmd_cphy>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 2432f0dd54d19ff6bb2287ce20037431cf85e50f Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 15 Oct 2020 13:57:29 +0530 Subject: [PATCH 0252/1809] ARM: dts: msm: Enable touch for Dual DSI panel on shima Enable touch for Dual DSI panel on shima. Change-Id: Icb198d7831b1932b199c0e680af0f32c72f0913f --- qcom/shima-idp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 61ac7628134b..9b4e69e21615 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -199,6 +199,27 @@ focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; + + atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + avdd-supply = <&L3C>; + vdd-supply = <&L8C>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + atmel,xy_switch; + atmel,inverty; + atmel,invertx; + reset-gpios = <&tlmm 22 0x00>; + irq-gpios = <&tlmm 23 0x2008>; + atmel,panel-coords = <0 0 479 799>; + atmel,display-coords = <0 0 339 729>; + panel = <&dsi_sharp_qhd_plus_dsc_cmd>; + }; }; &dai_mi2s2 { From 20787497c82c6d6319956d597d55f332f1c2611c Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Tue, 3 Nov 2020 23:08:08 +0530 Subject: [PATCH 0253/1809] ARM: dts: msm: Correct GCC clocks for UART instances This change will map Correct GCC clocks for UART nodes Change-Id: I4fdf9000369eca411fd05329760939d2503bd720 --- qcom/sdxlemur-blsp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi index 997db6b37078..56965fd69013 100644 --- a/qcom/sdxlemur-blsp.dtsi +++ b/qcom/sdxlemur-blsp.dtsi @@ -385,7 +385,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART2_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2a_tx_sleep>, <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; @@ -421,7 +421,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART2_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>, <&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>; @@ -457,7 +457,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART3_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_tx_sleep>, <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; @@ -493,7 +493,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART4_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4a_tx_sleep>, <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; @@ -529,7 +529,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART4_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4b_tx_sleep>, <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; From af3f5c76a2e0a37138edcb7f30a72c3125765f75 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 3 Nov 2020 15:06:28 -0800 Subject: [PATCH 0254/1809] dt-bindings: Add DDR cooling device Add DDR cooling device to vote for DDR frequency. Change-Id: Id719cb06ec6dafdff21281391e5fa3d475c83910 --- bindings/thermal/qti-ddr-cdev.txt | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/thermal/qti-ddr-cdev.txt diff --git a/bindings/thermal/qti-ddr-cdev.txt b/bindings/thermal/qti-ddr-cdev.txt new file mode 100644 index 000000000000..c081531b11d5 --- /dev/null +++ b/bindings/thermal/qti-ddr-cdev.txt @@ -0,0 +1,42 @@ +QTI DDR cooling device. + +The DDR cooling device will be used to place a DDR frequency vote. This +cooling device will be used in those cases where all the subsystem's are +thermally throttled and DDR has to be operated with a minimum performance +level. This cooling device vote can ensure the same. + +Properties: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,ddr-cooling-device" + +Cooling device node: +- qcom,ddr-freq: + Usage: required + Value type: + Definition: List of available DDR frequencies. + +-#cooling-cells: + Usage: required + Value type: + Definition: Must be 2. Needed for of_thermal as cooling device + identifier. Please refer to + for more + details. +Example: + qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + qcom,ddr-freq = <200000>, + <451000>, + <547000>, + <681000>, + <768000>, + <1017000>, + <1555000>, + <1708000>, + <2092000>, + <2736000>, + <3196000>; + #cooling-cells = <2>; + }; From 63edf5ee3512a2ddf3b67b6cb5d1dcd52eee3aea Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Wed, 4 Nov 2020 11:53:41 +0800 Subject: [PATCH 0255/1809] ARM: dts: msm: Add cti trig_out gpio for shima Add pinctil setting to cti trig_out gpio and configure trig_out gpio for shima. Change-Id: Ief2bcf78e1c8f423020d5aab1de416cbdfa72f43 --- qcom/shima-coresight.dtsi | 4 ++++ qcom/shima-pinctrl.dtsi | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 4536aeb7d154..90cccf9a0f3b 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -3129,6 +3129,10 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <0>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; }; cti3: cti@6013000 { diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index eeb47a49d145..5e2c03340973 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -3109,6 +3109,19 @@ bias-pull-down; }; }; + + trigout_a: trigout_a { + mux { + pins = "gpio14"; + function = "qdss_cti"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; }; }; From 68591d577880af21d196b8c0db04b4073d3c81d1 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 4 Nov 2020 12:41:48 +0800 Subject: [PATCH 0256/1809] ARM: dts: msm: adjust pm6150a_l1 initial voltage for Holi platforms Set pm6150a_l1 initial voltage to 1.8V by default and set it to 1.86V specific for Holi QRD platform to meet the display panel power requirement. Change-Id: I19beed5a3025a3e96653a4762ab8c2d73b7a0068 --- qcom/holi-qrd.dtsi | 4 ++++ qcom/holi-regulators.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 51c11a11dd60..5811c29a8d04 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -232,6 +232,10 @@ }; }; +&pm6150a_l1 { + qcom,init-voltage = <1860000>; +}; + &pm6150a_amoled { status = "ok"; }; diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index df74687f3251..1e5ef3a2bf65 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -459,7 +459,7 @@ L1E: pm6150a_l1: regulator-l1 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1650000>; + qcom,init-voltage = <1800000>; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <62000>; status = "okay"; From a6f0ab4b2b89d54eafeb11add144e8785710a248 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Wed, 4 Nov 2020 13:59:34 +0800 Subject: [PATCH 0257/1809] ARM: dts: msm: Add GPU mitigation rules for Lahaina QRD Add gpu-skin-avg sensor thermal zone mitigation rule with gpu based on the latest recommendation. Change-Id: I4186f2d0c6fd6aa37f7eabf117b063b0c4891448 --- qcom/lahaina-qrd-common.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 935146de871d..692d5fa395b6 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -347,3 +347,28 @@ &pm8350c_flash { status = "ok"; }; + +&thermal_zones { + gpu-skin-avg-step { + polling-delay-passive = <5000>; + polling-delay = <1000>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 1>, <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + sensor-aggregation = ; + coefficients = <3 7 0>; + trips { + gpuss_skin_config: active-config0 { + temperature = <570000>; + hysteresis = <20000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss_skin_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT 5>; + }; + }; + }; +}; From 2119a3172365bd50422d43aca7fe35a0e2564a6f Mon Sep 17 00:00:00 2001 From: nishant chaubey Date: Wed, 4 Nov 2020 15:18:45 +0530 Subject: [PATCH 0258/1809] ARM: dts: msm: Add vmid cdsprpc-smd for Holi Smmu fault occurs due to dynamically changing the VMID of nested context after attach. Change-Id: I32fe8759f1363747c69a8b1ee0ccb23cbcfaec9e --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a44459a09fe8..954926d03da6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1984,6 +1984,7 @@ iommus = <&apps_smmu 0x1009 0x0000>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; qcom,msm_fastrpc_compute_cb10 { From 054bc305fdee46943d04f4e9082dc162d9e50ef7 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 3 Nov 2020 15:07:09 -0800 Subject: [PATCH 0259/1809] ARM: dts: msm: Add DDR cooling device for Lahaina Add DDR cooling device for Lahaina to vote for DDR bandwidth when the DDR temp reaches 90C. Change-Id: I83106de17b587e5b59f0a8b7cd1fe1dad5af15b2 --- qcom/lahaina-thermal.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 27210b21b047..fb753c87f2dd 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -53,6 +53,25 @@ reg = <0x00635000 0x1000>; interrupts = ; }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,ddr-freq = <762000>, + <1720000>, + <2086000>, + <2597000>, + <2929000>, + <3879000>, + <5161000>, + <5931000>, + <6515000>, + <7980000>, + <8136000>, + <10437000>, + <12191000>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; }; &cpufreq_hw { @@ -751,7 +770,7 @@ thermal-governor = "step_wise"; trips { pop_trip: pop-trip { - temperature = <95000>; + temperature = <90000>; hysteresis = <0>; type = "passive"; }; @@ -764,6 +783,11 @@ <&apc1_cluster THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; + + pop_cdev1 { + trip = <&pop_trip>; + cooling-device = <&ddr_cdev 5 5>; + }; }; }; From c18494f849778f9c1890caa34e5ec513e60a74ba Mon Sep 17 00:00:00 2001 From: Ankur Bansal Date: Tue, 3 Nov 2020 09:06:22 +0530 Subject: [PATCH 0260/1809] ARM: dts: msm: Add DCC register list for holi Add DCC register list to support DCC register dump for Holi SOC. Change-Id: Ib97094105c612dacdacc6eac0bfa4dd511d3ccc7 --- qcom/holi.dtsi | 490 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 490 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 34fd9f97a15b..729b6f6cd5ba 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1583,6 +1583,496 @@ qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x6000>; + + link_list1 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; qcom,smp2p-modem { From 7d6bd23993c66a7cee4447ba4616a675896139b0 Mon Sep 17 00:00:00 2001 From: Rajeshwar Kurapaty Date: Thu, 5 Nov 2020 12:02:46 +0530 Subject: [PATCH 0261/1809] ARM: dts: msm: Add secure display heap configuration for Yupik Add secure display heap configuration to enable secure memory allocations for secure display/camera usecases. Change-Id: I27132f3b1d85458fc9dc77d4969a42c5aa29ad09 --- qcom/yupik-ion.dtsi | 6 ++++++ qcom/yupik.dtsi | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index c10aa1385e0e..a79bbd58abf5 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -15,6 +15,12 @@ reg = ; qcom,ion-heap-type = "SYSTEM_SECURE"; }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be693f53cd92..cc04ff320e6e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -322,6 +322,14 @@ reg = <0x0 0xc0000000 0x0 0x5100000>; }; + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From de3737da8d0cb56674babddf863c613a58661c3b Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 5 Nov 2020 13:28:59 +0530 Subject: [PATCH 0262/1809] ARM: dts: msm: Update the rpm-smd node with correct IRQ for holi Update the rpm-smd node with proper glink-rpm irq so that rpm driver can mask the glink-rpm interrupt while going to APSS deep sleep. Change-Id: I1823ce98a2c1cd0586a2f68d1610edae5bb2f0d7 --- qcom/holi.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a44459a09fe8..0c94a4b8af41 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -979,7 +979,10 @@ rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; - interrupts = ; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; From 66008f5ae6e4b60671114d35ab558e7787471f0b Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Thu, 5 Nov 2020 16:08:32 +0530 Subject: [PATCH 0263/1809] ARM: dts: msm: Add dmips and dynamic power co-efficient for Yupik Add capacity-dmips-mhz and dynamic power coefficient for Yupik, these are used by Energy aware scheduler for taskplacement decisions. Change-Id: I922e56d3df8f9c1cfb40ab8cfd77366375875006 --- qcom/yupik.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be693f53cd92..fe0bc64891df 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -63,6 +63,8 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -82,6 +84,8 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -96,6 +100,8 @@ reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -110,6 +116,8 @@ reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -124,6 +132,8 @@ reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -138,6 +148,8 @@ reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -152,6 +164,8 @@ reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -166,6 +180,8 @@ reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1985>; + dynamic-power-coefficient = <552>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; From 9613ee1fc9b14f8cb42e35d7affdf0ad0c82eea2 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 5 Nov 2020 16:09:39 +0530 Subject: [PATCH 0264/1809] ARM: dts: qcom: Add MicroUSB support for Holi For MicroUSB connector, charger driver takes care of notifying connect/disconnect to USB driver. Add charger extcon phandle to support MicroUSB on Holi. Change-Id: I3a2b314ba43265447ecceee26965e9d7ee123d90 --- qcom/holi-atp.dtsi | 2 +- qcom/holi-cdp.dtsi | 2 +- qcom/holi-mtp-usbc.dtsi | 2 +- qcom/holi-mtp.dtsi | 2 +- qcom/holi-qrd.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index 974b08da18ae..92cb1097aa6a 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -295,7 +295,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 7cbc0ae32d3c..413aed3a2660 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -306,7 +306,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index 4793aaa24948..7c454128af97 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -394,7 +394,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 77dcb6330af0..74fd9e74591b 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -375,7 +375,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 5811c29a8d04..776be0b0286c 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -465,7 +465,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; From 68019dd2fca102fe0be9b31c8880a3a7aba3f668 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 2 Nov 2020 18:37:30 -0800 Subject: [PATCH 0265/1809] ARM: dts: qcom: Add entries for power off/downlaod mode driver Revised entries to enable power off/download mode driver. Change-Id: I32f27f9125b73ecf5ee1bd345e5cbfe2aa0742ba --- qcom/sdxlemur-pmic-overlay.dtsi | 8 ++++++++ qcom/sdxlemur.dtsi | 7 ++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 67d96971500f..ea528c0ccbbf 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -208,3 +208,11 @@ }; }; }; + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..9a7a9657f507 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -172,11 +172,8 @@ }; }; - restart_pshold: restart@c264000 { - compatible = "qcom,pshold"; - reg = <0xc264000 0x4>, - <0x1fd3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; + dload_mode { + compatible = "qcom,dload-mode"; }; dcc: dcc_v2@117f000 { From 478799800f64151a6f866e20da712eebbb71fdb6 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:01:53 -0800 Subject: [PATCH 0266/1809] dt-bindings: Document the qcom,power-always-on property for SMMU devices Document the qcom,power-always-on property for SMMU devices. This property specifies that the votes for power resources for an SMMU should always be maintained. Change-Id: I854e07b65d93ed78f9d3e270149d28ef6b599039 --- bindings/iommu/arm,smmu.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 9e3e515e4e96..29e79cddee88 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -182,6 +182,13 @@ conditions. that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). +- qcom,power-always-on: + Boolean property which indicates that votes for power + resources (i.e. regulators, clocks, buses) should + always be maintained. This is required when the latency + for the SMMU's operation is greatly increased by adding and + removing votes for power resources. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : From 573cab957be2a46a86f112117364e47cad59d0b5 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:05:28 -0800 Subject: [PATCH 0267/1809] ARM: dts: msm: Enable qcom,power-always-on for GPU SMMUs on GKI targets The IOMMU page table management code is not optimal from a performance perspective in the GKI configuration, relative to the downstream implementation. When the GPU enters slumber, and requests the SMMU driver to unmap memory from the stage 1 page tables of the GPU. When unmapping memory, the SMMU driver must access the GPU SMMU's register space, so it must vote for power resources to access the TLB invalidation registers. When the GPU is in slumber, there aren't votes for the GPU SMMU's power resources, so the SMMU driver constantly ends up enabling/disabling the power resources, which takes a considerable amount of time. When paired with the suboptimal IOMMU page table management code, this leads to performance issues where the time taken to unmap memory is large. Thus, for all targets that support GKI, add the qcom,power-always-on property for the GPU SMMUs of these targets, to remove the latency incurred by having to enable/disable power resources in the GKI configuration. Change-Id: Id3237214e44c008871d01ec6652b08c4fb24e41c --- qcom/msm-arm-smmu-holi.dtsi | 1 + qcom/msm-arm-smmu-lahaina.dtsi | 1 + qcom/msm-arm-smmu-shima.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 20343e67832b..0b7fb0427195 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -7,6 +7,7 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index de6054d5d612..f373834017d1 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cc_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index c9c71235d746..4867686e4486 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; From 1200a3cad8998b053edf79d58865aaed8d369721 Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Mon, 12 Oct 2020 13:10:22 +0530 Subject: [PATCH 0268/1809] bindings: qcom-pmic-gpio: Add PMD9650 binding Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible string for PMD9650. Change-Id: Iaf8e830475bb362613e7bf8e9ff0838475ed8e64 --- bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index d506c20b8a13..84611b5347f5 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -33,6 +33,7 @@ PMIC's from Qualcomm. "qcom,pm6350-gpio" "qcom,pm6150l-gpio" "qcom,pmx65-gpio" + "qcom,pmd9650-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -120,6 +121,7 @@ to specify in a pin configuration subnode: gpio1-gpio9 for pm6350 gpio1-gpio12 for pm6150l gpio1-gpio16 for pmx65 + gpio1-gpio12 for pmd9650 - function: Usage: required From e867fe5513ddc53d5e2dfa21a039853b8e65d26c Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 6 Nov 2020 09:34:28 +0530 Subject: [PATCH 0269/1809] bindings: mproc: Add support for sm8150 mailbox string Update bindings of mailbox for sm8150 device. Change-Id: If9cae50e126a5c95e936c9bbe3a5a72598ccb314 --- bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/mailbox/qcom,apcs-kpss-global.txt b/bindings/mailbox/qcom,apcs-kpss-global.txt index 833c68a150c1..49702be69c3d 100644 --- a/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -19,6 +19,7 @@ platforms. "qcom,sdxlemur-apcs-gcc" "qcom,scuba-apcs-hmss-global" "qcom,monaco-apcs-hmss-global" + "qcom,sm8150-spcs-global" - reg: Usage: required From 8043b126f8931a3f9488c52007d3b93c20fdb2ed Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 20 Jul 2020 14:38:31 +0530 Subject: [PATCH 0270/1809] ARM: dts: msm: Add S3 die_temp channel for scuba Add S3 die_temp ADC channel node on PM2250 for scuba to read the S3 rail temperature. Change-Id: Ib23488190ec96b9cebecacb663b7064958f7e7df --- qcom/pm2250.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index c7125e133d60..f9b8bb82e9a0 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -146,6 +146,13 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + die_temp_s3 { + reg = ; + label = "die_temp_s3"; + qcom,pre-scaling = <1 3>; + qcom,scale-fn-type = ; + }; }; From d5331b4fde5535ab00124129dd483e7afcc7975d Mon Sep 17 00:00:00 2001 From: Niranjan Dumbala Date: Thu, 5 Nov 2020 22:49:10 -0800 Subject: [PATCH 0271/1809] Revert "ARM: dts: msm: Enable SCMI PLH protocol" This reverts commit 4cbc62a2c324fafb75656c6ab8ce9600c795e7a8. Change-Id: I3098ddec46f845042e5233869d8fe92312c2e02f --- qcom/holi.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 76255b11cbca..987c74ed483b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1496,10 +1496,6 @@ reg = <0x80>; #clock-cells = <1>; }; - scmi_perf_lock: protocol@81 { - reg = <0x81>; - #clock-cells = <1>; - }; }; rimps_log: qcom,rimps_log@fd04780 { From 67548697a558b33f3a360dcc1e1dd3574241a52e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 5 Nov 2020 11:08:34 -0800 Subject: [PATCH 0272/1809] dt-bindings: arm: msm: support tuning of PCIe EQ preset request vector Add DT entry to determine which preset is requested and evaluated in EQ master phase. Change-Id: Ica7c91fcda99e47cd93bb40a7ffc75f4cfb22b92 --- bindings/pci/pci-msm.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 8a9fa1e1c6fe..6c6285f4e714 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -346,6 +346,12 @@ interconnects: Definition: The latency(ms) between when PCIe link is up and before any device over the switch is accessed +- qcom,eq-pset-req-vec: + Usage: optional + Definition: EQ preset request vector. Determines which preset is + requested and evauluated during initial part of the EQ master + phase. Default will be 0 if entry is not present. + - qcom,core-preset: Usage: optional Definition: Determines how aggressive the PCIe PHY equalization is for @@ -522,6 +528,7 @@ Example qcom,ep-latency = <20>; qcom,switch-latency = <25>; + qcom,eq-pset-req-vec = <0>; qcom,core-preset = <0x55555555> /* short channel */ qcom,pcie-phy-ver = <0x2101>; /* v2 version 1.01 */ qcom,phy-status-offset = <0x814>; From b2df6be531a67723951411b0d843830628ba1ce0 Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Fri, 6 Nov 2020 10:34:59 -0800 Subject: [PATCH 0273/1809] ARM: dts: msm: Reorganize the apps_rsc node for Lahaina Move the 'apps_rsc' node to the beginning of the 'soc' node such that the rpmh-regulator devices are populated early in the boot process. As many consumers' probe depend on these regulator devices, placing 'apps_rsc' at the beginning would satisfy the consumer devices as soon as they are populated later in the boot. This way, the drivers no longer have to wait for the regulator devices to be populated, thus optimizing the boot performance. Change-Id: I11f15e625a3383c2936dddab0014a99e940d1c1b --- qcom/lahaina.dtsi | 62 +++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 0d190c4bc15a..2612800e8e4c 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -565,6 +565,37 @@ method = "smc"; }; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + system_pm { + compatible = "qcom,system-pm"; + }; + + clock_rpmh: qcom,rpmhclk { + compatible = "qcom,lahaina-rpmh-clk"; + #clock-cells = <1>; + }; + }; + slim_aud: slim@3ac0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; @@ -2771,37 +2802,6 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x18200000 0x10000>, - <0x18210000 0x10000>, - <0x18220000 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - - system_pm { - compatible = "qcom,system-pm"; - }; - - clock_rpmh: qcom,rpmhclk { - compatible = "qcom,lahaina-rpmh-clk"; - #clock-cells = <1>; - }; - }; - aggre1_noc: interconnect@16e0000 { compatible = "qcom,lahaina-aggre1_noc"; reg = <0x016E0000 0x1f180>; From 77481a38e012bb384a392c32dca364b89dd48916 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Sun, 8 Nov 2020 10:47:31 -0800 Subject: [PATCH 0274/1809] ARM: dts: msm: correct PCIe regulator labels for sdxlemur Mismatch PCIe regulator labels in devicetree is preventing PCIe driver from getting proper handles and info to set voltage and enable regulators. Correct the PCIe regulator labels for sdxlemur. Change-Id: Ia784cbb83cf464f8f5eb14d5e18fb0ece3e34277 --- qcom/sdxlemur-pcie.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 35e34a9c4b2d..2ea8fedc36bb 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -43,11 +43,11 @@ &pcie0_wake_default>; gdsc-vdd-supply = <&gcc_pcie_gdsc>; - vreg-1.8-supply = <&pmx65_l1>; - vreg-0.9-supply = <&pmx65_l4>; + vreg-1p8-supply = <&pmx65_l1>; + vreg-0p9-supply = <&pmx65_l4>; vreg-cx-supply = <&VDD_CX_LEVEL>; - qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>; - qcom,vreg-0.9-voltage-level = <912000 912000 132000>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; + qcom,vreg-0p9-voltage-level = <912000 912000 132000>; qcom,vreg-cx-voltage-level = ; qcom,bw-scale = From 55e31902c107a3f34bdcadad449755bdc36d8ab6 Mon Sep 17 00:00:00 2001 From: Gaurav Singh Date: Tue, 20 Oct 2020 16:58:12 +0530 Subject: [PATCH 0275/1809] ARM: dts: msm: Enable SCMI PLH protocol Enable SCMI PLH protocol for communicating with RIMPS PLH module Change-Id: I74c7a67101314462b591aa3f970780f7a81e566e --- qcom/holi.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 34fd9f97a15b..cf66057384fe 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1496,6 +1496,10 @@ reg = <0x80>; #clock-cells = <1>; }; + scmi_perf_lock: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; }; rimps_log: qcom,rimps_log@fd04780 { From 052a2b3eaa972d78040fe8504435778d9d86acb5 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 29 Oct 2020 17:52:42 +0530 Subject: [PATCH 0276/1809] ARM: dts: msm: Add vdd parent supply for holi GPU Add vdd parent supply for holi GPU to vote it from gfx driver during GPU wakeup and collapse sequence. Change-Id: I6de177b8c1e9e89a8bfe0123f4f3d51a084a983a --- bindings/gpu/adreno.txt | 4 ++++ qcom/holi-gpu.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index de91a4ee875e..12de7124472c 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -66,6 +66,8 @@ GDSC Oxili Regulators: - regulator-names: List of regulator name strings sorted in power-on order - vddcx-supply: Phandle for vddcx regulator device node. - vdd-supply: Phandle for vdd regulator device node. +- vdd-parent-supply: Phandle for vdd parent regulator device node. +- vdd-parent-min-corner: Minimum voltage corner value to set vdd parent supply. IOMMU Data: - iommu: Phandle for the KGSL IOMMU device node @@ -355,6 +357,8 @@ Example of A330 GPU in MSM8916: /* GDSC oxili regulators */ vdd-supply = <&gdsc_oxili_gx>; + vdd-parent-supply = <&VDD_GFX_LEVEL>; + vdd-parent-min-corner = ; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index c0728369bff4..d18c1771c956 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -1,3 +1,5 @@ +#include + #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) &soc { pil_gpu: qcom,kgsl-hyp { @@ -30,6 +32,8 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; + vdd-parent-supply = <&VDD_GFX_LEVEL>; + vdd-parent-min-corner = ; qcom,chipid = <0x06010900>; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; From ff5b0ffc1def1582cdcc29ec3ce6b7628bc15c4c Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 16 Oct 2020 11:19:06 +0530 Subject: [PATCH 0277/1809] ARM: dts: msm: Update regulator S3A for holi Set the min_voltage of S3A to collapse and set always-wait-for-ack property to follow HW recommendation. Change-Id: I4d01d650b2acaf124d18ee775abae0b5bfad54e5 --- qcom/holi-regulators.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index 1e5ef3a2bf65..d52be021a107 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -26,6 +26,7 @@ status = "okay"; qcom,resource-name = "rwgx"; qcom,resource-id = <0>; + qcom,always-wait-for-ack; VDD_GFX_LEVEL: S3A_LEVEL: pm6350_s3_level: regulator-s3-level { compatible = "qcom,rpm-smd-regulator"; @@ -46,7 +47,7 @@ regulator-name = "pm6350_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; qcom,use-voltage-level; From 1b7b06d24747532d70d94f7a0b1802e445494e0f Mon Sep 17 00:00:00 2001 From: Ankur Bansal Date: Tue, 3 Nov 2020 09:06:22 +0530 Subject: [PATCH 0278/1809] ARM: dts: msm: Add DCC register list for holi Add DCC register list to support DCC register dump for Holi SOC. Change-Id: Ib97094105c612dacdacc6eac0bfa4dd511d3ccc7 --- qcom/holi.dtsi | 490 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 490 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index cf66057384fe..25f8b9134b21 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1587,6 +1587,496 @@ qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x6000>; + + link_list1 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; qcom,smp2p-modem { From faf772ccd4b7a51cddd84de761d0ccda3ef6f011 Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Fri, 30 Oct 2020 13:37:20 -0700 Subject: [PATCH 0279/1809] ARM: dts: msm: Add v2 MTP VM device tree file for lahaina VM Add support for MTP v2 for lahaina SVM. Change-Id: I7ccfd86b8f15e9233bc76ed9286b12f3239d20a6 --- qcom/Makefile | 1 + qcom/lahaina-vm-mtp-v2.dts | 10 ++++++++++ qcom/lahaina-vm-mtp-v2.dtsi | 1 + 3 files changed, 12 insertions(+) create mode 100644 qcom/lahaina-vm-mtp-v2.dts create mode 100644 qcom/lahaina-vm-mtp-v2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 8ddaae69c558..68fa95bbdcd1 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -181,6 +181,7 @@ ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ lahaina-vm-cdp.dtb \ lahaina-vm-qrd.dtb \ + lahaina-vm-mtp-v2.dtb \ lahaina-vm-mtp-v2.1.dtb endif endif diff --git a/qcom/lahaina-vm-mtp-v2.dts b/qcom/lahaina-vm-mtp-v2.dts new file mode 100644 index 000000000000..3fbafff1e13b --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm-v2.dtsi" +#include "lahaina-vm-mtp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM MTP v2"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/lahaina-vm-mtp-v2.dtsi b/qcom/lahaina-vm-mtp-v2.dtsi new file mode 100644 index 000000000000..2a76b5241e44 --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.dtsi @@ -0,0 +1 @@ +#include "lahaina-vm-mtp.dtsi" From c9373311325590d0c9325c5bfc5732271e8df16d Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Mon, 9 Nov 2020 11:33:21 +0530 Subject: [PATCH 0280/1809] ARM: dts: msm: Add stub regulators for Monaco Add tub regulators for Monaco to allow consumers to register and vote for the regulators. Change-Id: I71e5c17c032f8ed967965aa24d13d90ad5b1a6b2 --- qcom/monaco-stub-regulator.dtsi | 336 ++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 qcom/monaco-stub-regulator.dtsi diff --git a/qcom/monaco-stub-regulator.dtsi b/qcom/monaco-stub-regulator.dtsi new file mode 100644 index 000000000000..b0eb6737362b --- /dev/null +++ b/qcom/monaco-stub-regulator.dtsi @@ -0,0 +1,336 @@ +#include + +/ { + VDD_CX_LEVEL: + S1A_LEVEL: + pm5100_s1_level: regulator-pm5100-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S1A_LEVEL_AO: + pm5100_s1_level_ao: regulator-pm5100-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s1_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S3A: + pm5100_s3: regulator-pm5100-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <790000>; + regulator-max-microvolt = <1374000>; + }; + + S4A: + pm5100_s4: regulator-pm5100-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + S5A: + pm5100_s5: regulator-pm5100-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2040000>; + }; + + L1A: + pm5100_l1: regulator-pm5100-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_EBI_LEVEL: + VDD_MXA_LEVEL: + L3A_LEVEL: + pm5100_l3_level: regulator-pm5100-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXA_LEVEL_AO: + L3A_LEVEL_AO: + pm5100_l3_level_ao: regulator-pm5100-l3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l3_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_LPI_CX_LEVEL: + L4A_LEVEL: + pm5100_l4_level: regulator-pm5100-l4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_LPI_MX_LEVEL: + L5A_LEVEL: + pm5100_l5_level: regulator-pm5100-l5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL: + L6A_LEVEL: + pm5100_l6_level: regulator-pm5100-l6-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l6_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL_AO: + L6A_LEVEL_AO: + pm5100_l6_level_ao: regulator-pm5100-l6-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l6_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L7A: + pm5100_l7: regulator-pm5100-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + L8A: + pm5100_l8: regulator-pm5100-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <968000>; + }; + + L9A: + pm5100_l9: regulator-pm5100-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + L10A: + pm5100_l10: regulator-pm5100-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + }; + + L11A: + pm5100_l11: regulator-pm5100-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + }; + + L12A: + pm5100_l12: regulator-pm5100-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + L13A: + pm5100_l13: regulator-pm5100-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + L14A: + pm5100_l14: regulator-pm5100-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + }; + + L15A: + pm5100_l15: regulator-pm5100-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L16A: + pm5100_l16: regulator-pm5100-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L17A: + pm5100_l17: regulator-pm5100-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1950000>; + }; + + L18A: + pm5100_l18: regulator-pm5100-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L19A: + pm5100_l19: regulator-pm5100-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L20A: + pm5100_l20: regulator-pm5100-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L21A: + pm5100_l21: regulator-pm5100-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + }; + + L22A: + pm5100_l22: regulator-pm5100-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L23A: + pm5100_l23: regulator-pm5100-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + }; + + L24A: + pm5100_l24: regulator-pm5100-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l24"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <3544000>; + }; + + L25A: + pm5100_l25: regulator-pm5100-l25 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l25"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L26A: + pm5100_l26: regulator-pm5100-l26 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l26"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + L27A: + pm5100_l27: regulator-pm5100-l27 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l27"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + L28A: + pm5100_l28: regulator-pm5100-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l28"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L29A: + pm5100_l29: regulator-pm5100-l29 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l29"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <3544000>; + }; +}; From 9c620c73d1d00199c3ae3d84789cab7e96b8092e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 9 Nov 2020 12:53:57 +0530 Subject: [PATCH 0281/1809] ARM: dts: msm: Change the node location for optimization for Shima Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Also, bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: I2fd58fdac57608b57a3996581397104168440ed0 --- qcom/shima.dtsi | 518 ++++++++++++++++++++++++------------------------ 1 file changed, 262 insertions(+), 256 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 8246b5473d9d..c042de94a110 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -31,7 +31,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -51,7 +57,9 @@ swr2 = &swr2; serial0 = &qupv3_se13_2uart; hsuart0 = &qupv3_se15_4uart; - }; + }; + + firmware: firmware {}; cpus { #address-cells = <2>; @@ -248,272 +256,270 @@ }; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_mem@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - reserved_xbl_uefi: reserved_xbl_uefi@80880000 { - no-map; - reg = <0x0 0x80880000 0x0 0x14000>; - }; - - smem_mem: smem@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - fw_mem: fw_mem@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_camera_mem: camera@85800000 { - no-map; - reg = <0x0 0x85800000 0x0 0x500000>; - }; - - pil_video_mem: video@85d00000 { - no-map; - reg = <0x0 0x85d00000 0x0 0x500000>; - }; - - pil_cvp_mem: cvp@86200000 { - no-map; - reg = <0x0 0x86200000 0x0 0x500000>; - }; - - pil_adsp_mem: adsp@86700000 { - no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; - }; - - pil_cdsp_mem: cdsp@88f00000 { - no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xC00000>; - }; - - pil_wlan_mem: wlan@8ad00000 { - no-map; - reg = <0x0 0x8ad00000 0x0 0xa00000>; - }; - - pil_ipa_fw_mem: ipa_fw@8b700000 { - no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: ipa_gsi@8b710000 { - no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; - }; - - pil_mpss_wlan_mem: mpss_wlan@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - removed_mem: removed_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x5100000>; - }; - - pil_trustedvm_mem: pil_trustedvm_region@d0800000 { - no-map; - reg = <0x0 0xd0800000 0x0 0x76f7000>; - }; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0xd7ef7000 0x0 0x9000>; - }; - - chan0_shbuf: neuron_block@0 { - no-map; - reg = <0x0 0xd7f00000 0x0 0x80000>; - }; - - chan1_shbuf: neuron_block@1 { - no-map; - reg = <0x0 0xd7f80000 0x0 0x80000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0xA000000>; - }; - - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qcom: ramoops { - compatible = "ramoops"; - reg = <0x0 0xa9000000 0x0 0x200000>; - pmsg-size = <0x200000>; - mem-type = <2>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - cdsp_mem: cdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x400000>; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x2c00000>; - }; - - audio_cma_mem: audio_cma_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1C00000>; - }; - - splash_memory: splash_region { - reg = <0x0 0xe1000000 0x0 0x02300000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_memory { - reg = <0x0 0xe3300000 0x0 0x0100000>; - label = "dfps_data_memory"; - }; - - non_secure_display_memory: non_secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x6400000>; - }; - }; - - chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; - }; soc: soc { }; - firmware: firmware { - scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; }; }; }; }; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_camera_mem: camera@85800000 { + no-map; + reg = <0x0 0x85800000 0x0 0x500000>; + }; + + pil_video_mem: video@85d00000 { + no-map; + reg = <0x0 0x85d00000 0x0 0x500000>; + }; + + pil_cvp_mem: cvp@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + pil_wlan_mem: wlan@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0xa00000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0xA000000>; + }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xa9000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x2c00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + splash_memory: splash_region { + reg = <0x0 0xe1000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_memory { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_memory"; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; From 6b84a80dde1ab6801f606e9f81cea291ef462da7 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 4 Nov 2020 16:05:27 +0530 Subject: [PATCH 0282/1809] ARM: dts: msm: Use PCIe_MSI for Shima This reverts commit a986821e2562b51c88ba1be50ca37edec93b3c4f. Commit a986821e2562b5 ("Revert "ARM: dts: msm: Use PCIe_MSI for Shima"") reverted the MSI changes due to there are pending MSI interrupts in PCIe DRV suspend state from device, which caused NOC error when host try to read MSI status register. Re-enabled the MSI changes as there is an changes made in ADSP side to check any pending interrupts before entering L1SS sleep. Change-Id: I6faa18002395d3b100e12362446da96ddb5b29ee --- qcom/shima-pcie.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..fbe74ebfb44d 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi>; + msi-parent = <&pcie0_msi_snps>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -194,6 +194,15 @@ }; }; + pcie0_msi_snps: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; + pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From 926d765cdf105b3e97bda60579baa6cf0cbda145 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 2 Nov 2020 19:55:31 +0530 Subject: [PATCH 0283/1809] ARM: dts: msm: Add RDPM register map for Shima GPU Add the RDPM register ranges so the graphics driver can share the current GPU frequency across drivers. Change-Id: Ib7bac0d639fe0e1aecffd82e2d370854fd9f1238 --- qcom/shima-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index f7808d3470d0..9766e11225f9 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -16,10 +16,10 @@ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>; + <0x06900000 0x80000>, <0x0636000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx"; + "isense_cntl", "qdss_gfx", "rdpm_mx"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; From 409eac43c7d8db60a4c504e0fda4e94c8419e060 Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Sun, 27 Sep 2020 15:02:11 +0530 Subject: [PATCH 0284/1809] ARM: dts: msm: Add PMIC devicetrees for SDXNIGHTJAR Add initial devicetree for PMD9650 and regulator devices for supporting SDXNIGHTJAR target. Change-Id: I40db010a3bd50200c539da86dbffcfb49da480e7 --- qcom/pmd9650-rpm-regulator.dtsi | 302 ++++++++++++++++++++++++++++++++ qcom/pmd9650.dtsi | 101 +++++++++++ qcom/sdxnightjar-regulator.dtsi | 258 +++++++++++++++++++++++++++ 3 files changed, 661 insertions(+) create mode 100644 qcom/pmd9650-rpm-regulator.dtsi create mode 100644 qcom/pmd9650.dtsi create mode 100644 qcom/sdxnightjar-regulator.dtsi diff --git a/qcom/pmd9650-rpm-regulator.dtsi b/qcom/pmd9650-rpm-regulator.dtsi new file mode 100644 index 000000000000..d89c52e2a1a8 --- /dev/null +++ b/qcom/pmd9650-rpm-regulator.dtsi @@ -0,0 +1,302 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { /* VDD_CX supply */ + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { /* VDD_MX supply */ + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pmd9650.dtsi b/qcom/pmd9650.dtsi new file mode 100644 index 000000000000..83ea13885ee3 --- /dev/null +++ b/qcom/pmd9650.dtsi @@ -0,0 +1,101 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmd9650@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd9650_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,pon-dbc-delay = <15625>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr"; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pmd9650_gpios: pinctrl@c000 { + compatible = "qcom,pmd9650-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmd9650_vadc: vadc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + ref_1p25 { + reg = ; + label = "ref_1p25"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,pmd9650_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + qcom,pmd9650@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd9650_pwm_1: pwm@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + + pmd9650_pwm_2: pwm@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + }; +}; diff --git a/qcom/sdxnightjar-regulator.dtsi b/qcom/sdxnightjar-regulator.dtsi new file mode 100644 index 000000000000..32126cb2c986 --- /dev/null +++ b/qcom/sdxnightjar-regulator.dtsi @@ -0,0 +1,258 @@ +#include + +&rpm_bus { + /* PMD9650 S1 = VDD_MSS supply */ + rpm-regulator-smpa1 { + status = "okay"; + pmd9650_s1: regulator-s1 { + regulator-name = "pmd9650_s1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pmd9650_s2: regulator-s2 { + regulator-name = "pmd9650_s2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1256000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pmd9650_s3: regulator-s3 { + regulator-name = "pmd9650_s3"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + qcom,init-voltage = <1024000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pmd9650_s4: regulator-s4 { + regulator-name = "pmd9650_s4"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + qcom,init-voltage = <1856000>; + status = "okay"; + }; + }; + + /* PMD9650 S5 = VDD_CX supply */ + rpm-regulator-smpa5 { + status = "okay"; + pmd9650_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pmd9650_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pmd9650_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pmd9650_l1: regulator-l1 { + regulator-name = "pmd9650_l1"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + qcom,init-voltage = <1224000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pmd9650_l2: regulator-l2 { + regulator-name = "pmd9650_l2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pmd9650_l3: regulator-l3 { + regulator-name = "pmd9650_l3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pmd9650_l4: regulator-l4 { + regulator-name = "pmd9650_l4"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + qcom,init-voltage = <928000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pmd9650_l5: regulator-l5 { + regulator-name = "pmd9650_l5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pmd9650_l6: regulator-l6 { + regulator-name = "pmd9650_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pmd9650_l7: regulator-l7 { + regulator-name = "pmd9650_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pmd9650_l8: regulator-l8 { + regulator-name = "pmd9650_l8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + /* PMD9650 L9 = VDD_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + pmd9650_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pmd9650_l10: regulator-l10 { + regulator-name = "pmd9650_l10"; + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3088000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pmd9650_l11: regulator-l11 { + regulator-name = "pmd9650_l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pmd9650_l12: regulator-l12 { + regulator-name = "pmd9650_l12"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pmd9650_l13: regulator-l13 { + regulator-name = "pmd9650_l13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; +}; + +&soc { + codec_buck_vreg: codec_buck_vreg { + compatible = "regulator-fixed"; + regulator-name = "codec_1.8v"; + regulator-always-on; + }; + + /* Rome 3.3V supply */ + rome_vreg: rome_vreg { + compatible = "regulator-fixed"; + regulator-name = "rome_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmd9650_gpios 6 0>; + }; + + /* SD card 2.95 V supply */ + sdc_vreg: sdc_vreg { + compatible = "regulator-fixed"; + regulator-name = "sdc_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm_pinmux 50 0>; + }; +}; From 3c9408beff76f27a9aca5adb33a150a098d6cfb8 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Mon, 9 Nov 2020 23:42:07 +0530 Subject: [PATCH 0285/1809] ARM: dts: msm: Disable sdcard on cdp & eMMC on mbb platform Disable sdcard on cdp & emmc on mtp mbb platform as mbb platform doesn't support eMMC. We would enable sdcard and eMMC separately on different platform specific dt file. Change-Id: Ife9ca9b5512a8bf0cb1f9de7dd40a80c6d168506 --- qcom/sdxlemur-cdp.dtsi | 2 +- qcom/sdxlemur-mtp-mbb.dtsi | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 6b6ff3fc2a0c..45963f72f1f0 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -9,7 +9,7 @@ }; &sdhc_1 { - status = "ok"; + status = "disabled"; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..12c0bd9dd1d5 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -14,6 +14,10 @@ qcom,boot-option = <0x1>; }; +&qnand_1 { + status = "ok"; +}; + &sdhc_1 { reg = <0x08804000 0x1000>, <0x08805000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; @@ -39,5 +43,5 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; - status = "ok"; + status = "disabled"; }; From 3d53a281f3688b49ab2c4207bfcd6b519bfbf35a Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Wed, 30 Sep 2020 00:43:21 +0530 Subject: [PATCH 0286/1809] ARM: dts: msm: Add initial device tree for Monaco Add initial device tree support for monaco target on rumi platform. Update the bindings for same. Change-Id: I6542a62d89cd07dd3495988ec2670f6f695c8470 --- bindings/arm/msm/msm.txt | 4 + bindings/pinctrl/qcom,monaco-pinctrl.yaml | 195 +++++++++++ qcom/Makefile | 9 + qcom/monaco-pinctrl.dtsi | 11 + qcom/monaco-rumi-overlay.dts | 11 + qcom/monaco-rumi.dts | 11 + qcom/monaco-rumi.dtsi | 14 + qcom/monaco.dts | 9 + qcom/monaco.dtsi | 389 ++++++++++++++++++++++ 9 files changed, 653 insertions(+) create mode 100644 bindings/pinctrl/qcom,monaco-pinctrl.yaml create mode 100644 qcom/monaco-pinctrl.dtsi create mode 100644 qcom/monaco-rumi-overlay.dts create mode 100644 qcom/monaco-rumi.dts create mode 100644 qcom/monaco-rumi.dtsi create mode 100644 qcom/monaco.dts create mode 100644 qcom/monaco.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 97bc621e80e4..0107b952f4b5 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -92,6 +92,9 @@ SoCs: - HOLI compatible = "qcom,holi" +- MONACO + compatible = "qcom,monaco" + Generic board variants: - CDP device: @@ -251,3 +254,4 @@ compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" compatible = "qcom,scuba-idp" +compatible = "qcom,monaco-rumi" diff --git a/bindings/pinctrl/qcom,monaco-pinctrl.yaml b/bindings/pinctrl/qcom,monaco-pinctrl.yaml new file mode 100644 index 000000000000..861e0e955568 --- /dev/null +++ b/bindings/pinctrl/qcom,monaco-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,monaco-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MONACO TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + MONACO platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,monaco-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@500000 { + compatible = "qcom,monaco-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 8ddaae69c558..f86aed7d876d 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -143,6 +143,15 @@ else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_MONACO) += \ + monaco-rumi-overlay.dtbo + +monaco-rumi-overlay.dtbo-base := monaco.dtb +else +dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SA8155) += \ sa8155-adp-star-overlay.dtbo \ diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi new file mode 100644 index 000000000000..0008896c79a9 --- /dev/null +++ b/qcom/monaco-pinctrl.dtsi @@ -0,0 +1,11 @@ +&soc { + tlmm: pinctrl@500000 { + compatible = "qcom,monaco-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/qcom/monaco-rumi-overlay.dts b/qcom/monaco-rumi-overlay.dts new file mode 100644 index 000000000000..4f3bb6574696 --- /dev/null +++ b/qcom/monaco-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "monaco-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco RUMI"; + compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; + qcom,msm-id = <459 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/monaco-rumi.dts b/qcom/monaco-rumi.dts new file mode 100644 index 000000000000..cb90f9641935 --- /dev/null +++ b/qcom/monaco-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "monaco.dtsi" +#include "monaco-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco RUMI"; + compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi new file mode 100644 index 000000000000..58b95639be9e --- /dev/null +++ b/qcom/monaco-rumi.dtsi @@ -0,0 +1,14 @@ +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f120000 { + clock-frequency = <500000>; + }; + + wdog: qcom,wdt@f017000 { + status = "disabled"; + }; + +}; diff --git a/qcom/monaco.dts b/qcom/monaco.dts new file mode 100644 index 000000000000..c9446f70c99a --- /dev/null +++ b/qcom/monaco.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "monaco.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco SoC"; + compatible = "qcom,monaco"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi new file mode 100644 index 000000000000..f33ea540e53e --- /dev/null +++ b/qcom/monaco.dtsi @@ -0,0 +1,389 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Monaco"; + compatible = "qcom,monaco"; + qcom,msm-id = <459 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + soc: soc { }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x80000>; /* GICR * 4 */ + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f121000 0x1000>, + <0x0f122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = ; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = ; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = ; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = ; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = ; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-slepp-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + }; +}; + +#include "monaco-pinctrl.dtsi" From 7a6358ab8fb874335bba34b5ec118af25bb3b997 Mon Sep 17 00:00:00 2001 From: Arun Prakash Date: Fri, 13 Mar 2020 14:20:39 +0530 Subject: [PATCH 0287/1809] ARM: dts: msm: Add support for glink for SM8150 Add glink and its dependent device tree node to support SM8150 for automotive platforms. Add snapshot of sm8150-smp2p.dtsi from 4.14 kernel with commit <1392da24f5ae6cda2bbca50433acc952b72061af> (drivers: iio: imu: Fix NULL pointer dereference in IMU drivers) to kernel 5.4. Change-Id: Iffc0f294c196dcdf874a9fbb19f63e4a4f626e2f --- qcom/sm8150-smp2p.dtsi | 142 ++++++++++++++++ qcom/sm8150.dtsi | 365 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 507 insertions(+) create mode 100644 qcom/sm8150-smp2p.dtsi diff --git a/qcom/sm8150-smp2p.dtsi b/qcom/sm8150-smp2p.dtsi new file mode 100644 index 000000000000..999901f99472 --- /dev/null +++ b/qcom/sm8150-smp2p.dtsi @@ -0,0 +1,142 @@ +#include + +&soc { + + qcom,smp2p-modem@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-dsps@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + dsps_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + dsps_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; + }; + +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index ca02103037dd..fcb8a87066b1 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -734,6 +734,370 @@ status = "ok"; }; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + sp_scsr: mailbox@188501c { + compatible = "qcom,sm8150-spcs-global"; + reg = <0x188501c 0x4>; + + #mbox-cells = <1>; + }; + + sp_scsr_block: syscon@1880000 { + compatible = "syscon"; + reg = <0x1880000 0x10000>; + }; + + intsp: qcom,qsee_irq { + compatible = "qcom,sm8150-qsee-irq"; + + syscon = <&sp_scsr_block>; + interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, + <0 349 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "sp_ipc0", + "sp_ipc1"; + + interrupt-controller; + #interrupt-cells = <3>; + }; + + qcom,qsee_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + label = "spss"; + interrupt-parent = <&intsp>; + interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apss_shared 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_slpi>, + <&glink_cdsp>, + <&glink_spss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apss_shared 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_slpi>, + <&glink_cdsp>; + }; + }; + + glink_slpi: dsps { + qcom,remote-pid = <3>; + transport = "smem"; + mboxes = <&apss_shared 24>; + mbox-names = "dsps_smem"; + interrupts = ; + + label = "slpi"; + qcom,glink-label = "dsps"; + + qcom,slpi_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,slpi_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apss_shared 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + /* qcom,target-dev = <&cdsp_cdsp_l3_lat>;*/ + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + qcom,compute-cx-limit-en; + qcom,compute-priority-mode = <2>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_slpi>; + }; + }; + + glink_spss: spss { + qcom,remote-pid = <8>; + transport = "spss"; + mboxes = <&sp_scsr 0>; + mbox-names = "spss_spss"; + interrupt-parent = <&intsp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + + qcom,spss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; }; &firmware { @@ -747,3 +1111,4 @@ #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" +#include "sm8150-smp2p.dtsi" From 6cfc62e22709690668e3b0894c1f3e6c573594eb Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 2 Apr 2020 19:45:33 +0530 Subject: [PATCH 0288/1809] dt-bindings: clocks: Add clock controller bindings for SM8150 Add clock controller bindings to support SM8150. Change-Id: I78b757d5f0bedea75f95c7686ff90d7523e6e685 --- bindings/clock/qcom,camcc.txt | 5 +++++ bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 2 ++ bindings/clock/qcom,gcc.txt | 8 ++++---- bindings/clock/qcom,gpucc.txt | 5 ++++- bindings/clock/qcom,npucc.txt | 33 +++++++++++++++++++++++++++++++++ bindings/clock/qcom,scc.txt | 23 +++++++++++++++++++++++ bindings/clock/qcom,videocc.txt | 4 ++++ 8 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 bindings/clock/qcom,npucc.txt create mode 100644 bindings/clock/qcom,scc.txt diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index aaa29dc09a63..b9e3105751a5 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -7,6 +7,11 @@ Required properties : "qcom,lahaina-camcc" "qcom,lahaina-camcc-v2" "qcom,shima-camcc" + "qcom,sm8150-camcc" + "qcom,sm8150-camcc-v2" + "qcom,sa8155-camcc" + "qcom,sa8155-camcc-v2" + - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 962376860141..c7d82f90a3c8 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -8,6 +8,7 @@ Required properties : "qcom,shima-debugcc" "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" + "qcom,sm8150-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index feaccf643a45..80bbef3710ec 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -9,6 +9,8 @@ Required properties : "qcom,lahaina-dispcc" "qcom,shima-dispcc" "qcom,holi-dispcc" + "qcom,sm8150-dispcc" + "qcom,sm8150-dispcc-v2" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 617a1a5125dc..f72a8ff537e6 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -24,10 +24,10 @@ Required properties : "qcom,gcc-sdm660" "qcom,gcc-sdm845" "qcom,lahaina-gcc" - "qcom,gcc-sm8150" - "qcom,gcc-sm8150-v2" - "qcom,gcc-sa8155" - "qcom,gcc-sa8155-v2" + "qcom,sm8150-gcc" + "qcom,sm8150-gcc-v2" + "qcom,sa8155-gcc" + "qcom,sa8155-gcc-v2" "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 4b987a3312c1..726c24257d24 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -5,7 +5,10 @@ Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", "qcom,lahaina-gpucc", "qcom,shima-gpucc", - "qcom,holi-gpucc". + "qcom,holi-gpucc", + "qcom,sm8150-gpucc", + "qcom,sa8155-gpucc". + - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Must contain "cc_base". diff --git a/bindings/clock/qcom,npucc.txt b/bindings/clock/qcom,npucc.txt new file mode 100644 index 000000000000..b05c0012dae5 --- /dev/null +++ b/bindings/clock/qcom,npucc.txt @@ -0,0 +1,33 @@ +Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding +---------------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sm8150-npucc" + "qcom,sm8150-npucc-v2" + "qcom,sa8155-npucc" + "qcom,sa8155-npucc-v2" + +- reg : shall contain base register location and length. +- reg-names: names of registers listed in the same order as in + the reg property. +- vdd_cx-supply: phandle to the CX rail that needs to be voted + on behalf of the NPU CC clocks. +- vdd_gdsc-supply: phandle to the NPU core GDSC that needs to be + toggled as part of the CRC sequence. +- #clock-cells : shall contain 1. +- #reset-cells : shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + npucc: qcom,npucc { + compatible = "qcom,npucc-sm8150"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&pm8150l_s6_level>; + vdd_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/bindings/clock/qcom,scc.txt b/bindings/clock/qcom,scc.txt new file mode 100644 index 000000000000..fce28e82ddb9 --- /dev/null +++ b/bindings/clock/qcom,scc.txt @@ -0,0 +1,23 @@ +Qualcomm Technologies, Inc. Sensor Clock Controller Bindings + +Required properties: +- compatible : shall contain only one of the following: + "qcom,sm8150-scc" + "qcom,sm8150-scc-v2" + "qcom,sa8155-scc" + "qcom,sa8155-scc-v2" + +- reg: shall contain base register location and length. +- vdd_scc_cx-supply: the logic rail supply. +- #clock-cells: shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + qcom,scc@2b10000 { + compatible = "qcom,scc-sm8150"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + }; diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index 9dd9a36d2743..e46fa2db829b 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -7,6 +7,10 @@ Required properties : "qcom,sdm845-videocc" "qcom,lahaina-videocc" "qcom,shima-videocc" + "qcom,sm8150-videocc" + "qcom,sm8150-videocc-v2" + "qcom,sa8155-videocc" + "qcom,sa8155-videocc-v2" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. From 26092a7c84c01a86d779d6a51156c76362fd12b4 Mon Sep 17 00:00:00 2001 From: Gaurav Singh Date: Tue, 20 Oct 2020 16:58:12 +0530 Subject: [PATCH 0289/1809] ARM: dts: msm: enable scmi plh protocol Enable SCMI PLH protocol to allow communication with RIMPS PLH module. Change-Id: I8a2a8f033239580830120b2225f11522c84223fc --- qcom/holi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 6b2dcde9fc03..1612a9ba3694 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1496,6 +1496,11 @@ reg = <0x80>; #clock-cells = <1>; }; + + scmi_perf_lock: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; }; rimps_log: qcom,rimps_log@fd04780 { From fa0123c58683cea2b3d1e9ca842a4f40c0745ae8 Mon Sep 17 00:00:00 2001 From: Vaibhav Agrawal Date: Thu, 29 Oct 2020 15:37:26 +0530 Subject: [PATCH 0290/1809] ARM: dts: msm: Add the hwkm ice slave regions to storage node The HWKM ICE slave memory regions are different for UFS and EMMC storage type. We parse the values in the storage related drivers now hence adding the memory regions to the corresponding storage driver dtsi nodes for holi, shima and lahaina. Change-Id: I5bec8a164f3b947d5d6ef6fcfc384624b1fa58ca --- qcom/holi.dtsi | 15 +++++++++------ qcom/lahaina.dtsi | 5 +++-- qcom/shima.dtsi | 11 +++++++---- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 6b2dcde9fc03..7c144eb95462 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2030,8 +2030,9 @@ ufshc_mem: ufshc@4804000 { compatible = "qcom,ufshc"; reg = <0x4804000 0x3000>, - <0x4808000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x4808000 0x8000>, + <0x4810000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -2131,8 +2132,10 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; - reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, + <0x04748000 0x8000>, <0x04750000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; @@ -2509,8 +2512,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; - reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; - reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>; + reg-names = "km_master", "ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 504381c5d367..689f7074ba84 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3045,8 +3045,9 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 8246b5473d9d..44ab78339e3f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1615,8 +1615,9 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -1752,8 +1753,10 @@ sdhc_1: sdhci@7C4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007c8000 0x8000>, <0x7d0000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; iommus = <&apps_smmu 0xc0 0x0>; dma-coherent; From db099333eb07df542a96825b164a8b2c970daa4e Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Tue, 3 Nov 2020 12:12:43 +0530 Subject: [PATCH 0291/1809] ARM: dts: msm: Include stub regulators for Monaco Include stub regulators for Monaco to allow consumers to register and vote for the regulators. Change-Id: Ib5d22709bb6e1e7ac324b0ab4b1d9cb337d39279 --- qcom/monaco-rumi.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 58b95639be9e..d6ea70d56500 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -12,3 +12,5 @@ }; }; + +#include "monaco-stub-regulator.dtsi" From 775d7cc341c2f0fd90e141698266bf5879353d05 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 10 Nov 2020 13:41:27 -0800 Subject: [PATCH 0292/1809] ARM: dts: qcom: Add entry for EUD driver Added an entry for the EUD driver. Change-Id: I8f0580fccec8c6e8150837aef714562cef3de027 --- qcom/sdxlemur.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..252b7014120b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -361,6 +361,18 @@ #clock-cells = <1>; }; + eud: qcom,msm-eud@ff0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0000 0x2000>, + <0xff2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + status = "ok"; + }; + serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; From c0677ba33d3aeb28c869e9328a7a034873cd5f96 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 8 Jul 2020 19:50:39 +0530 Subject: [PATCH 0293/1809] dt-bindings: interconnect: update interconnect bindings Update interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: Ib20f2a56509528638c4604d2fe8f755f06e25fc4 --- bindings/interconnect/qcom,sm8150.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/bindings/interconnect/qcom,sm8150.txt b/bindings/interconnect/qcom,sm8150.txt index 247fc9655b8f..a0b636af3c11 100644 --- a/bindings/interconnect/qcom,sm8150.txt +++ b/bindings/interconnect/qcom,sm8150.txt @@ -21,9 +21,6 @@ Required properties : "qcom,sm8150-mc_virt"; "qcom,sm8150-mmss_noc"; "qcom,sm8150-system_noc"; - "qcom,sm8150-gem_noc_display"; - "qcom,sm8150-mc_virt_display"; - "qcom,sm8150-mmss_noc_display"; - #interconnect-cells : should contain 1 Examples: From 57b0841f8fada9d0ea2279c6ae8849e517eca7bf Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 13 Apr 2020 15:29:30 +0530 Subject: [PATCH 0294/1809] dt-bindings: ufs: Add compitable string for V4 UFS PHY on SM8150 This change adds the compatible string for the V4 UFS PHY present on SM8150 chipset. Change-Id: I767c6b12d6423ddb04c0769f801c8e95cc1072dd --- bindings/ufs/ufs-qcom.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index c3db1a85b6e9..c4e221a8c05e 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -16,6 +16,8 @@ Required properties: for sdm845 emulation, "qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy present on Lahaina chipset. + "qcom,ufs-phy-qmp-v4" for V4 ufs phy present + on SM8150 chipset. "qcom,ufs-phy-qmp-v3" for V3 ufs phy present on holi chipset. - reg : should contain PHY register address space (mandatory), From 5b6a3044ee38bab61c701c82dcef8037b8ad7fbc Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 3 Nov 2020 11:50:51 +0530 Subject: [PATCH 0295/1809] dt-bindings: interconnect: add OSM L3 bindings Add bindings for the new interconnect OSM L3 driver. Change-Id: Ib240d9e8d900539fc6f8112c9fe55d530d51ae95 --- bindings/interconnect/qcom,osm-l3.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 bindings/interconnect/qcom,osm-l3.txt diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt new file mode 100644 index 000000000000..4d323fd7750b --- /dev/null +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -0,0 +1,25 @@ +Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +----------------------------------------------------------- + +The EPSS L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdm845-osm-l3", + "qcom,sm8150-osm-l3"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +osm_l3: interconnect@0x18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm8150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; +}; From 0cdf93f09ce678ebebcf132774dcf00dd4cab9d9 Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Tue, 10 Nov 2020 21:59:03 -0800 Subject: [PATCH 0296/1809] ARM: dts: msm: Disable unused flag for MDM Disable the page recycling feature. Disable lan rx napi. Change-Id: I9e2c19efbe0d05137fc37576c5f1ef4b283dc90f --- qcom/sdxlemur.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f833437c3762..cef83da65390 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -794,8 +794,6 @@ qcom,arm-smmu; qcom,smmu-fast-map; qcom,ipa-wdi3-over-gsi; - qcom,lan-rx-napi; - qcom,wan-use-skb-page; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; From d12f06fd42137a29dc498ca22e535e31af808192 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Mon, 12 Oct 2020 14:47:19 +0530 Subject: [PATCH 0297/1809] ARM: dts: msm: Add le-vm DT flag in lahaina TUI Add le-vm flag for GPI DT node in lahaina TUI . Change-Id: I8d24d823be4b55fedf34e4d7e5c024c810895294 --- qcom/lahaina-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 46d744d95235..f7b2d6708460 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -296,6 +296,7 @@ qcom,gpii-mask = <0x80>; qcom,ev-factor = <2>; qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; status = "ok"; }; From 2226c57ae73dbe0823540b010b9a945ac6d4fa5f Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Wed, 23 Sep 2020 15:44:20 +0530 Subject: [PATCH 0298/1809] ARM: dts: msm: increase log buf size for holi Increase log_buf size for holi, to avoid losing bootup logs which might be required for debugging. Change-Id: Id81dbed32b8eafa7ce06b2f5cd71b2d7221de1fb --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 6b2dcde9fc03..19f80434c700 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -448,7 +448,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; }; From 5d0e0faf2a2f7e209a166d376bea34a67da4127f Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 11 Nov 2020 18:30:39 +0530 Subject: [PATCH 0299/1809] ARM: dts: msm: Correct BAM register address on olympic This change will correct the UART nodes BAM base register address on olympic platform. Change-Id: Ib5819fea7c1201ae06bc72b8f080c40f286f5017 --- qcom/sdxlemur-blsp.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi index 997db6b37078..230b20c32b78 100644 --- a/qcom/sdxlemur-blsp.dtsi +++ b/qcom/sdxlemur-blsp.dtsi @@ -294,7 +294,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1a_hs>; @@ -330,7 +330,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1b_hs>; @@ -366,7 +366,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2a_hs>; @@ -402,7 +402,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2b_hs>; @@ -438,7 +438,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x831000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3_hs>; @@ -474,7 +474,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4a_hs>; @@ -510,7 +510,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4b_hs>; From 4086892f64e92aa56bfb5f5abe79ea707efed1bd Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 11 Nov 2020 11:14:22 -0800 Subject: [PATCH 0300/1809] ARM: dts: msm: add PCI DT node for generic attaches over oculink sdxlemur Add PCI DT node with default iommu configuration to support any endpoint connected over oculink on sdxlemur. Change-Id: Idfdc2d06311c0906054e7503a2e6d02cc34ad9ae --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 768d9aaa521c..3212a1a7041f 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -4,3 +4,19 @@ }; +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + pcie0_generic_ep: pcie0_rp_ep { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&pcie0_generic_ep_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + pcie0_generic_ep_iommu_group: pcie0_generic_ep_iommu_group { + qcom,iommu-dma = "atomic"; + }; + }; +}; From 9cc950721974f1658a0fdbbaebd0609fc8c74d8d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 11 Nov 2020 17:23:18 +0800 Subject: [PATCH 0301/1809] dt-bindings: arm: Add FUSE and DBGUI support Add binding document for FUSE and DBGUI feature. Change-Id: I3908ba891f6d093b4ebeeedffbdbe4ff46bc3407 --- bindings/arm/coresight.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 1fadc1b562cc..fc00b47abcd6 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -101,6 +101,14 @@ its hardware characteristcs. - Coresight remote ETM: "qcom,coresight-remote-etm" + - Coresight dbgui device: + "qcom,coresight-dbgui" + + - Coresight fuse device: + "arm,coresight-fuse" + "arm,coresight-fuse-v2" + "arm,coresight-fuse-v3" + * port or ports: see "Graph bindings for Coresight" below. * Additional required property for coresight-tgu devices: From e9c6cc6e6e89f886b4df90138472cf353f201efc Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Thu, 12 Nov 2020 10:05:39 +0530 Subject: [PATCH 0302/1809] ARM: dts: msm: Add pm-qos-latency for Shima Add pm-qos-latency which ensures that cpu is used to its full capability, there by increasing USB throughput for shima. Change-Id: Ifade66ebe820cbfe2e5a6b2ba003d301a180d36e --- qcom/shima-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi index 48b5d3839b21..f8e2e2a1daaa 100644 --- a/qcom/shima-usb.dtsi +++ b/qcom/shima-usb.dtsi @@ -39,6 +39,7 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ From 1d9db2ceb70da60aad2d33ba9b5cf2cf4533175f Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 11 Nov 2020 14:50:27 -0800 Subject: [PATCH 0303/1809] ARM: dts: msm: add LTR entries for HSP direct connects on sdxlemur HSP requires PCIe host to have LTR programmed for LPM usecases, therefore, add the required LTR entries for PCIe on sdxlemur. Change-Id: I38f82152f2113dc59c2da89f2328d51c2d161eb8 --- qcom/sdxlemur-cdp.dtsi | 2 ++ qcom/sdxlemur-mtp-mbb.dtsi | 2 ++ qcom/sdxlemur-rcm-rc.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 6b6ff3fc2a0c..fe6531308f6c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -32,4 +32,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..4f4c9bc92f04 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -12,6 +12,8 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; &sdhc_1 { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7e5f6471cab7..0eb9848df6f1 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -12,4 +12,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; From 92cec7f6a9c903b763cbb2c7d83ce4a08cac7dca Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 12 Nov 2020 11:21:58 -0800 Subject: [PATCH 0304/1809] ARM: dts: msm: Update PCIe PHY settings to v1.02 for sdxlemur Update PCIe PHY setting to version v1.02 based on hardware recommendation for sdxlemur. Change-Id: I3204ed8030f3f3e11a52d690794c4e04b93f3cca --- qcom/sdxlemur-pcie.dtsi | 52 +++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 35e34a9c4b2d..cfaf0f7cc936 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -95,7 +95,7 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <1101>; + qcom,pcie-phy-ver = <1102>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; @@ -147,43 +147,49 @@ 0x0a20 0x16 0x0 0x0bc0 0x38 0x0 0x0364 0xcc 0x0 + 0x0368 0x12 0x0 0x036c 0xcc 0x0 - 0x0378 0x31 0x0 + 0x0374 0x4a 0x0 + 0x0378 0x29 0x0 0x037c 0xc5 0x0 - 0x0380 0xcc 0x0 + 0x0380 0xac 0x0 0x0384 0xb6 0x0 - 0x0388 0xc2 0x0 - 0x038c 0x17 0x0 + 0x0388 0xc0 0x0 + 0x038c 0x07 0x0 0x0390 0xfb 0x0 - 0x0394 0x0f 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xc5 0x0 0x039c 0xee 0x0 0x03a0 0xbf 0x0 - 0x03a4 0x80 0x0 + 0x03a4 0xa0 0x0 0x03a8 0x81 0x0 - 0x03ac 0xdf 0x0 - 0x03b0 0x5f 0x0 + 0x03ac 0xde 0x0 + 0x03b0 0x7f 0x0 0x0b64 0xcc 0x0 + 0x0b68 0x12 0x0 0x0b6c 0xcc 0x0 - 0x0b78 0x31 0x0 + 0x0b74 0x4a 0x0 + 0x0b78 0x29 0x0 0x0b7c 0xc5 0x0 - 0x0b80 0xcc 0x0 + 0x0b80 0xac 0x0 0x0b84 0xb6 0x0 - 0x0b88 0xc2 0x0 - 0x0b8c 0x17 0x0 + 0x0b88 0xc0 0x0 + 0x0b8c 0x07 0x0 0x0b90 0xfb 0x0 - 0x0b94 0x0f 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xc5 0x0 0x0b9c 0xee 0x0 0x0ba0 0xbf 0x0 - 0x0ba4 0x80 0x0 + 0x0ba4 0xa0 0x0 0x0ba8 0x81 0x0 - 0x0bac 0xdf 0x0 - 0x0bb0 0x5f 0x0 + 0x0bac 0xde 0x0 + 0x0bb0 0x7f 0x0 0x03b4 0x20 0x0 0x022c 0x3f 0x0 - 0x0230 0x2d 0x0 + 0x0230 0x37 0x0 0x0bb4 0x20 0x0 0x0a2c 0x3f 0x0 - 0x0a30 0x2d 0x0 + 0x0a30 0x37 0x0 0x0078 0x05 0x0 0x007c 0xf6 0x0 0x0878 0x05 0x0 @@ -216,12 +222,12 @@ 0x0adc 0x0a 0x0 0x0308 0x0b 0x0 0x0b08 0x0b 0x0 - 0x027c 0x1f 0x0 - 0x0a7c 0x1f 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 0x02b4 0x00 0x0 0x0ab4 0x00 0x0 - 0x02ec 0x0d 0x0 - 0x0aec 0x0d 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 0x02c4 0x00 0x0 0x02c8 0x1f 0x0 0x0ac4 0x00 0x0 From c4c41afbad7261344e9ae57323d30cbcc4569bf2 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 16 Oct 2020 10:13:43 +0800 Subject: [PATCH 0305/1809] ARM: dts: msm: Add initial devicetrees for SDXNIGHTJAR target Add initial devicetree files for supporing SDXNIGHTJAR target. Change-Id: I78a27e41723c3ff3a90955285ab5508dc6187855 --- bindings/arm/msm/msm.txt | 6 + bindings/interrupt-controller/arm,gic.txt | 171 +++ qcom/Makefile | 4 + qcom/sdxnightjar-cdp.dts | 11 + qcom/sdxnightjar-cdp.dtsi | 6 + qcom/sdxnightjar-mtp.dts | 11 + qcom/sdxnightjar-mtp.dtsi | 6 + qcom/sdxnightjar-pinctrl.dtsi | 1335 +++++++++++++++++++++ qcom/sdxnightjar-qrd.dts | 11 + qcom/sdxnightjar-qrd.dtsi | 6 + qcom/sdxnightjar.dtsi | 429 +++++++ 11 files changed, 1996 insertions(+) create mode 100644 bindings/interrupt-controller/arm,gic.txt create mode 100644 qcom/sdxnightjar-cdp.dts create mode 100644 qcom/sdxnightjar-cdp.dtsi create mode 100644 qcom/sdxnightjar-mtp.dts create mode 100644 qcom/sdxnightjar-mtp.dtsi create mode 100644 qcom/sdxnightjar-pinctrl.dtsi create mode 100644 qcom/sdxnightjar-qrd.dts create mode 100644 qcom/sdxnightjar-qrd.dtsi create mode 100644 qcom/sdxnightjar.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 0107b952f4b5..339b6c9b59f5 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -95,6 +95,9 @@ SoCs: - MONACO compatible = "qcom,monaco" +- SDXNIGHTJAR + compatible = "qcom,sdxnightjar" + Generic board variants: - CDP device: @@ -255,3 +258,6 @@ compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" +compatible = "qcom,sdxnightjar-mtp" +compatible = "qcom,sdxnightjar-cdp" +compatible = "qcom,sdxnightjar-qrd" diff --git a/bindings/interrupt-controller/arm,gic.txt b/bindings/interrupt-controller/arm,gic.txt new file mode 100644 index 000000000000..7ac781f6efe9 --- /dev/null +++ b/bindings/interrupt-controller/arm,gic.txt @@ -0,0 +1,171 @@ +* ARM Generic Interrupt Controller + +ARM SMP cores are often associated with a GIC, providing per processor +interrupts (PPI), shared processor interrupts (SPI) and software +generated interrupts (SGI). + +Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. +Secondary GICs are cascaded into the upward interrupt controller and do not +have PPIs or SGIs. + +Main node required properties: + +- compatible : should be one of: + "arm,arm1176jzf-devchip-gic" + "arm,arm11mp-gic" + "arm,cortex-a15-gic" + "arm,cortex-a7-gic" + "arm,cortex-a9-gic" + "arm,eb11mp-gic" + "arm,gic-400" + "arm,pl390" + "arm,tc11mp-gic" + "brcm,brahma-b15-gic" + "nvidia,tegra210-agic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 3. + + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered (invalid for SPIs) + 4 = active high level-sensitive + 8 = active low level-sensitive (invalid for SPIs). + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of + the 8 possible cpus attached to the GIC. A bit set to '1' indicated + the interrupt is wired to that CPU. Only valid for PPI interrupts. + Also note that the configurability of PPI interrupts is IMPLEMENTATION + DEFINED and as such not guaranteed to be present (most SoC available + in 2014 seem to ignore the setting of this flag and use the hardware + default value). + +- reg : Specifies base physical address(s) and size of the GIC registers. The + first region is the GIC distributor register base and size. The 2nd region is + the GIC cpu interface register base and size. + +Optional +- interrupts : Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintenance interrupt on primary GIC (see + below). + +- cpu-offset : per-cpu offset within the distributor and cpu interface + regions, used when the GIC doesn't have banked registers. The offset is + cpu-offset * cpu-nr. + +- clocks : List of phandle and clock-specific pairs, one for each entry + in clock-names. +- clock-names : List of names for the GIC clock input(s). Valid clock names + depend on the GIC variant: + "ic_clk" (for "arm,arm11mp-gic") + "PERIPHCLKEN" (for "arm,cortex-a15-gic") + "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") + "clk" (for "arm,gic-400" and "nvidia,tegra210") + "gclk" (for "arm,pl390") + +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle, used when the GIC + is part of a Power or Clock Domain. + + +Example: + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + +* GIC virtualization extensions (VGIC) + +For ARM cores that support the virtualization extensions, additional +properties must be described (they only exist if the GIC is the +primary interrupt controller). + +Required properties: + +- reg : Additional regions specifying the base physical address and + size of the VGIC registers. The first additional region is the GIC + virtual interface control register base and size. The 2nd additional + region is the GIC virtual cpu interface register base and size. + +- interrupts : VGIC maintenance interrupt. + +Example: + + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + +* GICv2m extension for MSI/MSI-x support (Optional) + +Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). +This is enabled by specifying v2m sub-node(s). + +Required properties: + +- compatible : The value here should contain "arm,gic-v2m-frame". + +- msi-controller : Identifies the node as an MSI controller. + +- reg : GICv2m MSI interface register base and size + +Optional properties: + +- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect + value, this property should contain the SPI base of + the MSI frame, overriding the HW value. + +- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect + value, this property should contain the number of + SPIs assigned to the frame, overriding the HW value. + +Example: + + interrupt-controller@e1101000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + interrupts = <1 8 0xf04>; + ranges = <0 0 0 0xe1100000 0 0x100000>; + reg = <0x0 0xe1110000 0 0x01000>, + <0x0 0xe112f000 0 0x02000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + v2m0: v2m@0x8000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0 0x1000>; + }; + + .... + + v2mN: v2m@0x9000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0 0x1000>; + }; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 555a1bcb5460..ab69f402e2f2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -217,6 +217,10 @@ dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \ endif endif +dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ + sdxnightjar-cdp.dtb \ + sdxnightjar-qrd.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/sdxnightjar-cdp.dts b/qcom/sdxnightjar-cdp.dts new file mode 100644 index 000000000000..58a5bf7cdc99 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR CDP"; + compatible = "qcom,sdxnightjar-cdp", + "qcom,sdxnightjar", "qcom,cdp"; + qcom,board-id = <0x01 0>; +}; diff --git a/qcom/sdxnightjar-cdp.dtsi b/qcom/sdxnightjar-cdp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-mtp.dts b/qcom/sdxnightjar-mtp.dts new file mode 100644 index 000000000000..65e7fcd1c964 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/qcom/sdxnightjar-mtp.dtsi b/qcom/sdxnightjar-mtp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi new file mode 100644 index 000000000000..410f4f9b0700 --- /dev/null +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -0,0 +1,1335 @@ +&soc { + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,sdxnightjar-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_console_active: uart1_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio92"; + function = "qdss_cti"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart2_console_active: uart2_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_active: uart3_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_sleep: uart3_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + bmi160_int1_default: bmi160_int1_default { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + bmi160_int2_default: bmi160_int2_default { + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_sdio_active: cnss_sdio_active { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_sdio_sleep: cnss_sdio_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SMB CONFIGURATION */ + pmx_smb_stat { + smb_stat_active: smb_stat_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio64"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0_mdm2apstatus_default: pcie0_mdm2apstatus_default { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* UART HS CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_active: blsp1_uart4_active { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_sleep: blsp1_uart4_sleep { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_active: blsp1_uart4b_active { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_sleep: blsp1_uart4b_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + mdss_cs_active: mdss_cs_active { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_cs_sleep: mdss_cs_sleep { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_active: mdss_te_active { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_sleep: mdss_te_sleep { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_active: mdss_rs_active { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_sleep: mdss_rs_sleep { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_active: mdss_ad_active { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_sleep: mdss_ad_sleep { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_bl_active: mdss_bl_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + output-high; + }; + }; + + mdss_bl_sleep: mdss_bl_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + output-low; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s_data1_a"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s_data0_a"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s_data1_a"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s_data0_a"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_b_aux { + sec_ws_b_sleep: sec_ws_b_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_b_sleep: sec_sck_b_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_b_sleep: sec_dout_b_sleep { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_b_active_master: sec_ws_b_active_master { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_b_active_master: sec_sck_b_active_master { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_b_active_slave: sec_ws_b_active_slave { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_b_active_slave: sec_sck_b_active_slave { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_b_active: sec_dout_b_active { + mux { + pins = "gpio22"; + function = "sec_mi2s_data1_b"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_b_aux_din { + sec_din_b_sleep: sec_din_b_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_b_active: sec_din_b_active { + mux { + pins = "gpio21"; + function = "sec_mi2s_data0_b"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_wlan_gpio { + sdc1_wlan_gpio_active: sdc1_wlan_gpio_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc1_wlan_gpio_sleep: sdc1_wlan_gpio_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + pinctrl_pps: ppsgrp { + mux { + pins = "gpio39"; + function = "nav_dr"; + }; + + config { + pins = "gpio39"; + bias-pull-down; + }; + }; + + can_reset { + can_rst_on: rst_on { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + can_rst_off: rst_off { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + output-high; + }; + }; + }; + }; +}; diff --git a/qcom/sdxnightjar-qrd.dts b/qcom/sdxnightjar-qrd.dts new file mode 100644 index 000000000000..287997958419 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR QRD"; + compatible = "qcom,sdxnightjar-qrd", + "qcom,sdxnightjar", "qcom,qrd"; + qcom,board-id = <0xB 0>; +}; diff --git a/qcom/sdxnightjar-qrd.dtsi b/qcom/sdxnightjar-qrd.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi new file mode 100644 index 000000000000..ad15a0902055 --- /dev/null +++ b/qcom/sdxnightjar.dtsi @@ -0,0 +1,429 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; + compatible = "qcom,sdxnightjar"; + qcom,msm-id = <484 0x10000>; + interrupt-parent = <&intc>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + chosen { }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + peripheral1_mem: peripheral1_region@0x87800000 { + no-map; + reg = <0x87800000 0x400000>; + label = "peripheral1_mem"; + }; + + peripheral2_mem: peripheral2_region@0x87d00000 { + no-map; + reg = <0x87d00000 0x300000>; + label = "peripheral2_mem"; + }; + }; + + aliases { }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x004a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x8600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x8600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + }; + + clock_gcc: qcom,gcc@1800000 { + ompatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_debug: qcom,cc-debug@1874000 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,clock-a7@0b010008 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + /*TODO: Fix the clock when tree is available*/ + clock-names = "cpu0_clk", "cpu1_clk", + "cpu2_clk", "cpu3_clk"; + qcom,cpufreq-table = + < 200000 >, + < 300000 >, + < 384000 >, + < 600000 >, + < 787200 >, + < 998400 >, + < 1190400 >, + < 1286400 >; + }; + + ahb_clk: qcom,ahb-clk-src { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + /*TODO: Fix the clock when tree is available*/ + governor = "powersave"; + freq-tbl-khz = + < 19200 >, + < 50000 >, + < 100000 >, + < 133330 >; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x0193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xb021000 0x1000>, + <0xb022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xb023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xb024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xb025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xb026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xb027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xb028000 0x1000>; + status = "disabled"; + }; + + frame@b029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xb029000 0x1000>; + status = "disabled"; + }; + }; + + + + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + /*TODO: Fix the clock when tree is available*/ + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@08600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + qcom,qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <171430000>; + }; + + qcom,qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_seecom: qseecom@87800000 { + compatible = "qcom,qseecom"; + reg = <0x87800000 0x200000>; + reg-names = "secapp-region"; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 200000 400000>, + <47 512 300000 800000>, + <47 512 400000 1000000>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = <0 107 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b1000 0x200>; + interrupts = <0 109 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <1 3 0>, <1 2 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + jtag_mm0: jtagmm@842000 { + compatible = "qcom,jtag-mm"; + reg = <0x842000 0x1000>, + <0x840000 0x1000>; + reg-names = "etm-base","debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "core_a_clk"; + }; + + qcom,smem@87e80000 { + compatible = "qcom,smem"; + reg = <0x87e80000 0xc0000>, + <0xb011008 0x4>, + <0x60000 0x6000>, + <0x193d000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1000>; + interrupts = <0 25 1>; + label = "modem"; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + qcom,irq-no-suspend; + qcom,not-loadable; + }; + }; + + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = <0 190 0>; + qcom,pmic-arb-channel = <0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-max-peripherals = <256>; + qcom,pmic-arb-max-periph-interrupts = <256>; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + }; +}; + +#include "sdxnightjar-pinctrl.dtsi" From 89db130d8d46284775595eea53cf067cb465f621 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Tue, 27 Oct 2020 14:00:23 +0530 Subject: [PATCH 0306/1809] ARM: dts: msm: Enable touch for Dual DSI video mode on shima Enable touch for Dual DSI video mode panel on shima target. Change-Id: I4d7316f34d6e9a2051213435bfe22a576e667ba7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index dd34ac6cbd57..584af558244e 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -217,7 +217,8 @@ irq-gpios = <&tlmm 23 0x2008>; atmel,panel-coords = <0 0 479 799>; atmel,display-coords = <0 0 339 729>; - panel = <&dsi_sharp_qhd_plus_dsc_cmd>; + panel = <&dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; From c5c105b971b841dcf7292bcf37d8dcd63656e006 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 13 Nov 2020 09:30:05 -0800 Subject: [PATCH 0307/1809] ARM: dts: msm: update PCIe1 to support m.2 and generic EP on lahaina HDK PCIe1 on lahaina HDK has a m.2 interface which requires additional settings such as gpio to control the 3.3V, increased timeout for linking up, and having PCIe enumerate during its probe. Endpoints which connect to this slot will not manually trigger PCIe bus driver to do enumeration. Therefore update devicetree node to support PCIe1 on lahaina HDK. Change-Id: I533b6e51c81a80085833c53b7aa2500e2307b2db --- qcom/lahaina-hdk.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 005e4ff816c5..6af3c39a4c7a 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -184,3 +184,9 @@ }; }; }; + +&pcie1 { + qcom,link-check-max-count = <50>; + qcom,ep-gpio = <&tlmm 6 0>; + qcom,boot-option = <0x0>; +}; From ac729f1e9ef1277acf10f81100a8dbb28d748e11 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Fri, 13 Nov 2020 09:15:41 -0800 Subject: [PATCH 0308/1809] ARM: dts: qcom: update JEITA FCC threshold for alium 3600mAh battery Alium battery 3600mAh can support only 3.6 A (1C rate) consistently. Hence update JEITA FCC threshold for it. Change-Id: Ic3b3eb63391378096ccbc6cfda400042536ffac9 --- qcom/qg-batterydata-alium-3600mah.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/qg-batterydata-alium-3600mah.dtsi b/qcom/qg-batterydata-alium-3600mah.dtsi index 051f64164fb2..4ade2fcaa7af 100644 --- a/qcom/qg-batterydata-alium-3600mah.dtsi +++ b/qcom/qg-batterydata-alium-3600mah.dtsi @@ -10,7 +10,7 @@ qcom,alium_860_89032_0000_3600mAh { qcom,qg-batt-profile-ver = <100>; qcom,jeita-fcc-ranges = <0 50 2500000 - 51 400 5400000 + 51 400 3600000 401 450 2500000>; qcom,jeita-fv-ranges = <0 50 4250000 51 400 4350000 From 7ee3b14e737c94b3ac9e116e26f29649ab9b17d9 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 5 Nov 2020 13:28:59 +0530 Subject: [PATCH 0309/1809] ARM: dts: msm: Update the rpm-smd node with correct IRQ for holi Update the rpm-smd node with proper glink-rpm irq so that rpm driver can mask the glink-rpm interrupt while going to APSS deep sleep. Change-Id: I1823ce98a2c1cd0586a2f68d1610edae5bb2f0d7 --- qcom/holi.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 25f8b9134b21..9b119fb91ea6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -979,7 +979,10 @@ rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; - interrupts = ; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; From 16dff9f88fab83ffa5b90fc513f99daf85f21d0b Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 19 Oct 2020 20:13:59 +0530 Subject: [PATCH 0310/1809] ARM: dts: qcom: Change cci3 gpio function from cci to gpio Configure the gpio pins for cci3 from cci control to gpio. Change-Id: I34fc8c7ae77ae42bc47a291db13fccd80671fd65 --- qcom/holi-pinctrl.dtsi | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/qcom/holi-pinctrl.dtsi b/qcom/holi-pinctrl.dtsi index 07f202cf86a7..7ef2bf71ba05 100644 --- a/qcom/holi-pinctrl.dtsi +++ b/qcom/holi-pinctrl.dtsi @@ -809,34 +809,6 @@ }; }; - cci3_active: cci3_active { - mux { - /* CLK, DATA */ - pins = "gpio2", "gpio3"; - function = "CCI_I2C"; - }; - - config { - pins = "gpio2", "gpio3"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci3_suspend: cci3_suspend { - mux { - /* CLK, DATA */ - pins = "gpio2", "gpio3"; - function = "CCI_I2C"; - }; - - config { - pins = "gpio2", "gpio3"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK 0*/ mux { From c1f6098935d0f579501300c25d34c8b5a921f7da Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 9 Nov 2020 21:23:44 +0530 Subject: [PATCH 0311/1809] ARM: dts: msm: Add pmd9650 gpio nodes for SDXNIGHTJAR Add pmd9650 nodes and include pmic devicetree files in target specific files. Change-Id: Ia19f577dc8a295dabd20ce4089dca553b9e881e8 --- qcom/sdxnightjar-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 3 +++ 2 files changed, 31 insertions(+) diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index 410f4f9b0700..fe045ec0167e 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -1,3 +1,5 @@ +#include + &soc { tlmm_pinmux: pinctrl@1000000 { compatible = "qcom,sdxnightjar-pinctrl"; @@ -1333,3 +1335,29 @@ }; }; }; + +&pmd9650_gpios { + gpio@c100 { /* GPIO 2 - VADC */ + /* GPIO should be left off, and in the high + * impedance state when the pin is used with the VADC + */ + pins = "gpio2"; + function = "normal"; + bias-high-impedance; /* DISABLE GPIO */ + }; + + gpio@c200 { /* GPIO 3 - LED */ + pins = "gpio3"; + function = "normal"; + bias-high-impedance; /* DISABLE GPIO */ + }; + + gpio@c400 { /* GPIO 5 - USB_ID */ + pins = "gpio5"; + function = "normal"; + input-enable; /* Digital input */ + bias-pull-up; + qcom,pull-up-strength = ; /* Pull up 1.5 uA */ + power-source = <1>; /* 1.8 V */ + }; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index ad15a0902055..622d46a7c381 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -426,4 +426,7 @@ }; }; +#include "pmd9650.dtsi" +#include "pmd9650-rpm-regulator.dtsi" +#include "sdxnightjar-regulator.dtsi" #include "sdxnightjar-pinctrl.dtsi" From 1ce3af36b4f4e50507d868323105f72835786641 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 9 Nov 2020 16:01:00 +0530 Subject: [PATCH 0312/1809] ARM: dts: msm: Change the node location for optimise Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Change-Id: I655c0ff8ac720c16b61da680b8e389585b5a01a6 --- qcom/holi.dtsi | 341 +++++++++++++++++++++++++------------------------ 1 file changed, 172 insertions(+), 169 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e106fc3161c4..9487018bbdad 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -22,7 +22,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -238,173 +244,6 @@ }; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_mem@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - smem_mem: smem@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - fw_mem: fw_mem@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_wlan_mem: wlan@86500000 { - no-map; - reg = <0x0 0x86500000 0x0 0x200000>; - }; - - pil_adsp_mem: adsp@86700000 { - no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; - }; - - pil_cdsp_mem: cdsp@88f00000 { - no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; - }; - - pil_camera_mem: camera@8ad00000 { - no-map; - reg = <0x0 0x8ad00000 0x0 0x500000>; - }; - - pil_video_mem: video@8b200000 { - no-map; - reg = <0x0 0x8b200000 0x0 0x500000>; - }; - - pil_ipa_fw_mem: ipa_fw@8b700000 { - no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: ipa_gsi@8b710000 { - no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; - }; - - pil_mpss_wlan_mem: mpss_wlan@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - removed_mem: removed_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x5100000>; - }; - - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x5c00000>; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x800000>; - }; - - splash_memory: splash_region@0x85200000 { - reg = <0x0 0x85200000 0x0 0x00c00000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region@85e00000 { - reg = <0x0 0x85e00000 0x0 0x00100000>; - label = "dfps_data_region"; - }; - - qcom: ramoops { - compatible = "ramoops"; - reg = <0x0 0xd0000000 0x0 0x200000>; - pmsg-size = <0x200000>; - mem-type = <2>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x800000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - }; soc: soc { }; @@ -446,9 +285,173 @@ reg = <0x0 0x0 0x0 0x80>; }; }; +}; - chosen { - bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_wlan_mem: wlan@86500000 { + no-map; + reg = <0x0 0x86500000 0x0 0x200000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: camera@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: video@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + splash_memory: splash_region@0x85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@85e00000 { + reg = <0x0 0x85e00000 0x0 0x00100000>; + label = "dfps_data_region"; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; }; }; From 0529d8ca2f1c8310cd54f1aa6c33c0cd11cc3e24 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 9 Nov 2020 16:35:19 +0530 Subject: [PATCH 0313/1809] ARM: dts: msm: Move firmware node ahead Bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: Iae35be08cae1e514d6b6ad051e5e42137f99db8b --- qcom/holi.dtsi | 55 +++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 9487018bbdad..8053abd609dd 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -49,6 +49,8 @@ swr1 = &swr1; }; + firmware: firmware {}; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -244,35 +246,8 @@ }; }; - soc: soc { }; - firmware: firmware { - scm { - compatible = "qcom,scm"; - }; - - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; - }; - }; - }; - sram: sram@fd04480 { #address-cells = <2>; #size-cells = <2>; @@ -287,6 +262,32 @@ }; }; +&firmware { + scm { + compatible = "qcom,scm"; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; +}; + &reserved_memory { #address-cells = <2>; #size-cells = <2>; From 77fb1250c0c640d388d87f94cc0f261dcba71bca Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Tue, 17 Nov 2020 16:56:35 +0800 Subject: [PATCH 0314/1809] ARM: dts: msm: add touch for 144hz panel Add new 144Hz panel node for Lahaina devices. Change-Id: I271b0740d6f274c7312f57726b4c35a359f0d937 --- qcom/lahaina-cdp.dtsi | 2 +- qcom/lahaina-mtp.dtsi | 2 +- qcom/lahaina-qrd-common.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 4989e97dd77e..3ef0db6a20c7 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -101,7 +101,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 39f56296aed0..9efb33e86994 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -103,7 +103,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 692d5fa395b6..c5a0bb9fc7ab 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -204,7 +204,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 7a99e2e0d8e037a81ee7312e21e4b27cf4b454c5 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 14 Sep 2020 16:40:38 +0530 Subject: [PATCH 0315/1809] dt-bindings: clock: Add support for YUPIK clock controllers Update the GCC, GPUCC, CAMCC, DISPCC, VIDEOCC and debug clock controller bindings for YUPIK device. Change-Id: Id5e12fa1671030dc183b7a9cabda7a9dca198f52 --- bindings/clock/qcom,camcc.txt | 1 + bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 11 ++++++----- bindings/clock/qcom,videocc.txt | 1 + 6 files changed, 11 insertions(+), 5 deletions(-) diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index b9e3105751a5..cc72c85575d0 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-camcc-v2" "qcom,sa8155-camcc" "qcom,sa8155-camcc-v2" + "qcom,yupik-camcc" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index c7d82f90a3c8..59290aa6d1a4 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" "qcom,sm8150-debugcc" + "qcom,yupik-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index 80bbef3710ec..8341e8b8c742 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,holi-dispcc" "qcom,sm8150-dispcc" "qcom,sm8150-dispcc-v2" + "qcom,yupik-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index f72a8ff537e6..c15e9b6800b7 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -31,6 +31,7 @@ Required properties : "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" + "qcom,yupik-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 726c24257d24..efd611826979 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -3,11 +3,12 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", - "qcom,lahaina-gpucc", - "qcom,shima-gpucc", - "qcom,holi-gpucc", - "qcom,sm8150-gpucc", - "qcom,sa8155-gpucc". + "qcom,lahaina-gpucc" + "qcom,shima-gpucc" + "qcom,holi-gpucc" + "qcom,sm8150-gpucc" + "qcom,sa8155-gpucc" + "qcom,yupik-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index e46fa2db829b..64f41ad07942 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-videocc-v2" "qcom,sa8155-videocc" "qcom,sa8155-videocc-v2" + "qcom,yupik-videocc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. From 6638f17f131be817cf9bcf80d162874557e8c0e3 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 13 Nov 2020 16:04:36 -0800 Subject: [PATCH 0316/1809] ARM: dts: msm: Add eMMC device tree files for sdxlemur Add eMMC device tree files for sdxlemur. Change-Id: I834b09d948478862fe6191a62e3e8c8db2bb3eae --- qcom/sdxlemur-mtp-mbb-emmc.dts | 12 ++++++++++++ qcom/sdxlemur-mtp-mbb-emmc.dtsi | 6 ++++++ 2 files changed, 18 insertions(+) create mode 100644 qcom/sdxlemur-mtp-mbb-emmc.dts create mode 100644 qcom/sdxlemur-mtp-mbb-emmc.dtsi diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts new file mode 100644 index 000000000000..acdb4853a32a --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -0,0 +1,12 @@ +/dts v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-emmc.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010108 0> +}; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi new file mode 100644 index 000000000000..768d9aaa521c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -0,0 +1,6 @@ +#include "sdxlemur-pmic-overlay.dtsi" + +&soc { + +}; + From de5645824c27c1925164f3958ed221c3add4ae01 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 17 Nov 2020 08:25:43 -0800 Subject: [PATCH 0317/1809] ARM: dts: msm: Include sdxlemur-mtp dt on all mtp trees Added include statement for the sdxlemur-mtp device tree on all the mtp device trees. Change-Id: Id6e72b0095c36b0601d7046b72b49ba6e50f14ec --- qcom/sdxlemur-mtp-cpe.dtsi | 2 +- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 2 +- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 2 +- qcom/sdxlemur-mtp-mbb.dtsi | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index cc3a833f430e..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..25ea231003cb 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,5 +1,5 @@ -#include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" +#include "sdxlemur-mtp.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; From f0605f94d47d17ecc111b056ae32ffcf704127fb Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 17 Nov 2020 22:23:19 +0530 Subject: [PATCH 0318/1809] bindings: SMB358: Add documentation for smb358 charger Add snapshot of smb358 charger documentation from msm-4.14 'commit 50f9f83dd79b ("Merge "defconfig : Enable pinctrl and clock driver for SA8195"")'. SMB358 is a single-cell battery charger. It can charge the battery and power the system via the USB/AC adapter input. Change-Id: Id3aef2dab81a67061d728f661ce568917e86b08e --- bindings/power/supply/qcom/smb358-charger.txt | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 bindings/power/supply/qcom/smb358-charger.txt diff --git a/bindings/power/supply/qcom/smb358-charger.txt b/bindings/power/supply/qcom/smb358-charger.txt new file mode 100644 index 000000000000..55c2ced3f877 --- /dev/null +++ b/bindings/power/supply/qcom/smb358-charger.txt @@ -0,0 +1,106 @@ +Summit smb358 battery charger + +SMB358 is a single-cell battery charger. It can charge +the battery and power the system via the USB/AC adapter input. + +The smb358 interface is via I2C bus. + +Required Properties: +- compatible Must be "qcom,smb358-charger". +- reg The device 7-bit I2C address. +- interrupt-parent parent of interrupt. +- interrupts This indicates the IRQ number of the GPIO + connected to the STAT pin. +- qcom,irq-gpio GPIO which receives interrupts from STAT output. +- qcom,bms-psy-name This is a string and it points to the bms + power supply name. +- qcom,float-voltage-mv Float Voltage in mV - the maximum voltage up to which + the battery is charged. Supported range 3500mV to 4500mV + +Optional Properties: + +- qcom,fastchg-current-max-ma Fast Charging current in mA. Supported range is + from 200mA to 2000mA. +- qcom,chg-valid-gpio GPIO which indicates the charger presence. + This GPIO is connected to the SYSOK pin. +- qcom,chg-autonomous-mode This is a bool property and it indicates that the + charger is configured for autonomous operation and + does not require any software configuration. +- qcom,disable-apsd This is a bool property which disables automatic + power source detection (APSD). If this is set + charger detection is done by DCIN UV irq. +- qcom,charger-disabled This is a bool property which disables charging. +- qcom,using-pmic-therm This property indicates thermal pin connected to pmic or smb. +- qcom,vcc-i2c-supply Power source required to power up i2c bus. +- qcom,bms-controlled-charging This property indicates integrating with VMBMS, charger + driver and BMS communicates with each other via power_supply + framework. Property "qcom,iterm-disabled" also needs defined + if using this feature to make sure that the charger doesn't + terminate charging on its own. +- qcom,iterm-ma Specifies the termination current to indicate end-of-charge. + Possible values in mA - 30, 40, 60, 80, 100, 125, 150, 200. +- qcom,iterm-disabled Disables the termination current feature. This is a bool + property. +- qcom,recharge-mv Recharge threshold in mV - the offset from the float-volatge + as which the charger restarts charging. Possible + values are 50mV to 300mV. +- qcom,recharge-disabled Boolean value which disables the auto-recharge. +- qcom,chg-inhibit-disabled This is a bool property which disables charger inhibit. + Charger inhibit option prevents battery charging upon insertion + of the charger when battery voltage is above the programmed inhibit + threshold. +- qcom,chg-adc_tm phandle to the corresponding VADC device to read the ADC channels. +- qcom,cold-bat-decidegc Cold battery temperature in decidegC. +- qcom,hot-bat-decidegc Hot battery temperature in decidegC. +- qcom,bat-present-decidegc This is a property indicating battery present temperature, if + higher than it, battery should exist. Default value is negative, + if this property is 200, it stands for -200 decidegC. +- qcom,warm-bat-decidegc: Warm battery temperature in decidegC. After hitting this threshold, + "qcom,warm-bat-ma" defines maximum charging current and + "qcom,warm-bat-mv" defines maximum target voltage. +- qcom,cool-bat-decidegc: Cool battery temperature in decidegC. After hitting this threshold, + "qcom,cool-bat-ma" defines maximum charging current and + "qcom,cool-bat-mv" defines maximum target voltage. +- qcom,warm-bat-ma: Maximum warm battery charge current in milli-amps. +- qcom,cool-bat-ma: Maximum cool battery charge current in milli-amps. +- qcom,warm-bat-mv: Maximum warm battery target voltage in milli-volts. +- qcom,cool-bat-mv: Maximum cool battery target voltage in milli-volts. +- qcom,chg-vadc Corresponding VADC device's phandle. +- qcom,skip-usb-suspend-for-fake-battery: A boolean property to skip suspending USB path for fake + battery. If this property is not present then 'qcom,batt-id-vref-uv' and + 'qcom,batt-id-rpullup-kohm' should be present. +- qcom,batt-id-vref-uv The reference voltage on the battery-ID line + specified in micro-volts. +- qcom,batt-id-rpullup-kohm The pull-up resistor connected on the battery-ID + (vref) line. +- qcom,using-vbat-sns Bool property to indicate that VBAT sense can be + done by PMIC. + +Example: + i2c@f9967000 { + smb358-charger@1b { + compatible = "qcom,smb358-charger"; + reg = <0x1b>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x0>; + qcom,irq-gpio = <&msmgpio 17 0x00>; + qcom,vcc-i2c-supply = <&pm8226_lvs1>; + qcom,float-voltage-mv = <4350>; + qcom,disable-apsd; + qcom,chg-inhibit-disabled; + qcom,bms-controlled-charging; + qcom,fastchg-current-max-ma = <1500>; + qcom,bms-psy-name = "bms"; + qcom,chg-vadc = <&pm8226_vadc>; + qcom,chg-adc_tm = <&pm8226_adc_tm>; + qcom,hot-bat-decidegc = <500>; + qcom,cold-bat-decidegc = <0>; + qcom,bat-present-decidegc = <200>; + qcom,warm-bat-decidegc = <450>; + qcom,cool-bat-decidegc = <100>; + qcom,warm-bat-ma = <350>; + qcom,cool-bat-ma = <350>; + qcom,warm-bat-mv = <4200>; + qcom,cool-bat-mv = <4200>; + }; + }; From 6f9c6f456548b65206336cff7309d3f9d085e5ef Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 9 Nov 2020 10:05:35 +0530 Subject: [PATCH 0319/1809] ARM: dts: msm: Add IOMMU Geometry property for storage Add IOMMU Geometry property to help save SMMU page table memory saving for UFS/eMMC. No functional change but helps saving memory table space. Change-Id: I94f9c4c58ca58f3491209bb8f12c1f080810dceb --- qcom/holi.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 34fd9f97a15b..3f6054571a56 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2111,6 +2111,23 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "fastmap"; + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; @@ -2137,6 +2154,24 @@ iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; From 1b866d34e2c5eb8f9597a9ae9f2bdaa8cec0935b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 17:10:28 -0700 Subject: [PATCH 0320/1809] ARM: dts: msm: add MX entries for PCIe on sdxlemur To properly support PCIe Gen4 on sdxlemur, PCIe needs to vote and scale MX rails accordingly. Add the required MX entries to enable PCIe bus driver to do so for sdxlemur. Change-Id: Ia56142013d07c9a811f5357e8ce29fdb3c76dd39 --- qcom/sdxlemur-pcie.dtsi | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ea8fedc36bb..2ab0fd2ceba7 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -46,15 +46,30 @@ vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen4 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From d37c0931341137a01ea913b0c3c584bc31a7af34 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:24:01 -0700 Subject: [PATCH 0321/1809] dt-bindings: arm: msm: add support for tuning PCIe EQ Master Phase Add DT entry to determine the minimum amount of time PCIe needs to remain in equalization master phase. Change-Id: I14f0e0b28dd69b8b38ac7be1cae282635ef11fe5 --- bindings/pci/pci-msm.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 6c6285f4e714..6f3e41eac5bc 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -290,6 +290,13 @@ interconnects: Definition: L1.2 LTR threshold value to be multipled with scale to define L1.2 latency tolerance reporting (LTR) +- qcom,eq-fmdc-t-min-phase23: + Usage: optional + Value type: + Definition: Determines minimum time (ms) to remain in equalization + master phase before checking for convergence of the + coefficients. + - qcom,slv-addr-space-size: Usage: required Value type: @@ -519,6 +526,7 @@ Example qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; + qcom,eq-fmdc-t-min-phase23 = <1>; /* 1ms */ qcom,slv-addr-space-size = <0x1000000>; /* 16MB */ qcom,wr-halt-size = <0xa>; /* 1KB */ qcom,tlp-rd-size = <0x5>; /* 4KB */ From 08a5b7bc69e8ee92fca57e0e1824f0ddd9cf87e3 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:27:46 -0700 Subject: [PATCH 0322/1809] ARM: dts: msm: keep PCIe in EQ Master Phase for at least 1ms on sdxlemur PCIe PHY on sdxlemur requires the equalization master phase of link training to be at least 1ms long before proceeding to the next LTSSM state. Add the corresponding DT entry to configure the controller to meet this requirement on sdxlemur. Change-Id: Ied893d27cdc7a62c8a9284a9f16348ab8122094a --- qcom/sdxlemur-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ab0fd2ceba7..9e13fe07f23d 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -107,6 +107,7 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From fc54767186df903ef76cfcaf3315bf4773e8358d Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 11 Nov 2020 21:06:43 +0530 Subject: [PATCH 0323/1809] ARM: dts: msm: Remove display clock as client for CX SDPM for SHIMA Remove display clock as client for CX sdpm configuration for SHIMA as support not available. Change-Id: Ifabe6c7c5554179185e7a60cdc2dda0b3ec95619 --- qcom/shima-thermal.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 0568cabd69b5..6a5999deec8b 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -79,14 +79,12 @@ cx_sdpm@0x00634000 { compatible = "qcom,sdpm"; reg = <0x00634000 0x1000>; - clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0"; clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&videocc VIDEO_CC_MVS0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&videocc VIDEO_CC_MVS0_CLK_SRC>; cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; - disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; - csr-id = <0 2 5>; + csr-id = <0 2>; }; mx_pe: mx_rdpm_pe@0x00637000 { From 772f7eedab05a02fd04a5831bdbaa8eebdca578b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 17 Nov 2020 00:28:27 +0530 Subject: [PATCH 0324/1809] ARM: dts: qcom: Update skin and cx thermal config for HOLI Add quiet-therm,pa-therm0 and xo-therm skin sensors thermal config for HOLI based on latest recomondations. Add q6-hvx sensor thermal config mitigation for HOLI based on latest recomondations. Change-Id: If534b2c11786f89e165f3bae28b1f4b8c927c1ce --- qcom/holi-qrd.dtsi | 201 +++++++++++++++++++++++++++++++++++++---- qcom/holi-thermal.dtsi | 35 +++---- 2 files changed, 199 insertions(+), 37 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 776be0b0286c..e941e3c47126 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -326,64 +326,231 @@ &thermal_zones { quiet-therm-step { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; - trips { - quiet_modem_trip0: quiet-modem-trip0 { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { temperature = <42000>; hysteresis = <4000>; type = "passive"; }; - quiet_modem_trip1: quiet-modem-trip1 { + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { temperature = <44000>; hysteresis = <4000>; type = "passive"; }; - quiet_cx_trip: quiet-cx-trip { - temperature = <55000>; - hysteresis = <5000>; + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; type = "passive"; }; - quiet_modem_trip2: quiet-modem-trip2 { - temperature = <56000>; + battery_trip2: battery-trip2 { + temperature = <46000>; hysteresis = <2000>; type = "passive"; }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { - gpu-cdev { - trip = <&quiet_cx_trip>; + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; /* throttle to 565000000Hz */ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cdev0 { - trip = <&quiet_cx_trip>; - cooling-device = <&cdsp_sw 4 4>; + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; modem-skin-cdev0 { - trip = <&quiet_modem_trip0>; + trip = <&modem_skin_trip0>; cooling-device = <&modem_skin 1 1>; }; modem-skin-cdev1 { - trip = <&quiet_modem_trip1>; + trip = <&modem_skin_trip1>; cooling-device = <&modem_skin 2 2>; }; modem-skin-cdev2 { - trip = <&quiet_modem_trip2>; + trip = <&cx_trip>; cooling-device = <&modem_skin 3 3>; }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; }; }; }; diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index 13cb49406f32..c98479d3b71a 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -905,13 +905,13 @@ thermal-governor = "step_wise"; trips { - cdsp_trip0: cdsp-trip0 { + q6_hvx_trip0: q6-hvx-trip0 { temperature = <95000>; hysteresis = <0>; type = "passive"; }; - cdsp_cx_mon: cdsp-cx-mon { + q6_hvx_cx_mon: q6-hvx-cx-mon { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -919,32 +919,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&cdsp_trip0>; + q6-hvx-cdev0 { + trip = <&q6_hvx_trip0>; cooling-device = <&cdsp_sw THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; - cdsp-cx-cdev0 { - trip = <&cdsp_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cx-cdev1 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_tj 3 3>; + q6-hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_skin 3 3>; }; - cdsp-cx-cdev2 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_pa 3 3>; - }; - - cdsp-cx-cdev3 { - trip = <&cdsp_cx_mon>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&cdsp_sw 4 4>; }; }; }; From be7a27fb2acad63617ee9013c3df6e3621cb7d5b Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Wed, 18 Nov 2020 09:40:28 -0800 Subject: [PATCH 0325/1809] ARM: dts: msm: Turn off KPTI for Lahaina Kernel Page Table Isolation (KPTI) is a software workaround technique used to mitigate the meltdown security vulnarability. Since Lahaina hardware is meltdown safe, it can safely turn off the feature. Hence, turn the KPTI off via its command line option. Change-Id: Idc469ce6804e53073860c32a2635ca9c8f479fe3 --- qcom/lahaina.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 53e480f7cdcd..fae512ee7191 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -34,7 +34,7 @@ #size-cells = <2>; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; From fd9c852a45e2f38a97fe542f6974e81665769c84 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 18 Nov 2020 12:47:56 -0800 Subject: [PATCH 0326/1809] ARM: dts: msm: Add PMX65 die temperature channel Add the appropriate ADC channel so that the pmx65_tz thermal zone may obtain the right value of PMIC die temperature for monitoring purposes. Change-Id: Ib67624ddcafc7e46d94e8b9ca83938bde32005b9 --- qcom/sdxlemur-pmic-overlay.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index ea528c0ccbbf..36bac4c770ee 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -62,6 +62,14 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + pmx65_die_temp { + reg = ; + label = "pmx65_die_temp"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; }; &pmk8350_adc_tm { @@ -216,3 +224,8 @@ nvmem-cell-names = "restart_reason"; }; }; + +&pmx65_tz { + io-channels = <&pmk8350_vadc PMX65_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; From 6cdfb0dd43265e023d6f44c4bd4cd722ce0f82b1 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Thu, 5 Nov 2020 15:48:18 +0530 Subject: [PATCH 0327/1809] ARM: dts: msm: Add QUPv3 SE and GPI DT nodes for yupik Add QUPv3(I2C, SPI and UART) and GPI DT node on yupik Change-Id: I6f62861c20f8c3778d087506efea75bd52957d78 --- qcom/yupik-pinctrl.dtsi | 1005 +++++++++++++++++++++++++++++++++++++++ qcom/yupik-qupv3.dtsi | 735 ++++++++++++++++++++++++++++ 2 files changed, 1740 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 01404eb41ded..acc672a31e62 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -9,6 +9,306 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "qup02"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup02"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup03"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "qup03"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { qupv3_se5_2uart_active: qupv3_se5_2uart_active { mux { @@ -36,5 +336,710 @@ }; }; }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { + qupv3_se7_default_cts: + qupv3_se7_default_cts { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_default_rtsrx: + qupv3_se7_default_rtsrx { + mux { + pins = "gpio29", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio29", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_default_tx: + qupv3_se7_default_tx { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_ctsrx: qupv3_se7_ctsrx { + mux { + pins = "gpio28", "gpio31"; + function = "qup07"; + }; + + config { + pins = "gpio28", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rts: qupv3_se7_rts { + mux { + pins = "gpio29"; + function = "qup07"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_tx: qupv3_se7_tx { + mux { + pins = "gpio30"; + function = "qup07"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup10"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup10"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup11"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup11"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup12"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_default_txrx: qupv3_se10_default_txrx { + mux { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_active: qupv3_se6_2uart_active { + mux { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup13"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup14"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup14"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup15"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup15"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup16"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se14_2uart_pins: qupv3_se14_2uart_pins { + qupv3_se14_default_txrx: qupv3_se14_default_txrx { + mux { + pins = "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_2uart_active: qupv3_se14_2uart_active { + mux { + pins = "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_2uart_sleep: qupv3_se14_2uart_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio60", "gpio61"; + function = "qup17"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup17"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + }; }; }; diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index a593d4406eda..4d11215b0327 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -1,6 +1,25 @@ #include &soc { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup0 0: SE 8 + * Qup0 1: SE 9 + * Qup0 2: SE 10 + * Qup0 3: SE 11 + * Qup0 4: SE 12 + * Qup0 5: SE 13 + * Qup0 6: SE 14 + * Qup0 7: SE 15 + */ + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,qupv3-geni-se"; @@ -16,6 +35,33 @@ status = "ok"; }; + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x136 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + /* Debug UART Instance */ qupv3_se5_2uart: qcom,qup_uart@994000 { compatible = "qcom,msm-geni-console"; @@ -32,4 +78,693 @@ qcom,wrapper-core = <&qupv3_0>; status = "ok"; }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se7_4uart: qcom,qup_uart@99c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x99c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se7_default_cts>, + <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; + pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + pinctrl-2 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x43 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x56 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se10_default_txrx>; + pinctrl-1 = <&qupv3_se10_2uart_active>; + pinctrl-2 = <&qupv3_se10_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + qcom,shared; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* Travel adapter over 2-wire HSUART, no wakeup */ + qupv3_se14_2uart: qcom,qup_uart@a98000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa98000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se14_default_txrx>; + pinctrl-1 = <&qupv3_se14_2uart_active>; + pinctrl-2 = <&qupv3_se14_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + dmas = <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + dmas = <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; }; From 2a4c9134a26d55779461649ec4668af49b9918df Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Mon, 16 Nov 2020 17:30:27 +0530 Subject: [PATCH 0328/1809] ARM: dts: msm: Enable SMMU and PSCI for scuba Enable SMMU, PSCI and correct compatible string for scuba 32 bit target. Change-Id: Ie4b35e7609d851146af4bb42ff46ff6ceae8cfe2 --- qcom/msm-arm-smmu-scuba.dtsi | 2 -- qcom/scuba-iot-idp-overlay.dts | 2 +- qcom/scuba-iot.dtsi | 6 ++++++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi index 2876f6370a71..bb960362ef1a 100644 --- a/qcom/msm-arm-smmu-scuba.dtsi +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -2,7 +2,6 @@ &soc { kgsl_smmu: kgsl-smmu@0x59a0000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0x59a0000 0x10000>, <0x59c2000 0x20>; @@ -40,7 +39,6 @@ }; apps_smmu: apps-smmu@0xc600000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0xc600000 0x80000>, <0xc782000 0x20>; diff --git a/qcom/scuba-iot-idp-overlay.dts b/qcom/scuba-iot-idp-overlay.dts index 7f356c2e6abf..1121781ca5f1 100644 --- a/qcom/scuba-iot-idp-overlay.dts +++ b/qcom/scuba-iot-idp-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Scuba IDP"; - compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp"; + compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp"; qcom,msm-id = <441 0x10000>, <471 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index cd431074d371..82571a44c271 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -9,6 +9,8 @@ #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&intc>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; mem-offline { @@ -120,6 +122,10 @@ }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; reserved-memory { #address-cells = <2>; From 9a381b30f80df711f5728cfb5b5d89c1b193562c Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 16 Nov 2020 12:27:36 +0530 Subject: [PATCH 0329/1809] ARM: dts: msm: Add scm pas node Add scm pas node for Yupik platform. Change-Id: Id1c1e3032a57a5aef617baa80eeacf4411bf6192 --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index cc04ff320e6e..fdb89bb4acec 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1154,6 +1154,11 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; }; + + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + }; }; #include "shima-gdsc.dtsi" From e3b04e8a9de01e77dab5baac52a954be29a3e245 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 29 Oct 2020 17:50:34 +0530 Subject: [PATCH 0330/1809] ARM: dts: msm: Add LPASS pil node for Yupik Add LPASS pil node to support LPASS subsystem for Yupik platform. Change-Id: I9d38b38f38e0fffa79844949d98fd9bf83ee6779 --- qcom/yupik.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index fdb89bb4acec..5da945d70e97 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Yupik"; @@ -1159,6 +1160,52 @@ compatible = "qcom,pil-tz-scm-pas"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + + qcom,lpass@3700000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x3700000 0x00100>; + + vdd_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "shima-gdsc.dtsi" From 775a317ccf30dbc4ec469789ec3f569ae79f2ffe Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 29 Oct 2020 18:05:26 +0530 Subject: [PATCH 0331/1809] ARM: dts: msm: Add CDSP pil node for Yupik Add CDSP pil node to support CDSP subsystem for Yupik. Change-Id: I9b21026a278aa3794e89ae5fac425a644035ab41 --- qcom/yupik.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 5da945d70e97..61a0912b69a1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1206,6 +1206,54 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + + qcom,turing@a300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xa300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "shima-gdsc.dtsi" From f2d0535fb897c9d585edf28a66c1a40e4358f671 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 11 Nov 2020 17:00:24 +0530 Subject: [PATCH 0332/1809] ARM: dts: msm: Enable eMMC for sdxlemur target Enable eMMC for sdxlemur target. Change-Id: I984fec01e0b99b189d1f2e299239336e77af966d --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 768d9aaa521c..0e75a90da2b4 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -4,3 +4,30 @@ }; +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; From 7840876856aa1dbdb2f38bcb7cb6b68038ca0c01 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 12 Nov 2020 21:54:40 -0800 Subject: [PATCH 0333/1809] ARM: dts: msm: update pm7250b devices for sdxlemur platforms Add necessary configurations needed for charger, QG, PD_PHY devices present on PM7250B to support sdxlemur platforms that uses them. Since, it needs some VADC channels from PM7250B, add them as well. Change-Id: I065f1365b7278a92e0a8646a32e955d5e168c70c --- qcom/sdxlemur-mtp-mbb.dtsi | 161 ++++++++++++++++++++++++++++++++++++- qcom/sdxlemur-rcm-rc.dtsi | 159 +++++++++++++++++++++++++++++++++++- 2 files changed, 317 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index c104dfebb64d..d477797ee914 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,5 +1,6 @@ -#include "pm7250b.dtsi" #include "sdxlemur-mtp.dtsi" +#include "pm7250b.dtsi" +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -7,7 +8,10 @@ }; &soc { - + mbb_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; &pcie0 { @@ -47,3 +51,156 @@ status = "disabled"; }; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&mbb_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&mbb_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 0eb9848df6f1..4293e321bd09 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,5 +1,6 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -7,7 +8,10 @@ }; &soc { - + rcm_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; &pcie0 { @@ -15,3 +19,156 @@ qcom,l1-2-th-scale = <2>; /* 1us */ qcom,l1-2-th-value = <70>; }; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&rcm_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&rcm_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; From 1b2dafb3b21057e091e44fb38f7d975abd319d0c Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 19 Nov 2020 17:49:23 -0800 Subject: [PATCH 0334/1809] ARM: dts: msm: add spmi_debug_bus for sdxlemur Add spmi_debug_bus so that PMIC peripherals can be accessed via debug bus on sdxlemur devices where the fuse is not blown. This is useful for debugging. Change-Id: Ica647e8eee31028d25363aec88dd102cc0780ab6 --- qcom/sdxlemur-mtp-mbb.dtsi | 11 +++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 11 +++++++++++ qcom/sdxlemur.dtsi | 28 ++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..de785008447c 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-mtp.dtsi" #include "pm7250b.dtsi" #include +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -14,6 +15,16 @@ }; }; +&spmi_debug_bus { + qcom,pm7250b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + &pcie0 { qcom,boot-option = <0x1>; qcom,l1-2-th-scale = <2>; /* 1us */ diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..79a7e4a576da 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" #include +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -14,6 +15,16 @@ }; }; +&spmi_debug_bus { + qcom,pm7250b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + &pcie0 { qcom,boot-option = <0x1>; qcom,l1-2-th-scale = <2>; /* 1us */ diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 6aa9e75a2eed..c761d1ea5c55 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -904,6 +905,33 @@ qcom,ee = <0>; }; + spmi_debug_bus: qcom,spmi-debug@6b12000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b12000 0x60>, <0x7820a8 0x4>; + reg-names = "core", "fuse"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmx65-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + thermal_zones: thermal-zones { }; From 156ccb23cf89a329f09dba621c1e2bc1236c9f61 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 3 Nov 2020 12:45:35 +0530 Subject: [PATCH 0335/1809] ARM: dts: msm: add gfx smmu node on yupik Add the SMMU devicetree node for gfx that can be used by the respective clients for VA to PA translations. Change-Id: Ib0894591aff1be8fcdf50b0d57f7533efc67350c --- qcom/msm-arm-smmu-yupik.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index 22ee8245eb6e..06c00b29cadf 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -2,7 +2,6 @@ &soc { kgsl_smmu: kgsl-smmu@3da0000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0x3da0000 0x20000>, <0x3dd6000 0x20>; @@ -10,11 +9,30 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,split-tables; #global-interrupts = <2>; #size-cells = <1>; #address-cells = <1>; ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , , , @@ -43,7 +61,6 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; - }; apps_smmu: apps-smmu@15000000 { @@ -216,14 +233,13 @@ }; kgsl_iommu_test_device { - status = "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x7 0>; qcom,iommu-dma = "disabled"; }; kgsl_iommu_coherent_test_device { - status = "disabled"; + status= "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x407 0>; qcom,iommu-dma = "disabled"; From 650dbd60dc2b6ba30d6be4f14aa1ac0d30669039 Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 11 Nov 2020 12:50:21 +0530 Subject: [PATCH 0336/1809] ARM: dts: msm: Add initial v1 memory map for Monaco Added initial memory map and created regured cma areas for monaco. Change-Id: I3355fa9b9ec9b95b658e8f252b238cde2294c7fa --- qcom/monaco.dtsi | 87 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f33ea540e53e..864b5e1ab4eb 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -115,6 +115,93 @@ soc: soc { }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + rpmbackup_mem: rpmbackup_mem@45D00000 { + no-map; + reg = <0x0 0x45D00000 0x0 0x100000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x110000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_adsp_mem: adsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1c00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@53600000 { + no-map; + reg = <0x0 0x53600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + no-map; + reg = <0x0 0x53610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@53615000 { + no-map; + reg = <0x0 0x53615000 0x0 0x2000>; + }; + + removed_region: removed_region@5f800000 { + no-map; + reg = <0x0 0x5f800000 0x0 0x2700000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; From 0cd8bc6a549ac46a94ea24adecd2a2914855dda7 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 18 Nov 2020 21:19:56 -0800 Subject: [PATCH 0337/1809] ARM: dts: msm: specify thermal mitigation levels for sdxlemur platforms Specify thermal mitigation levels for sdxlemur platforms based on the battery used. This is used to limit charging current when thermal SW requests different levels through charge_control_limit property in battery power supply. Change-Id: I2fe6142f110701b47d9f9f467a02632b20f1d7bb --- qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-rcm-rc.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..150af268d702 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -130,6 +130,7 @@ qcom,fcc-stepping-enable; qcom,fcc-step-delay-ms = <100>; qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; qcom,smb-internal-pull-kohm = <0>; qcom,en-skin-therm-mitigation; qcom,hvdcp3-standalone-config; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..9790544a1f02 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -98,6 +98,7 @@ qcom,fcc-stepping-enable; qcom,fcc-step-delay-ms = <100>; qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; qcom,smb-internal-pull-kohm = <0>; qcom,en-skin-therm-mitigation; qcom,hvdcp3-standalone-config; From 55aba0a4a2145be1cf0131508d8d8d3a09c2df7b Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 11 Nov 2020 14:15:14 +0530 Subject: [PATCH 0338/1809] ARM: dts: msm: Add ion heap for monaco Describe the memory region reserved for the ion allocator. Change-Id: I53ce5c36dc77909fdbd8e1b2b24bd7292e6ef728 --- qcom/monaco-ion.dtsi | 17 +++++++++++++++++ qcom/monaco.dtsi | 2 ++ 2 files changed, 19 insertions(+) create mode 100644 qcom/monaco-ion.dtsi diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi new file mode 100644 index 000000000000..a0a50ce4dbd2 --- /dev/null +++ b/qcom/monaco-ion.dtsi @@ -0,0 +1,17 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 864b5e1ab4eb..cc7e290d0da2 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -474,3 +474,5 @@ }; #include "monaco-pinctrl.dtsi" +#include "monaco-ion.dtsi" + From f9ae418471b6d428460c5fbc798646a8777c35ed Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 18 Nov 2020 14:59:08 +0530 Subject: [PATCH 0339/1809] ARM: dts: qcom: add ADC channels for pm8350b and smb139x on shima Add CHG_TEMP, IIN_FB and ICHG_FB channels on PM8350B to read charger temperature, input current and charging current. Add SMB_TEMP, IIN_SMB and ICHG_SMB on both SMB139x charge pumps to read SMB temperature, input current and charging current which happens over reading virtual channels through PBS. Change-Id: I347cacdf2aacc0db2b7e94a6b49293f45bc8665b --- qcom/shima-pmic-overlay.dtsi | 67 ++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index d83e6fa3b45c..437a1088620a 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -1,4 +1,5 @@ #include +#include #include "pmk8350.dtsi" #include "pm8350.dtsi" @@ -116,6 +117,72 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + pm8350b_chg_temp { + reg = ; + label = "pm8350b_chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_iin_fb { + reg = ; + label = "pm8350b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; + + pm8350b_ichg_fb { + reg = ; + label = "pm8350b_ichg_fb"; + qcom,pre-scaling = <1000 305185>; + }; + + smb139x_1_smb_temp { + reg = ; + label = "smb139x_1_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_1_ichg_smb { + reg = ; + label = "smb139x_1_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_1_ichg_smb_pt { + reg = ; + label = "smb139x_1_ichg_smb_pt"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_1_iin_smb { + reg = ; + label = "smb139x_1_iin_smb"; + qcom,pre-scaling = <28 100>; + }; + + smb139x_2_smb_temp { + reg = ; + label = "smb139x_2_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_2_ichg_smb { + reg = ; + label = "smb139x_2_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_2_ichg_smb_pt { + reg = ; + label = "smb139x_2_ichg_smb_pt"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_2_iin_smb { + reg = ; + label = "smb139x_2_iin_smb"; + qcom,pre-scaling = <28 100>; + }; }; &pmk8350_adc_tm { From 3e646840d9b13a7c0fac6ad7703d2ea7bc76f414 Mon Sep 17 00:00:00 2001 From: nishant chaubey Date: Fri, 20 Nov 2020 13:32:49 +0530 Subject: [PATCH 0340/1809] ARM: dts: msm: Reduce secure heap to 30MB 30MB memory is sufficient for fastrpc securepd usecase. Reduce secure heap to 30MB. Change-Id: Ic680bfb74ff6ac37925a2c9b4edae275acc9d260 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 28c75c04dada..47a95eaeb137 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -320,7 +320,7 @@ cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; + reg = <0x0 0x80c00000 0x0 0x1e00000>; }; pil_wlan_mem: wlan@86500000 { From be1f95bbcdeda891892b6a47a307d9de52f99630 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 20 Nov 2020 12:52:42 -0800 Subject: [PATCH 0341/1809] ARM: dts: msm: Disable PMX65 VBUS_DET on sdxlemur MTP-MBB and RCM-RC boards On these boards, VBUS detection is through PM7250B, so disable the VBUS_DET peripheral. Change-Id: If408b620c296df6bf1fbfeafb96b3e720de83114 --- qcom/sdxlemur-mtp-mbb.dtsi | 4 ++++ qcom/sdxlemur-rcm-rc.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..c28a01a0a5fe 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -204,3 +204,7 @@ "typec_mode", "pe_start"; }; + +&vbus_detect { + status = "disabled"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..b5cd20db732c 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -172,3 +172,7 @@ "typec_mode", "pe_start"; }; + +&vbus_detect { + status = "disabled"; +}; From b625000a5d446a100da0f81cebee93f444d32e6d Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Thu, 19 Nov 2020 11:44:59 -0800 Subject: [PATCH 0342/1809] ARM: dts: msm: Add missing memory map region for sdxlemur Correct the memory map to match version 1. Change-Id: I2da959263e0d0805b75ecc78c79b76ffaa08f41b --- qcom/sdxlemur-512mb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-512mb.dtsi b/qcom/sdxlemur-512mb.dtsi index 4e48c97523d0..29098f1f0707 100644 --- a/qcom/sdxlemur-512mb.dtsi +++ b/qcom/sdxlemur-512mb.dtsi @@ -46,6 +46,11 @@ reg = <0x8fced000 0x10000>; }; + tz_heap_mem: tz_heap_region@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + mpss_dsm: mpss_dsm_region@8c400000 { no-map; reg = <0x8c400000 0x3200000>; From 03fea8ad8a0cf1f964e8f0efcb6bf2e10a307d92 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 24 Sep 2020 14:42:14 +0530 Subject: [PATCH 0343/1809] ARM: dts: msm: Update GCC clock node and GDSC for YUPIK Update the global clock controller node and the corresponding GDSC's of YUPIK. While at it, move the qcom,retain-regs property from platform specific shima dtsi file to generic shima gdsc dtsi file which is used by SHIMA and YUPIK. Change-Id: Idbeea95e2a5c2cf7ac69b1f764325b2464713b18 --- qcom/shima-gdsc.dtsi | 19 +++++++++++++++++++ qcom/shima.dtsi | 17 ----------------- qcom/yupik-rumi.dtsi | 4 ++++ qcom/yupik.dtsi | 18 ++++++------------ 4 files changed, 29 insertions(+), 29 deletions(-) diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index d6d058295306..0686c9dfeb67 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -6,6 +6,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,gds-timeout = <500>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -15,6 +16,7 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,gds-timeout = <500>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -22,6 +24,7 @@ compatible = "qcom,gdsc"; reg = <0x177004 0x4>; regulator-name = "gcc_ufs_phy_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -29,6 +32,7 @@ compatible = "qcom,gdsc"; reg = <0x10f004 0x4>; regulator-name = "gcc_usb30_prim_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -36,6 +40,7 @@ compatible = "qcom,gdsc"; reg = <0x19e004 0x4>; regulator-name = "gcc_usb30_sec_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -116,6 +121,7 @@ compatible = "qcom,gdsc"; reg = <0xad0c120 0x4>; regulator-name = "cam_cc_titan_top_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -123,6 +129,7 @@ compatible = "qcom,gdsc"; reg = <0xad07004 0x4>; regulator-name = "cam_cc_bps_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -130,6 +137,7 @@ compatible = "qcom,gdsc"; reg = <0xad0a004 0x4>; regulator-name = "cam_cc_ife_0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -137,6 +145,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b004 0x4>; regulator-name = "cam_cc_ife_1_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -144,6 +153,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b070 0x4>; regulator-name = "cam_cc_ife_2_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -151,6 +161,7 @@ compatible = "qcom,gdsc"; reg = <0xad08004 0x4>; regulator-name = "cam_cc_ipe_0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -161,6 +172,7 @@ regulator-name = "disp_cc_mdss_core_gdsc"; proxy-supply = <&disp_cc_mdss_core_gdsc>; qcom,proxy-consumer-enable; + qcom,retain-regs; status = "disabled"; }; @@ -186,6 +198,7 @@ regulator-name = "gpu_cx_gdsc"; hw-ctrl-addr = <&gpu_cx_hw_ctrl>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -196,6 +209,7 @@ sw-reset = <&gpu_gx_sw_reset>; domain-addr = <&gpu_gx_domain_addr>; qcom,reset-aon-logic; + qcom,retain-regs; status = "disabled"; }; @@ -204,6 +218,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d18 0x4>; regulator-name = "video_cc_mvs0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -211,6 +226,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0bf8 0x4>; regulator-name = "video_cc_mvs0c_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -218,6 +234,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d98 0x4>; regulator-name = "video_cc_mvs1_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -225,6 +242,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0c98 0x4>; regulator-name = "video_cc_mvs1c_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -232,6 +250,7 @@ compatible = "qcom,gdsc"; reg = <0xaaf2004 0x4>; regulator-name = "video_cc_mvsc_gdsc"; + qcom,retain-regs; status = "disabled"; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 44ab78339e3f..0fef6712174d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3890,22 +3890,18 @@ }; &gcc_pcie_0_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_pcie_1_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_ufs_phy_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_usb30_prim_gdsc { - qcom,retain-regs; status = "ok"; }; @@ -3945,7 +3941,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3954,7 +3949,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3962,7 +3956,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3970,7 +3963,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3978,7 +3970,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3987,7 +3978,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3996,7 +3986,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4004,7 +3993,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4012,7 +4000,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_GFX_LEVEL>; - qcom,retain-regs; qcom,skip-disable-before-sw-enable; status = "ok"; }; @@ -4022,7 +4009,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4030,7 +4016,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4039,7 +4024,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4047,7 +4031,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 1efb6b32bfaa..3cf06415ef73 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -75,3 +75,7 @@ &qupv3_se5_2uart { qcom,rumi_platform; }; + +&gcc { + clocks = <&bi_tcxo>, <&sleep_clk>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 59808e07e047..317092da3274 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -600,8 +600,12 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,yupik-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1304,56 +1308,46 @@ #include "ipcc-test-yupik.dtsi" &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_pcie_1_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &gcc_usb30_sec_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_turing_mmu_tbu0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_turing_mmu_tbu1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; From 6719abb50ee49f345d74cc0c2fa2d83ab24d7610 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 27 Oct 2020 10:35:49 +0530 Subject: [PATCH 0344/1809] ARM: dts: msm: Update GPUCC clock node and GDSC for YUPIK Update GPUCC clock node and corresponding GDSC's for YUPIK. Change-Id: Ib5c4e21fa3e8da086689c16a3f766a869d459969 --- qcom/yupik-rumi.dtsi | 7 +++++++ qcom/yupik.dtsi | 22 ++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 3cf06415ef73..138f7c0482f8 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -1,3 +1,5 @@ +#include + &soc { timer { clock-frequency = <5000000>; @@ -79,3 +81,8 @@ &gcc { clocks = <&bi_tcxo>, <&sleep_clk>; }; + +&gpucc { + clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 317092da3274..53621f3c4afc 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -625,8 +625,15 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,yupik-gpucc", "syscon"; + reg = <0x3d90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1392,12 +1399,19 @@ }; &gpu_cx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; &gpu_gx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_GFX_LEVEL>; + qcom,retain-regs; + qcom,skip-disable-before-sw-enable; status = "ok"; }; From 696feed44ec4cf74380fc0ee1bf94069f951316b Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 22 Nov 2020 10:59:45 +0530 Subject: [PATCH 0345/1809] ARM: dts: msm: Disable scaling for SD and eMMC on sdxlemur Disable scaling for SD and eMMC as for SD card the clocks were not getting scaled properly. Change-Id: Ic90f783ad141a9cb8e8bde10aacfd365aac3b3dc --- qcom/sdxlemur.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 6aa9e75a2eed..fde7c5e79304 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -459,8 +459,6 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; - qcom,devfreq,freq-table = <50000000 200000000>; - status = "disabled"; qos0 { From 17cf51a99a48a15167de8d38a156024865ea9eaa Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 27 Oct 2020 17:12:35 +0530 Subject: [PATCH 0346/1809] ARM: dts: msm: Add dummy clock nodes for MONACO Dummy clock nodes are required for clocks client to request, so add support for the same. Also add the dummy GDSCs required by clients for monaco. Change-Id: I16e204fb2c04cbe750db25af4364a8af0b252404 --- qcom/monaco-gdsc.dtsi | 91 +++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 qcom/monaco-gdsc.dtsi diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi new file mode 100644 index 000000000000..e1bf1597ede3 --- /dev/null +++ b/qcom/monaco-gdsc.dtsi @@ -0,0 +1,91 @@ +&soc { + /* GDSCs in GCC */ + gcc_camss_top_gdsc: qcom,gdsc@1458004 { + compatible = "regulator-fixed"; + reg = <0x1458004 0x4>; + regulator-name = "gcc_camss_top_gdsc"; + status = "disabled"; + }; + + gcc_usb20_prim_gdsc: qcom,gdsc@141c004 { + compatible = "regulator-fixed"; + reg = <0x141c004 0x4>; + regulator-name = "gcc_usb20_prim_gdsc"; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@14580a8 { + compatible = "regulator-fixed"; + reg = <0x14580a8 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@1458084 { + compatible = "regulator-fixed"; + reg = <0x1458084 0x4>; + regulator-name = "gcc_venus_gdsc"; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { + compatible = "regulator-fixed"; + reg = <0x147d078 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { + compatible = "regulator-fixed"; + reg = <0x147d074 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + /* GDSCs in DISPCC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "regulator-fixed"; + reg = <0x5f03000 0x4>; + regulator-name = "mdss_core_gdsc"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + /* GDSCs in GPUCC */ + gpu_gx_sw_reset: syscon@5994008 { + compatible = "syscon"; + reg = <0x5994008 0x4>; + }; + + gpu_cx_hw_ctrl: syscon@5994540 { + compatible = "syscon"; + reg = <0x5994540 0x4>; + }; + + gpu_gx_domain_addr: syscon@5994508 { + compatible = "syscon"; + reg = <0x5994508 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@5994064 { + compatible = "regulator-fixed"; + reg = <0x5994064 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599400c { + compatible = "regulator-fixed"; + reg = <0x599400c 0x4>; + regulator-name = "gpu_gx_gdsc"; + sw-reset = <&gpu_gx_sw_reset>; + domain-addr = <&gpu_gx_domain_addr>; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index cc7e290d0da2..f15bcb2b78b3 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1,4 +1,8 @@ #include +#include +#include +#include +#include / { model = "Qualcomm Technologies, Inc. Monaco"; @@ -471,8 +475,105 @@ qcom,dump-id = <0x123>; }; }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@1410000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5994000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; #include "monaco-pinctrl.dtsi" #include "monaco-ion.dtsi" +#include "monaco-gdsc.dtsi" +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_usb20_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; From 62ae3115f95151095063dbf02e63431172b1560c Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 5 Oct 2020 17:04:04 +0530 Subject: [PATCH 0347/1809] ARM: dts: msm: Add new GPU DCVS corners for Shima GPU clock plan is updated to add new corners SVS_L0 and LOW_SVS_L1. This change updates the clock plan to add these new corners. Change-Id: Ic4fb5fddb838432a3e7b1418c72fd672783fe83a --- qcom/shima-gpu.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 79 insertions(+), 9 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 9766e11225f9..84349ff83d3e 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -143,7 +143,7 @@ #size-cells = <0>; qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -203,6 +203,20 @@ qcom,gpu-pwrlevel@4 { reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -215,8 +229,22 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -235,12 +263,12 @@ #size-cells = <0>; qcom,speed-bin = <105>; - qcom,initial-pwrlevel = <2>; + qcom,initial-pwrlevel = <3>; qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <490000000>; - qcom,level = ; + qcom,level = ; qcom,bus-freq-ddr7 = <11>; qcom,bus-min-ddr7 = <10>; @@ -267,6 +295,20 @@ qcom,gpu-pwrlevel@2 { reg = <2>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -290,7 +332,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <365000000>; - qcom,level = ; + qcom,level = ; qcom,bus-freq-ddr7 = <10>; qcom,bus-min-ddr7 = <8>; @@ -321,7 +363,7 @@ #size-cells = <0>; qcom,speed-bin = <158>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -381,6 +423,20 @@ qcom,gpu-pwrlevel@4 { reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -393,8 +449,22 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <285000000>; qcom,level = ; From 68d9dff9f9ef0e830be95811d148f689aba5cf0b Mon Sep 17 00:00:00 2001 From: Wu Gao Date: Thu, 22 Oct 2020 02:07:28 -0700 Subject: [PATCH 0348/1809] ARM: dts: msm: Support CNSS WLAN device for sdxlemur Support CNSS WLAN device for sdxlemur. Change-Id: I152ecbd2064b63f15ea38cc300531371d4c0d925 --- qcom/sdxlemur-cdp.dtsi | 1 + qcom/sdxlemur-cnss.dtsi | 196 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-pinctrl.dtsi | 30 ++++++ qcom/sdxlemur-rcm-rc.dtsi | 1 + qcom/sdxlemur.dtsi | 8 ++ 6 files changed, 237 insertions(+) create mode 100644 qcom/sdxlemur-cnss.dtsi diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index b59aa174c58a..fc20abab6a3d 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-cnss.dtsi" &soc { diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi new file mode 100644 index 000000000000..bcbdd6ec0501 --- /dev/null +++ b/qcom/sdxlemur-cnss.dtsi @@ -0,0 +1,196 @@ + +&soc { + wlan: qcom,cnss-qca6490@b0000000 { + compatible = "qcom,cnss-qca6490"; + reg = <0xb0000000 0x10000>, + <0xb2e5510 0x690>; + reg-names = "smmu_iova_ipa", "tcs_cmd"; + wlan-en-gpio = <&tlmm 91 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x420000>; + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "rf_clk"; + + use-pm-domain; + cnss-enable-self-recovery; + + vdd-wlan-aon-supply = <&S7B>; + qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>; + vdd-wlan-rfa1-supply = <&S4B>; + qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>; + vdd-wlan-rfa2-supply = <&S2B>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + + interconnects = + <&system_noc MASTER_PCIE_0 &system_noc SLAVE_SNOC_MEM_NOC_GC>, + <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <7>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <2250 390000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <7500 390000>, + /* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <30000 790000>, + /* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <100000 790000>, + /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ + <175000 1600000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz + * ddr: 547.2 MHz + */ + <7500 390000>, + /** ICC Path 2 **/ + <0 0>, + <2250 1804800>, + <7500 1804800>, + <30000 1804800>, + <100000 1804800>, + <175000 6220800>, + <7500 2188800>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <0>; + mhi,priority = <2>; + mhi,brstmode = <2>; + mhi,data-type = <3>; + }; + }; + + mhi_devices { + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + qcom,low-latency; + }; + }; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + }; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 6b5d5c919674..5b77ee6bc08b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -2,6 +2,7 @@ #include "pm7250b.dtsi" #include #include +#include "sdxlemur-cnss.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 7acc8527e1b9..f4d0c0e303f2 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -186,6 +186,36 @@ }; }; + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + i2c_1 { i2c_1_active: i2c_1_active { mux { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 824582ac94dc..5c036cf23b5f 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -2,6 +2,7 @@ #include "pm7250b.dtsi" #include #include +#include "sdxlemur-cnss.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..0e98cafa1c0d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -55,6 +55,14 @@ no-map; size = <0x400000>; }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; }; cpus { From 94e42e875fb9903d3282beee97990d5f5b520c0c Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 19 Nov 2020 18:53:11 -0800 Subject: [PATCH 0349/1809] ARM: dts: msm: add number of PARF testbus selectors for lahaina When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on lahaina. Change-Id: I6026679298f0be09dbf9871129dc329731febeb5 --- qcom/lahaina-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..4bf919cc1da9 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -109,6 +109,7 @@ qcom,l1-2-th-value = <70>; qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <10100>; qcom,phy-status-offset = <0x214>; @@ -335,6 +336,7 @@ qcom,no-l0s-supported; qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <1106>; qcom,phy-status-offset = <0x214>; From 451a0741ee5c9f0762250796ea61177a13041aa2 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:28:40 -0800 Subject: [PATCH 0350/1809] ARM: dts: msm: add number of PARF testbus selectors for sdxlemur When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on sdxlemur. Change-Id: I5e903983830bb5a51ebde2606d37a8dc2ad80d8a --- qcom/sdxlemur-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 8df0c684343a..c625387e4b4f 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -94,6 +94,7 @@ qcom,aux-clk-freq = <17>; /* 16.6 MHz */ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,pcie-phy-ver = <1102>; qcom,phy-status-offset = <0x1214>; From 0d3e1900e16824b83569972233e50cd295ebb69d Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:29:59 -0800 Subject: [PATCH 0351/1809] ARM: dts: msm: add number of PARF testbus selectors for shima When collecting PCIe PARF registers, also collect the PARF testbus signals. Add the number of PARF testbus selectors supported for PCIe on shima. Change-Id: Iadd31d7e2fadd1c55655d40e35eb3caa4c055cd8 --- qcom/shima-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fce90dee366f..b6f3875e59fe 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -105,6 +105,7 @@ qcom,l1-2-th-value = <70>; qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; From d97d709d67a5942ff0d18f02e79854554d5230da Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Nov 2020 08:37:15 -0800 Subject: [PATCH 0352/1809] dt-bindings: arm: msm: add entry for number of PARF testbus selectors The number of PCIe PARF testbus signals available varies for each PCIe controller version. Add entry to specify how many PCIe PARF testbus selectors are available. Change-Id: I58d94c99f65c1b9fb7e37ca102a60e71a9f0c1aa --- bindings/pci/pci-msm.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 6c6285f4e714..359461341214 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -341,6 +341,12 @@ interconnects: de-asserted. This guarantees the 100MHz clock is available for the PCIe devices +- qcom,num-parf-testbus-sel: + Usage: optional + Value type: + Definition: Defines the number of testbus selectors available for PARF + for a given PCIe controller. + - qcom,switch-latency: Usage: optional Definition: The latency(ms) between when PCIe link is up and before @@ -526,6 +532,7 @@ Example qcom,perst-delay-us-min = <10>; qcom,perst-delay-us-max = <15>; qcom,ep-latency = <20>; + qcom,num-parf-testbus-sel = <0xb9>; qcom,switch-latency = <25>; qcom,eq-pset-req-vec = <0>; From 343beb8375faa8ba3908f68be2ef2a621961c3cc Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 23 Nov 2020 16:06:53 -0800 Subject: [PATCH 0353/1809] ARM: dts: msm: DDR cooling device no mitigation for lahaina DDR cooling device right now votes for the lowest bandwidth when there is no request from cooling device. Instead of voting to lowest level, vote for zero bandwidth, so that it doesn't prevent sleep. Change-Id: Ibf7895568f7c102bd4dc7267327b7decf45362e8 --- qcom/lahaina-thermal.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index fb753c87f2dd..30711401984a 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -57,7 +57,7 @@ ddr_cdev: qcom,ddr-cdev { compatible = "qcom,ddr-cooling-device"; #cooling-cells = <2>; - qcom,ddr-freq = <762000>, + qcom,ddr-freq = <0>, <1720000>, <2086000>, <2597000>, From 5e9e8bc32655dbb64c0d9cce45a4d7075c554a10 Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Mon, 23 Nov 2020 10:13:08 +0800 Subject: [PATCH 0354/1809] ARM: dts: msm: Add label for bluetooth bootstrap pin EDL_MODE on sdxlemur GPIO17 also drives bluetooth bootstrap pin EDL_MODE for sdxlemur, so add a label for bluetooth. CRs-Fixed: 2824381 Change-Id: I3779e8fa26e9a41b6a0a378b4ed97b7b985bd2c1 --- qcom/sdxlemur-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 7acc8527e1b9..a5d5e1e8261f 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -1417,7 +1417,7 @@ }; pmx_sec_mi2s_aux_din { - sec_din_sleep: sec_din_sleep { + bt_edl_default: sec_din_sleep: sec_din_sleep { mux { pins = "gpio17"; function = "gpio"; From 0e4ed0f33548674d9d29d287985def521d9261aa Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Mon, 23 Nov 2020 11:00:48 +0800 Subject: [PATCH 0355/1809] ARM: dts: msm: Enable bluetooth for sdxlemur Enable bluetooth for sdxlemur. CRs-Fixed: 2824381 Change-Id: I37762923eb49bfb3b3bbb19a5f088540f473f4e4 --- qcom/sdxlemur-bluetooth.dtsi | 40 ++++++++++++++++++++++++++++++++++ qcom/sdxlemur-cdp.dts | 1 + qcom/sdxlemur-mtp-mbb-emmc.dts | 1 + qcom/sdxlemur-mtp-mbb.dts | 1 + qcom/sdxlemur-rcm-rc.dts | 1 + 5 files changed, 44 insertions(+) create mode 100644 qcom/sdxlemur-bluetooth.dtsi diff --git a/qcom/sdxlemur-bluetooth.dtsi b/qcom/sdxlemur-bluetooth.dtsi new file mode 100644 index 000000000000..d4848e87ad4c --- /dev/null +++ b/qcom/sdxlemur-bluetooth.dtsi @@ -0,0 +1,40 @@ +#include + +&pmx65_gpios { + bt_en { + bt_en_default: bt_en_default { + pins = "gpio15"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <1>; + }; + }; +}; + +&soc { + bluetooth: bt_qca6490 { + compatible = "qcom,qca6490"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default &bt_edl_default>; + qcom,bt-reset-gpio = <&pmx65_gpios 15 0>; /* BT_EN */ + qcom,bt-sw-ctrl-gpio = <&pmx65_gpios 2 0>; /* SW_CTRL */ + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "ref3_clk"; + + qcom,bt-vdd-aon-supply = <&S7B>; + qcom,bt-vdd-aon-config = <1012000 1012000 0 0>; + qcom,bt-vdd-io-supply = <&L6B>; + qcom,bt-vdd-io-config = <1800000 1800000 0 0>; + }; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&i2c_6 { + status = "disabled"; +}; diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 93cd0f92dd66..68c99b5dd58d 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts index acdb4853a32a..734bb19c3f1b 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-emmc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index e9bc21eb4200..bdcc2ce058b1 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index 990224dd464a..a5fd339b9fa4 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-rc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; From aaf5337d6323ee77861d98d83ef1c42e88a0c7b9 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 22 Nov 2020 11:02:03 +0530 Subject: [PATCH 0356/1809] ARM: dts: msm: Enable NAND and SD card for sdxlemur target Enable NAND and SD card for all the boards available on sdxlemur target. Change-Id: I17b3321bde161fbfbec8950d9893854912297ba9 --- qcom/sdxlemur-cdp.dtsi | 2 +- qcom/sdxlemur-mtp-mbb.dtsi | 32 -------------------------------- qcom/sdxlemur-rcm-pcie-ep.dtsi | 21 +++++++++++++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 22 ++++++++++++++++++++++ 4 files changed, 44 insertions(+), 33 deletions(-) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index b59aa174c58a..fe6531308f6c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -9,7 +9,7 @@ }; &sdhc_1 { - status = "disabled"; + status = "ok"; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 6b5d5c919674..a11b05d3ad25 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -31,38 +31,6 @@ qcom,l1-2-th-value = <70>; }; -&qnand_1 { - status = "ok"; -}; - -&sdhc_1 { - reg = <0x08804000 0x1000>, <0x08805000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; - - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - bus-width = <8>; - non-removable; - supports-cqe; - - vdd-supply = <&vreg_sd_vdd>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&L6B>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 200000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - - status = "disabled"; -}; - &pm7250b_vadc { charger_skin_therm { reg = ; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index 768d9aaa521c..e61e86ac8459 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -4,3 +4,24 @@ }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 824582ac94dc..765f3859f4c3 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -31,6 +31,28 @@ qcom,l1-2-th-value = <70>; }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pm7250b_vadc { charger_skin_therm { reg = ; From d3a6a451555346bff9bf5c60231e96b599a4e965 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 24 Nov 2020 10:28:51 +0530 Subject: [PATCH 0357/1809] ARM: dts: msm: add msm_rtb tracing Add qcom,msm-rtb entry to device tree to enable msm_rtb tracing on Yupik. Change-Id: Ib441c46b16c6ac22436e619188b5dd71f759e11f --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index dc3ac3c89aca..0c833b5cdc2c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -785,6 +785,11 @@ interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; }; + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From 38fbea3672c645c186ff7136f6b4eeb3a3409955 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 24 Nov 2020 10:48:01 +0530 Subject: [PATCH 0358/1809] ARM: dts: msm: Add boot_stats node for Yupik Add DT node for boot_stats for Yupik. Change-Id: Ibd3d7d688128d0f60886f4f724421fa9922cf51c --- qcom/yupik.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 0c833b5cdc2c..f7e7639ed6c4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -790,6 +790,12 @@ qcom,rtb-size = <0x100000>; }; + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From ae8150eac6573c0caff8153bfb4db7c0221dcfd6 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Fri, 6 Nov 2020 10:43:35 +0800 Subject: [PATCH 0359/1809] ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina Add dma-coherent for tmc-etr to avoid cache flush issue between etr and usb. Change-Id: Iba762e88442294c93c22675f2b4d2c2937c1e9dd --- qcom/lahaina-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index ff7750e6f034..b773c609af39 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -154,6 +154,7 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + dma-coherent; qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; From e8ca9d4eee66a37e15493abca64f463712ba5eb5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 6 Nov 2020 09:22:55 +0530 Subject: [PATCH 0360/1809] ARM: dts: msm: Add clock controller and gdsc nodes for sm8150 Add support for all the clock controllers and also add gdsc regulators. Change-Id: Ic313db887845e43c1d69b82f6bd8af4154145832 --- qcom/sa8155-regulator.dtsi | 1 + qcom/sa8155-v1.dtsi | 20 +++ qcom/sa8155-v2.dtsi | 20 +++ qcom/sa8155.dtsi | 13 ++ qcom/sm8150-gdsc.dtsi | 254 +++++++++++++++++++++++++++++++ qcom/sm8150-regulator.dtsi | 1 + qcom/sm8150-v2.dtsi | 24 +++ qcom/sm8150.dtsi | 296 +++++++++++++++++++++++++++++++++++-- 8 files changed, 620 insertions(+), 9 deletions(-) create mode 100644 qcom/sm8150-gdsc.dtsi diff --git a/qcom/sa8155-regulator.dtsi b/qcom/sa8155-regulator.dtsi index a3575be84b12..5685f98c665a 100644 --- a/qcom/sa8155-regulator.dtsi +++ b/qcom/sa8155-regulator.dtsi @@ -344,6 +344,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S3C_LEVEL: pm8150_2_s3_level: regulator-pm8150-2-s3-level { regulator-name = "pm8150_2_s3_level"; qcom,set = ; diff --git a/qcom/sa8155-v1.dtsi b/qcom/sa8155-v1.dtsi index 50d09d7a5ba4..1e52e3797265 100644 --- a/qcom/sa8155-v1.dtsi +++ b/qcom/sa8155-v1.dtsi @@ -7,3 +7,23 @@ qcom,msm-name = "SA8155 V1"; qcom,msm-id = <362 0x10000>; }; + +&scc { + compatible = "qcom,sa8155-scc", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc", "syscon"; +}; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index 09d9488c0872..f995a319af99 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -6,3 +6,23 @@ qcom,msm-name = "SA8155 V2"; qcom,msm-id = <362 0x20000>; }; + +&scc { + compatible = "qcom,sa8155-scc-v2", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc-v2", "syscon"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index b048176d4cbb..a3fcc5063c04 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -55,3 +55,16 @@ /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" + +&gpucc { + compatible = "qcom,sa8155-gpucc", "syscon"; +}; + +&scc { + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; +}; diff --git a/qcom/sm8150-gdsc.dtsi b/qcom/sm8150-gdsc.dtsi new file mode 100644 index 000000000000..07d8e929ce7a --- /dev/null +++ b/qcom/sm8150-gdsc.dtsi @@ -0,0 +1,254 @@ +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + regulator-name = "emac_gdsc"; + reg = <0x106004 0x4>; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + pcie_1_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_1_gdsc"; + reg = <0x18d004 0x4>; + status = "disabled"; + }; + + ufs_card_gdsc: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_gdsc"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + usb30_sec_gdsc: qcom,gdsc@110004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_sec_gdsc"; + reg = <0x110004 0x4>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d050 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d054 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d058 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x17d05c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x17d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad07004 0x4>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad08004 0x4>; + status = "disabled"; + }; + + ipe_1_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad09004 0x4>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad0a004 0x4>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0b004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0b004 0x4>; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0c1bc { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0c1bc 0x4>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@2c91540 { + compatible = "syscon"; + reg = <0x2c91540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@2c9106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x2c9106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,skip-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + mboxes = <&qmp_aop 0>; + status = "disabled"; + }; + + gpu_gx_domain_addr: syscon@2c91508 { + compatible = "syscon"; + reg = <0x2c91508 0x4>; + }; + + gpu_gx_sw_reset: syscon@2c91008 { + compatible = "syscon"; + reg = <0x2c91008 0x4>; + }; + + gpu_gx_gdsc: qcom,gdsc@2c9100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x2c9100c 0x4>; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + qcom,reset-aon-logic; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + mvsc_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + regulator-name = "mvsc_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + mvs0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + regulator-name = "mvs0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + mvs1_gdsc: qcom,gdsc@ab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "mvs1_gdsc"; + reg = <0xab008b4 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@9911028 { + compatible = "qcom,gdsc"; + regulator-name = "npu_core_gdsc"; + reg = <0x9911028 0x4>; + status = "disabled"; + }; +}; diff --git a/qcom/sm8150-regulator.dtsi b/qcom/sm8150-regulator.dtsi index b03ebd06ffe3..8cb0baf556e8 100644 --- a/qcom/sm8150-regulator.dtsi +++ b/qcom/sm8150-regulator.dtsi @@ -450,6 +450,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S2C_LEVEL: pm8150l_s2_level: regulator-pm8150l-s2-level { regulator-name = "pm8150l_s2_level"; qcom,set = ; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 3f6b99c92e77..a7ec31ec4fa3 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -5,3 +5,27 @@ qcom,msm-name = "SM8150 V2"; qcom,msm-id = <339 0x20000>; }; + +&gcc { + compatible = "qcom,sm8150-gcc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sm8150-camcc-v2", "syscon"; +}; + +&dispcc { + compatible = "qcom,sm8150-dispcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sm8150-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sm8150-npucc-v2", "syscon"; +}; + +&scc { + compatible = "qcom,sm8150-scc-v2", "syscon"; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fcb8a87066b1..50f901d5282a 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1,3 +1,11 @@ +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include @@ -701,24 +709,138 @@ }; + aopcc: qcom,aopcc { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; + compatible = "qcom,sm8150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm8150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + npucc: clock-controller@9910000 { + compatible = "qcom,sm8150-npucc", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_NPU_GPLL0_CLK_SRC>, + <&gcc GCC_NPU_AXI_CLK>; + clock-names = + "bi_tcxo", + "gcc_npu_gpll0_div_clk_src", + "gcc_npu_gpll0_clk_src", + "gcc_npu_axi_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sm8150-gpucc", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: clock-controller@2b10000 { + compatible = "qcom,sm8150-scc", "syscon"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&pm8150_l8_level>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0000 0x4>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm8150-debugcc"; + qcom,gcc = <&gcc>; + qcom,videocc = <&videocc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,npucc = <&npucc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc 123>, - <&gcc 124>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; ranges; #address-cells = <2>; #size-cells = <2>; @@ -729,7 +851,7 @@ compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; - clocks = <&gcc 105>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; status = "ok"; }; @@ -1112,3 +1234,159 @@ #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sm8150-smp2p.dtsi" +#include "sm8150-gdsc.dtsi" + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&pcie_1_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&ufs_card_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +}; From 6236ec35c7a1d93c97fe119e64d7ba8e7ae71a2d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 2 Mar 2020 16:08:59 +0530 Subject: [PATCH 0361/1809] ARM: dts: msm: add interconnect devices for sm8150 Add stub interconnect devices for aggre1_noc, aggre2_noc, camnoc_virt, compute_noc, config_noc, dc_noc, gem_noc, ipa_virt, mc_virt, mmss_noc, system_noc, gem_noc_display, mc_virt_display, mmss_noc_display. This will allow consumers to get their path and set bandwidth constraints on them. And add bcm voter devices that live under RSC devices to allow interconnect providers to target their votes for meeting bandwidth constraints. Change-Id: I6c46d36928ecfbeaa5b568a61d3dfee9e9e0349d --- qcom/sm8150.dtsi | 99 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 50f901d5282a..cc62d8d3f78e 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -681,6 +683,10 @@ , ; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; #clock-cells = <1>; @@ -707,6 +713,11 @@ , ; + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; + }; aopcc: qcom,aopcc { @@ -835,6 +846,94 @@ #clock-cells = <1>; }; + config_noc: interconnect@1500000 { + reg = <0x1500000 0x7400>; + compatible = "qcom,sm8150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x19400>; + compatible = "qcom,sm8150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + camnoc_virt: interconnect@1630000 { + compatible = "qcom,sm8150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1640000 { + compatible = "qcom,sm8150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16E0000 0xD080>; + compatible = "qcom,sm8150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x3B100>; + compatible = "qcom,sm8150-aggre2_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1710000 { + compatible = "qcom,sm8150-compute_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm8150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm8150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm8150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + mc_virt: interconnect@9690000 { + compatible = "qcom,sm8150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; From 24f8b6eb0b0acbe4d701c8515777daae1cb7bbba Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 13 Apr 2020 15:28:57 +0530 Subject: [PATCH 0362/1809] ARM: dts: msm: Add UFS support for SA8155 Add UFS host controller and UFS PHY (attached to embedded UFS card) for SM8150 platform and SA8155. Change-Id: I2f58f3bd2457fed0baaffa5233bbd2c92ec22c12 --- qcom/sa8155-adp-common.dtsi | 25 +++++++ qcom/sa8155.dtsi | 4 ++ qcom/sm8150.dtsi | 140 ++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index 44b2ac0d79b8..fc99f15ac51c 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -1,2 +1,27 @@ #include #include + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-pll-supply = <&pm8150_2_l8>; + vdda-phy-max-microamp = <87100>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_1_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_1_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index a3fcc5063c04..8f7a349e5ad9 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -68,3 +68,7 @@ &gpu_gx_gdsc { parent-supply = <&VDD_GFX_LEVEL>; }; + +&ufsphy_mem { + vdda-phy-supply = <&pm8150_2_l18>; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index cc62d8d3f78e..593cdf061a10 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &uart2; }; @@ -934,6 +936,144 @@ }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xda8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; From e61901e2640b29e1ca821b088f54678955172630 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 3 Nov 2020 11:51:08 +0530 Subject: [PATCH 0363/1809] ARM: dts: msm: Add interconnect osm l3 devices for SM8150 Add a device that allows voting for l3. Change-Id: I6bf4bb5e1092dcbc03a591cb8f2a8da1f6e5cecc --- qcom/sm8150.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 593cdf061a10..dc15e677873c 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -848,6 +849,14 @@ #clock-cells = <1>; }; + osm_l3: interconnect@0x18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm8150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + config_noc: interconnect@1500000 { reg = <0x1500000 0x7400>; compatible = "qcom,sm8150-config_noc"; From 61540c97ebea006f6d72108d1ed6700027e33478 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 24 Nov 2020 17:53:15 +0800 Subject: [PATCH 0364/1809] ARM: dts: msm: refine QDSS config for sdxlemur Add reset and flush trigger number for etr and etf. Change-Id: Iec420ee00ac45ca37e525f3736e0204d6c36e71b --- qcom/sdxlemur-coresight.dtsi | 8 ++++++-- qcom/sdxlemur.dtsi | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 2e977b84e52b..073cfa4332f9 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -147,7 +149,9 @@ arm,scatter-gather; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..0553ed188bfc 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -946,6 +946,7 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-regulators.dtsi" +#include "sdxlemur-coresight.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" From 46d06ca5d9e86fbeb05abbd88a523b981220f17d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 24 Nov 2020 17:57:07 +0800 Subject: [PATCH 0365/1809] ARM: dts: msm: modify dcc_ram_offset for sdxlemur Modify dcc_ram_offset to 0x12000 on sdxlemur. Change-Id: Iadb7d0ce55976cb9a29fdc6d57b4ea46783bc6b1 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..f31fbbd269c9 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -185,7 +185,7 @@ qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; - dcc-ram-offset = <0x800>; + dcc-ram-offset = <0x12000>; }; wdog: qcom,wdt@17817000 { From 0f04d225a15500fc60ace11175ce4cad84c7f788 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Tue, 24 Nov 2020 12:58:50 +0530 Subject: [PATCH 0366/1809] ARM: dts: msm: Add a new pinctrl state for shima This change adds new pinctrl state shutdown. Change-Id: I6582bfd5f6f2e2b08803e9177d0a26b72a3fdfa1 --- qcom/shima-qupv3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index aa158a9189e4..3a6c21606b15 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -341,13 +341,15 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se15_default_cts>, <&qupv3_se15_default_rtsrx>, <&qupv3_se15_default_tx>; pinctrl-1 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>, <&qupv3_se15_tx>; pinctrl-2 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>, <&qupv3_se15_tx>; + pinctrl-3 = <&qupv3_se15_default_cts>, + <&qupv3_se15_default_rtsrx>, <&qupv3_se15_default_tx>; qcom,wakeup-byte = <0xFD>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; From bfa6da3aff0b87d9a5845202bda9fb0536976d7f Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Tue, 24 Nov 2020 17:54:26 +0530 Subject: [PATCH 0367/1809] ARM: dts: msm: Update the rpm-smd node with IRQ for sdxnightjar Update the rpm-smd node with glink-rpm irq so that rpm driver can mask the glink-rpm interrupt while going to APSS deep sleep. Change-Id: Ibc106eb9dc044f1f49fc478bf392fa3026226df9 --- qcom/sdxnightjar.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 622d46a7c381..5bb8fbec25de 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -344,6 +344,7 @@ rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; + interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; From 5c82b2e59b26ee87d03043103e816c71e03711c9 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 17 Nov 2020 00:28:27 +0530 Subject: [PATCH 0368/1809] ARM: dts: qcom: Update skin and cx thermal config for HOLI Add quiet-therm,pa-therm0 and xo-therm skin sensors thermal config for HOLI based on latest recomondations. Add q6-hvx sensor thermal config mitigation for HOLI based on latest recomondations. Change-Id: If534b2c11786f89e165f3bae28b1f4b8c927c1ce --- qcom/holi-qrd.dtsi | 201 +++++++++++++++++++++++++++++++++++++---- qcom/holi-thermal.dtsi | 35 +++---- 2 files changed, 199 insertions(+), 37 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 776be0b0286c..e941e3c47126 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -326,64 +326,231 @@ &thermal_zones { quiet-therm-step { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; - trips { - quiet_modem_trip0: quiet-modem-trip0 { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { temperature = <42000>; hysteresis = <4000>; type = "passive"; }; - quiet_modem_trip1: quiet-modem-trip1 { + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { temperature = <44000>; hysteresis = <4000>; type = "passive"; }; - quiet_cx_trip: quiet-cx-trip { - temperature = <55000>; - hysteresis = <5000>; + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; type = "passive"; }; - quiet_modem_trip2: quiet-modem-trip2 { - temperature = <56000>; + battery_trip2: battery-trip2 { + temperature = <46000>; hysteresis = <2000>; type = "passive"; }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { - gpu-cdev { - trip = <&quiet_cx_trip>; + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; /* throttle to 565000000Hz */ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cdev0 { - trip = <&quiet_cx_trip>; - cooling-device = <&cdsp_sw 4 4>; + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; modem-skin-cdev0 { - trip = <&quiet_modem_trip0>; + trip = <&modem_skin_trip0>; cooling-device = <&modem_skin 1 1>; }; modem-skin-cdev1 { - trip = <&quiet_modem_trip1>; + trip = <&modem_skin_trip1>; cooling-device = <&modem_skin 2 2>; }; modem-skin-cdev2 { - trip = <&quiet_modem_trip2>; + trip = <&cx_trip>; cooling-device = <&modem_skin 3 3>; }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; }; }; }; diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index 13cb49406f32..c98479d3b71a 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -905,13 +905,13 @@ thermal-governor = "step_wise"; trips { - cdsp_trip0: cdsp-trip0 { + q6_hvx_trip0: q6-hvx-trip0 { temperature = <95000>; hysteresis = <0>; type = "passive"; }; - cdsp_cx_mon: cdsp-cx-mon { + q6_hvx_cx_mon: q6-hvx-cx-mon { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -919,32 +919,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&cdsp_trip0>; + q6-hvx-cdev0 { + trip = <&q6_hvx_trip0>; cooling-device = <&cdsp_sw THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; - cdsp-cx-cdev0 { - trip = <&cdsp_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cx-cdev1 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_tj 3 3>; + q6-hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_skin 3 3>; }; - cdsp-cx-cdev2 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_pa 3 3>; - }; - - cdsp-cx-cdev3 { - trip = <&cdsp_cx_mon>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&cdsp_sw 4 4>; }; }; }; From 112d45d5e72cd15aed3558af5b94ed037ea81937 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 19 Oct 2020 20:13:59 +0530 Subject: [PATCH 0369/1809] ARM: dts: qcom: Change cci3 gpio function from cci to gpio Configure the gpio pins for cci3 from cci control to gpio. Change-Id: I34fc8c7ae77ae42bc47a291db13fccd80671fd65 --- qcom/holi-pinctrl.dtsi | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/qcom/holi-pinctrl.dtsi b/qcom/holi-pinctrl.dtsi index 07f202cf86a7..7ef2bf71ba05 100644 --- a/qcom/holi-pinctrl.dtsi +++ b/qcom/holi-pinctrl.dtsi @@ -809,34 +809,6 @@ }; }; - cci3_active: cci3_active { - mux { - /* CLK, DATA */ - pins = "gpio2", "gpio3"; - function = "CCI_I2C"; - }; - - config { - pins = "gpio2", "gpio3"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci3_suspend: cci3_suspend { - mux { - /* CLK, DATA */ - pins = "gpio2", "gpio3"; - function = "CCI_I2C"; - }; - - config { - pins = "gpio2", "gpio3"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK 0*/ mux { From 4287e469a6fce4e95921849c847543e09253c7f7 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 24 Nov 2020 14:26:10 -0800 Subject: [PATCH 0370/1809] ARM: dts: msm: Add USB PHY related PDC interrupts and enable on sdxlemur Update USB PHY related PDC interrupts configuration and set qcom,use-pdc-interrupts flag to start using those for wakeup and resume functionality. Change-Id: Ic77276d5881456b2f7941097316a0c08afd30a4d --- qcom/sdxlemur-usb.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 007c96f3e20f..baa7270ff5c1 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -14,8 +14,13 @@ ranges; dma-ranges; - interrupts = <0 130 0>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&pdc 19 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 18 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; USB3_GDSC-supply = <&gcc_usb30_gdsc>; clocks = <&gcc GCC_USB30_MASTER_CLK>, From 407d0a7127972297b93c060304e7529b2a308a9e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 24 Nov 2020 18:24:46 -0800 Subject: [PATCH 0371/1809] ARM: dts: msm: update generic PCI node name on sdxlemur Update incorrect node name for generic PCIe node to match with its label on sdxlemur. Change-Id: I91b9c243bb1ff757f378934ab73f4571748d07a2 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index f70362342353..575214139b71 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -8,7 +8,7 @@ #address-cells = <5>; #size-cells = <0>; - pcie0_generic_ep: pcie0_rp_ep { + pcie0_generic_ep: pcie0_generic_ep { reg = <0 0 0 0 0>; qcom,iommu-group = <&pcie0_generic_ep_iommu_group>; From 80eb9cdb1f9232e098e58d516c66cda240f370cb Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Wed, 25 Nov 2020 12:22:57 +0800 Subject: [PATCH 0372/1809] ARM: dts: msm: Remove bluetooth bootstrap pin EDL_MODE settings Audio DLKM is ready to load automatically and will set this pin default state, so remove settings from bluetooth. CRs-Fixed: 2824381 Change-Id: Ia2612db5688abbce905d87389a74a708a5fd090c --- qcom/sdxlemur-bluetooth.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-bluetooth.dtsi b/qcom/sdxlemur-bluetooth.dtsi index d4848e87ad4c..51252f8a9a3c 100644 --- a/qcom/sdxlemur-bluetooth.dtsi +++ b/qcom/sdxlemur-bluetooth.dtsi @@ -17,7 +17,7 @@ bluetooth: bt_qca6490 { compatible = "qcom,qca6490"; pinctrl-names = "default"; - pinctrl-0 = <&bt_en_default &bt_edl_default>; + pinctrl-0 = <&bt_en_default>; qcom,bt-reset-gpio = <&pmx65_gpios 15 0>; /* BT_EN */ qcom,bt-sw-ctrl-gpio = <&pmx65_gpios 2 0>; /* SW_CTRL */ From 1fe6660ca9b872ba08ddd224d3e2c9e87bb96425 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 18 Nov 2020 10:32:36 +0530 Subject: [PATCH 0373/1809] ARM: dts: msm: remove SMB1398 clock frequency setting on holi Remove SMB1398 setting to change qupv3_se10_i2c clock frequency to 100kHz as it is not needed for SMB1398 v2 and v3. Change-Id: I65534d7fca92b9f494807b5d08944c766903d31c --- qcom/holi-mtp-usbc.dtsi | 1 - qcom/holi-mtp.dtsi | 1 - qcom/holi-qrd.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index 7c454128af97..d63ae35c1288 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -322,7 +322,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 74fd9e74591b..3434873e8a13 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -289,7 +289,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index e941e3c47126..651a5cad83ad 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -703,7 +703,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; From 1f9f5b30b52db4abe27b3b3211d6ddf44ed8c4dd Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 12 Oct 2020 22:29:48 +0800 Subject: [PATCH 0374/1809] ARM: dts: msm: Add jtagv8 devices for yupik Jtagv8 driver can be used to save and restore debug and ETM registers across power collapse. Change-Id: I410734f5c2c00cefd65bf7f475f55c0d4c5b4448 --- qcom/yupik.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bbefeda3d6dc..574f74aea9d5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -532,6 +532,94 @@ }; }; + jtag_mm0: jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From c44ace7d5679b4bbb58c7ec6cc2d0eb1c95fe8c7 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 24 Nov 2020 13:39:37 +0530 Subject: [PATCH 0375/1809] ARM: dts: msm: Update thermal mitigation config for SHIMA Update quiet-therm sensor skin thermal zone mitigation config for SHIMA based on latest recommendation. Add modem lte sub6 skin sensor based thermal zone mitigation config for SHIMA on latest recomondation. Change-Id: I1305de5650dae6d234fc4338b0dee9665a2c844d --- qcom/shima-qrd.dtsi | 107 +++++++++++++++++++++++++++++++++------- qcom/shima-thermal.dtsi | 88 +++++++++++++++++++++++++++++++++ 2 files changed, 178 insertions(+), 17 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 3c4d58ff97f2..512c64634168 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -205,30 +205,72 @@ thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>; trips { - quiet_gpu_trip: quiet-gpu-trip { - temperature = <45000>; - hysteresis = <0>; + quiet_batt_trip0: quiet-batt-trip0 { + temperature = <43000>; + hysteresis = <2000>; type = "passive"; }; - quiet_cpu4_trip: quiet-cpu4-trip { + quiet_batt_trip1: quiet-batt-trip1 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_modem_skin_trip0: quiet-modem-skin-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_gpu_trip: quiet-gpu-trip { temperature = <46000>; hysteresis = <0>; type = "passive"; }; - quiet_cpu7_trip: quiet-cpu7-trip { + quiet_batt_trip2: quiet-batt-trip2 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_modem_skin_trip1: quiet-modem-skin-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_apc_trip: quiet-apc-trip { temperature = <48000>; hysteresis = <0>; type = "passive"; }; + quiet_batt_trip3: quiet-batt-trip3 { + temperature = <49000>; + hysteresis = <2000>; + type = "passive"; + }; + quiet_cpu0_trip: quiet-cpu0-trip { temperature = <50000>; hysteresis = <0>; type = "passive"; }; + quiet_batt_trip4: quiet-batt-trip4 { + temperature = <50000>; + hysteresis = <1000>; + type = "passive"; + }; + + quiet_modem_skin_trip2: quiet-modem-skin-trip2 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + quiet_cx_trip: quiet-cx-trip { temperature = <55000>; hysteresis = <5000>; @@ -258,18 +300,9 @@ (THERMAL_MAX_LIMIT-7)>; }; - cpufreq4-cdev { - trip = <&quiet_cpu4_trip>; - /* throttle to 1651200KHz */ - cooling-device = <&CPU4 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-5)>; - }; - - cpufreq7-cdev { - trip = <&quiet_cpu7_trip>; - /* throttle to 1862400KHz */ - cooling-device = <&CPU7 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-5)>; + apc-cdev { + trip = <&quiet_apc_trip>; + cooling-device = <&apc1_cluster THERMAL_NO_LIMIT 5>; }; cdsp-cdev { @@ -286,6 +319,46 @@ trip = <&quiet_cx_trip>; cooling-device = <&modem_tj 3 3>; }; + + modem-skin-cdev0 { + trip = <&quiet_modem_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&quiet_modem_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&quiet_modem_skin_trip2>; + cooling-device = <&modem_skin 3 3>; + }; + + modem-batt-cdev0 { + trip = <&quiet_batt_trip0>; + cooling-device = <&battery_charger 8 8>; + }; + + modem-batt-cdev1 { + trip = <&quiet_batt_trip1>; + cooling-device = <&battery_charger 12 12>; + }; + + modem-batt-cdev2 { + trip = <&quiet_batt_trip2>; + cooling-device = <&battery_charger 14 14>; + }; + + modem-batt-cdev3 { + trip = <&quiet_batt_trip3>; + cooling-device = <&battery_charger 16 16>; + }; + + modem-batt-cdev4 { + trip = <&quiet_batt_trip4>; + cooling-device = <&battery_charger 18 18>; + }; }; }; }; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 6a5999deec8b..fe9edb42f5c3 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1411,6 +1411,94 @@ }; }; + modem-lte-sub6-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <54000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem_cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem_cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + modem-lte-sub6-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; + mx-pe-step { polling-delay-passive = <0>; polling-delay = <0>; From ddaae4656aaae25de9a8589682540a525b92b6a6 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 24 Nov 2020 14:41:27 +0530 Subject: [PATCH 0376/1809] ARM: dts: msm: Update BCL, Alarm and CPU thermal mitigation for SHIMA Update the BCL rule in SHIMA to include CDSP mitigation for all three violations. Update PM8350 alarm rule in SHIMA to have cpufreq as mitigation devcie instead of cpu-isolate cooling device for silver and gold cores. Update silver core mitigation to ensure minimum operating performance. Change-Id: I5ba29ee1e606cf9104e4ab4745606c473b9ea497 --- qcom/shima-thermal-overlay.dtsi | 53 ++++++++++++++++++++------------- qcom/shima-thermal.dtsi | 24 --------------- 2 files changed, 32 insertions(+), 45 deletions(-) diff --git a/qcom/shima-thermal-overlay.dtsi b/qcom/shima-thermal-overlay.dtsi index aa352a783037..e2f347492c47 100644 --- a/qcom/shima-thermal-overlay.dtsi +++ b/qcom/shima-thermal-overlay.dtsi @@ -49,6 +49,11 @@ trip = <&b_bcl_lvl0>; cooling-device = <&msm_gpu 2 2>; }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; @@ -68,6 +73,11 @@ trip = <&b_bcl_lvl1>; cooling-device = <&msm_gpu 4 4>; }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; }; }; @@ -78,6 +88,12 @@ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; }; }; @@ -98,6 +114,11 @@ trip = <&c_bcl_lvl0>; cooling-device = <&msm_gpu 2 2>; }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; @@ -118,6 +139,11 @@ trip = <&c_bcl_lvl1>; cooling-device = <&msm_gpu 4 4>; }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; }; }; @@ -129,6 +155,12 @@ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; }; }; @@ -151,27 +183,6 @@ THERMAL_MAX_LIMIT>; }; - pm8350_cpu0_freq { - trip = <&pm8350_trip0>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - pm8350_cpu1 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm8350_cpu2 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm8350_cpu3 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm8350_cpu4 { trip = <&pm8350_trip0>; cooling-device = <&cpu4_isolate 1 1>; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index fe9edb42f5c3..8d8dacd4cef4 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -834,12 +834,6 @@ cooling-device = <&cpu0_isolate 1 1>; }; - cpu00_cdev1 { - trip = <&cpu00_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu00_cdev2 { trip = <&cpu00_config1>; cooling-device = <&cpu0_hotplug 1 1>; @@ -872,12 +866,6 @@ cooling-device = <&cpu1_isolate 1 1>; }; - cpu01_cdev1 { - trip = <&cpu01_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu01_cdev2 { trip = <&cpu01_config1>; cooling-device = <&cpu1_hotplug 1 1>; @@ -910,12 +898,6 @@ cooling-device = <&cpu2_isolate 1 1>; }; - cpu02_cdev1 { - trip = <&cpu02_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu02_cdev2 { trip = <&cpu02_config1>; cooling-device = <&cpu2_hotplug 1 1>; @@ -948,12 +930,6 @@ cooling-device = <&cpu3_isolate 1 1>; }; - cpu03_cdev1 { - trip = <&cpu03_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu03_cdev2 { trip = <&cpu03_config1>; cooling-device = <&cpu3_hotplug 1 1>; From 4b0a5adb1939d9b5aea61834201710e70d05b34b Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 10 Nov 2020 21:40:11 +0530 Subject: [PATCH 0377/1809] dt-bindings: interconnect: update interconnect bindings Update interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: I4bca29bda915717690efd24bf80ce1e3bd3b4154 --- bindings/interconnect/qcom,yupik.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/interconnect/qcom,yupik.txt b/bindings/interconnect/qcom,yupik.txt index f60a0b12fe7e..094f92f0e756 100644 --- a/bindings/interconnect/qcom,yupik.txt +++ b/bindings/interconnect/qcom,yupik.txt @@ -14,6 +14,8 @@ Required properties : "qcom,yupik-aggre2_noc", "qcom,yupik-clk_virt", "qcom,yupik-config_noc", + "qcom,yupik-cnoc2", + "qcom,yupik-cnoc3", "qcom,yupik-dc_noc", "qcom,yupik-gem_noc", "qcom,yupik-lpass_ag_noc", From 3b55265d6c1c04aa13adaca4ac75049d1dfc81d5 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 10 Nov 2020 18:21:59 +0530 Subject: [PATCH 0378/1809] ARM: dts: msm: Update interconnect nodes for YUPIK Add bcm voter devices that live under RSC devices to allow interconnect providers to target their votes for meeting bandwidth constraints. Also update the interconnect nodes so that real provider drivers get probed. Change-Id: I2359c9b2b789891045d2d70f83d5b19ebc529646 --- qcom/yupik.dtsi | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bbefeda3d6dc..d8daa43d8821 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -816,59 +816,86 @@ #interconnect-cells = <1>; }; - config_noc: interconnect@1500000 { - compatible = "qcom,yupik-config_noc"; + cnoc2: interconnect@1500000 { + reg = <0x1500000 0x1000>; + compatible = "qcom,yupik-cnoc2"; + #interconnect-cells = <1>; + }; + + cnoc3: interconnect@1502000 { + reg = <0x1502000 0x1000>; + compatible = "qcom,yupik-cnoc3"; #interconnect-cells = <1>; }; mc_virt: interconnect@1580000 { + reg = <0x1580000 0x4>; compatible = "qcom,yupik-mc_virt"; #interconnect-cells = <1>; }; system_noc: interconnect@1680000 { + reg = <0x1680000 0x15480>; compatible = "qcom,yupik-system_noc"; #interconnect-cells = <1>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,yupik-aggre1_noc"; + reg = <0x016e0000 0x1c080>; #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x2b080>; compatible = "qcom,yupik-aggre2_noc"; #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1e080>; compatible = "qcom,yupik-mmss_noc"; #interconnect-cells = <1>; }; lpass_ag_noc: interconnect@3c40000 { + reg = <0x03c40000 0xf080>; compatible = "qcom,yupik-lpass_ag_noc"; #interconnect-cells = <1>; }; dc_noc: interconnect@90e0000 { + reg = <0x90e0000 0x5080>; compatible = "qcom,yupik-dc_noc"; #interconnect-cells = <1>; }; gem_noc: interconnect@9100000 { + reg = <0x9100000 0xe2200>; compatible = "qcom,yupik-gem_noc"; #interconnect-cells = <1>; }; nsp_noc: interconnect@a0c0000 { + reg = <0x0a0c0000 0x10000>; compatible = "qcom,yupik-nsp_noc"; #interconnect-cells = <1>; }; epss_l3_cpu: l3_cpu@18590000 { - compatible = "qcom,yupik-epss-l3-cpu"; + reg = <0x18590000 0x4000>; + compatible = "qcom,lahaina-epss-l3-cpu"; #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + status = "disabled"; }; apps_rsc: rsc@18200000 { From ea9228516acc7ff5c8415d958cff9dd41fd56c10 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 20 Nov 2020 12:31:01 +0530 Subject: [PATCH 0379/1809] dt-bindings: input: qpnp-power-on: Update "reg" property description Update the description of "reg" property to add the PON_PBS base address along with PON_HLOS base address. Also add "reg-names" property. Change-Id: I257950babd4b68f3ab933679bd94936813531e25 --- bindings/input/qpnp-power-on.txt | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt index d935a2a443d3..b1b16685dcb1 100644 --- a/bindings/input/qpnp-power-on.txt +++ b/bindings/input/qpnp-power-on.txt @@ -9,10 +9,18 @@ peripheral is connected to the host processor via the SPMI interface. Required properties: - compatible: Must be "qcom,qpnp-power-on" -- reg: Specifies the SPMI base address for this PON - (power-on) peripheral. +- reg: Specifies the SPMI base address for this + PON (power-on) peripheral. For PMICs that have + PON peripheral (GEN3) split into PON_HLOS and + PON_PBS, this can hold addresses of both. + PON_PBS base address needs to be specified for + such devices if "qcom,kdpwr-sw-debounce" is + specified. Optional properties: +- reg-names: For PON GEN1 and GEN2, it should be "pon". + For PON GEN3, it should include "pon_hlos" and + optionally "pon_pbs". - interrupts: Specifies the interrupts associated with PON. - interrupt-names: Specifies the interrupt names associated with the interrupts property. Must be a subset of @@ -245,3 +253,23 @@ Examples: qcom,pon-spare-reg-bit = <1>; }; }; + + pon_hlos@1300 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; + }; From a2607bacd2d074096f697bf38a8a1bfebea42b01 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 23 Nov 2020 21:08:12 +0530 Subject: [PATCH 0380/1809] ARM: dts: msm: add no-memory-wc to sram node for holi This flag indicates to the driver that SRAM memory region has not to be remapped as write combining. Change-Id: I05529a30066d373ce1fad9a88a6f18e9e4467b64 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 47a95eaeb137..e6014ee34a26 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -252,6 +252,7 @@ #address-cells = <2>; #size-cells = <2>; compatible = "mmio-sram"; + no-memory-wc; reg = <0x0 0x0fd04480 0x0 0x80>; ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; From 8b87ea3c6c6c48b83520eca1bb334d827cb154ac Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 25 Nov 2020 14:33:46 -0800 Subject: [PATCH 0381/1809] Revert "ARM: dts: msm: Disable PMX65 VBUS_DET on sdxlemur MTP-MBB and RCM-RC boards" This change reverts commit be1f95bbcdeda891892b6a47a307d9de52f99630. Disabling VBUS_DET causes adb enumeration to fail as usb extcon node need to be assigned an alternate device, such as pm7250b_pdphy. However, to get this properly working, we need PMIC HW initialization to be done in the bootloader stage. Hence reverting this until that is ready. Change-Id: Ie8efaab512cc74a4d61f88021c6d87ef001d5aae --- qcom/sdxlemur-mtp-mbb.dtsi | 4 ---- qcom/sdxlemur-rcm-rc.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 6b5d5c919674..834ad0b8e5de 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -216,7 +216,3 @@ "typec_mode", "pe_start"; }; - -&vbus_detect { - status = "disabled"; -}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 824582ac94dc..ed2936ca66c9 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -184,7 +184,3 @@ "typec_mode", "pe_start"; }; - -&vbus_detect { - status = "disabled"; -}; From 1e58c041b8ae0b3519c3b57603d04f934f8487c6 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Wed, 25 Nov 2020 18:24:12 +0530 Subject: [PATCH 0382/1809] ARM: dts: msm: Enable mproc drivers for SDXNIGHTJAR Enable smem, smp2p, glink for communication with remote host. Change-Id: Ibfce48c8e4e06f573194154180863e171042764e --- bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + qcom/sdxnightjar.dtsi | 178 ++++++++++++++++++--- 2 files changed, 157 insertions(+), 22 deletions(-) diff --git a/bindings/mailbox/qcom,apcs-kpss-global.txt b/bindings/mailbox/qcom,apcs-kpss-global.txt index 49702be69c3d..af6b3a22c0ee 100644 --- a/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -20,6 +20,7 @@ platforms. "qcom,scuba-apcs-hmss-global" "qcom,monaco-apcs-hmss-global" "qcom,sm8150-spcs-global" + "qcom,sdxnightjar-apcs-gcc" - reg: Usage: required diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 622d46a7c381..ed5983e23272 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -373,37 +373,171 @@ clock-names = "core_clk", "core_a_clk"; }; - qcom,smem@87e80000 { - compatible = "qcom,smem"; - reg = <0x87e80000 0xc0000>, - <0xb011008 0x4>, - <0x60000 0x6000>, - <0x193d000 0x8>; - reg-names = "smem", "irq-reg-base", "aux-mem1", - "smem_targ_info_reg"; - qcom,mpu-enabled; + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; - qcom,smd-modem { - compatible = "qcom,smd"; + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + apcs_glb: mailbox@0xb011008 { + compatible = "qcom,sdxnightjar-apcs-gcc"; + reg = <0xb011008 0x4>; + #mbox-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x6000>; + }; + + smem_mem: smem_region@87e80000 { + reg = <0x87e80000 0xc0000>; + no-map; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smd { + compatible = "qcom,smd"; + + modem { qcom,smd-edge = <0>; - qcom,smd-irq-offset = <0x0>; - qcom,smd-irq-bitmask = <0x1000>; - interrupts = <0 25 1>; - label = "modem"; + mboxes = <&apcs_glb 12>; + qcom,remote-pid = <1>; + interrupts = ; + label = "mpss"; + + qcom,smd-channels = "IPCRTR"; + qcom,modem_qrtr { + qcom,low-latency; + }; }; - qcom,smd-rpm { - compatible = "qcom,smd"; + rpm { qcom,smd-edge = <15>; - qcom,smd-irq-offset = <0x0>; - qcom,smd-irq-bitmask = <0x1>; - interrupts = <0 168 1>; + mboxes = <&apcs_glb 0>; + interrupts = ; label = "rpm"; - qcom,irq-no-suspend; - qcom,not-loadable; + + rpm_requests: rpm_requests@0 { + compatible = "qcom,rpm-smd"; + qcom,smd-channels = "rpm_requests"; + }; }; }; + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 15>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-data5-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA5_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl0"; + }; + + qcom,glinkpkt-data6-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA6_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl1"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-data21 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA21"; + qcom,glinkpkt-dev-name = "smd21"; + }; + + qcom,glinkpkt-data22 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA22"; + qcom,glinkpkt-dev-name = "smd22"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; From 8ef27580115eaaa02ca73c9582adfc7db1320991 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 26 Nov 2020 17:08:57 +0530 Subject: [PATCH 0383/1809] ARM: dts: qcom: update skin sensor modem mitigation threshold for shima Update skin sensor thermal zone threshold for modem level 3 mitigation for shima. Change-Id: Ibf9ccd1998becc541e1646ca2d2429800c6e57b4 --- qcom/shima-qrd.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 512c64634168..0cc752e49599 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -265,12 +265,6 @@ type = "passive"; }; - quiet_modem_skin_trip2: quiet-modem-skin-trip2 { - temperature = <50000>; - hysteresis = <4000>; - type = "passive"; - }; - quiet_cx_trip: quiet-cx-trip { temperature = <55000>; hysteresis = <5000>; @@ -331,7 +325,7 @@ }; modem-skin-cdev2 { - trip = <&quiet_modem_skin_trip2>; + trip = <&quiet_cx_trip>; cooling-device = <&modem_skin 3 3>; }; From a4d7fb12745c5fe67cba5095e63d8f5720f8f681 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 26 Nov 2020 17:17:15 +0530 Subject: [PATCH 0384/1809] ARM: dts: msm: Make sdhc aliases start from 0 Make sdhc aliases start from 0 instead of to create block devices starting from mmcblk0 for emmc and mmcblk1 for sdcard. Change-Id: I3cd709230a50afec0c9f3a8b481f458d9a15765b --- qcom/holi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 47a95eaeb137..7d7268c521a6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -41,8 +41,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ - sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &qupv3_se9_2uart; hsuart0 = &qupv3_se1_4uart; swr0 = &swr0; From b874d822148ba5b808fe710c188b55cd90986765 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 26 Nov 2020 18:11:11 +0530 Subject: [PATCH 0385/1809] dt-bindings: qpnp-amoled: add support to disable pulse skipping Add support to disable pulse skipping for customers that require it. When the property is added, IBB regulator is forced into CCM mode whenever it gets enabled. Change-Id: I46dbe4f411b0f4022105188349d7a6f4d1412254 --- bindings/regulator/qpnp-amoled-regulator.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/regulator/qpnp-amoled-regulator.txt b/bindings/regulator/qpnp-amoled-regulator.txt index 078df30b8dfb..11bba440bf1b 100644 --- a/bindings/regulator/qpnp-amoled-regulator.txt +++ b/bindings/regulator/qpnp-amoled-regulator.txt @@ -77,6 +77,12 @@ Subnode common properties for OLEDB and AB/IBB regulator devices. Definition: A boolean property to specify that IBB regulator needs to be configured in single phase always. +- qcom,ibb-enable-force-ccm-wa: + Usage: optional + Value type: + Definition: A boolean property to specify that IBB regulator needs to + be forced into CCM mode when it gets enabled. + Example: pm8150a_amoled: oledb@e000 { From dcb08f648448d2127c0ca2c021841e128463d51a Mon Sep 17 00:00:00 2001 From: Jinlong Mao Date: Thu, 26 Nov 2020 08:43:39 -0800 Subject: [PATCH 0386/1809] Revert "ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina" This reverts commit ae8150eac6573c0caff8153bfb4db7c0221dcfd6. Change-Id: Iaffe99667a84834907c710e500ed0e5d48845539 --- qcom/lahaina-coresight.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index b773c609af39..ff7750e6f034 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -154,7 +154,6 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; - dma-coherent; qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; From 1b046bf67327c44b108fe79866b56448133a391e Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 23 Nov 2020 21:20:07 +0530 Subject: [PATCH 0387/1809] ARM: dts: msm: update PMU cache and log buffer addresses for holi target Locations of PMU cache and log buffer are changed on RIMPS side. Update them accordingly for driver. Change-Id: If396306e148ff670eb10c9849f3f367742d42fe7 --- qcom/holi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e6014ee34a26..2b043ec48608 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1444,7 +1444,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; - reg = <0x0fd04980 0x300>; + reg = <0xfd04580 0x280>; reg-names = "pmu-base"; cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { @@ -1470,7 +1470,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; - reg = <0x0fd04980 0x300>; + reg = <0xfd04580 0x280>; reg-names = "pmu-base"; cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { @@ -1513,8 +1513,8 @@ rimps_log: qcom,rimps_log@fd04780 { compatible = "qcom,rimps-log"; - reg = <0x0fd04580 0x200>, - <0x0fd04780 0x200>; + reg = <0x0fd04800 0x200>, + <0x0fd04A00 0x200>; mboxes = <&rimps 1>; }; From 25f03c3cd7d0ed96d1929ee9976ec57547c03fff Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 19 Nov 2020 10:42:23 +0530 Subject: [PATCH 0388/1809] ARM: dts: msm: Enable KPDPWR software debounce for PMK8350 Enable the SW debounce handling for KPDPWR_N rising edge. Change-Id: I6a083b1436ae4339de1eef58ffe0f464df02b1e3 --- qcom/pmk8350.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi index 164366a0734b..c8727dd690ee 100644 --- a/qcom/pmk8350.dtsi +++ b/qcom/pmk8350.dtsi @@ -29,10 +29,12 @@ pon_hlos@1300 { compatible = "qcom,qpnp-power-on"; - reg = <0x1300>; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; qcom,pon_1 { qcom,pon-type = ; From a9deebd92d56e32078681a2036aaa19fdf914bd2 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 15 Nov 2020 12:46:17 +0530 Subject: [PATCH 0389/1809] ARM: dts: qcom: Add RPMh controlled PMIC regulators for yupik Add rpmh-regulator device nodes for the PMIC PM7325, PM8350C, and PMR735A regulators. This ensures that consumers are able to modify the physical state of these PMIC regulators. Change-Id: I30719e56559e1f2f3cf31decb15ef168f6fe5ca6 --- qcom/yupik-regulators.dtsi | 914 +++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 2 +- 2 files changed, 915 insertions(+), 1 deletion(-) create mode 100644 qcom/yupik-regulators.dtsi diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi new file mode 100644 index 000000000000..9e45d4640ba9 --- /dev/null +++ b/qcom/yupik-regulators.dtsi @@ -0,0 +1,914 @@ +#include + +&apps_rsc { + rpmh-regulator-smpb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb1"; + S1B: + pm7325_s1: regulator-pm7325-s1 { + regulator-name = "pm7325_s1"; + qcom,set = ; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1872000>; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + VDD_EBI_LEVEL: + S2B_LEVEL: + pm7325_s2_level: regulator-pm7325-s2-level { + regulator-name = "pm7325_s2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: + pm7325_s7: regulator-pm7325-s7 { + regulator-name = "pm7325_s7"; + qcom,set = ; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + qcom,init-voltage = <972000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: + pm7325_s8: regulator-pm7325-s8 { + regulator-name = "pm7325_s8"; + qcom,set = ; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + qcom,init-voltage = <1272000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1B: + pm7325_l1: regulator-pm7325-l1 { + regulator-name = "pm7325_l1"; + qcom,set = ; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2B: + pm7325_l2: regulator-pm7325-l2 { + regulator-name = "pm7325_l2"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3B: + pm7325_l3: regulator-pm7325-l3 { + regulator-name = "pm7325_l3"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + qcom,init-voltage = <504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + VDD_LPI_MX_LEVEL: + L4B_LEVEL: + pm7325_l4_level: regulator-pm7325-l4-level { + regulator-name = "pm7325_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + VDD_LPI_CX_LEVEL: + L5B_LEVEL: + pm7325_l5_level: regulator-pm7325-l5-level { + regulator-name = "pm7325_l5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6B: + pm7325_l6: regulator-pm7325-l6 { + regulator-name = "pm7325_l6"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L7B: + pm7325_l7: regulator-pm7325-l7 { + regulator-name = "pm7325_l7"; + qcom,set = ; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2952000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8B: + pm7325_l8: regulator-pm7325-l8 { + regulator-name = "pm7325_l8"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9B: + pm7325_l9: regulator-pm7325-l9 { + regulator-name = "pm7325_l9"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L10B: + pm7325_l10: regulator-pm7325-l10 { + regulator-name = "pm7325_l10"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L11B: + pm7325_l11: regulator-pm7325-l11 { + regulator-name = "pm7325_l11"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12B: + pm7325_l12: regulator-pm7325-l12 { + regulator-name = "pm7325_l12"; + qcom,set = ; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <751000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L13B: + pm7325_l13: regulator-pm7325-l13 { + regulator-name = "pm7325_l13"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <530000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L14B: + pm7325_l14: regulator-pm7325-l14 { + regulator-name = "pm7325_l14"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L15B: + pm7325_l15: regulator-pm7325-l15 { + regulator-name = "pm7325_l15"; + qcom,set = ; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + qcom,init-voltage = <765000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L16B: + pm7325_l16: regulator-pm7325-l16 { + regulator-name = "pm7325_l16"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L17B: + pm7325_l17: regulator-pm7325-l17 { + regulator-name = "pm7325_l17"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L18B: + pm7325_l18: regulator-pm7325-l18 { + regulator-name = "pm7325_l18"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L19B: + pm7325_l19: regulator-pm7325-l19 { + regulator-name = "pm7325_l19"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc1"; + S1C: + pm8350c_s1: regulator-pm8350c-s1 { + regulator-name = "pm8350c_s1"; + qcom,set = ; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + qcom,init-voltage = <2190000>; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S2C_LEVEL: + pm8350c_s2_level: regulator-pm8350c-s2-level { + regulator-name = "pm8350c_s2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S2C_LEVEL_AO: + pm8350c_s2_level_ao: regulator-pm8350c-s2-level-ao { + regulator-name = "pm8350c_s2_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + S5C_LEVEL: + pm8350c_s5_level: regulator-pm8350c-s5-level { + regulator-name = "pm8350c_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: + S7C_LEVEL: + pm8350c_s7_level: regulator-pm8350c-s7-level { + regulator-name = "pm8350c_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpc9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc9"; + S9C: + pm8350c_s9: regulator-pm8350c-s9 { + regulator-name = "pm8350c_s9"; + qcom,set = ; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1084000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MX_LEVEL>; + VDD_MX_LEVEL: + S10C_LEVEL: + pm8350c_s10_level: regulator-pm8350c-s10-level { + regulator-name = "pm8350c_s10_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MX_LEVEL_AO: + S10C_LEVEL_AO: + pm8350c_s10_level_ao: regulator-pm8350c-s10-level-ao { + regulator-name = "pm8350c_s10_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobc1"; + BOB: pm8350c_bob: regulator-pm8350c-bob { + regulator-name = "pm8350c_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1C: + pm8350c_l1: regulator-pm8350c-l1 { + regulator-name = "pm8350c_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2C: + pm8350c_l2: regulator-pm8350c-l2 { + regulator-name = "pm8350c_l2"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3C: + pm8350c_l3: regulator-pm8350c-l3 { + regulator-name = "pm8350c_l3"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + qcom,init-voltage = <2800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4C: + pm8350c_l4: regulator-pm8350c-l4 { + regulator-name = "pm8350c_l4"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L5C: + pm8350c_l5: regulator-pm8350c-l5 { + regulator-name = "pm8350c_l5"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6C: + pm8350c_l6: regulator-pm8350c-l6 { + regulator-name = "pm8350c_l6"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2960000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L7C: + pm8350c_l7: regulator-pm8350c-l7 { + regulator-name = "pm8350c_l7"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8C: + pm8350c_l8: regulator-pm8350c-l8 { + regulator-name = "pm8350c_l8"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9C: + pm8350c_l9: regulator-pm8350c-l9 { + regulator-name = "pm8350c_l9"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2960000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L10C: + pm8350c_l10: regulator-pm8350c-l10 { + regulator-name = "pm8350c_l10"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L11C: + pm8350c_l11: regulator-pm8350c-l11 { + regulator-name = "pm8350c_l11"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12C: + pm8350c_l12: regulator-pm8350c-l12 { + regulator-name = "pm8350c_l12"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L13C: + pm8350c_l13: regulator-pm8350c-l13 { + regulator-name = "pm8350c_l13"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1D: + pm8350b_l1: regulator-pm8350b-l1 { + regulator-name = "pm8350b_l1"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2E: + pmr735a_l2: regulator-pmr735a-l2 { + regulator-name = "pmr735a_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3E: + pmr735a_l3: regulator-pmr735a-l3 { + regulator-name = "pmr735a_l3"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1020000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4E: + pmr735a_l4: regulator-pmr735a-l4 { + regulator-name = "pmr735a_l4"; + qcom,set = ; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1776000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L5E: + pmr735a_l5: regulator-pmr735a-l5 { + regulator-name = "pmr735a_l5"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6E: + pmr735a_l6: regulator-pmr735a-l6 { + regulator-name = "pmr735a_l6"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <904000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d8daa43d8821..60d74c52c43f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1344,8 +1344,8 @@ #include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-pm.dtsi" -#include "yupik-stub-regulator.dtsi" #include "ipcc-test-yupik.dtsi" +#include "yupik-regulators.dtsi" &gcc_pcie_0_gdsc { qcom,support-hw-trigger; From 666f3418c7ce4e4fe3dd3bbdab0c86c5f086d7e4 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Fri, 27 Nov 2020 13:27:11 +0530 Subject: [PATCH 0390/1809] ARM: dts: msm: Add trustedvm enablement nodes for Yupik Add trusted VM configuration for Yupik SoC. Change-Id: I4f628c7958ac32ebd41e99243a6849b7b21812ed --- qcom/yupik.dtsi | 79 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bbefeda3d6dc..c5f47c0f6775 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -339,6 +339,26 @@ reg = <0x0 0xc0000000 0x0 0x5100000>; }; + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; @@ -1219,6 +1239,65 @@ interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + qcom,trustedvm@d0800000 { + compatible = "qcom,pil-tz-generic"; + status = "ok"; + qcom,pas-id = <28>; + qcom,firmware-name = "trustedvm"; + memory-region = <&pil_trustedvm_mem>; + }; + + qcom,guestvm_loader { + compatible = "qcom,guestvm-loader"; + image_to_be_loaded = "trustedvm"; + }; + + qcom,svm_neuron_block { + compatible = "qcom,neuron-service"; + #address-cells = <1>; + #size-cells = <0>; + protocol { + compatible = "qcom,neuron-protocol-block"; + processes = "server"; + }; + + application { + compatible = "qcom,neuron-block-server"; + }; + + channel@0 { + compatible = "qcom,neuron-channel-haven-shmem"; + reg = <0>; + class = "message-queue"; + direction = "receive"; + max-size = <0 65536>; + shared-buffer = <&chan0_shbuf>; + qcom,primary; + haven-label = <1>; + peer-name = <2>; + }; + + channel@1 { + compatible = "qcom,neuron-channel-haven-shmem"; + reg = <1>; + class = "message-queue"; + direction = "send"; + max-size = <0 65536>; + shared-buffer = <&chan1_shbuf>; + qcom,primary; + haven-label = <2>; + peer-name = <2>; + }; + }; + + qrtr-haven { + compatible = "qcom,qrtr-haven"; + qcom,master; + haven-label = <3>; + peer-name = <2>; + shared-buffer = <&qrtr_shbuf>; + }; + qcom,lpass@3700000 { compatible = "qcom,pil-tz-generic"; reg = <0x3700000 0x00100>; From 1f265a56a855627fd356fb33307b9c6b2b22fb90 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 27 Nov 2020 16:05:23 +0530 Subject: [PATCH 0391/1809] ARM: dts: qcom: use separate thermal zone names for modem pa for shima Use separate thermal zone node names for same modem pa sensors with different thermal governors. Otherwise second thermal zone node will override first one. Change-Id: I7e2d76eb13f9466b451639ab9cea8e8b43185c67 --- qcom/shima-thermal.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 8d8dacd4cef4..653a24778481 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1387,7 +1387,7 @@ }; }; - modem-lte-sub6-pa1 { + modem-lte-pa1-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; @@ -1431,7 +1431,7 @@ }; }; - modem-lte-sub6-pa2 { + modem-lte-pa2-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; From 5dabbf5407b3b993886e066285bbbefdb24a620c Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Fri, 27 Nov 2020 16:07:16 +0530 Subject: [PATCH 0392/1809] ARM: dts: msm: switch off kpti on shima/lahaina/yupik Turn off kpti on targets that are not vulnerable. Change-Id: I2d4aecc28f22bb460d93a79a3de34da9c8e75ba7 --- qcom/lahaina.dtsi | 2 +- qcom/shima.dtsi | 2 +- qcom/yupik.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index e7a0171f6fc1..d130a7c3b4c3 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -34,7 +34,7 @@ #size-cells = <2>; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 903cd3b29602..39225b49decd 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -33,7 +33,7 @@ #size-cells = <2>; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d8daa43d8821..b7d3a5295abb 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -361,7 +361,7 @@ soc: soc { }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; }; From e74cc92e7b9f08b949e801df5db79841fba4263f Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 24 Nov 2020 12:22:27 +0530 Subject: [PATCH 0393/1809] ARM: dts: msm: Change micbias no for VA DMIC for shima Update micbias no for VA DMIC as per schematics. Change-Id: I5a3dcfb2ea2938e869da71a9c77c6fa507c47634 --- qcom/shima-idps-digital-mics.dtsi | 16 ++++++++-------- qcom/shima-qrd.dtsi | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/shima-idps-digital-mics.dtsi b/qcom/shima-idps-digital-mics.dtsi index c2cd1782aca2..4d7d74fc6275 100644 --- a/qcom/shima-idps-digital-mics.dtsi +++ b/qcom/shima-idps-digital-mics.dtsi @@ -24,13 +24,13 @@ "TX DMIC0", "Digital Mic0", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "Digital Mic1", - "TX DMIC1", "MIC BIAS3", + "TX DMIC1", "MIC BIAS1", "TX DMIC2", "Digital Mic2", - "TX DMIC2", "MIC BIAS4", + "TX DMIC2", "MIC BIAS3", "TX DMIC3", "Digital Mic3", - "TX DMIC3", "MIC BIAS1", + "TX DMIC3", "MIC BIAS3", "TX DMIC4", "Digital Mic4", - "TX DMIC4", "MIC BIAS3", + "TX DMIC4", "MIC BIAS4", "TX DMIC5", "Digital Mic5", "TX DMIC5", "MIC BIAS4", "IN1_HPHL", "HPHL_OUT", @@ -58,10 +58,10 @@ "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3", "VA DMIC4", "VA MIC BIAS4", "VA DMIC5", "VA MIC BIAS4"; qcom,msm-mbhc-hphl-swh = <1>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 512c64634168..4bbe7fd29657 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -447,10 +447,10 @@ "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS4", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3", + "VA DMIC4", "VA MIC BIAS4", "VA DMIC5", "VA MIC BIAS4"; qcom,swr-dmic-max-devs = <0>; From c0ee7832ec69982ba6ed89ebc069137fa6b1b818 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Fri, 27 Nov 2020 18:10:38 +0530 Subject: [PATCH 0394/1809] ARM: dts: msm: Add dma coherent flag for ufs Add dma coherent flag to avoid inconsistency with the data transfer through dma involving ufs. Change-Id: I733f0fc46ed04f51a9368c37e1e85bac347d3822 --- qcom/yupik.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bbefeda3d6dc..8b94e065b4d1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -764,6 +764,8 @@ resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; + dma-coherent; + rpm-level = <3>; spm-level = <3>; From b04ca6dd34f7160df0ff68c22e247b4cdf4a6803 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 27 Nov 2020 22:57:12 +0530 Subject: [PATCH 0395/1809] ARM: dts: msm: Add support for RPMHCC for YUPIK Enable the rpmh clock driver and use dummy clock driver for YUPIK RUMI. Change-Id: Ib251309f00a0afd18bc3896b22d06c27e4d0a349 --- bindings/clock/qcom,rpmh-clk.txt | 1 + qcom/yupik-rumi.dtsi | 20 ++++++++++++++++++++ qcom/yupik.dtsi | 29 ++++++----------------------- 3 files changed, 27 insertions(+), 23 deletions(-) diff --git a/bindings/clock/qcom,rpmh-clk.txt b/bindings/clock/qcom,rpmh-clk.txt index bb1dacb9491c..2f8d511d701f 100644 --- a/bindings/clock/qcom,rpmh-clk.txt +++ b/bindings/clock/qcom,rpmh-clk.txt @@ -13,6 +13,7 @@ Required properties : "qcom,sdm845-rpmh-clk" "qcom,sm8150-rpmh-clk" "qcom,sdxlemur-rpmh-clk" + "qcom,yupik-rpmh-clk" - #clock-cells : must contain 1 diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 138f7c0482f8..66cf1b93aed5 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -28,6 +28,21 @@ 0x0 0x4>; }; + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; }; &usb0 { @@ -78,6 +93,11 @@ qcom,rumi_platform; }; +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; + &gcc { clocks = <&bi_tcxo>, <&sleep_clk>; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d8daa43d8821..8e3c45f16b00 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -569,22 +569,6 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <4>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <4>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - aopcc: qcom,aopcc { compatible = "qcom,dummycc"; clock-output-names = "aopcc_clocks"; @@ -592,13 +576,6 @@ #reset-cells = <1>; }; - rpmhcc: qcom,rpmhcc { - compatible = "qcom,dummycc"; - clock-output-names = "rpmhcc_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - gcc: clock-controller@100000 { compatible = "qcom,yupik-gcc", "syscon"; reg = <0x100000 0x1f0000>; @@ -918,6 +895,12 @@ system_pm { compatible = "qcom,system-pm"; }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,yupik-rpmh-clk"; + #clock-cells = <1>; + }; + }; disp_rsc: rsc@af20000 { From 0f4b18cdadbec95193c1f6218a688ba9136277a9 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Sun, 29 Nov 2020 06:58:03 +0530 Subject: [PATCH 0396/1809] ARM: dts: msm: Bind sdcard to slot 1 Bind sdcard to slot 1 to avoid slot mixup between emmc and sdcard. Change-Id: I56c74bd7b5a09649f2a54bc22ddb901363216e03 --- qcom/lahaina.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index e7a0171f6fc1..7421bb308061 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -51,7 +51,7 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &qupv3_se3_2uart; hsuart0 = &qupv3_se18_4uart; pci-domain0 = &pcie0; /* PCIe0 domain */ From 71e4c799a62f0e93f0aa25244ef7309b4e36deda Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Sun, 29 Nov 2020 07:00:10 +0530 Subject: [PATCH 0397/1809] ARM: dts: msm: Bind emmc and sdcard slot to 0 & 1 Bind emmc and sdcard slot to 0 & 1 respectively to avoid emmc and sdcard slot mixup. Change-Id: I85196b467eb1e1b938fc7f657a95d7a34b19532f --- qcom/shima.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 903cd3b29602..2aed904f638d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -50,8 +50,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ - sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ swr0 = &swr0; swr1 = &swr1; swr2 = &swr2; From f3ce2ebedb3b918346302c6c98a1a12cb2225fc0 Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Fri, 6 Nov 2020 11:37:37 +0800 Subject: [PATCH 0398/1809] ARM: dts: msm: Add camera device tree inclusions for lahaina hdk Need update camera sensor node for lahaina hdk platform. Change-Id: Iea2b9b858b834029406a3d698779749c21d652ae --- qcom/lahaina-hdk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 6af3c39a4c7a..3f1d30fee0e1 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -1,4 +1,5 @@ #include "lahaina-qrd-common.dtsi" +#include "camera/lahaina-camera-sensor-hdk.dtsi" &wsa883x_0222 { status = "disabled"; From c65cbc41b43c22df7eda7b664552a41ca21442b4 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Wed, 14 Oct 2020 16:37:18 +0530 Subject: [PATCH 0399/1809] ARM: dts: msm: Add ICNSS2 DT node for Yupik Add ICNSS2 DT node for Yupik Change-Id: I55a18081ba800c74a64b7ef91b4ac9d991a36cd5 --- qcom/yupik.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6fc836586383..519862cae97c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -639,6 +639,47 @@ status = "disabled"; }; + icnss2: qcom,wcn6750 { + compatible = "qcom,wcn6750"; + reg = <0x17a10040 0x0>; + reg-names = "msi_addr"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; + cnss-daemon-support; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>; From 1bd807832928968c4eb2aa7f6cec22596e99bcf8 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Fri, 20 Nov 2020 12:32:44 +0530 Subject: [PATCH 0400/1809] ARM: dts: msm: Add initial device tree for Yupik for IDP/ATP Add initial device tree to support Yupik IDP and ATP platforms. Change-Id: Ie90cf5ffde58e900706f8e4923d1d49e50acd477 --- bindings/arm/msm/msm.txt | 2 ++ qcom/Makefile | 13 +++++++++++-- qcom/yupik-atp-overlay.dts | 11 +++++++++++ qcom/yupik-atp.dts | 10 ++++++++++ qcom/yupik-atp.dtsi | 2 ++ qcom/yupik-idp-overlay.dts | 11 +++++++++++ qcom/yupik-idp.dts | 10 ++++++++++ qcom/yupik-idp.dtsi | 2 ++ qcom/yupik-idps-digital-mics-overlay.dts | 11 +++++++++++ qcom/yupik-idps-digital-mics.dts | 10 ++++++++++ qcom/yupik-idps-digital-mics.dtsi | 4 ++++ 11 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 qcom/yupik-atp-overlay.dts create mode 100644 qcom/yupik-atp.dts create mode 100644 qcom/yupik-atp.dtsi create mode 100644 qcom/yupik-idp-overlay.dts create mode 100644 qcom/yupik-idp.dts create mode 100644 qcom/yupik-idp.dtsi create mode 100644 qcom/yupik-idps-digital-mics-overlay.dts create mode 100644 qcom/yupik-idps-digital-mics.dts create mode 100644 qcom/yupik-idps-digital-mics.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 339b6c9b59f5..c529b3464dc0 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -222,6 +222,8 @@ compatible = "qcom,shima-idp" compatible = "qcom,shima-atp" compatible = "qcom,shima-qrd" compatible = "qcom,yupik-rumi" +compatible = "qcom,yupik-idp" +compatible = "qcom,yupik-atp" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index ab69f402e2f2..793a51038a7f 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -136,11 +136,20 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_YUPIK) += \ - yupik-rumi-overlay.dtbo + yupik-rumi-overlay.dtbo \ + yupik-idp-overlay.dtbo \ + yupik-atp-overlay.dtbo \ + yupik-idps-digital-mics-overlay.dtbo yupik-rumi-overlay.dtbo-base := yupik.dtb +yupik-idp-overlay.dtbo-base := yupik.dtb +yupik-atp-overlay.dtbo-base := yupik.dtb +yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb else -dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb +dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ + yupik-idp.dtb \ + yupik-atp.dtb \ + yupik-idps-digital-mics.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/yupik-atp-overlay.dts b/qcom/yupik-atp-overlay.dts new file mode 100644 index 000000000000..f237148be030 --- /dev/null +++ b/qcom/yupik-atp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik ATP"; + compatible = "qcom,yupik-atp", "qcom,yupik", "qcom,atp"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/yupik-atp.dts b/qcom/yupik-atp.dts new file mode 100644 index 000000000000..3072654a2103 --- /dev/null +++ b/qcom/yupik-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik ATP"; + compatible = "qcom,yupik-atp", "qcom,yupik", "qcom,atp"; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-atp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/yupik-idp-overlay.dts b/qcom/yupik-idp-overlay.dts new file mode 100644 index 000000000000..efa85633b394 --- /dev/null +++ b/qcom/yupik-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-idp.dts b/qcom/yupik-idp.dts new file mode 100644 index 000000000000..51843e3fc21e --- /dev/null +++ b/qcom/yupik-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-idp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/yupik-idps-digital-mics-overlay.dts b/qcom/yupik-idps-digital-mics-overlay.dts new file mode 100644 index 000000000000..5ee602b037e0 --- /dev/null +++ b/qcom/yupik-idps-digital-mics-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-idps-digital-mics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDPS + DIGITAL MICS"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-idps-digital-mics.dts b/qcom/yupik-idps-digital-mics.dts new file mode 100644 index 000000000000..0adab7cdd2c4 --- /dev/null +++ b/qcom/yupik-idps-digital-mics.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-idps-digital-mics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDPS + DIGITAL MICS"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-idps-digital-mics.dtsi b/qcom/yupik-idps-digital-mics.dtsi new file mode 100644 index 000000000000..885e5af51402 --- /dev/null +++ b/qcom/yupik-idps-digital-mics.dtsi @@ -0,0 +1,4 @@ +#include "yupik-idp.dtsi" + +&soc { +}; From 879b89687182cc19c5977358c8b10a8f158ef062 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 17 Nov 2020 15:45:01 +0530 Subject: [PATCH 0401/1809] ARM: dts: msm: Add eMMC, SD card support for yupik Add eMMC, SD card support for yupik. Change-Id: I09dfa009575967b5263a7b057a1e4e758c7990ed --- qcom/yupik-pinctrl.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-rumi.dtsi | 42 ++++++++++++++++- qcom/yupik.dtsi | 77 ++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index acc672a31e62..5c51c0efa182 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -37,6 +37,108 @@ }; }; + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio91"; + bias-disable; + drive-strength = <2>; + }; + }; + qupv3_se0_spi_pins: qupv3_se0_spi_pins { qupv3_se0_spi_active: qupv3_se0_spi_active { mux { diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 66cf1b93aed5..33c0546db1eb 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -1,5 +1,5 @@ #include - +#include &soc { timer { clock-frequency = <5000000>; @@ -54,6 +54,46 @@ }; }; +&sdhc_1 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + cap-mmc-highspeed; +}; + +&sdhc_2 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cap-sd-highspeed; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qrbtc-sdm845"; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6fc836586383..4050cb4d5098 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -26,6 +26,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ }; firmware: firmware { @@ -1229,6 +1231,81 @@ interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + sdhc_1: sdhci@7C4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + non-removable; + supports-cqe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; + }; + qcom,lpass@3700000 { compatible = "qcom,pil-tz-generic"; reg = <0x3700000 0x00100>; From 38a946e4a5d33b5b0436724a42276e859a45a377 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 25 Nov 2020 19:40:16 +0530 Subject: [PATCH 0402/1809] ARM: dts: msm: add no-memory-wc to sram node for holi This flag indicates to the driver that SRAM memory region has not to be remapped as write combined. Change-Id: I05529a30066d373ce1fad9a88a6f18e9e4467b64 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 47a95eaeb137..e6014ee34a26 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -252,6 +252,7 @@ #address-cells = <2>; #size-cells = <2>; compatible = "mmio-sram"; + no-memory-wc; reg = <0x0 0x0fd04480 0x0 0x80>; ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; From c90b98c48b7d590138bed5d291eaa109583fda38 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 23 Nov 2020 21:20:07 +0530 Subject: [PATCH 0403/1809] ARM: dts: msm: update PMU cache and log buffer addresses for holi target Locations of PMU cache and log buffer are changed on RIMPS side. Update them accordingly for driver. Change-Id: If396306e148ff670eb10c9849f3f367742d42fe7 --- qcom/holi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 47a95eaeb137..2713b380e533 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1443,7 +1443,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; - reg = <0x0fd04980 0x300>; + reg = <0xfd04580 0x280>; reg-names = "pmu-base"; cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { @@ -1469,7 +1469,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; - reg = <0x0fd04980 0x300>; + reg = <0xfd04580 0x280>; reg-names = "pmu-base"; cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { @@ -1512,8 +1512,8 @@ rimps_log: qcom,rimps_log@fd04780 { compatible = "qcom,rimps-log"; - reg = <0x0fd04580 0x200>, - <0x0fd04780 0x200>; + reg = <0x0fd04800 0x200>, + <0x0fd04A00 0x200>; mboxes = <&rimps 1>; }; From 93438e5208137055619708c9ffaf22781c0e20af Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 18 Nov 2020 10:32:36 +0530 Subject: [PATCH 0404/1809] ARM: dts: msm: remove SMB1398 clock frequency setting on holi Remove SMB1398 setting to change qupv3_se10_i2c clock frequency to 100kHz as it is not needed for SMB1398 v2 and v3. Change-Id: I65534d7fca92b9f494807b5d08944c766903d31c --- qcom/holi-mtp-usbc.dtsi | 1 - qcom/holi-mtp.dtsi | 1 - qcom/holi-qrd.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index 7c454128af97..d63ae35c1288 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -322,7 +322,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 74fd9e74591b..3434873e8a13 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -289,7 +289,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index e941e3c47126..651a5cad83ad 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -703,7 +703,6 @@ }; &qupv3_se10_i2c { - qcom,clk-freq-out = <100000>; status = "ok"; #include "smb1398.dtsi" }; From e641dc696ccbfc05972f612c48f01016790a5cc3 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 26 Nov 2020 17:17:15 +0530 Subject: [PATCH 0405/1809] ARM: dts: msm: Make sdhc aliases start from 0 Make sdhc aliases start from 0 instead of to create block devices starting from mmcblk0 for emmc and mmcblk1 for sdcard. Change-Id: I3cd709230a50afec0c9f3a8b481f458d9a15765b --- qcom/holi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 47a95eaeb137..7d7268c521a6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -41,8 +41,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ - sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &qupv3_se9_2uart; hsuart0 = &qupv3_se1_4uart; swr0 = &swr0; From 542a4447865f5c4e6fbc66fe050a9fd3c31fc5ff Mon Sep 17 00:00:00 2001 From: Siddartha Mohanadoss Date: Mon, 23 Nov 2020 17:44:58 -0800 Subject: [PATCH 0406/1809] ARM: dts: msm: Add PCIe EP and MHI device for sdxlemur PCIe end point device driver and Modem host interface driver is used to support mobile broadband interface module. Change-Id: I3237dfcc56098df9efda9b5c59976deaf829a521 --- qcom/sdxlemur-pinctrl.dtsi | 36 ++++++ qcom/sdxlemur.dtsi | 243 +++++++++++++++++++++++++++++++++++++ 2 files changed, 279 insertions(+) diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 27bb483e2d35..bf46e4507e98 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -216,6 +216,42 @@ }; }; + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + i2c_1 { i2c_1_active: i2c_1_active { mux { diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 279d02c7ca5e..7ade3cdbd9a3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -785,6 +785,249 @@ compatible = "qcom,msm_gsi"; }; + + pcie_ep: qcom,pcie@40002000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40002000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x01c03000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 0>; + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + vreg-1p8-supply = <&pmx65_l1>; + vreg-0p9-supply = <&pmx65_l4>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 3000>; + qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0308>; + qcom,pcie-link-speed = <4>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x1214>; + qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,aoss-rst-clr; + + qcom,phy-init = <0x1240 0x01 0x0 + 0x100c 0x02 0x0 + 0x1044 0x14 0x0 + 0x104c 0x07 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x27 0x0 + 0x1078 0x0a 0x0 + 0x107c 0x17 0x0 + 0x1080 0x19 0x0 + 0x1084 0x00 0x0 + 0x1088 0x03 0x0 + 0x1094 0x00 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0xff 0x0 + 0x10b0 0x04 0x0 + 0x10b4 0xff 0x0 + 0x10b8 0x09 0x0 + 0x10bc 0x19 0x0 + 0x10c4 0x28 0x0 + 0x117c 0x06 0x0 + 0x10ec 0xfb 0x0 + 0x10f0 0x01 0x0 + 0x10f4 0xfb 0x0 + 0x10f8 0x01 0x0 + 0x110c 0x02 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x20 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0364 0xcc 0x0 + 0x0368 0x12 0x0 + 0x036c 0xcc 0x0 + 0x0374 0x4a 0x0 + 0x0378 0x29 0x0 + 0x037c 0xc5 0x0 + 0x0380 0xac 0x0 + 0x0384 0xb6 0x0 + 0x0388 0xc0 0x0 + 0x038c 0x07 0x0 + 0x0390 0xfb 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xc5 0x0 + 0x039c 0xee 0x0 + 0x03a0 0xbf 0x0 + 0x03a4 0xa0 0x0 + 0x03a8 0x81 0x0 + 0x03ac 0xde 0x0 + 0x03b0 0x7f 0x0 + 0x0b64 0xcc 0x0 + 0x0b68 0x12 0x0 + 0x0b6c 0xcc 0x0 + 0x0b74 0x4a 0x0 + 0x0b78 0x29 0x0 + 0x0b7c 0xc5 0x0 + 0x0b80 0xac 0x0 + 0x0b84 0xb6 0x0 + 0x0b88 0xc0 0x0 + 0x0b8c 0x07 0x0 + 0x0b90 0xfb 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xc5 0x0 + 0x0b9c 0xee 0x0 + 0x0ba0 0xbf 0x0 + 0x0ba4 0xa0 0x0 + 0x0ba8 0x81 0x0 + 0x0bac 0xde 0x0 + 0x0bb0 0x7f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x37 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x37 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1c03000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c03000 0x1000>, + <0x3E28000 0x4>, + <0x3E28148 0x4>; + reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", + "ipa_uc_mbox_erdb"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-ipa-software-channel; + interrupts = <0 145 0>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x030817cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "disabled"; + }; + qcom,rmnet-ipa { compatible = "qcom,rmnet-ipa3"; qcom,rmnet-ipa-ssr; From bea76a2b861725afe6ee3973c89add43719d7edf Mon Sep 17 00:00:00 2001 From: Siddartha Mohanadoss Date: Tue, 24 Nov 2020 11:17:48 -0800 Subject: [PATCH 0407/1809] ARM: dts: msm: Enable PCIe EP on sdxlemur MBB Enable PCIe EP and MHI device for mobile broadband interface module platform. Change-Id: I01a753c204020b46ed6f27322728c40ccbb4d73d --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index e39236090d51..188a1bbe32c7 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,6 +1,41 @@ #include "sdxlemur-mtp.dtsi" +#include "sdxlemur.dtsi" &soc { }; +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; + +&mhi_device { + status = "ok"; +}; + +&mhi_net_device { + status = "ok"; +}; + +&ipa_hw { + qcom,use-ipa-in-mhi-mode; + ipa_smmu_ap { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_wlan { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_uc { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_11ad { + qcom,iommu-dma = "bypass"; + }; +}; From d038d835c325822f97841a078638d76e940ade73 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Tue, 1 Dec 2020 12:48:23 +0530 Subject: [PATCH 0408/1809] ARM: dts: msm: Increase max voltage of S11B regulator to 2.04V Increase max voltage of S11B regulator to 2.04V. Change-Id: I424ab87db26576dfae288b5fa0b30617d56f9db1 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 39225b49decd..f4298e8a7dac 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3535,7 +3535,7 @@ vdd-wlan-io-supply = <&S10B>; qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; vdd-wlan-rfa1-supply = <&S11B>; - qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1880000 2040000 0 0 1>; vdd-wlan-rfa2-supply = <&S12B>; qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; wlan-ant-switch-supply = <&L11C>; From 74a0510f4afc69d999b359e972021b46dffa7609 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 23 Nov 2020 15:16:14 +0530 Subject: [PATCH 0409/1809] ARM: dts: msm: Disable atmel_mxt_ts on shima Disable atmel maxTouch on shima platform. Change-Id: Ib9422dc1382657513f4f8809fda906ce0e7af859 --- qcom/shima-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 584af558244e..728936ec43b3 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -219,6 +219,7 @@ atmel,display-coords = <0 0 339 729>; panel = <&dsi_sharp_qhd_plus_dsc_cmd &dsi_sharp_qhd_plus_dsc_video>; + status = "disabled"; }; }; From af551eb2bc86de6d1ad35ecd802dd6bfca79b796 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 27 Nov 2020 20:58:09 +0800 Subject: [PATCH 0410/1809] ARM: dts: msm: Add clock support for uart driver Clock is available, so add the clock support for sdx12 uart driver. Change-Id: I7ed108a50075f24b647bf489e745b4076179a1bb --- qcom/sdxnightjar.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 622d46a7c381..d87e70d136b7 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -318,7 +318,8 @@ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; - /*TODO: Fix the clock when tree is available*/ + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; @@ -327,7 +328,8 @@ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; - /*TODO: Fix the clock when tree is available*/ + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; @@ -336,7 +338,8 @@ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b1000 0x200>; interrupts = <0 109 0>; - /*TODO: Fix the clock when tree is available*/ + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; From 82e16bca340778e06042af259d5ca1eafb9e1a67 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 2 Dec 2020 00:30:52 +0530 Subject: [PATCH 0411/1809] dt-bindings: Update bindings for guestvm-loader Update bindings for guestvm-loader with the new properties for CPU reservation. Change-Id: Ic3f0e9282524ecf9021ded582d67e80752156301 --- bindings/soc/qcom/qcom,guestvm-loader.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/bindings/soc/qcom/qcom,guestvm-loader.yaml b/bindings/soc/qcom/qcom,guestvm-loader.yaml index 10533eb7bb46..5c0f71be6b19 100644 --- a/bindings/soc/qcom/qcom,guestvm-loader.yaml +++ b/bindings/soc/qcom/qcom,guestvm-loader.yaml @@ -16,6 +16,13 @@ properties: image_to_be_loaded: $ref: /schemas/types.yaml#/definitions/string + qcom,reserved-cpus: + Value type: + Definition: should contain cpus reserved for guestvm + + qcom,unisolate-timeout-ms: + description: timeout, in ms, for unisolating reserved cpus. + required: - compatible - image_to_be_loaded @@ -25,5 +32,7 @@ examples: qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; -... \ No newline at end of file +... From 49ac72dafce321fbf2a172f48dfe864b28f75fa1 Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Tue, 1 Dec 2020 18:43:01 -0800 Subject: [PATCH 0412/1809] ARM: dts: msm: add new properties to guestvm node Add new properties to support cpu isolation and unisolation when the VM boot is start. Change-Id: I56a0a344230ef22e84a375431d0be2e0ed52a130 --- qcom/lahaina.dtsi | 2 ++ qcom/shima.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index d130a7c3b4c3..4817d6aa6c38 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5191,6 +5191,8 @@ qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; ssc_sensors: qcom,msm-ssc-sensors { diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 39225b49decd..bd70e14fe87f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1174,6 +1174,8 @@ qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; From 446c4e1999bc19d13a0cc49ce8706d1f75543dda Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Tue, 13 Oct 2020 11:21:30 +0530 Subject: [PATCH 0413/1809] ARM: dts: msm: Add SMMU device tree for Monaco Add SMMU device tree support for monaco target on rumi platform. Change-Id: Ie1f18d85864408e4e951777f318c4d530d32bb81 --- qcom/msm-arm-smmu-monaco.dtsi | 216 ++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 qcom/msm-arm-smmu-monaco.dtsi diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi new file mode 100644 index 000000000000..8e6cc4e08ab7 --- /dev/null +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -0,0 +1,216 @@ +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x59a0000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x59a0000 0x10000>, + <0x59da000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,no-dynamic-asid; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + #size-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* ALL CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x30B>; + + gfx_0_tbu: gfx_0_tbu@0x59c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x59dd000 0x1000>, + <0x59da200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + }; + }; + + apps_smmu: apps-smmu@0xc600000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc7f2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + + qcom,actlr = + /* For rt TBU +3 deep PF */ + <0x400 0x3ff 0x103>, + /* For nrt TBU +3 deep PF */ + <0x800 0x3ff 0x103>; + + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc7f5000 0x1000>, + <0xc7f2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc7f9000 0x1000>, + <0xc7f2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc7fd000 0x1000>, + <0xc7f2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + }; + + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x1E0 0x0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E1 0x0>; + dma-coherent; + }; +}; From 6b5fa4faad57f57811ad866566089018ccce494d Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 24 Nov 2020 12:54:47 +0530 Subject: [PATCH 0414/1809] ARM: dts: msm: Update tune params of HS PHY Update the tune params(USB_PHY_PARAMETER_OVERRIDE_X0, USB_PHY_PARAMETER_OVERRIDE_X1, USB_PHY_PARAMETER_OVERRIDE_X2) according to the latest HPG sequence for Shima and Lahaina. Change-Id: Ida54fb3f01f7abba564ed695ed279f8330e0d40c --- qcom/lahaina-usb.dtsi | 4 ++-- qcom/shima-usb.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 24ef02754f1e..2c9df5d05fe1 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -132,8 +132,8 @@ resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = - <0x63 0x6c /* override_x0 */ - 0xC8 0x70 /* override_x1 */ + <0xe6 0x6c /* override_x0 */ + 0x0b 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ }; diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi index 5e428a4a689c..bec66832b2c7 100644 --- a/qcom/shima-usb.dtsi +++ b/qcom/shima-usb.dtsi @@ -103,8 +103,8 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = - <0x63 0x6c /* override_x0 */ - 0xC8 0x70 /* override_x1 */ + <0xe6 0x6c /* override_x0 */ + 0x0b 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ }; From aec3e8e6c21d9c54fe8d8e4d98e3051043b6d7e4 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 2 Dec 2020 11:12:41 +0530 Subject: [PATCH 0415/1809] ARM: dts: msm: Update ion heap for monaco Update reg memory region reserved for the ion allocator. Change-Id: Ie2673baa41b8960953c5cf44caad2d8e946ff243 --- qcom/monaco-ion.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi index a0a50ce4dbd2..fe3f006d9574 100644 --- a/qcom/monaco-ion.dtsi +++ b/qcom/monaco-ion.dtsi @@ -5,12 +5,12 @@ #size-cells = <0>; system_heap: qcom,ion-heap@25 { - reg = <25>; - qcom,ion-heap-type = "SYSTEM"; + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; }; system_secure_heap: qcom,ion-heap@9 { - reg = <9>; + reg = ; qcom,ion-heap-type = "SYSTEM_SECURE"; }; }; From 2e2417d13eef3a3c72ab180451a7dd8f0c7e5db3 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 25 Nov 2020 11:51:42 +0530 Subject: [PATCH 0416/1809] ARM: dts: msm: Add support of clock AOP for YUPIK QDSS clocks uses the qmp mailbox phandle to register the clock. Thus add the phandle and also add support to send a request to AOP for stopping DDR logging during kernel panic. Change-Id: Ibb39536e6a75267ca28205bc4b3a16f64963493d --- qcom/yupik.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6fc836586383..ea7d228b9ee8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -570,10 +570,11 @@ }; aopcc: qcom,aopcc { - compatible = "qcom,dummycc"; - clock-output-names = "aopcc_clocks"; + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; #clock-cells = <1>; - #reset-cells = <1>; + qcom,clk-stop-bimc-log; }; gcc: clock-controller@100000 { From bea7a85c1ecf23e713d9ef0ff08948ee3e21f105 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 1 Dec 2020 12:51:31 +0530 Subject: [PATCH 0417/1809] ARM: dts: msm: Add support for TUI over SPI on LE VM Adds SPI DTSI node support to enable Trusted VM usecase for TUI. Change-Id: I0373601889bcd90f5c1c9a3cb2ce92cde8015f22 --- qcom/shima-qupv3.dtsi | 5 +++-- qcom/shima-vm.dtsi | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index a4c05936d55c..1b30f1c5ed89 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -59,6 +59,7 @@ qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; status = "ok"; }; @@ -197,8 +198,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se10_spi_active>; pinctrl-1 = <&qupv3_se10_spi_sleep>; - dmas = <&gpi_dma0 0 2 1 64 0>, - <&gpi_dma0 1 2 1 64 0>; + dmas = <&gpi_dma0 0 2 1 64 2>, + <&gpi_dma0 1 2 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_0>; diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 9a94097f5cc2..c29e3fe76683 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -246,6 +246,7 @@ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x9c0000 0x2000>; + status = "ok"; }; /* GPI Instance */ @@ -298,6 +299,23 @@ }; }; + /* SPI SE */ + qupv3_se10_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + reg-names = "se_phys"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + qcom,le-vm; + status = "disabled"; + }; + + }; #include "lahaina-vm-ion.dtsi" #include "display/trustedvm-shima-sde.dtsi" From d88aac062361aa1adb5460382a4a4b630a099429 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 23 Oct 2020 15:15:33 +0530 Subject: [PATCH 0418/1809] ARM: dts: msm: Add cpu7 qos latfloor device on shima Create a qos latfloor device on shima target to cover compute bound workloads running on cpu7 above 2.0 GHz. Change-Id: I4a437076d9dfb0217d6b957d010e142509641069 --- qcom/shima.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 39225b49decd..29160b4e1cc2 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2464,6 +2464,13 @@ mboxes = <&qmp_aop 0>; }; + cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor { + compatible = "qcom,devfreq-qoslat"; + governor = "mem_latency"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { qcom,core-dev-table = < 300000 300000000 >, @@ -2733,6 +2740,16 @@ < 300000 1 >, < 3000000 2 >; }; + + cpu7_qoslatmon: qcom,cpu7-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 2169600 1 >, + < 2707200 2 >; + }; }; qcom,sps { From 8b77828d559dbcc469187eaaef30f594547c3b2e Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Sat, 17 Oct 2020 23:07:39 +0530 Subject: [PATCH 0419/1809] ARM: dts: msm: Add L3 snoop bw device on Lahaina Create L3 devfreq device on Lahaina to scale L3 based on snoop bandwidth. Change-Id: I6ac8f482bde014989bb578e2f052b8d8c5f77aaa --- qcom/shima.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 29160b4e1cc2..82503e5d2631 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2303,6 +2303,28 @@ qcom,count-unit = <0x10000>; }; + snoop_l3_bw: qcom,snoop-l3-bw { + compatible = "qcom,devfreq-icc-l3bw"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + qcom,bus-width = <32>; + governor = "bw_hwmon"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + + snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b9100 0x300>, <0x90b9000 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&snoop_l3_bw>; + qcom,count-unit = <0x10000>; + }; + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { compatible = "qcom,devfreq-icc-l3"; reg = <0x18590100 0xa0>; From 0243614076350b7b5a65fbb7e479a205084828b0 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Sun, 22 Nov 2020 02:36:38 -0800 Subject: [PATCH 0420/1809] ARM: dts: msm: Add extcon node for sdxlemur platforms Enable cable detection on sdxlemur platforms having pdphy functionality. Change-Id: I50f11ddb6fc31c75a420f492f09e0996a2647613 --- qcom/sdxlemur-mtp-mbb.dtsi | 8 ++++++++ qcom/sdxlemur-rcm-rc.dtsi | 8 ++++++++ qcom/sdxlemur-usb.dtsi | 8 +++++--- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 834ad0b8e5de..678db43a2fa6 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -216,3 +216,11 @@ "typec_mode", "pe_start"; }; + +&usb { + extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index ed2936ca66c9..f5feac33e39d 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -184,3 +184,11 @@ "typec_mode", "pe_start"; }; + +&usb { + extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 007c96f3e20f..ab9674bd42fc 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -18,6 +18,7 @@ interrupt-names = "pwr_event_irq"; USB3_GDSC-supply = <&gcc_usb30_gdsc>; + dpdm-supply = <&usb2_phy>; clocks = <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, @@ -100,9 +101,10 @@ usb2_phy: hsphy@ff4000 { compatible = "qcom,usb-hsphy-snps-femto"; - reg = <0xff4000 0x120>; - reg-names = "hsusb_phy_base"; - + reg = <0xff4000 0x120>, + <0xff2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; vdd-supply = <&pmx65_l4>; qcom,vdd-voltage-level = <0 912000 912000>; vdda18-supply = <&pmx65_l5>; From 1195e31202212b81daa6f65fcaaecfe2105094cd Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 2 Dec 2020 10:52:09 -0800 Subject: [PATCH 0421/1809] ARM: dts: msm: Add ddr type to the subtype for sdxlemur Add ddr subtypes to the device trees for sdxlemur Change-Id: I44b4133fc03a927f24316cf5320b543471b6a0cd --- qcom/sdxlemur-cdp.dts | 2 +- qcom/sdxlemur-mtp-cpe.dts | 2 +- qcom/sdxlemur-mtp-mbb-emmc.dts | 2 +- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 2 +- qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 2 +- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 2 +- qcom/sdxlemur-mtp-mbb.dts | 2 +- qcom/sdxlemur-mtp.dts | 2 +- qcom/sdxlemur-rcm-pcie-ep.dts | 2 +- qcom/sdxlemur-rcm-rc.dts | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 68c99b5dd58d..32b5a27c0977 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", "qcom,sdxlemur", "qcom,cdp"; - qcom,board-id = <0x01 0>; + qcom,board-id = <0x01 0x300>; }; diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 0e48eebc0c2f..0ae7ce387e8f 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x6010008 0>; + qcom,board-id = <0x6010008 0x306>; }; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts index 734bb19c3f1b..1fcd14c01d1f 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -9,5 +9,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x2010108 0> + qcom,board-id = <0x2010108 0x302> }; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts index e8afacb3c415..0f207e33241f 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x5010008 0>; + qcom,board-id = <0x5010008 0x305>; }; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts index eb4521abbe69..5bfbf5417937 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x4010008 0>; + qcom,board-id = <0x4010008 0x304>; }; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts index ac65ac0913e2..10b2d8c0dbca 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x3010008 0>; + qcom,board-id = <0x3010008 0x303>; }; diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index bdcc2ce058b1..239e0bc30e0a 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -9,5 +9,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x2010008 0>; + qcom,board-id = <0x2010008 0x302>; }; diff --git a/qcom/sdxlemur-mtp.dts b/qcom/sdxlemur-mtp.dts index dfbdf23171f0..0483238314ac 100644 --- a/qcom/sdxlemur-mtp.dts +++ b/qcom/sdxlemur-mtp.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x08 0>; + qcom,board-id = <0x08 0x300>; }; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts index 43e60bca2eca..a43e055fbad9 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dts +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x1010015 0>; + qcom,board-id = <0x1010015 0x301>; }; diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index a5fd339b9fa4..95711468a255 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -9,5 +9,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x1010015 0>; + qcom,board-id = <0x1010015 0x301>; }; From 4c70eeaa5135bafe56a8d446e0b491297044d9d4 Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Wed, 2 Dec 2020 11:12:12 -0800 Subject: [PATCH 0422/1809] ARM: dts: msm: Add support for Lahaina HSP Pro Add device-tree support for Lahaina HSP Pro platform. Change-Id: I804ddde4f54f365e542648baa6b30ed682ff0dc9 --- qcom/Makefile | 16 ++++++++++++++-- qcom/lahaina-cdp-hsp-pro-overlay.dts | 10 ++++++++++ qcom/lahaina-cdp-hsp-pro.dtsi | 1 + qcom/lahaina-mtp-hsp-pro-overlay.dts | 10 ++++++++++ qcom/lahaina-mtp-hsp-pro.dtsi | 1 + qcom/lahaina-qrd-hsp-pro-overlay.dts | 10 ++++++++++ qcom/lahaina-qrd-hsp-pro.dtsi | 1 + qcom/lahaina-v2.1-cdp-hsp-pro.dts | 10 ++++++++++ qcom/lahaina-v2.1-mtp-hsp-pro.dts | 10 ++++++++++ qcom/lahaina-v2.1-qrd-hsp-pro.dts | 10 ++++++++++ 10 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 qcom/lahaina-cdp-hsp-pro-overlay.dts create mode 100644 qcom/lahaina-cdp-hsp-pro.dtsi create mode 100644 qcom/lahaina-mtp-hsp-pro-overlay.dts create mode 100644 qcom/lahaina-mtp-hsp-pro.dtsi create mode 100644 qcom/lahaina-qrd-hsp-pro-overlay.dts create mode 100644 qcom/lahaina-qrd-hsp-pro.dtsi create mode 100644 qcom/lahaina-v2.1-cdp-hsp-pro.dts create mode 100644 qcom/lahaina-v2.1-mtp-hsp-pro.dts create mode 100644 qcom/lahaina-v2.1-qrd-hsp-pro.dts diff --git a/qcom/Makefile b/qcom/Makefile index ab69f402e2f2..9bd5a994973b 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -15,7 +15,10 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \ lahainap-qrd-overlay.dtbo \ lahaina-cdp-v2.2-overlay.dtbo \ lahaina-mtp-v2-overlay.dtbo \ - lahaina-mtp-v2.1-overlay.dtbo + lahaina-mtp-v2.1-overlay.dtbo \ + lahaina-mtp-hsp-pro-overlay.dtbo \ + lahaina-cdp-hsp-pro-overlay.dtbo \ + lahaina-qrd-hsp-pro-overlay.dtbo lahaina-rumi-overlay.dtbo-base := lahaina.dtb lahaina-mtp-hsp-overlay.dtbo-base := lahaina.dtb @@ -36,6 +39,12 @@ lahaina-mtp-v2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ lahaina-v2.1.dtb lahaina-mtp-v2.1-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ lahaina-v2.1.dtb +lahaina-mtp-hsp-pro-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ + lahaina-v2.1.dtb +lahaina-cdp-hsp-pro-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ + lahaina-v2.1.dtb +lahaina-qrd-hsp-pro-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ + lahaina-v2.1.dtb else dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-mtp-hsp.dtb \ @@ -72,7 +81,10 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahainap-v2.1-atp.dtb \ lahainap-v2.1-qrd.dtb \ lahaina-mtp-v2.dtb \ - lahaina-mtp-v2.1.dtb + lahaina-mtp-v2.1.dtb \ + lahaina-v2.1-mtp-hsp-pro.dts \ + lahaina-v2.1-cdp-hsp-pro.dts \ + lahaina-v2.1-qrd-hsp-pro.dts endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/lahaina-cdp-hsp-pro-overlay.dts b/qcom/lahaina-cdp-hsp-pro-overlay.dts new file mode 100644 index 000000000000..01492bcb2c02 --- /dev/null +++ b/qcom/lahaina-cdp-hsp-pro-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-cdp-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina CDP-HSP-PRO"; + compatible = "qcom,lahaina-cdp", "qcom,lahaina", "qcom,cdp"; + qcom,board-id = <0x3010001 0>; +}; diff --git a/qcom/lahaina-cdp-hsp-pro.dtsi b/qcom/lahaina-cdp-hsp-pro.dtsi new file mode 100644 index 000000000000..fdf9ed586642 --- /dev/null +++ b/qcom/lahaina-cdp-hsp-pro.dtsi @@ -0,0 +1 @@ +#include "lahaina-cdp.dtsi" diff --git a/qcom/lahaina-mtp-hsp-pro-overlay.dts b/qcom/lahaina-mtp-hsp-pro-overlay.dts new file mode 100644 index 000000000000..f7a785252a74 --- /dev/null +++ b/qcom/lahaina-mtp-hsp-pro-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-mtp-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina MTP-HSP-PRO"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x2010008 0>; +}; diff --git a/qcom/lahaina-mtp-hsp-pro.dtsi b/qcom/lahaina-mtp-hsp-pro.dtsi new file mode 100644 index 000000000000..af2a598d00ab --- /dev/null +++ b/qcom/lahaina-mtp-hsp-pro.dtsi @@ -0,0 +1 @@ +#include "lahaina-mtp.dtsi" diff --git a/qcom/lahaina-qrd-hsp-pro-overlay.dts b/qcom/lahaina-qrd-hsp-pro-overlay.dts new file mode 100644 index 000000000000..27879c707b1a --- /dev/null +++ b/qcom/lahaina-qrd-hsp-pro-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-qrd-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina QRD-HSP-PRO"; + compatible = "qcom,lahaina-qrd", "qcom,lahaina", "qcom,qrd"; + qcom,board-id = <0x201000B 0>; +}; diff --git a/qcom/lahaina-qrd-hsp-pro.dtsi b/qcom/lahaina-qrd-hsp-pro.dtsi new file mode 100644 index 000000000000..74843fc49873 --- /dev/null +++ b/qcom/lahaina-qrd-hsp-pro.dtsi @@ -0,0 +1 @@ +#include "lahaina-qrd.dtsi" diff --git a/qcom/lahaina-v2.1-cdp-hsp-pro.dts b/qcom/lahaina-v2.1-cdp-hsp-pro.dts new file mode 100644 index 000000000000..f4591cb558f2 --- /dev/null +++ b/qcom/lahaina-v2.1-cdp-hsp-pro.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-v2.1.dtsi" +#include "lahaina-cdp-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina CDP-HSP-PRO"; + compatible = "qcom,lahaina-cdp", "qcom,lahaina", "qcom,cdp"; + qcom,board-id = <0x3010001 0>; +}; diff --git a/qcom/lahaina-v2.1-mtp-hsp-pro.dts b/qcom/lahaina-v2.1-mtp-hsp-pro.dts new file mode 100644 index 000000000000..cad03d7fa86a --- /dev/null +++ b/qcom/lahaina-v2.1-mtp-hsp-pro.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-v2.1.dtsi" +#include "lahaina-mtp-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina MTP-HSP-PRO"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x2010008 0>; +}; diff --git a/qcom/lahaina-v2.1-qrd-hsp-pro.dts b/qcom/lahaina-v2.1-qrd-hsp-pro.dts new file mode 100644 index 000000000000..c7dfd067c5b8 --- /dev/null +++ b/qcom/lahaina-v2.1-qrd-hsp-pro.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-v2.1.dtsi" +#include "lahaina-qrd-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina QRD-HSP-PRO"; + compatible = "qcom,lahaina-qrd", "qcom,lahaina", "qcom,qrd"; + qcom,board-id = <0x201000B 0>; +}; From 8e88c87c02a8ce33c0ddcfca8d2f8cc43f5e04ef Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Wed, 2 Dec 2020 10:40:40 +0800 Subject: [PATCH 0423/1809] ARM: dts: msm: increase vddio voltage for hdk r66451 dsi panel Set vddio voltage to 1.86v for hdk, since some of hdk dsi panel's vddio voltage has a larger drop, they could not work well on 1.8v. Change-Id: Id7dde6d1ffee9cab853b23b05c1c345e829aea87 --- qcom/lahaina-hdk.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 6af3c39a4c7a..687b8501a061 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -190,3 +190,10 @@ qcom,ep-gpio = <&tlmm 6 0>; qcom,boot-option = <0x0>; }; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; From 97a2ef3ab012a55d1137e41fb9717ef600ca9cf3 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 6 Oct 2020 20:01:07 +0530 Subject: [PATCH 0424/1809] ARM: dts: msm: Add PMIC support for yupik Add an SPMI PMIC arbiter device to communicate with PMICs attached to the SPMI bus. Add an SPMI debug bus device and associated child devices. Add PMIC Glink device and their client devices. Add top level SPMI slave devices for PM7325 and PM7325B PMICs. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: I9ffaceb1a41560ab35e1d54ed53a345aa7872a5b --- qcom/pm7325.dtsi | 61 ++++++++++ qcom/pm7325b.dtsi | 68 +++++++++++ qcom/yupik-pmic-overlay.dtsi | 218 +++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 154 +++++++++++++++++++++++++ 4 files changed, 501 insertions(+) create mode 100644 qcom/pm7325.dtsi create mode 100644 qcom/pm7325b.dtsi create mode 100644 qcom/yupik-pmic-overlay.dtsi diff --git a/qcom/pm7325.dtsi b/qcom/pm7325.dtsi new file mode 100644 index 000000000000..ddfdde1f358e --- /dev/null +++ b/qcom/pm7325.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm7325@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7325_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7325_gpios: pinctrl@8800 { + compatible = "qcom,pm7325-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm7325_temp_alarm: pm7325_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325_tz>; + + trips { + pm7325_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7325_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pm7325_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pm7325b.dtsi b/qcom/pm7325b.dtsi new file mode 100644 index 000000000000..0ca5f7732a39 --- /dev/null +++ b/qcom/pm7325b.dtsi @@ -0,0 +1,68 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm7325b@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7325b_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7325b_gpios: pinctrl@8800 { + compatible = "qcom,pm7325b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7250b_vib: qcom,vibrator@df00 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0xdf00>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + }; +}; + +&thermal_zones { + pm7325b_temp_alarm: pm7325b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_tz>; + + trips { + pm7325b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7325b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pm7325b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi new file mode 100644 index 000000000000..b47e3d16e5e1 --- /dev/null +++ b/qcom/yupik-pmic-overlay.dtsi @@ -0,0 +1,218 @@ +#include +#include + +#include "pmk8350.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmr735a.dtsi" + +&pm7325_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; + +&pmk8350_vadc { + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + /* PM7325 Channel nodes */ + pm7325_ref_gnd { + reg = ; + label = "pm7325_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm7325_vref_1p25 { + reg = ; + label = "pm7325_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm7325_die_temp { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm7325_vph_pwr { + reg = ; + label = "pm7325_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm7325_quiet_therm { + reg = ; + label = "pm7325_quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7325_cam_flash_therm { + reg = ; + label = "pm7325_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7325_sdm_skin_therm { + reg = ; + label = "pm7325_sdm_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7325_wide_rfc_therm { + reg = ; + label = "pm7325_wide_rfc_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + + pm7325_quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7325_cam_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7325_sdm_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7325_wide_rfc_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmk8350_xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-cam-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7325_tz { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmr735a_tz { + io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 4050cb4d5098..48ee2e97ae98 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -919,6 +920,149 @@ ; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + spmi_debug_bus: qcom,spmi-debug@6b12000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b12000 0x60>, <0x7820b0 0x4>; + reg-names = "core", "fuse"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + status = "disabled"; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7325-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8350c-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8350b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmr735a-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + qcom,pmic_glink { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "adsp"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8350b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + qcom,can-sleep; + }; + }; + + /* Secondary (QUP) SPMI bus */ + spmi@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,smb1394-debug@b { + compatible = "qcom,spmi-pmic"; + reg = <11 SPMI_USID>; + qcom,can-sleep; + }; + + qcom,smb1394-debug@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + qcom,can-sleep; + }; + + }; + }; + }; + + thermal_zones: thermal-zones { + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; @@ -1097,6 +1241,16 @@ <&glink_cdsp>, <&glink_wpss>; }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3>; + }; }; glink_cdsp: cdsp { From c00540a303779576ddb65e95c27fdebc1085c83c Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 11 Nov 2020 15:56:06 +0530 Subject: [PATCH 0425/1809] ARM: dts: msm: Add PM8008 support for yupik Add support for managing the PM8008I and PM8008J chips via I2C. This ensures that consumers are able to modify the physical state of these PMIC regulators. Change-Id: I390c8d41f950148e4532e614f0ddcf98effebb22 --- qcom/yupik-pmic-overlay.dtsi | 232 +++++++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index b47e3d16e5e1..e15564e25061 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -18,6 +18,28 @@ }; }; +&pm8350c_gpios { + pm8008i_reset { + pm8008i_active: pm8008i_active { + pins = "gpio3"; + function = "normal"; + bias-disable; + output-high; + power-source = <1>; + }; + }; + + pm8008j_reset { + pm8008j_active: pm8008j_active { + pins = "gpio4"; + function = "normal"; + bias-disable; + output-high; + power-source = <1>; + }; + }; +}; + &pmk8350_vadc { /delete-node/ pm8350_ref_gnd; /delete-node/ pm8350_vref_1p25; @@ -207,6 +229,216 @@ }; }; +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8008i_chip: pm8008i@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008i_active>; + + pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008I_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008i-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + }; + + pm8008i_ldo: pm8008i@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8008i-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8008I_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&BOB>; + vdd_l5-supply = <&S1B>; + vdd_l6-supply = <&BOB>; + vdd_l7-supply = <&BOB>; + + L1I: pm8008i_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8008i_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <160000>; + qcom,hpm-min-load = <30000>; + }; + + L2I: pm8008i_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8008i_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <30000>; + }; + + L3I: pm8008i_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8008i_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <144000>; + }; + + L4I: pm8008i_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8008i_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + }; + + L5I: pm8008i_l5: regulator@4400 { + reg = <0x4400>; + regulator-name = "pm8008i_l5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,min-dropout-voltage = <136000>; + }; + + L6I: pm8008i_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8008i_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + }; + + L7I: pm8008i_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8008i_l7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <312000>; + }; + }; + }; + + pm8008j_chip: pm8008j@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008j_active>; + + pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008J_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008j-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + }; + + pm8008j_ldo: pm8008j@d { + compatible = "qcom,i2c-pmic"; + reg = <0xd>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8008j-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8008J_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&S1B>; + vdd_l5-supply = <&BOB>; + vdd_l6-supply = <&BOB>; + vdd_l7-supply = <&BOB>; + + L1J: pm8008j_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8008j_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <96000>; + qcom,hpm-min-load = <30000>; + }; + + L2J: pm8008j_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8008j_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1250000>; + qcom,min-dropout-voltage = <24000>; + qcom,hpm-min-load = <30000>; + }; + + L3J: pm8008j_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8008j_l3"; + regulator-min-microvolt = <1460000>; + regulator-max-microvolt = <1800000>; + qcom,min-dropout-voltage = <224000>; + }; + + L4J: pm8008j_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8008j_l4"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1600000>; + qcom,min-dropout-voltage = <0>; + }; + + L5J: pm8008j_l5: regulator@4400 { + reg = <0x4400>; + regulator-name = "pm8008j_l5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <104000>; + }; + + L6J: pm8008j_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8008j_l6"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,min-dropout-voltage = <112000>; + }; + + L7J: pm8008j_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8008j_l7"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + qcom,min-dropout-voltage = <96000>; + }; + }; + }; +}; + &pm7325_tz { io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; io-channel-names = "thermal"; From 52a2b16c6ed6f677c116895dfba0a8ba5eef8ac2 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 5 Nov 2020 18:03:44 +0530 Subject: [PATCH 0426/1809] dt-bindings: pinctrl: qcom-pmic-gpio: add PM7325 and PM7325B bindings Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible strings for PM7325 and PM7325B PMICs. Change-Id: Ie9d7f653d2d73691e7d7040bd6fcfb17b6753cb7 --- bindings/pinctrl/qcom,pmic-gpio.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index 84611b5347f5..a8784580baa9 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -34,6 +34,8 @@ PMIC's from Qualcomm. "qcom,pm6150l-gpio" "qcom,pmx65-gpio" "qcom,pmd9650-gpio" + "qcom,pm7325-gpio" + "qcom,pm7325b-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -122,6 +124,8 @@ to specify in a pin configuration subnode: gpio1-gpio12 for pm6150l gpio1-gpio16 for pmx65 gpio1-gpio12 for pmd9650 + gpio1-gpio10 for pm7325 + gpio1-gpio8 for pm7325b - function: Usage: required From 3aec0f023763445282560dc077de209ec3d2a533 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Thu, 19 Nov 2020 16:39:29 +0530 Subject: [PATCH 0427/1809] ARM: dts: msm: Add PMIC support for monaco Add an SPMI arbiter device to communicate with PMICs attached to the SPMI bus. Add top level SPMI slave device for pm5100 and also some of the peripheral devices within the SPMI slave. Change-Id: Ifd73a8fc3418911c85343c2201a6e36c7915e72c --- qcom/monaco.dtsi | 19 ++++++++++++++++ qcom/pm5100.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 qcom/pm5100.dtsi diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f15bcb2b78b3..27dbb3c6e971 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -535,6 +535,25 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; }; #include "monaco-pinctrl.dtsi" diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi new file mode 100644 index 000000000000..8a163724775f --- /dev/null +++ b/qcom/pm5100.dtsi @@ -0,0 +1,56 @@ +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm5100@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon_hlos@1300 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1300>; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; + }; + + pm5100_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm5100_gpios: pinctrl@8800 { + compatible = "qcom,pm5100-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm5100_rtc: qcom,pm5100_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>; + }; + }; +}; From be01a670a8bdb87783579266f79181bcb7fbfb58 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Thu, 5 Nov 2020 14:29:24 +0530 Subject: [PATCH 0428/1809] ARM: dts: msm: add interconnect paths for smmu Add interconnect paths for SMMU which is used for bandwidth voting. Change-Id: I1a1a344715a2746034b9c7d7e4aea554959ccc09 --- qcom/msm-arm-smmu-yupik.dtsi | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index 06c00b29cadf..a35d60de4a3c 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -33,6 +33,8 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + interrupts = , , , @@ -159,12 +161,19 @@ , ; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; + anoc_1_tbu: anoc_1_tbu@151dd000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151dd000 0x1000>, <0x151da200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; }; anoc_2_tbu: anoc_2_tbu@151e1000 { @@ -173,6 +182,9 @@ <0x151da208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; }; mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 { @@ -181,6 +193,11 @@ <0x151da210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + interconnects = <&mmss_noc MASTER_MDP0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; }; mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 { @@ -189,6 +206,11 @@ <0x151da218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + interconnects = <&mmss_noc MASTER_MDP0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; }; compute_dsp_1_tbu: compute_dsp_1_tbu@151ed000 { @@ -197,6 +219,11 @@ <0x151da220 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; }; compute_dsp_0_tbu: compute_dsp_0_tbu@151f1000 { @@ -205,6 +232,11 @@ <0x151da228 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; }; adsp_tbu: adsp_tbu@151f5000 { @@ -213,6 +245,9 @@ <0x151da230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &lpass_ag_noc SLAVE_LPASS_CORE_CFG>; + qcom,active-only; }; anoc_1_pcie_tbu: anoc_1_pcie_tbu@151f9000 { @@ -221,6 +256,9 @@ <0x151da238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; }; mnoc_sf_0_tbu: mnoc_sf_0_tbu@151fd000 { @@ -229,6 +267,11 @@ <0x151da240 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; }; }; From e30008504abf81f69698301d86022ca03f292d3d Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Thu, 3 Dec 2020 21:52:05 +0530 Subject: [PATCH 0429/1809] ARM: dts: msm: Update spmi_bus configuration for sdxnightjar Update spmi_bus channel configuration for sdxnightjar for spmi_pmic_arbiter. Change-Id: I9fbf0fce986641c1a2921f71abac5ac236b8aa4a --- qcom/sdxnightjar.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index d87e70d136b7..91e394489bae 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -417,13 +417,13 @@ <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupts = <0 190 0>; - qcom,pmic-arb-channel = <0>; - qcom,pmic-arb-ee = <0>; + qcom,channel = <0>; + qcom,ee = <0>; qcom,pmic-arb-max-peripherals = <256>; qcom,pmic-arb-max-periph-interrupts = <256>; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; - #address-cells = <1>; + #address-cells = <2>; #size-cells = <0>; cell-index = <0>; }; From 9f4d962011c066716f0447fd14610fc1abf40825 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 1 Dec 2020 13:05:49 -0800 Subject: [PATCH 0430/1809] ARM: dts: msm: Added warm reset for sdxlemur pcie devices Added support for warm reset for sdxlemur pcie devices Change-Id: Iae71d19a14fc9232e238bedc4a3c69a0b1ef0df2 --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 4 ++++ qcom/sdxlemur.dtsi | 6 +++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 188a1bbe32c7..4b0b1069ad6f 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -5,6 +5,10 @@ }; +&chosen { + bootargs = "reboot=w"; +}; + &pcie0 { status = "disabled"; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7ade3cdbd9a3..9f339bf1985d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -24,7 +24,7 @@ pci-domain0 = &pcie0; /* PCIe0 domain */ }; - chosen { }; + chosen: chosen { }; memory { device_type = "memory"; reg = <0 0>; }; @@ -88,6 +88,10 @@ }; }; +&chosen { + +}; + &soc { #address-cells = <1>; #size-cells = <1>; From 19094a2b6eca8fdb878ac81129659d047af4f0fc Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Mon, 21 Sep 2020 18:36:29 +0530 Subject: [PATCH 0431/1809] ARM: dts: msm: Add rmtfs_sharedmem support for yupik Add shared memory support to enable the rmt_storage service in userspace that allows other processor to access the primary storage device to store its data. Change-Id: Idc238177059b9c7d5b6eda5be40219fa015a1950 --- qcom/yupik.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bdcc5baf0904..50cf33c2a8e2 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1400,6 +1400,14 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; }; #include "shima-gdsc.dtsi" From afad1f578d6245919a38879b93efde7f366c87e7 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Mon, 12 Oct 2020 11:45:28 +0530 Subject: [PATCH 0432/1809] ARM: dts: msm: Add secondary controller USB nodes for Yupik Add secondary controller nodes to support usb on peripheral mode for Yupik. Change-Id: Ic8a80b80e7b733f41dec5ced52978060777d7504 --- qcom/yupik-rumi.dtsi | 25 ++++++++++++++++++ qcom/yupik-usb.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 87 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 33c0546db1eb..214eb9eb7441 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -28,6 +28,21 @@ 0x0 0x4>; }; + usb_emu_phy_1: usb_emu_phy@8c0e000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x08c0e000 0x9500>; + + qcom,emu-init-seq = <0xffff 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + bi_tcxo: bi_tcxo { compatible = "fixed-factor-clock"; clock-mult = <1>; @@ -43,6 +58,7 @@ clocks = <&xo_board>; #clock-cells = <0>; }; + }; &usb0 { @@ -54,6 +70,15 @@ }; }; +&usb1 { + /delete-property/ extcon; + dwc3@8c00000 { + usb-phy = <&usb_emu_phy_1>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; + &sdhc_1 { status = "disabled"; diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 0d8f7d16b223..829de6693452 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -45,7 +45,7 @@ dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xcd00>; + reg = <0xa600000 0xe000>; interrupts = ; linux,sysdev_is_parent; snps,disable-clk-gating; @@ -62,6 +62,67 @@ }; }; + usb1: hsusb@8c00000 { + status = "disabled"; + compatible = "qcom,dwc-usb3-msm"; + reg = <0x8c00000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk","bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + dwc3@8c00000 { + compatible = "snps,dwc3"; + reg = <0x8c00000 0xe000>; + interrupts = ; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; From 4561f0f716a34b0f748cee362a529d016f4e892c Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Mon, 7 Dec 2020 14:53:46 +0530 Subject: [PATCH 0433/1809] ARM: dts: msm: Configure I2C pinctrl setting as per codec requirement Configure I2C pinctrl settings as per audio codec requirement. Change-Id: I86c85b37f5b8d36d4922a998aa483df55dac52c8 --- qcom/sdxlemur-pinctrl.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index bf46e4507e98..9e46bae72197 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -318,20 +318,20 @@ config { pins = "gpio10", "gpio11"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; }; i2c_3_sleep: i2c_3_sleep { mux { pins = "gpio10", "gpio11"; - function = "gpio"; + function = "blsp_i2c3"; }; config { pins = "gpio10", "gpio11"; drive-strength = <2>; - bias-disable; + bias-pull-up; }; }; }; From 9a91c60e1bc482afdab7a582dcb09cff522a9e1c Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Mon, 7 Dec 2020 16:03:45 +0530 Subject: [PATCH 0434/1809] bindings: mproc: add smdpkt.txt Update bindings for smd pkt driver Change-Id: I9138949fb85fdd559dc776066f45f7c5fd5a26d6 --- bindings/arm/msm/smdpkt.txt | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/arm/msm/smdpkt.txt diff --git a/bindings/arm/msm/smdpkt.txt b/bindings/arm/msm/smdpkt.txt new file mode 100644 index 000000000000..684088828364 --- /dev/null +++ b/bindings/arm/msm/smdpkt.txt @@ -0,0 +1,42 @@ +Qualcomm Technologies, Inc. Shared Memory Packet Driver (smdpkt) + +[Root level node] +Required properties: +-compatible : should be "qcom,smdpkt" + +[Second level nodes] +qcom,smdpkt-port-names +Required properties: +-qcom,smdpkt-remote : the remote subsystem name +-qcom,smdpkt-port-name : the smd channel name +-qcom,smdpkt-dev-name : the smdpkt device name + +Example: + + qcom,smdpkt { + compatible = "qcom,smdpkt"; + + qcom,smdpkt-data5-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-dev-name = "smdcntl0"; + }; + + qcom,smdpkt-data6-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA6_CNTL"; + qcom,smdpkt-dev-name = "smdcntl1"; + }; + + qcom,smdpkt-cxm-qmi-port-8064 { + qcom,smdpkt-remote = "wcnss"; + qcom,smdpkt-port-name = "CXM_QMI_PORT_8064"; + qcom,smdpkt-dev-name = "smd_cxm_qmi"; + }; + + qcom,smdpkt-loopback { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "LOOPBACK"; + qcom,smdpkt-dev-name = "smd_pkt_loopback"; + }; + }; From 9222fd809b7d27dcd1111afdaf8fc9d402cead98 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 7 Dec 2020 10:43:19 -0800 Subject: [PATCH 0435/1809] ARM: dts: msm: Add a 5C hysteresis for DDR rule in Lahaina Add a 5C hysteresis for DDR temperature monitoring in Lahaina. This will ensure that the mitigation is held for a while before it is relaxed. Change-Id: Ie54f2c03bacd76c85c127029439f12d6b0061dbf --- qcom/lahaina-thermal.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index fb753c87f2dd..1c421644fc51 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -774,6 +774,12 @@ hysteresis = <0>; type = "passive"; }; + + pop_trip1: pop-trip1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { @@ -785,7 +791,7 @@ }; pop_cdev1 { - trip = <&pop_trip>; + trip = <&pop_trip1>; cooling-device = <&ddr_cdev 5 5>; }; }; From db4a7ceebb05bb7bebde6661514238346978da55 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 22 Nov 2020 20:02:25 +0530 Subject: [PATCH 0436/1809] ARM: dts: msm: Enable NAND and SD card for sdxnightjar Enable NAND and SD card for sdxnightjar. Change-Id: I7381fc7bbfa2c086bdd62593e28362d9e0a97bef --- qcom/sdxnightjar-cdp.dtsi | 19 ++++++++++ qcom/sdxnightjar-mtp.dtsi | 19 ++++++++++ qcom/sdxnightjar-pinctrl.dtsi | 40 +++++++++++++++++++++ qcom/sdxnightjar-qrd.dtsi | 19 ++++++++++ qcom/sdxnightjar.dtsi | 68 +++++++++++++++++++++++++++++++++++ 5 files changed, 165 insertions(+) diff --git a/qcom/sdxnightjar-cdp.dtsi b/qcom/sdxnightjar-cdp.dtsi index 084e2aec6ca1..4aea425b73a3 100644 --- a/qcom/sdxnightjar-cdp.dtsi +++ b/qcom/sdxnightjar-cdp.dtsi @@ -4,3 +4,22 @@ pinctrl-0 = <&uart3_console_active>; }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&sdc_vreg>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pmd9650_l7>; + qcom,vdd-io-voltage-level = <1800000 2848000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + status = "ok"; +}; diff --git a/qcom/sdxnightjar-mtp.dtsi b/qcom/sdxnightjar-mtp.dtsi index 084e2aec6ca1..4aea425b73a3 100644 --- a/qcom/sdxnightjar-mtp.dtsi +++ b/qcom/sdxnightjar-mtp.dtsi @@ -4,3 +4,22 @@ pinctrl-0 = <&uart3_console_active>; }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&sdc_vreg>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pmd9650_l7>; + qcom,vdd-io-voltage-level = <1800000 2848000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + status = "ok"; +}; diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index fe045ec0167e..31438ed9f00b 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -401,6 +401,46 @@ }; }; + sdc2_on: sdc2_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + /* SMB CONFIGURATION */ pmx_smb_stat { smb_stat_active: smb_stat_active { diff --git a/qcom/sdxnightjar-qrd.dtsi b/qcom/sdxnightjar-qrd.dtsi index 084e2aec6ca1..4aea425b73a3 100644 --- a/qcom/sdxnightjar-qrd.dtsi +++ b/qcom/sdxnightjar-qrd.dtsi @@ -4,3 +4,22 @@ pinctrl-0 = <&uart3_console_active>; }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&sdc_vreg>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pmd9650_l7>; + qcom,vdd-io-voltage-level = <1800000 2848000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + status = "ok"; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 2d345ee2c865..1351851d849f 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -542,6 +542,74 @@ }; }; + qnand_1: nand@7980000 { + compatible = "qcom,msm-nand"; + reg = <0x07980000 0x1000>, + <0x07984000 0x1a000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = ; + interrupt-names = "bam_irq"; + + clock-names = "core_clk"; + clocks = <&rpmcc RPM_SMD_QPIC_CLK>; + + interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 400000>; + + status = "disabled"; + }; + + sdhc_1: sdhci@7824000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, <0x07824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "sdhc-ddr"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */ + <1600 3200>, /* 400 KB/s*/ + <100000 200000>, /* 25 MB/s */ + <200000 400000>, /* 50 MB/s */ + <400000 800000>, /* 100 MB/s */ + <400000 800000>, /* 200 MB/s */ + <2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + + status = "disabled"; + + qos0 { + mask = <0x1>; + vote = <70>; + }; + }; + spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, From 615c78a87ad1494e7a7ba57021be428468a8955d Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 28 Sep 2020 10:28:40 +0530 Subject: [PATCH 0437/1809] bindings: clock: Add clock controller bindings for SDXNIGHTJAR Add gcc, debugcc and rpmcc clock controller bindings to support SDXNIGHTJAR. Change-Id: I6574b444221da5bbb7448ae4222d81e1695cb816 --- bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,rpmcc.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 59290aa6d1a4..b6356b499bcb 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -10,6 +10,7 @@ Required properties : "qcom,sdxlemur-debugcc" "qcom,sm8150-debugcc" "qcom,yupik-debugcc" + "qcom,sdxnightjar-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index c15e9b6800b7..5c131248c402 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -32,6 +32,7 @@ Required properties : "qcom,holi-gcc" "qcom,sdxlemur-gcc" "qcom,yupik-gcc" + "qcom,sdxnightjar-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index 3d073dd00e36..dc0e0c697bdc 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -19,6 +19,7 @@ Required properties : "qcom,rpmcc-msm8998", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" "qcom,rpmcc-holi", "qcom,rpmcc" + "qcom,rpmcc-sdxnightjar", "qcom,rpmcc" - #clock-cells : shall contain 1 From d221be90771d2fd4e6381607014677a3d04f0b0c Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Tue, 24 Nov 2020 21:29:23 +0530 Subject: [PATCH 0438/1809] ARM: dts: qcom: Add dtsi node entry for Slimbus in yupik Add Slimbus dtsi node entry for yupik. Change-Id: If899283dbbb0c21b667f8540a4073f8a3cf1246a --- qcom/yupik.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 59808e07e047..60a82f55eaf0 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -371,6 +371,24 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + slim_aud: slim@3ac0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x3ac0000 0x2c000>, + <0x3a84000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x3e0>; + iommus = <&apps_smmu 0x1826 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From cdc551c5eebd0c854cd4ed8358821efd1af18318 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 8 Dec 2020 19:10:44 +0800 Subject: [PATCH 0439/1809] ARM: dts: msm: Add initial device tree for Yupik for QRD Add initial device tree to support Yupik QRD platforms. Change-Id: I3646f0964832735ac8a21bfa09d3101d11420f4d --- bindings/arm/msm/msm.txt | 1 + qcom/Makefile | 3 +++ qcom/yupik-qrd-overlay.dts | 11 +++++++++++ qcom/yupik-qrd.dts | 10 ++++++++++ qcom/yupik-qrd.dtsi | 2 ++ 5 files changed, 27 insertions(+) create mode 100644 qcom/yupik-qrd-overlay.dts create mode 100644 qcom/yupik-qrd.dts create mode 100644 qcom/yupik-qrd.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index c529b3464dc0..5274f24ffb56 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -224,6 +224,7 @@ compatible = "qcom,shima-qrd" compatible = "qcom,yupik-rumi" compatible = "qcom,yupik-idp" compatible = "qcom,yupik-atp" +compatible = "qcom,yupik-qrd" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index 793a51038a7f..543aa180dcd1 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -139,16 +139,19 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-rumi-overlay.dtbo \ yupik-idp-overlay.dtbo \ yupik-atp-overlay.dtbo \ + yupik-qrd-overlay.dtbo \ yupik-idps-digital-mics-overlay.dtbo yupik-rumi-overlay.dtbo-base := yupik.dtb yupik-idp-overlay.dtbo-base := yupik.dtb yupik-atp-overlay.dtbo-base := yupik.dtb +yupik-qrd-overlay.dtbo-base := yupik.dtb yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ yupik-atp.dtb \ + yupik-qrd.dtb \ yupik-idps-digital-mics.dtb endif diff --git a/qcom/yupik-qrd-overlay.dts b/qcom/yupik-qrd-overlay.dts new file mode 100644 index 000000000000..34be33030649 --- /dev/null +++ b/qcom/yupik-qrd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik QRD"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,qrd"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupik-qrd.dts b/qcom/yupik-qrd.dts new file mode 100644 index 000000000000..81d265719335 --- /dev/null +++ b/qcom/yupik-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik QRD"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-qrd.dtsi @@ -0,0 +1,2 @@ +&soc { +}; From 8d175b1670b2c10388c7c0b2ccb98460eda990b4 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 8 Dec 2020 11:35:52 -0800 Subject: [PATCH 0440/1809] ARM: dts: msm: Add label for llcc Added a label for the llcc node. Change-Id: If7377a7e19f124ba95ada27f3435be3032aed9a8 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 279d02c7ca5e..58b803b24a0e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -593,7 +593,7 @@ reg = <0x1fc0000 0x30000>; }; - cache-controller@9200000 { + llcc: cache-controller@9200000 { compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2"; reg = <0x9200000 0x50000>; reg-names = "llcc_base"; From 930ed05ae6ff01045d2b5ee1b7752a96432b8826 Mon Sep 17 00:00:00 2001 From: priyankar Date: Tue, 1 Dec 2020 14:33:29 +0530 Subject: [PATCH 0441/1809] ARM: dts: msm: Increase max voltage of S11B regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change: Increase max voltage of S11B regulator to 2.04V. Reason: BT and WLAN vote for S11B first followed by camera driver. As the max limit set by BT and WLAN is 1.88V, later on when camera tries to vote for same regulator it fails. As min voltage required by camera is 1.952V which is greater than max limit of BT and WLAN so camera vote cant be allowed. note: At the time of BU, camera was voting for some lower voltage thats why this issue is not seen at that time. Fix: PMIC team suggested to increase max limit for BT and WLAN as 2.04 V. The regulator S11B’s supported voltage range is min: 1.7V – max: 2.04V. Change-Id: Ie56bddc73a464610ed5a6224376f9eaa8b77bed7 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 9c68240d7f86..e25d6c74f82e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3754,7 +3754,7 @@ qcom,bt-vdd-dig-config = <950000 952000 0 1>; qcom,bt-vdd-rfacmn-config = <950000 952000 0 1>; qcom,bt-vdd-rfa-0p8-config = <950000 952000 0 1>; - qcom,bt-vdd-rfa1-config = <1880000 1880000 0 1>; + qcom,bt-vdd-rfa1-config = <1880000 2040000 0 1>; qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>; qcom,bt-vdd-asd-config = <2800000 2800000 0 1>; }; From 7d2a025db98b66d1b058cbf51cfc0a3250595015 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 9 Dec 2020 18:53:20 +0530 Subject: [PATCH 0442/1809] ARM: dts: msm: Enable tzlog driver on sdxlemur Add dtsi entries for tz log driver for sdxlemur target. Change-Id: I459411e50cbc41d992179f861dc26461aa9a1800 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 279d02c7ca5e..f651c4457dc5 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -948,6 +948,11 @@ }; }; + qcom_tzlog: tz-log@1468F720 { + compatible = "qcom,tz-log"; + reg = <0x1468F720 0x2000>; + }; + thermal_zones: thermal-zones { }; From 5346bd9ba014ab8b045abff3fc6589cc457a0918 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 9 Dec 2020 10:09:42 -0800 Subject: [PATCH 0443/1809] ARM: dts: msm: Fix pmx65 die_temp configuration Since pmx65 die_temp channel is internally read and uses absolute calibration i.e. no thermistor is used and hence doesn't need ratiometric calibration, update it. Change-Id: I3755548fb4aec9b1788702180ddc5ea07500e1f3 --- qcom/sdxlemur-pmic-overlay.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 36bac4c770ee..1aa8c1140419 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -66,8 +66,6 @@ pmx65_die_temp { reg = ; label = "pmx65_die_temp"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; From 26529e5dedc7154e431e91ec948c2beaabcc5187 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Fri, 6 Nov 2020 18:36:32 +0530 Subject: [PATCH 0444/1809] ARM: dts: qcom: Add entries for audio overlay - Add audio overlay entries. - Update the number of WSAs supported. Change-Id: Idf45765f84afab89d90a78709d7915f5ae3066c8 --- qcom/sdx-audio-lpass.dtsi | 2 +- qcom/sdx-wsa881x.dtsi | 27 ++---------- qcom/sdxlemur-audio-overlay.dtsi | 60 +++++++++++++-------------- qcom/sdxlemur-cdp-audio-overlay.dtsi | 14 +++++++ qcom/sdxlemur-cdp.dtsi | 1 + qcom/sdxlemur-ion.dtsi | 6 +++ qcom/sdxlemur-mtp-audio-overlay.dtsi | 10 +++++ qcom/sdxlemur-mtp-cpe.dtsi | 1 + qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-mtp.dtsi | 1 + qcom/sdxlemur-pinctrl.dtsi | 16 +++---- qcom/sdxlemur-wcd.dtsi | 4 +- qcom/sdxlemur.dtsi | 3 +- 16 files changed, 84 insertions(+), 65 deletions(-) create mode 100644 qcom/sdxlemur-cdp-audio-overlay.dtsi create mode 100644 qcom/sdxlemur-mtp-audio-overlay.dtsi diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi index 8a5b8374ea3f..bc1beebeac0c 100644 --- a/qcom/sdx-audio-lpass.dtsi +++ b/qcom/sdx-audio-lpass.dtsi @@ -14,7 +14,7 @@ }; qcom,msm-audio-ion { - compatible = "qcom,msm-audio-ion"; + compatible = "qcom,msm-audio-ion-cma"; memory-region = <&audio_mem>; }; diff --git a/qcom/sdx-wsa881x.dtsi b/qcom/sdx-wsa881x.dtsi index 4cf0330514ff..bd4ba29d6156 100644 --- a/qcom/sdx-wsa881x.dtsi +++ b/qcom/sdx-wsa881x.dtsi @@ -1,35 +1,16 @@ -&soc { +&i2c_3 { tavil_codec { swr_master { compatible = "qcom,swr-wcd"; #address-cells = <2>; #size-cells = <0>; - - wsa881x_0211: wsa881x@20170211 { - status = "disabled"; - compatible = "qcom,wsa881x"; - reg = <0x00 0x20170211>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; - }; - - wsa881x_0212: wsa881x@20170212 { - status = "disabled"; - compatible = "qcom,wsa881x"; - reg = <0x00 0x20170212>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; - }; - - wsa881x_0213: wsa881x@21170213 { - status = "disabled"; - compatible = "qcom,wsa881x"; - reg = <0x00 0x21170213>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; - }; + qcom,swr-num-dev = <1>; wsa881x_0214: wsa881x@21170214 { compatible = "qcom,wsa881x"; reg = <0x00 0x21170214>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + qcom,wsa-prefix = "SpkrLeft"; }; }; }; diff --git a/qcom/sdxlemur-audio-overlay.dtsi b/qcom/sdxlemur-audio-overlay.dtsi index 950bc2e383a5..172f7237318f 100644 --- a/qcom/sdxlemur-audio-overlay.dtsi +++ b/qcom/sdxlemur-audio-overlay.dtsi @@ -6,41 +6,40 @@ qcom,audio-routing = "RX_BIAS", "MCLK", "MADINPUT", "MCLK", - "AMIC2", "MIC BIAS2", - "MIC BIAS2", "Headset Mic", - "AMIC3", "MIC BIAS2", - "MIC BIAS2", "ANCRight Headset Mic", - "AMIC4", "MIC BIAS2", - "MIC BIAS2", "ANCLeft Headset Mic", - "AMIC5", "MIC BIAS3", - "MIC BIAS3", "Handset Mic", + "AMIC2", "Headset Mic", + "Headset Mic", "MIC BIAS2", + "AMIC3", "ANCRight Headset Mic", + "ANCRight Headset Mic", "MIC BIAS2", + "AMIC4", "ANCLeft Headset Mic", + "ANCLeft Headset Mic", "MIC BIAS2", + "AMIC5", "Handset Mic", + "Handset Mic", "MIC BIAS3", + "DMIC1", "Digital Mic1", "DMIC1", "MIC BIAS1", - "MIC BIAS1", "Digital Mic1", + "DMIC2", "Digital Mic2", "DMIC2", "MIC BIAS3", - "MIC BIAS3", "Digital Mic2", + "DMIC3", "Digital Mic3", "DMIC3", "MIC BIAS3", - "MIC BIAS3", "Digital Mic3", + "DMIC4", "Digital Mic4", "DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", + "DMIC5", "Digital Mic5", "DMIC5", "MIC BIAS4", - "MIC BIAS4", "Digital Mic5", - "SpkrRight IN", "SPK2 OUT"; + "SpkrLeft IN", "SPK2 OUT"; qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; qcom,cdc-ext-clk-rate = <19200000>; - qcom,tavil-mclk-clk-freq = <9600000>; + qcom,tavil-mclk-clk-freq = <12288000>; asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; + qcom,wsa-max-devs = <1>; + qcom,swr-num-dev = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft"; }; &soc { @@ -50,7 +49,7 @@ interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&tlmm>; - qcom,gpio-connect = <&tlmm 96 0>; + qcom,gpio-connect = <&tlmm 48 0>; pinctrl-names = "default"; pinctrl-0 = <&wcd_intr_default>; }; @@ -58,7 +57,7 @@ clock_audio_up: audio_ext_clk_up { compatible = "qcom,audio-ref-clk"; qcom,codec-ext-clk-src = ; - qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-clk-id = <0x302>; qcom,codec-lpass-ext-clk-freq = <9600000>; qcom,use-pinctrl = <1>; pinctrl-names = "sleep", "active"; @@ -67,16 +66,17 @@ #clock-cells = <1>; }; - wcd_rst_gpio: msm_cdc_pinctrl@92 { + wcd_rst_gpio: msm_cdc_pinctrl@49 { compatible = "qcom,msm-cdc-pinctrl"; - qcom,cdc-rst-n-gpio = <&tlmm 92 0>; + qcom,cdc-rst-n-gpio = <&tlmm 49 0>; pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&cdc_reset_active>; pinctrl-1 = <&cdc_reset_sleep>; }; }; -&soc { +&i2c_3 { + status = "ok"; wcd934x_cdc: tavil_codec { compatible = "qcom,tavil-i2c"; reg = <0x0d>; @@ -91,23 +91,23 @@ clock-names = "wcd_clk"; clocks = <&clock_audio_up 0>; - cdc-vdd-buck-supply = <&pmxprairie_l6>; + cdc-vdd-buck-supply = <&pmx65_l6>; qcom,cdc-vdd-buck-voltage = <1800000 1800000>; qcom,cdc-vdd-buck-current = <650000>; - cdc-buck-sido-supply = <&pmxprairie_l6>; + cdc-buck-sido-supply = <&pmx65_l6>; qcom,cdc-buck-sido-voltage = <1800000 1800000>; qcom,cdc-buck-sido-current = <250000>; - cdc-vdd-tx-h-supply = <&pmxprairie_l6>; + cdc-vdd-tx-h-supply = <&pmx65_l6>; qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-tx-h-current = <25000>; - cdc-vdd-rx-h-supply = <&pmxprairie_l6>; + cdc-vdd-rx-h-supply = <&pmx65_l6>; qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-rx-h-current = <25000>; - cdc-vddpx-1-supply = <&pmxprairie_l6>; + cdc-vddpx-1-supply = <&pmx65_l6>; qcom,cdc-vddpx-1-voltage = <1800000 1800000>; qcom,cdc-vddpx-1-current = <10000>; diff --git a/qcom/sdxlemur-cdp-audio-overlay.dtsi b/qcom/sdxlemur-cdp-audio-overlay.dtsi new file mode 100644 index 000000000000..589ba030b873 --- /dev/null +++ b/qcom/sdxlemur-cdp-audio-overlay.dtsi @@ -0,0 +1,14 @@ +#include "sdxlemur-audio-overlay.dtsi" + +&soc { + sound-tavil { + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft"; + }; +}; + +&wsa_spkr_wcd_sd2 { + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; +}; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 2d64f22dc8a6..4f802df82626 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -1,5 +1,6 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "sdxlemur-cnss.dtsi" +#include "sdxlemur-cdp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index 5eb8ae2d48f1..3ad735dd3ecb 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -10,6 +10,12 @@ reg = ; qcom,ion-heap-type = "MSM_SYSTEM"; }; + + qcom,ion-heap@8 { /* AUDIO HEAP */ + reg = ; + memory-region = <&audio_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/sdxlemur-mtp-audio-overlay.dtsi b/qcom/sdxlemur-mtp-audio-overlay.dtsi new file mode 100644 index 000000000000..b6680a1d9226 --- /dev/null +++ b/qcom/sdxlemur-mtp-audio-overlay.dtsi @@ -0,0 +1,10 @@ +#include "sdxlemur-audio-overlay.dtsi" + +&soc { + sound-tavil { + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft"; + }; +}; + diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index e39236090d51..42f218547fd1 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-mtp.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index e39236090d51..42f218547fd1 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-mtp.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 188a1bbe32c7..f0e34fd7795e 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,5 +1,6 @@ #include "sdxlemur-mtp.dtsi" #include "sdxlemur.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 575214139b71..b5afaa63db11 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-mtp.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b350930cd462..fe3402b3a3d0 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -3,6 +3,7 @@ #include #include #include "sdxlemur-cnss.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 7213eb337afb..586d9c3fe0dd 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 9e46bae72197..d336e3fa3eb4 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -1157,12 +1157,12 @@ wcd9xxx_intr { wcd_intr_default: wcd_intr_default { mux { - pins = "gpio96"; + pins = "gpio48"; function = "gpio"; }; config { - pins = "gpio96"; + pins = "gpio48"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* pull down */ input-enable; @@ -1173,12 +1173,12 @@ cdc_reset_ctrl { cdc_reset_sleep: cdc_reset_sleep { mux { - pins = "gpio92"; + pins = "gpio49"; function = "gpio"; }; config { - pins = "gpio92"; + pins = "gpio49"; drive-strength = <2>; bias-disable; output-low; @@ -1187,12 +1187,12 @@ cdc_reset_active:cdc_reset_active { mux { - pins = "gpio92"; + pins = "gpio49"; function = "gpio"; }; config { - pins = "gpio92"; + pins = "gpio49"; drive-strength = <8>; bias-pull-down; output-high; @@ -1275,7 +1275,7 @@ pri_ws_active_master: pri_ws_active_master { mux { pins = "gpio12"; - function = "pri_mi2s"; + function = "pri_mi2s_ws"; }; config { @@ -1303,7 +1303,7 @@ pri_ws_active_slave: pri_ws_active_slave { mux { pins = "gpio12"; - function = "pri_mi2s"; + function = "pri_mi2s_ws"; }; config { diff --git a/qcom/sdxlemur-wcd.dtsi b/qcom/sdxlemur-wcd.dtsi index 512253fd0ddd..40853ca660c5 100644 --- a/qcom/sdxlemur-wcd.dtsi +++ b/qcom/sdxlemur-wcd.dtsi @@ -1,8 +1,8 @@ -&soc { +&i2c_3 { tavil_codec { wcd: wcd_pinctrl@5 { compatible = "qcom,wcd-pinctrl"; - qcom,num-gpios = <5>; + qcom,gpios-count = <5>; gpio-controller; #gpio-cells = <2>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7ade3cdbd9a3..fc0b68ed6f9a 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -52,7 +52,8 @@ audio_mem: audio_region@0 { compatible = "shared-dma-pool"; - no-map; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; size = <0x400000>; }; From f0d74414dea208e6cc27079045811aab6868d71c Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 9 Dec 2020 14:54:09 -0800 Subject: [PATCH 0445/1809] ARM: dts: msm: Update ddr subtype for 512mb variant Updated the ddr subtype for 512mb variant. Change-Id: I2c7b14c18c17673661a0666d546587789c22a34f --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts index 10b2d8c0dbca..26181b776280 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x3010008 0x303>; + qcom,board-id = <0x3010008 0x203>; }; From 86f8d2e68346280ef1e7f12786aa38d8fa632b8b Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Wed, 9 Dec 2020 15:26:21 +0800 Subject: [PATCH 0446/1809] ARM: dts: qcom: update redriver of shima/lahaina QRD allow USB and redriver share one GPIO. Change-Id: I71934530ae01a722279eeb09bd5eaa13b0c8aff4 --- qcom/lahaina-qrd-module.dtsi | 8 +++++--- qcom/lahaina-qrd.dtsi | 8 +++++--- qcom/shima-qrd.dtsi | 8 +++++--- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/qcom/lahaina-qrd-module.dtsi b/qcom/lahaina-qrd-module.dtsi index e69c9b3b3c8d..454c4defac70 100644 --- a/qcom/lahaina-qrd-module.dtsi +++ b/qcom/lahaina-qrd-module.dtsi @@ -20,7 +20,7 @@ }; &usb_qmp_dp_phy { - pinctrl-names = "portselect"; + pinctrl-names = "unused"; }; &usb0 { @@ -30,13 +30,15 @@ &qupv3_se13_i2c { status = "ok"; + #address-cells = <1>; + #size-cells = <0>; redriver: redriver@1c { compatible = "onnn,redriver"; reg = <0x1c>; - pinctrl-names = "enable_gpio"; + pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_gpio>; - orientation_gpio = <&tlmm 81 0>; + gpios = <&tlmm 81 0>; eq = /bits/ 8 < /* Parameters for USB */ diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi index d169151f2a0f..6f951aa71eb1 100644 --- a/qcom/lahaina-qrd.dtsi +++ b/qcom/lahaina-qrd.dtsi @@ -20,7 +20,7 @@ }; &usb_qmp_dp_phy { - pinctrl-names = "portselect"; + pinctrl-names = "unused"; }; &usb0 { @@ -30,13 +30,15 @@ &qupv3_se13_i2c { status = "ok"; + #address-cells = <1>; + #size-cells = <0>; redriver: redriver@1c { compatible = "onnn,redriver"; reg = <0x1c>; - pinctrl-names = "enable_gpio"; + pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_gpio>; - orientation_gpio = <&tlmm 81 0>; + gpios = <&tlmm 81 0>; eq = /bits/ 8 < /* Parameters for USB */ diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 89af7cd016bc..926f4c272a16 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -481,19 +481,21 @@ }; &usb_qmp_dp_phy { - pinctrl-names = "portselect"; + pinctrl-names = "unused"; }; &qupv3_se5_i2c { status = "ok"; + #address-cells = <1>; + #size-cells = <0>; redriver: redriver@1c { compatible = "onnn,redriver"; reg = <0x1c>; - pinctrl-names = "enable_gpio"; + pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_gpio>; - orientation_gpio = <&tlmm 81 0>; + gpios = <&tlmm 81 0>; eq = /bits/ 8 < /* Parameters for USB */ From ce961a50c26e5b35c965baf5b08a2db12f56bc53 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Thu, 10 Dec 2020 12:13:31 +0530 Subject: [PATCH 0447/1809] ARM: dts: msm: Add reserved region for uefi for holi Add reserve region for uefi to avoid mapping of same in kernel. Change-Id: I4e8a3a2b5d9acc7e389e666ab74232279902f54b --- qcom/holi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e82cea81e542..1353a8b75ddd 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -309,6 +309,11 @@ reg = <0x0 0x80860000 0x0 0x20000>; }; + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + smem_mem: smem@80900000 { no-map; reg = <0x0 0x80900000 0x0 0x200000>; From 1314b3182081d2e4fd90ef445f8ec1ee551d301f Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Thu, 22 Oct 2020 18:46:03 +0530 Subject: [PATCH 0448/1809] ARM: dts: msm: Add PIL node for WPSS in Yupik DTSI Add support for loading WPSS usnig PIL generic driver. Change-Id: Iebb7b1534c353e875df421c6943a364d408cba39 --- qcom/yupik-rumi.dtsi | 3 +++ qcom/yupik.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 214eb9eb7441..9ef144149b00 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -58,7 +58,10 @@ clocks = <&xo_board>; #clock-cells = <0>; }; +}; +&pil_wpss { + clocks = <&bi_tcxo>; }; &usb0 { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c7b0ec92ddbe..20c6b6d4bdb1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1372,6 +1372,48 @@ }; }; + pil_wpss: qcom,wpss@8a00000 { + compatible = "qcom,pil-tz-generic"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + /* Needs to add vdd_cx at SOD time.*/ + + qcom,firmware-name = "wpss"; + memory-region = <&pil_wpss_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,minidump-id = <4>; + qcom,ssctl-instance-id = <0x19>; + qcom,pas-id = <0x6>; + qcom,smem-id = <626>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "wpss-pil"; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP From ebb087f4de57baccb8fa589e5261302b718d4438 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 2 Dec 2020 18:03:46 +0530 Subject: [PATCH 0449/1809] ARM: dts: msm: Add Yupik trustedVM device configuration Add device configuration for RUMI/IDP/ATP/QRD platforms for Yupik trusted VM. Change-Id: Ib62b74bcea63689218d16f4604b0373be917aaf9 --- qcom/Makefile | 9 ++ qcom/yupik-vm-atp.dts | 10 ++ qcom/yupik-vm-atp.dtsi | 2 + qcom/yupik-vm-idp.dts | 10 ++ qcom/yupik-vm-idp.dtsi | 2 + qcom/yupik-vm-qrd.dts | 10 ++ qcom/yupik-vm-qrd.dtsi | 2 + qcom/yupik-vm-rumi.dts | 11 ++ qcom/yupik-vm-rumi.dtsi | 5 + qcom/yupik-vm.dtsi | 227 ++++++++++++++++++++++++++++++++++++++++ 10 files changed, 288 insertions(+) create mode 100644 qcom/yupik-vm-atp.dts create mode 100644 qcom/yupik-vm-atp.dtsi create mode 100644 qcom/yupik-vm-idp.dts create mode 100644 qcom/yupik-vm-idp.dtsi create mode 100644 qcom/yupik-vm-qrd.dts create mode 100644 qcom/yupik-vm-qrd.dtsi create mode 100644 qcom/yupik-vm-rumi.dts create mode 100644 qcom/yupik-vm-rumi.dtsi create mode 100644 qcom/yupik-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 793a51038a7f..e61756bacf4a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -230,6 +230,15 @@ dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ sdxnightjar-cdp.dtb \ sdxnightjar-qrd.dtb +ifeq ($(CONFIG_ARCH_YUPIK), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtb-$(CONFIG_ARCH_QTI_VM) += yupik-vm-rumi.dtb \ + yupik-vm-atp.dtb \ + yupik-vm-idp.dtb \ + yupik-vm-qrd.dtb +endif +endif + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/yupik-vm-atp.dts b/qcom/yupik-vm-atp.dts new file mode 100644 index 000000000000..f018914d5ff6 --- /dev/null +++ b/qcom/yupik-vm-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-vm.dtsi" +#include "yupik-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik VM ATP"; + compatible = "qcom,yupik-atp", "qcom,yupik", "qcom,atp"; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/yupik-vm-atp.dtsi b/qcom/yupik-vm-atp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-vm-atp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/yupik-vm-idp.dts b/qcom/yupik-vm-idp.dts new file mode 100644 index 000000000000..26076b98e008 --- /dev/null +++ b/qcom/yupik-vm-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-vm.dtsi" +#include "yupik-vm-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik VM IDP"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-vm-idp.dtsi b/qcom/yupik-vm-idp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-vm-idp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/yupik-vm-qrd.dts b/qcom/yupik-vm-qrd.dts new file mode 100644 index 000000000000..785e01cba32f --- /dev/null +++ b/qcom/yupik-vm-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-vm.dtsi" +#include "yupik-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik VM QRD"; + compatible = "qcom,yupik-qrd", "qcom,yupik", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupik-vm-qrd.dtsi b/qcom/yupik-vm-qrd.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/yupik-vm-qrd.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/yupik-vm-rumi.dts b/qcom/yupik-vm-rumi.dts new file mode 100644 index 000000000000..2ab68ccf2f9d --- /dev/null +++ b/qcom/yupik-vm-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "yupik-vm.dtsi" +#include "yupik-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik SVM RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-vm-rumi.dtsi b/qcom/yupik-vm-rumi.dtsi new file mode 100644 index 000000000000..48c92e0c09e8 --- /dev/null +++ b/qcom/yupik-vm-rumi.dtsi @@ -0,0 +1,5 @@ +&soc { + timer { + clock-frequency = <5000000>; + }; +}; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi new file mode 100644 index 000000000000..9fbf122b960a --- /dev/null +++ b/qcom/yupik-vm.dtsi @@ -0,0 +1,227 @@ +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <475 0x10000>; + interrupt-parent = <&vgic>; + + qcom-mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + }; + + chosen { + bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + linux,initrd-start = <0x2a900000>; + linux,initrd-end = <0x2b100000>; /* 8 MB */ + kaslr-seed = <0xfeedbeef 0xc0def00d>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN>; + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + neuron-client-block { + compatible = "qcom,neuron-service"; + #address-cells = <1>; + #size-cells = <0>; + + protocol { + compatible = "qcom,neuron-protocol-block"; + processes = "client"; + }; + + application { + compatible = "qcom,neuron-block-client"; + }; + + channel@0 { + reg = <0>; + compatible = "qcom,neuron-channel-haven-shmem"; + class = "message-queue"; + direction = "send"; + max-size = <0 65536>; + haven-label = <1>; + }; + + channel@1 { + reg = <1>; + compatible = "qcom,neuron-channel-haven-shmem"; + class = "message-queue"; + direction = "receive"; + max-size = <0 65536>; + haven-label = <2>; + }; + }; + + qrtr-haven { + compatible = "qcom,qrtr-haven"; + haven-label = <3>; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "Qualcomm Technologies, Inc."; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + + iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0 + 0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1 + 0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1 + 0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1 + 0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1 + 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; + + gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */ + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + base-address = <0x0 0xD0800000>; + size-min = <0x0 0x76f7000>; /* 118 MB */ + }; + + segments { + ramdisk = <2>; /* 8MB */ + }; + + vcpus { + config = "/cpus"; + affinity = "static"; + affinity-map = <0x4 0x5>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + + neuron-ch1-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/neuron-ch1-shm"; + push-compatible = "qcom,neuron-channel-haven-shmem-gen"; + peer-default; + memory { + qcom,label = <0x1>; + allocate-base; + }; + }; + + neuron-ch2-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/neuron-ch2-shm"; + push-compatible = "qcom,neuron-channel-haven-shmem-gen"; + peer-default; + memory { + qcom,label = <0x2>; + allocate-base; + }; + }; + + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-haven-gen"; + peer-default; + memory { + qcom,label = <0x3>; + allocate-base; + }; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + }; +}; From 8353df6d34793ec86e757e7b5b56195c9982aaa5 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Thu, 12 Nov 2020 13:26:02 +0530 Subject: [PATCH 0450/1809] ARM: dts: msm: Add clock controller nodes for SDXNIGHTJAR Add GCC/DEBUGCC/RPMCC clock controller nodes for SDXNIGHTJAR. Change-Id: Ieee31a7fcca34634ce5c523cb9d72c25e2f1c16a --- qcom/sdxnightjar.dtsi | 55 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index ffae6937de9b..6f4fa1aae835 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1,4 +1,6 @@ #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; @@ -96,19 +98,58 @@ }; }; - clock_gcc: qcom,gcc@1800000 { - ompatible = "qcom,dummycc"; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-sdxnightjar"; #clock-cells = <1>; }; - clock_debug: qcom,cc-debug@1874000 { - compatible = "qcom,dummycc"; + gcc: qcom,gcc@1800000 { + compatible = "qcom,sdxnightjar-gcc", "syscon"; + reg = <0x1800000 0x80000>; + reg-names = "cc_base"; + vdd_cx-supply = <&pmd9650_s5_level>; + vdd_cx_ao-supply = <&pmd9650_s5_level_ao>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + debugcc: qcom,cc-debug@1874000 { + compatible = "qcom,sdxnightjar-debugcc"; + qcom,gcc = <&gcc>; + clock-names = "xo_clk_src"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; #clock-cells = <1>; }; - clock_cpu: qcom,clock-a7@0b010008 { - compatible = "qcom,dummycc"; - #clock-cells = <1>; + gdsc_usb30: qcom,gdsc@fc401e84 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x185e078 0x4>; + }; + + gdsc_pcie: qcom,gdsc@0xfc401e18 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_pcie"; + reg = <0x0185d044 0x4>; }; qcom,msm-cpufreq { From 845ee6ed4d6f1e7f265598a10a83d44b1a46a512 Mon Sep 17 00:00:00 2001 From: Siva Kumar Akkireddi Date: Thu, 10 Dec 2020 18:48:36 +0530 Subject: [PATCH 0451/1809] ARM: dts: msm: Add SPS node for SDXNIGHTJAR Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for SDXNIGHTJAR. Change-Id: I73916bc9b28523bb92fe3ceb823440531519210d --- qcom/sdxnightjar.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index ffae6937de9b..74ee1c8a5fd9 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -212,8 +212,10 @@ }; }; - - + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; qcom,msm_gsi { compatible = "qcom,msm_gsi"; From cb1c36fc8734b2afcace061b7ea0d78456bc735d Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Wed, 9 Dec 2020 13:18:31 -0800 Subject: [PATCH 0452/1809] ARM: dts: msm: Add support for SM8325 platforms Add support for SM8325 platform for the MSM and APQ variants. Change-Id: If5dbbbec42ca4b51067173fab69496ef504fac14 --- qcom/lahaina-v2.1.dtsi | 2 +- qcom/lahaina-v2.dtsi | 2 +- qcom/lahaina-vm-v2.dtsi | 2 +- qcom/lahaina-vm.dtsi | 2 +- qcom/lahaina.dtsi | 2 +- qcom/lahainap-v2.1.dtsi | 2 +- qcom/lahainap-v2.dtsi | 2 +- qcom/lahainap.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-v2.1.dtsi b/qcom/lahaina-v2.1.dtsi index 15408d1cb09f..05d6a478c305 100644 --- a/qcom/lahaina-v2.1.dtsi +++ b/qcom/lahaina-v2.1.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina v2.1"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20001>, <456 0x20001>; + qcom,msm-id = <415 0x20001>, <456 0x20001>, <501 0x20001>; }; &pcie0 { diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 02c849e2dba2..577504633359 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina v2"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20000>, <456 0x20000>; + qcom,msm-id = <415 0x20000>, <456 0x20000>, <501 0x20000>; }; &CPU4 { diff --git a/qcom/lahaina-vm-v2.dtsi b/qcom/lahaina-vm-v2.dtsi index 6c5494ed784f..5cddeda9c901 100644 --- a/qcom/lahaina-vm-v2.dtsi +++ b/qcom/lahaina-vm-v2.dtsi @@ -3,5 +3,5 @@ / { model = "Qualcomm Technologies, Inc. Lahaina VM v2"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20000>; + qcom,msm-id = <415 0x20000>, <501 0x20000>; }; diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index f7b2d6708460..e59a59188cba 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -6,7 +6,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <415 0x10000>; + qcom,msm-id = <415 0x10000>, <501 0x10000>; interrupt-parent = <&vgic>; qcom-mem-buf { diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 2f972efe885c..841b453c9ee9 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -27,7 +27,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x10000>, <456 0x10000>; + qcom,msm-id = <415 0x10000>, <456 0x10000>, <501 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 99f51cf73f39..67728c60f3b9 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -3,5 +3,5 @@ / { model = "Qualcomm Technologies, Inc. LahainaP v2.1"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x20001>; + qcom,msm-id = <439 0x20001>, <502 0x20001>; }; diff --git a/qcom/lahainap-v2.dtsi b/qcom/lahainap-v2.dtsi index dd53c27b15b6..118618be4b7b 100644 --- a/qcom/lahainap-v2.dtsi +++ b/qcom/lahainap-v2.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. LahainaP v2"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x20000>; + qcom,msm-id = <439 0x20000>, <502 0x20000>; }; &ipa_hw { diff --git a/qcom/lahainap.dtsi b/qcom/lahainap.dtsi index dee1f6a43c26..ae99b94831d3 100644 --- a/qcom/lahainap.dtsi +++ b/qcom/lahainap.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. LahainaP"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x10000>; + qcom,msm-id = <439 0x10000>, <502 0x10000>; }; &ipa_hw { From 3ee9379acf7f4578a1eccc7f6cba8974a8cf1c02 Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Thu, 10 Dec 2020 12:22:52 +0530 Subject: [PATCH 0453/1809] ARM: dts: qcom: enable hypervisor core_ctl for Yupik Enable hyp_core_ctl support for Yupik, which is used reserving cpus for Secondary VM. Change-Id: Icfd08b04c290c63e919ee3941f0727344bf842c0 --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 16cbd231d5f8..4c7225f15669 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -505,6 +505,11 @@ }; }; + hyp_core_ctl: qcom,hyp-core-ctl { + compatible = "qcom,hyp-core-ctl"; + status = "ok"; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; From a87724249061ade73b979754374d3c4204d75426 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 2 Nov 2020 23:17:10 +0530 Subject: [PATCH 0454/1809] ARM: dts: msm: Add USB nodes for SDXNIGHTJAR Add usb nodes to support usb in high speed for SDXNIGHTJAR. Change-Id: I9f7c12da4adcf60a30a04a8125138efb1f84e3d1 --- qcom/sdxnightjar-usb.dtsi | 94 +++++++++++++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 1 + 2 files changed, 95 insertions(+) create mode 100644 qcom/sdxnightjar-usb.dtsi diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi new file mode 100644 index 000000000000..0f48467b6a62 --- /dev/null +++ b/qcom/sdxnightjar-usb.dtsi @@ -0,0 +1,94 @@ +&soc { + usb3: ssusb@8a00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x08a00000 0xf8c00>, + <0x0007e000 0x400>; + reg-names = "core_base", "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq"; + USB3_GDSC-supply = <&gdsc_usb30>; + + qcom,lpm-to-suspend-delay-ms = <2000>; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_PHY_CFG_AHB_CLK>; + + clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", + "xo", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB_30_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x140 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x08a00000 0xcd00>; + interrupts = ; + usb-phy = <&qusb_phy>, <&usb_nop_phy>; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,bus-suspend-enable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + xhci-imod-value = <4000>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + qusb_phy: qusb@79000 { + compatible = "qcom,qusb2phy"; + reg = <0x00079000 0x180>; + reg-names = "qusb_phy_base"; + vdd-supply = <&pmd9650_l4>; + vdda18-supply = <&pmd9650_l5>; + vdda33-supply = <&pmd9650_l10>; + qcom,vdd-voltage-level = <0 928000 928000>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_QUSB_REF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>; + + clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", + "iface_clk"; + + resets = <&gcc GCC_QUSB2A_PHY_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; + diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 622d46a7c381..8f058b323235 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -429,4 +429,5 @@ #include "pmd9650.dtsi" #include "pmd9650-rpm-regulator.dtsi" #include "sdxnightjar-regulator.dtsi" +#include "sdxnightjar-usb.dtsi" #include "sdxnightjar-pinctrl.dtsi" From 8dd34523051fbd0227ad07243acd0b2e2734c228 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Fri, 11 Dec 2020 11:43:50 +0530 Subject: [PATCH 0455/1809] ARM: dts: msm: Add Superspeed PHY node on sdxnightjar Add Superspeed PHY node and the corresponding resources to support USB superspeed on sdxnightjar. Change-Id: Ib41978095f544b3dac76109274c31778ce6ba6af --- qcom/sdxnightjar-usb.dtsi | 106 +++++++++++++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 0f48467b6a62..e274820066d5 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -42,7 +42,7 @@ compatible = "snps,dwc3"; reg = <0x08a00000 0xcd00>; interrupts = ; - usb-phy = <&qusb_phy>, <&usb_nop_phy>; + usb-phy = <&qusb_phy>, <&ssphy>; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; @@ -50,7 +50,7 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; xhci-imod-value = <4000>; - maximum-speed = "high-speed"; + maximum-speed = "super-speed"; dr_mode = "otg"; }; }; @@ -87,6 +87,108 @@ reset-names = "phy_reset"; }; + ssphy: ssphy@78000 { + compatible = "qcom,usb-ssphy-qmp"; + reg = <0x00078000 0x9f8>, + <0x01947244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + qcom,qmp-phy-init-seq = <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x194 0x06 0x3e8 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x70 0x0f 0x00 + 0x100 0x80 0x00 + 0x440 0x0b 0x00 + 0x4d8 0x02 0x00 + 0x4dc 0x6c 0x00 + 0x4e0 0xbb 0x00 + 0x508 0x77 0x00 + 0x50c 0x80 0x00 + 0x514 0x03 0x00 + 0x51c 0x16 0x00 + 0x448 0x75 0x00 + 0x454 0x00 0x00 + 0x40c 0x0a 0x00 + 0x41c 0x06 0x00 + 0x510 0x00 0x00 + 0x268 0x45 0x00 + 0x2ac 0x12 0x00 + 0x294 0x06 0x00 + 0x254 0x00 0x00 + 0x8c8 0x83 0x00 + 0x8c4 0x02 0x00 + 0x8cc 0x09 0x00 + 0x8d0 0xa2 0x00 + 0x8d4 0x85 0x00 + 0x880 0xd1 0x00 + 0x884 0x1f 0x00 + 0x888 0x47 0x00 + 0x80c 0x9f 0x00 + 0x824 0x17 0x00 + 0x828 0x0f 0x00 + 0x8b8 0x75 0x00 + 0x8bc 0x13 0x00 + 0x8b0 0x86 0x00 + 0x8a0 0x04 0x00 + 0x88c 0x44 0x00 + 0x870 0xe7 0x00 + 0x874 0x03 0x00 + 0x878 0x40 0x00 + 0x87c 0x00 0x00 + 0x9d8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800 + 0x808>; + vdd-supply = <&pmd9650_l4>; + core-supply = <&pmd9650_l5>; + qcom,vdd-voltage-level = <0 928000 928000>; + qcom,core-voltage-level = <0 1800000 1800000>; + + clocks = <&gcc GCC_USB3_AUX_CLK>, + <&gcc GCC_USB3_PIPE_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_SS_REF_CLK>; + + clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", + "ref_clk_src", "ref_clk"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; From 47510aa48a3a36e01c023558ca27f0ba2f176394 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 9 Dec 2020 18:54:48 +0800 Subject: [PATCH 0456/1809] ARM: dts: msm: Add QDSS IPA bam connection config for sdxlemur Add QDSS IPA bam connection config for QDSS to pcie hw transfer. Change-Id: Ia129b5f201a44b89d29ef91bb557616183af4c43 --- bindings/arm/coresight.txt | 3 +++ qcom/sdxlemur-coresight.dtsi | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 9991ffa3e0d9..a4d29ec88108 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -151,6 +151,9 @@ its hardware characteristcs. * cti-flush-trig-num: Specifies the flush CTI trigger number for TMC ETR and TMC ETF. + * qcom,qdss-ipa-support : indicates whether qdss to ipa bam connection + need to support. + * Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address error for CATU and four interrupts for TGU to get trigger from four diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 073cfa4332f9..2678a9b36f87 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -148,6 +148,13 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + qcom,qdss-ipa-support; + ipa-conn-data-base-pa = <0x1468B000>; + ipa-conn-data-size = <0x3000>; + ipa-conn-desc-base-pa = <0x1468E000>; + ipa-conn-desc-size = <0x1000>; + ipa-peer-evt-reg-pa = <0x6077818>; + coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; cti-reset-trig-num = <0>; From 7ac37e6cc5ec7815ab259859c41c1ba4e17c105e Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 11 Dec 2020 16:04:36 +0530 Subject: [PATCH 0457/1809] ARM: dts: msm: Update the init-mode of LDO11C for shima Update the init-mode of LDO11C to LPM and leaving it to the clients to configure the mode runtime. This improves the power if there is no requirement from the client to be in LPM. Change-Id: I811db3a1bb7cbd12a3781c01d43d3a63501308b0 --- qcom/shima-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index 1f59c58316c9..56356b7c06a4 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -661,7 +661,7 @@ regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; qcom,init-voltage = <1650000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; From e8931d6dddc7ebd64ac5d5d1d46366232c4d882d Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Fri, 11 Dec 2020 20:06:26 +0800 Subject: [PATCH 0458/1809] ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina This reverts commit dcb08f648448d2127c0ca2c021841e128463d51a. This is to enable dma-coherent for tmc-etr to aovid cache flush issue. Change-Id: Ie36cd7612a33f3b09bb3aa0894e459b42291ff6a --- qcom/lahaina-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index ff7750e6f034..b773c609af39 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -154,6 +154,7 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + dma-coherent; qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; From 0d9e03032e643055b199d995268d772d22664e1f Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 2 Dec 2020 23:01:58 +0530 Subject: [PATCH 0459/1809] ARM: dts: msm: Add bcm voter devices for Yupik Add bcm voter devices that live under RSC devices to allow interconnect providers to target their votes for meeting bandwidth constraints. Change-Id: Iffa6b6dbcc02cf00448940184de8fae7382772ad --- qcom/yupik.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 16cbd231d5f8..a5c5ceab5b08 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -856,36 +856,48 @@ clk_virt: interconnect { compatible = "qcom,yupik-clk_virt"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; cnoc2: interconnect@1500000 { reg = <0x1500000 0x1000>; compatible = "qcom,yupik-cnoc2"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; cnoc3: interconnect@1502000 { reg = <0x1502000 0x1000>; compatible = "qcom,yupik-cnoc3"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1580000 { reg = <0x1580000 0x4>; compatible = "qcom,yupik-mc_virt"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; system_noc: interconnect@1680000 { reg = <0x1680000 0x15480>; compatible = "qcom,yupik-system_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,yupik-aggre1_noc"; reg = <0x016e0000 0x1c080>; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; @@ -894,6 +906,8 @@ reg = <0x1700000 0x2b080>; compatible = "qcom,yupik-aggre2_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, @@ -904,30 +918,40 @@ reg = <0x1740000 0x1e080>; compatible = "qcom,yupik-mmss_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; lpass_ag_noc: interconnect@3c40000 { reg = <0x03c40000 0xf080>; compatible = "qcom,yupik-lpass_ag_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; dc_noc: interconnect@90e0000 { reg = <0x90e0000 0x5080>; compatible = "qcom,yupik-dc_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { reg = <0x9100000 0xe2200>; compatible = "qcom,yupik-gem_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; nsp_noc: interconnect@a0c0000 { reg = <0x0a0c0000 0x10000>; compatible = "qcom,yupik-nsp_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; epss_l3_cpu: l3_cpu@18590000 { @@ -961,6 +985,10 @@ compatible = "qcom,system-pm"; }; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: qcom,rpmhclk { compatible = "qcom,yupik-rpmh-clk"; #clock-cells = <1>; @@ -980,6 +1008,11 @@ , , ; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; }; spmi_bus: qcom,spmi@c440000 { From fd39fc40c7fe18888c3f0489315221016b8c4b6a Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 20 Jul 2020 11:33:57 +0530 Subject: [PATCH 0460/1809] ARM: dts: msm: Add initial device tree for SA6155 Add initial device tree to support SA6155 chipset on automotive platforms. Change-Id: I27ea3d0a1972fa852298af07f13464e717900af1 --- bindings/arm/msm/msm.txt | 6 + bindings/clock/qcom,rpmh-clk.txt | 1 + qcom/Makefile | 30 + qcom/sa6155-adp-air-overlay.dts | 11 + qcom/sa6155-adp-air.dts | 10 + qcom/sa6155-adp-air.dtsi | 1 + qcom/sa6155-adp-common.dtsi | 5 + qcom/sa6155-adp-star-overlay.dts | 11 + qcom/sa6155-adp-star.dts | 9 + qcom/sa6155-adp-star.dtsi | 1 + qcom/sa6155.dts | 9 + qcom/sa6155.dtsi | 8 + qcom/sa6155p-adp-air-overlay.dts | 11 + qcom/sa6155p-adp-air.dts | 10 + qcom/sa6155p-adp-star-lpass-overlay.dts | 12 + qcom/sa6155p-adp-star-lpass.dts | 12 + qcom/sa6155p-adp-star-overlay.dts | 11 + qcom/sa6155p-adp-star.dts | 10 + qcom/sa6155p-v2-adp-air-lpass-overlay.dts | 11 + qcom/sa6155p-v2-adp-air-lpass.dts | 12 + qcom/sa6155p-v2-adp-air-overlay.dts | 11 + qcom/sa6155p-v2-adp-air.dts | 10 + qcom/sa6155p-v2-adp-star-overlay.dts | 11 + qcom/sa6155p-v2-adp-star.dts | 10 + qcom/sa6155p.dts | 9 + qcom/sa6155p.dtsi | 7 + qcom/sm6150-qupv3.dtsi | 18 + qcom/sm6150.dts | 10 + qcom/sm6150.dtsi | 682 ++++++++++++++++++++++ qcom/sm6150p.dts | 10 + qcom/sm6150p.dtsi | 7 + 31 files changed, 976 insertions(+) create mode 100644 qcom/sa6155-adp-air-overlay.dts create mode 100644 qcom/sa6155-adp-air.dts create mode 100644 qcom/sa6155-adp-air.dtsi create mode 100644 qcom/sa6155-adp-common.dtsi create mode 100644 qcom/sa6155-adp-star-overlay.dts create mode 100644 qcom/sa6155-adp-star.dts create mode 100644 qcom/sa6155-adp-star.dtsi create mode 100644 qcom/sa6155.dts create mode 100644 qcom/sa6155.dtsi create mode 100644 qcom/sa6155p-adp-air-overlay.dts create mode 100644 qcom/sa6155p-adp-air.dts create mode 100644 qcom/sa6155p-adp-star-lpass-overlay.dts create mode 100644 qcom/sa6155p-adp-star-lpass.dts create mode 100644 qcom/sa6155p-adp-star-overlay.dts create mode 100644 qcom/sa6155p-adp-star.dts create mode 100644 qcom/sa6155p-v2-adp-air-lpass-overlay.dts create mode 100644 qcom/sa6155p-v2-adp-air-lpass.dts create mode 100644 qcom/sa6155p-v2-adp-air-overlay.dts create mode 100644 qcom/sa6155p-v2-adp-air.dts create mode 100644 qcom/sa6155p-v2-adp-star-overlay.dts create mode 100644 qcom/sa6155p-v2-adp-star.dts create mode 100644 qcom/sa6155p.dts create mode 100644 qcom/sa6155p.dtsi create mode 100644 qcom/sm6150-qupv3.dtsi create mode 100644 qcom/sm6150.dts create mode 100644 qcom/sm6150.dtsi create mode 100644 qcom/sm6150p.dts create mode 100644 qcom/sm6150p.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 5274f24ffb56..9e6bd7969c74 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -239,6 +239,12 @@ compatible = "qcom,sm6150-mtp" compatible = "qcom,sm6150-cdp" compatible = "qcom,sm6150-qrd" compatible = "qcom,sm6150-idp" +compatible = "qcom,sm6150p" +compatible = "qcom,sa6155-adp-star" +compatible = "qcom,sa6155p-adp-star" +compatible = "qcom,sa6155p" +compatible = "qcom,sa6155-adp-air" +compatible = "qcom,sa6155p-adp-air" compatible = "qcom,qcs405-rumi" compatible = "qcom,qcs405-iot" compatible = "qcom,qcs403-iot" diff --git a/bindings/clock/qcom,rpmh-clk.txt b/bindings/clock/qcom,rpmh-clk.txt index 2f8d511d701f..877068e9a435 100644 --- a/bindings/clock/qcom,rpmh-clk.txt +++ b/bindings/clock/qcom,rpmh-clk.txt @@ -12,6 +12,7 @@ Required properties : "qcom,kona-rpmh-clk", "qcom,sdm845-rpmh-clk" "qcom,sm8150-rpmh-clk" + "qcom,sm6150-rpmh-clk" "qcom,sdxlemur-rpmh-clk" "qcom,yupik-rpmh-clk" diff --git a/qcom/Makefile b/qcom/Makefile index 543aa180dcd1..cdb2f2bf458a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -184,6 +184,36 @@ dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155p-v2-adp-air.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SA6155) += \ + sa6155-adp-star-overlay.dtbo \ + sa6155p-adp-star-overlay.dtbo \ + sa6155p-adp-star-lpass-overlay.dtbo \ + sa6155-adp-air-overlay.dtbo \ + sa6155p-adp-air-overlay.dtbo \ + sa6155p-v2-adp-star-overlay.dtbo \ + sa6155p-v2-adp-air-overlay.dtbo \ + sa6155p-v2-adp-air-lpass-overlay.dtbo + +sa6155-adp-star-overlay.dtbo-base := sa6155.dtb +sa6155p-adp-star-overlay.dtbo-base := sa6155p.dtb +sa6155p-adp-star-lpass-overlay.dtbo-base :=sa6155p.dtb +sa6155p-v2-adp-star-overlay.dtbo-base := sa6155p.dtb +sa6155-adp-air-overlay.dtbo-base := sa6155.dtb +sa6155p-adp-air-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-air-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-air-lpass-overlay.dtbo-base := sa6155p.dtb +else +dtb-$(CONFIG_ARCH_SA6155) += sa6155-adp-star.dtb \ + sa6155p-adp-star.dtb \ + sa6155p-adp-star-lpass.dtb \ + sa6155-adp-air.dtb \ + sa6155p-adp-air.dtb \ + sa6155p-v2-adp-star.dtb \ + sa6155p-v2-adp-air.dtb \ + sa6155p-v2-adp-air-lpass.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SA8195) += \ sa8195p-adp-star-overlay.dtbo \ diff --git a/qcom/sa6155-adp-air-overlay.dts b/qcom/sa6155-adp-air-overlay.dts new file mode 100644 index 000000000000..ae2cf1199a62 --- /dev/null +++ b/qcom/sa6155-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-AIR"; + compatible = "qcom,sa6155-adp-air", "qcom,sa6155", "qcom,adp-air"; + qcom,msm-id = <384 0x0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/qcom/sa6155-adp-air.dts b/qcom/sa6155-adp-air.dts new file mode 100644 index 000000000000..750e157d640b --- /dev/null +++ b/qcom/sa6155-adp-air.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa6155.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-AIR"; + compatible = "qcom,sa6155-adp-air", "qcom,sa6155", "qcom,adp-air"; + qcom,board-id = <0x03010019 0>; +}; diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi new file mode 100644 index 000000000000..91c1ac0cdf99 --- /dev/null +++ b/qcom/sa6155-adp-air.dtsi @@ -0,0 +1 @@ +#include "sa6155-adp-common.dtsi" diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi new file mode 100644 index 000000000000..c2d9e07465c0 --- /dev/null +++ b/qcom/sa6155-adp-common.dtsi @@ -0,0 +1,5 @@ +#include + +&qupv3_0 { + status = "ok"; +}; diff --git a/qcom/sa6155-adp-star-overlay.dts b/qcom/sa6155-adp-star-overlay.dts new file mode 100644 index 000000000000..cd1c59523798 --- /dev/null +++ b/qcom/sa6155-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-STAR"; + compatible = "qcom,sa6155-adp-star", "qcom,sa6155", "qcom,adp-star"; + qcom,msm-id = <384 0x0>; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa6155-adp-star.dts b/qcom/sa6155-adp-star.dts new file mode 100644 index 000000000000..d77e02ff960b --- /dev/null +++ b/qcom/sa6155-adp-star.dts @@ -0,0 +1,9 @@ +/dts-v1/; +#include "sa6155.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-STAR"; + compatible = "qcom,sa6155-adp-star", "qcom,sa6155", "qcom,adp-star"; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa6155-adp-star.dtsi b/qcom/sa6155-adp-star.dtsi new file mode 100644 index 000000000000..91c1ac0cdf99 --- /dev/null +++ b/qcom/sa6155-adp-star.dtsi @@ -0,0 +1 @@ +#include "sa6155-adp-common.dtsi" diff --git a/qcom/sa6155.dts b/qcom/sa6155.dts new file mode 100644 index 000000000000..a291137daa1b --- /dev/null +++ b/qcom/sa6155.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "sa6155.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 SoC"; + compatible = "qcom,sa6155"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi new file mode 100644 index 000000000000..3306572750b1 --- /dev/null +++ b/qcom/sa6155.dtsi @@ -0,0 +1,8 @@ +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155"; + compatible = "qcom,sa6155"; + qcom,msm-name = "SA6155"; + qcom,msm-id = <384 0x10000>; +}; diff --git a/qcom/sa6155p-adp-air-overlay.dts b/qcom/sa6155p-adp-air-overlay.dts new file mode 100644 index 000000000000..c584ca4a7946 --- /dev/null +++ b/qcom/sa6155p-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/qcom/sa6155p-adp-air.dts b/qcom/sa6155p-adp-air.dts new file mode 100644 index 000000000000..20c0b040210a --- /dev/null +++ b/qcom/sa6155p-adp-air.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x03010019 0>; +}; diff --git a/qcom/sa6155p-adp-star-lpass-overlay.dts b/qcom/sa6155p-adp-star-lpass-overlay.dts new file mode 100644 index 000000000000..74aa69119ddc --- /dev/null +++ b/qcom/sa6155p-adp-star-lpass-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" + +/ { + model = "LPASS Audio PLL sourced from eMAC PPO ADP-Star"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x01010019 0>; +}; + diff --git a/qcom/sa6155p-adp-star-lpass.dts b/qcom/sa6155p-adp-star-lpass.dts new file mode 100644 index 000000000000..7615a0f40afe --- /dev/null +++ b/qcom/sa6155p-adp-star-lpass.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P LPASS Audio PLL sourced + from eMAC PPO ADP-Star"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x01010019 0>; +}; + diff --git a/qcom/sa6155p-adp-star-overlay.dts b/qcom/sa6155p-adp-star-overlay.dts new file mode 100644 index 000000000000..0a49f5baca76 --- /dev/null +++ b/qcom/sa6155p-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa6155p-adp-star.dts b/qcom/sa6155p-adp-star.dts new file mode 100644 index 000000000000..2ccdcf0a1278 --- /dev/null +++ b/qcom/sa6155p-adp-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-air-lpass-overlay.dts b/qcom/sa6155p-v2-adp-air-lpass-overlay.dts new file mode 100644 index 000000000000..e8b6ba202f7c --- /dev/null +++ b/qcom/sa6155p-v2-adp-air-lpass-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" + +/ { + model = "LPASS Audio PLL sourced from eMAC PPO ADP-Air"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x04010019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-air-lpass.dts b/qcom/sa6155p-v2-adp-air-lpass.dts new file mode 100644 index 000000000000..a78afe32278c --- /dev/null +++ b/qcom/sa6155p-v2-adp-air-lpass.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P v2 LPASS Audio PLL sourced + from eMAC PPO ADP-Air"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x04010019 0>; +}; + diff --git a/qcom/sa6155p-v2-adp-air-overlay.dts b/qcom/sa6155p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..c86c51cf35ae --- /dev/null +++ b/qcom/sa6155p-v2-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03020019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-air.dts b/qcom/sa6155p-v2-adp-air.dts new file mode 100644 index 000000000000..d2ef4583c69a --- /dev/null +++ b/qcom/sa6155p-v2-adp-air.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x03020019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-star-overlay.dts b/qcom/sa6155p-v2-adp-star-overlay.dts new file mode 100644 index 000000000000..238de97a680d --- /dev/null +++ b/qcom/sa6155p-v2-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x020019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-star.dts b/qcom/sa6155p-v2-adp-star.dts new file mode 100644 index 000000000000..dffd3c18d374 --- /dev/null +++ b/qcom/sa6155p-v2-adp-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x020019 0>; +}; diff --git a/qcom/sa6155p.dts b/qcom/sa6155p.dts new file mode 100644 index 000000000000..d689543fd75c --- /dev/null +++ b/qcom/sa6155p.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "sa6155p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P SoC"; + compatible = "qcom,sa6155p"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi new file mode 100644 index 000000000000..b77b5f81a3d5 --- /dev/null +++ b/qcom/sa6155p.dtsi @@ -0,0 +1,7 @@ +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P"; + qcom,msm-name = "SA6155P"; + qcom,msm-id = <377 0>, <380 0>; +}; diff --git a/qcom/sm6150-qupv3.dtsi b/qcom/sm6150-qupv3.dtsi new file mode 100644 index 000000000000..fba310e3e2eb --- /dev/null +++ b/qcom/sm6150-qupv3.dtsi @@ -0,0 +1,18 @@ + +&soc { + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x008c0000 0x6000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + qupv3_se0_2uart: qcom,qup_uart@0x880000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + status = "ok"; + }; + }; +}; diff --git a/qcom/sm6150.dts b/qcom/sm6150.dts new file mode 100644 index 000000000000..77363a3a064e --- /dev/null +++ b/qcom/sm6150.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 SoC"; + compatible = "qcom,sm6150"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi new file mode 100644 index 000000000000..c205367f4f57 --- /dev/null +++ b/qcom/sm6150.dtsi @@ -0,0 +1,682 @@ +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SM6150"; + compatible = "qcom,sm6150"; + qcom,msm-name = "SM6150"; + qcom,msm-id = <355 0x0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { + serial0 = &qupv3_se0_2uart; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_0: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_100>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_100: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_200>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_200: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_300>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_300: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_400>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_400: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_500>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_500: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x10000>; + next-level-cache = <&L2_600>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_600: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_600: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_600: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x10000>; + next-level-cache = <&L2_700>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_700: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_700: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_700: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + }; + + soc: soc { }; + + firmware: firmware { + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@85fff000 { + no-map; + reg = <0x0 0x85fff000 0x0 0x1000>; + }; + + smem_region: smem@86000000 { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_region: removed_region@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x2d00000>; + }; + + pil_camera_mem: camera_region@8ab00000 { + no-map; + reg = <0x0 0x8ab00000 0x0 0x500000>; + }; + + pil_modem_mem: modem_region@8b000000 { + no-map; + reg = <0x0 0x8b000000 0x0 0x8400000>; + }; + + pil_video_mem: pil_video_region@93400000 { + no-map; + reg = <0x0 0x93400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@93900000 { + no-map; + reg = <0x0 0x93900000 0x0 0x200000>; + }; + + pil_cdsp_mem: cdsp_regions@93b00000 { + no-map; + reg = <0x0 0x93b00000 0x0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@95900000 { + no-map; + reg = <0x0 0x95900000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@0x97700000 { + no-map; + reg = <0x0 0x97700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@0x97710000 { + no-map; + reg = <0x0 0x97710000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@0x97715000 { + no-map; + reg = <0x0 0x97715000 0x0 0x2000>; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { + no-map; + reg = <0x0 0x9f800000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + cont_splash_memory: cont_splash_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x0f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@9cf00000 { + reg = <0x0 0x9cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01000000>; + label = "disp_rdump_region"; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@0xc221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm6150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; + + system_pm { + compatible = "qcom,system-pm"; + }; + }; +}; + +#include "sm6150-qupv3.dtsi" diff --git a/qcom/sm6150p.dts b/qcom/sm6150p.dts new file mode 100644 index 000000000000..b870d0579282 --- /dev/null +++ b/qcom/sm6150p.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sm6150p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P SoC"; + compatible = "qcom,sm6150p"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sm6150p.dtsi b/qcom/sm6150p.dtsi new file mode 100644 index 000000000000..9899d9049b16 --- /dev/null +++ b/qcom/sm6150p.dtsi @@ -0,0 +1,7 @@ +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P"; + qcom,msm-name = "SM6150P"; + qcom,msm-id = <369 0>; +}; From 010106479672bea9fad9df6f4929d84abb9bf8a1 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 11 Dec 2020 16:55:51 -0800 Subject: [PATCH 0461/1809] ARM: dts: msm: Remove test devices for sdxlemur v1 This functionality is not supported on v1 hardware. Change-Id: I885d67d76316650da73adb592371fd0cb1af6b0a --- qcom/msm-arm-smmu-sdxlemur.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/msm-arm-smmu-sdxlemur.dtsi b/qcom/msm-arm-smmu-sdxlemur.dtsi index d173665338c3..3a9d9a4535b8 100644 --- a/qcom/msm-arm-smmu-sdxlemur.dtsi +++ b/qcom/msm-arm-smmu-sdxlemur.dtsi @@ -75,12 +75,14 @@ }; apps_iommu_test_device { + status = "disabled"; compatible = "iommu-debug-test"; iommus = <&apps_smmu 0x100 0>; qcom,iommu-dma = "disabled"; }; apps_iommu_coherent_test_device { + status = "disabled"; compatible = "iommu-debug-test"; iommus = <&apps_smmu 0x101 0>; qcom,iommu-dma = "disabled"; From 980006a2d149b8bb84651ab6d03e6552b2816337 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 9 Dec 2020 15:58:53 +0530 Subject: [PATCH 0462/1809] bindings: interconnect: Update OSM L3 Update the bindings document with proper data. Change-Id: Ia42bbe70c08777f570615c4c509b607a5e334f83 --- bindings/interconnect/qcom,osm-l3.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt index 4d323fd7750b..a50f0018e2fd 100644 --- a/bindings/interconnect/qcom,osm-l3.txt +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -1,7 +1,7 @@ -Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +Qualcomm Technologies, Inc. OSM L3 interconnect driver binding ----------------------------------------------------------- -The EPSS L3 Interconnect provider supports the scaling of L3 cache +The OSM L3 Interconnect provider supports the scaling of L3 cache performance states of the CPU subsystem. Required properties : From 7bdc7e540027c7f108e1641a920f1d6b9f3823a7 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 9 Dec 2020 11:45:20 +0530 Subject: [PATCH 0463/1809] Revert "ARM: dts: msm: add initial support for hw memlat devices" This reverts commit 690d106d3d544e9c979c8b33135f934a446d23df. Change-Id: I609e6b4623854f49c3fa4605ee1614437130072a --- qcom/holi.dtsi | 272 ++++++++++++++++++++++++++++++------------------- 1 file changed, 168 insertions(+), 104 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e82cea81e542..4f2eedcbb8f4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -247,20 +247,6 @@ }; soc: soc { }; - - sram: sram@fd04480 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x0 0x0fd04480 0x0 0x80>; - ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scp-shmem"; - reg = <0x0 0x0 0x0 0x80>; - }; - }; }; &firmware { @@ -1338,6 +1324,66 @@ qcom,count-unit = <0x10000>; }; + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; + }; + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devfreq-icc"; governor = "compute"; @@ -1354,6 +1400,26 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; + }; + cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -1370,10 +1436,78 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; @@ -1402,6 +1536,26 @@ compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU6 &CPU7>; + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; @@ -1428,96 +1582,6 @@ }; }; - rimps: qcom,rimps@0f400000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "qcom,rimps"; - reg = <0x0f400000 0x10>, - <0x0fd90000 0x2000>; - #mbox-cells = <1>; - interrupts = <0 22 4>; - }; - - cpu0_grp: qcom,cpu0_grp { - compatible = "qcom,rimps-memlat-cpugrp"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xfd04580 0x280>; - reg-names = "pmu-base"; - - cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { - compatible = "qcom,rimps-memlat-mon-l3"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,cachemiss-ev = <0x17>; - reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; - reg-names = "ftbl-base", "perf-base"; - - qcom,core-dev-table = - < 710400 300000000 >, - < 940800 518400000 >, - < 1190400 748800000 >, - < 1478400 921600000 >, - < 1574400 1305600000 >, - < 1804800 1459000000 >; - }; - }; - - cpu6_grp: qcom,cpu6_grp { - compatible = "qcom,rimps-memlat-cpugrp"; - qcom,cpulist = <&CPU6 &CPU7>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xfd04580 0x280>; - reg-names = "pmu-base"; - - cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { - compatible = "qcom,rimps-memlat-mon-l3"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,cachemiss-ev = <0x17>; - qcom,wb-ev = <0x18>; - qcom,access-ev = <0x2B>; - reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; - reg-names = "ftbl-base", "perf-base"; - - qcom,core-dev-table = - < 1017600 518400000 >, - < 1248000 748800000 >, - < 1536000 921600000 >, - < 1651200 1171200000 >, - < 1804800 1305600000 >, - < 2035200 1459000000 >; - }; - }; - - scmi: qcom,scmi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,scmi"; - mboxes = <&rimps 0>; - mbox-names = "tx"; - shmem = <&cpu_scp_lpri>; - - scmi_memlat: protocol@80 { - reg = <0x80>; - #clock-cells = <1>; - }; - - scmi_perf_lock: protocol@81 { - reg = <0x81>; - #clock-cells = <1>; - }; - }; - - rimps_log: qcom,rimps_log@fd04780 { - compatible = "qcom,rimps-log"; - reg = <0x0fd04800 0x200>, - <0x0fd04A00 0x200>; - mboxes = <&rimps 1>; - }; - tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; From 40a825752d94fd32de6b427b0f0c3bc07f42e857 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 3 Sep 2020 17:20:22 +0530 Subject: [PATCH 0464/1809] dt-bindings: interconnect: update OSM L3 bindings Add bindings for the sm6150 and scshrike osm l3 driver. Change-Id: I5b5f37dc2eee08a2cf693a4c5bd73a58c80f241d --- bindings/interconnect/qcom,osm-l3.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt index a50f0018e2fd..82ea64a41455 100644 --- a/bindings/interconnect/qcom,osm-l3.txt +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -8,6 +8,8 @@ Required properties : - compatible : shall contain only one of the following: "qcom,sdm845-osm-l3", "qcom,sm8150-osm-l3"; + "qcom,sm6150-osm-l3"; + "qcom,scshrike-osm-l3"; - reg : Address and length of the register set for the device - clock-names: should contain "xo", "alternate" - clocks: list of phandle and clock specifier pairs corresponding to From d67d8d60a22e29fc432412f1b68babb8cabe271a Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 9 Dec 2020 17:37:54 +0530 Subject: [PATCH 0465/1809] ARM: dts: msm: Enable qcedev and qcrypto on olympic Add dts entries for qcedev and qcrypto modules on olympic target. Change-Id: Iffd514a3246409416cc53d87d31176e31a9bdf7c --- qcom/sdxlemur.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index dbecd245a777..1c329f137b86 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1203,6 +1203,48 @@ thermal_zones: thermal-zones { }; + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0066 0x0011>, + <&apps_smmu 0x0076 0x0011>; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0064 0x0011>, + <&apps_smmu 0x0074 0x0011>; + }; + qcom,rmtfs_sharedmem@0 { compatible = "qcom,sharedmem-uio"; reg = <0x0 0x400000>; From 53d71d92f27dabb1958585c5357fe7b0b7e61aa3 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 11 Dec 2020 16:40:37 +0530 Subject: [PATCH 0466/1809] ARM: dts: qcom: Add second trip to xo-therm userspace rule for lahaina There are two clients in userspace who can request different trip thresholds to xo-therm. Add another thermal zone trip node to xo-therm for second client to configure its own threshold. Change-Id: I16cbd65e5ca7955df9cf4e68f91e9cb3411eade5 --- qcom/lahaina-pmic-overlay.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 5bb23e5950e5..7146731f2773 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -605,6 +605,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; From af7a6a85330431664c6a85bd1a0957f0a2a8e22f Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Mon, 14 Dec 2020 18:47:57 +0530 Subject: [PATCH 0467/1809] ARM: dts: msm: Add SPS node for monaco Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for monaco. Change-Id: Iba0cd7c441792157e8513b17ab3b03647d640047 --- qcom/monaco.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 27dbb3c6e971..2edd89d9e90b 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -383,6 +383,11 @@ qcom,wakeup-enable; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; From 671c95b49d17eb4d5fa5be93dcfab714adb948e6 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 14 Dec 2020 13:23:36 -0800 Subject: [PATCH 0468/1809] ARM: dts: msm: Update ddr variant for all sdxlemur 512mb variants Updated the ddr variant for all sdxlemur 512mb variants. Change-Id: I800974193eab05431a4c8ca412aa1baf0e0adfd5 --- qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 2 +- qcom/sdxlemur-rcm-pcie-ep.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts index 5bfbf5417937..ef5c1f24cad7 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x4010008 0x304>; + qcom,board-id = <0x4010008 0x204>; }; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts index a43e055fbad9..788509431064 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dts +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x1010015 0x301>; + qcom,board-id = <0x1010015 0x201>; }; From 03f962b4611a947cba1fe6a92e65d961ef3fcb7c Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 14 Dec 2020 17:38:24 -0800 Subject: [PATCH 0469/1809] ARM: dts: msm: Enable USB bus suspend functionality on sdxlemur This change set "snps,bus-suspend-enable" property with USB controller's node which allows putting USB device into low power mode on receiving USB bus suspend interrupt in USB device mode. Change-Id: Id7d25ae1e37972b2bf15b62ca063ee0ff2febc40 --- qcom/sdxlemur-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index baa7270ff5c1..99b9aebb2a91 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -63,6 +63,7 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; snps,usb3-u1u2-disable; + snps,bus-suspend-enable; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; From 25538987f7d687255b454be887728a05f637b493 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 30 Nov 2020 13:14:07 +0530 Subject: [PATCH 0470/1809] ARM: dts: msm: Enable download/restart mode drivers for Yupik Enable new download/restart mode drivers for Yupik SoC. Change-Id: If580f2040013962db29ae94e235ce7e72d58b6d0 --- qcom/yupik-pmic-overlay.dtsi | 8 ++++++++ qcom/yupik.dtsi | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index e15564e25061..654d66696222 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -448,3 +448,11 @@ io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; io-channel-names = "thermal"; }; + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 4c7225f15669..00c229d266c6 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -34,6 +34,7 @@ firmware: firmware { scm { compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; }; android { compatible = "android,firmware"; @@ -842,6 +843,10 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; + dload_mode { + compatible = "qcom,dload-mode"; + }; + kryo-erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , From 8c9d54bc96b31d28b2d8dcba8f52966bd982b2a8 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 25 Nov 2020 10:16:48 +0530 Subject: [PATCH 0471/1809] ARM: dts: msm: Add audio dtsi changes for yupik Add audio related dtsi files for yupik. Change-Id: I65bff7b78f8a0e25c790df7cd888097f387c6d9e --- qcom/yupik-audio-overlay.dtsi | 476 ++++++++++ qcom/yupik-audio.dtsi | 272 ++++++ qcom/yupik-lpi.dtsi | 1679 +++++++++++++++++++++++++++++++++ qcom/yupik-pinctrl.dtsi | 1197 +++++++++++++++++++++++ qcom/yupik.dtsi | 4 + 5 files changed, 3628 insertions(+) create mode 100644 qcom/yupik-audio-overlay.dtsi create mode 100644 qcom/yupik-audio.dtsi create mode 100644 qcom/yupik-lpi.dtsi diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi new file mode 100644 index 000000000000..3fabb9a34729 --- /dev/null +++ b/qcom/yupik-audio-overlay.dtsi @@ -0,0 +1,476 @@ +#include +#include +#include +#include + +&bolero { + qcom,num-macros = <4>; + qcom,bolero-version = <4>; + #address-cells = <1>; + #size-cells = <1>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; + qcom,rx_mclk_mode_muxsel = <0x033240D8>; + qcom,wsa_mclk_mode_muxsel = <0x033220D8>; + qcom,va_mclk_mode_muxsel = <0x033A0000>; + clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", + "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk"; + clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, + <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, + <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>, + <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; + }; + + va_macro: va-macro@3370000 { + compatible = "qcom,va-macro"; + reg = <0x3370000 0x0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,va-vdd-micb-voltage = <1800000 1800000>; + qcom,va-vdd-micb-current = <11200>; + qcom,va-dmic-sample-rate = <600000>; + qcom,default-clk-id = ; + qcom,is-used-swr-gpio = <0>; + }; + + tx_macro: tx-macro@3220000 { + compatible = "qcom,tx-macro"; + reg = <0x3220000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-swr-gpios = <&tx_swr_gpios>; + qcom,tx-dmic-sample-rate = <2400000>; + qcom,disable-afe-wakeup-event-listener = <1>; + swr2: tx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <3>; + qcom,swrm-hctl-reg = <0x032a90a8>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x3230000 0x0>; + interrupts-extended = + <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + qcom,swr-num-ports = <3>; + qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>, + <1 SWRM_TX1_CH2 0x2>, + <1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>, + <2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>, + <2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>, + <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, + <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-mstr-irq-wakeup-capable = <1>; + wcd938x_tx_slave: wcd938x-tx-slave { + status = "disabled"; + compatible = "qcom,wcd938x-slave"; + reg = <0x0D 0x01170223>; + }; + + wcd937x_tx_slave: wcd937x-tx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0A 0x01170223>; + }; + + }; + }; + + rx_macro: rx-macro@3200000 { + compatible = "qcom,rx-macro"; + reg = <0x3200000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x033240D8>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>; + qcom,default-clk-id = ; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <2>; + qcom,swrm-hctl-reg = <0x032a90a0>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x3210000 0x0>; + interrupts = ; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <6>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>, <6 PCM_OUT1 0x01>; + qcom,swr-num-dev = <2>; + qcom,swr-clock-stop-mode0 = <1>; + swr_haptics: swr_haptics@f0170220 { + compatible = "qcom,pm8350b-swr-haptics"; + reg = <0x01 0xf0170220>; + swr-slave-supply = <&hap_swr_slave_reg>; + qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>; + }; + + wcd938x_rx_slave: wcd938x-rx-slave { + status = "disabled"; + compatible = "qcom,wcd938x-slave"; + reg = <0x0D 0x01170224>; + }; + + wcd937x_rx_slave: wcd937x-rx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0A 0x01170224>; + }; + }; + }; + + wsa_macro: wsa-macro@3240000 { + compatible = "qcom,wsa-macro"; + reg = <0x3240000 0x0>; + clock-names = "wsa_core_clk", "wsa_npl_clk"; + clocks = <&clock_audio_wsa_1 0>, + <&clock_audio_wsa_2 0>; + qcom,wsa-swr-gpios = <&wsa_swr_gpios>; + qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>; + qcom,default-clk-id = ; + swr0: wsa_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <1>; + qcom,swrm-hctl-reg = <0x032a90b0>; + qcom,mipi-sdw-block-packing-mode = <0>; + swrm-io-base = <0x3250000 0x0>; + interrupts = ; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <8>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr-num-dev = <2>; + qcom,dynamic-port-map-supported = <0>; + wsa883x_0221: wsa883x@02170221 { + compatible = "qcom,wsa883x"; + reg = <0x2 0x2170221>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + qcom,bolero-handle = <&bolero>; + + cdc-vdd-1p8-supply = <&L18B>; + qcom,cdc-vdd-1p8-voltage = <1800000 1800000>; + qcom,cdc-vdd-1p8-current = <20000>; + qcom,cdc-static-supplies = "cdc-vdd-1p8"; + qcom,wsa-prefix = "SpkrLeft"; + }; + + wsa883x_0222: wsa883x@02170222 { + compatible = "qcom,wsa883x"; + reg = <0x2 0x2170222>; + qcom,spkr-sd-n-node = <&wsa_spkr_en2>; + qcom,bolero-handle = <&bolero>; + + cdc-vdd-1p8-supply = <&L18B>; + qcom,cdc-vdd-1p8-voltage = <1800000 1800000>; + qcom,cdc-vdd-1p8-current = <20000>; + qcom,cdc-static-supplies = "cdc-vdd-1p8"; + qcom,wsa-prefix = "SpkrRight"; + }; + }; + }; + + wcd937x_codec: wcd937x-codec { + compatible = "qcom,wcd937x-codec"; + qcom,split-codec = <1>; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, + <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, + <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, + <4 DSD_R 0x2 0 DSD_R>; + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>, + <1 ADC2 0x1 0 SWRM_TX2_CH1>, + <1 ADC3 0x2 0 SWRM_TX2_CH2>, + <2 DMIC0 0x1 0 SWRM_TX1_CH4>, + <2 DMIC1 0x2 0 SWRM_TX2_CH1>, + <2 MBHC 0x4 0 SWRM_TX2_CH2>, + <3 DMIC2 0x1 0 SWRM_TX2_CH3>, + <3 DMIC3 0x2 0 SWRM_TX2_CH4>, + <3 DMIC4 0x4 0 SWRM_TX3_CH1>, + <3 DMIC5 0x8 0 SWRM_TX3_CH2>; + + qcom,wcd-rst-gpio-node = <&wcd93xx_rst_gpio>; + qcom,rx-slave = <&wcd937x_rx_slave>; + qcom,tx-slave = <&wcd937x_tx_slave>; + + cdc-vdd-rxtx-supply = <&L18B>; + qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; + qcom,cdc-vdd-rxtx-current = <30000>; + + cdc-vddpx-supply = <&L18B>; + qcom,cdc-vddpx-voltage = <1800000 1800000>; + qcom,cdc-vddpx-current = <30000>; + + cdc-vdd-buck-supply = <&L17B>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <600000>; + + cdc-vdd-mic-bias-supply = <&BOB>; + qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; + qcom,cdc-vdd-mic-bias-current = <45000>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx", + "cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; + }; + + wcd938x_codec: wcd938x-codec { + status = "disabled"; + compatible = "qcom,wcd938x-codec"; + qcom,split-codec = <1>; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, + <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, + <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, + <4 DSD_R 0x2 0 DSD_R>; + + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>, + <0 ADC2 0x2 0 SWRM_TX1_CH2>, + <1 ADC3 0x1 0 SWRM_TX2_CH1>, + <1 ADC4 0x2 0 SWRM_TX2_CH2>, + <2 DMIC0 0x1 0 SWRM_TX1_CH3>, + <2 DMIC1 0x2 0 SWRM_TX1_CH4>, + <2 MBHC 0x4 0 SWRM_TX2_CH3>, + <2 DMIC2 0x4 0 SWRM_TX2_CH3>, + <2 DMIC3 0x8 0 SWRM_TX2_CH4>, + <3 DMIC4 0x1 0 SWRM_TX3_CH1>, + <3 DMIC5 0x2 0 SWRM_TX3_CH2>, + <3 DMIC6 0x4 0 SWRM_TX3_CH3>, + <3 DMIC7 0x8 0 SWRM_TX3_CH4>; + + qcom,wcd-rst-gpio-node = <&wcd93xx_rst_gpio>; + qcom,rx-slave = <&wcd938x_rx_slave>; + qcom,tx-slave = <&wcd938x_tx_slave>; + + cdc-vdd-rxtx-supply = <&L18B>; + qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; + qcom,cdc-vdd-rxtx-current = <30000>; + + cdc-vddpx-supply = <&L18B>; + qcom,cdc-vddpx-voltage = <1800000 1800000>; + qcom,cdc-vddpx-current = <30000>; + + cdc-vdd-buck-supply = <&L17B>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <600000>; + + cdc-vdd-mic-bias-supply = <&BOB>; + qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; + qcom,cdc-vdd-mic-bias-current = <30000>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx", + "cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; + }; + +}; + +&yupik_snd { + qcom,model = "lahaina-yupikidp-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>; + qcom,tdm-max-slots = <8>; + qcom,wcd-disabled = <0>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS1", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS3", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS1", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS1", + "TX DMIC4", "Digital Mic4", + "TX DMIC4", "MIC BIAS1", + "TX DMIC5", "Digital Mic5", + "TX DMIC5", "MIC BIAS1", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC4", "VA MIC BIAS1", + "VA DMIC5", "VA MIC BIAS1"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,swr-dmic-max-devs = <0>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd937x_codec>, <&swr_haptics>, + <&wsa883x_0221>, <&wsa883x_0222>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd937x_codec", "swr-haptics", + "wsa-codec1", "wsa-codec2"; + qcom,wsa-max-devs = <2>; + qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; + qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>; + qcom,cps_threshold_levels = <148 168>; + qcom,cps_normal_values = <0x8E 0x8F 0x8F>; + qcom,cps_lower1_values = <0x10 0xD0 0xD0>; + qcom,cps_lower2_values = <0x0F 0x0F 0x18>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; + +&soc { + wsa_spkr_en1: wsa_spkr_en1_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_en2: wsa_spkr_en2_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + + wcd93xx_rst_gpio: msm_cdc_pinctrl@83 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd93xx_reset_active>; + pinctrl-1 = <&wcd93xx_reset_sleep>; + }; + + clock_audio_wsa_1: wsa_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x309>; + #clock-cells = <1>; + }; + + clock_audio_wsa_2: wsa_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30A>; + #clock-cells = <1>; + }; + + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + clock_audio_va_1: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30B>; + #clock-cells = <1>; + }; + + clock_audio_va_2: va_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x310>; + #clock-cells = <1>; + }; +}; + diff --git a/qcom/yupik-audio.dtsi b/qcom/yupik-audio.dtsi new file mode 100644 index 000000000000..7092fd185013 --- /dev/null +++ b/qcom/yupik-audio.dtsi @@ -0,0 +1,272 @@ +#include +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + iommus = <&apps_smmu 0x1801 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&audio_apr { + msm_audio_ion_cma: qcom,msm-audio-ion-cma { + compatible = "qcom,msm-audio-ion-cma"; + }; + + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + #address-cells = <1>; + #size-cells = <1>; + lpass_core_hw_vote: vote_lpass_core_hw { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; + + lpass_audio_hw_vote: vote_lpass_audio_hw { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; + + lpi_tlmm: lpi_pinctrl@33c0000 { + compatible = "qcom,lpi-pinctrl"; + reg = <0x33c0000 0x0>; + qcom,slew-reg = <0x355a000 0x0>; + qcom,gpios-count = <15>; + gpio-controller; + #gpio-cells = <2>; + qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>, + <0x00002000>, <0x00003000>, + <0x00004000>, <0x00005000>, + <0x00006000>, <0x00007000>, + <0x00008000>, <0x00009000>, + <0x0000A000>, <0x0000B000>, + <0x0000C000>, <0x0000D000>, + <0x0000E000>; + qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, + <0x00000004>, <0x00000008>, + <0x0000000A>, <0x0000000C>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000010>, <0x00000012>, + <0x00000000>, <0x00000000>, + <0x00000006>; + + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@3370000 { + }; + + tx_macro: tx-macro@3220000 { + swr2: tx_swr_master { + }; + }; + + rx_macro: rx-macro@3200000 { + swr1: rx_swr_master { + }; + }; + + wsa_macro: wsa-macro@3240000 { + swr0: wsa_swr_master { + }; + }; + }; + }; +}; + +#include "yupik-lpi.dtsi" + +&q6core { + wsa_swr_gpios: wsa_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>; + pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <155>; + #gpio-cells = <0>; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active + &rx_swr_data1_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep + &rx_swr_data1_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <148>; + #gpio-cells = <0>; + }; + + tx_swr_gpios: tx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active + &tx_swr_data1_active &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep + &tx_swr_data1_sleep &tx_swr_data2_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <145 158>; + #gpio-cells = <0>; + }; + + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <150 151>; + #gpio-cells = <0>; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <153>; + #gpio-cells = <0>; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + qcom,tlmm-pins = <156 157>; + #gpio-cells = <0>; + }; +}; + +&q6core { + yupik_snd: sound { + compatible = "qcom,lahaina-asoc-snd"; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,wcn-bt = <0>; + qcom,ext-disp-audio-rx = <0>; + qcom,afe-rxtx-lb = <0>; + + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_dp>, <&dai_dp1>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&dai_sen_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&afe_proxy_tx_1>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>, + <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, + <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, + <&wsa_cdc_dma_2_tx>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.242", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945", + "msm-dai-cdc-dma-dev.45056", + "msm-dai-cdc-dma-dev.45057", + "msm-dai-cdc-dma-dev.45058", + "msm-dai-cdc-dma-dev.45059", + "msm-dai-cdc-dma-dev.45061", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + }; +}; diff --git a/qcom/yupik-lpi.dtsi b/qcom/yupik-lpi.dtsi new file mode 100644 index 000000000000..a5714d6f05e2 --- /dev/null +++ b/qcom/yupik-lpi.dtsi @@ -0,0 +1,1679 @@ +&lpi_tlmm { + quat_mi2s_sck { + quat_mi2s_sck_sleep: quat_mi2s_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sck_active: quat_mi2s_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_ws { + quat_mi2s_ws_sleep: quat_mi2s_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_ws_active: quat_mi2s_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sck { + lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sck_active: lpi_i2s1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_ws { + lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_ws_active: lpi_i2s1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd0 { + lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd0_active: lpi_i2s1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd1 { + lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd1_active: lpi_i2s1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sck { + lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sck_active: lpi_i2s2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_ws { + lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_ws_active: lpi_i2s2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sd0 { + lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sd0_active: lpi_i2s2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sd1 { + lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sd1_active: lpi_i2s2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sck { + quat_tdm_sck_sleep: quat_tdm_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sck_active: quat_tdm_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_ws { + quat_tdm_ws_sleep: quat_tdm_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_ws_active: quat_tdm_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd0 { + quat_tdm_sd0_sleep: quat_tdm_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd0_active: quat_tdm_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd1 { + quat_tdm_sd1_sleep: quat_tdm_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd1_active: quat_tdm_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd2 { + quat_tdm_sd2_sleep: quat_tdm_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd2_active: quat_tdm_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd3 { + quat_tdm_sd3_sleep: quat_tdm_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd3_active: quat_tdm_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sck { + lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sck_active: lpi_tdm1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_ws { + lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_ws_active: lpi_tdm1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sd0 { + lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sd0_active: lpi_tdm1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sd1 { + lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sd1_active: lpi_tdm1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sck { + lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sck_active: lpi_tdm2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_ws { + lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_ws_active: lpi_tdm2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sd0 { + lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sd0_active: lpi_tdm2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sd1 { + lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sd1_active: lpi_tdm2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sck { + quat_aux_sck_sleep: quat_aux_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sck_active: quat_aux_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_ws { + quat_aux_ws_sleep: quat_aux_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_ws_active: quat_aux_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd0 { + quat_aux_sd0_sleep: quat_aux_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd0_active: quat_aux_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd1 { + quat_aux_sd1_sleep: quat_aux_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd1_active: quat_aux_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd2 { + quat_aux_sd2_sleep: quat_aux_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd2_active: quat_aux_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd3 { + quat_aux_sd3_sleep: quat_aux_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd3_active: quat_aux_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sck { + lpi_aux1_sck_sleep: lpi_aux1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sck_active: lpi_aux1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_ws { + lpi_aux1_ws_sleep: lpi_aux1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_ws_active: lpi_aux1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sd0 { + lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sd0_active: lpi_aux1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sd1 { + lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sd1_active: lpi_aux1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sck { + lpi_aux2_sck_sleep: lpi_aux2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sck_active: lpi_aux2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_ws { + lpi_aux2_ws_sleep: lpi_aux2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_ws_active: lpi_aux2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sd0 { + lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sd0_active: lpi_aux2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sd1 { + lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sd1_active: lpi_aux2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio10"; + function = "func2"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio10"; + function = "func2"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio11"; + function = "func2"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio11"; + function = "func2"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + + tx_swr_clk_sleep: tx_swr_clk_sleep { + mux { + pins = "gpio0"; + function = "func1"; + input-enable; + bias-pull-down; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + }; + }; + + tx_swr_clk_active: tx_swr_clk_active { + mux { + pins = "gpio0"; + function = "func1"; + }; + + config { + pins = "gpio0"; + drive-strength = <4>; + slew-rate = <1>; + bias-disable; + }; + }; + + tx_swr_data0_sleep: tx_swr_data0_sleep { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + input-enable; + bias-bus-hold; + }; + }; + + tx_swr_data0_active: tx_swr_data0_active { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <4>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_data1_sleep: tx_swr_data1_sleep { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + tx_swr_data1_active: tx_swr_data1_active { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <4>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_data2_sleep: tx_swr_data2_sleep { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + tx_swr_data2_active: tx_swr_data2_active { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <4>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_clk_sleep: rx_swr_clk_sleep { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_clk_active: rx_swr_clk_active { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + }; + + rx_swr_data_sleep: rx_swr_data_sleep { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_data_active: rx_swr_data_active { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_data1_sleep: rx_swr_data1_sleep { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_data1_active: rx_swr_data1_active { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic23_clk_active: dmic23_clk_active { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic23_clk_sleep: dmic23_clk_sleep { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic23_data_active: dmic23_data_active { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic23_data_sleep: dmic23_data_sleep { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic45_clk_active: dmic45_clk_active { + mux { + pins = "gpio12"; + function = "func1"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic45_clk_sleep: dmic45_clk_sleep { + mux { + pins = "gpio12"; + function = "func1"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic45_data_active: dmic45_data_active { + mux { + pins = "gpio13"; + function = "func1"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic45_data_sleep: dmic45_data_sleep { + mux { + pins = "gpio13"; + function = "func1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; +}; diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 5c51c0efa182..23c867f78890 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1143,5 +1143,1202 @@ }; }; }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd93xx_reset_active: wcd93xx_reset_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + output-high; + }; + }; + + wcd93xx_reset_sleep: wcd93xx_reset_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio100"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_clk_sleep: sec_aux_pcm_clk_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_clk_active: sec_aux_pcm_clk_active { + mux { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + sec_aux_pcm_ws_sleep: sec_aux_pcm_ws_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_ws_active: sec_aux_pcm_ws_active { + mux { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio105"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_clk_active: tert_aux_pcm_clk_active { + mux { + pins = "gpio101"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + + tert_aux_pcm_ws_sleep: tert_aux_pcm_ws_sleep { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_ws_active: tert_aux_pcm_ws_active { + mux { + pins = "gpio103"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio103"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio102"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio102"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio104"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio104"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio100"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm { + sec_tdm_sck_sleep: sec_tdm_sck_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_sck_active: sec_tdm_sck_active { + mux { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + sec_tdm_ws_sleep: sec_tdm_ws_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_ws_active: sec_tdm_ws_active { + mux { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio105"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_clk_sleep: tert_tdm_clk_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_clk_active: tert_tdm_clk_active { + mux { + pins = "gpio101"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + + tert_tdm_ws_sleep: tert_tdm_ws_sleep { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_ws_active: tert_tdm_ws_active { + mux { + pins = "gpio103"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio103"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio102"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio102"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio104"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio104"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio96"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio100"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio105"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_sck { + sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sck_active: sec_mi2s_sck_active { + mux { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_ws { + sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_ws_active: sec_mi2s_ws_active { + mux { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio105"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sck { + tert_mi2s_sck_sleep: tert_mi2s_sck_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sck_active: tert_mi2s_sck_active { + mux { + pins = "gpio101"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_ws { + tert_mi2s_ws_sleep: tert_mi2s_ws_sleep { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_ws_active: tert_mi2s_ws_active { + mux { + pins = "gpio103"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio103"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio102"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio102"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio104"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio104"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 4c7225f15669..e4e3588f5a7b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -29,6 +29,9 @@ ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ sdhc1 = &sdhc_2; /* SDC2 SD card slot */ + swr0 = &swr0; + swr1 = &swr1; + swr2 = &swr2; }; firmware: firmware { @@ -1787,3 +1790,4 @@ #include "yupik-ion.dtsi" #include "msm-arm-smmu-yupik.dtsi" #include "yupik-qupv3.dtsi" +#include "yupik-audio.dtsi" From f09c4d256c49ade898c248f89b4883735051b3d6 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 15 Dec 2020 18:28:08 +0530 Subject: [PATCH 0472/1809] ARM: dts: msm: Update drive strength values for sdc1 node on shima Getting CRC errors for some eMMC devices on shima. So use the VI recommended drive strength values for sdc1 node. Change-Id: I86ff6acaf12156cf1bc0c885acc62814606e32eb --- qcom/shima-pinctrl.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 5e2c03340973..672784ffdbdd 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -1550,19 +1550,19 @@ clk { pins = "sdc1_clk"; bias-disable; - drive-strength = <16>; + drive-strength = <12>; }; cmd { pins = "sdc1_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <12>; }; data { pins = "sdc1_data"; bias-pull-up; - drive-strength = <10>; + drive-strength = <12>; }; rclk { From 30893f414dc4e82faf8ea5e1b9689afe2989dc00 Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Fri, 23 Oct 2020 11:40:35 +0530 Subject: [PATCH 0473/1809] ARM: dts: msm: Add venus pil node for Yupik Add venus pil node to load venus subsystem for Yupik. Change-Id: Ib00af73b7f3cd12092fd4316c2f9eeb279bcefee --- qcom/yupik.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 16cbd231d5f8..7f2ef82e8057 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -644,6 +644,31 @@ #reset-cells = <1>; }; + qcom,venus@aab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaab0000 0x2000>; + + vdd-supply = <&video_cc_mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>; + clock-names = "core", "ahb"; + qcom,proxy-clock-names = "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; reg-names = "phy_mem"; From 8125711557445d7a5e6eccfa496f8450b78f07ed Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 11 Dec 2020 16:24:33 -0800 Subject: [PATCH 0474/1809] ARM: dts: msm: Revised emmc device tree and added to makefile Revised the emmc device tree, added it to the makefile, and disabled nand on emmc devices. Change-Id: I995c871ae4c390420322c59fdac5170bd3dec93e --- qcom/Makefile | 1 + qcom/sdxlemur-mtp-mbb-emmc.dts | 4 ++-- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/Makefile b/qcom/Makefile index 793a51038a7f..edf2a8fca33e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -209,6 +209,7 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-mtp-cpe.dtb \ + sdxlemur-mtp-mbb-emmc.dtb \ sdxlemur-mtp-mbb-ntn3-pcie.dtb \ sdxlemur-mtp-mbb-pcie-ep.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts index 1fcd14c01d1f..8b5774a69767 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -1,4 +1,4 @@ -/dts v1/; +/dts-v1/; #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-emmc.dtsi" @@ -9,5 +9,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x2010108 0x302> + qcom,board-id = <0x2010108 0x302>; }; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 0e75a90da2b4..7d4753791231 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -13,7 +13,6 @@ bus-width = <8>; non-removable; - supports-cqe; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; From 19d978502b746a9fa860689e7b8b2c746484d822 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 16 Dec 2020 00:10:31 +0530 Subject: [PATCH 0475/1809] ARM: dts: qcom: Add second trip to quiet-therm userspace rule for SHIMA There are two clients in userspace who can request different trip thresholds to quiet-therm. Add another thermal zone trip node to quiet-therm for second client to configure its own threshold. Change-Id: Ie8f5d6fbb08644f9eb99b7361c6424ecb54f55a8 --- qcom/shima-pmic-overlay.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index 437a1088620a..3869c2791578 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -250,6 +250,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; From c1846e805a6df07ff879f6f82722997e6f6e401d Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 24 Nov 2020 16:53:25 +0530 Subject: [PATCH 0476/1809] ARM: dts: msm: Update VideoCC node and Multimedia GDSC's for YUPIK Update VideoCC clock node and GDSC's of Camera, Display and Video clock controllers to real from dummy. Change-Id: I8a413d13a0b0406af09c8a38251dd4192bdf0676 --- qcom/yupik-rumi.dtsi | 4 ++++ qcom/yupik.dtsi | 45 +++++++++++++++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 11 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 9ef144149b00..c4b5ffdcba88 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -174,3 +174,7 @@ clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; }; + +&videocc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 2dae0b2503d4..768db173d15a 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -663,8 +663,13 @@ }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,yupik-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1827,41 +1832,55 @@ }; &cam_cc_titan_top_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; reg = <0xad0c194 0x4>; status = "ok"; }; &cam_cc_bps_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &cam_cc_ife_0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_1_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_2_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ipe_0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &disp_cc_mdss_core_gdsc { - compatible = "regulator-fixed"; reg = <0xaf01004 0x4>; + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; @@ -1884,14 +1903,18 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; reg = <0xaaf3004 0x4>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &video_cc_mvsc_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; From 6a940e847d5aa37c47de5d2c534cdce304396112 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Thu, 11 Jun 2020 10:03:48 +0800 Subject: [PATCH 0477/1809] ARM: dts: msm: Add initial device tree for Quin virtual machine Add initial device tree for SA8155 Quin virtual machine. Change-Id: I1728cb9593e1232d362e67dd6291f5c77ec38340 --- qcom/Makefile | 5 + qcom/quin-vm-common.dtsi | 182 +++++++++++++++++++++++++++++++++++ qcom/sa8155-vm-la-mt.dts | 11 +++ qcom/sa8155-vm-la-mt.dtsi | 6 ++ qcom/sa8155-vm-la.dts | 11 +++ qcom/sa8155-vm-la.dtsi | 6 ++ qcom/sa8155-vm-lv-mt.dts | 11 +++ qcom/sa8155-vm-lv-mt.dtsi | 6 ++ qcom/sa8155-vm-lv.dts | 11 +++ qcom/sa8155-vm-lv.dtsi | 6 ++ qcom/sa8155-vm.dtsi | 196 ++++++++++++++++++++++++++++++++++++++ 11 files changed, 451 insertions(+) create mode 100644 qcom/quin-vm-common.dtsi create mode 100644 qcom/sa8155-vm-la-mt.dts create mode 100644 qcom/sa8155-vm-la-mt.dtsi create mode 100644 qcom/sa8155-vm-la.dts create mode 100644 qcom/sa8155-vm-la.dtsi create mode 100644 qcom/sa8155-vm-lv-mt.dts create mode 100644 qcom/sa8155-vm-lv-mt.dtsi create mode 100644 qcom/sa8155-vm-lv.dts create mode 100644 qcom/sa8155-vm-lv.dtsi create mode 100644 qcom/sa8155-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index f33d75c4c022..a5593e0a6a67 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -242,6 +242,11 @@ dtb-$(CONFIG_ARCH_QTI_VM) += yupik-vm-rumi.dtb \ endif endif +dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ + sa8155-vm-lv.dtb \ + sa8155-vm-la-mt.dtb \ + sa8155-vm-lv-mt.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi new file mode 100644 index 000000000000..a8993b0c00a1 --- /dev/null +++ b/qcom/quin-vm-common.dtsi @@ -0,0 +1,182 @@ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket"; + }; + + soc: soc { }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "ok"; + }; + }; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: vgic@0 { + qvm,vdev = "gic"; + }; + + dummycc: qcom,dummycc { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: virtio_clock@1c200000 { + compatible = "virtio,mmio"; + reg = <0x1c200000 0x1000>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: virtio_clock@1c300000 { + compatible = "virtio,mmio"; + reg = <0x1c300000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + regulator: virtio_regulator@1c700000 { + compatible = "virtio,mmio"; + reg = <0x1c700000 0x1000>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; + }; + + msm_ion: qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; + + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x14680000 0x1000>; + ranges = <0x0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,mpm2-sleep-counter@0xc221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; +}; diff --git a/qcom/sa8155-vm-la-mt.dts b/qcom/sa8155-vm-la-mt.dts new file mode 100644 index 000000000000..156d1895f826 --- /dev/null +++ b/qcom/sa8155-vm-la-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8155-vm.dtsi" +#include "sa8155-vm-la-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Multi LA Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0x2000001 0>; +}; diff --git a/qcom/sa8155-vm-la-mt.dtsi b/qcom/sa8155-vm-la-mt.dtsi new file mode 100644 index 000000000000..63e1d6eabba3 --- /dev/null +++ b/qcom/sa8155-vm-la-mt.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x2c200000 0x0 0x53e00000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8155-vm-la.dts b/qcom/sa8155-vm-la.dts new file mode 100644 index 000000000000..7ca0c92eb6f2 --- /dev/null +++ b/qcom/sa8155-vm-la.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8155-vm.dtsi" +#include "sa8155-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Single LA Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi new file mode 100644 index 000000000000..c38dc4de64e2 --- /dev/null +++ b/qcom/sa8155-vm-la.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x6a500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8155-vm-lv-mt.dts b/qcom/sa8155-vm-lv-mt.dts new file mode 100644 index 000000000000..7798a82c5c47 --- /dev/null +++ b/qcom/sa8155-vm-lv-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8155-vm.dtsi" +#include "sa8155-vm-lv-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Multi LV Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0x2000002 0>; +}; diff --git a/qcom/sa8155-vm-lv-mt.dtsi b/qcom/sa8155-vm-lv-mt.dtsi new file mode 100644 index 000000000000..63e1d6eabba3 --- /dev/null +++ b/qcom/sa8155-vm-lv-mt.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x2c200000 0x0 0x53e00000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8155-vm-lv.dts b/qcom/sa8155-vm-lv.dts new file mode 100644 index 000000000000..d7b7655d2720 --- /dev/null +++ b/qcom/sa8155-vm-lv.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8155-vm.dtsi" +#include "sa8155-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Single LV Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0x1000002 0>; +}; diff --git a/qcom/sa8155-vm-lv.dtsi b/qcom/sa8155-vm-lv.dtsi new file mode 100644 index 000000000000..c38dc4de64e2 --- /dev/null +++ b/qcom/sa8155-vm-lv.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x6a500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi new file mode 100644 index 000000000000..6c89f083c055 --- /dev/null +++ b/qcom/sa8155-vm.dtsi @@ -0,0 +1,196 @@ +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + qcom,msm-name = "SA8155 V2"; + qcom,msm-id = <362 0x20000>; +}; + + +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + +®ulator { + usb30_prim_gdsc: usb30_prim_gdsc { + regulator-name = "usb30_prim_gdsc"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + regulator-name = "usb30_sec_gdsc"; + }; + + pcie_0_gdsc: pcie_0_gdsc { + regulator-name = "pcie_0_gdsc"; + }; + + pcie_1_gdsc: pcie_1_gdsc { + regulator-name = "pcie_1_gdsc"; + }; + + L2A: pm8150_1_l2: regulator-pm8150-1-l2 { + regulator-name = "ldoa2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + }; + + L5A: pm8150_1_l5: regulator-pm8150-1-l5 { + regulator-name = "ldoa5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + L12A: pm8150_1_l12: regulator-pm8150-1-l12 { + regulator-name = "ldoa12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + L17A: pm8150_1_l17: regulator-pm8150-1-l17 { + regulator-name = "ldoa17"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + }; + + L8C: pm8150_2_l8: regulator-pm8150-2-l8 { + regulator-name = "ldoc8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + L13C: pm8150_2_l13: regulator-pm8150-2-l13 { + regulator-name = "ldoc13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + L15C: pm8150_2_l15: regulator-pm8150-2-l15 { + regulator-name = "ldoc15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + L18C: pm8150_2_l18: regulator-pm8150-2-l18 { + regulator-name = "ldoc18"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-allow-set-load; + }; + + S6A: pm8150_1_s6: regulator-pm8150-1-s6 { + regulator-name = "smpa6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1352000>; + }; + + S4C: pm8150_2_s4: regulator-pm8150-2-s4 { + regulator-name = "smpc4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; + + S5C: pm8150_2_s5: regulator-pm8150-2-s5 { + regulator-name = "smpc5"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + }; +}; From 91248cad3a8490e2ec3a6d37e31b7379a438f2c3 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 16 Dec 2020 19:55:31 +0530 Subject: [PATCH 0478/1809] ARM: dts: msm: Update interrupt configuration for sdxnightjar Update interrupt configuration for spmi_bus for interrupts for all peripherals. Change-Id: I47f0836b75fb290e9285aba9d47ac8047d6c5899 --- qcom/sdxnightjar.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 3a68cdedc7f0..898954ff6e0a 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -593,11 +593,10 @@ <0x3800000 0x200000>, <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupts = <0 190 0>; + interrupt-names = "periph_irq"; + interrupts = ; qcom,channel = <0>; qcom,ee = <0>; - qcom,pmic-arb-max-peripherals = <256>; - qcom,pmic-arb-max-periph-interrupts = <256>; #interrupt-cells = <4>; interrupt-controller; #address-cells = <2>; From affa46ac8c27aad2bfec50503f792ab55a6c1416 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Tue, 15 Dec 2020 17:47:39 +0530 Subject: [PATCH 0479/1809] ARM: dts: qcom: Add slimbus dtsi node for monaco Add slimbus dtsi node for monaco. Change-Id: Idcc7052b8193d08f133d189527c65a8ffe380860 --- qcom/monaco.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 27dbb3c6e971..d889153eb44b 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -554,6 +554,21 @@ #interrupt-cells = <4>; cell-index = <0>; }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical", "slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x3f0>; + status = "ok"; + }; }; #include "monaco-pinctrl.dtsi" From ee17ea5be706b522ca48047d69955d03c0273990 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 6 Nov 2020 09:23:45 +0530 Subject: [PATCH 0480/1809] arm64: dts: qcom: sm8150: Add cpufreq HW device node Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs. Change-Id: I37fe076fbcc66b04183939ef555381f02825f387 Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20191219120633.20723-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson Git-commit: fea8930bd55e6d88e43ce44cd058aee3b85de274 Git-repo: https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next [vvegivad@codeaurora.org: minor modifications needed to handle as per cpufreq-hw driver] Signed-off-by: Veera Vegivada --- qcom/sm8150.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index dc15e677873c..28a139213f08 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -42,6 +42,7 @@ cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -76,6 +77,7 @@ cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -105,6 +107,7 @@ cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_2>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -134,6 +137,7 @@ cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_3>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -163,6 +167,7 @@ cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -201,6 +206,7 @@ cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -239,6 +245,7 @@ cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -277,6 +284,7 @@ cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 2 4>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -849,6 +857,20 @@ #clock-cells = <1>; }; + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>, + <0x18327800 0x1400>; + reg-names = "freq-domain0", "freq-domain1", + "freq-domain2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + + #freq-domain-cells = <2>; + }; + osm_l3: interconnect@0x18321000 { reg = <0x18321000 0x1400>; compatible = "qcom,sm8150-osm-l3"; From 12dee74ffc5cdd52dca24a2f0d162e54b82e1699 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Thu, 19 Nov 2020 14:02:56 +0530 Subject: [PATCH 0481/1809] ARM: dts: msm: Add the SMMU devices for SM8150 Add the set of devices that describe the APPS and graphics SMMU register spaces and various properties for SM8150. Change-Id: I149b53bbb2c36410df69a954dc246ccbc9350534 --- qcom/msm-arm-smmu-sm8150-v2.dtsi | 318 +++++++++++++++++++++++++++++ qcom/msm-arm-smmu-sm8150.dtsi | 332 +++++++++++++++++++++++++++++++ qcom/sm8150-v2.dtsi | 6 + qcom/sm8150.dtsi | 1 + 4 files changed, 657 insertions(+) create mode 100644 qcom/msm-arm-smmu-sm8150-v2.dtsi create mode 100644 qcom/msm-arm-smmu-sm8150.dtsi diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi new file mode 100644 index 000000000000..b694e0b014e8 --- /dev/null +++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -0,0 +1,318 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02ca0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02ca0000 0x10000>, + <0x2cc2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2cc5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2cc9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518d000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + /* No GDSC */ + qcom,active-only; + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + qcom,active-only; + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + + adsp_tbu: adsp_tbu@0x1519d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519d000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151a1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,opt-out-tbu-halting; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151a5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151a5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + qcom,iommu-dma = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x407 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF0 and HF1 TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>, + + /* SF TBU: +3 deep PF */ + <0x2000 0x3ff 0x103>, + + /* NPU SIDs: +15 deep PF */ + <0x1480 0x3 0x303>, + <0x1484 0x1 0x303>, + <0x1080 0x3 0x303>, + <0x1084 0x1 0x303>; +}; diff --git a/qcom/msm-arm-smmu-sm8150.dtsi b/qcom/msm-arm-smmu-sm8150.dtsi new file mode 100644 index 000000000000..f279e5a55d46 --- /dev/null +++ b/qcom/msm-arm-smmu-sm8150.dtsi @@ -0,0 +1,332 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02CA0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02CA0000 0x10000>, + <0x2CC2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + qcom,min-iova-align; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC5000 0x1000>, + <0x2CC2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC9000 0x1000>, + <0x2CC2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + qcom,min-iova-align; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518D000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + + adsp_tbu: adsp_tbu@0x1519D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519D000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,opt-out-tbu-halting; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + /* No GDSC */ + qcom,active-only; + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + qcom,iommu-dma = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x407 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* SIDs 0x1460 - 0x1463 of NPU: +3 deep PF */ + <0x1460 0x3 0x103>, + + /* SIDs 0x1464 - 0x1465 of NPU: +3 deep PF */ + <0x1464 0x1 0x103>, + + /* SIDs 0x2060 - 0x2063 of NPU: +3 deep PF */ + <0x2060 0x3 0x103>, + + /* SIDs 0x2064 - 0x2065 of NPU: +3 deep PF */ + <0x2064 0x1 0x103>, + + /* Display SIDs: +3 deep PF */ + <0x0800 0x0420 0x103>, + <0x0801 0x0420 0x103>, + <0x1040 0x0001 0x103>, + + /* Video SIDs: +3 deep PF */ + <0x1300 0x0060 0x103>, + <0x1301 0x0004 0x103>, + <0x1303 0x0020 0x103>, + <0x1304 0x0060 0x103>, + <0x1342 0x0000 0x103>; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index a7ec31ec4fa3..a6f26d35f304 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -6,6 +6,10 @@ qcom,msm-id = <339 0x20000>; }; +/* Remove smmu nodes specific to SM8150 */ +/delete-node/ &apps_smmu; +/delete-node/ &kgsl_smmu; + &gcc { compatible = "qcom,sm8150-gcc-v2", "syscon"; }; @@ -29,3 +33,5 @@ &scc { compatible = "qcom,sm8150-scc-v2", "syscon"; }; + +#include "msm-arm-smmu-sm8150-v2.dtsi" diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 28a139213f08..961e4e0fb6e2 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1505,6 +1505,7 @@ #include "sm8150-slpi-pinctrl.dtsi" #include "sm8150-smp2p.dtsi" #include "sm8150-gdsc.dtsi" +#include "msm-arm-smmu-sm8150.dtsi" &emac_gdsc { status = "ok"; From 2dc593d1e4e806a0fb8ff1e362a323f773cbeef0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sat, 18 Jul 2020 15:42:14 +0530 Subject: [PATCH 0482/1809] dt-bindings: interconnect: add interconnect bindings Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices for scshrike. Change-Id: I0db869169f33aa73a9fe4be376136b98215f17c9 --- bindings/interconnect/qcom,scshrike.txt | 31 +++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 bindings/interconnect/qcom,scshrike.txt diff --git a/bindings/interconnect/qcom,scshrike.txt b/bindings/interconnect/qcom,scshrike.txt new file mode 100644 index 000000000000..8ab12b107d8c --- /dev/null +++ b/bindings/interconnect/qcom,scshrike.txt @@ -0,0 +1,31 @@ +Qualcomm Technologies, Inc. SCSHRIKE Network-On-Chip interconnect driver binding +------------------------------------------------------------------------------ + +SCSHRIKE interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,scshrike-aggre1_noc"; + "qcom,scshrike-aggre2_noc"; + "qcom,scshrike-camnoc_virt"; + "qcom,scshrike-compute_noc"; + "qcom,scshrike-config_noc"; + "qcom,scshrike-dc_noc"; + "qcom,scshrike-gem_noc"; + "qcom,scshrike-ipa_virt"; + "qcom,scshrike-mc_virt"; + "qcom,scshrike-mmss_noc"; + "qcom,scshrike-system_noc"; +- #interconnect-cells : should contain 1 + +Examples: + +aggre1_noc: interconnect@16e0000 { + "qcom,scshrike-aggre1_noc"; + interconnect-cells = <1>; +}; From 00c55b977495c726850ed33439ce930eac875081 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 23 Jul 2020 08:46:12 +0530 Subject: [PATCH 0483/1809] dt-bindings: clocks: Add clock controller bindings for SCSHRIKE Add clock controller bindings to support SCSHRIKE. Change-Id: I1a650b8b13ce86c54c4e9685673b4a70d94b0242 --- bindings/clock/qcom,camcc.txt | 2 ++ bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 2 ++ bindings/clock/qcom,gcc.txt | 2 ++ bindings/clock/qcom,gpucc.txt | 1 + bindings/clock/qcom,scc.txt | 2 ++ 6 files changed, 10 insertions(+) diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index cc72c85575d0..9eaa2b3d7618 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -12,6 +12,8 @@ Required properties : "qcom,sa8155-camcc" "qcom,sa8155-camcc-v2" "qcom,yupik-camcc" + "qcom,scshrike-camcc" + "qcom,scshrike-camcc-v2" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index b6356b499bcb..4cc0522d7bdd 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-debugcc" "qcom,yupik-debugcc" "qcom,sdxnightjar-debugcc" + "qcom,scshrike-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index 8341e8b8c742..ebd301af54b7 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -12,6 +12,8 @@ Required properties : "qcom,sm8150-dispcc" "qcom,sm8150-dispcc-v2" "qcom,yupik-dispcc" + "qcom,scshrike-dispcc" + "qcom,scshrike-dispcc-v2" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 5c131248c402..e06b80ade895 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -33,6 +33,8 @@ Required properties : "qcom,sdxlemur-gcc" "qcom,yupik-gcc" "qcom,sdxnightjar-gcc" + "qcom,scshrike-gcc" + "qcom,scshrike-gcc-v2" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index efd611826979..46fe5bd2eb84 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,sm8150-gpucc" "qcom,sa8155-gpucc" "qcom,yupik-gpucc" + "qcom,scshrike-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,scc.txt b/bindings/clock/qcom,scc.txt index fce28e82ddb9..9794d7bf66ac 100644 --- a/bindings/clock/qcom,scc.txt +++ b/bindings/clock/qcom,scc.txt @@ -6,6 +6,8 @@ Required properties: "qcom,sm8150-scc-v2" "qcom,sa8155-scc" "qcom,sa8155-scc-v2" + "qcom,sa8195-scc" + "qcom,sa8195-scc-v2" - reg: shall contain base register location and length. - vdd_scc_cx-supply: the logic rail supply. From 96101caa9db8860ca1dca774caf2c63ca78f9e3a Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 12:01:36 +0530 Subject: [PATCH 0484/1809] ARM: dts: msm: Add RSC and cmd_db support for SDMSHRIKE Add apps_rsc, disp_rsc and cmd_db support. Change-Id: I301d33796caba4fe8ffd322389abef556dc8479f --- qcom/sdmshrike.dtsi | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index c1079ca2028a..c97dd9653df4 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -314,6 +314,12 @@ reg = <0x0 0x85ffd000 0x0 0x3000>; }; + aop_cmd_db: memory@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + smem_region: smem@86000000 { no-map; reg = <0x0 0x86000000 0x0 0x200000>; @@ -620,19 +626,32 @@ label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x18200000 0x10000>, - <0x18210000 0x10000>, - <0x18220000 0x10000>; + <0x18210000 0x10000>, + <0x18220000 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , - , - ; + , + ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , - , - , - ; + , + , + ; + }; + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; }; qupv3_id_1: geniqup@ac0000 { From 2cbc4b940ec70c5664f243c9dc9f5101153d50c6 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 11:41:36 +0530 Subject: [PATCH 0485/1809] ARM: dts: msm: Add regulators for SDMSHRIKE Add rpmh and refgen regulators for sdmshrike. Change-Id: I9d303e66fc02da8888fc6565ff590dcf2b4b77c7 --- qcom/sa8195-pmic.dtsi | 62 +++ qcom/sa8195-regulator.dtsi | 882 ++++++++++++++++++++++++++++++++++++ qcom/sa8195p-regulator.dtsi | 768 +++++++++++++++++++++++++++++++ qcom/sa8195p.dtsi | 1 + qcom/sdmshrike.dtsi | 1 + 5 files changed, 1714 insertions(+) create mode 100644 qcom/sa8195-pmic.dtsi create mode 100644 qcom/sa8195-regulator.dtsi create mode 100644 qcom/sa8195p-regulator.dtsi diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi new file mode 100644 index 000000000000..db67174ef773 --- /dev/null +++ b/qcom/sa8195-pmic.dtsi @@ -0,0 +1,62 @@ +/* Remove regulator nodes specific to sdmshrike */ +&apps_rsc { + /* Logical rails */ + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-gfxlvl; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-mmcxlvl; + /delete-node/ rpmh-regulator-msslvl; + /delete-node/ rpmh-regulator-ebilvl; + + /* PM8150_1 regulators */ + /delete-node/ rpmh-regulator-smpa5; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-ldoa7; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-smpe4; + /delete-node/ rpmh-regulator-smpe5; + /delete-node/ rpmh-regulator-ldoe1; + /delete-node/ rpmh-regulator-ldoe2; + /delete-node/ rpmh-regulator-ldoe5; + /delete-node/ rpmh-regulator-ldoe7; + /delete-node/ rpmh-regulator-ldoe10; + /delete-node/ rpmh-regulator-ldoe13; + /delete-node/ rpmh-regulator-ldoe14; + /delete-node/ rpmh-regulator-ldoe15; + /delete-node/ rpmh-regulator-ldoe16; + /delete-node/ rpmh-regulator-ldoe17; + /delete-node/ rpmh-regulator-smpc6; + /delete-node/ rpmh-regulator-smpc7; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; +}; + +&soc { + /* Stub regulators */ + /delete-node/ regulator-pm8150_1-s4; + + /* refgen-regulator@88e7000 */ + /delete-node/ refgen; +}; + +#include "sa8195p-regulator.dtsi" diff --git a/qcom/sa8195-regulator.dtsi b/qcom/sa8195-regulator.dtsi new file mode 100644 index 000000000000..4317499b6ade --- /dev/null +++ b/qcom/sa8195-regulator.dtsi @@ -0,0 +1,882 @@ +#include + +&apps_rsc { + /* PM8150_1 regulators */ + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa5"; + S5A: pm8150_1_s5: regulator-pm8150_1-s5 { + regulator-name = "pm8150_1_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + /* PM8150_1 S10 + S9 + S8 + S7 + S6 = VDD_GFX */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: + S10A_LEVEL: pm8150_1_s10_level: regulator-pm8150_1-s10-level { + regulator-name = "pm8150_1_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L3A: pm8150_1_l3: regulator-pm8150_1-l3 { + regulator-name = "pm8150_1_l3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm8150_1_l5: regulator-pm8150_1-l5 { + regulator-name = "pm8150_1_l5"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6A: pm8150_1_l6: regulator-pm8150_1-l6 { + regulator-name = "pm8150_1_l6"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm8150_1_l7: regulator-pm8150_1-l7 { + regulator-name = "pm8150_1_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm8150_1_l9: regulator-pm8150_1-l9 { + regulator-name = "pm8150_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11A: pm8150_1_l11: regulator-pm8150_1-l11 { + regulator-name = "pm8150_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8150_1_l12: regulator-pm8150_1-l12 { + regulator-name = "pm8150_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L12A_AO: pm8150_1_l12_ao: regulator-pm8150_1-l12-ao { + regulator-name = "pm8150_1_l12_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + regulator-pm8150_1-l12-so { + regulator-name = "pm8150_1_l12_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8150_1_l13: regulator-pm8150_1-l13 { + regulator-name = "pm8150_1_l13"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8150_1_l15: regulator-pm8150_1-l15 { + regulator-name = "pm8150_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8150_1_l16: regulator-pm8150_1-l16 { + regulator-name = "pm8150_1_l16"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm8150_1_l18: regulator-pm8150_1-l18 { + regulator-name = "pm8150_1_l18"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + /* PM8150_2 regulators */ + /* PM8150_2 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + pm8150_2_s3_level-parent-supply = <&VDD_MX_LEVEL>; + pm8150_2_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: S3E_LEVEL: + pm8150_2_s3_level: regulator-pm8150_2-s3-level { + regulator-name = "pm8150_2_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3E_LEVEL_AO: + pm8150_2_s3_level_ao: regulator-pm8150_2-s3-level-ao { + regulator-name = "pm8150_2_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe4"; + S4E: pm8150_2_s4: regulator-pm8150_2-s4 { + regulator-name = "pm8150_2_s4"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <752000>; + }; + }; + + rpmh-regulator-smpe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe5"; + S5E: pm8150_2_s5: regulator-pm8150_2-s5 { + regulator-name = "pm8150_2_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1E: pm8150_2_l1: regulator-pm8150_2-l1 { + regulator-name = "pm8150_2_l1"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2E: pm8150_2_l2: regulator-pm8150_2-l2 { + regulator-name = "pm8150_2_l2"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + L4E_LEVEL: pm8150_2_l4_level: regulator-pm8150_2-l4-level { + regulator-name = "pm8150_2_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5E: pm8150_2_l5: regulator-pm8150_2-l5 { + regulator-name = "pm8150_2_l5"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L5E_AO: pm8150_2_l5_ao: regulator-pm8150_2-l5-ao { + regulator-name = "pm8150_2_l5_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm8150_2-l5-so { + regulator-name = "pm8150_2_l5_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7E: pm8150_2_l7: regulator-pm8150_2-l7 { + regulator-name = "pm8150_2_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + L8E_LEVEL: pm8150_2_l8_level: regulator-pm8150_2-l8-level { + regulator-name = "pm8150_2_l8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10E: pm8150_2_l10: regulator-pm8150_2-l10 { + regulator-name = "pm8150_2_l10"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13E: pm8150_2_l13: regulator-pm8150_2-l13 { + regulator-name = "pm8150_2_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14E: pm8150_2_l14: regulator-pm8150_2-l14 { + regulator-name = "pm8150_2_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L15E: pm8150_2_l15: regulator-pm8150_2-l15 { + regulator-name = "pm8150_2_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16E: pm8150_2_l16: regulator-pm8150_2-l16 { + regulator-name = "pm8150_2_l16"; + qcom,set = ; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L17E: pm8150_2_l17: regulator-pm8150_2-l17 { + regulator-name = "pm8150_2_l17"; + qcom,set = ; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2960000>; + qcom,init-mode = ; + }; + }; + + /* PM8150C regulators */ + + /* PM8150C S1 = VDD_MMCX supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mmcx.lvl"; + + VDD_MMCX_LEVEL: + S1C_LEVEL: pm8150c_s1_level: regulator-pm8150c-s1-level { + regulator-name = "pm8150c_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MMCX_LEVEL_AO: S1C_LEVEL_AO: + pm8150c_s1_level_ao: regulator-pm8150c-s1-level-ao { + regulator-name = "pm8150c_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150C S2 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + S2C_LEVEL: pm8150c_s2_level: regulator-pm8150c-s2-level { + regulator-name = "pm8150c_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150C S3 + S4 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: S3C_LEVEL: + pm8150c_s3_level: regulator-pm8150c-s3-level { + regulator-name = "pm8150c_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S3C_LEVEL_AO: + pm8150c_s3_level_ao: regulator-pm8150c-s3-level-ao { + regulator-name = "pm8150c_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150C S5 = VDDA_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + S5C_LEVEL: pm8150c_s5_level: regulator-pm8150c-s5-level { + regulator-name = "pm8150c_s5_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-smpc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc6"; + S6C: pm8150c_s6: regulator-pm8150c-s6 { + regulator-name = "pm8150c-s6"; + qcom,set = ; + regulator-min-microvolt = <1260000>; + regulator-max-microvolt = <1396000>; + qcom,init-voltage = <1260000>; + }; + }; + + rpmh-regulator-smpc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc7"; + S7C: pm8150c_s7: regulator-pm8150c-s7 { + regulator-name = "pm8150c-s7"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "smpc8"; + S8C: pm8150c_s8: regulator-pm8150c-s8 { + regulator-name = "pm8150c_s8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "ldoc1"; + L1C: pm8150c_l1: regulator-pm8150c-l1 { + regulator-name = "pm8150c_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2C: pm8150c_l2: regulator-pm8150c-l2 { + regulator-name = "pm8150c_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3C: pm8150c_l3: regulator-pm8150c-l3 { + regulator-name = "pm8150c_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm8150c_l4: regulator-pm8150c-l4 { + regulator-name = "pm8150c_l4"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C: pm8150c_l6: regulator-pm8150c-l6 { + regulator-name = "pm8150c_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8150c_l7: regulator-pm8150c-l7 { + regulator-name = "pm8150c_l7"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "ldoc8"; + L8C: pm8150c_l8: regulator-pm8150c-l8 { + regulator-name = "pm8150c_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L9C: pm8150c_l9: regulator-pm8150c-l9 { + regulator-name = "pm8150c_l9"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10C: pm8150c_l10: regulator-pm8150c-l10 { + regulator-name = "pm8150c_l10"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm8150c_l11: regulator-pm8150c-l11 { + regulator-name = "pm8150c_l11"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,send-defaults; + + BOB: pm8150c_bob: regulator-pm8150c-bob { + regulator-name = "pm8150c_bob"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + + BOB_AO: pm8150c_bob_ao: regulator-pm8150c-bob-ao { + regulator-name = "pm8150c_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; +}; + +&soc { + /* Stub regulators */ + + /* + * RPMh does not provide support for PM8150_1 S4. Therefore, + * use a stub regulator for S4. + */ + S4A: pm8150_1_s4: regulator-pm8150_1-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_1_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-regulator"; + reg = <0x88e7000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; +}; diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi new file mode 100644 index 000000000000..5d480a9a464b --- /dev/null +++ b/qcom/sa8195p-regulator.dtsi @@ -0,0 +1,768 @@ +#include + +&apps_rsc { + + /* PM8195_1 S1 = VDD_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + S1A_LEVEL: pm8195_1_s1_level: regulator-pm8195-1-s1-level { + regulator-name = "pm8195_1_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8195_1 S2 = VDDCX_MM supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mmcx.lvl"; + + VDD_MMCX_LEVEL: + S7A_LEVEL: pm8195_1_s7_level: regulator-pm8195-1-s7-level { + regulator-name = "pm8195_1_s7_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MMCX_LEVEL_AO: S7A_LEVEL_AO: + pm8195_1_s7_level_ao: regulator-pm8195-1-s7-level-ao { + regulator-name = "pm8195_1_s7_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-smpa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa3"; + S3A: pm8195_1_s3: regulator-pm8195-1-s3 { + regulator-name = "pm8195_1_s3"; + qcom,set = ; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <969000>; + qcom,init-voltage = <788000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa5"; + S5A: pm8195_1_s5: regulator-pm8195-1-s5 { + regulator-name = "pm8195_1_s5"; + qcom,set = ; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <900000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa6"; + S6A: pm8195_1_s6: regulator-pm8195-1-s6 { + regulator-name = "pm8195_1_s6"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa2"; + S2A: pm8195_1_s2: regulator-pm8195-1-s2 { + regulator-name = "pm8195_1_s2"; + qcom,set = ; + regulator-min-microvolt = <1179000>; + regulator-max-microvolt = <1379000>; + qcom,init-voltage = <1179000>; + }; + }; + + /* pm8195_1 S8 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MSS_LEVEL: + S8A_LEVEL: pm8195_1_s8_level: regulator-pm8195-1-s8-level { + regulator-name = "pm8195_1_s8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8195_1 S10 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S10A_LEVEL: pm8195_1_s10_level: regulator-pm8195-1-s10-level { + regulator-name = "pm8195_1_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S10A_LEVEL_AO: + pm8195_1_s10_level_ao: regulator-pm8195-1-s10-level-ao { + regulator-name = "pm8195_1_s10_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm8195_1_l2: regulator-pm8195-1-l2 { + regulator-name = "pm8195_1_l2"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm8195_1_l3: regulator-pm8195-1-l3 { + regulator-name = "pm8195_1_l3"; + qcom,set = ; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <816000>; + qcom,init-voltage = <760000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm8195_1_l5: regulator-pm8195-1-l5 { + regulator-name = "pm8195_1_l5"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <720000>; + qcom,init-mode = ; + }; + }; + + /* DSI display 1.2 */ + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm8195_1_l9: regulator-pm8195-1-l9 { + regulator-name = "pm8195_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm8195_1_l10: regulator-pm8195-1-l10 { + regulator-name = "pm8195_1_l10"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm8195_1_l11: regulator-pm8195-1-l11 { + regulator-name = "pm8195_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8195_1_l12: regulator-pm8195-1-l12 { + regulator-name = "pm8195_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + regulator-always-on; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8195_1_l13: regulator-pm8195-1-l13 { + regulator-name = "pm8195_1_l13"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8195_1_l15: regulator-pm8195-1-l15 { + regulator-name = "pm8195_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1751000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8195_1_l16: regulator-pm8195-1-l16 { + regulator-name = "pm8195_1_l16"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm8195_1_l17: regulator-pm8195-1-l17 { + regulator-name = "pm8195_1_l17"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm8195_1_l18: regulator-pm8195-1-l18 { + regulator-name = "pm8195_1_l18"; + qcom,set = ; + regulator-min-microvolt = <831000>; + regulator-max-microvolt = <918000>; + qcom,init-voltage = <831000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc1"; + S1C: pm8195_2_s1: regulator-pm8195-2-s1 { + regulator-name = "pm8195_2_s1"; + qcom,set = ; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <648000>; + qcom,init-voltage = <570000>; + }; + }; + + rpmh-regulator-smpc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc2"; + S2C: pm8195_2_s2: regulator-pm8195-2-s2 { + regulator-name = "pm8195_2_s2"; + qcom,set = ; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1060000>; + }; + }; + + rpmh-regulator-smpc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc4"; + S4C: pm8195_2_s4: regulator-pm8195-2-s4 { + regulator-name = "pm8195_2_s4"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1620000>; + }; + }; + + rpmh-regulator-smpc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc5"; + S5C: pm8195_2_s5: regulator-pm8195-2-s5 { + regulator-name = "pm8195_2_s5"; + qcom,set = ; + regulator-min-microvolt = <1713000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1713000>; + }; + }; + + /* PM8195_2 S10 + S9 + S8 + S7 + S6 = VDD_GFX supply */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX: + S10C_LEVEL: pm8195_2_s10_level: regulator-pm8195-2-s10-level { + regulator-name = "pm8195_2_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm8195_2_l2: regulator-pm8195-2-l2 { + regulator-name = "pm8195_2_l2"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3330000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm8195_2_l5: regulator-pm8195-2-l5 { + regulator-name = "pm8195_2_l5"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8195_2_l7: regulator-pm8195-2-l7 { + regulator-name = "pm8195_2_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10C: pm8195_2_l10: regulator-pm8195-2-l10 { + regulator-name = "pm8195_2_l10"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm8195_2_l11: regulator-pm8195-2-l11 { + regulator-name = "pm8195_2_l11"; + qcom,set = ; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1236000>; + qcom,init-voltage = <1144000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12C: pm8195_2_l12: regulator-pm8195-2-l12 { + regulator-name = "pm8195_2_l12"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + /* PM8195_3 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + pm8195_3_s3_level-parent-supply = <&VDD_MX_LEVEL>; + pm8195_3_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: + S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level { + regulator-name = "pm8195_3_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3E_LEVEL_AO: + pm8195_3_s3_level_ao: regulator-pm8195-3-s3-level-ao { + regulator-name = "pm8195_3_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe4"; + S4E: pm8195_3_s4: regulator-pm8195-3-s4 { + regulator-name = "pm8195_3_s4"; + qcom,set = ; + regulator-min-microvolt = <402000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <402000>; + }; + }; + + rpmh-regulator-smpe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe5"; + S5E: pm8195_3_s5: regulator-pm8195-3-s5 { + regulator-name = "pm8195_3_s5"; + qcom,set = ; + regulator-min-microvolt = <1811000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1811000>; + }; + }; + + /* PM8195_3 L4 - LPI_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + L4E_LEVEL: pm8195_3_l4_level: regulator-pm8195-3-l4 { + regulator-name = "pm8195_3_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5E: pm8195_3_l5: regulator-pm8195-3-l5 { + regulator-name = "pm8195_3_l5"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7E: pm8195_3_l7: regulator-pm8195-3-l7 { + regulator-name = "pm8195_3_l7"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + /* pm8195_3 L8 - LPI_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + VDD_SCC_CX_LEVEL: + L8E_LEVEL: pm8195_3_l8_level: regulator-pm8195-3-l8 { + regulator-name = "pm8195_3_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9E: pm8195_3_l9: regulator-pm8195-3-l9 { + regulator-name = "pm8195_3_l9"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <830000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10E: pm8195_3_l10: regulator-pm8195-3-l10 { + regulator-name = "pm8195_3_l10"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12E: pm8195_3_l12: regulator-pm8195-3-l12 { + regulator-name = "pm8195_3_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16E: pm8195_3_l16: regulator-pm8195-3-l16 { + regulator-name = "pm8195_3_l16"; + qcom,set = ; + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2921000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17E: pm8195_3_l17: regulator-pm8195-3-l17 { + regulator-name = "pm8195_3_l17"; + qcom,set = ; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2900000>; + qcom,init-mode = ; + }; + }; +}; + +&soc { + /* Stub regulator */ + /* + * RPMh does not provide support for PM8195 S4 because it is always-on + * at 1.8 V in auto mode. Therefore, use a stub regulator for S4. + */ + S4A: pm8195_s4: regulator-pm8195-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8195_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 0032ea7d78af..7fe00b0a2047 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -1,4 +1,5 @@ #include "sdmshrike-v2.dtsi" +#include "sa8195-pmic.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P"; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index c97dd9653df4..57ced1af6751 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -673,3 +673,4 @@ }; #include "sdmshrike-pinctrl.dtsi" +#include "sa8195-regulator.dtsi" From 83c782245516e00c6963bab97db33b055cd6367f Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 12:05:39 +0530 Subject: [PATCH 0486/1809] ARM: dts: msm: Add Power management nodes for SDMSHRIKE This change adds two items for power management. 1. Add PDC interrupt controller device. The interrupt map remains same as sm8150. Also mention PDC as wakeup parent for TLMM. 2. Include power management for sm8150 for APSS low power modes and various stats drivers. Change-Id: I3473f86bbaa3c289199d3ca88d0c31be5712f145 --- qcom/sdmshrike-pinctrl.dtsi | 11 ++++++++++- qcom/sdmshrike.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index e4af602e1c7a..c5e4ae02bc2f 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -3,11 +3,20 @@ compatible = "qcom,sdmshrike-pinctrl"; reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>; reg-names = "pinctrl", "spi_cfg"; - interrupts =; + interrupts = , + , + , + , + , + , + , + , + ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; ufs_dev_reset_assert: ufs_dev_reset_assert { config { diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 57ced1af6751..41fde14e63a1 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -500,6 +500,15 @@ interrupt-parent = <&intc>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, @@ -674,3 +683,4 @@ #include "sdmshrike-pinctrl.dtsi" #include "sa8195-regulator.dtsi" +#include "sm8150-pm.dtsi" From d9b4a91ec0b565f76efab14924077a5012676e6c Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 12:50:16 +0530 Subject: [PATCH 0487/1809] ARM: dts: msm: Add system_pm device for SDMSHRIKE system_pm device is required for system level low power modes. Change-Id: Ib65fc22d67218bc6584c6aec044d4b06e22d6acc --- qcom/sdmshrike.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 41fde14e63a1..a56b27af3d27 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -647,6 +647,10 @@ , , ; + + system_pm { + compatible = "qcom,system-pm"; + }; }; disp_rsc: rsc@af20000 { From 84f6405c27d56e753c01c31d9d529e6bd0bdcbf0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 17 Dec 2020 14:21:17 +0530 Subject: [PATCH 0488/1809] ARM: dts: msm: add PMIC devices for SM8150 Add top level SPMI slave devices for PM8150. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: Ia59d63861135913f5968050d88a5f8d5c63882df --- qcom/pm8150.dtsi | 164 +++++++++++++++++++++++++++++++++ qcom/sa8155-adp-common.dtsi | 2 + qcom/sa8155-pmic-overlay.dtsi | 169 ++++++++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 84 +++++++++++++++++ 4 files changed, 419 insertions(+) create mode 100644 qcom/pm8150.dtsi create mode 100644 qcom/sa8155-pmic-overlay.dtsi diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi new file mode 100644 index 000000000000..21683a4ecffb --- /dev/null +++ b/qcom/pm8150.dtsi @@ -0,0 +1,164 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8150_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8150_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm8150_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8150_div_clk1", + "pm8150_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150_rtc: qcom,pm8150_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8150_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8150_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100>; + }; + + pm8150_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8150_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>, + <&pm8150_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm8150_vadc ADC5_AMUX_THM2_100K_PU>; + }; + }; + + qcom,pm8150@1 { + compatible ="qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; + +&thermal_zones { + pm8150_temp_alarm: pm8150_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_tz>; + wake-capable-sensor; + + trips { + pm8150_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8150_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index fc99f15ac51c..b7e203419cc2 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -1,6 +1,8 @@ #include #include +#include "sa8155-pmic-overlay.dtsi" + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi new file mode 100644 index 000000000000..4c4fd12fe728 --- /dev/null +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -0,0 +1,169 @@ + +#include "pm8150.dtsi" + +pm8150_1_tz: &pm8150_tz { +}; + +pm8150_1_clkdiv: &pm8150_clkdiv { + clock-output-names = "pm8150_1_div_clk1", "pm8150_1_div_clk2"; +}; + +pm8150_1_rtc: &pm8150_rtc { +}; + +pm8150_1_gpios: &pm8150_gpios { +}; + +/* PM8150_2: */ +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8150@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8150_2_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8150_2_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8150_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8150_2_div_clk1", + "pm8150_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8150_2_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; + + qcom,pm8150@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMIC GPIO pin control configurations: */ +&pm8150_1_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; + +#include + +&thermal_zones { + pm8150_2_temp_alarm: pm8150_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_2_tz>; + wake-capable-sensor; + + trips { + pm8150_2_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8150_2_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + }; + +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 961e4e0fb6e2..b8e9208d6ec6 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. SM8150"; @@ -871,6 +873,88 @@ #freq-domain-cells = <2>; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + spmi_debug_bus: qcom,spmi-debug@6b22000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b22000 0x60>, <0x7820a8 0x4>; + reg-names = "core", "fuse"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + status = "disabled"; + + qcom,pm8150-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150l-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150l-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + thermal_zones: thermal-zones { + }; + osm_l3: interconnect@0x18321000 { reg = <0x18321000 0x1400>; compatible = "qcom,sm8150-osm-l3"; From f4ef7e13ed6af7c658bf57ce2e2059b394c8bfa9 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 17 Dec 2020 16:26:30 +0530 Subject: [PATCH 0489/1809] ARM: dts: msm: Update CAMCC clock node for YUPIK Update the camera clock controller node to real from dummmy. Change-Id: Ifbfa1ebca24e6e927a0c288a1c5037aadd3d6401 --- qcom/yupik-rumi.dtsi | 4 ++++ qcom/yupik.dtsi | 10 ++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index c4b5ffdcba88..59020d3960ef 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -178,3 +178,7 @@ &videocc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; }; + +&camcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 768db173d15a..1534acfa43fc 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -635,8 +635,14 @@ }; camcc: clock-controller@ad00000 { - compatible = "qcom,dummycc"; - clock-output-names = "camcc_clocks"; + compatible = "qcom,yupik-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; From 63cc4bfb06bdd08458a53934fe60168d6e6865ba Mon Sep 17 00:00:00 2001 From: himta ram Date: Tue, 15 Dec 2020 17:33:17 +0530 Subject: [PATCH 0490/1809] ARM: dts: msm: add the current load parameter for vdd reg Add the current load parameter for vdd regulator. CRs-Fixed: 2840578 Change-Id: I941ed7351d0230d9ec1493945f998baff2a9ae27 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 22919880f93c..5ddd3ae5c358 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -4089,6 +4089,7 @@ fmint-gpio = <&tlmm 50 0>; vdd-supply = <&L11C>; rtc6226,vdd-supply-voltage = <2800000 2800000>; + rtc6226,vdd-load = <30000>; vio-supply = <&S10B>; rtc6226,vio-supply-voltage = <1800000 1800000 >; }; From 0a8a024eeed4d87a189038d65cf9ad10d2082d7c Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Wed, 7 Oct 2020 13:59:57 +0530 Subject: [PATCH 0491/1809] ARM: dts: msm: Add video device for Yupik Add video device node for Yupik. Change-Id: Ife41f22b336f9d2baafb1cd15f7441b2514b884d --- qcom/yupik-vidc.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 97 insertions(+) create mode 100644 qcom/yupik-vidc.dtsi diff --git a/qcom/yupik-vidc.dtsi b/qcom/yupik-vidc.dtsi new file mode 100644 index 000000000000..8c207620b265 --- /dev/null +++ b/qcom/yupik-vidc.dtsi @@ -0,0 +1,96 @@ +&soc { + msm_vidc: qcom,vidc { + compatible = "qcom,msm-vidc", "qcom,yupik-vidc"; + status = "okay"; + reg = <0x0aa00000 0x0100000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvsc_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "video_cc_mvsc_ctl_axi", + "video_cc_mvs0_ctl_axi", "core_clk", + "vcodec_clk", "iface_clk"; + clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&videocc VIDEO_CC_MVS0_AXI_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>; + qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi", + "video_cc_mvs0_ctl_axi", "core_clk", + "vcodec_clk", "iface_clk"; + /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ + qcom,clock-configs = <0x0 0x0 0x1 0x1 0x0>; + qcom,allowed-clock-rates = <133330000 240000000 + 335000000 424000000 460000000>; + + qcom,reg-presets = <0xB0088 0x0 0x11>; + + /* Video Firmware ELF image name */ + vidc,firmware-name = "vpu20_1v"; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_VENUS_CFG>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 8000000>; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x2180 0x0020>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + #dma-coherent-hint-cached; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x2184 0x0020>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + buffer-types = <0x480>; + virtual-addr-pool = <0x01000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x2181 0x0004>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + buffer-types = <0x241>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x2183 0x0000>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + buffer-types = <0x106>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 28df86a51168..6dc78144f107 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1898,6 +1898,7 @@ status = "ok"; }; +#include "yupik-vidc.dtsi" #include "yupik-usb.dtsi" #include "yupik-ion.dtsi" #include "msm-arm-smmu-yupik.dtsi" From 6db1bb6ad4c0166fcd1fea2f91c60671af982e30 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 17 Dec 2020 17:33:41 +0530 Subject: [PATCH 0492/1809] ARM: dts: msm: Update clocks and clock-names of GCC node for YUPIK Update the clocks and clock-names of GCC node to have all GCC external clocks. Change-Id: I8b25e58fb59b7d93e95baa1cc5f15958231ad892 --- qcom/yupik-rumi.dtsi | 6 +++++- qcom/yupik.dtsi | 12 ++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 9ef144149b00..34e49bd40431 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -167,7 +167,11 @@ }; &gcc { - clocks = <&bi_tcxo>, <&sleep_clk>; + clocks = <&bi_tcxo>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gpucc { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 28df86a51168..ef8134229467 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -631,8 +631,16 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; - clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; From 61c4bfbba06fcf6a5f620faa910b412668fb1f5c Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Fri, 6 Nov 2020 14:56:09 +0530 Subject: [PATCH 0493/1809] ARM: dts: msm: add actlr settings for yupik Add ACTLR settings for SMMU on Yupik. Change-Id: I00c12b8b680ac4d30af42e6d6cea5a1a205d5ee1 --- qcom/msm-arm-smmu-yupik.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index a35d60de4a3c..f9dea0234c00 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -48,6 +48,10 @@ , ; + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x7ff 0x32B>; + gfx_0_tbu: gfx_0_tbu@3dd9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x3dd9000 0x1000>, @@ -161,6 +165,19 @@ , ; + qcom,actlr = + /* For Camera: Disable prefetch */ + <0x800 0x24E1 0x1>, + <0x2000 0x163 0x1>, + <0x2080 0x461 0x1>, + <0x2100 0x161 0x1>, + /* For Display: +3 deep PF */ + <0x900 0x407 0x103>, + /* For Video : +3 deep PF */ + <0x2180 0x27 0x103>, + /* For Compute: +15 deep PF */ + <0x1000 0x7ff 0x303>; + interconnects = <&gem_noc MASTER_APPSS_PROC &cnoc3 SLAVE_TCU>; qcom,active-only; From 45691e42a74eb4ab3c479cc10c7aff0eddf0b442 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 17 Dec 2020 21:15:56 +0530 Subject: [PATCH 0494/1809] ARM: dts: msm: Add wdi2 support for holi Add changes to enable support for WDI2.0 in holi target. Change-Id: I850237ee7e23b954a93094c56c8b095b6af2dfde --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e82cea81e542..22b9d482a5da 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -3162,6 +3162,7 @@ qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; qcom,ipa-wdi2_over_gsi; qcom,arm-smmu; qcom,use-64-bit-dma-mask; From 6e491c98be5b0717fe6aeb9adc9473074516029b Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 18 Dec 2020 10:35:26 +0530 Subject: [PATCH 0495/1809] ARM: dts: msm: Add ACD control register values for Shima GPU Add the dvm values to enable ACD support for all GPU power levels. Change-Id: If769d32e54c75d5d162ed0947da4d337c4785321 --- qcom/shima-gpu.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 84349ff83d3e..7f15e0a95637 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -157,6 +157,8 @@ qcom,bus-freq-ddr8 = <11>; qcom,bus-min-ddr8 = <10>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa8295ffd>; }; qcom,gpu-pwrlevel@1 { @@ -171,6 +173,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; }; qcom,gpu-pwrlevel@2 { @@ -185,6 +189,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; }; qcom,gpu-pwrlevel@3 { @@ -199,6 +205,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@4 { @@ -213,6 +221,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@5 { @@ -227,6 +237,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@6 { @@ -241,6 +253,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882f5ffd>; }; qcom,gpu-pwrlevel@7 { @@ -255,6 +269,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x882f5ffd>; }; }; @@ -277,6 +293,8 @@ qcom,bus-freq-ddr8 = <11>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@1 { @@ -291,6 +309,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@2 { @@ -305,6 +325,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882f5ffd>; }; qcom,gpu-pwrlevel@3 { @@ -319,6 +341,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x882f5ffd>; }; }; @@ -341,6 +365,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882f5ffd>; }; qcom,gpu-pwrlevel@1 { @@ -355,6 +381,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x882f5ffd>; }; }; @@ -377,6 +405,8 @@ qcom,bus-freq-ddr8 = <11>; qcom,bus-min-ddr8 = <10>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa8295ffd>; }; qcom,gpu-pwrlevel@1 { @@ -391,6 +421,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; }; qcom,gpu-pwrlevel@2 { @@ -405,6 +437,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; }; qcom,gpu-pwrlevel@3 { @@ -419,6 +453,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@4 { @@ -433,6 +469,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@5 { @@ -447,6 +485,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@6 { @@ -461,6 +501,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x882f5ffd>; }; qcom,gpu-pwrlevel@7 { @@ -475,6 +517,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x882f5ffd>; }; }; }; From 826b4dc9485d4264764ff744ed4a3a98f5dff5bc Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 17 Nov 2020 22:39:21 +0530 Subject: [PATCH 0496/1809] dt-bindings: interconnect: add interconnect bindings for SDXNIGHTJAR Add interconnect device bindings. These devices can be used to describe any RPM and NoC based interconnect devices. Change-Id: I434ab6ce6cdaa17a3d86d52920c6e7500720526d --- bindings/interconnect/qcom,sdxnightjar.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 bindings/interconnect/qcom,sdxnightjar.txt diff --git a/bindings/interconnect/qcom,sdxnightjar.txt b/bindings/interconnect/qcom,sdxnightjar.txt new file mode 100644 index 000000000000..72e19d5edae9 --- /dev/null +++ b/bindings/interconnect/qcom,sdxnightjar.txt @@ -0,0 +1,52 @@ +QTI SDXNIGHTJAR Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdxnightjar-bimc", + "qcom,sdxnightjar-pcnoc", + "qcom,sdxnightjar-snoc", +- #interconnect-cells : should contain 1 + +reg : specifies the physical base address and size of registers +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus" and "bus_a" + +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + +Examples: + +soc { + ... + system_noc: interconnect@580000 { + reg = <0x580000 0x14000>; + compatible = "qcom,sdxnightjar-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>, + }; + + pc_noc: interconnect@500000{ + reg = <0x500000 0x11000>; + compatible = "qcom,sdxnightjar-pcnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + bimc: interconnect@400000{ + reg = <0x400000 0x62000>; + compatible = "qcom,sdxnightjar-bimc"; + qcom,util-factor = <153>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; +}; From 7404db6771fb8a106cf3888a7977582449640a00 Mon Sep 17 00:00:00 2001 From: Pranav Patel Date: Fri, 18 Dec 2020 19:19:48 +0530 Subject: [PATCH 0497/1809] ARM: dts: msm: Add apb_pclk to GMU clock list for Lahaina apb_pclk is required to access QDSS registers. GMU need to add vote before access can be made. Change-Id: I36f27809824f1b3d09dd55f19080e9f40edb692a --- qcom/lahaina-gpu.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 1fc038a7f72a..ceb8de50a6ba 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -270,10 +270,11 @@ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, - <&clock_gpucc GPU_CC_HUB_CX_INT_CLK>; + <&clock_gpucc GPU_CC_HUB_CX_INT_CLK>, + <&clock_aop QDSS_CLK>; clock-names = "gmu_clk", "cxo_clk", "axi_clk", - "memnoc_clk", "ahb_clk", "hub_clk"; + "memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; From 346600cdb3f41fe3de6dedac7f6b35f14d96fc24 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 18 Dec 2020 18:28:22 +0530 Subject: [PATCH 0498/1809] ARM: dts: msm: Update power source for PM8350C GPIOs for yupik Update power source for PM8350C GPIOs 3 and 4 to ensure correct GPIO configuration is applied for PM8008 reset. Change-Id: If157c295b2c35861b31cc368f2a7cf3af20cb6ac --- qcom/yupik-pmic-overlay.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index e15564e25061..b14cf9a3d053 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -25,7 +25,7 @@ function = "normal"; bias-disable; output-high; - power-source = <1>; + power-source = <0>; }; }; @@ -35,7 +35,7 @@ function = "normal"; bias-disable; output-high; - power-source = <1>; + power-source = <0>; }; }; }; From 85b618618461ecb83954ec08b75dab33ab0d68a0 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Tue, 15 Dec 2020 11:53:01 -0800 Subject: [PATCH 0499/1809] ARM: dts: msm: Split tz mem region for sdxlemur Split off the tz_apps region from the tz_mem region. Change-Id: I6409c251bf862867ae4613f6ad6e6a757d1b06f8 --- qcom/sdxlemur-512mb.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-512mb.dtsi b/qcom/sdxlemur-512mb.dtsi index 29098f1f0707..ba61e13cbec3 100644 --- a/qcom/sdxlemur-512mb.dtsi +++ b/qcom/sdxlemur-512mb.dtsi @@ -4,9 +4,14 @@ reg = <0x90800000 0xF800000>; }; + tz_apps_mem: tz_apps_mem_region@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + tz_mem: tz_mem_region@8ff00000 { no-map; - reg = <0x8ff00000 0x600000>; + reg = <0x8ff00000 0x100000>; }; cmd_db: reserved-memory@8fee0000 { From dc75150365239db1429109a81d068729e69e0d2e Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 9 Dec 2020 10:07:22 -0800 Subject: [PATCH 0500/1809] ARM: dts: msm: add conn_therm and charger_skin_therm for sdxlemur platforms Add conn_therm and charger_skin_therm ADC_TM channels on PM7250B and corresponding thermal zones so that these can be monitored via thermal framework. Change-Id: I07096484020efd069d47dfb3c547aa1d28f3b122 --- qcom/sdxlemur-mtp-mbb.dtsi | 59 ++++++++++++++++++++++++++++++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 59 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index fe3402b3a3d0..e8bf5abbdd5b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -51,6 +51,65 @@ }; }; +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + &pm7250b_charger { #io-channel-cells = <1>; io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7178de77c818..5af113e478b8 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -72,6 +72,65 @@ }; }; +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + &pm7250b_charger { #io-channel-cells = <1>; io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, From 58efc38d79bed494ce86dc744a27e29f74bd8285 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Mon, 28 Sep 2020 11:41:03 -0700 Subject: [PATCH 0501/1809] dt-bindings: Update for CNSS driver to support WCN7850 device Add support for WCN7850 device in CNSS driver DT bindings. Change-Id: I701e4858fcbfdbecd5914f69bb36ee831934a566 --- bindings/cnss/cnss-wlan.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index c1de42da51fb..5a77cba316b3 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -15,6 +15,7 @@ Required properties: "qcom,cnss-qca6290" for QCA6290 device "qcom,cnss-qca6390" for QCA6390 device "qcom,cnss-qca6490" for QCA6490 device + "qcom,cnss-wcn7850" for WCN7850 device - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications - vdd-wlan-supply: phandle to the regulator device tree node - pinctrl-names: Names corresponding to the numbered pinctrl states From 92f7eaa3334c436e69f8bd1debb894ee4498e692 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:13:52 +0530 Subject: [PATCH 0502/1809] ARM: dts: msm: add interconnect devices for scshrike Add interconnect devices for scshrike. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I1aa051d639fb9c4d7d5da4eb7b0acbf573c94a46 --- qcom/sdmshrike.dtsi | 96 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index a56b27af3d27..12929be71bab 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1,4 +1,6 @@ #include +#include +#include #include #include @@ -648,6 +650,10 @@ , ; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + system_pm { compatible = "qcom,system-pm"; }; @@ -665,6 +671,96 @@ , , ; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x7400>; + compatible = "qcom,scshrike-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x29400>; + compatible = "qcom,scshrike-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@0 { + compatible = "qcom,scshrike-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + camnoc_virt: interconnect@1 { + compatible = "qcom,scshrike-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16E0000 0x1A080>; + compatible = "qcom,scshrike-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x3A080>; + compatible = "qcom,scshrike-aggre2_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnet@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,scshrike-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,scshrike-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,scshrike-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,scshrike-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + compute_noc: interconnect@9800000 { + reg = <0x9800000 0x40000>; + compatible = "qcom,scshrike-compute_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; qupv3_id_1: geniqup@ac0000 { From ee580336dcbdac0f5caa926d53cd18bea37724d3 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:21:02 +0530 Subject: [PATCH 0503/1809] ARM: dts: msm: Add support for glink for SDMSHRIKE Add glink and its dependent device tree node to support SDMSHRIKE for automotive platforms. Change-Id: Ib259938079713c19521edf00eb7c612c61ced57b --- qcom/sa8195-smp2p.dtsi | 84 ++++++++++++ qcom/sdmshrike.dtsi | 293 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 377 insertions(+) create mode 100644 qcom/sa8195-smp2p.dtsi diff --git a/qcom/sa8195-smp2p.dtsi b/qcom/sa8195-smp2p.dtsi new file mode 100644 index 000000000000..eae7afdc53d6 --- /dev/null +++ b/qcom/sa8195-smp2p.dtsi @@ -0,0 +1,84 @@ +#include + +&soc { + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-dsps { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + dsps_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + dsps_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 12929be71bab..d55ebe79786a 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -763,6 +763,298 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + sp_scsr: mailbox@188501c { + compatible = "qcom,sm8150-spcs-global"; + reg = <0x188501c 0x4>; + + #mbox-cells = <1>; + }; + + sp_scsr_block: syscon@1880000 { + compatible = "syscon"; + reg = <0x1880000 0x10000>; + }; + + intsp: qcom,qsee_irq { + compatible = "qcom,sm8150-qsee-irq"; + + syscon = <&sp_scsr_block>; + interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, + <0 349 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "sp_ipc0", + "sp_ipc1"; + + interrupt-controller; + #interrupt-cells = <3>; + }; + + qcom,qsee_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + label = "spss"; + interrupt-parent = <&intsp>; + interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apss_shared 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_slpi>, + <&glink_cdsp>, + <&glink_spss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apss_shared 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_slpi>, + <&glink_cdsp>; + }; + }; + + glink_slpi: dsps { + qcom,remote-pid = <3>; + transport = "smem"; + mboxes = <&apss_shared 24>; + mbox-names = "dsps_smem"; + interrupts = ; + + label = "slpi"; + qcom,glink-label = "dsps"; + + qcom,slpi_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,slpi_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apss_shared 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_slpi>; + }; + }; + + glink_spss: spss { + qcom,remote-pid = <8>; + transport = "spss"; + mboxes = <&sp_scsr 0>; + mbox-names = "spss_spss"; + interrupt-parent = <&intsp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + + qcom,spss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + qcom,remote-pid = <10>; + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; @@ -784,3 +1076,4 @@ #include "sdmshrike-pinctrl.dtsi" #include "sa8195-regulator.dtsi" #include "sm8150-pm.dtsi" +#include "sa8195-smp2p.dtsi" From a076a28637aca6f1f2303a0f29d2614012c355e9 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:29:12 +0530 Subject: [PATCH 0504/1809] ARM: dts: msm: Add all clock controller and gdsc nodes for scshrike Add support for aopcc, camcc, dispcc, gcc, gpucc, npucc, rpmhcc, scc, videocc, debugcc and also add gdsc regulators. Change-Id: Ia5751e7de691e3da606c4e2b94f21e726830d0f1 --- qcom/sa8195-gdsc.dtsi | 47 ++++++ qcom/sa8195-pmic.dtsi | 9 + qcom/sa8195p.dtsi | 4 + qcom/sdmshrike-v2.dtsi | 25 +++ qcom/sdmshrike.dtsi | 361 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 446 insertions(+) create mode 100644 qcom/sa8195-gdsc.dtsi diff --git a/qcom/sa8195-gdsc.dtsi b/qcom/sa8195-gdsc.dtsi new file mode 100644 index 000000000000..162c15715572 --- /dev/null +++ b/qcom/sa8195-gdsc.dtsi @@ -0,0 +1,47 @@ +#include "sm8150-gdsc.dtsi" + +&soc { + /* GDSCs in Global CC */ + pcie_2_gdsc: qcom,gdsc@19d004 { + compatible = "qcom,gdsc"; + reg = <0x19d004 0x4>; + regulator-name = "pcie_2_gdsc"; + status = "disabled"; + }; + + pcie_3_gdsc: qcom,gdsc@1a3004 { + compatible = "qcom,gdsc"; + reg = <0x1a3004 0x4>; + regulator-name = "pcie_3_gdsc"; + status = "disabled"; + }; + + ufs_card_2_gdsc: qcom,gdsc@1a2004 { + compatible = "qcom,gdsc"; + reg = <0x1a2004 0x4>; + regulator-name = "ufs_card_2_gdsc"; + status = "disabled"; + }; + + usb30_mp_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + reg = <0x1a6004 0x4>; + regulator-name = "usb30_mp_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + ife_2_gdsc: qcom,gdsc@ad0f004 { + compatible = "qcom,gdsc"; + reg = <0xad0f004 0x4>; + regulator-name = "ife_2_gdsc"; + status = "disabled"; + }; + + ife_3_gdsc: qcom,gdsc@ad0f070 { + compatible = "qcom,gdsc"; + reg = <0xad0f070 0x4>; + regulator-name = "ife_3_gdsc"; + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index db67174ef773..b7685fdd1316 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -59,4 +59,13 @@ /delete-node/ refgen; }; +&camcc { + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_MMCX_LEVEL>; +}; + #include "sa8195p-regulator.dtsi" diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 7fe00b0a2047..77cdf96d63eb 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -7,3 +7,7 @@ qcom,msm-id = <405 0x20000>; }; +&scc { + vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>; + status = "ok"; +}; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index 863f841f4398..acbb61d0ecc6 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -6,3 +6,28 @@ qcom,msm-id = <340 0x20000>; }; +/delete-node/ &ufs_card_gdsc; + +&camcc { + compatible = "qcom,scshrike-camcc-v2", "syscon"; +}; + +&dispcc { + compatible = "qcom,scshrike-dispcc-v2", "syscon"; +}; + +&gcc { + compatible = "qcom,scshrike-gcc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sm8150-npucc-v2", "syscon"; +}; + +&scc { + compatible = "qcom,sa8195-scc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sm8150-videocc-v2", "syscon"; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index d55ebe79786a..a5f732365872 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1,3 +1,11 @@ +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include @@ -579,6 +587,22 @@ }; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + }; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; @@ -654,6 +678,12 @@ compatible = "qcom,bcm-voter"; }; + rpmhcc: clock-controller { + compatible = "qcom,sm8150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; + system_pm { compatible = "qcom,system-pm"; }; @@ -777,6 +807,147 @@ #mbox-cells = <1>; }; + aopcc: qcom,aopcc@0 { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,scshrike-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = + "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: clock-controller@2b10000 { + compatible = "qcom,sa8195-scc"; + reg = <0x2b10000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + status = "disabled"; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,scshrike-gpucc", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + npucc: clock-controller@9910000 { + compatible = "qcom,sm8150-npucc", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_NPU_GPLL0_CLK_SRC>, + <&gcc GCC_NPU_AXI_CLK>; + clock-names = + "bi_tcxo", + "gcc_npu_gpll0_div_clk_src", + "gcc_npu_gpll0_clk_src", + "gcc_npu_axi_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm8150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = + "cfg_ahb_clk", + "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,scshrike-camcc", "syscon"; + reg = <0xad00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = + "cfg_ahb_clk", + "bi_tcxo", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,scshrike-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = + "cfg_ahb_clk", + "bi_tcxo", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,scshrike-debugcc"; + qcom,gcc = <&gcc>; + qcom,videocc = <&videocc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,npucc = <&npucc>; + qcom,gpucc = <&gpucc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; @@ -1077,3 +1248,193 @@ #include "sa8195-regulator.dtsi" #include "sm8150-pm.dtsi" #include "sa8195-smp2p.dtsi" +#include "sa8195-gdsc.dtsi" + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&pcie_1_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&pcie_2_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&pcie_3_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ufs_card_2_gdsc { + status = "ok"; +}; + +&ufs_card_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_mp_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_3_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&npu_core_gdsc { + clocks = <&gcc GCC_NPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + status = "ok"; +}; + +&mvs0_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvsc_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; From dd51641fbd67c90e726064270ad20bde606a67be Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 17 Dec 2020 14:28:23 +0530 Subject: [PATCH 0505/1809] ARM: dts: msm: Add cpufreq HW device node SDMSHRIKE Add cpufreq HW device node to scale 4 domain-0 & 4 domain-1 cores on SDMSHRIKE SoCs. Change-Id: I2cf89a059d028ed559623dba0d4abebfc1fe4c85 --- qcom/sdmshrike.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index a5f732365872..fb75c9c7178d 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -39,6 +39,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -72,6 +73,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 4>; #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -99,6 +101,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_2>; + qcom,freq-domain = <&cpufreq_hw 0 4>; #cooling-cells = <2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -126,6 +129,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_3>; + qcom,freq-domain = <&cpufreq_hw 0 4>; #cooling-cells = <2>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -153,6 +157,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 1 4>; #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -180,6 +185,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 1 4>; #cooling-cells = <2>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -207,6 +213,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 4>; #cooling-cells = <2>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -234,6 +241,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 1 4>; #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -948,6 +956,15 @@ #clock-cells = <1>; }; + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <2>; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; From b1ed71a1b017fdf6df9055bd04fce2109f2fe5a3 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:39:23 +0530 Subject: [PATCH 0506/1809] ARM: dts: msm: Enable L3 interconnect driver for scshrike Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: I99a5085192c1d551e5d0973bb50f96d27d97746a --- qcom/sdmshrike.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index fb75c9c7178d..57a88936e1df 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -716,6 +717,14 @@ }; }; + osm_l3: interconnect@18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,scshrike-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + config_noc: interconnect@1500000 { reg = <0x1500000 0x7400>; compatible = "qcom,scshrike-config_noc"; From 65e155622d87b892b20e3d6526c9bc8a912fcd0e Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Sat, 19 Dec 2020 13:44:52 -0800 Subject: [PATCH 0507/1809] ARM: dts: msm: Disable USB SMMU S1 on sdxlemur pcie ep platform Disable smmu s1 for usb on pcie ep platform as IPA does not use smmu for this board. Change-Id: I3a15369407bacea9a2e8f377af9e20073fdbeeb4 --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 5ba52a7dd66f..6ff59f6e0590 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -44,3 +44,7 @@ qcom,iommu-dma = "bypass"; }; }; + +&usb { + qcom,iommu-dma = "bypass"; +}; From b10a12e903b64779fd217b82789f5ba50f83f8fa Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Mon, 21 Dec 2020 10:23:20 +0800 Subject: [PATCH 0508/1809] ARM: dts: msm: fix USB2 issue on holi QRD DVT change PLL_BIAS_CONTROL_2 from 0x17 to 0x20. Change-Id: I0ed46b97cfcb3d6088a3298d4cd8fa7479ea1fef --- qcom/holi-qrd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 651a5cad83ad..ede97e819b69 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -649,7 +649,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ @@ -670,7 +670,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ From 7cf6499ef389a5c6500d10f36619b7bcdf5bd20d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 21 Dec 2020 17:06:13 +0800 Subject: [PATCH 0509/1809] ARM: dts: msm: add DCC register list for sdxlemur Add DCC register list to support DCC register dump for sdxlemur. Change-Id: I5d58d87084d173f298488d378223b74d7fa92ef9 --- qcom/sdxlemur.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 5378d2465d40..da49b411b2ab 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -199,6 +199,15 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; + + link_list1 { + qcom,curr-link-list = <2>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + ; + }; }; wdog: qcom,wdt@17817000 { From 3364e7cdcda660c770594dc84cb3e0b68a5ccb3a Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Mon, 21 Dec 2020 16:42:56 +0530 Subject: [PATCH 0510/1809] ARM: dts: msm: Add MPROC device nodes for monaco Add SMEM, TCSR Mutex, Glink and SMP2P devices for enabling interprocessor communication with MPSS, LPASS and RPM. Change-Id: Ib0ff3ed3478ddaf09e7e0febdc7efbac60fe8276 --- qcom/monaco.dtsi | 183 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 00a455b2e82a..4f480c12f34b 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -574,6 +574,189 @@ qcom,ea-pc = <0x3f0>; status = "ok"; }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x4000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,monaco-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "monaco-pinctrl.dtsi" From 5676a416a7b5773bcc71a7213de031e4351b7d0f Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 25 Nov 2020 15:30:16 +0530 Subject: [PATCH 0511/1809] ARM: dts: msm: Add EUD node for Yupik Add EUD DT node to enable the EUD driver on Yupik platform. Change-Id: Icb7016fba153e0e3ae3e84d77553a6dcf75ca852 --- qcom/yupik.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c9453138edba..bd6917dfd6c9 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -669,6 +669,18 @@ qcom,coresight-jtagmm-cpu = <&CPU7>; }; + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x088e0000 0x2000>, + <0x088e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + status = "ok"; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From f3dc7c34344295d7f61812e1edeb583123420a1e Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 9 Dec 2020 11:45:20 +0530 Subject: [PATCH 0512/1809] Revert "ARM: dts: msm: add initial support for hw memlat devices" This reverts commit 690d106d3d544e9c979c8b33135f934a446d23df. Change-Id: I609e6b4623854f49c3fa4605ee1614437130072a --- qcom/holi.dtsi | 272 ++++++++++++++++++++++++++++++------------------- 1 file changed, 168 insertions(+), 104 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a6fd5b665950..8341ad465c55 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -247,20 +247,6 @@ }; soc: soc { }; - - sram: sram@fd04480 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x0 0x0fd04480 0x0 0x80>; - ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scp-shmem"; - reg = <0x0 0x0 0x0 0x80>; - }; - }; }; &firmware { @@ -1343,6 +1329,66 @@ qcom,count-unit = <0x10000>; }; + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; + }; + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devfreq-icc"; governor = "compute"; @@ -1359,6 +1405,26 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; + }; + cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -1375,10 +1441,78 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; @@ -1407,6 +1541,26 @@ compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU6 &CPU7>; + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; @@ -1433,96 +1587,6 @@ }; }; - rimps: qcom,rimps@0f400000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "qcom,rimps"; - reg = <0x0f400000 0x10>, - <0x0fd90000 0x2000>; - #mbox-cells = <1>; - interrupts = <0 22 4>; - }; - - cpu0_grp: qcom,cpu0_grp { - compatible = "qcom,rimps-memlat-cpugrp"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xfd04580 0x280>; - reg-names = "pmu-base"; - - cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { - compatible = "qcom,rimps-memlat-mon-l3"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,cachemiss-ev = <0x17>; - reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; - reg-names = "ftbl-base", "perf-base"; - - qcom,core-dev-table = - < 710400 300000000 >, - < 940800 518400000 >, - < 1190400 748800000 >, - < 1478400 921600000 >, - < 1574400 1305600000 >, - < 1804800 1459000000 >; - }; - }; - - cpu6_grp: qcom,cpu6_grp { - compatible = "qcom,rimps-memlat-cpugrp"; - qcom,cpulist = <&CPU6 &CPU7>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xfd04580 0x280>; - reg-names = "pmu-base"; - - cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { - compatible = "qcom,rimps-memlat-mon-l3"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,cachemiss-ev = <0x17>; - qcom,wb-ev = <0x18>; - qcom,access-ev = <0x2B>; - reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; - reg-names = "ftbl-base", "perf-base"; - - qcom,core-dev-table = - < 1017600 518400000 >, - < 1248000 748800000 >, - < 1536000 921600000 >, - < 1651200 1171200000 >, - < 1804800 1305600000 >, - < 2035200 1459000000 >; - }; - }; - - scmi: qcom,scmi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,scmi"; - mboxes = <&rimps 0>; - mbox-names = "tx"; - shmem = <&cpu_scp_lpri>; - - scmi_memlat: protocol@80 { - reg = <0x80>; - #clock-cells = <1>; - }; - - scmi_perf_lock: protocol@81 { - reg = <0x81>; - #clock-cells = <1>; - }; - }; - - rimps_log: qcom,rimps_log@fd04780 { - compatible = "qcom,rimps-log"; - reg = <0x0fd04800 0x200>, - <0x0fd04A00 0x200>; - mboxes = <&rimps 1>; - }; - tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; From f7ee8ba79b6f4833f0732b9e263e10b7fa949863 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 17 Dec 2020 16:42:10 -0800 Subject: [PATCH 0513/1809] ARM: dts: msm: Remove sdxlemur dt from pcie-ep dtsi Inclusion of the base sdxlemur device tree in the pcie-ep tree was disabling the nand and causing it not to probe. This change removes its inclusion. Change-Id: If47b99fce5340bf4296f00491dff9ecf86598066 --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 5ba52a7dd66f..8c020a3f4db1 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,5 +1,4 @@ #include "sdxlemur-mtp.dtsi" -#include "sdxlemur.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" &soc { From 437dbaca6fdd51099f5c825e0d8bb36c4919f326 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 21 Dec 2020 10:53:37 +0530 Subject: [PATCH 0514/1809] ARM: dts: msm: Adding all CoreTech DT Changes to Mainline 5.4 Changes Included:- 1.) PCIE:- 3185343 2.) USB:- 3185077 3337896 3353566 3.) BUSES:- 3178854 3181107 3226742 3218985 3380173 4.) STORAGE:- 3366250 3261571. Change-Id: I0765efaa30aed15f659e75b9c641fee0f9dfe20f --- qcom/sa8155-adp-common.dtsi | 30 ++ qcom/sa8155-v2.dtsi | 248 +++++++++++ qcom/sa8155.dtsi | 32 ++ qcom/sm8150-pcie.dtsi | 593 ++++++++++++++++++++++++++ qcom/sm8150-pinctrl.dtsi | 157 ++----- qcom/sm8150-qupv3.dtsi | 829 ++++++++++++++++++++++++++++++++++++ qcom/sm8150-ssc-qupv3.dtsi | 109 +++++ qcom/sm8150-usb.dtsi | 349 +++++++++++++++ qcom/sm8150-v2.dtsi | 261 ++++++++++++ qcom/sm8150.dtsi | 67 ++- 10 files changed, 2543 insertions(+), 132 deletions(-) create mode 100644 qcom/sm8150-pcie.dtsi create mode 100644 qcom/sm8150-qupv3.dtsi create mode 100644 qcom/sm8150-ssc-qupv3.dtsi create mode 100644 qcom/sm8150-usb.dtsi diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index b7e203419cc2..431edd4ef15f 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -3,6 +3,10 @@ #include "sa8155-pmic-overlay.dtsi" +&qupv3_3 { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; @@ -27,3 +31,29 @@ status = "ok"; }; + +&pcie1 { + qcom,boot-option = <0x0>; +}; + +&sdhc_2 { + vdd-supply = <&pm8150_1_l17>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150_2_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + cd-gpios = <&pm8150_1_gpios 4 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index f995a319af99..8862fd543d7f 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -7,6 +7,254 @@ qcom,msm-id = <362 0x20000>; }; +&pcie0 { + qcom,pcie-phy-ver = <2114>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x0288 0x82 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cb4 0x33 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0ca4 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x12 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; +}; + +&pcie1 { + qcom,pcie-phy-ver = <2111>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x0288 0x82 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x0688 0x82 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x04 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x12 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0eb4 0x33 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0ea4 0x0f 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; +}; + &scc { compatible = "qcom,sa8155-scc-v2", "syscon"; }; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 8f7a349e5ad9..bfc7cfe41273 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -53,9 +53,41 @@ status = "ok"; }; +&usb2_phy0 { + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; +}; + +&usb2_phy1 { + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; +}; + +&usb_qmp_phy { + vdd-supply = <&pm8150_1_l5>; + core-supply = <&pm8150_2_l8>; +}; + /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" +&pcie0 { + vreg-1p8-supply = <&pm8150_2_l8>; + vreg-0p9-supply = <&pm8150_2_l18>; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + qcom,core-preset = <0x77777777>; +}; + +&pcie1 { + vreg-1p8-supply = <&pm8150_2_l8>; + vreg-0p9-supply = <&pm8150_2_l18>; + qcom,core-preset = <0x77777777>; +}; + &gpucc { compatible = "qcom,sa8155-gpucc", "syscon"; }; diff --git a/qcom/sm8150-pcie.dtsi b/qcom/sm8150-pcie.dtsi new file mode 100644 index 000000000000..7547335577bb --- /dev/null +++ b/qcom/sm8150-pcie.dtsi @@ -0,0 +1,593 @@ +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c04000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x05 0x0 + 0x0c38 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x14 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x39 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x39 0x0 + 0x0594 0x37 0x0 + 0x0570 0x7f 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0xdb 0x0 + 0x0580 0x75 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0414 0x04 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x66 0x0 + 0x0998 0x08 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x04b4 0x02 0x0 + 0x04b8 0x02 0x0 + 0x04bc 0xaa 0x0 + 0x04c0 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0460 0xa0 0x0 + 0x05c4 0x0c 0x0 + 0x0464 0x00 0x0 + 0x05c0 0x10 0x0 + 0x04dc 0x05 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8150l_l3>; + vreg-0p9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <0x40>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + dma-coherent; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c08000 0x4000>, + <0x1c0c000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0050 0x07 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x32 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x01 0x0 + 0x0284 0x05 0x0 + 0x029c 0x12 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x04d8 0x01 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x14 0x0 + 0x0570 0x7f 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0xdb 0x0 + 0x0580 0x75 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x39 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x39 0x0 + 0x05a8 0x31 0x0 + 0x05b4 0x04 0x0 + 0x04b4 0x02 0x0 + 0x04b8 0x02 0x0 + 0x04bc 0xaa 0x0 + 0x04c0 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0460 0xa0 0x0 + 0x05c4 0x0c 0x0 + 0x0464 0x00 0x0 + 0x05c0 0x10 0x0 + 0x04dc 0x05 0x0 + 0x0684 0x05 0x0 + 0x069c 0x12 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x08d8 0x01 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x14 0x0 + 0x0970 0x7f 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0xdb 0x0 + 0x0980 0x75 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3a 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x39 0x0 + 0x09a8 0x31 0x0 + 0x09b4 0x04 0x0 + 0x08b4 0x02 0x0 + 0x08b8 0x02 0x0 + 0x08bc 0xaa 0x0 + 0x08c0 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x0860 0xa0 0x0 + 0x09c4 0x0c 0x0 + 0x0864 0x00 0x0 + 0x09c0 0x10 0x0 + 0x08dc 0x05 0x0 + 0x0a98 0x01 0x0 + 0x0abc 0x56 0x0 + 0x0adc 0x0d 0x0 + 0x0b88 0x66 0x0 + 0x0ba4 0x01 0x0 + 0x0b98 0x08 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e78 0x50 0x0 + 0x0e90 0x00 0x0 + 0x0ea0 0x11 0x0 + 0x0e38 0x03 0x0 + 0x0e50 0x00 0x0 + 0x0e20 0x01 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1p8-supply = <&pm8150l_l3>; + vreg-0p9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <0x40>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + dma-coherent; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + pcie_rc1: pcie_rc1 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index d1db3b16af65..e5391f4ffef5 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -68,160 +68,55 @@ }; }; - storage_cd: storage_cd { - mux { - pins = "gpio96"; - function = "gpio"; + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ }; - config { + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + sd-cd { pins = "gpio96"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { + sdc2_off: sdc2_off { + clk { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { + cmd { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { + data { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_data_ds_400KHz: sdc2_data_ds_400KHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_ds_50MHz: sdc2_data_ds_50MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_ds_100MHz: sdc2_data_ds_100MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_ds_200MHz: sdc2_data_ds_200MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ + sd-cd { + pins = "gpio96"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ }; }; diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi new file mode 100644 index 000000000000..1dbbcbf1bde8 --- /dev/null +++ b/qcom/sm8150-qupv3.dtsi @@ -0,0 +1,829 @@ +#include +#include + +&soc { + /* QUPv3 South Instances + * South 0 : SE 0 + * South 1 : SE 1 + * South 2 : SE 2 + * South 3 : SE 3 + * South 4 : SE 4 + * South 5 : SE 5 + * South 6 : SE 6 + * South 7 : SE 7 + * + * QUPv3 North & East Instances + * North 0 : SE 8 + * North 1 : SE 9 + * North 2 : SE 10 + * North 3 : SE 11 + * North 4 : SE 12 + * North 5 : SE 16 + * East 0 : SE 17 + * East 1 : SE 18 + * East 2 : SE 19 + * East 3 : SE 13 + * East 4 : SE 14 + * East 5 : SE 15 + */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0xc3 0x0>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep &qupv3_se3_spi_miso_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x603 0x0>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* 4-wire UART */ + qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>, + <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 46 0>; + qcom,wrapper-core = <&qupv3_2>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_active>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* QUPv3 East Instances */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xcc0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x7a3 0x0>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* I2C */ + qupv3_se13_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se14_i2c: i2c@0xc90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@0xc94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@0xc80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@0xc84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@0xc88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se13_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + +}; diff --git a/qcom/sm8150-ssc-qupv3.dtsi b/qcom/sm8150-ssc-qupv3.dtsi new file mode 100644 index 000000000000..33183503124e --- /dev/null +++ b/qcom/sm8150-ssc-qupv3.dtsi @@ -0,0 +1,109 @@ +#include +#include + +&soc { + /* QUPv3 SSC Instance */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x26c0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x4e3 0x0>; + qcom,iommu-dma = "fastmap"; + status = "disabled"; + }; + + /* I2C*/ + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE0_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi new file mode 100644 index 000000000000..81c724f22e49 --- /dev/null +++ b/qcom/sm8150-usb.dtsi @@ -0,0 +1,349 @@ +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + /* + * GCC_USB3_SEC_CLKREF_CLK provides ref_clk for both + * USB instances. Hence GCC_USB3_PRIM_CLKREF_CLK is not + * used here. + */ + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,ignore-wakeup-src-in-hostmode; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en1_default>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150l_l3>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index a6f26d35f304..c2d7cb5fb7f2 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -35,3 +35,264 @@ }; #include "msm-arm-smmu-sm8150-v2.dtsi" + +&pcie0 { + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + qcom,pcie-phy-ver = <2110>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; +}; + +&pcie1 { + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + qcom,pcie-phy-ver = <2109>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x04 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x12 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0eb4 0x33 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0ea4 0x0f 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index b8e9208d6ec6..b267c74748e4 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -29,7 +29,11 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ - serial0 = &uart2; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + pci-domain0 = &pcie0; /* PCIe0 domain */ + pci-domain1 = &pcie1; /* PCIe1 domain */ + serial0 = &qupv3_se12_2uart; + hsuart0 = &qupv3_se13_4uart; }; cpus { @@ -1574,6 +1578,63 @@ interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>,<100000 100000>, + /* 50 MB/s */ + <130718 200000>,<133320 133320>, + /* 100 MB/s */ + <261438 200000>,<150000 150000>, + /* 200 MB/s */ + <261438 400000>,<300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 25000000 50000000 100750000 + 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 201500000>; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <44>; + }; + + qos1 { + mask = <0xc0>; + vote = <44>; + }; + }; }; &firmware { @@ -1586,7 +1647,9 @@ #include "sm8150-pinctrl.dtsi" #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" +#include "sm8150-qupv3.dtsi" #include "sm8150-slpi-pinctrl.dtsi" +#include "sm8150-ssc-qupv3.dtsi" #include "sm8150-smp2p.dtsi" #include "sm8150-gdsc.dtsi" #include "msm-arm-smmu-sm8150.dtsi" @@ -1745,3 +1808,5 @@ clocks = <&gcc GCC_NPU_CFG_AHB_CLK>; status = "ok"; }; +#include "sm8150-pcie.dtsi" +#include "sm8150-usb.dtsi" From 1a105a8ad074851ac667b14b58a8c1f04b8b2740 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 21 Dec 2020 16:37:04 +0800 Subject: [PATCH 0515/1809] ARM: dts: msm: correct modem etm0 connecton on sdxlemur Correct modem etm0 connecton and add modem diag node on sdxlemur. Change-Id: I63dd2c54d12b27d068912f390ea2b0da72ab3131 --- qcom/sdxlemur-coresight.dtsi | 74 +++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 6 deletions(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 073cfa4332f9..4cc7c33e6375 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -614,11 +614,11 @@ }; }; - port@2 { - reg = <2>; - funnel_modem_in_funnel_modem_q6: endpoint { + port@3 { + reg = <3>; + funnel_modem_in_funnel_mq6_dup: endpoint { remote-endpoint = - <&funnel_modem_q6_out_funnel_modem>; + <&funnel_mq6_dup_out_funnel_modem>; }; }; }; @@ -654,9 +654,9 @@ out-ports { port { - funnel_modem_q6_out_funnel_modem: endpoint { + funnel_modem_q6_out_funnel_mq6_dup: endpoint { remote-endpoint = - <&funnel_modem_in_funnel_modem_q6>; + <&funnel_mq6_dup_in_funnel_modem_q6>; }; }; }; @@ -674,6 +674,68 @@ }; }; + funnel_mq6_dup: funnel@680d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x680d000 0x1000>, + <0x680c000 0x1000>; + + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem-q6_dup"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + out-ports { + port { + funnel_mq6_dup_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_mq6_dup>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + funnel_mq6_dup_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_mq6_dup>; + }; + }; + + port@2 { + reg = <2>; + funnel_mq6_dup_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_mq6_dup>; + }; + }; + }; + }; + + modem_diag: dummy_source { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + + out-ports { + port { + modem_diag_out_funnel_mq6_dup: endpoint { + remote-endpoint = + <&funnel_mq6_dup_in_modem_diag>; + }; + }; + }; + }; + modem_etm0 { compatible = "qcom,coresight-remote-etm"; From 8540d76fe4b59d8ec48be82a3be50888c47ac654 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 23 Oct 2020 18:06:36 +0800 Subject: [PATCH 0516/1809] ARM: dts: msm: Add QDSS devictree for sdxnightjar Add QDSS component devicetree file for sdxnightjar. Change-Id: I446f3b88f094282c2cc0019611f6188ddcdb695d --- qcom/sdxnightjar-coresight.dtsi | 608 ++++++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 5 +- 2 files changed, 611 insertions(+), 2 deletions(-) create mode 100644 qcom/sdxnightjar-coresight.dtsi diff --git a/qcom/sdxnightjar-coresight.dtsi b/qcom/sdxnightjar-coresight.dtsi new file mode 100644 index 000000000000..1a5475cc1d32 --- /dev/null +++ b/qcom/sdxnightjar-coresight.dtsi @@ -0,0 +1,608 @@ +&soc { + fuse: fuse@a601c { + compatible = "arm,coresight-fuse-v2"; + reg = <0xa601c 0x8>, + <0xa600c 0x4>; + reg-names = "fuse-base", "qpdi-fuse-base"; + coresight-name = "coresight-fuse"; + + }; + + csr: csr@801000 { + compatible = "qcom,coresight-csr"; + reg = <0x801000 0x1000>; + reg-names = "csr-base"; + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + + hwevent { + compatible = "qcom,coresight-hwevent"; + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + stm: stm@802000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x802000 0x1000>, + <0x9280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-stm"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + }; + + dbgui: dbgui@86d000 { + compatible = "qcom,coresight-dbgui"; + reg = <0x86d000 0x1000>; + reg-names = "dbgui-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-dbgui"; + + qcom,dbgui-addr-offset = <0x30>; + qcom,dbgui-data-offset = <0xb0>; + qcom,dbgui-size = <0x20>; + + out-ports { + port { + dbgui_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_dbugi>; + }; + }; + }; + }; + + etm0: etm@842000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb956>; + reg = <0x842000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-etm0"; + + out-ports { + port { + etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_etm0>; + }; + }; + }; + }; + + + tpdm_modem: tpdm@83a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x83a000 0x1000>; + reg-names = "tpdm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tpdm-modem"; + + out-ports { + port { + tpdm_modem_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem>; + }; + }; + }; + }; + + modem_etm0: modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + + qcom,inst-id = <2>; + + out-ports { + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + }; + + rpm_etm0: rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-rpm-etm0"; + + qcom,inst-id = <4>; + + out-ports { + port { + rpm_etm0_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_rpm_etm0>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@864000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x864000 0x1000>; + reg-names = "tpdm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tpdm-dcc"; + qcom,hw-enable-check; + + out-ports { + port { + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_dcc>; + }; + }; + }; + }; + + + tpda_modem: tpda@83b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x083b000 0x1000>; + reg-names = "tpda-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 8>; + + out-ports { + port { + tpda_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_modem>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_in_tpdm_modem: endpoint { + + remote-endpoint = + <&tpdm_modem_out_tpda_modem>; + }; + }; + + }; + }; + + + tpda: tpda@803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x0803000 0x1000>; + reg-names = "tpda-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,cmb-elem-size = <0 8>; + + out-ports { + port { + tpda_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + }; + }; + + funnel_in0: funnel@821000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0821000 0x1000>; + reg-names = "funnel-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-funnel-in0"; + + out-ports { + port { + funnel_in0_out_funnel_merge: endpoint { + remote-endpoint = + <&funnel_merge_in_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in0_in_rpm_etm0: endpoint { + remote-endpoint = + <&rpm_etm0_out_funnel_in0>; + }; + }; + + port@4 { + reg = <4>; + funnel_in0_in_dbugi: endpoint { + remote-endpoint = + <&dbgui_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_tpda: endpoint { + remote-endpoint = + <&tpda_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@822000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0822000 0x1000>; + reg-names = "funnel-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-funnel-in1"; + + out-ports { + port { + funnel_in1_out_funnel_merge: endpoint { + remote-endpoint = + <&funnel_merge_in_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in1_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_in1>; + }; + }; + + port@7 { + reg = <7>; + funnel_in1_in_etm0: endpoint { + remote-endpoint = + <&etm0_out_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@825000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0825000 0x1000>; + reg-names = "funnel-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-funnel-merg"; + + out-ports { + port { + funnel_merge_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merge>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merge_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_merge>; + }; + }; + + port@1 { + reg = <1>; + funnel_merge_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_merge>; + }; + }; + + }; + }; + + tmc_etf: tmc@827000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0827000 0x1000>; + reg-names = "tmc-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; + + in-ports { + port { + tmc_etf_in_funnel_merge: endpoint { + remote-endpoint = + <&funnel_merge_out_tmc_etf>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port { + tmc_etf_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_tmc_etf>; + }; + }; + + }; + }; + + replicator_qdss: replicator@8026000 { + compatible = "arm,coresight-dynamic-replicator", + "arm,primecell"; + reg = <0x0826000 0x1000>; + reg-names = "replicator-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-replicator-qdss"; + + in-ports { + port { + replicator_qdss_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_qdss>; + }; + }; + }; + + out-ports { + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_qdss>; + }; + }; + }; + }; + + tmc_etr: tmc@828000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0828000 0x1000>, + <0x884000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-tmc-etr"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges; + arm,buffer-size = <0x100000>; + arm,scatter-gather; + + coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; + coresight-csr = <&csr>; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + in-ports { + port { + tmc_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + + }; + }; + + cti0: cti@810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x810000 0x1000>; + + reg-names = "cti-base"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti0"; + + }; + + cti1: cti@811000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x811000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti1"; + + }; + + cti2: cti@812000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x812000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti2"; + }; + + cti3: cti@813000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x813000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti3"; + }; + + cti4: cti@814000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x814000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti4"; + }; + + cti5: cti@815000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x815000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti5"; + }; + + cti6: cti@816000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x816000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti6"; + + }; + + cti_modem_cpu0: cti@8390000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x839000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti-modem-cpu0"; + }; + + cti_pmu_cpu0: cti@841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x841000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti-pmu-cpu0"; + cpu = <&CPU0>; + }; + + cti_cpu0: cti@843000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x843000 0x1000>; + reg-names = "cti-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + }; +}; + + diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index cfcbc5d7de08..d761c1f57407 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -414,9 +414,9 @@ reg-names = "etm-base","debug-base"; qcom,coresight-jtagmm-cpu = <&CPU0>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; - /*TODO: Fix the clock when tree is available*/ - clock-names = "core_clk", "core_a_clk"; }; tcsr_mutex_regs: syscon@1905000 { @@ -678,4 +678,5 @@ #include "pmd9650-rpm-regulator.dtsi" #include "sdxnightjar-regulator.dtsi" #include "sdxnightjar-usb.dtsi" +#include "sdxnightjar-coresight.dtsi" #include "sdxnightjar-pinctrl.dtsi" From dfb2ab789daeb8484a3152f638a745483cb4e448 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 17 Nov 2020 22:37:48 +0530 Subject: [PATCH 0517/1809] ARM: dts: msm: add interconnect devices for sdxnightjar Add the interconnect devices for pcnoc, snoc and bimc to enable the real interconenct devices. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: If1809eee334af77081fe525b4bfe9566116d5284 --- qcom/sdxnightjar.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index e26f40eb7346..8337f22edeb9 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1,3 +1,5 @@ +#include +#include #include #include #include @@ -673,6 +675,37 @@ #size-cells = <0>; cell-index = <0>; }; + + bimc: interconnect@400000 { + reg = <0x400000 0x62000>; + compatible = "qcom,sdxnightjar-bimc"; + qcom,util-factor = <153>; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + pc_noc: interconnect@500000 { + reg = <0x500000 0x11000>; + compatible = "qcom,sdxnightjar-pcnoc"; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + system_noc: interconnect@580000 { + reg = <0x580000 0x14000>; + compatible = "qcom,sdxnightjar-snoc"; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; }; #include "pmd9650.dtsi" From 503cb26177480f5e5e796cbb4fceaf0f3767f17f Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 15 Dec 2020 15:22:08 +0530 Subject: [PATCH 0518/1809] ARM: dts: msm: Add device trees for YupikP variant Add device tree support for YupikP variant. Change-Id: Ib6b459c7ab0a083e5a35038f2dfef77f7fd23abc --- bindings/arm/msm/msm.txt | 6 ++++++ qcom/Makefile | 17 +++++++++++++++-- qcom/yupikp-atp-overlay.dts | 11 +++++++++++ qcom/yupikp-atp.dts | 10 ++++++++++ qcom/yupikp-atp.dtsi | 1 + qcom/yupikp-idp-overlay.dts | 11 +++++++++++ qcom/yupikp-idp.dts | 10 ++++++++++ qcom/yupikp-idp.dtsi | 1 + qcom/yupikp-idps-digital-mics-overlay.dts | 11 +++++++++++ qcom/yupikp-idps-digital-mics.dts | 10 ++++++++++ qcom/yupikp-idps-digital-mics.dtsi | 1 + qcom/yupikp-qrd-overlay.dts | 11 +++++++++++ qcom/yupikp-qrd.dts | 10 ++++++++++ qcom/yupikp-qrd.dtsi | 1 + qcom/yupikp.dts | 9 +++++++++ qcom/yupikp.dtsi | 7 +++++++ 16 files changed, 125 insertions(+), 2 deletions(-) create mode 100644 qcom/yupikp-atp-overlay.dts create mode 100644 qcom/yupikp-atp.dts create mode 100644 qcom/yupikp-atp.dtsi create mode 100644 qcom/yupikp-idp-overlay.dts create mode 100644 qcom/yupikp-idp.dts create mode 100644 qcom/yupikp-idp.dtsi create mode 100644 qcom/yupikp-idps-digital-mics-overlay.dts create mode 100644 qcom/yupikp-idps-digital-mics.dts create mode 100644 qcom/yupikp-idps-digital-mics.dtsi create mode 100644 qcom/yupikp-qrd-overlay.dts create mode 100644 qcom/yupikp-qrd.dts create mode 100644 qcom/yupikp-qrd.dtsi create mode 100644 qcom/yupikp.dts create mode 100644 qcom/yupikp.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 5274f24ffb56..983235d4beff 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -59,6 +59,9 @@ SoCs: - YUPIK compatible = "qcom,yupik" +- YUPIKP + compatible = "qcom,yupikp" + - LITO compatible = "qcom,lito" @@ -225,6 +228,9 @@ compatible = "qcom,yupik-rumi" compatible = "qcom,yupik-idp" compatible = "qcom,yupik-atp" compatible = "qcom,yupik-qrd" +compatible = "qcom,yupikp-idp" +compatible = "qcom,yupikp-atp" +compatible = "qcom,yupikp-qrd" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index c65b118ebe95..3709b6ccd9a6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -140,19 +140,32 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-idp-overlay.dtbo \ yupik-atp-overlay.dtbo \ yupik-qrd-overlay.dtbo \ - yupik-idps-digital-mics-overlay.dtbo + yupik-idps-digital-mics-overlay.dtbo \ + yupikp-idp-overlay.dtbo \ + yupikp-atp-overlay.dtbo \ + yupikp-qrd-overlay.dtbo \ + yupikp-idps-digital-mics-overlay.dtbo + yupik-rumi-overlay.dtbo-base := yupik.dtb yupik-idp-overlay.dtbo-base := yupik.dtb yupik-atp-overlay.dtbo-base := yupik.dtb yupik-qrd-overlay.dtbo-base := yupik.dtb yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb +yupikp-idp-overlay.dtbo-base := yupikp.dtb +yupikp-atp-overlay.dtbo-base := yupikp.dtb +yupikp-qrd-overlay.dtbo-base := yupikp.dtb +yupikp-idps-digital-mics-overlay.dtbo-base := yupikp.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ yupik-atp.dtb \ yupik-qrd.dtb \ - yupik-idps-digital-mics.dtb + yupik-idps-digital-mics.dtb \ + yupikp-idp.dtb \ + yupikp-atp.dtb \ + yupikp-qrd.dtb \ + yupikp-idps-digital-mics.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/yupikp-atp-overlay.dts b/qcom/yupikp-atp-overlay.dts new file mode 100644 index 000000000000..5f0074600cdd --- /dev/null +++ b/qcom/yupikp-atp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP ATP"; + compatible = "qcom,yupikp-atp", "qcom,yupikp", "qcom,atp"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/yupikp-atp.dts b/qcom/yupikp-atp.dts new file mode 100644 index 000000000000..47b1b5f99c06 --- /dev/null +++ b/qcom/yupikp-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP ATP"; + compatible = "qcom,yupikp-atp", "qcom,yupikp", "qcom,atp"; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/yupikp-atp.dtsi b/qcom/yupikp-atp.dtsi new file mode 100644 index 000000000000..ace77c9c344c --- /dev/null +++ b/qcom/yupikp-atp.dtsi @@ -0,0 +1 @@ +#include "yupik-atp.dtsi" diff --git a/qcom/yupikp-idp-overlay.dts b/qcom/yupikp-idp-overlay.dts new file mode 100644 index 000000000000..363ffd6b330d --- /dev/null +++ b/qcom/yupikp-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDP"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-idp.dts b/qcom/yupikp-idp.dts new file mode 100644 index 000000000000..23c559faaa8f --- /dev/null +++ b/qcom/yupikp-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDP"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-idp.dtsi b/qcom/yupikp-idp.dtsi new file mode 100644 index 000000000000..aeef58f4f289 --- /dev/null +++ b/qcom/yupikp-idp.dtsi @@ -0,0 +1 @@ +#include "yupik-idp.dtsi" diff --git a/qcom/yupikp-idps-digital-mics-overlay.dts b/qcom/yupikp-idps-digital-mics-overlay.dts new file mode 100644 index 000000000000..ede5df06f0b6 --- /dev/null +++ b/qcom/yupikp-idps-digital-mics-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idps-digital-mics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDPS + DIGITAL MICS"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-idps-digital-mics.dts b/qcom/yupikp-idps-digital-mics.dts new file mode 100644 index 000000000000..d798a6a6a2d0 --- /dev/null +++ b/qcom/yupikp-idps-digital-mics.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-idps-digital-mics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDPS + DIGITAL MICS"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-idps-digital-mics.dtsi b/qcom/yupikp-idps-digital-mics.dtsi new file mode 100644 index 000000000000..12c906256483 --- /dev/null +++ b/qcom/yupikp-idps-digital-mics.dtsi @@ -0,0 +1 @@ +#include "yupik-idps-digital-mics.dtsi" diff --git a/qcom/yupikp-qrd-overlay.dts b/qcom/yupikp-qrd-overlay.dts new file mode 100644 index 000000000000..307add32befa --- /dev/null +++ b/qcom/yupikp-qrd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP QRD"; + compatible = "qcom,yupikp-qrd", "qcom,yupikp", "qcom,qrd"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupikp-qrd.dts b/qcom/yupikp-qrd.dts new file mode 100644 index 000000000000..5bb5da05765a --- /dev/null +++ b/qcom/yupikp-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP QRD"; + compatible = "qcom,yupikp-qrd", "qcom,yupikp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupikp-qrd.dtsi b/qcom/yupikp-qrd.dtsi new file mode 100644 index 000000000000..aa5635d74c44 --- /dev/null +++ b/qcom/yupikp-qrd.dtsi @@ -0,0 +1 @@ +#include "yupik-qrd.dtsi" diff --git a/qcom/yupikp.dts b/qcom/yupikp.dts new file mode 100644 index 000000000000..2e9612abbc45 --- /dev/null +++ b/qcom/yupikp.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupikp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP SoC"; + compatible = "qcom,yupikp"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupikp.dtsi b/qcom/yupikp.dtsi new file mode 100644 index 000000000000..59bbff5be81e --- /dev/null +++ b/qcom/yupikp.dtsi @@ -0,0 +1,7 @@ +#include "yupik.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP"; + compatible = "qcom,yupikp"; + qcom,msm-id = <499 0x10000>; +}; From 5af26faaf2d6559a09eade42f94bbc0f30829958 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:43:44 +0530 Subject: [PATCH 0519/1809] ARM: dts: msm: Add UFS support for SDMSHRIKE Add UFS host controller and UFS PHY (attached to embedded UFS card) for SDMSHRIKE platform and SA8195P. Change-Id: I8a9ce2b24b88a8a76f294d1cdb0d6147986e00ab --- qcom/sa8195p.dtsi | 30 ++++++++++ qcom/sdmshrike.dtsi | 133 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 77cdf96d63eb..a4157c692c36 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -11,3 +11,33 @@ vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>; status = "ok"; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + vdda-phy-supply = <&pm8195_3_l5>; + vdda-pll-supply = <&pm8195_1_l9>; + vdda-phy-max-microamp = <138000>; + vdda-pll-max-microamp = <65100>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8195_3_l10>; + vcc-voltage-level = <2894000 2904000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8195_1_l11>; + vccq2-supply = <&pm8195_3_l7>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vccq-parent-supply = <&pm8195_1_s2>; + qcom,vccq-parent-max-microamp = <210000>; + + status= "ok"; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 57a88936e1df..a2dc9d377a90 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ aliases { serial0 = &uart2; + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ }; cpus { @@ -974,6 +976,137 @@ #freq-domain-cells = <2>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = + <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_UFS_MEM_0_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; From 48d5987170a37a6573951c61f4eb16e414095d9d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 1 Dec 2020 13:47:05 +0530 Subject: [PATCH 0520/1809] ARM: dts: msm: add PMIC devices for SCSHRIKE Add top level SPMI slave devices for PM8195. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: Ic6fc5967aef72f72398ef99057aa3fe9f84a1753 --- qcom/pm8195.dtsi | 307 ++++++++++++++++++++++++++++++++++++++++++ qcom/sa8195-pmic.dtsi | 1 + qcom/sdmshrike.dtsi | 24 ++++ 3 files changed, 332 insertions(+) create mode 100644 qcom/pm8195.dtsi diff --git a/qcom/pm8195.dtsi b/qcom/pm8195.dtsi new file mode 100644 index 000000000000..08ab33830f0f --- /dev/null +++ b/qcom/pm8195.dtsi @@ -0,0 +1,307 @@ +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8195@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8195_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8195_1_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm8195_1_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm8195_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_1_div_clk1", + "pm8195_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_1_rtc: qcom,pm8195_1_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8195_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8195_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100>; + }; + + }; + + qcom,pm8195@1 { + compatible ="qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm8195 */ + qcom,pm8195@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8195_2_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8195_2_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm8195_2_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8195_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_2_div_clk1", + "pm8195_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8195@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* below definitions are for the third instance of pm8195 */ + qcom,pm8195@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8195_3_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8195_3_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm8195_3_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8195_3_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_3_div_clk1", + "pm8195_3_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_3_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8195@9 { + compatible ="qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMIC GPIO pin control configurations */ +&pm8195_1_gpios { + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index b7685fdd1316..959c0d0ce208 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -69,3 +69,4 @@ }; #include "sa8195p-regulator.dtsi" +#include "pm8195.dtsi" diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index a2dc9d377a90..e7dfea7f3030 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDMSHRIKE"; @@ -1107,6 +1109,28 @@ status = "disabled"; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1000>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x700>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; From ee0d9122af007f6c127c72385213226993208594 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 8 Dec 2020 12:40:48 +0530 Subject: [PATCH 0521/1809] ARM: dts: msm: Add TUI support over SPI and I2C on LE VM for Yupik Adds SPI and I2 DTSI node support to enable Trusted VM usecase for TUI on Yupik. Client should enable the instance and run the usecase. Change-Id: I51b1ccc2fc7e7cc1ed4b4368d6ed06249bffa387 --- qcom/yupik-qupv3.dtsi | 12 +++++---- qcom/yupik-vm.dtsi | 61 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 5 deletions(-) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index 4d11215b0327..9bb6f89e0941 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -389,10 +389,12 @@ , , ; - qcom,gpii-mask = <0xff>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x7e>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; status = "ok"; }; @@ -636,8 +638,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se13_i2c_active>; pinctrl-1 = <&qupv3_se13_i2c_sleep>; - dmas = <&gpi_dma1 0 5 3 64 0>, - <&gpi_dma1 1 5 3 64 0>; + dmas = <&gpi_dma1 0 5 3 64 2>, + <&gpi_dma1 1 5 3 64 2>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; qcom,shared; @@ -658,8 +660,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se13_spi_active>; pinctrl-1 = <&qupv3_se13_spi_sleep>; - dmas = <&gpi_dma1 0 5 1 64 0>, - <&gpi_dma1 1 5 1 64 0>; + dmas = <&gpi_dma1 0 5 1 64 2>, + <&gpi_dma1 1 5 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index 9fbf122b960a..e07023a4627a 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -224,4 +224,65 @@ , ; }; + + /* Qup3_1 SE5: se_13 */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + status = "ok"; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x80>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 5 3 64 2>, + <&gpi_dma1 1 5 3 64 2>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + qcom,le-vm; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 5 1 64 2>, + <&gpi_dma1 1 5 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + qcom,le-vm; + status = "disabled"; + }; }; From 9f6522fa3ba896ecca65e8609ac4b68245e90dee Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 9 Dec 2020 15:53:42 +0530 Subject: [PATCH 0522/1809] ARM: dts: msm: Update labels for sdxnightjar regulators Update labels for all regulators so that clients can access the handles easily, Also add the proxy consumer support. Change-Id: I064749eac19ff32ef8e28b90d4903035e64c7cf7 --- qcom/sdxnightjar-regulator.dtsi | 53 ++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/qcom/sdxnightjar-regulator.dtsi b/qcom/sdxnightjar-regulator.dtsi index 32126cb2c986..3de4186dbb5b 100644 --- a/qcom/sdxnightjar-regulator.dtsi +++ b/qcom/sdxnightjar-regulator.dtsi @@ -4,7 +4,7 @@ /* PMD9650 S1 = VDD_MSS supply */ rpm-regulator-smpa1 { status = "okay"; - pmd9650_s1: regulator-s1 { + S1A: pmd9650_s1: regulator-s1 { regulator-name = "pmd9650_s1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; @@ -15,7 +15,7 @@ rpm-regulator-smpa2 { status = "okay"; - pmd9650_s2: regulator-s2 { + S2A: pmd9650_s2: regulator-s2 { regulator-name = "pmd9650_s2"; regulator-min-microvolt = <1256000>; regulator-max-microvolt = <1256000>; @@ -26,7 +26,7 @@ rpm-regulator-smpa3 { status = "okay"; - pmd9650_s3: regulator-s3 { + S3A: pmd9650_s3: regulator-s3 { regulator-name = "pmd9650_s3"; regulator-min-microvolt = <1024000>; regulator-max-microvolt = <1024000>; @@ -37,7 +37,7 @@ rpm-regulator-smpa4 { status = "okay"; - pmd9650_s4: regulator-s4 { + S4A: pmd9650_s4: regulator-s4 { regulator-name = "pmd9650_s4"; regulator-min-microvolt = <1856000>; regulator-max-microvolt = <1856000>; @@ -49,7 +49,9 @@ /* PMD9650 S5 = VDD_CX supply */ rpm-regulator-smpa5 { status = "okay"; - pmd9650_s5_level: regulator-s5-level { + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S5A_LEVEL: pmd9650_s5_level: regulator-s5-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmd9650_s5_level"; qcom,set = <3>; @@ -57,9 +59,16 @@ ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage =; qcom,use-voltage-level; }; + VDD_CX_LEVEL_AO: + S5A_LEVEL_AO: pmd9650_s5_level_ao: regulator-s5-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmd9650_s5_level_ao"; @@ -71,6 +80,8 @@ qcom,use-voltage-level; }; + VDD_CX_FLOOR_LEVEL: + S5A_FLOOR_LEVEL: pmd9650_s5_floor_level: regulator-s5-floor-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmd9650_s5_floor_level"; @@ -85,7 +96,7 @@ rpm-regulator-ldoa1 { status = "okay"; - pmd9650_l1: regulator-l1 { + L1A: pmd9650_l1: regulator-l1 { regulator-name = "pmd9650_l1"; regulator-min-microvolt = <1224000>; regulator-max-microvolt = <1224000>; @@ -96,7 +107,7 @@ rpm-regulator-ldoa2 { status = "okay"; - pmd9650_l2: regulator-l2 { + L2A: pmd9650_l2: regulator-l2 { regulator-name = "pmd9650_l2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -107,7 +118,7 @@ rpm-regulator-ldoa3 { status = "okay"; - pmd9650_l3: regulator-l3 { + L3A: pmd9650_l3: regulator-l3 { regulator-name = "pmd9650_l3"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -118,7 +129,7 @@ rpm-regulator-ldoa4 { status = "okay"; - pmd9650_l4: regulator-l4 { + L4A: pmd9650_l4: regulator-l4 { regulator-name = "pmd9650_l4"; regulator-min-microvolt = <928000>; regulator-max-microvolt = <928000>; @@ -129,7 +140,7 @@ rpm-regulator-ldoa5 { status = "okay"; - pmd9650_l5: regulator-l5 { + L5A: pmd9650_l5: regulator-l5 { regulator-name = "pmd9650_l5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -140,7 +151,7 @@ rpm-regulator-ldoa6 { status = "okay"; - pmd9650_l6: regulator-l6 { + L6A: pmd9650_l6: regulator-l6 { regulator-name = "pmd9650_l6"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -151,7 +162,7 @@ rpm-regulator-ldoa7 { status = "okay"; - pmd9650_l7: regulator-l7 { + L7A: pmd9650_l7: regulator-l7 { regulator-name = "pmd9650_l7"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2848000>; @@ -162,7 +173,7 @@ rpm-regulator-ldoa8 { status = "okay"; - pmd9650_l8: regulator-l8 { + L8A: pmd9650_l8: regulator-l8 { regulator-name = "pmd9650_l8"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -174,6 +185,9 @@ /* PMD9650 L9 = VDD_MX supply */ rpm-regulator-ldoa9 { status = "okay"; + proxy-supply = <&VDD_MX_LEVEL>; + VDD_MX_LEVEL: + L9A_LEVEL: pmd9650_l9_level: regulator-l9-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmd9650_l9_level"; @@ -182,13 +196,18 @@ ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage =; qcom,use-voltage-level; }; }; rpm-regulator-ldoa10 { status = "okay"; - pmd9650_l10: regulator-l10 { + L10A: pmd9650_l10: regulator-l10 { regulator-name = "pmd9650_l10"; regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; @@ -199,7 +218,7 @@ rpm-regulator-ldoa11 { status = "okay"; - pmd9650_l11: regulator-l11 { + L11A: pmd9650_l11: regulator-l11 { regulator-name = "pmd9650_l11"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2848000>; @@ -210,7 +229,7 @@ rpm-regulator-ldoa12 { status = "okay"; - pmd9650_l12: regulator-l12 { + L12A: pmd9650_l12: regulator-l12 { regulator-name = "pmd9650_l12"; regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; @@ -221,7 +240,7 @@ rpm-regulator-ldoa13 { status = "okay"; - pmd9650_l13: regulator-l13 { + L13A: pmd9650_l13: regulator-l13 { regulator-name = "pmd9650_l13"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2848000>; From 4681d73f53a4933c438adae2f8a4c0f14cf1c855 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Wed, 23 Dec 2020 16:29:49 +0800 Subject: [PATCH 0523/1809] ARM: dts: qcom: Add second trip to quiet-therm-usr for holi There are two clients in userspace who can request different trip thresholds to quiet-therm. Add another thermal zone trip node to quiet-therm for second client to configure its own threshold. Change-Id: I4f51ec03e13141c804c6b146e15665461a4383ee --- qcom/holi-pmic-overlay.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 2cc337167393..4909413fd031 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -356,6 +356,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; From 85a87cdee824dffc73cc9eb19a37e0454dd6d80d Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Wed, 23 Dec 2020 18:28:00 +0530 Subject: [PATCH 0524/1809] ARM: dts: msm: Add USB BAM device node on sdx12 This change adds USB BAM device node and required pipe configuration for USB QDSS BAM2BAM functionality. Change-Id: Id4b729acbe8f235f18cd6b89d43e7702d1013fa0 --- qcom/sdxnightjar-usb.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index e274820066d5..423d6e4b7253 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -53,6 +53,36 @@ maximum-speed = "super-speed"; dr_mode = "otg"; }; + + qcom,usbbam@0x8B04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x8b04000 0x1b000>; + interrupt-parent = <&intc>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x08604000>; + qcom,usb-bam-num-pipes = <1>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x00884000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0xc00>; + qcom,descriptor-fifo-offset = <0xc00>; + qcom,descriptor-fifo-size = <0x400>; + }; + }; }; qusb_phy: qusb@79000 { From e55d554ce767e8ccb4de53c1cea3a1bde1330fc5 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 11 Nov 2020 17:30:17 +0530 Subject: [PATCH 0525/1809] ARM: dts: msm: add UCSI connector and USB port on Yupik Add UCSI & USB port related information to allow USB role switch framework to discover connection, and provide USB role related configuration. Change-Id: I94aae8650d1034696bd5261a65640c3f9f69e813 --- qcom/yupik-usb.dtsi | 7 +++++++ qcom/yupik.dtsi | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 829de6693452..c33d2f3e6f02 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -42,6 +42,7 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + usb-role-switch; dwc3@a600000 { compatible = "snps,dwc3"; @@ -60,6 +61,12 @@ maximum-speed = "super-speed"; dr_mode = "otg"; }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; }; usb1: hsusb@8c00000 { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..1408502b1947 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1268,6 +1268,11 @@ qcom,ucsi { compatible = "qcom,ucsi-glink"; + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; }; altmode: qcom,altmode { From a1b5bab6fcdac09b84b1356281c05c68380651e5 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Wed, 25 Nov 2020 17:57:59 +0530 Subject: [PATCH 0526/1809] ARM: dts: msm: Add dtsi nodes for i2c, spi and hsuart Add dtsi nodes for i2c, spi and hsuart for sdxnightjar. Change-Id: Ic0c755c7642111aabc13b11bb05516244cd2e096 --- qcom/sdxnightjar-blsp.dtsi | 385 +++++++++++++++++++++++++++++++++++++ 1 file changed, 385 insertions(+) create mode 100644 qcom/sdxnightjar-blsp.dtsi diff --git a/qcom/sdxnightjar-blsp.dtsi b/qcom/sdxnightjar-blsp.dtsi new file mode 100644 index 000000000000..f6950a0c4149 --- /dev/null +++ b/qcom/sdxnightjar-blsp.dtsi @@ -0,0 +1,385 @@ +#include "sdxnightjar-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@0x7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x23000>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@78b5000 { /* BLSP1 QUP1 gpios 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@78B6000 { /* BLSP1 QUP2 gpios 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@78B7000 { /* BLSP1 QUP3 gpios 10, 11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@78B8000 { /* BLSP1 QUP4 gpios 14, 15 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78B8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + spi_1: spi@78B5000 { /* BLSP1 QUP1 gpios 0, 1, 2, 3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B5000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_2: spi@78B6000 { /* BLSP1 QUP2 gpios 4, 5, 6, 7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78B6000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_3: spi@78B7000 { /* BLSP1 QUP3 gpios 8, 9, 10, 11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B7000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_4: spi@78B8000 { /* BLSP1 QUP4 gpios 16, 17, 18, 19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x078B8000 0x600>, + <0x7884000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + status = "disabled"; + }; + + blsp1_uart1_hs: uart@78AF000 { /* BLSP1 UART1 gpios 0, 1, 2, 3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78AF000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 107 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 1 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@78B0000 { /* BLSP1 UART2 gpios 4, 5, 6, 7 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B0000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 108 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 5 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@78B1000 { /* BLSP1 UART3 gpios 8, 9, 10, 11 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B1000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 109 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 9 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_sleep>; + pinctrl-1 = <&blsp1_uart3_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@78B2000 { /* BLSP1 UART4 gpios 12, 13, 14, 15*/ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B2000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 13 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4_sleep>; + pinctrl-1 = <&blsp1_uart4_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@78B2000 { /* BLSP1 UART4b gpios 16, 17, 18, 19*/ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78B2000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 17 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_sleep>; + pinctrl-1 = <&blsp1_uart4b_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + status = "disabled"; + }; +}; From d8fbed3b75ea4cbe70226657a6caacd5e621171a Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Mon, 23 Nov 2020 17:13:48 +0530 Subject: [PATCH 0527/1809] ARM: dts: msm: Add camera device tree inclusions for Yupik camera Include camera device tree nodes to enable camera functionality on Yupik target. Change-Id: I3fcbd3eb89ae3363f01943a85f29190659af644c --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..aded71229ec2 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2072,3 +2072,4 @@ #include "msm-arm-smmu-yupik.dtsi" #include "yupik-qupv3.dtsi" #include "yupik-audio.dtsi" +#include "camera/yupik-camera.dtsi" From 3af3e42f8ef19a685d9ca7056c09d3398884dfe8 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 1 Nov 2020 23:31:07 +0530 Subject: [PATCH 0528/1809] dt-bindings: interconnect: add interconnect bindings Add interconnect device bindings. These devices can be used to describe any RPM and NoC based interconnect devices. Change-Id: Idb224692464f63d53dca7f0ca9bee1dd7fd1a43d --- bindings/interconnect/qcom,monaco.txt | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 bindings/interconnect/qcom,monaco.txt diff --git a/bindings/interconnect/qcom,monaco.txt b/bindings/interconnect/qcom,monaco.txt new file mode 100644 index 000000000000..2ac33b985abb --- /dev/null +++ b/bindings/interconnect/qcom,monaco.txt @@ -0,0 +1,46 @@ +QTI MONACO Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,monaco-bimc", + "qcom,monaco-system_noc", + "qcom,monaco-config_noc", + "qcom,monaco-clk_virt", + "qcom,monaco-mmnrt_virt", + "qcom,monaco-mmrt_virt", +- #interconnect-cells : should contain 1 + +reg : specifies the physical base address and size of registers +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus" and "bus_a" + +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + +Examples: + +soc { + ... + system_noc: interconnect@1880000 { + reg = <0x1880000 0x5e200>; + compatible = "qcom,monaco-system_noc"; + qcom,util-factor = <142>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x1900000 0xa400>; + compatible = "qcom,monaco-config_noc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; +}; From e03b6b6260878c172f4b5878bb2d3b5a460fb852 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 12 Oct 2020 22:25:13 +0800 Subject: [PATCH 0529/1809] ARM: dts: msm: Add dcc node for yupik Add dcc node for yupik to support dcc dump. Disable DCC first for dependency on DCC virtualization. Change-Id: Icf7f5bddfac8b42d68d94a1825344178221b5aab --- qcom/yupik.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..b29fb77ddd40 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -534,6 +534,18 @@ status = "ok"; }; + dcc: dcc_v2@117f000 { + compatible = "qcom,dcc-v2"; + reg = <0x117f000 0x1000>, + <0x1112000 0x6000>; + + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x12000>; + status = "disabled"; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; From 4136653f2acea71d04741532b4405007da6b910f Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Thu, 26 Nov 2020 11:56:43 +0800 Subject: [PATCH 0530/1809] ARM: dts: msm: Update memory map for SDXNIGHTJAR target Update the memory map for SDXNIGHTJAR target per the v1 memory map. Change-Id: Idd52b9ef8d4682fc8ef35d4019abe3ca3a112596 --- qcom/sdxnightjar.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8337f22edeb9..8f86692b9b3a 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -19,7 +19,7 @@ reg = <0 0>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; @@ -32,9 +32,21 @@ peripheral2_mem: peripheral2_region@0x87d00000 { no-map; - reg = <0x87d00000 0x300000>; + reg = <0x87d00000 0x100000>; label = "peripheral2_mem"; }; + + smem_mem: smem_region@0x87e80000 { + no-map; + reg = <0x87e80000 0xc0000>; + label = "smem_mem"; + }; + + mss_mem: mss_region@0x88000000 { + no-map; + reg = <0x88000000 0x7300000>; + label = "mss_mem"; + }; }; aliases { }; From 65bff870a40c0e7023f7ffb4e45b974de4863fdf Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 12 Oct 2020 22:47:47 +0800 Subject: [PATCH 0531/1809] ARM: dts: msm: Add coreisght device tree for yupik Add coresight config to device tree for yupik. Change-Id: Ic52bd4c31b33741b779defe40883ef64002cde85 --- qcom/yupik-coresight.dtsi | 3347 +++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 3348 insertions(+) create mode 100644 qcom/yupik-coresight.dtsi diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi new file mode 100644 index 000000000000..5a75371c6b43 --- /dev/null +++ b/qcom/yupik-coresight.dtsi @@ -0,0 +1,3347 @@ +&soc { + replicator_qdss: replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", + "arm,primecell"; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_cx_in_swao_out: endpoint { + remote-endpoint= + <&replicator_swao_out_cx_in>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator0_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator0>; + }; + }; + }; + }; + + replicator_swao: replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", + "arm,primecell"; + + reg = <0x6b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_swao_in_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@0 { + reg = <0>; + replicator_swao_out_cx_in: endpoint { + remote-endpoint = + <&replicator_cx_in_swao_out>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + + tmc_etf_swao: tmc@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-csr = <&swao_csr>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_swao_in_funnel_swao: endpoint { + remote-endpoint= + <&funnel_swao_out_tmc_etf_swao>; + }; + }; + }; + + out-ports { + port { + tmc_etf_swao_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf_swao>; + }; + }; + + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04a0 0>, + <&apps_smmu 0x04c0 0>; + + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + arm,scatter-gather; + + qcom,sw-usb; + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; + coresight-csr = <&csr>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + in-ports { + port { + tmc_etr_in_replicator0: endpoint { + remote-endpoint = + <&replicator0_out_tmc_etr>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm@6b46000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + out-ports { + port { + tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_tpdm_lpass_lpi>; + }; + }; + }; + }; + + funnel_lpass_lpi: funnel@6b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi"; + + out-ports { + port { + funnel_lpass_lpi_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_lpass_lpi>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi>; + }; + }; + }; + }; + + funnel_swao: funnel@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@5 { + reg = <5>; + funnel_swao_in_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_out_funnel_swao>; + }; + }; + + port@6 { + reg = <6>; + funnel_swao_in_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_out_funnel_swao>; + }; + }; + + port@7 { + reg = <7>; + funnel_swao_in_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_out_funnel_swao>; + }; + }; + }; + + out-ports { + port { + funnel_swao_out_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_in_funnel_swao>; + }; + }; + + }; + }; + + tpda_swao: tpda@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6b08000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + qcom,dsb-elem-size = <4 32>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_swao_in_tpdm_swao_p0: endpoint { + remote-endpoint = + <&tpdm_swao_p0_out_tpda_swao>; + }; + }; + + port@1 { + reg = <1>; + tpda_swao_in_tpdm_swao_p1: endpoint { + remote-endpoint = + <&tpdm_swao_p1_out_tpda_swao>; + }; + }; + + port@2 { + reg = <2>; + tpda_swao_in_tpdm_swao_p2: endpoint { + remote-endpoint = + <&tpdm_swao_p2_out_tpda_swao>; + }; + }; + + port@3 { + reg = <3>; + tpda_swao_in_tpdm_swao_p3: endpoint { + remote-endpoint = + <&tpdm_swao_p3_out_tpda_swao>; + }; + }; + + port@4 { + reg = <4>; + tpda_swao_in_tpdm_swao1: endpoint { + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + }; + }; + }; + + tpdm_swao_p0: tpdm@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + + reg = <0x6b09000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p0_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p0>; + }; + }; + }; + }; + + tpdm_swao_p1: tpdm@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + + reg = <0x6b0a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p1_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p1>; + }; + }; + }; + }; + + tpdm_swao_p2: tpdm@6b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + + reg = <0x6b0b000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p2_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p2>; + }; + }; + }; + }; + + tpdm_swao_p3: tpdm@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + + reg = <0x6b0c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p3_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p3>; + }; + }; + }; + }; + + tpdm_swao1: tpdm@6b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6b0d000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@1 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@6b0f000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0f000 0x1000>, + <0x6b0f0f8 0x50>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in0_in_snoc: endpoint { + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <3>; + funnel_qatb_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_qatb>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@4 { + reg = <4>; + funnel_in1_in_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + + port@6 { + reg = <6>; + funnel_in1_in_funnel_dlct5: endpoint { + remote-endpoint = + <&funnel_dlct5_out_funnel_in1>; + }; + }; + }; + }; + + funnel_dlct5: funnel@6c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6c38000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct5"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_dlct5_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dlct5>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlct5_in_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_out_funnel_dlct5>; + }; + }; + + port@6 { + reg = <6>; + funnel_dlct5_in_funnel_dl_turing: endpoint { + remote-endpoint = + <&funnel_dl_turing_out_funnel_dlct5>; + }; + }; + }; + }; + + tpda_dlct5: tpda@6c37000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6c37000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-dlct_5"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <11 64>, + <12 64>, + <15 32>, + <21 32>, + <22 64>, + <28 64>; + qcom,dsb-elem-size = <4 32>, + <5 32>, + <8 32>, + <14 32>, + <19 32>, + <27 32>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_dlct5_out_funnel_dlct5: endpoint { + remote-endpoint = + <&funnel_dlct5_in_tpda_dlct5>; + }; + + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@2 { + reg = <2>; + tpda_dlct5_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_tpda_dlct5>; + }; + }; + + port@5 { + reg = <5>; + tpda_dlct5_in_tpdm_dlct_1: endpoint { + remote-endpoint = + <&tpdm_dlct_1_out_tpda_dlct5>; + }; + }; + + port@8 { + reg = <8>; + tpda_dlct5_in_tpdm_mdss: endpoint { + remote-endpoint = + <&tpdm_mdss_out_tpda_dlct5>; + }; + }; + + port@b { + reg = <11>; + tpda_dlct5_in_funnel_dlct_1_11: endpoint { + remote-endpoint = + <&funnel_dlct_1_11_out_tpda_dlct5>; + }; + }; + + port@c { + reg = <12>; + tpda_dlct5_in_funnel_dlct_1_12: endpoint { + remote-endpoint = + <&funnel_dlct_1_12_out_tpda_dlct5>; + }; + }; + + port@e { + reg = <14>; + tpda_dlct5_14_in_tpdm_turing: endpoint { + remote-endpoint = + <&tpdm_turing_out_tpda_dlct5_14>; + }; + }; + + port@f { + reg = <15>; + tpda_dlct5_15_in_tpdm_llm_turing: endpoint { + remote-endpoint = + <&tpdm_llm_turing_out_tpda_dlct5_15>; + }; + }; + + port@13 { + reg = <19>; + tpda_dlct5_in_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_out_tpda_dlct5>; + }; + }; + + port@14 { + reg = <20>; + tpda_dlct5_20_in_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_out_tpda_dlct5_20>; + }; + }; + + port@15 { + reg = <21>; + tpda_dlct5_21_in_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_out_tpda_dlct5_21>; + }; + }; + + port@18 { + reg = <27>; + tpda_dlct5_in_tpdm_dlct5_0: endpoint { + remote-endpoint = + <&tpdm_dlct5_0_out_tpda_dlct5>; + }; + }; + + port@19 { + reg = <28>; + tpda_dlct5_in_tpdm_dlct5_1: endpoint { + remote-endpoint = + <&tpdm_dlct5_1_out_tpda_dlct5>; + }; + }; + }; + }; + + + funnel_lpass: funnel@6846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_lpass_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_funnel_lpass>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@6844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_dlct_1: tpdm@6c08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6c08000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct_1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_dlct_1_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_tpdm_dlct_1>; + }; + }; + }; + }; + + tpdm_mdss: tpdm@6c60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6c60000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mdss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_mdss_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_tpdm_mdss>; + }; + }; + }; + }; + + tpdm_rdpm: tpdm@6ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6ac0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_out_funnel_dlct_1_0: endpoint { + remote-endpoint = + <&funnel_dlct_1_0_in_tpdm_rdpm>; + }; + }; + }; + }; + + tpdm_rdpm_mx: tpdm@6ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6ac1000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-mx"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_mx_out_funnel_dlct_1_1: endpoint { + remote-endpoint = + <&funnel_dlct_1_1_in_tpdm_rdpm_mx>; + }; + }; + }; + }; + + funnel_dlct_1: funnel@6ac2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6ac2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlct_1_11_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_funnel_dlct_1_11>; + source = <&tpdm_rdpm>; + }; + }; + + port@1 { + reg = <1>; + funnel_dlct_1_12_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_funnel_dlct_1_12>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlct_1_0_in_tpdm_rdpm: endpoint { + remote-endpoint = + <&tpdm_rdpm_out_funnel_dlct_1_0>; + }; + }; + + port@1 { + reg = <1>; + funnel_dlct_1_1_in_tpdm_rdpm_mx: endpoint { + remote-endpoint = + <&tpdm_rdpm_mx_out_funnel_dlct_1_1>; + }; + }; + }; + }; + + tpdm_turing: tpdm@6980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + out-ports { + port { + turing_etm_out_funnel_dup_turing: endpoint { + remote-endpoint = + <&funnel_dup_turing_in_turing_etm>; + }; + }; + }; + }; + + tpdm_llm_turing: tpdm@69810000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-turing-llm"; + qcom,dummy-source; + + out-ports { + port { + tpdm_llm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_llm_turing>; + }; + }; + }; + }; + + funnel_turing: funnel@6985000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6985000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpdm_turing_out_tpda_dlct5_14: endpoint { + remote-endpoint = + <&tpda_dlct5_14_in_tpdm_turing>; + source = <&tpdm_turing>; + }; + }; + + port@1 { + reg = <1>; + tpdm_llm_turing_out_tpda_dlct5_15: endpoint { + remote-endpoint = + <&tpda_dlct5_15_in_tpdm_llm_turing>; + source = <&tpdm_llm_turing>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_turing_out_funnel_dlct5: endpoint { + remote-endpoint = + <&funnel_dlct5_in_funnel_dl_turing>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_in_tpdm_llm_turing: endpoint { + remote-endpoint = + <&tpdm_llm_turing_out_funnel_turing>; + }; + }; + + port@4 { + reg = <4>; + turing_in_turing_dup: endpoint { + remote-endpoint = + <&turing_dup_out_turing>; + }; + }; + }; + }; + + funnel_dup_turing: funnel@6986000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6986000 0x1000>, + <0x6985000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing_dup"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + out-ports { + port { + turing_dup_out_turing: endpoint { + remote-endpoint = + <&turing_in_turing_dup>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@3 { + reg = <3>; + funnel_dup_turing_in_turing_etm: endpoint { + remote-endpoint = + <&turing_etm_out_funnel_dup_turing>; + }; + }; + }; + }; + + tpdm_ddr_ch01: tpdm@6e10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x06e10000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch01"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_ddr_ch01_out_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_in_tpdm_ddr_ch01>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@6e00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x06e00000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_ddr_out_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_in_tpdm_ddr>; + }; + }; + }; + }; + + tpdm_shrm: tpdm@6e01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x06e01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-shrm"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_shrm_out_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_in_tpdm_shrm>; + }; + }; + }; + }; + + funnel_ddr_0: funnel@6e05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6e05000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_ddr_0_out_tpda_dlct5_20: endpoint { + remote-endpoint = + <&tpda_dlct5_20_in_funnel_ddr_0>; + source = <&tpdm_ddr>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_0_out_tpda_dlct5_21: endpoint { + remote-endpoint = + <&tpda_dlct5_21_in_funnel_ddr_0>; + source = <&tpdm_shrm>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_0_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_funnel_ddr_0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_ddr_0_in_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_out_funnel_ddr_0>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_0_in_tpdm_ddr: endpoint { + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_0_in_tpdm_shrm: endpoint { + remote-endpoint = + <&tpdm_shrm_out_funnel_ddr_0>; + }; + }; + }; + }; + + funnel_ddr_ch01: funnel@6e12000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6e12000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-ch01"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ddr_ch01_out_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_in_funnel_ddr_ch01>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_ddr_ch01_in_tpdm_ddr_ch01: endpoint { + remote-endpoint = + <&tpdm_ddr_ch01_out_funnel_ddr_ch01>; + }; + }; + }; + }; + + tpdm_dlct5_0: tpdm@6c30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x06c30000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct5_0"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_dlct5_0_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_tpdm_dlct5_0>; + }; + }; + }; + }; + + tpdm_dlct5_1: tpdm@6c31000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x06c31000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct5_1"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_dlct5_1_out_tpda_dlct5: endpoint { + remote-endpoint = + <&tpda_dlct5_in_tpdm_dlct5_1>; + }; + }; + }; + }; + + funnel_modem: funnel@6804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_in_funnel_mq6_dup: endpoint { + remote-endpoint = + <&funnel_mq6_dup_out_funnel_modem>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + funnel_modem_q6: funnel@680c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x680c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem-q6"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_modem_q6_out_funnel_mq6_dup: endpoint { + remote-endpoint = + <&funnel_mq6_dup_in_funnel_modem_q6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_modem_q6_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6>; + }; + }; + }; + }; + + funnel_mq6_dup: funnel@680d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x680d000 0x1000>, + <0x680c000 0x1000>; + + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem-q6_dup"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + out-ports { + port { + funnel_mq6_dup_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_mq6_dup>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + funnel_mq6_dup_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_mq6_dup>; + }; + }; + + port@2 { + reg = <2>; + funnel_mq6_dup_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_mq6_dup>; + }; + }; + }; + }; + + modem_diag: dummy_source { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + + out-ports { + port { + modem_diag_out_funnel_mq6_dup: endpoint { + remote-endpoint = + <&funnel_mq6_dup_in_modem_diag>; + }; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + out-ports { + port { + modem_etm0_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_etm0>; + }; + }; + }; + }; + + tpda_modem: tpda@6803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_in_tpdm_modem_0: endpoint { + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_in_tpdm_modem_1: endpoint { + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@6800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_modem_0_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_0>; + }; + }; + }; + }; + + tpdm_modem_1: tpdm@6801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6801000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-1"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + out-ports { + port { + tpdm_modem_1_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_1>; + }; + }; + }; + }; + + funnel_apss_merg: funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + + }; + }; + + etm0: etm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7040000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm0>; + }; + }; + }; + }; + + etm1: etm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7140000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm1>; + }; + }; + }; + }; + + etm2: etm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm2>; + }; + }; + }; + }; + + etm3: etm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm3>; + }; + }; + }; + }; + + etm4: etm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7440000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm4_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm4>; + }; + }; + }; + }; + + etm5: etm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7540000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm5_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm5>; + }; + }; + }; + }; + + etm6: etm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7640000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm6_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm6>; + }; + }; + }; + }; + + etm7: etm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7740000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm7_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm7>; + }; + }; + }; + }; + + funnel_apss: funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@1 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + + port@6 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + + port@7 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + snoc: snoc { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-snoc"; + qcom,dummy-source; + + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <25 32>, + <31 32>; + qcom,tc-elem-size = <31 32>; + qcom,dsb-elem-size = <10 32>, + <21 32>, + <25 32>, + <26 64>, + <31 32>; + qcom,cmb-elem-size = <5 32>, + <6 32>, + <23 32>, + <24 32>, + <27 32>, + <28 32>, + <29 32>, + <31 64>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@5 { + reg = <5>; + tpda_5_in_funnel_dlet: endpoint { + remote-endpoint = + <&funnel_dlet_out_tpda_5>; + }; + }; + + port@6 { + reg = <6>; + tpda_6_in_funnel_dlet: endpoint { + remote-endpoint = + <&funnel_dlet_out_tpda_6>; + }; + }; + + port@a { + reg = <10>; + tpda_10_in_funnel_dlet: endpoint { + remote-endpoint = + <&funnel_dlet_out_tpda_10>; + }; + }; + + port@15 { + reg = <21>; + tpda_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda>; + }; + }; + + port@17 { + reg = <23>; + tpda_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + port@18 { + reg = <24>; + tpda_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@19 { + reg = <25>; + tpda_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + + port@1a { + reg = <26>; + tpda_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tpda>; + }; + }; + + port@1b { + reg = <27>; + tpda_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@1c { + reg = <28>; + tpda_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda>; + }; + }; + + port@1d { + reg = <29>; + tpda_in_tpdm_sdcc_2: endpoint { + remote-endpoint = + <&tpdm_sdcc_2_out_tpda>; + }; + }; + + port@1f { + reg = <31>; + tpda_in_tpdm_pimem: endpoint { + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + }; + }; + + tpdm_wpss_0: tpdm@6c70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + + reg = <0x6c70000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-wpss-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss_0>; + }; + }; + }; + }; + + wpss_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-wpss-etm0"; + qcom,inst-id = <3>; + + out-ports { + port { + wpss_etm0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_wpss_etm0>; + }; + }; + }; + }; + + funnel_wpss: funnel@6c73000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6c73000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wpss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_wpss_in_tpdm_wpss_0: endpoint { + remote-endpoint = + <&tpdm_wpss_0_out_funnel_wpss>; + }; + }; + + + port@2 { + reg = <2>; + funnel_wpss_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_funnel_wpss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_wpss_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_wpss>; + source = <&tpdm_wpss_0>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_wpss>; + }; + }; + }; + }; + + funnel_dlet: funnel@6c2e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6c2e000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlet"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlet_out_tpda_5: endpoint { + remote-endpoint = + <&tpda_5_in_funnel_dlet>; + source = <&tpdm_sdcc_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_dlet_out_tpda_6: endpoint { + remote-endpoint = + <&tpda_6_in_funnel_dlet>; + source = <&tpdm_sdcc_4>; + }; + }; + + port@2 { + reg = <2>; + funnel_dlet_out_tpda_10: endpoint { + remote-endpoint = + <&tpda_10_in_funnel_dlet>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@4 { + reg = <4>; + funnel_dlet_in_tpdm_sdcc_1: endpoint { + remote-endpoint = + <&tpdm_sdcc_1_out_funnel_dlet>; + }; + }; + + port@5 { + reg = <5>; + funnel_dlet_in_tpdm_sdcc_4: endpoint { + remote-endpoint = + <&tpdm_sdcc_4_out_funnel_dlet>; + }; + }; + + port@7 { + reg = <7>; + funnel_dlet_in_tpdm_dlet: endpoint { + remote-endpoint = + <&tpdm_dlet_out_funnel_dlet>; + }; + }; + }; + }; + + tpdm_sdcc_1: tpdm@684e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x684e000 0x1000>; + reg-names = "tpdm-base"; + qcom,cmb-msr-skip; + + coresight-name = "coresight-tpdm-sdcc-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_1_out_funnel_dlet: endpoint { + remote-endpoint = + <&funnel_dlet_in_tpdm_sdcc_1>; + }; + }; + }; + }; + + tpdm_sdcc_4: tpdm@6859000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6859000 0x1000>; + reg-names = "tpdm-base"; + qcom,cmb-msr-skip; + + coresight-name = "coresight-tpdm-sdcc-4"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_4_out_funnel_dlet: endpoint { + remote-endpoint = <&funnel_dlet_in_tpdm_sdcc_4>; + }; + }; + }; + }; + + tpdm_dlet: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlet"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlet_out_funnel_dlet: endpoint { + remote-endpoint = <&funnel_dlet_in_tpdm_dlet>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_prng: tpdm@6841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@682c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x682c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@600f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x600f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_spdm>; + }; + }; + }; + }; + + tpdm_sdcc_2: tpdm@684f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x684f000 0x1000>; + reg-names = "tpdm-base"; + qcom,cmb-msr-skip; + + coresight-name = "coresight-tpdm-sdcc-2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_2_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_sdcc_2>; + }; + }; + }; + }; + + tpdm_pimem: tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + }; + + tpda_apss: tpda@7863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x7863000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <3 64>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 64>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss>; + }; + }; + + port@1 { + reg = <1>; + tpda_apss_in_tpdm_llm_gold: endpoint { + remote-endpoint = + <&tpdm_llm_gold_out_tpda_apss>; + }; + }; + + port@2 { + reg = <2>; + tpda_apss_in_tpdm_actpm: endpoint { + remote-endpoint = + <&tpdm_actpm_out_tpda_apss>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_in_tpdm_apss: endpoint { + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_gold_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_gold>; + }; + }; + }; + }; + + tpdm_actpm: tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_actpm_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_actpm>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x7861000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + out-ports { + port { + audio_etm0_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_audio_etm0>; + }; + }; + }; + }; + + ipcb_tgu: tgu@6b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + reg = <0x06b0e000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_apss: cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_apss: cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_apss: cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_ddr_ch01: cti@6e11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6e11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_ch01_dl_cti_0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr0: cti@6e02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6e02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@6e0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6e0c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@6e0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6e0d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_ddr1: cti@6e0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6e0e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_gpu_isdb: cti@6961000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6961000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass: cti@6845000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6845000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass_dl_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_lpi: cti@6b41000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b41000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti_lpass_lpi_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_q6: cti@6b4b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b4b000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-lpass_q6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mdss: cti@6c61000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6c61000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mdss_dl_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@680b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x680b000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti_mss_q6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_vq6: cti@6813000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6813000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-mss_vq6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_titan: cti@6c13000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6c13000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-sierra_a6_cti"; + status = "disabled"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_swao:cti@6b00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b00000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao:cti@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b01000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao:cti@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing:cti@6982000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6982000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing_dl_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing_q6:cti@698b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x698b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing_q6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu0: cti@7020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7020000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu1: cti@7120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7120000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@7220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7220000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@7320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7320000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@7420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7420000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@7520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7520000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@7620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7620000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@7720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7720000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..195641a233c4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1930,6 +1930,7 @@ }; #include "shima-gdsc.dtsi" +#include "yupik-coresight.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-pm.dtsi" #include "ipcc-test-yupik.dtsi" From 737ca43c8d446b4be90058a87e5304ba22d2b0b3 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 23 Dec 2020 11:58:57 +0530 Subject: [PATCH 0532/1809] ARM: dts: qcom: add refgen regulator device for yupik Add a refgen-regulator device for the South refgen used by the DSI PHY. Change-Id: Ic7e7ef11f5fd24dc2190cbcd2f3075eea995a400 --- qcom/yupik-regulators.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index 9e45d4640ba9..a6bab1707981 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -912,3 +912,14 @@ }; }; }; + +&soc { + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-kona-regulator"; + reg = <0x88e7000 0x84>; + regulator-name = "refgen"; + proxy-supply = <&refgen>; + qcom,proxy-consumer-enable; + regulator-enable-ramp-delay = <5>; + }; +}; From 9c05d5e75dafe9bc16bd2b35a2d1d4ca58e58293 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Sun, 27 Dec 2020 22:03:02 +0530 Subject: [PATCH 0533/1809] ARM: dts: msm: define mem offline node in yupik Define the memory offline node in yupik. This node defines the offlineable memory size used by PASR. Change-Id: Ic70703300f3b73d950a611b6c50307a2df76514a --- qcom/yupik.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..31f9d325512a 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -25,6 +25,15 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ From 198c2e585a842577ac55c4a427a5cbbafc1e22ad Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Thu, 24 Dec 2020 21:30:58 +0530 Subject: [PATCH 0534/1809] ARM: dts: msm: Add SMMU devices for sdmshrike Add the device tree nodes that describe the APPS and graphics SMMU for sdmshrike target. Change-Id: Id35fc89251d834f7fd3d82555ec8fa6c82303ab0 --- qcom/msm-arm-smmu-sdmshrike.dtsi | 378 +++++++++++++++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + 2 files changed, 379 insertions(+) create mode 100644 qcom/msm-arm-smmu-sdmshrike.dtsi diff --git a/qcom/msm-arm-smmu-sdmshrike.dtsi b/qcom/msm-arm-smmu-sdmshrike.dtsi new file mode 100644 index 000000000000..28a31ba15cd7 --- /dev/null +++ b/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -0,0 +1,378 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02CA0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02CA0000 0x10000>, + <0x2CC2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,dynamic; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC5000 0x1000>, + <0x2CC2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC9000 0x1000>, + <0x2CC2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + gfx_2_tbu: gfx_2_tbu@0x2CCD000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CCD000 0x1000>, + <0x2CC2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + }; + + gfx_3_tbu: gfx_3_tbu@0x2CD1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CD1000 0x1000>, + <0x2CC2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518D000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,active-only; + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,active-only; + interconnects = <&compute_noc MASTER_NPU + &compute_noc SLAVE_CDSP_MEM_NOC>; + }; + + adsp_tbu: adsp_tbu@0x1519D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519D000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_pcie: anoc_pcie@151A1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151A5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + qcom,iommu-dma = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x303>, + <0x400 0x3ff 0x303>, + <0x800 0x3ff 0x303>, + <0xc00 0x3ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF0/1, SF TBU +3 PF */ + <0x800 0x3ff 0x103>, + <0xc00 0x3ff 0x103>, + <0x2000 0x3ff 0x103>, + + /* NPU SIDs: +15 deep PF */ + <0x1480 0x7 0x303>, + <0x1080 0x7 0x303>; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index e7dfea7f3030..1f903bce965f 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1432,6 +1432,7 @@ #include "sm8150-pm.dtsi" #include "sa8195-smp2p.dtsi" #include "sa8195-gdsc.dtsi" +#include "msm-arm-smmu-sdmshrike.dtsi" &emac_gdsc { status = "ok"; From 737887d9b5b164a01bec37e52fe9d79b8a09ae31 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 23 Dec 2020 17:15:21 +0530 Subject: [PATCH 0535/1809] ARM: dts: msm: Update ion heap for scuba Update ION heap for scuba. Change-Id: I47d3f202d5e3380e4ce0b4d57d0133d2d24a15b7 --- qcom/scuba-ion.dtsi | 13 +++++++------ qcom/scuba-iot-idp.dtsi | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/qcom/scuba-ion.dtsi b/qcom/scuba-ion.dtsi index cba6f834d9d9..c19c0bf75298 100644 --- a/qcom/scuba-ion.dtsi +++ b/qcom/scuba-ion.dtsi @@ -1,3 +1,4 @@ +#include &soc { qcom,ion { compatible = "qcom,msm-ion"; @@ -5,29 +6,29 @@ #size-cells = <0>; system_heap: qcom,ion-heap@25 { - reg = <25>; - qcom,ion-heap-type = "SYSTEM"; + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; }; system_secure_heap: qcom,ion-heap@9 { - reg = <9>; + reg = ; qcom,ion-heap-type = "SYSTEM_SECURE"; }; qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ - reg = <10>; + reg = ; memory-region = <&secure_display_memory>; qcom,ion-heap-type = "HYP_CMA"; }; qcom,ion-heap@27 { /* QSEECOM HEAP */ - reg = <27>; + reg = ; memory-region = <&qseecom_mem>; qcom,ion-heap-type = "DMA"; }; qcom,ion-heap@19 { /* QSEECOM HEAP */ - reg = <19>; + reg = ; memory-region = <&qseecom_ta_mem>; qcom,ion-heap-type = "DMA"; }; diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi index d0b147079ba0..91456469df2f 100644 --- a/qcom/scuba-iot-idp.dtsi +++ b/qcom/scuba-iot-idp.dtsi @@ -1,5 +1,6 @@ #include #include +#include "scuba-ion.dtsi" &soc { scuba_batterydata: qcom,battery-data { From 6334e3c800ca9b6adf9f4ec45399a3080e0a4fd1 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 8 Dec 2020 23:11:39 +0530 Subject: [PATCH 0536/1809] ARM: dts: msm: Rectify all BLSP QUP nodes with correct clocks This change corrects clock nodes for each QUP instance for sdxnightjar. Also correct the interconnect end points for each BLSP QUP instance. Change-Id: I3b3c85b82c23b0e103a2ac11b8c009593dda586a --- qcom/sdxnightjar-blsp.dtsi | 78 +++++++++++++++++++------------------- qcom/sdxnightjar.dtsi | 1 + 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/qcom/sdxnightjar-blsp.dtsi b/qcom/sdxnightjar-blsp.dtsi index f6950a0c4149..6fa8b09ba546 100644 --- a/qcom/sdxnightjar-blsp.dtsi +++ b/qcom/sdxnightjar-blsp.dtsi @@ -33,12 +33,12 @@ dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_1_active>; pinctrl-1 = <&i2c_1_sleep>; @@ -56,12 +56,12 @@ dmas = <&dma_blsp1 10 64 0x20000020 0x20>, <&dma_blsp1 11 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; @@ -79,12 +79,12 @@ dmas = <&dma_blsp1 12 64 0x20000020 0x20>, <&dma_blsp1 13 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; @@ -102,12 +102,12 @@ dmas = <&dma_blsp1 14 64 0x20000020 0x20>, <&dma_blsp1 15 32 0x20000020 0x20>; dma-names = "tx", "rx"; - qcom,master-id = <86>; + qcom,master-id = ; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; @@ -129,14 +129,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <8>; qcom,bam-producer-pipe-index = <9>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_1_active>; pinctrl-1 = <&spi_1_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; status = "disabled"; }; @@ -155,14 +155,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <10>; qcom,bam-producer-pipe-index = <11>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_2_active>; pinctrl-1 = <&spi_2_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; status = "disabled"; }; @@ -181,14 +181,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <12>; qcom,bam-producer-pipe-index = <13>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_3_active>; pinctrl-1 = <&spi_3_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; status = "disabled"; }; @@ -207,14 +207,14 @@ qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <14>; qcom,bam-producer-pipe-index = <15>; - qcom,master-id = <86>; + qcom,master-id = ; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_4_active>; pinctrl-1 = <&spi_4_sleep>; clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, - <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; status = "disabled"; }; @@ -240,14 +240,14 @@ qcom,bam-rx-ep-pipe-index = <1>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart1_sleep>; pinctrl-1 = <&blsp1_uart1_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -273,14 +273,14 @@ qcom,bam-rx-ep-pipe-index = <3>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2_sleep>; pinctrl-1 = <&blsp1_uart2_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -306,14 +306,14 @@ qcom,bam-rx-ep-pipe-index = <5>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_sleep>; pinctrl-1 = <&blsp1_uart3_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -339,14 +339,14 @@ qcom,bam-rx-ep-pipe-index = <7>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4_sleep>; pinctrl-1 = <&blsp1_uart4_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; @@ -372,14 +372,14 @@ qcom,bam-rx-ep-pipe-index = <7>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4b_sleep>; pinctrl-1 = <&blsp1_uart4b_active>; interconnect-names = "blsp-ddr"; - interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; status = "disabled"; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8337f22edeb9..033cddbd138e 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -713,3 +713,4 @@ #include "sdxnightjar-regulator.dtsi" #include "sdxnightjar-usb.dtsi" #include "sdxnightjar-pinctrl.dtsi" +#include "sdxnightjar-blsp.dtsi" From 1e489ea670636359227d68f1a2941945608b779e Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 12 Oct 2020 22:33:50 +0800 Subject: [PATCH 0537/1809] ARM: dts: msm: Add mem_dump node for yupik Add mem_dump node for yupik to support memory dump feature. Change-Id: I1875d8c0532bc0d3cd1c073b81fcce208f927ee5 --- qcom/yupik.dtsi | 362 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 362 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..8d1af5d9f802 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -383,6 +383,13 @@ size = <0x0 0x2000000>; linux,cma-default; }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x2c00000>; + }; }; soc: soc { }; @@ -1927,6 +1934,361 @@ qcom,client-id = <0x00000001>; qcom,vm-nav-path; }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c200_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c300_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c400_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x134>; + }; + + c500_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x135>; + }; + + c600_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x136>; + }; + + c700_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x137>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x32100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; + + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x3a0>; + qcom,dump-id = <0x47>; + }; + + l2_cache400 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x120100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0xc100>; + qcom,dump-id = <0x127>; + }; + + gemnoc { + qcom,dump-size = <0x100000>; + qcom,dump-id = <0x162>; + }; + + mhm_scan { + qcom,dump-size = <0x20000>; + qcom,dump-id = <0x161>; + }; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x140>; + }; + + LLCC_2: llcc_2_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x141>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; }; #include "shima-gdsc.dtsi" From f28a68723fe4d22130f40ee4fd79821e579de648 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Mon, 21 Dec 2020 12:13:37 +0530 Subject: [PATCH 0538/1809] ARM: dts: msm: Update CMA region for monaco . Update CMA memory region . fix compilation error for monaco-ion. Change-Id: I66469ae2147c567ce8805dcdc452c8d334b4cbb6 --- qcom/monaco-ion.dtsi | 1 + qcom/monaco.dtsi | 24 ++++++++++++++++++++++++ qcom/msm-arm-smmu-monaco.dtsi | 8 ++++---- 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi index fe3f006d9574..ce1a9e482129 100644 --- a/qcom/monaco-ion.dtsi +++ b/qcom/monaco-ion.dtsi @@ -1,3 +1,4 @@ +#include &soc { qcom,ion { compatible = "qcom,msm-ion"; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4f480c12f34b..d4a79502b755 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -195,6 +195,30 @@ size = <0 0x800000>; }; + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index 8e6cc4e08ab7..c9e6c47f03df 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -39,7 +39,7 @@ /* ALL CBs of GFX: +15 deep PF */ <0x0 0x3ff 0x30B>; - gfx_0_tbu: gfx_0_tbu@0x59c5000 { + gfx_0_tbu: gfx_0_tbu@0x59dd000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x59dd000 0x1000>, <0x59da200 0x8>; @@ -141,7 +141,7 @@ /* For nrt TBU +3 deep PF */ <0x800 0x3ff 0x103>; - anoc_1_tbu: anoc_1_tbu@0xc785000 { + anoc_1_tbu: anoc_1_tbu@0xc7f5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0xc7f5000 0x1000>, <0xc7f2200 0x8>; @@ -159,7 +159,7 @@ ; }; - mm_rt_tbu: mm_rt_tbu@0xc789000 { + mm_rt_tbu: mm_rt_tbu@0xc7f9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0xc7f9000 0x1000>, <0xc7f2208 0x8>; @@ -177,7 +177,7 @@ ; }; - mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + mm_nrt_tbu: mm_nrt_tbu@0xc7fd000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0xc7fd000 0x1000>, <0xc7f2210 0x8>; From 6f8bfd2a58f8fd33d95f8c94a737afb97cb37107 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Fri, 18 Dec 2020 12:18:39 +0530 Subject: [PATCH 0539/1809] bindings: clock: Add CPU clock controller bindings for SDXNIGHTJAR Add CPU clock controller bindings to support SDXNIGHTJAR. While at it, also cleanup few properties for the CPU clock. Change-Id: I28ef84b8a9f16dda4ee2bcf3b05cdda517913393 --- bindings/clock/qcom,sdxlemur-apsscc.txt | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/bindings/clock/qcom,sdxlemur-apsscc.txt b/bindings/clock/qcom,sdxlemur-apsscc.txt index f54f7aa282bc..9d341ac41994 100644 --- a/bindings/clock/qcom,sdxlemur-apsscc.txt +++ b/bindings/clock/qcom,sdxlemur-apsscc.txt @@ -7,15 +7,15 @@ clocks and allows CPU frequency scaling on qcs405 based platforms. Required properties: - compatible: Shall contain following: "qcom,sdxlemur-apsscc" + "qcom,sdxnightjar-apsscc" - clocks: Phandle to the clock device. - clock-names: Names of the used clocks. Shall contain following: "xo_ao", "gpll0_ao" - reg: Shall contain base register offset and size. - reg-names: Names of the bases for the above registers. Shall contain following: "apcs_cmd", "apcs_pll" -- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL. -- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL. -- cpu-vdd-supply: The regulator powering the APSS RCG. +- vdd-pll-supply: The regulator(active only) powering the Analog logic of APSS PLL. +- cpu-vdd-supply: The regulator(active only) powering the APSS RCG. - qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping. Format: This represents the max frequency possible for each possible @@ -25,7 +25,6 @@ Required properties: Optional properties: - reg-names: "efuse" -- qcom,cpucc-init-rate: Initial rate which needs to be set from cpu driver. Example: clock_cpu: qcom,clock-cpu@17808100 { @@ -33,10 +32,9 @@ Example: clocks = <&rpmhcc RPMH_CXO_CLK>>; <&gcc GPLL0_AO_OUT_MAIN>;; clock-names = "xo_ao", "gpll0_ao" ; - reg = <0x17810008 0x8>, - <0x17808100 0x44>; + reg = <0x17810008 0x8>, <0x17808100 0x44>; reg-names = "apcs_cmd" , "apcs_pll"; - vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>; + vdd-pll-supply = <&VDD_CX_LEVEL_AO>; cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; qcom,speed0-bin-v0 = < 0 RPMH_REGULATOR_LEVEL_OFF>, From 5abae268f91f36efb755a48855efde75df75ffba Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Mon, 28 Dec 2020 16:30:53 +0530 Subject: [PATCH 0540/1809] ARM: dts: msm: device nodes for SVM usecases on yupik Add the device nodes that will be used for the SVM usecases on yupik. Change-Id: I8326b58de9c2791bf5beaa6ae0e9fc67a337d931 --- qcom/yupik.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 31f9d325512a..279512068fc8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1694,6 +1694,12 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + + qcom-mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; }; pil_scm_pas { From aaeb47fada5f0e424935907fbe0a7015a365c86f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Tue, 2 Jun 2020 15:20:31 -0600 Subject: [PATCH 0541/1809] ARM: dts: msm: Add l3 endpoints and pwrlevels for gpu Add the l3 endpoints as well as the frequency table to be able to vote for l3 for gpu usecases that need l3 scaling. Change-Id: If1398e4554c83b32cfc31a5609e9c237883003fb --- qcom/lahaina-gpu.dtsi | 27 +++++++++++++++++++++++++-- qcom/lahaina-v2-gpu.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index ceb8de50a6ba..e959d6174d38 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -57,8 +57,9 @@ qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; - interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; - interconnect-names = "gpu_icc_path"; + interconnect-names = "gpu_icc_path", "l3_path"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>, + <&epss_l3_cpu MASTER_EPSS_L3_APPS &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; qcom,bus-table-ddr7 = , /* index=0 */ @@ -93,6 +94,28 @@ <0>, /* Off */ <100>; /* On */ + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <614400000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1516800000>; + }; + }; + qcom,gpu-mempools { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 194a286726f2..7b23189b324a 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -4,6 +4,28 @@ /delete-property/qcom,initial-pwrlevel; /delete-node/qcom,gpu-pwrlevels; + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <614400000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1593600000>; + }; + }; + /* Power levels bins */ qcom,gpu-pwrlevel-bins { compatible="qcom,gpu-pwrlevel-bins"; From 496c418e9c7725336fb1b32c8fed1d11561d322f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Mon, 30 Nov 2020 11:39:04 -0700 Subject: [PATCH 0542/1809] ARM: dts: msm: Add ddr qos devfreq device to lahaina gpu This is used to set DDR qos level for GPU bandwidth votes for better performance. Change-Id: I56f3a6a0844ecdc153f1af4d11e39ce5a23c97a2 --- qcom/lahaina-gpu.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index e959d6174d38..b95afe9c0a9a 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -9,6 +9,13 @@ memory-region = <&pil_gpu_mem>; }; + kgsl_ddr_qos: qcom,kgsl-ddr-qos { + compatible = "qcom,devfreq-qoslat"; + governor = "powersave"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + msm_gpu: qcom,kgsl-3d0@3d00000 { compatible = "qcom,kgsl-3d0"; status = "ok"; From fddb0b0ee2e268dc8ff5bb9d166c6b042eb186f1 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 29 Dec 2020 10:04:11 +0800 Subject: [PATCH 0543/1809] ARM: dts: msm: Add initial device tree for Lahaina HHG Add initial device tree support for Lahaina HHG platform. Change-Id: Id7498273e2487d44a3ee595f9aea056129c9ab17 --- qcom/Makefile | 3 +++ qcom/lahaina-hhg-overlay.dts | 10 ++++++++++ qcom/lahaina-hhg.dtsi | 1 + qcom/lahaina-v2.1-hhg.dts | 10 ++++++++++ 4 files changed, 24 insertions(+) create mode 100644 qcom/lahaina-hhg-overlay.dts create mode 100644 qcom/lahaina-hhg.dtsi create mode 100644 qcom/lahaina-v2.1-hhg.dts diff --git a/qcom/Makefile b/qcom/Makefile index 4b4e5e611072..753d47b18537 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -7,6 +7,7 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \ lahaina-qrd-overlay.dtbo \ lahaina-atp-overlay.dtbo \ lahaina-hdk-overlay.dtbo \ + lahaina-hhg-overlay.dtbo \ lahaina-qrd-hsp-overlay.dtbo \ lahaina-qrd-module-overlay.dtbo \ lahainap-mtp-overlay.dtbo \ @@ -23,6 +24,7 @@ lahaina-mtp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-cdp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-atp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-hdk-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb +lahaina-hhg-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-qrd-hsp-overlay.dtbo-base := lahaina.dtb lahaina-qrd-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-qrd-module-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb @@ -65,6 +67,7 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-v2.1-cdp.dtb \ lahaina-v2.1-atp.dtb \ lahaina-v2.1-hdk.dtb \ + lahaina-v2.1-hhg.dtb \ lahaina-v2.1-qrd.dtb \ lahaina-v2.1-qrd-module.dtb \ lahainap-v2.1-mtp.dtb \ diff --git a/qcom/lahaina-hhg-overlay.dts b/qcom/lahaina-hhg-overlay.dts new file mode 100644 index 000000000000..b68b1d7e69bf --- /dev/null +++ b/qcom/lahaina-hhg-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-hhg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina HHG"; + compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; + qcom,board-id = <0x1001f 0x01>; +}; diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi new file mode 100644 index 000000000000..34d65173b6ce --- /dev/null +++ b/qcom/lahaina-hhg.dtsi @@ -0,0 +1 @@ +#include "lahaina-hdk.dtsi" diff --git a/qcom/lahaina-v2.1-hhg.dts b/qcom/lahaina-v2.1-hhg.dts new file mode 100644 index 000000000000..a38a944022cb --- /dev/null +++ b/qcom/lahaina-v2.1-hhg.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahainap-v2.1.dtsi" +#include "lahaina-hhg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina HHG"; + compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; + qcom,board-id = <0x1001f 0x01>; +}; From 18bfefb9e4254c431e0c9a977b82f43b54812426 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 8 Dec 2020 19:08:12 +0530 Subject: [PATCH 0544/1809] ARM: dts: msm: Add platform-specific PMIC changes for yupik Add PMIC support for yupik ATP, IDP and QRD platforms, including PM7325B for IDP and PM8350B for ATP and QRD. Include platform-specific changes for some devices like VADC, ADC_TM, battery_charger and volume up key. Change-Id: Ia9709a39b1412daffb0cf1df683dfd5a2b90fc92 --- qcom/yupik-atp.dtsi | 164 +++++++++++++++++++++++++ qcom/yupik-idp.dtsi | 191 +++++++++++++++++++++++++++++ qcom/yupik-qrd.dtsi | 284 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 639 insertions(+) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 17f1e228977f..09214819936b 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -1,2 +1,166 @@ +#include +#include "yupik-pmic-overlay.dtsi" +#include "pm8350b.dtsi" + &soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pmk8350_vadc { + pm8350b_ref_gnd { + reg = ; + label = "pm8350b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vref_1p25 { + reg = ; + label = "pm8350b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_die_temp { + reg = ; + label = "pm8350b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vph_pwr { + reg = ; + label = "pm8350b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_vbat_sns { + reg = ; + label = "pm8350b_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_usb_conn_therm { + reg = ; + label = "pm8350b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_chg_skin_therm { + reg = ; + label = "pm8350b_chg_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM8350B_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>; + + pm8350b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm8350b_chg_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + charger-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350b_haptics { + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; +}; + +&pm8350b_tz { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8008i_chip { + status = "disabled"; +}; + +&pm8008i_ldo { + status = "disabled"; +}; + +&pm8008j_chip { + status = "disabled"; +}; + +&pm8008j_ldo { + status = "disabled"; +}; + +&pm8350c_flash { + status = "disabled"; }; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 17f1e228977f..a58128b89e96 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -1,2 +1,193 @@ +#include +#include +#include +#include "yupik-pmic-overlay.dtsi" +#include "pm7325b.dtsi" + &soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pmk8350_vadc { + pm7325b_ref_gnd { + reg = ; + label = "pm7325b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_vref_1p25 { + reg = ; + label = "pm7325b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_die_temp { + reg = ; + label = "pm7325b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_vph_pwr { + reg = ; + label = "pm7325b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm7325b_vbat_sns { + reg = ; + label = "pm7325b_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + pm7325b_usb_conn_therm { + reg = ; + label = "pm7325b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_chg_skin_therm { + reg = ; + label = "pm7325b_chg_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_chg_temp { + reg = ; + label = "pm7325b_chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_ichg_fb { + reg = ; + label = "pm7325b_ichg_fb"; + qcom,pre-scaling = <1000 305185>; + }; + + smb139x_1_smb_temp { + reg = ; + label = "smb139x_1_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_2_smb_temp { + reg = ; + label = "smb139x_2_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm7325b_iin_fb { + reg = ; + label = "pm7325b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM7325B_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PM7325B_ADC7_GPIO2_100K_PU>; + + pm7325b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7325b_chg_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325B_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + charger-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM7325B_ADC7_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350c_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8350c_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8350c_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8350c_flash { + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; +}; + +&pm7325b_tz { + io-channels = <&pmk8350_vadc PM7325B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; }; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 17f1e228977f..eb1c79491267 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -1,2 +1,286 @@ +#include +#include +#include "yupik-pmic-overlay.dtsi" +#include "pm8350b.dtsi" + &soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pmk8350_vadc { + pm8350b_ref_gnd { + reg = ; + label = "pm8350b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vref_1p25 { + reg = ; + label = "pm8350b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_die_temp { + reg = ; + label = "pm8350b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vph_pwr { + reg = ; + label = "pm8350b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_vbat_sns { + reg = ; + label = "pm8350b_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_usb_conn_therm { + reg = ; + label = "pm8350b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_chg_skin_therm { + reg = ; + label = "pm8350b_chg_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_chg_temp { + reg = ; + label = "pm8350b_chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_iin_fb { + reg = ; + label = "pm8350b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; + + pm8350b_ichg_fb { + reg = ; + label = "pm8350b_ichg_fb"; + qcom,pre-scaling = <1000 305185>; + }; + + smb139x_1_smb_temp { + reg = ; + label = "smb139x_1_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_1_ichg_smb { + reg = ; + label = "smb139x_1_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_1_ichg_smb_pt { + reg = ; + label = "smb139x_1_ichg_smb_pt"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_1_iin_smb { + reg = ; + label = "smb139x_1_iin_smb"; + qcom,pre-scaling = <28 100>; + }; + + smb139x_2_smb_temp { + reg = ; + label = "smb139x_2_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_2_ichg_smb { + reg = ; + label = "smb139x_2_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_2_ichg_smb_pt { + reg = ; + label = "smb139x_2_ichg_smb_pt"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_2_iin_smb { + reg = ; + label = "smb139x_2_iin_smb"; + qcom,pre-scaling = <28 100>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM8350B_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>; + + pm8350b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm8350b_chg_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + charger-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350c_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8350c_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8350c_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8350c_flash { + status = "ok"; +}; + +&pmk8350_sdam_2 { + hap_cl_brake: cl_brake@7c { + reg = <0x7c 0x1>; + bits = <0 8>; + }; +}; + +&pm8350b_haptics { + nvmem-cell-names = "hap_cl_brake"; + nvmem-cells = <&hap_cl_brake>; + nvmem-names = "hap_cfg_sdam"; + nvmem = <&pmk8350_sdam_46>; + qcom,pbs-client = <&pm8350b_pbs2>; + + qcom,vmax-mv = <1300>; + qcom,lra-period-us = <5880>; + status = "ok"; + + effect_0 { + /* CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_1 { + /* DOUBLE_CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_2 { + /* TICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_3 { + /* THUD */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_4 { + /* POP */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; +}; + +&battery_charger { + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 + 5000000 4500000 4000000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; +}; + +&pm8350b_tz { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; }; From 9793f0d567099b7e672971856c976acdf173163a Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 24 Dec 2020 10:43:34 +0530 Subject: [PATCH 0545/1809] ARM: dts: msm: Update regulators for yupik Remove PM7325 LDO 10B as it does not have any direct clients. Expose PM8350B LDO 1D only on platforms having PM8350B. Change-Id: Ia03cd7378b3f093a5bb8c674939af15246c781ed --- qcom/yupik-atp.dtsi | 22 ++++++++++++++++++++++ qcom/yupik-qrd.dtsi | 22 ++++++++++++++++++++++ qcom/yupik-regulators.dtsi | 38 -------------------------------------- 3 files changed, 44 insertions(+), 38 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 09214819936b..bcf6f5d1242d 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -1,4 +1,5 @@ #include +#include #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" @@ -124,6 +125,27 @@ }; }; +&apps_rsc { + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1D: + pm8350b_l1: regulator-pm8350b-l1 { + regulator-name = "pm8350b_l1"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; +}; + &spmi_debug_bus { status = "ok"; }; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index eb1c79491267..97bb75f28f1e 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -1,4 +1,5 @@ #include +#include #include #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" @@ -191,6 +192,27 @@ }; }; +&apps_rsc { + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1D: + pm8350b_l1: regulator-pm8350b-l1 { + regulator-name = "pm8350b_l1"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; +}; + &spmi_debug_bus { status = "ok"; }; diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index 9e45d4640ba9..40161ad79780 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -221,25 +221,6 @@ }; }; - rpmh-regulator-ldob10 { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "ldob10"; - qcom,regulator-type = "pmic5-ldo"; - qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; - L10B: - pm7325_l10: regulator-pm7325-l10 { - regulator-name = "pm7325_l10"; - qcom,set = ; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; - qcom,init-mode = ; - }; - }; - rpmh-regulator-ldob11 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldob11"; @@ -798,25 +779,6 @@ }; }; - rpmh-regulator-ldod1 { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "ldod1"; - qcom,regulator-type = "pmic5-ldo"; - qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; - L1D: - pm8350b_l1: regulator-pm8350b-l1 { - regulator-name = "pm8350b_l1"; - qcom,set = ; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - qcom,init-voltage = <1100000>; - qcom,init-mode = ; - }; - }; - rpmh-regulator-ldoe2 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldoe2"; From 448a527994b040f35f779f2a439e30c52b1e20b5 Mon Sep 17 00:00:00 2001 From: Yong Ding Date: Thu, 16 Jul 2020 13:55:27 +0800 Subject: [PATCH 0546/1809] dt-bindings: add bindings for HAB driver Add snapshot for device tree bindings of HAB from msm-4.14 commit dc8efee55368(soc: qcom: Add support for HAB). Change-Id: I3fba56b1e3e11e16ccd34a3f19cb977d738ea9d5 --- bindings/soc/qcom/guest_shm.txt | 19 +++++++++++++++ bindings/soc/qcom/hab.txt | 41 +++++++++++++++++++++++++++++++++ bindings/vendor-prefixes.yaml | 2 ++ 3 files changed, 62 insertions(+) create mode 100644 bindings/soc/qcom/guest_shm.txt create mode 100644 bindings/soc/qcom/hab.txt diff --git a/bindings/soc/qcom/guest_shm.txt b/bindings/soc/qcom/guest_shm.txt new file mode 100644 index 000000000000..9491344c7b9f --- /dev/null +++ b/bindings/soc/qcom/guest_shm.txt @@ -0,0 +1,19 @@ +QVM Guest Shared Memory + +guest_shm is a device that enables linux as a guest operating system +to allocate shared memory between virtual machines and send notifications +of updates to other virtual machines. + +Required properties: +- compatible: Must be "qvm,guest_shm". +- interrupt-parent: Parent interrupt controller. +- interrupts: Should contain QVM interrupt. +- reg: Physical address of the guest factory and length. + +Example: + qvm,guest_shm { + compatible = "qvm,guest_shm"; + interrupt-parent = <&gic>; + interrupts = <6 4>; + reg = <0x1c050000 0x1000>; + }; diff --git a/bindings/soc/qcom/hab.txt b/bindings/soc/qcom/hab.txt new file mode 100644 index 000000000000..32f79e7ff498 --- /dev/null +++ b/bindings/soc/qcom/hab.txt @@ -0,0 +1,41 @@ +* HAB + +HAB(Hypervisor ABstraction) is meant to be a cross-platform abstraction layer +for utilizing the underlying hypervisor system. This API can be accessed from +both user and kernel sides. +The intended users of this are primarily the multimedia drivers who want to +communicate with the host OS to use the multimedia hardware. + +Required properties: +- compatible: Must be "qcom,hab" +- vmid: the local VM's ID + It should be unique in a system, and host's ID should be 0. Here is an + example for a system as qvm host + agl gvm + android gvm, and such below + setting is proper, + qvm host's vmid: 0 + agl gvm's vmid: 1 + android gvm's vmid: 2 +- mmid group properties: + - grp-start-id: mmid group starting ID, eg, 100 is for MM_AUD_1~4 + - role: the local role of this group, and must be "fe" or "be" + - remote-vmids: When the local role is "fe", this is to tell which VM is the + relevant BE. When it is "be", this is to tell which VMs it will support as + BE. + +Example: + qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmid100: mmid-grp@100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmid200: mmid-grp@200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + } diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index ea21bdf2ead6..2b11450bfa7b 100644 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -759,6 +759,8 @@ patternProperties: description: QiaoDian XianShi Corporation "^qnap,.*": description: QNAP Systems, Inc. + "^qvm,.*": + description: BlackBerry Ltd "^radxa,.*": description: Radxa "^raidsonic,.*": From daffa1fbc4853c8115ba5d2b2d1fa0a38555c2f5 Mon Sep 17 00:00:00 2001 From: Ashish Kori Date: Tue, 29 Dec 2020 11:45:40 +0530 Subject: [PATCH 0547/1809] dt-bindings: spi-msm-geni: Define fixed timeout property SPI timeout is calculated dynamically based on current transfer size and frequency. The property qcom,use-fixed-timeout can be used to fix the timeout of 250ms for all transfers. Change-Id: Id655fdf5d39c9e11753f797038217383de96ee1e --- bindings/spi/qcom,spi-msm-geni.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/spi/qcom,spi-msm-geni.txt b/bindings/spi/qcom,spi-msm-geni.txt index 261457495c32..6805a394b530 100644 --- a/bindings/spi/qcom,spi-msm-geni.txt +++ b/bindings/spi/qcom,spi-msm-geni.txt @@ -36,7 +36,9 @@ Optional properties: - qcom,shared_se: Specifies that this serial engine is shared simultaneously between execution environments. A true multi-EE usecase. - qcom,le_vm: Specifies that this serial engine is operating in a trusted VM. - +- qcom,use-fixed-timeout : Set this flag to use 250ms fixed timeout value. This + will improve overall SPI KPI value but not preferred + for large transfer. SPI slave nodes must be children of the SPI master node and can contain the following properties. From 5979e40a0fa143f3921a5796ecd78647df460653 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 29 Dec 2020 15:17:12 +0800 Subject: [PATCH 0548/1809] ARM: dts: msm: Add new DT file for Dual WIFI support for sdxnightjar Add new device tree file support for sdxnightjar hardware which supports dual wifi. Change-Id: I7a21397aa494f01455f55d507b734000a67319b1 --- qcom/Makefile | 3 ++- qcom/sdxnightjar-dualwifi-mtp.dts | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxnightjar-dualwifi-mtp.dts diff --git a/qcom/Makefile b/qcom/Makefile index 4b4e5e611072..9cd9730ea283 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -275,7 +275,8 @@ endif dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ sdxnightjar-cdp.dtb \ - sdxnightjar-qrd.dtb + sdxnightjar-qrd.dtb \ + sdxnightjar-dualwifi-mtp.dtb ifeq ($(CONFIG_ARCH_YUPIK), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) diff --git a/qcom/sdxnightjar-dualwifi-mtp.dts b/qcom/sdxnightjar-dualwifi-mtp.dts new file mode 100644 index 000000000000..ee12068b8c8e --- /dev/null +++ b/qcom/sdxnightjar-dualwifi-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP - DWIFI"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 3>; +}; From 511fd17fb1f3df0b6a5fa1f16637f00371d1cf9a Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Tue, 29 Dec 2020 16:46:13 +0530 Subject: [PATCH 0549/1809] ARM: dts: msm: Add GDSC for HS USB PHY for SDXNIGHTJAR To enable the HS USB PHY clocks it is required to keep the GDSC ON. So add the GDSC regulator node to HS USB PHY as well to ensure to keep the GDSC on before turning on the required USB clocks. Change-Id: I6e5ef31928ea20f476a8363e699f5093e2969dc5 --- qcom/sdxnightjar-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index e274820066d5..42fbb8fadc52 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -75,6 +75,7 @@ 0x00 0x18>; phy_type = "utmi"; + USB3_GDSC-supply = <&gdsc_usb30>; clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_QUSB_REF_CLK>, <&gcc GCC_USB_PHY_CFG_AHB_CLK>, From 1b352d2c04f49c6f3b50d8a7eb8162c523bb0625 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Wed, 30 Dec 2020 10:47:01 +0800 Subject: [PATCH 0550/1809] ARM: dts: msm: add setting for Lahaina HHG audio Add setting for Lahaina HHG audio. Change-Id: I9839c8936edbf1ec5a26fff70a6520c25d2e4df8 --- qcom/lahaina-hhg.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 34d65173b6ce..833d8fd0c2fb 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -1 +1,46 @@ #include "lahaina-hdk.dtsi" + +&wsa883x_0222 { + status = "ok"; +}; + +&wsa_spkr_en2 { + status = "ok"; +}; + +&lahaina_snd { + qcom,model = "lahaina-hhg-snd-card"; + + qcom,audio-routing = + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS3", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHL", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS2"; + + qcom,wsa-max-devs = <2>; +}; From 13421d7cc2ea359cfad4085c3d8881b06b5767ae Mon Sep 17 00:00:00 2001 From: xsang Date: Thu, 10 Dec 2020 16:11:35 +0800 Subject: [PATCH 0551/1809] ARM: dts: msm: add node in device tree for yupik QRD add device information for yupik QRD. Change-Id: Iaacc38d7e6328eda647034444fd2b91783cffb36 --- qcom/yupik-qrd.dtsi | 113 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index eb1c79491267..11a5c1ee9a67 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -2,6 +2,7 @@ #include #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" +#include "yupik-audio-overlay.dtsi" &soc { gpio_keys { @@ -284,3 +285,115 @@ io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; io-channel-names = "thermal"; }; + +&wsa883x_0221 { + status = "disabled"; +}; + +&swr_haptics { + status = "okay"; +}; + +&tx_macro { + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; +}; + +&wcd938x_rx_slave { + status = "okay"; +}; + +&wcd938x_tx_slave { + status = "okay"; +}; + +&wcd938x_codec { + status = "okay"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + + +&yupik_snd { + qcom,model = "lahaina-yupikqrd-snd-card"; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS1", + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS3", + "TX DMIC4", "Digital Mic4", + "Digital Mic4", "MIC BIAS4", + "TX DMIC5", "Digital Mic5", + "Digital Mic5", "MIC BIAS4", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS4", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC4", "VA MIC BIAS3", + "VA DMIC5", "VA MIC BIAS4"; + qcom,swr-dmic-max-devs = <0>; + + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&swr_haptics>, + <&wsa883x_0222>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "swr-haptics", + "wsa-codec2"; + qcom,wsa-max-devs = <1>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + From da80b647aa3bf6b6dff4702204d9d3b2acbc79da Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 28 Dec 2020 19:03:20 +0530 Subject: [PATCH 0552/1809] ARM: dts: msm: Update the APSSCC clock node for SDXLEMUR The regulator supply name has been updated, thus update the same. Change-Id: I8c91d93ba9d749bbb12f5b464e20108cc0f7b6e9 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 5378d2465d40..9b43f3c57fbf 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -498,7 +498,7 @@ reg = <0x17810008 0x16>, <0x17808100 0x100>; reg-names = "apcs_cmd", "apcs_pll"; - vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>; + vdd-pll-supply = <&VDD_CX_LEVEL_AO>; cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; qcom,speed0-bin-v0 = < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, From d1800afad7fd30970e1ca522c67e3ac14fac1c74 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Wed, 30 Dec 2020 18:51:41 +0530 Subject: [PATCH 0553/1809] ARM: dts: msm: Add a new pinctrl state for holi This change adds new pinctrl state shutdown. Change-Id: I9daef30d17f8c0984da2e44d5ede8d0f9ba607d5 --- qcom/holi-qupv3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index 2d2975b0c717..3376a25d47cc 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -127,13 +127,15 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se1_default_cts>, <&qupv3_se1_default_rtsrx>, <&qupv3_se1_default_tx>; pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>, <&qupv3_se1_tx>; pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>, <&qupv3_se1_tx>; + pinctrl-3 = <&qupv3_se1_default_cts>, + <&qupv3_se1_default_rtsrx>, <&qupv3_se1_default_tx>; qcom,wakeup-byte = <0xFD>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; From b86d2257164a4ca5b1e786334df58e31fa6c998d Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 21 Dec 2020 15:48:22 +0530 Subject: [PATCH 0554/1809] ARM: dts: msm: Add idle states for sdmshrike Idle states for sdmshrike are different from sm8150. Add idle states, rpmh master stats and soc sleep stats device nodes. Change-Id: Ibea19855197b773a6cee868fae6eb1334830e0c2 --- qcom/sdmshrike-pm.dtsi | 123 +++++++++++++++++++++++++++++++++++++++++ qcom/sdmshrike.dtsi | 2 +- 2 files changed, 124 insertions(+), 1 deletion(-) create mode 100644 qcom/sdmshrike-pm.dtsi diff --git a/qcom/sdmshrike-pm.dtsi b/qcom/sdmshrike-pm.dtsi new file mode 100644 index 000000000000..647068c4d3b5 --- /dev/null +++ b/qcom/sdmshrike-pm.dtsi @@ -0,0 +1,123 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L3"; + qcom,clstr-tmr-add = <1000>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l3-wfi"; + entry-latency-us = <48>; + exit-latency-us = <51>; + min-residency-us = <99>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + LLCC_OFF: qcom,pm-cluster-level@1 { /* AOSS sleep */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0xa340>; + qcom,psci-mode = <0xa34>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <57>; + exit-latency-us = <43>; + min-residency-us = <100>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + SLVR_RAIL_OFF: qcom,pm-cpu-level@1 { /* C4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <57>; + exit-latency-us = <43>; + min-residency-us = <83>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + GOLD_RAIL_OFF: qcom,pm-cpu-level@1 { /* C4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <2411>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 1f903bce965f..aeb490411db7 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1429,7 +1429,7 @@ #include "sdmshrike-pinctrl.dtsi" #include "sa8195-regulator.dtsi" -#include "sm8150-pm.dtsi" +#include "sdmshrike-pm.dtsi" #include "sa8195-smp2p.dtsi" #include "sa8195-gdsc.dtsi" #include "msm-arm-smmu-sdmshrike.dtsi" From 68baff9a7c4c44dbec2cbbe4b5108e8abc368e2b Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 18 Dec 2020 15:46:08 +0530 Subject: [PATCH 0555/1809] ARM: dts: msm: Disable haptics for yupik idp As Yupik IDP has Cotes PMIC which dosent support haptics. So disable haptics for IDP and enable only for QRD which has Puhi Chip. Change-Id: Ib28e804f284b2ea691faf7ca734d1013b0c29524 --- qcom/yupik-audio-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index 3fabb9a34729..19050be88416 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -118,6 +118,7 @@ qcom,swr-num-dev = <2>; qcom,swr-clock-stop-mode0 = <1>; swr_haptics: swr_haptics@f0170220 { + status = "disabled"; compatible = "qcom,pm8350b-swr-haptics"; reg = <0x01 0xf0170220>; swr-slave-supply = <&hap_swr_slave_reg>; @@ -332,7 +333,6 @@ "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", - "HAP_IN", "PCM_OUT", "WSA SRC0_INP", "SRC0", "WSA_TX DEC0_INP", "TX DEC0 MUX", "WSA_TX DEC1_INP", "TX DEC1 MUX", From 23797b1efb5cdc9a102334c676cc0d35e78ba9bb Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 28 Oct 2020 15:00:21 +0530 Subject: [PATCH 0556/1809] ARM: dts: msm: Add USB Phy Support on Yupik Add USB Phy support for primary and secondary controller on Yupik. Change-Id: I04229c74d8d78a63f8a560007071f1007df61327 --- qcom/yupik-usb.dtsi | 255 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 252 insertions(+), 3 deletions(-) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index c33d2f3e6f02..4117781f37b6 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { /* Primary USB port related controller */ @@ -31,7 +32,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = @@ -43,11 +44,20 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; usb-role-switch; + extcon = <&eud>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + + qcom,usb-charger = <&battery_charger>; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xe000>; interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -69,6 +79,218 @@ }; }; + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x114>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L10C>; + vdda18-supply = <&L1C>; + vdda33-supply = <&L2B>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; /* override_x1 */ + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L1B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L6B>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + + }; + usb1: hsusb@8c00000 { status = "disabled"; compatible = "qcom,dwc-usb3-msm"; @@ -98,8 +320,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <120000000>; - qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate = <60000000>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ @@ -114,6 +335,7 @@ compatible = "snps,dwc3"; reg = <0x8c00000 0xe000>; interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -130,7 +352,34 @@ }; + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e4000 { + status = "disabled"; + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x114>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L10C>; + vdda18-supply = <&L1C>; + vdda33-supply = <&L2B>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; }; From f1defa9d0c358ec1d2a0154f3266acf23fcbe7d0 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 16 Dec 2020 18:40:37 +0530 Subject: [PATCH 0557/1809] ARM: dts: msm: Add SMMU nodes for Yupik Adding SMMU nodes for Yupik for both primary and secondary controller. Change-Id: I2fa53e633403b159845b6329a9d327d9005d3df0 --- qcom/yupik-usb.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 4117781f37b6..24d67f57fe97 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -8,9 +8,14 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xe0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; #address-cells = <1>; #size-cells = <1>; ranges; + dma-ranges; interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, @@ -297,6 +302,9 @@ reg = <0x8c00000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xa0 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; From 051d00bf584aef58ba9e22039e3180c14f6ae0ca Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 16 Dec 2020 19:02:09 +0530 Subject: [PATCH 0558/1809] ARM: dts: msm: Add pm-qos-latency for Yupik Add pm-qos-latency which ensures that cpu is used to its full capability, therefore increasing USB throughput for Yupik. Adding the parameter for both controllers. Change-Id: Ifb01d6d156ef17abe6dcbda33ab78978e2b17757 --- qcom/yupik-usb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 24d67f57fe97..137e2b4bcd91 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -40,6 +40,7 @@ qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ @@ -330,6 +331,7 @@ qcom,core-clk-rate = <60000000>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ From 55b0b07506803cd57e23ea64612b491ab07dcc47 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 21 Dec 2020 20:56:33 +0530 Subject: [PATCH 0559/1809] ARM: dts: msm: Add TSENS node support for yupik Add TSENS node and user thermal zone configurations for temperature sensors in YUPIK. Change-Id: I86a4a39a2ddb703a0b585b91590cb9807deefd15 --- qcom/yupik-thermal.dtsi | 576 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 5 + 2 files changed, 581 insertions(+) create mode 100644 qcom/yupik-thermal.dtsi diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi new file mode 100644 index 000000000000..eb26ba324b6d --- /dev/null +++ b/qcom/yupik-thermal.dtsi @@ -0,0 +1,576 @@ +#include + +&soc { + tsens0:tsens@c222000 { + compatible = "qcom,tsens26xx"; + reg = <0x0C222000 0x8>, + <0x0C263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts-extended = <&intc GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 20 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tsens-upper-lower", + "tsens-critical", + "tsens-0C"; + #thermal-sensor-cells = <1>; + }; + + tsens1:tsens@c223000 { + compatible = "qcom,tsens26xx"; + reg = <0x0C223000 0x8>, + <0x0C265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts-extended = <&intc GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 21 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tsens-upper-lower", + "tsens-critical", + "tsens-0C"; + #thermal-sensor-cells = <1>; + }; +}; + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 7>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 8>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 9>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 10>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 12>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 13>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 14>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nspss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nspss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 7>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 8>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 9>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 10>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 42e12b2b55d1..8b1ae942a03f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1379,6 +1379,10 @@ thermal_zones: thermal-zones { }; + qmi_tmd: qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; @@ -2347,6 +2351,7 @@ #include "yupik-pm.dtsi" #include "ipcc-test-yupik.dtsi" #include "yupik-regulators.dtsi" +#include "yupik-thermal.dtsi" &gcc_pcie_0_gdsc { qcom,support-hw-trigger; From d2d5400b18464a5d0cd583b378ab8168fb3c50b0 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 23 Dec 2020 22:39:40 +0530 Subject: [PATCH 0560/1809] ARM: dts: msm: Add support for CPUFREQ HW for YUPIK Add CPU scaling and debugfs nodes to support cpu frequency scaling and print the registers. Change-Id: Ia8078c3bd0082e3098ef79251ef8f07062fee382 --- qcom/yupik-rumi.dtsi | 5 +++++ qcom/yupik.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 2103affa18e3..83894d7154ca 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -186,3 +186,8 @@ &camcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; }; + +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>; + status = "disabled"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8b1ae942a03f..aa4c6f3c90e3 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -82,6 +82,7 @@ cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -103,6 +104,7 @@ cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -119,6 +121,7 @@ cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -135,6 +138,7 @@ cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -151,6 +155,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -167,6 +172,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -183,6 +189,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -199,6 +206,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1985>; dynamic-power-coefficient = <552>; + qcom,freq-domain = <&cpufreq_hw 2 4>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -820,6 +828,35 @@ #reset-cells = <1>; }; + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw-epss"; + reg = <0x18591000 0x1000>, <0x18592000 0x1000>, + <0x18593000 0x1000>; + reg-names = "freq-domain0", "freq-domain1", + "freq-domain2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + qcom,lut-row-size = <4>; + qcom,skip-enable-check; + + interrupts = , + , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; + + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@18591000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x18591000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; + qcom,venus@aab0000 { compatible = "qcom,pil-tz-generic"; reg = <0xaab0000 0x2000>; From 552e376c8a9aca70febfc44b1b260f6f32b09311 Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Mon, 4 Jan 2021 10:01:01 +0800 Subject: [PATCH 0561/1809] ARM: dts: msm: Remove duplicated smem_mem on SDXNIGHTJAR smem_mem should be included in reserved_memory node, so remove the duplicated label outside it. Change-Id: I3f9090fbb6aa0228871f96bbd8bad986fc8895fa --- qcom/sdxnightjar.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index ad65edb5b533..92739096a05d 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -456,11 +456,6 @@ reg = <0x60000 0x6000>; }; - smem_mem: smem_region@87e80000 { - reg = <0x87e80000 0xc0000>; - no-map; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; From 056344fd565ee9407921a574620479a7fc3d2fc8 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 22 Jul 2020 09:39:51 +0530 Subject: [PATCH 0562/1809] ARM: dts: msm: Add slpi pinctrl to SDMSHRIKE Add slpi pinctrl support for SDMSHRIKE Change-Id: I0806b8d183a9f81b024650bc4b7c112045bcf6ea --- qcom/sdmshrike.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index aeb490411db7..c841ad2b4405 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1433,6 +1433,7 @@ #include "sa8195-smp2p.dtsi" #include "sa8195-gdsc.dtsi" #include "msm-arm-smmu-sdmshrike.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" &emac_gdsc { status = "ok"; @@ -1622,3 +1623,7 @@ parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; + +&slpi_tlmm { + status = "ok"; +}; From b97461ab233dc1879320f8cdf82d3eb15e9ebf28 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 1 Nov 2020 23:32:05 +0530 Subject: [PATCH 0563/1809] ARM: dts: msm: add stub interconnect devices for Monaco Add stub interconnect devices for cnoc, snoc, bimc, clk_virt, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I25a0d5a021999ff8f723bde3bd78d80c4279df8a --- qcom/monaco.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index d4a79502b755..0e42eb96e08f 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -3,6 +3,9 @@ #include #include #include +#include +#include + / { model = "Qualcomm Technologies, Inc. Monaco"; @@ -780,6 +783,36 @@ interrupt-controller; #interrupt-cells = <2>; }; + } + + clk_virt: interconnect { + compatible = "qcom,monaco-clk_virt"; + #interconnect-cells = <1>; + }; + + mmnrt_virt: interconnect@0 { + compatible = "qcom,monaco-mmnrt_virt"; + #interconnect-cells = <1>; + }; + + mmrt_virt: interconnect@1 { + compatible = "qcom,monaco-mmrt_virt"; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1880000 { + compatible = "qcom,monaco-system_noc"; + #interconnect-cells = <1>; + }; + + config_noc: interconnect@1900000 { + compatible = "qcom,monaco-config_noc"; + #interconnect-cells = <1>; + }; + + bimc: interconnect@4480000 { + compatible = "qcom,monaco-bimc"; + #interconnect-cells = <1>; }; }; From 22227dd0aa31da4315877ae5fca9beb92ce1dd23 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Thu, 30 Jul 2020 20:36:27 +0530 Subject: [PATCH 0564/1809] ARM: dts: msm: Add ion support for SDMSHRIKE Add ION support for SDMSHRIKE and reserved memory changes. Change-Id: I418bfa88f995e4ea48747346570c3f2668eb2199 --- qcom/sdmshrike-ion.dtsi | 55 +++++++++++++++++++++++++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + 2 files changed, 56 insertions(+) create mode 100644 qcom/sdmshrike-ion.dtsi diff --git a/qcom/sdmshrike-ion.dtsi b/qcom/sdmshrike-ion.dtsi new file mode 100644 index 000000000000..b32c1fef4c51 --- /dev/null +++ b/qcom/sdmshrike-ion.dtsi @@ -0,0 +1,55 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap-sys { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + qcom,ion-heap-adsp { /* ADSP HEAP */ + reg = ; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-user { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-qsee { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-qseeta { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-spss { /* SPSS HEAP */ + reg = ; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap-secdisp { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap-syssecure { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index c841ad2b4405..bff586f63aeb 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1434,6 +1434,7 @@ #include "sa8195-gdsc.dtsi" #include "msm-arm-smmu-sdmshrike.dtsi" #include "sm8150-slpi-pinctrl.dtsi" +#include "sdmshrike-ion.dtsi" &emac_gdsc { status = "ok"; From 57980e9804ddf43dffed6b198b81e19c9b22602d Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 4 Jan 2021 12:24:10 +0530 Subject: [PATCH 0565/1809] ARM: dts: qcom: Add node to enable haptics on yupik qrd Add node to enable haptics on yupik qrd. Change-Id: I51a040478e4092cf0a80cf8eb136f08a39d8a7c6 --- qcom/yupik-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index e3c97e8cdd7e..90a68efcb1ad 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -314,6 +314,7 @@ &swr_haptics { status = "okay"; + swr-slave-supply = <&hap_swr_slave_reg>; }; &tx_macro { From a78d2c71361d90f634e407348056c9528aed611d Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 27 Dec 2020 19:57:15 +0530 Subject: [PATCH 0566/1809] ARM: dts: msm: Add bus voting and platform support for yupik Add bus voting and platform support for yupik. Change-Id: I0041f34533220f6b49b878991c68ecbf16282cd3 --- qcom/yupik-atp.dtsi | 36 ++++++++++++++++++++++++++++++++ qcom/yupik-idp.dtsi | 36 ++++++++++++++++++++++++++++++++ qcom/yupik-qrd.dtsi | 35 +++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 158 insertions(+) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index bcf6f5d1242d..1d6b5e173e81 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -186,3 +186,39 @@ &pm8350c_flash { status = "disabled"; }; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2952000 2952000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + status = "ok"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index a58128b89e96..b3ee0ab1052e 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -191,3 +191,39 @@ io-channels = <&pmk8350_vadc PM7325B_ADC7_DIE_TEMP>; io-channel-names = "thermal"; }; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2952000 2952000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + status = "ok"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index e3c97e8cdd7e..cbb1a622d7b9 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -419,3 +419,38 @@ <&bolero>; }; +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2952000 2952000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + status = "ok"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8b1ae942a03f..39d89f693316 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1769,6 +1769,32 @@ qcom,ice-clk-rates = <300000000 100000000>; + interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1000 590000>, <2000 1590000>, + /* 25 MB/s */ + <50000 590000>, <30000 1590000>, + /* 50 MB/s */ + <80000 590000>, <40000 1590000>, + /* 100 MB/s */ + <100000 590000>, <50000 1590000>, + /* 200 MB/s */ + <150000 2060000>, <80000 6440000>, + /* 400 MB/s */ + <261438 2060000>, <300000 6440000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 9170000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 400000000 4294967295>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; @@ -1810,6 +1836,31 @@ clock-names = "core", "iface"; bus-width = <4>; + + interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1000 590000>, <2000 1590000>, + /* 25 MB/s */ + <50000 590000>, <30000 1590000>, + /* 50 MB/s */ + <80000 590000>, <40000 1590000>, + /* 100 MB/s */ + <100000 590000>, <50000 1590000>, + /* 200 MB/s */ + <261438 2060000>, <300000 6440000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 9170000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; From 5cc7c3e8f514441bc69bc977a3ca58bfade6bc79 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Fri, 27 Nov 2020 12:37:44 +0530 Subject: [PATCH 0567/1809] ARM: dts: msm: Add qfprom and qfprom_sys node Add qfprom and qfprom_sys DT node for Yupik platform. Change-Id: Ic357ed2fdfacecee6d51ee959f637e12b4c43fc8 --- qcom/yupik.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8b1ae942a03f..9df1517b805c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2343,6 +2343,19 @@ qcom,dump-id = <0x165>; }; }; + + qfprom: qfprom@780000 { + compatible = "qcom,qfprom"; + reg = <0x780000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + }; }; #include "shima-gdsc.dtsi" From a042b98603a3bca8ef070cf9ebc7afd675c79281 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Fri, 30 Oct 2020 17:58:31 +0530 Subject: [PATCH 0568/1809] ARM: dts: msm: Signal aop change for PIL for YUPIK Add aop signalling property for adsp and cdsp PIL nodes for Yupik platform. Change-Id: Ic08bcfc3c5b9c1d2e5183b16ed3806226f803870 --- qcom/yupik.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 9df1517b805c..787a7a872f7d 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1908,6 +1908,7 @@ qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; memory-region = <&pil_adsp_mem>; + qcom,signal-aop; qcom,complete-ramdump; /* Inputs from lpass */ @@ -1954,6 +1955,7 @@ qcom,ssctl-instance-id = <0x17>; qcom,firmware-name = "cdsp"; memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; qcom,complete-ramdump; interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; From d551da474868005599f2f9e9d02e1ae0d97009b8 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 26 Nov 2020 10:57:33 +0530 Subject: [PATCH 0569/1809] ARM: dts: msm: Add Modem pil node for Yupik Add Modem pil DT node to support Modem subsystem for Yupik platform. Change-Id: Ib7e026841e45e104c42847698d94a7bf3bea9d3e --- qcom/yupik.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8b1ae942a03f..03aa07834953 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1887,6 +1887,56 @@ shared-buffer = <&qrtr_shbuf>; }; + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MODEM_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <4>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,minidump-id = <3>; + qcom,ssctl-instance-id = <0x12>; + qcom,firmware-name = "modem"; + memory-region = <&pil_mpss_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + qcom,lpass@3700000 { compatible = "qcom,pil-tz-generic"; reg = <0x3700000 0x00100>; From b0b303fb788eb5a70eb3352c6f12180935dabac9 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 2 Dec 2020 23:36:48 +0530 Subject: [PATCH 0570/1809] ARM: dts: msm: Add IPA DT entry for sdxnightjar target Add IPA DT entry for sdxnightjar target. Change-Id: I8138ab15c3d773eac8452a1daa00380f5339913c --- qcom/sdxnightjar.dtsi | 85 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8337f22edeb9..054211f93229 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -586,6 +586,19 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; qnand_1: nand@7980000 { @@ -706,6 +719,78 @@ clocks = <&rpmcc RPM_SMD_SNOC_CLK>, <&rpmcc RPM_SMD_SNOC_A_CLK>; }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + ipa_hw: qcom,ipa@07B00000 { + compatible = "qcom,ipa"; + reg = <0x07B00000 0x34000>, + <0x07B84000 0x31FFFF>, + <0x07B04000 0x2C000>; + reg-names = "ipa-base", "bam-base", "gsi-base"; + interrupts = + , + , + ; + interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; + qcom,ipa-hw-ver = <10>; /* IPA core version = IPAv3.0 */ + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ + qcom,platform-type = <0>; /* MDM platform */ + qcom,ee = <0>; + qcom,use-rg10-limitation-mitigation; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + clock-names = "core_clk"; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + /* SVS2 */ + qcom,svs2 = + <80000 64000 80000 64000 80000 16000>; + /* SVS */ + qcom,svs = + <80000 640000 80000 640000 80000 160000>; + /* NOMINAL */ + qcom,nominal = + <206000 960000 206000 960000 206000 400000>; + /* TURBO */ + qcom,turbo = + <206000 3600000 206000 3600000 206000 960000>; + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* ipa tz unlock registers */ + qcom,ipa-tz-unlock-reg = + <0x4043583c 0x1000>; /* 32-bit reg addr and size */ + /* smp2p gpio information */ + qcom,smp2pgpio_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2pgpio_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; }; #include "pmd9650.dtsi" From ed22a4a98fe45e251af848e4b8e536e8a3f244eb Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 4 Jan 2021 15:02:37 -0800 Subject: [PATCH 0571/1809] ARM: dts: msm: Revised RCM RC variant id for sdxlemur Amended the variant id for rcm-rc sdxlemur device. Change-Id: Ic8a68970d69c8d25603f1a139d2dcdade902ce2f --- qcom/sdxlemur-rcm-rc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index 95711468a255..cbd8d5c1ee12 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -9,5 +9,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x1010015 0x301>; + qcom,board-id = <0x10015 0x300>; }; From 65a21729836b76d476fe607e6f64a91e557381e6 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 11 Dec 2020 11:55:08 -0800 Subject: [PATCH 0572/1809] ARM: dts: msm: Add device tree files for sdxlemur v2 Added base device tree files for sdxlemur v2 Change-Id: Ic76fe821b8d6f1365bee37538d636e73e34f6ca6 --- qcom/Makefile | 11 ++++++++++- qcom/sdxlemur-v2-cdp.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-cpe.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-mbb-emmc.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-mbb.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp.dts | 12 ++++++++++++ qcom/sdxlemur-v2-rcm-pcie-ep.dts | 12 ++++++++++++ qcom/sdxlemur-v2-rcm-rc.dts | 12 ++++++++++++ qcom/sdxlemur-v2.dtsi | 8 ++++++++ 12 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-v2-cdp.dts create mode 100644 qcom/sdxlemur-v2-mtp-cpe.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-emmc.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb.dts create mode 100644 qcom/sdxlemur-v2-mtp.dts create mode 100644 qcom/sdxlemur-v2-rcm-pcie-ep.dts create mode 100644 qcom/sdxlemur-v2-rcm-rc.dts create mode 100644 qcom/sdxlemur-v2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 3799f11a48c2..149ca1310ab3 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -264,7 +264,16 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-rcm-pcie-ep.dtb \ - sdxlemur-rcm-rc.dtb + sdxlemur-rcm-rc.dtb \ + sdxlemur-v2-cdp.dtb \ + sdxlemur-v2-mtp-mbb.dtb \ + sdxlemur-v2-mtp-cpe.dtb \ + sdxlemur-v2-mtp-mbb-emmc.dtb \ + sdxlemur-v2-mtp-mbb-ntn3-pcie.dtb \ + sdxlemur-v2-mtp-mbb-pcie-ep.dtb \ + sdxlemur-v2-mtp-mbb-pcie-rc-ep.dtb \ + sdxlemur-v2-rcm-pcie-ep.dtb \ + sdxlemur-v2-rcm-rc.dtb ifeq ($(CONFIG_ARCH_SHIMA), y) diff --git a/qcom/sdxlemur-v2-cdp.dts b/qcom/sdxlemur-v2-cdp.dts new file mode 100644 index 000000000000..a40de23838ce --- /dev/null +++ b/qcom/sdxlemur-v2-cdp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-cdp.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR CDP V2"; + compatible = "qcom,sdxlemur-cdp", + "qcom,sdxlemur", "qcom,cdp"; + qcom,board-id = <0x20001 0x300>; +}; diff --git a/qcom/sdxlemur-v2-mtp-cpe.dts b/qcom/sdxlemur-v2-mtp-cpe.dts new file mode 100644 index 000000000000..42e5d0a51d6b --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-cpe.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x6020008 0x306>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts new file mode 100644 index 000000000000..9076ddf8c3d3 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-emmc.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2020108 0x302>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts new file mode 100644 index 000000000000..37fd541cd0b2 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x5020008 0x305>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts new file mode 100644 index 000000000000..77326071dd86 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x4020008 0x204>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts new file mode 100644 index 000000000000..c5956de09f13 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x3020008 0x203>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb.dts b/qcom/sdxlemur-v2-mtp-mbb.dts new file mode 100644 index 000000000000..3814ef3e3d07 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2020008 0x302>; +}; diff --git a/qcom/sdxlemur-v2-mtp.dts b/qcom/sdxlemur-v2-mtp.dts new file mode 100644 index 000000000000..40cb9249df97 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x20008 0x300>; +}; diff --git a/qcom/sdxlemur-v2-rcm-pcie-ep.dts b/qcom/sdxlemur-v2-rcm-pcie-ep.dts new file mode 100644 index 000000000000..b22c1df9690e --- /dev/null +++ b/qcom/sdxlemur-v2-rcm-pcie-ep.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-rcm-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP V2"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x1020015 0x201>; +}; diff --git a/qcom/sdxlemur-v2-rcm-rc.dts b/qcom/sdxlemur-v2-rcm-rc.dts new file mode 100644 index 000000000000..385329444730 --- /dev/null +++ b/qcom/sdxlemur-v2-rcm-rc.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex V2"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x20015 0x300>; +}; diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi new file mode 100644 index 000000000000..59cb20523cbd --- /dev/null +++ b/qcom/sdxlemur-v2.dtsi @@ -0,0 +1,8 @@ +#include "sdxlemur.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR V2"; + compatible = "qcom,sdxlemur"; + qcom,msm-id = <458 0x20000>, <483 0x20000>; +}; + From 01df4aa8198d2f007c48eadb8b6836223d19e9f0 Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Wed, 30 Dec 2020 10:24:18 +0530 Subject: [PATCH 0573/1809] ARM: dts: msm: Enable qsee drivers for yupik Add device node entries on DT include file to enable QSEECOM, SMCINVOKE, QRNG, qcedev, qcrypto, HWKM and tzlog drivers for yupik. Change-Id: I8f72e1d83543797b2dff12583493432fe04f018a --- qcom/yupik-ion.dtsi | 18 ++++++ qcom/yupik.dtsi | 152 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 166 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index a79bbd58abf5..e22976a73288 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -21,6 +21,24 @@ memory-region = <&secure_display_memory>; qcom,ion-heap-type = "HYP_CMA"; }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..05257ba9b920 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -366,6 +366,30 @@ reg = <0x0 0xd7f80000 0x0 0x80000>; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; @@ -452,6 +476,112 @@ method = "smc"; }; + qcom_tzlog: tz-log@0x146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_qseecom: qseecom@c1800000 { + compatible = "qcom,qseecom"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@10d3000 { + compatible = "qcom,msm-rng"; + reg = <0x10d3000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_HWKM>; + clock-names = "km_clk_src"; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x04E6 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x4F2 0>, + <&apps_smmu 0x4F8 0>, + <&apps_smmu 0x4F9 0>, + <&apps_smmu 0x4FF 0>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x4F3 0>, + <&apps_smmu 0x4FC 0>, + <&apps_smmu 0x4FD 0>, + <&apps_smmu 0x4FE 0>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x04E4 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; @@ -799,6 +929,16 @@ memory-region = <&pil_video_mem>; }; + qcom_hwkm: hwkm@10c0000 { + compatible = "qcom,hwkm"; + reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>; + reg-names = "km_master", "ice_slave"; + qcom,enable-hwkm-clk; + clock-names = "km_clk_src"; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + qcom,op-freq-hz = <75000000>; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; reg-names = "phy_mem"; @@ -859,8 +999,10 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>; - reg-names = "ufs_mem"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -1694,8 +1836,10 @@ sdhc_1: sdhci@7C4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007c8000 0x8000>, <0x7d0000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; interrupts = , ; From c04929634be25870388cb211969783da9b9aa39e Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Fri, 30 Oct 2020 18:08:37 +0530 Subject: [PATCH 0574/1809] ARM: dts: msm: Add minidump id for LPASS/CDSP on Yupik Add minidump id, to enable minidump collection for LPASS/CDSP on Yupik SOC. Also, dump minidump ELF in ELF32 format, for LPASS and CDSP subsystems. Change-Id: Id861d1d9340cd189aafdaf90e7a98071ae857269 --- qcom/yupik.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 787a7a872f7d..1581c57db14b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1904,12 +1904,14 @@ qcom,pas-id = <1>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; + qcom,minidump-id = <5>; qcom,sysmon-id = <1>; qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; memory-region = <&pil_adsp_mem>; qcom,signal-aop; qcom,complete-ramdump; + qcom,minidump-as-elf32; /* Inputs from lpass */ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, @@ -1951,12 +1953,14 @@ qcom,pas-id = <18>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <601>; + qcom,minidump-id = <7>; qcom,sysmon-id = <7>; qcom,ssctl-instance-id = <0x17>; qcom,firmware-name = "cdsp"; memory-region = <&pil_cdsp_mem>; qcom,signal-aop; qcom,complete-ramdump; + qcom,minidump-as-elf32; interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; From ce6a7f570d3f4f9f585982f4b0fd2bf1aae3bbff Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 22 Jul 2020 12:53:10 +0530 Subject: [PATCH 0575/1809] ARM: dts: msm: Add tlmm pinctrl support for SM6150 Add support for TLMM pinctrl on SM6150 platform. Change-Id: I9091beb207d0b2d99a377715b727fb790cafa4ac --- bindings/pinctrl/qcom,sm6150-pinctrl.txt | 190 ++ qcom/sm6150-pinctrl.dtsi | 2274 ++++++++++++++++++++++ qcom/sm6150.dtsi | 1 + 3 files changed, 2465 insertions(+) create mode 100644 bindings/pinctrl/qcom,sm6150-pinctrl.txt create mode 100644 qcom/sm6150-pinctrl.dtsi diff --git a/bindings/pinctrl/qcom,sm6150-pinctrl.txt b/bindings/pinctrl/qcom,sm6150-pinctrl.txt new file mode 100644 index 000000000000..0d930465a4f6 --- /dev/null +++ b/bindings/pinctrl/qcom,sm6150-pinctrl.txt @@ -0,0 +1,190 @@ +Qualcomm Technologies, Inc. SM6150 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SM6150 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sm6150-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the north, south, west + and east TLMM tiles. + +- reg-names: + Usage: required + Value type: + Defintiion: names for the cells of reg, must contain "north", "south" + "west" and "east". + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-ranges: + Usage: required + Value type: + Definition: see ../gpio/gpio.txt + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: see ../gpio/gpio.txt + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + ufs_reset + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, + audio_ref, atest_usb1, atest_usb2, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb20, + atest_usb21, atest_usb22, atest_usb2, atest_usb23, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, + emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist, + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, + pa_indicator, pci_e0, phase_flag, pll_bypassnl, + pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws, + prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s, + qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, + qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, + sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s, + tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, + usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03900000 0x300000>, + <0x03D00000 0x300000>; + reg-names = "west", "east", "north", "south"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 175>; + gpio-reserved-ranges = <0 4>, <126 4>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi new file mode 100644 index 000000000000..71308852030e --- /dev/null +++ b/qcom/sm6150-pinctrl.dtsi @@ -0,0 +1,2274 @@ +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* QUPv3_0 South SE mappings */ + /* SE 0 pin mappings */ + qupv3_se0_2uart_pins: qupv3_se0_2uart_pins { + qupv3_se0_2uart_active: qupv3_se0_2uart_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup00"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio18", "gpio19"; + function = "qup03"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins { + ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + + ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + }; + + /* QUPv3_1 North instances */ + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <16>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <16>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup11"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio10", "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { + qupv3_se7_ctsrx: qupv3_se7_ctsrx { + mux { + pins = "gpio10", "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rts: qupv3_se7_rts { + mux { + pins = "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_tx: qupv3_se7_tx { + mux { + pins = "gpio12"; + function = "qup13"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + lt9611_pins: lt9611_pins { + mux { + pins = "gpio26", "gpio20", "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio20", "gpio79"; + drive-strength = <8>; + bias-disable = <0>; /* no pull */ + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + fsa_usbc_ana_en_n@114 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + sde_dp_switch_active: sde_dp_switch_active { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-up; /* pull up */ + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_switch_suspend: sde_dp_switch_suspend { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-down; + output-low; + drive-strength = <2>; + }; + }; + + sde_dp_connector_enable: sde_dp_connector_enable { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_ctrl: sde_dp_hotplug_ctrl { + mux { + pins = "gpio103"; + function = "debug_hot"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_tlmm: sde_dp_hotplug_tlmm { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + ter_i2s_sck_ws { + ter_i2s_sck_sleep: ter_i2s_sck_sleep { + mux { + pins = "gpio115", "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <2>; /* 2 mA */ + bias-disable; + }; + }; + + ter_i2s_sck_active: ter_i2s_sck_active { + mux { + pins = "gpio115", "gpio116"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <8>; /* 8 mA */ + output-high; + bias-disable; + }; + }; + }; + + ter_i2s_data0 { + ter_i2s_data0_sleep: ter_i2s_data0_sleep { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + ter_i2s_data0_active: ter_i2s_data0_active { + mux { + pins = "gpio117"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 8 mA */ + input-enable; + bias-disable; + }; + }; + }; + + ter_i2s_data1 { + ter_i2s_data1_sleep: ter_i2s_data1_sleep { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + bias-disable; + }; + }; + + ter_i2s_data1_active: ter_i2s_data1_active { + mux { + pins = "gpio118"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <8>; /* 8 mA */ + output-high; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio90"; + function = "pcie_clk"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pri_aux_pcm_sck { + pri_aux_pcm_sck_sleep: pri_aux_pcm_sck_sleep { + mux { + pins = "gpio108"; + function = "mi2s_1"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_sck_active: pri_aux_pcm_sck_active { + mux { + pins = "gpio108"; + function = "mi2s_1"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_ws { + pri_aux_pcm_ws_sleep: pri_aux_pcm_ws_sleep { + mux { + pins = "gpio109"; + function = "mi2s_1"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_ws_active: pri_aux_pcm_ws_active { + mux { + pins = "gpio109"; + function = "mi2s_1"; + }; + + config { + pins = "gpio109"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_data0 { + pri_aux_pcm_data0_sleep: pri_aux_pcm_data0_sleep { + mux { + pins = "gpio110"; + function = "mi2s_1"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_data0_active: pri_aux_pcm_data0_active { + mux { + pins = "gpio110"; + function = "mi2s_1"; + }; + + config { + pins = "gpio110"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_data1 { + pri_aux_pcm_data1_sleep: pri_aux_pcm_data1_sleep { + mux { + pins = "gpio111"; + function = "mi2s_1"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_data1_active: pri_aux_pcm_data1_active { + mux { + pins = "gpio111"; + function = "mi2s_1"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + output-high; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio89", "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio89", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor0_active: cam_sensor0_active { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_suspend: cam_sensor0_suspend { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_active: cam_sensor1_active { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_suspend: cam_sensor1_suspend { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + flash_led3_front { + flash_led3_front_en: flash_led3_front_en { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-high; + bias-disable; + }; + }; + + flash_led3_front_dis: flash_led3_front_dis { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-low; + bias-disable; + }; + }; + }; + + cam_sensor_ir_cut_on: cam_sensor_ir_led_on { + /*IR_LED*/ + mux { + pins = "gpio73", "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio73", "gpio74"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_ir_cut_off: cam_sensor_ir_led_off { + /*IR_LED*/ + mux { + pins = "gpio73", "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio73", "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + hs0_i2s_sck_ws { + hs0_i2s_sck_sleep: hs0_i2s_sck_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_sck_active: hs0_i2s_sck_active { + mux { + pins = "gpio36", "gpio37"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs0_i2s_data0 { + hs0_i2s_data0_sleep: hs0_i2s_data0_sleep { + mux { + pins = "gpio38"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio38"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_data0_active: hs0_i2s_data0_active { + mux { + pins = "gpio38"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio38"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs0_i2s_data1 { + hs0_i2s_data1_sleep: hs0_i2s_data1_sleep { + mux { + pins = "gpio39"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio39"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_data1_active: hs0_i2s_data1_active { + mux { + pins = "gpio39"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio39"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs1_i2s_sck_ws { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio24", "gpio25"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio26"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio26"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio26"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio27"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio27"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio27"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio113"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio113"; + bias-pull-up; + }; + }; + + emac_mdio: emac_mdio { + mux { + pins = "gpio114"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio96"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio96"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio95"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio95"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio94"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio94"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio93"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio93"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio92"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio92"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio97"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio97"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio83"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio83"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio82"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio82"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio81"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio81"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio103"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio103"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxc_suspend: emac_rgmii_rxc_suspend { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + input-disable; + }; + }; + + emac_rgmii_rxc_resume: emac_rgmii_rxc_resume { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + input-enable; + bias-disable;/* NO pull */ + }; + }; + + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio112"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio112"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio121"; + function = "emac_phy"; + }; + + config { + pins = "gpio121"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio91"; + function = "rgmii_sync"; + }; + + config { + pins = "gpio91"; + bias-pull-up; + drive-strength = <16>; + }; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + usb0_hs_ac_en_default: usb0_hs_ac_en_default { + mux { + pins = "gpio88"; + function = "usb0_hs_ac"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb1_hs_ac_en_default: usb1_hs_ac_en_default { + mux { + pins = "gpio89"; + function = "usb1_hs_ac"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index c205367f4f57..7cfff14ca003 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -680,3 +680,4 @@ }; #include "sm6150-qupv3.dtsi" +#include "sm6150-pinctrl.dtsi" From 8d76c55ae72f217dbad240ade0414c07af35b901 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 23 Dec 2020 11:26:42 +0530 Subject: [PATCH 0576/1809] ARM: dts: msm: Change address-cells to 1 for pm2250 SPMI addressing in msm-5.4 uses one cell (base) and size is set default to 0x100. So change accordingly for pm2250. Change-Id: If3c6fe392434d77d3ff16a88a7b1aae6fd45b226 --- qcom/pm2250.dtsi | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index f9b8bb82e9a0..aa231533cbf6 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -13,17 +13,17 @@ qcom,pm2250@0 { compatible = "qcom,spmi-pmic"; reg = <0 SPMI_USID>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; pm2250_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; - reg = <0x100 0x100>; + reg = <0x100>; }; qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; - reg = <0x800 0x100>; + reg = <0x800>; interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "kpdpwr", "resin"; @@ -47,7 +47,7 @@ pm2250_tz: qcom,temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400 0x100>; + reg = <0x2400>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; io-channels = <&pm2250_vadc ADC5_DIE_TEMP>; io-channel-names = "thermal"; @@ -57,7 +57,7 @@ pm2250_vadc: vadc@3100 { compatible = "qcom,spmi-adc5-lite"; - reg = <0x3100 0x100>; + reg = <0x3100>; reg-names = "adc5-usr-base"; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ pm2250_gpios: pinctrl@c000 { compatible = "qcom,spmi-gpio"; - reg = <0xc000 0xa00>; + reg = <0xc000>; interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, <0x0 0xc1 0 IRQ_TYPE_NONE>, <0x0 0xc2 0 IRQ_TYPE_NONE>, @@ -204,7 +204,7 @@ qcom,qgauge@4800 { status = "okay"; - reg = <0x4800 0x100>; + reg = <0x4800>; interrupts = <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, @@ -216,7 +216,7 @@ qcom,qg-sdam@b600 { status = "okay"; - reg = <0xb600 0x100>; + reg = <0xb600>; }; }; @@ -228,7 +228,7 @@ qcom,pmic-revid = <&pm2250_revid>; qcom,chgr@1000 { - reg = <0x1000 0x100>; + reg = <0x1000>; interrupts = <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, @@ -242,7 +242,7 @@ }; qcom,dcdc@1100 { - reg = <0x1100 0x100>; + reg = <0x1100>; interrupts = <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, @@ -258,7 +258,7 @@ }; qcom,batif@1200 { - reg = <0x1200 0x100>; + reg = <0x1200>; interrupts = <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, @@ -274,7 +274,7 @@ }; qcom,usb@1300 { - reg = <0x1300 0x100>; + reg = <0x1300>; interrupts = <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, @@ -292,7 +292,7 @@ }; qcom,typec@1500 { - reg = <0x1500 0x100>; + reg = <0x1500>; interrupts = <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, @@ -312,7 +312,7 @@ }; qcom,misc@1600 { - reg = <0x1600 0x100>; + reg = <0x1600>; interrupts = <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, @@ -332,7 +332,7 @@ }; qcom,schgm-flashlite@a600 { - reg = <0xa600 0x100>; + reg = <0xa600>; interrupts = <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, @@ -350,19 +350,19 @@ pm2250_1: qcom,pm2250@1 { compatible = "qcom,spmi-pmic"; reg = <1 SPMI_USID>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; pm2250_vib: qcom,vibrator@5600 { compatible = "qcom,qpnp-vibrator-ldo"; - reg = <0x5600 0x100>; + reg = <0x5600>; qcom,vib-ldo-volt-uv = <3000000>; qcom,disable-overdrive; }; pm2250_pwm1: qcom,pwms@bc00 { compatible = "qcom,pwm-lpg"; - reg = <0xbc00 0x100>; + reg = <0xbc00>; reg-names = "lpg-base"; qcom,num-lpg-channels = <1>; #pwm-cells = <2>; @@ -370,7 +370,7 @@ pm2250_pwm2: qcom,pwms@bd00 { compatible = "qcom,pwm-lpg"; - reg = <0xbd00 0x100>; + reg = <0xbd00>; reg-names = "lpg-base"; qcom,num-lpg-channels = <1>; #pwm-cells = <2>; @@ -378,7 +378,7 @@ pm2250_pwm3: qcom,pwms@be00 { compatible = "qcom,pwm-lpg"; - reg = <0xbe00 0x100>; + reg = <0xbe00>; reg-names = "lpg-base"; qcom,num-lpg-channels = <1>; #pwm-cells = <2>; From 6a22e59ebbcfe53bf81a549faf6b2c6fd0bfad87 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 23 Dec 2020 11:30:01 +0530 Subject: [PATCH 0577/1809] ARM: dts: msm: Change DT configuration for PMIC GPIO device Couple of changes required to match with GPIO driver on msm-5.4 kernel 1. Compatible string should contain PMIC name 2. Need not explicitly list down all the PMIC GPIOs. It is provided as data in match table within the driver. Change-Id: I1b661cffee893779d9233b76bf5cb15fbb19ebc3 --- qcom/pm2250.dtsi | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index aa231533cbf6..e22694c8414d 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -157,27 +157,12 @@ pm2250_gpios: pinctrl@c000 { - compatible = "qcom,spmi-gpio"; + compatible = "qcom,pm2250-gpio"; reg = <0xc000>; - interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, - <0x0 0xc1 0 IRQ_TYPE_NONE>, - <0x0 0xc2 0 IRQ_TYPE_NONE>, - <0x0 0xc3 0 IRQ_TYPE_NONE>, - <0x0 0xc4 0 IRQ_TYPE_NONE>, - <0x0 0xc5 0 IRQ_TYPE_NONE>, - <0x0 0xc6 0 IRQ_TYPE_NONE>, - <0x0 0xc7 0 IRQ_TYPE_NONE>, - <0x0 0xc8 0 IRQ_TYPE_NONE>, - <0x0 0xc9 0 IRQ_TYPE_NONE>; - - interrupt-names = "pm2250_gpio1", "pm2250_gpio2", - "pm2250_gpio3", "pm2250_gpio4", - "pm2250_gpio5", "pm2250_gpio6", - "pm2250_gpio7", "pm2250_gpio8", - "pm2250_gpio9", "pm2250_gpio10"; - gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; pm2250_rtc: qcom,pm2250_rtc { From 9bd364376921be36cc29192008b50cd72109d9e1 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 23 Dec 2020 11:33:50 +0530 Subject: [PATCH 0578/1809] ARM: dts: msm: Add thermal zones for pm2250 Add thermal zones required for temp-alarm driver for pm2250 Change-Id: Ib5f8de6df281fa026f01dccbfaac3762b338ab9e --- qcom/pm2250.dtsi | 30 ++++++++++++++++++++++++++++++ qcom/scuba-iot.dtsi | 2 ++ 2 files changed, 32 insertions(+) diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index e22694c8414d..7865afd38967 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -370,3 +370,33 @@ }; }; }; + +&thermal_zones { + pm2250_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm2250_tz>; + wake-capable-sensor; + + trips { + pm2250_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm2250_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 20ef7dd9fb96..3ac31cd6c8d9 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -446,6 +446,8 @@ qcom,guard-memory; }; + thermal_zones: thermal-zones { }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; From 51685e4611231c828da8465b6e13f53fd2bb7dd6 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 5 Jan 2021 18:31:02 +0530 Subject: [PATCH 0579/1809] ARM: dts: msm: Add pinctrl information for Yupik target This change adds pinctrl information of reset and tear check(TE) GPIO for Yupik target. Change-Id: I3a77b931b3984073e494bc93b65b4b63db10fd0d --- qcom/yupik-pinctrl.dtsi | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 23c867f78890..459bcfa870e7 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -2340,5 +2340,60 @@ }; }; }; + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio80"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio80"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; }; }; From b5ed7585d29c4988e9ae41b1b5be3cecc67ceb24 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Tue, 5 Jan 2021 11:46:11 -0500 Subject: [PATCH 0580/1809] ARM: dts: msm: Introduce demura HFC region nodes ABL expects the demura HFC region nodes to always be present under a device's reserved memory regions. If this node is not present, ABL is unable to insert it and demura continuous splash cannot be handled. Introduce dummy demura HFC regions into the device tree. These nodes are given an address and size of 0 to allow the kernel to specially handle them. Change-Id: I6b95a145b4d515e24a454d9ad293e477e6dec66f --- qcom/lahaina.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 841b453c9ee9..45d3ecd39f62 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -527,6 +527,20 @@ label = "cont_splash_region"; }; + /* + * Demura memory regions are to be commented out if + * feature not in use. + */ + demura_memory_0: demura_region_0 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 0"; + }; + + demura_memory_1: demura_region_1 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 1"; + }; + dfps_data_memory: dfps_data_region { reg = <0x0 0xe3300000 0x0 0x0100000>; label = "dfps_data_region"; From 83682c0361bbf5412cf8a4326481450f40842998 Mon Sep 17 00:00:00 2001 From: gururaj chalgeri Date: Mon, 23 Nov 2020 06:53:10 +0530 Subject: [PATCH 0581/1809] ARM: dts: msm: Add fastrpc and cdsp/adsp device node Add fastrpc context banks, memory regions, cdsp device node adsp and also restricting dma pools. Change-Id: Ia7177230e060519256f81ff6d25576f24a78b8cd --- qcom/yupik-ion.dtsi | 9 +++ qcom/yupik.dtsi | 188 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 197 insertions(+) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index a79bbd58abf5..88de7176ff89 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -16,6 +16,15 @@ qcom,ion-heap-type = "SYSTEM_SECURE"; }; + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = ; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_secure_heap_mem>; + token = <0x20000000>; + }; + }; + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ reg = ; memory-region = <&secure_display_memory>; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..b251394d0651 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -315,6 +315,14 @@ reg = <0x0 0x88f00000 0x0 0x1e00000>; }; + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + pil_camera_mem: video@8ad00000 { no-map; reg = <0x0 0x8ad00000 0x0 0x500000>; @@ -2412,6 +2420,186 @@ qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A1 0x0420>, + <&apps_smmu 0x1181 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A2 0x0420>, + <&apps_smmu 0x1182 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A3 0x0420>, + <&apps_smmu 0x1183 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A4 0x0420>, + <&apps_smmu 0x1184 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A5 0x0420>, + <&apps_smmu 0x1185 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A6 0x0420>, + <&apps_smmu 0x1186 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A7 0x0420>, + <&apps_smmu 0x1187 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A8 0x0420>, + <&apps_smmu 0x1188 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x11A9 0x0420>, + <&apps_smmu 0x1189 0x0420>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1803 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1804 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1805 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + shared-cb = <5>; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AB 0x0420>, + <&apps_smmu 0x118B 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AC 0x0420>, + <&apps_smmu 0x118C 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AD 0x0420>, + <&apps_smmu 0x118D 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb16 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AE 0x0420>, + <&apps_smmu 0x118E 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + }; }; #include "shima-gdsc.dtsi" From 84fdc29d743ab1de141d72e021427a2ea8f767a9 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Wed, 12 Feb 2020 11:04:02 +0800 Subject: [PATCH 0582/1809] dt-bindings: Add dt binding for NT36xxx driver Add device tree binding document for new touch driver. Change-Id: Ib45cabd7b2de3d094dc6832a9aff66520b033aaa --- .../input/touchscreen/novatek_nt36xxx.txt | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 bindings/input/touchscreen/novatek_nt36xxx.txt diff --git a/bindings/input/touchscreen/novatek_nt36xxx.txt b/bindings/input/touchscreen/novatek_nt36xxx.txt new file mode 100644 index 000000000000..44b963f1a264 --- /dev/null +++ b/bindings/input/touchscreen/novatek_nt36xxx.txt @@ -0,0 +1,32 @@ +* Novatek nt36xxx touch controller + +Please add this description here: The Novatek Touch controller is connected to the +host processor via I2C. The controller generates interrupts when the user touches +the panel. The host controller is expected to read the touch coordinates over I2C and +pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "novatek,NVT-ts" + - reg : i2c slave address of the device. + - vdd-supply : digital voltage power supply needed to power device. + - avdd-supply : analog voltage power supply needed to power device. + - novatek,reset-gpio : reset gpio. + - novatek,irq-gpio : irq gpio. + +Example: + &i2c_1 { + status = "ok"; + + /* Novatek device tree node */ + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + status = "ok"; + + vdd-supply = <&pm8994_lvs2>; + avdd-supply = <&pm8994_l22>; + + novatek,reset-gpio = <&msm_gpio 102 0x00>; + novatek,irq-gpio = <&msm_gpio 65 0x2001>; + }; + }; \ No newline at end of file From 2a29e84f1c631bf8e819bf6dd26acaadc8230c92 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Tue, 5 Jan 2021 10:35:42 -0800 Subject: [PATCH 0583/1809] ARM: dts: msm: Add bindings for ARM performance measuring unit Add initial bindings for ARM PMU driver. This enables measurement of events like cycles, cache misses etc. Change-Id: I80521c085b90b851e38abf8af03da68711aa8120 --- bindings/arm/pmu.txt | 70 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 bindings/arm/pmu.txt diff --git a/bindings/arm/pmu.txt b/bindings/arm/pmu.txt new file mode 100644 index 000000000000..13611a8199bb --- /dev/null +++ b/bindings/arm/pmu.txt @@ -0,0 +1,70 @@ +* ARM Performance Monitor Units + +ARM cores often have a PMU for counting cpu and cache events like cache misses +and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU +representation in the device tree should be done as under:- + +Required properties: + +- compatible : should be one of + "apm,potenza-pmu" + "arm,armv8-pmuv3" + "arm,cortex-a73-pmu" + "arm,cortex-a72-pmu" + "arm,cortex-a57-pmu" + "arm,cortex-a53-pmu" + "arm,cortex-a35-pmu" + "arm,cortex-a17-pmu" + "arm,cortex-a15-pmu" + "arm,cortex-a12-pmu" + "arm,cortex-a9-pmu" + "arm,cortex-a8-pmu" + "arm,cortex-a7-pmu" + "arm,cortex-a5-pmu" + "arm,arm11mpcore-pmu" + "arm,arm1176-pmu" + "arm,arm1136-pmu" + "brcm,vulcan-pmu" + "cavium,thunder-pmu" + "qcom,scorpion-pmu" + "qcom,scorpion-mp-pmu" + "qcom,krait-pmu" +- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu + interrupt (PPI) then 1 interrupt should be specified. + +Optional properties: + +- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + +- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd + events. + +- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +Example: + +pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <100 101>; +}; From 043c3d60b4f45da1f1fef764e3c74f60eef443f9 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Mon, 4 Jan 2021 17:19:56 -0800 Subject: [PATCH 0584/1809] ARM: dts: msm: Add device node for ARM PMU for Olympic Add the ARM CPU Performace measuring unit device tree node to measure various hardware events like cache misses, cycles etc. Change-Id: If0d1f358757586e7774ce2810c4683dbc152da66 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f833437c3762..cdc92be053cd 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -257,6 +257,11 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + qcom,msm-imem@1468f000 { compatible = "qcom,msm-imem"; reg = <0x1468f000 0x1000>; /* Address and size of IMEM */ From 5d0dac9fe45db2e96b155a3ca1d7422794b40029 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Thu, 17 Dec 2020 13:57:00 -0800 Subject: [PATCH 0585/1809] ARM: dts: msm: Add support for ddr scaling on sdxlemur Add ddr bandwidth table and other dt nodes to support ddr bandwidth scaling for sdxlemur target. Change-Id: I9580bd0bb7d78019b2750a2bb7f8df273560dce0 --- qcom/sdxlemur.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index cdc92be053cd..d9276398b37b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -10,6 +10,9 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + / { #address-cells = <1>; #size-cells = <1>; @@ -437,6 +440,50 @@ status = "disabled"; }; + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 100, 4); /* 381 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_tbl: qcom,cpu0-cpu-ddr-tbl { + qcom,core-dev-table = + < 345600 MHZ_TO_MBPS( 300, 4) >, + < 576000 MHZ_TO_MBPS( 768, 4) >, + < 1440000 MHZ_TO_MBPS(1555, 4) >, + < 1497600 MHZ_TO_MBPS(2092, 4) >; + }; + + memlat_cpugrp: qcom,memlat-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0>; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,core-dev-table = <&cpu0_cpu_ddr_tbl>; + }; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; From 34f0a89aa4e55483f91e8fb4fd04921d3956e4e4 Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Tue, 5 Jan 2021 17:48:04 -0800 Subject: [PATCH 0586/1809] ARM: dts: msm: enable HOLB monitor feature Enable HOLB monitor feature. Change-Id: I2c725f17e1454f41a447aeec495869c4050385c7 --- qcom/sdxlemur.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 9b43f3c57fbf..411ad2de3696 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1070,6 +1070,10 @@ qcom,ipa-wdi3-over-gsi; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; + qcom,ipa-uc-holb-monitor; + qcom,ipa-holb-monitor-poll-period = <5>; + qcom,ipa-holb-monitor-max-cnt-wlan = <10>; + qcom,ipa-holb-monitor-max-cnt-usb = <10>; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; From c603e634a8ee55aa13f386f2492dce2ac216a456 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Wed, 6 Jan 2021 11:16:29 +0530 Subject: [PATCH 0587/1809] ARM: dts: msm: remove kgsl smmu interconnect node for Lahaina Remove kgsl smmu interconnect node. For TCU config register access we shouldn't required DDR path votes. KGSL smmu already votes for clock and regulator so it should be fine. Change-Id: I7ecf688aeafe07c6a844220b217a5f49380b6795 --- qcom/msm-arm-smmu-lahaina.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index f373834017d1..862492a73ce7 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -35,8 +35,6 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; - qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x400 0x32B>, From a91bdb9f1be42f707cbab44e3b86bce3f6ba91d4 Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Wed, 6 Jan 2021 12:04:02 +0530 Subject: [PATCH 0588/1809] ARM: dts: msm: Correct QUPv3 device nodes Fix interrupt number, usage of shared flag and GSI mask values. Also remove the obsolete device nodes. Change-Id: Ia735f1f0402e56688a4bb6068b5db4e2f3e7614c --- qcom/yupik-qupv3.dtsi | 86 +++++++++++++++++-------------------------- 1 file changed, 34 insertions(+), 52 deletions(-) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index 9bb6f89e0941..b6e0ba1b3e4f 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -55,7 +55,7 @@ , , ; - qcom,gpii-mask = <0xff>; + qcom,gpii-mask = <0x7f>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; @@ -67,7 +67,7 @@ compatible = "qcom,msm-geni-console"; reg = <0x994000 0x4000>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -84,7 +84,7 @@ reg = <0x980000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -105,7 +105,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -126,7 +126,7 @@ reg = <0x984000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -138,6 +138,7 @@ <&gpi_dma0 1 1 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_0>; + qcom,shared; status = "disabled"; }; @@ -147,7 +148,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -168,7 +169,7 @@ reg = <0x988000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -189,7 +190,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -210,7 +211,7 @@ reg = <0x98c000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -231,7 +232,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -252,7 +253,7 @@ reg = <0x990000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -273,7 +274,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -294,7 +295,7 @@ reg = <0x998000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -315,7 +316,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, @@ -336,7 +337,7 @@ compatible = "qcom,msm-geni-serial-hs"; reg = <0x99c000 0x4000>; reg-names = "se_phys"; - interrupts-extended = <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 31 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, @@ -390,7 +391,7 @@ , ; qcom,static-gpii-mask = <0x1>; - qcom,gpii-mask = <0x7e>; + qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; @@ -403,7 +404,7 @@ reg = <0xa80000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -424,7 +425,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -445,7 +446,7 @@ reg = <0xa84000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -466,7 +467,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -486,7 +487,7 @@ compatible = "qcom,msm-geni-serial-hs"; reg = <0xa88000 0x4000>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -504,7 +505,7 @@ reg = <0xa88000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -525,7 +526,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -546,7 +547,7 @@ reg = <0xa8c000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -567,7 +568,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -588,7 +589,7 @@ reg = <0xa90000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -609,7 +610,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -630,7 +631,7 @@ reg = <0xa94000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -642,7 +643,6 @@ <&gpi_dma1 1 5 3 64 2>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; - qcom,shared; status = "disabled"; }; @@ -652,7 +652,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -668,30 +668,12 @@ status = "disabled"; }; - /* Travel adapter over 2-wire HSUART, no wakeup */ - qupv3_se14_2uart: qcom,qup_uart@a98000 { - compatible = "qcom,msm-geni-serial-hs"; - reg = <0xa98000 0x4000>; - reg-names = "se_phys"; - interrupts = ; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, - <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; - pinctrl-0 = <&qupv3_se14_default_txrx>; - pinctrl-1 = <&qupv3_se14_2uart_active>; - pinctrl-2 = <&qupv3_se14_2uart_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - qupv3_se14_i2c: i2c@a98000 { compatible = "qcom,i2c-geni"; reg = <0xa98000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -712,7 +694,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -733,7 +715,7 @@ reg = <0xa9c000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, @@ -754,7 +736,7 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - interrupts = ; + interrupts = ; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, From fdb14d445b00271588a1ce3a6024d09b44ca9eee Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 23 Dec 2020 22:51:23 +0530 Subject: [PATCH 0589/1809] ARM: dts: msm: Add cpu clock node for sdxnightjar The CPU clock node is required to be enabled to be able to switch various CPU clock. While at it, also update the regulator phandles to use the levels phandles. Change-Id: I1ee31ca20e565664e21b0d8f5e6a9f4be5787c76 --- qcom/sdxnightjar.dtsi | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8337f22edeb9..6ddab81f4740 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; @@ -125,8 +126,8 @@ compatible = "qcom,sdxnightjar-gcc", "syscon"; reg = <0x1800000 0x80000>; reg-names = "cc_base"; - vdd_cx-supply = <&pmd9650_s5_level>; - vdd_cx_ao-supply = <&pmd9650_s5_level_ao>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>; clock-names = "bi_tcxo", "bi_tcxo_ao"; @@ -134,9 +135,15 @@ #reset-cells = <1>; }; + cpucc: syscon@b01101c { + compatible = "syscon"; + reg = <0xb01101c 0x4>; + }; + debugcc: qcom,cc-debug@1874000 { compatible = "qcom,sdxnightjar-debugcc"; qcom,gcc = <&gcc>; + qcom,cpucc = <&cpucc>; clock-names = "xo_clk_src"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; #clock-cells = <1>; @@ -154,6 +161,24 @@ reg = <0x0185d044 0x4>; }; + apsscc: clock-controller@b010008 { + compatible = "qcom,sdxnightjar-apsscc"; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0_AO>; + clock-names = "bi_tcxo_ao", "gpll0_out_even"; + reg = <0xb010008 0x8>, <0xb008018 0x28>; + reg-names = "apcs_cmd", "apcs_pll"; + vdd-pll-supply = <&VDD_CX_LEVEL_AO>; + cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; + qcom,speed0-bin-v0 = + < 0 RPM_SMD_REGULATOR_LEVEL_NONE>, + < 200000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS>, + < 384000000 RPM_SMD_REGULATOR_LEVEL_SVS>, + < 787200000 RPM_SMD_REGULATOR_LEVEL_NOM>, + < 1286400000 RPM_SMD_REGULATOR_LEVEL_TURBO>; + #clock-cells = <1>; + }; + qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; /*TODO: Fix the clock when tree is available*/ From 338c0369c02434f05e303ca7ad39ad420c7b4866 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 6 Jan 2021 13:54:39 +0530 Subject: [PATCH 0590/1809] ARM: dts: msm: correct refgen type for holi Correct the compatible property for refgen regulator used on holi. Change-Id: I623a0a3d2acd4f22419858fac50e7801397b4518 --- qcom/holi-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index d52be021a107..6de77ac0f4ba 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -570,7 +570,7 @@ &soc { refgen: refgen-regulator@162F000 { - compatible = "qcom,refgen-kona-regulator"; + compatible = "qcom,refgen-regulator"; reg = <0x162F000 0x60>; regulator-name = "refgen"; regulator-enable-ramp-delay = <5>; From 61b9aeffe464a3a98c4ad25084c6468bc0a568b0 Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Tue, 5 Jan 2021 17:10:29 +0800 Subject: [PATCH 0591/1809] ARM: dts: msm: Enable bluetooth for sdxnightjar Enable bluetooth for sdxnightjar. CRs-Fixed: 2848490 Change-Id: Iedb40bb8208128a94bf1b6e76a1b2e633a570895 --- qcom/sdxnightjar-bluetooth.dtsi | 36 +++++++++++++++++++++++++++++++ qcom/sdxnightjar-cdp.dts | 1 + qcom/sdxnightjar-dualwifi-mtp.dts | 1 + qcom/sdxnightjar-mtp.dts | 1 + 4 files changed, 39 insertions(+) create mode 100644 qcom/sdxnightjar-bluetooth.dtsi diff --git a/qcom/sdxnightjar-bluetooth.dtsi b/qcom/sdxnightjar-bluetooth.dtsi new file mode 100644 index 000000000000..578fd72d2fc9 --- /dev/null +++ b/qcom/sdxnightjar-bluetooth.dtsi @@ -0,0 +1,36 @@ +&pmd9650_gpios { + bt_en { + bt_en_default: bt_en_default { + pins = "gpio8"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <0>; + }; + }; +}; + +&soc { + bluetooth: bt_qca6490 { + compatible = "qcom,qca6174"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default>; + qcom,bt-reset-gpio = <&pmd9650_gpios 8 0>; /* BT_EN */ + + qcom,bt-vdd-aon-supply = <&L4A>; + qcom,bt-vdd-aon-config = <928000 928000 0 0>; + qcom,bt-vdd-io-supply = <&L5A>; + qcom,bt-vdd-io-config = <1800000 1800000 0 0>; + qcom,bt-vdd-core-supply = <&rome_vreg>; + qcom,bt-vdd-core-config = <0 0 0 0>; + }; +}; + +&blsp1_uart2_hs { + status = "okay"; +}; + +&spi_2 { + status = "disabled"; +}; diff --git a/qcom/sdxnightjar-cdp.dts b/qcom/sdxnightjar-cdp.dts index 58a5bf7cdc99..1afb792b629d 100644 --- a/qcom/sdxnightjar-cdp.dts +++ b/qcom/sdxnightjar-cdp.dts @@ -2,6 +2,7 @@ #include "sdxnightjar.dtsi" #include "sdxnightjar-cdp.dtsi" +#include "sdxnightjar-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDX NIGHTJAR CDP"; diff --git a/qcom/sdxnightjar-dualwifi-mtp.dts b/qcom/sdxnightjar-dualwifi-mtp.dts index ee12068b8c8e..31514c860b21 100644 --- a/qcom/sdxnightjar-dualwifi-mtp.dts +++ b/qcom/sdxnightjar-dualwifi-mtp.dts @@ -2,6 +2,7 @@ #include "sdxnightjar.dtsi" #include "sdxnightjar-mtp.dtsi" +#include "sdxnightjar-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP - DWIFI"; diff --git a/qcom/sdxnightjar-mtp.dts b/qcom/sdxnightjar-mtp.dts index 65e7fcd1c964..bae253df1376 100644 --- a/qcom/sdxnightjar-mtp.dts +++ b/qcom/sdxnightjar-mtp.dts @@ -2,6 +2,7 @@ #include "sdxnightjar.dtsi" #include "sdxnightjar-mtp.dtsi" +#include "sdxnightjar-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP"; From 2f2549d26c1725f80c6600ce41329af9d6132464 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 22 Dec 2020 20:41:26 +0530 Subject: [PATCH 0592/1809] ARM: dts: msm: Enable SMB1351 for sdxnightjar Enable SMB1351 for sdxnightjar, SMB1351 is a single-cell battery charger. It can charge the battery and power the system via the USB/AC adapter input. Change-Id: I9d8c8431d7dd49a5b2e8a7936058f7df77d5ef0f --- qcom/sdxnightjar-pinctrl.dtsi | 2 +- qcom/sdxnightjar.dtsi | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index 31438ed9f00b..ac2ca4510732 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -1392,7 +1392,7 @@ bias-high-impedance; /* DISABLE GPIO */ }; - gpio@c400 { /* GPIO 5 - USB_ID */ + usb_id_detect: gpio@c400 { /* GPIO 5 - USB_ID */ pins = "gpio5"; function = "normal"; input-enable; /* Digital input */ diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index fffbd92d1d50..3009b39b50cc 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -812,3 +812,26 @@ #include "sdxnightjar-coresight.dtsi" #include "sdxnightjar-pinctrl.dtsi" #include "sdxnightjar-blsp.dtsi" + +&i2c_3 { + status = "ok"; + smb1351_otg_supply: smb1351-charger@55 { + compatible = "qcom,smb1351-charger"; + reg = <0x55>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <83 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm_pinmux 83 IRQ_TYPE_LEVEL_LOW>, <&pmd9650_gpios 5 0>; + interrupt-names = "smb1351_chg_stat_irq","smb1351_usb_id_irq"; + qcom,usb-id-gpio = <&pmd9650_gpios 5 0>; + qcom,float-voltage-mv = <4200>; + qcom,charging-timeout = <1536>; + qcom,recharge-thresh-mv = <200>; + qcom,iterm-ma = <100>; + regulator-name = "smb1351_otg_supply"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_active>, <&usb_id_detect>; + qcom,switch-freq = <2>; + qcom,id-line-not-connected; + dpdm-supply = <&qusb_phy>; + }; +}; From e6ef72b48a981d69c34cc84b5da2861efeb5d636 Mon Sep 17 00:00:00 2001 From: Satish Kodishala Date: Wed, 6 Jan 2021 15:15:47 +0530 Subject: [PATCH 0593/1809] ARM: dts: qcom: Add dtsi entry for BT slimbus in yupik Add BT slimbus node entry in yupik dt. CRs-Fixed: 2849376 Change-Id: If2546f1d98f37d734786232393c0e098ae9fb869 --- qcom/yupik.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..c712eecdc31e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -430,6 +430,14 @@ qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; + + /* Slimbus Slave DT for QCA6490 */ + btfmslim_codec: qca6490 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 21 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 21 02 17 02]; + }; }; intc: interrupt-controller@17a00000 { From 9e320d1cc0cc640600d558dbc15c9c49f02dfcda Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 5 Jan 2021 16:07:55 +0530 Subject: [PATCH 0594/1809] dt-bindings: ufs: Add compatible string for yupik phy driver This change add compatible string information for yupik UFS phy driver. Change-Id: I79a898fb5abb80cdb159ac63231f7a0e02f88beb --- bindings/ufs/ufs-qcom.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index c4e221a8c05e..ce95343f685b 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -16,6 +16,8 @@ Required properties: for sdm845 emulation, "qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy present on Lahaina chipset. + "qcom,ufs-phy-qmp-v4-yupik" for V4 ufs phy + present on yupik chipset. "qcom,ufs-phy-qmp-v4" for V4 ufs phy present on SM8150 chipset. "qcom,ufs-phy-qmp-v3" for V3 ufs phy From a92910f592d782448526151f2c11fed94c55702c Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 07:40:56 +0530 Subject: [PATCH 0595/1809] ARM: dts: msm: Add device node for IMEM on SM8150 Add IMEM device tree node on sm8150 target. Change-Id: I3fac756393c9d5152a52b3f42bcf35163584d7e9 --- qcom/sm8150.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index b267c74748e4..0a34f1cc28ac 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -678,6 +678,49 @@ }; }; + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From f2e2f9d4ea8714bd903f19d7398395492f47a9f3 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 16 Jul 2020 10:43:22 +0530 Subject: [PATCH 0596/1809] ARM: dts: msm: Add modem device node for PIL SM8150 Add PIL device tree node to load firmware images of modem on SM8150. Change-Id: I2e6c2c0c5e20c948213bd9fa7873d86ac13bb140 --- qcom/sa8155-adp-common.dtsi | 4 +++ qcom/sa8155.dtsi | 5 ++++ qcom/sm8150.dtsi | 49 +++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index 431edd4ef15f..fefcd3bad4be 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -57,3 +57,7 @@ &qupv3_se12_2uart { status = "ok"; }; + +&pil_modem { + status = "disabled"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index bfc7cfe41273..0df8a5221cd3 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -101,6 +101,11 @@ parent-supply = <&VDD_GFX_LEVEL>; }; + +&pil_modem { + vdd_mss-supply = <&pm8150_1_s8_level>; +}; + &ufsphy_mem { vdda-phy-supply = <&pm8150_2_l18>; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 0a34f1cc28ac..e6ce2a1ce7b9 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1678,6 +1678,55 @@ vote = <44>; }; }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&pm8150_s1_level>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&pdc 0 266 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; }; &firmware { From f3b1e79deb4866d560a68b0431b5f62fdd24ea75 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 16 Jul 2020 14:41:14 +0530 Subject: [PATCH 0597/1809] ARM: dts: msm: Add slpi device node for PIL on SM8150 Add PIL device tree node to load firmware images of slpi on sm8150. Change-Id: I890b05c40aea755c1c631a3b1e7556bfca155f80 --- qcom/sa8155.dtsi | 4 ++++ qcom/sm8150.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 0df8a5221cd3..ff361ab4427e 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -101,6 +101,10 @@ parent-supply = <&VDD_GFX_LEVEL>; }; +&pil_ssc { + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; +}; &pil_modem { vdd_mss-supply = <&pm8150_1_s8_level>; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index e6ce2a1ce7b9..2846681eda10 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1727,6 +1727,54 @@ mboxes = <&qmp_aop 0>; mbox-names = "mss-pil"; }; + + pil_ssc: qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + + vdd_cx-supply = <&pm8150_l8_level>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&pm8150_l4_level>; + qcom,vdd_mx-uV-uA = ; + + qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; + qcom,keep-proxy-regs-on; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from ssc */ + interrupts-extended = <&pdc 0 494 1>, + <&dsps_smp2p_in 0 0>, + <&dsps_smp2p_in 2 0>, + <&dsps_smp2p_in 1 0>, + <&dsps_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to ssc */ + qcom,smem-states = <&dsps_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "slpi-pil"; + }; }; &firmware { From ecc5553052c1acfd2982d018b06a1d3931577ea6 Mon Sep 17 00:00:00 2001 From: Anil Kumar Kanakanti Date: Tue, 5 Jan 2021 17:14:54 +0530 Subject: [PATCH 0598/1809] ARM: dts: msm: Add camera device pinctrl change for Yupik camera Include GPIO pinctrl changes for cam sensor and cci device nodes for Yupik camera. Change-Id: Ic7de3d4478a222bcd5e716d45bade508bd6f11e3 --- qcom/yupik-pinctrl.dtsi | 398 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 398 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 23c867f78890..356cec7b0c21 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1144,6 +1144,146 @@ }; }; + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + /* WSA speaker reset pins */ spkr_1_sd_n { spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { @@ -1233,6 +1373,264 @@ }; }; + cam_sensor_active_rst0: cam_sensor_active_rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 3 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 3 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 4 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 4 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* DATA, CLK */ + pins = "gpio69","gpio70"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio69","gpio70"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* DATA, CLK */ + pins = "gpio69","gpio70"; + function = "cci_i2c"; + }; + + config { + pins = "gpio69","gpio70"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* DATA, CLK */ + pins = "gpio71","gpio72"; + function = "cci_i2c"; + }; + + config { + pins = "gpio71","gpio72"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* DATA, CLK */ + pins = "gpio71","gpio72"; + function = "cci_i2c"; + }; + + config { + pins = "gpio71","gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* DATA, CLK */ + pins = "gpio73","gpio74"; + function = "cci_i2c"; + }; + + config { + pins = "gpio73","gpio74"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* DATA, CLK */ + pins = "gpio73","gpio74"; + function = "cci_i2c"; + }; + + config { + pins = "gpio73","gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* DATA, CLK */ + pins = "gpio75","gpio76"; + function = "cci_i2c"; + }; + + config { + pins = "gpio75","gpio76"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* DATA, CLK */ + pins = "gpio75","gpio76"; + function = "cci_i2c"; + }; + + config { + pins = "gpio75","gpio76"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + }; + pri_aux_pcm_clk { pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { mux { From ea84bb0f581f72faff7ff95a1fb185dd03a40b9f Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 07:50:30 +0530 Subject: [PATCH 0599/1809] ARM: dts: msm: Add device node for PIL scm pas on SM8150 Add PIL device tree node for pil_scm_pas on sm8150. Change-Id: I475359192355a1b9c22505036e00355666aabc09 --- qcom/sm8150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index b267c74748e4..885fa909f0b3 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -683,6 +683,12 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO + &mc_virt SLAVE_EBI1>; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 343be50d3314154a357abf3b04a2f6d796d0402c Mon Sep 17 00:00:00 2001 From: Kasin Li Date: Tue, 20 Oct 2020 10:36:32 +0800 Subject: [PATCH 0600/1809] ARM: dts: msm: add bindings for HGSL driver Hgsl communicates with GPU hardware using either GPU registers or TCSR compute signaling hardware block. Change-Id: I881941953ee2340a4c47f10e85e4b0a1dfb87a50 --- bindings/soc/qcom/hgsl-tcsr.txt | 31 +++++++++++++++++++++++++++++++ bindings/soc/qcom/hgsl.txt | 30 ++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 bindings/soc/qcom/hgsl-tcsr.txt create mode 100644 bindings/soc/qcom/hgsl.txt diff --git a/bindings/soc/qcom/hgsl-tcsr.txt b/bindings/soc/qcom/hgsl-tcsr.txt new file mode 100644 index 000000000000..80e237de49fa --- /dev/null +++ b/bindings/soc/qcom/hgsl-tcsr.txt @@ -0,0 +1,31 @@ +Top Control and Status Register(TCSR) for HGSL + +TCSR hardware contains compute signal sub-block, which allows drivers in hypervisor +Linux to communicate with GPU hardware directly. This HGSL TCSR driver is to enable +the TCSR compute signal hardware. There are multiple instances of compute signal. +Each instance is either a signal sender or signal receiver. + +The HGSL TCSR driver is built on top of generic TCSR driver, refer to +Documentation/devicetree/bindings/mfd/qcom,tcsr.txt for the generic TCSR driver. + +Required properties: +- compatible : Must be "qcom,hgsl-tcsr-sender" or "qcom,hgsl-tcsr-receiver" +- syscon : Point to the generic TCSR compute signal node +- syscon-glb : Point to the generice TCSR node for compute signal global control. + This is only needed by signal sender. +- interrupts : Specify IRQ information used by the compute signal. + This is only needed by signal receiver. + +Examples: + hgsl_tcsr_sender0: hgsl_tcsr_sender0 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender0>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver0>; + interrupts = <0 238 0>; + }; + diff --git a/bindings/soc/qcom/hgsl.txt b/bindings/soc/qcom/hgsl.txt new file mode 100644 index 000000000000..4b608005b5ce --- /dev/null +++ b/bindings/soc/qcom/hgsl.txt @@ -0,0 +1,30 @@ +* HGSL + +HGSL(Hypervisor Graphics system layer) is graphics driver under the hypervisor system. + +Required properties: +- compatible : Must be "qcom,hgsl" + +- reg : physical base address and length of the register set(s). + +- reg-names : names corresponding to each reg property value. + reg_hwver: HW version registers + reg_doorbell_idx: address of GMUAO_DOORBELL_IDX + +Optional properties: +- qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select + which sender to use. The driver will use TCSR compute signal to + send signal to GPU. +- qcom,glb-db-receivers : Point to possible nodes of HGSL TCSR receiver. The user will + select which receiver to use. The driver will use TCSR compute + signal to receive signal from GPU. + +Example: + msm_gpu_hyp { + compatible = "qcom,hgsl"; + reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; + reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + + qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>; + qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>; + }; From f35a6138330f5b7fdd31fa314a0c503668e0c64f Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Thu, 7 Jan 2021 10:59:13 +0800 Subject: [PATCH 0601/1809] dt-bindings: add documentation for max31760 fancontroller Add documentation for MAX31760 Fan Controller driver. Change-Id: Ib065dec13fee8f5f7890468c8562fbf54206f35b --- bindings/thermal/max31760.txt | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 bindings/thermal/max31760.txt diff --git a/bindings/thermal/max31760.txt b/bindings/thermal/max31760.txt new file mode 100644 index 000000000000..db27cdbe5b0d --- /dev/null +++ b/bindings/thermal/max31760.txt @@ -0,0 +1,38 @@ +Bindings for the Maxim MAX31760 Intelligent Fan Controller +========================================================== + +The Maxim MAX31760 is a i2c device providing closed-loop, multi-channel fan +management with temperature. Various fan control features are provided, +including PWM frequency control, temperature hysteresis, dual tachometer +measurements, and fan health monitoring. + +Required properties: +- compatible : should be "maxim,max31760". +- reg : I2C address, 0x50. + +Optional properties: +- maxim,vdd-supply : regulator supplying the vdd pin +- maxim,vdd-max-uv : regulator max voltage +- maxim,vdd-min-uv : regulator min voltage +- maxim,vdd-load-ua : regulator load current output +- maxim,vcca-supply : regulator supplying the vcca pin +- maxim,vcca-max-uv : regulator max voltage +- maxim,vcca-min-uv : regulator min voltage +- maxim,vcca-load-ua : regulator load current output +- maxim,fan_en_gpio : fan enable gpio + +Example: + max31760@50 { + compatible = "maxim,max31760"; + reg = <0x50>; + maxim,vdd-supply = <&some_reg>; + regulator-names = "maxim,vdd"; + maxim,vdd-max-uv = <3400000>; + maxim,vdd-min-uv = <3300000>; + maxim,vdd-load-ua = <300000>; + maxim,vcca-supply = <&some_reg>; + maxim,vcca-max-uv = <1800000>; + maxim,vcca-min-uv = <1800000>; + maxim,vcca-load-ua = <600000>; + maxim,fan_en_gpio = <&tlmm 10 0x00>; + }; From 9298de6f20f31790c1be77da659733b7493b3021 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 16 Dec 2020 15:29:46 +0530 Subject: [PATCH 0602/1809] ARM: dts: msm: add dcvs nodes for yupik target Add dcvs nodes for yupik target needed to scale L3, LLCC and DDR frequencies. Change-Id: Ic891e8e78efadd08727da5bb055727f51c915509 --- qcom/yupik.dtsi | 563 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 563 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..2f4cf6649e8f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -15,6 +15,15 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} +#define DDR_TYPE_LPDDR4X 7 +#define DDR_TYPE_LPDDR5 8 + + / { model = "Qualcomm Technologies, Inc. Yupik"; compatible = "qcom,yupik"; @@ -1180,6 +1189,560 @@ status = "disabled"; }; + llcc_pmu: llcc-pmu@9095000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x09095000 0x300>; + reg-names = "lagg-base"; + }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + BW_OPP_ENTRY( 1066, 16); /* 15258 MB/s */ + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */ + BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */ + BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */ + BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */ + BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */ + BW_OPP_ENTRY_DDR( 1017, 4, 0x80); /* 3879 MB/s */ + BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */ + BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */ + BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /* 6515 MB/s */ + BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */ + BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */ + BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */ + BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */ + }; + + qoslat_opp_table: qoslat-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + + opp-2 { + opp-hz = /bits/ 64 < 2 >; + }; + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "bw_hwmon"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "bw_hwmon"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x9091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + snoop_l3_bw: qcom,snoop-l3-bw { + compatible = "qcom,devfreq-icc-l3bw"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + qcom,bus-width = <32>; + governor = "bw_hwmon"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + + snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b9100 0x300>, <0x90b9000 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&snoop_l3_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU5>; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; + }; + + cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "compute"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "mem_latency"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "mem_latency"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "compute"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "compute"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "compute"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat { + compatible = "qcom,devfreq-qoslat"; + governor = "mem_latency"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + + cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor { + compatible = "qcom,devfreq-qoslat"; + governor = "mem_latency"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 691200 556800000 >, + < 806400 652800000 >, + < 940800 768000000 >, + < 1152000 844800000 >, + < 1324800 1065600000 >, + < 1516800 1190400000 >, + < 1651200 1305600000 >, + < 1804800 1516800000 >; + }; + + cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl { + qcom,core-dev-table = + < 940800 556800000 >, + < 12288000 768000000 >, + < 1651200 1190400000 >, + < 1900800 1401600000 >, + < 2400000 1516800000 >; + }; + + cpu7_cpu_l3_tbl: qcom,cpu7-cpu-l3-tbl { + qcom,core-dev-table = + < 1056000 556800000 >, + < 1324800 768000000 >, + < 1766400 1190400000 >, + < 2208000 1401600000 >, + < 2707200 1516800000 >; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu7_cpu_l3_tbl>; + }; + + cpu7_l3_computemon: qcom,cpu7-l3-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_latfloor>; + qcom,core-dev-table = + < 2035200 300000000 >, + < 2707200 1516800000 >; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 1152000 MHZ_TO_MBPS( 300, 16) >, + < 1516800 MHZ_TO_MBPS( 466, 16) >, + < 1804800 MHZ_TO_MBPS( 600, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 940800 MHZ_TO_MBPS( 451, 4) >, + < 1152000 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS( 1017, 4) >; + }; + + ddr5-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 940800 MHZ_TO_MBPS( 451, 4) >, + < 1152000 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS( 1555, 4) >; + }; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1152000 MHZ_TO_MBPS( 451, 4) >, + < 1516800 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 691000 MHZ_TO_MBPS( 300, 16) >, + < 940800 MHZ_TO_MBPS( 466, 16) >, + < 1228800 MHZ_TO_MBPS( 600, 16) >, + < 1651200 MHZ_TO_MBPS( 806, 16) >, + < 2400000 MHZ_TO_MBPS( 933, 16) >, + < 2707200 MHZ_TO_MBPS( 1066, 16) >; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 691000 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS(1017, 4) >, + < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 2380800 MHZ_TO_MBPS(1708, 4) >, + < 2707200 MHZ_TO_MBPS(2133, 4) >; + }; + + ddr5-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 691000 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS( 768, 4) >, + < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >, + < 2380800 MHZ_TO_MBPS(2092, 4) >, + < 2707200 MHZ_TO_MBPS(3196, 4) >; + }; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 691000 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651800 MHZ_TO_MBPS(1017, 4) >, + < 1900800 MHZ_TO_MBPS(1555, 4) >, + < 2400000 MHZ_TO_MBPS(1708, 4) >, + < 2707200 MHZ_TO_MBPS(2133, 4) >; + }; + + ddr5-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 691000 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >, + < 2400000 MHZ_TO_MBPS(2092, 4) >, + < 2707200 MHZ_TO_MBPS(3196, 4) >; + }; + }; + + cpu4_llcc_computemon: qcom,cpu4-llcc-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu4_cpu_llcc_latfloor>; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,core-dev-table = + < 1900800 MHZ_TO_MBPS( 150, 16) >, + < 2707200 MHZ_TO_MBPS( 600, 16) >; + }; + + cpu7_computemon: qcom,cpu7-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu7_cpu_ddr_latfloor>; + qcom,cpulist = <&CPU7>; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 2380800 MHZ_TO_MBPS( 451, 4) >, + < 2707200 MHZ_TO_MBPS(2133, 4) >; + }; + + ddr5-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 2380800 MHZ_TO_MBPS( 451, 4) >, + < 2707200 MHZ_TO_MBPS(3196, 4) >; + }; + }; + + cpu4_qoslatmon: qcom,cpu4-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_qoslat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 1 >, + < 3000000 2 >; + }; + + cpu7_qoslatmon: qcom,cpu7-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 2035200 1 >, + < 2707200 2 >; + }; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 4a1b850b6ff0909fbb366fcfd1560c3fd8aee96d Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Thu, 7 Jan 2021 12:00:27 +0530 Subject: [PATCH 0603/1809] ARM: dts: msm: Update GIC interrupt polarity for Yupik Correct the interrupt polarity for GIC. Here, we are changing interrupt polarity for GIC to adhere with other chipsets. Change-Id: Ibe8b561bb6caac586d10014930cd19fba544e308 --- qcom/yupik.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..d5b93e2c4c78 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -440,7 +440,7 @@ redistributor-stride = <0x0 0x20000>; reg = <0x17a00000 0x10000>, /* GICD */ <0x17a60000 0x100000>; /* GICR * 8 */ - interrupts = ; + interrupts = ; }; pdc: interrupt-controller@b220000 { From 6b40000d5b1e30d8dc3df8f3155f30e0725b7c47 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 5 Jan 2021 14:15:47 +0530 Subject: [PATCH 0604/1809] ARM: dts: msm: Add feature config node for qfprom for Yupik Add feature config node for qfprom for reading fuse bits for Yupik SoC. Change-Id: Id839a115243f28c548a12688d51261b15a734966 --- qcom/yupik.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..868b9fd258a4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2407,10 +2407,17 @@ #size-cells = <1>; read-only; ranges; + + feat_conf_m7: feat_conf_m7@6020 { + reg = <0x6020 0x4>; + }; }; qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&feat_conf_m7>; + nvmem-cell-names = "feat_conf_m7"; }; }; From f316097565470544032f9c2e42e64f4db863a3dc Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 29 Dec 2020 19:11:21 +0530 Subject: [PATCH 0605/1809] ARM: dts: msm: Add SDIO support for sdxnightjar Add SDIO support for sdxnightjar. Change-Id: Ib6d3df8894cc993d362b253c42c378013c438d31 --- qcom/sdxnightjar-dualwifi-mtp.dts | 17 +++++++++++++++++ qcom/sdxnightjar-pinctrl.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/qcom/sdxnightjar-dualwifi-mtp.dts b/qcom/sdxnightjar-dualwifi-mtp.dts index ee12068b8c8e..99a4e0263741 100644 --- a/qcom/sdxnightjar-dualwifi-mtp.dts +++ b/qcom/sdxnightjar-dualwifi-mtp.dts @@ -9,3 +9,20 @@ "qcom,sdxnightjar", "qcom,mtp"; qcom,board-id = <8 3>; }; + +&sdhc_1 { + vdd-io-supply = <&pmd9650_l7>; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-always-on; + qcom,vdd-io-current-level = <0 10000>; + + keep-power-in-suspend; + qcom,core_3_0v_support; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_wlan_gpio_active>; + pinctrl-1 = <&sdc2_off &sdc2_wlan_gpio_sleep>; + + status = "ok"; +}; diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index 31438ed9f00b..27f9f8ee576c 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -441,6 +441,36 @@ }; }; + sdc2_wlan_gpio { + sdc2_wlan_gpio_active: sdc2_wlan_gpio_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc2_wlan_gpio_sleep: sdc2_wlan_gpio_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + /* SMB CONFIGURATION */ pmx_smb_stat { smb_stat_active: smb_stat_active { From af2dba926e2fa1774ffa7b5e6dda6a98763e3d81 Mon Sep 17 00:00:00 2001 From: Devender Kaushik Date: Thu, 7 Jan 2021 16:05:42 +0530 Subject: [PATCH 0606/1809] ARM: dts: msm: add remote debugger support Add remote debugger device configuration. The Remote Debugger driver allows a debugger running on a host PC to communicate with a remote stub running on peripheral subsystems. Change-Id: I8ac42ca0d737f6891cc8eb4689a3c7e5653140df --- qcom/yupik.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..677df1a868bb 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1426,6 +1426,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-nsp { @@ -1448,6 +1459,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-modem { @@ -2560,3 +2582,4 @@ #include "yupik-qupv3.dtsi" #include "yupik-audio.dtsi" #include "camera/yupik-camera.dtsi" +#include "msm-rdbg.dtsi" From 0cde770cc679c7c3a7e7a75cd2fabe2b95e44b76 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 8 Jan 2021 13:49:22 +0800 Subject: [PATCH 0607/1809] bindings: Add device-tree bindings for pil-q6v5 driver Add device-tree bindings documentation describing the properties for the pil-q6v5 driver. Change-Id: I8b91cefc4b4cdf226d28565705c2815edc1b761c --- bindings/pil/pil-q6v5-mss.txt | 151 ++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 bindings/pil/pil-q6v5-mss.txt diff --git a/bindings/pil/pil-q6v5-mss.txt b/bindings/pil/pil-q6v5-mss.txt new file mode 100644 index 000000000000..793a9652ec33 --- /dev/null +++ b/bindings/pil/pil-q6v5-mss.txt @@ -0,0 +1,151 @@ +Qualcomm Technologies Inc MSS QDSP6v5 Peripheral Image Loader + +pil-qdsp6v5-mss is a peripheral image loader (PIL) driver. It is used for +loading QDSP6v5 (Hexagon) firmware images for modem subsystems into memory and +preparing the subsystem's processor to execute code. It's also responsible for +shutting down the processor when it's not needed. + +Required properties: +- compatible: Must be "qcom,pil-q6v5-mss" or "qcom,pil-q6v55-mss" or + "qcom,pil-q6v56-mss". +- reg: Pairs of physical base addresses and region sizes of + memory mapped registers. +- reg-names: Names of the bases for the above registers. "qdsp6_base", + "rmb_base", "restart_reg" or "restart_reg_sec"(optional + for secure mode) are expected. + If "halt_base" is in same 4K pages this register then + this will be defined else "halt_q6", "halt_modem", + "halt_nc" is required. + "pdc_sync" is the power domain register introduced in + sdm845 for power domain of subsystems. + If alternative reset is required, "alt_reset" maps to + mss_alt_ares. +- interrupts: The modem watchdog interrupt +- vdd_cx-supply: Reference to the regulator that supplies the vdd_cx domain. +- vdd_cx-voltage: Voltage corner/level(max) for cx rail. +- vdd_mx-supply: Reference to the regulator that supplies the memory rail. +- vdd_mx-uV: Voltage setting for the mx rail. +- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp" + +Optional properties: +- vdd_mss-supply: Reference to the regulator that supplies the processor. + This may be a shared regulator that is already voted + on in the PIL proxy voting code (and also managed by the + modem on its own), hence we mark it as as optional. +- vdd_mss-uV: Voltage to set for vdd_mss. +- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail. +- qcom,vdd_pll: Voltage to be set for the PLL's rail. +- reg-names: "cxrail_bhs_reg" - control register for modem power + domain. +- clocks: Array of listing + all the clocks that are accesed by this subsystem. +- qcom,proxy-clock-names: Names of the clocks that need to be turned on/off during + proxy voting/unvoting. +- qcom,active-clock-names: Names of the clocks that need to be turned on for the + subsystem to run. Turned off when the subsystem is shutdown. +- clock-names: Names of all the clocks that are accessed by the subsystem. +- qcom,is-not-loadable: Boolean- Present if the image does not need to + be loaded. +- qcom,pil-self-auth: Boolean- True if authentication is required. +- qcom,mem-protect-id: Virtual ID used by PIL to call into TZ/HYP to protect/unprotect + subsystem related memory. +- qcom,gpio-err-fatal: GPIO used by the modem to indicate error fatal to the apps. +- qcom,gpio-err-ready: GPIO used by the modem to indicate error ready to the apps. +- qcom,gpio-proxy-unvote: GPIO used by the modem to trigger proxy unvoting in + the apps. +- qcom,gpio-force-stop: GPIO used by the apps to force the modem to shutdown. +- qcom,gpio-stop-ack: GPIO used by the modem to ack force stop or a graceful stop + to the apps. +- qcom,gpio-ramdump-disable: GPIO used by the modem to inform the apps that ramdump + collection should be disabled. +- qcom,gpio-shutdown-ack: GPIO used by the modem to indicate that it has done the + necessary cleanup and that the apps can move forward with + the shutdown sequence. +- qcom,restart-group: List of subsystems that will need to restart together. +- qcom,mba-image-is-not-elf: Boolean- Present if MBA image doesn't use the ELF + format. +- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL + service. +- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem. +- qcom,override-acc: Boolean- Present if we need to override the default ACC settings +- qcom,mss_pdc_offset: Integer- Mandatory if PDC register is specified. It is + used to specify which bit in the PDC register + corresponds to the modem. +- qcom,ahb-clk-vote: Boolean- Present if we need to remove the vote for the mss_cfg_ahb + clock after the modem boots up +- qcom,pnoc-clk-vote: Boolean- Present if the modem needs the PNOC bus to be + clocked before it boots up +- qcom,qdsp6v56-1-3: Boolean- Present if the qdsp version is v56 1.3 +- qcom,qdsp6v56-1-5: Boolean- Present if the qdsp version is v56 1.5 +- qcom,edge: GLINK logical name of the remote subsystem +- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown + on behalf of the subsystem driver. +- qcom,pil-mss-memsetup: Boolean - True if TZ need to be informed of modem start address and size. +- qcom,pas-id: pas_id of the subsystem. +- qcom,qdsp6v56-1-8: Boolean- Present if the qdsp version is v56 1.8 +- qcom,qdsp6v56-1-8-inrush-current: Boolean- Present if the qdsp version is V56 1.8 and has in-rush + current issue. +- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1 +- qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2 +- qcom,qdsp6v62-1-4: Boolean- Present if the qdsp version is v62 1.4 +- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5 +- qcom,qdsp6v65-1-0: Boolean- Present if the qdsp version is v65 1.0 +- qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory + wordline clamp, and compiler memory clamp during MSS restart. +- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10 +- qcom,override-acc-1: Override the default ACC settings with this value if present. +- qcom,minidump-id: Unique id for each subsystem +- qcom,reset-clk: Enable clock after MSS restart + +One child node to represent the MBA image may be specified, when the MBA image +needs to be loaded in a specifically carved out memory region. + +Required properties: +- compatible: Must be "qcom,pil-mba-mem" +- memory-region: A phandle that points to a reserved memory where the MBA image will be loaded. + +Example: + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg"; + interrupts = <0 24 1>; + vdd_mss-supply = <&pm8841_s3>; + vdd_cx-supply = <&pm8841_s2>; + vdd_cx-voltage = <7>; + vdd_mx-supply = <&pm8841_s1>; + vdd_mx-uV = <105000>; + + clocks = <&clock_rpm clk_xo_pil_mss_clk>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>; + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; + + qcom,is-not-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + qcom,mba-image-is-not-elf; + qcom,override-acc; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + qcom,ssctl-instance-id = <12>; + qcom,sysmon-id = <0>; + + qcom,mba-mem@0 { + compatible = "qcom,pil-mba-mem"; + memory-region = <&peripheral_mem>; + }; + }; From e03c652af18edf86dc6285d4bc0c1adab30c5d1e Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Fri, 8 Jan 2021 09:55:15 +0530 Subject: [PATCH 0608/1809] ARM: dts: msm: Add SMP2P entry and enable SIDs for WLAN Add smp2p entry to communicate between APPS and WPSS. Add SIDS and enable S1 bypass in ICNSS2 node. Change-Id: I26c082e65ac6b7d98b51bb91947060e23e66c2b8 --- qcom/yupik.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 956f177295b5..27128f7e6904 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1014,6 +1014,7 @@ compatible = "qcom,wcn6750"; reg = <0x17a10040 0x0>; reg-names = "msi_addr"; + iommus = <&apps_smmu 0x1c00 0x1>; interrupts = , , , @@ -1047,8 +1048,21 @@ , ; + qcom,iommu-dma = "bypass"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; cnss-daemon-support; + qcom,fw-prefix; + qcom,smem-states = <&smp2p_wlan_1_out 0>; + qcom,smem-state-names = "wlan-smp2p-out"; + + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; }; ufshc_mem: ufshc@1d84000 { @@ -1642,6 +1656,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_out: qcom,smp2p-wlan-1-out { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; }; qcom,glink { From b4df1eefbc07b73faabb2939f6edc0103cf8f955 Mon Sep 17 00:00:00 2001 From: xsang Date: Fri, 8 Jan 2021 14:36:15 +0800 Subject: [PATCH 0609/1809] ARM: dts: qcom: swap WSA enable pin Swap WSA enable pin due to right speaker using first one. Change-Id: I22679cc5615c30d718053692c11de97244203b26 --- qcom/yupik-audio-overlay.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index 19050be88416..918c21f49f4b 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -173,7 +173,7 @@ wsa883x_0221: wsa883x@02170221 { compatible = "qcom,wsa883x"; reg = <0x2 0x2170221>; - qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + qcom,spkr-sd-n-node = <&wsa_spkr_en2>; qcom,bolero-handle = <&bolero>; cdc-vdd-1p8-supply = <&L18B>; @@ -186,7 +186,7 @@ wsa883x_0222: wsa883x@02170222 { compatible = "qcom,wsa883x"; reg = <0x2 0x2170222>; - qcom,spkr-sd-n-node = <&wsa_spkr_en2>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; qcom,bolero-handle = <&bolero>; cdc-vdd-1p8-supply = <&L18B>; From 446dc787b06744d9130a05b59005e75f112771ce Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Sat, 2 Jan 2021 18:03:03 +0800 Subject: [PATCH 0610/1809] ARM: dts: msm: Added pil nodes for sdxnightjar Added entries for pil modem nodes on sdxnightjar. Change-Id: I1cfaef1fa1799501fea760ced44f2d68959f29b0 --- qcom/sdxnightjar.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index fffbd92d1d50..fb4004232753 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; @@ -112,6 +113,65 @@ }; }; + mss: qcom,mss@4080000{ + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x194e000 0x400>, + <0x4180000 0x040>, + <0x1810000 0x004>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK >, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_CLK_SRC>, + <&rpmcc RPM_SMD_QPIC_CLK>; + + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk", + "gpll0_mss_clk", "qpic"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", + "gpll0_mss_clk"; + + vdd_cx-supply = <&pmd9650_s5_level>; + interrupts = <0 24 1>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pmd9650_l9_level>; + vdd_mx-uV = ; + vdd_pll-supply = <&pmd9650_l5>; + qcom,vdd_pll = <1800000>; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,override-acc; + qcom,qdsp6v61-1-1; + memory-region = <&mss_mem>; + qcom,reset-clk; + qcom,sequential-fw-load; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + status = "ok"; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From fb67569025edea85d7b189c9b03b7f44e59156ce Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 17 Dec 2020 18:07:18 +0530 Subject: [PATCH 0611/1809] ARM: dts: msm: Adding IPA nodes for yupik target Adding IPA nodes for yupik target. Change-Id: If0a0c2d77117d51f2fe1e22258effba7984b777d --- qcom/yupik.dtsi | 148 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 956f177295b5..622017c45b96 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1620,6 +1620,18 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-wpss { @@ -2744,6 +2756,142 @@ dma-coherent-hint-cached; }; }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "yupik_ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_gsi_mem>; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + mboxes = <&qmp_aop 0>; + reg = + <0x1e00000 0x84000>, + <0x1e04000 0x23000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = + <0 654 IRQ_TYPE_LEVEL_HIGH>, + <0 432 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi3-over-gsi; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-64-bit-dma-mask; + qcom,ipa-endp-delay-wa-v2; + qcom,lan-rx-napi; + qcom,tx-napi; + qcom,wan-use-skb-page; + qcom,rmnet-ctl-enable; + qcom,ipa-uc-holb-monitor; + qcom,use-gsi-ipa-fw = "yupik_ipa_fws"; + qcom,gsi_wdi_db_polling; + qcom,ipa-holb-monitor-poll-period = <5>; + qcom,ipa-holb-monitor-max-cnt-wlan = <10>; + qcom,ipa-holb-monitor-max-cnt-usb = <10>; + qcom,ipa-holb-monitor-max-cnt-11ad = <10>; + qcom,tx-wrapper-cache-max-size = <400>; + qcom,ipa-gpi-event-rp-ddr; + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <150000 600000 150000 1804000 0 74000>; + + /* SVS */ + qcom,svs = + <625000 1200000 625000 3072000 0 150000>; + + /* NOMINAL */ + qcom,nominal = + <1250000 2400000 1250000 6220800 0 400000>; + + /* TURBO */ + qcom,turbo = + <2000000 3500000 2000000 7219200 0 400000>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x480 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x146A8000 0x146A8000 0x2000>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + qcom,ipa-q6-smem-size = <36864>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x482 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_11ad: ipa_smmu_11ad { + compatible = "qcom,ipa-smmu-11ad-cb"; + iommus = <&apps_smmu 0x483 0x0>; + dma-coherent; + qcom,shared-cb; + qcom,iommu-group = <>; + }; + }; }; #include "shima-gdsc.dtsi" From 43237301ff5d735f9e5c7f41e49314739f0b0c50 Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Thu, 7 Jan 2021 15:23:25 +0530 Subject: [PATCH 0612/1809] ARM: dts: msm: Add I2C NFC device node and LDO voting for yupik Device node changes required on yupik describing the GPIO configuration for Nfc controller chip. Modified corresponding Nfc device node for ATP, MTP & QRD platforms. Add device node properties to support NFC LDO voting. Change-Id: Ic41b05505db6970be002578255c21242f75fdbc4 --- qcom/yupik-atp.dtsi | 24 +++++++++++++++++ qcom/yupik-idp.dtsi | 24 +++++++++++++++++ qcom/yupik-pinctrl.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++ qcom/yupik-qrd.dtsi | 24 +++++++++++++++++ 4 files changed, 132 insertions(+) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index bcf6f5d1242d..f7d965e7acb1 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -23,6 +23,30 @@ }; }; +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 41 0x00>; + qcom,sn-ven = <&tlmm 38 0x00>; + qcom,sn-firm = <&tlmm 40 0x00>; + qcom,sn-clkreq = <&tlmm 39 0x00>; + qcom,sn-vdd-1p8-supply = <&L18B>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <41 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &pmk8350_vadc { pm8350b_ref_gnd { reg = ; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index a58128b89e96..90bcefa27cd0 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -24,6 +24,30 @@ }; }; +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 41 0x00>; + qcom,sn-ven = <&tlmm 38 0x00>; + qcom,sn-firm = <&tlmm 40 0x00>; + qcom,sn-clkreq = <&tlmm 39 0x00>; + qcom,sn-vdd-1p8-supply = <&L18B>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <41 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &pmk8350_vadc { pm7325b_ref_gnd { reg = ; diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 23c867f78890..fbfee95af1cc 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -670,6 +670,66 @@ }; }; + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 41: NFC Read Interrupt */ + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 41: NFC Read Interrupt */ + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* 38: Enable, 40: Firmware, 39: CLOCK */ + pins = "gpio38", "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio40", "gpio39"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + /* 38: Enable, 40: Firmware, 39: CLOCK */ + pins = "gpio38", "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio40", "gpio39"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + qupv3_se9_spi_pins: qupv3_se9_spi_pins { qupv3_se9_spi_active: qupv3_se9_spi_active { mux { diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index e3c97e8cdd7e..d6283b2c1863 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -25,6 +25,30 @@ }; }; +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 41 0x00>; + qcom,sn-ven = <&tlmm 38 0x00>; + qcom,sn-firm = <&tlmm 40 0x00>; + qcom,sn-clkreq = <&tlmm 39 0x00>; + qcom,sn-vdd-1p8-supply = <&L18B>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <41 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &pmk8350_vadc { pm8350b_ref_gnd { reg = ; From 929a7fd7db4752d6b031798443797d513d38b359 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Mon, 28 Dec 2020 17:26:25 +0800 Subject: [PATCH 0613/1809] ARM: dts: msm: Add scm dt nodes for sdxnightjar Add scm and scm pas device tree nodes for sdxnightjar target. These are required for pil image authentication. Change-Id: I066ca55d37aea8e248f4df88bba363a472bebabe --- qcom/sdxnightjar.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8f86692b9b3a..caa3f6076413 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -51,6 +51,13 @@ aliases { }; + firmware: firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + cpus { #size-cells = <0>; #address-cells = <1>; @@ -371,6 +378,11 @@ qcom,rmnet-ipa-ssr; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>; + }; + blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; @@ -445,6 +457,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@0x1937000 { + compatible = "syscon"; + reg = <0x1937000 0x21000>; + }; + apcs_glb: mailbox@0xb011008 { compatible = "qcom,sdxnightjar-apcs-gcc"; reg = <0xb011008 0x4>; From e598c121e3b9b6cdb43c41f28d16a39d8fec40bd Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Tue, 5 Jan 2021 21:35:45 +0530 Subject: [PATCH 0614/1809] ARM: dts: msm: Adding CoreTech sa8195 DT Changes to Mainline 5.4 Changes Included:- 1.) PCIE:- 3315638 2.) USB:- 3303659 3.) BUSES:- 3265704 4.) STORAGE:- 3306109. Change-Id: I6f206b8722cb046d45cc90ca76f72b72b34ab727 --- qcom/sa8195-qupv3.dtsi | 832 +++++++++++++++++++++ qcom/sa8195-ssc-qupv3.dtsi | 109 +++ qcom/sa8195-usb.dtsi | 203 ++++++ qcom/sa8195p-adp-common.dtsi | 24 +- qcom/sa8195p-pcie.dtsi | 1326 ++++++++++++++++++++++++++++++++++ qcom/sa8195p.dtsi | 14 + qcom/sdmshrike-pinctrl.dtsi | 76 +- qcom/sdmshrike.dtsi | 69 +- 8 files changed, 2591 insertions(+), 62 deletions(-) create mode 100644 qcom/sa8195-qupv3.dtsi create mode 100644 qcom/sa8195-ssc-qupv3.dtsi create mode 100644 qcom/sa8195-usb.dtsi create mode 100644 qcom/sa8195p-pcie.dtsi diff --git a/qcom/sa8195-qupv3.dtsi b/qcom/sa8195-qupv3.dtsi new file mode 100644 index 000000000000..6cf8da2377cf --- /dev/null +++ b/qcom/sa8195-qupv3.dtsi @@ -0,0 +1,832 @@ +#include + +&soc { + /* QUPv3 West Instances + * West 0 : SE 0 + * West 1 : SE 1 + * West 2 : SE 2 + * West 3 : SE 3 + * West 4 : SE 4 + * West 5 : SE 5 + * West 6 : SE 6 + * West 7 : SE 7 + * + * QUPv3 East0 and East1 Instances + * East1 0 : SE 8 + * East1 1 : SE 9 + * East1 2 : SE 10 + * East1 3 : SE 11 + * East1 4 : SE 12 + * East1 5 : SE 16 + * East1 0 : SE 17 + * East0 1 : SE 18 + * East0 2 : SE 19 + * East0 3 : SE 13 + * East0 4 : SE 14 + * East0 5 : SE 15 + */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x4c3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3 East1 Instances */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x603 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* 4-wire UART */ + qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>, + <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 46 0>; + qcom,wrapper-core = <&qupv3_2>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_active>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* QUPv3 East Instances */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xcc0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x7a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* I2C */ + qupv3_se13_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se14_i2c: i2c@0xc90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@0xc94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@0xc80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@0xc84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@0xc88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se13_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + +}; diff --git a/qcom/sa8195-ssc-qupv3.dtsi b/qcom/sa8195-ssc-qupv3.dtsi new file mode 100644 index 000000000000..cf0506dd1c30 --- /dev/null +++ b/qcom/sa8195-ssc-qupv3.dtsi @@ -0,0 +1,109 @@ +#include + +&soc { + /* QUPv3 SSC Instance */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x26c0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x4e3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + status = "disabled"; + }; + + /* I2C*/ + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE0_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-usb.dtsi b/qcom/sa8195-usb.dtsi new file mode 100644 index 000000000000..72f24f8fb7cc --- /dev/null +++ b/qcom/sa8195-usb.dtsi @@ -0,0 +1,203 @@ +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + qcom,ignore-wakeup-src-in-hostmode; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; +}; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 195d8d5a96dc..40b33a95405f 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1,27 @@ #include -&qupv3_id_1 { +&qupv3_3 { + status = "ok"; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8195_1_l10>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8195_1_l2>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; + status = "ok"; }; diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi new file mode 100644 index 000000000000..e02c8da3cc37 --- /dev/null +++ b/qcom/sa8195p-pcie.dtsi @@ -0,0 +1,1326 @@ +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + dma-coherent; + qcom,bw-scale = ; /* Gen3 */ + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1: qcom,pcie@1c10000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c10000 0x3000>, + <0x01c16000 0x2000>, + <0x68000000 0xf1d>, + <0x68000f20 0xa8>, + <0x68001000 0x1000>, + <0x68100000 0x100000>, + <0x68200000 0x100000>, + <0x68300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 175 0>; + wake-gpio = <&tlmm 177 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <2113>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1c80>; + + dma-coherent; + qcom,bw-scale = ; /* Gen3 */ + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x200 &apps_smmu 0x1c82 0x1>, + <0x300 &apps_smmu 0x1c83 0x1>, + <0x400 &apps_smmu 0x1c84 0x1>, + <0x500 &apps_smmu 0x1c85 0x1>, + <0x600 &apps_smmu 0x1c86 0x1>, + <0x700 &apps_smmu 0x1c87 0x1>, + <0x800 &apps_smmu 0x1c88 0x1>, + <0x900 &apps_smmu 0x1c89 0x1>, + <0xa00 &apps_smmu 0x1c8a 0x1>, + <0xb00 &apps_smmu 0x1c8b 0x1>, + <0xc00 &apps_smmu 0x1c8c 0x1>, + <0xd00 &apps_smmu 0x1c8d 0x1>, + <0xe00 &apps_smmu 0x1c8e 0x1>, + <0xf00 &apps_smmu 0x1c8f 0x1>; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + pcie_rc1: pcie_rc1 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie2: qcom,pcie@1c18000 { + compatible = "qcom,pci-msm"; + cell-index = <2>; + + reg = <0x1c18000 0x3000>, + <0x01c1c000 0x2000>, + <0x70000000 0xf1d>, + <0x70000f20 0xa8>, + <0x70001000 0x1000>, + <0x70100000 0x100000>, + <0x70200000 0x100000>, + <0x70300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x70200000 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x70300000 0x0 0x3d00000>; + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_clkreq_default + &pcie2_perst_default + &pcie2_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_2_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie2_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <2>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d00>; + + dma-coherent; + qcom,bw-scale = ; /* Gen3 */ + + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>, + <0x200 &apps_smmu 0x1d02 0x1>, + <0x300 &apps_smmu 0x1d03 0x1>, + <0x400 &apps_smmu 0x1d04 0x1>, + <0x500 &apps_smmu 0x1d05 0x1>, + <0x600 &apps_smmu 0x1d06 0x1>, + <0x700 &apps_smmu 0x1d07 0x1>, + <0x800 &apps_smmu 0x1d08 0x1>, + <0x900 &apps_smmu 0x1d09 0x1>, + <0xa00 &apps_smmu 0x1d0a 0x1>, + <0xb00 &apps_smmu 0x1d0b 0x1>, + <0xc00 &apps_smmu 0x1d0c 0x1>, + <0xd00 &apps_smmu 0x1d0d 0x1>, + <0xe00 &apps_smmu 0x1d0e 0x1>, + <0xf00 &apps_smmu 0x1d0f 0x1>; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", + "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk", + "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk", + "pcie_2_ldo", "pcie_2_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_2_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + + reset-names = "pcie_2_core_reset", + "pcie_2_phy_reset"; + + pcie_rc2: pcie_rc2 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie2_msi: qcom,pcie2_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie3: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <3>; + + reg = <0x1c08000 0x3000>, + <0x1c0c000 0x4000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie3>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0044 0x1c 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x029c 0x12 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x0684 0x35 0x0 + 0x063c 0x11 0x0 + 0x069c 0x12 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x2a40 0x03 0x0 + 0x2010 0x00 0x0 + 0x201c 0x31 0x0 + 0x2020 0x01 0x0 + 0x2024 0xde 0x0 + 0x2028 0x07 0x0 + 0x2030 0x4c 0x0 + 0x2034 0x06 0x0 + 0x2048 0x90 0x0 + 0x2044 0x1c 0x0 + 0x2058 0x0f 0x0 + 0x2074 0x06 0x0 + 0x2078 0x06 0x0 + 0x207c 0x16 0x0 + 0x2080 0x16 0x0 + 0x2084 0x36 0x0 + 0x2088 0x36 0x0 + 0x2094 0x08 0x0 + 0x20a4 0x42 0x0 + 0x20ac 0x0a 0x0 + 0x20b0 0x1a 0x0 + 0x20b4 0x14 0x0 + 0x20b8 0x34 0x0 + 0x20bc 0x82 0x0 + 0x20c4 0x68 0x0 + 0x20cc 0x55 0x0 + 0x20d0 0x55 0x0 + 0x20d4 0x03 0x0 + 0x20d8 0xab 0x0 + 0x20dc 0xaa 0x0 + 0x20e0 0x02 0x0 + 0x210c 0x02 0x0 + 0x2110 0x24 0x0 + 0x2118 0xb4 0x0 + 0x211c 0x03 0x0 + 0x2154 0x34 0x0 + 0x2158 0x01 0x0 + 0x216c 0x08 0x0 + 0x21ac 0xb9 0x0 + 0x21b0 0x1e 0x0 + 0x21b4 0x94 0x0 + 0x21b8 0x18 0x0 + 0x21bc 0x11 0x0 + 0x2284 0x35 0x0 + 0x223c 0x11 0x0 + 0x229c 0x12 0x0 + 0x2408 0x0c 0x0 + 0x2414 0x03 0x0 + 0x2434 0x7f 0x0 + 0x2444 0x70 0x0 + 0x2460 0x30 0x0 + 0x2464 0x00 0x0 + 0x24d4 0x54 0x0 + 0x24d8 0x07 0x0 + 0x24dc 0x0d 0x0 + 0x24e8 0x00 0x0 + 0x24ec 0x0e 0x0 + 0x24f0 0x4a 0x0 + 0x24f4 0x0f 0x0 + 0x24f8 0xc0 0x0 + 0x24fc 0x00 0x0 + 0x2510 0x17 0x0 + 0x2518 0x1c 0x0 + 0x251c 0x03 0x0 + 0x2524 0x1e 0x0 + 0x2570 0xff 0x0 + 0x2574 0xff 0x0 + 0x2578 0xff 0x0 + 0x257c 0x7f 0x0 + 0x2580 0x66 0x0 + 0x2584 0x24 0x0 + 0x2588 0xe4 0x0 + 0x258c 0xec 0x0 + 0x2590 0x3b 0x0 + 0x2594 0x36 0x0 + 0x2598 0xd4 0x0 + 0x259c 0x54 0x0 + 0x25a0 0xdb 0x0 + 0x25a4 0x3b 0x0 + 0x25a8 0x31 0x0 + 0x25bc 0x0c 0x0 + 0x2684 0x35 0x0 + 0x263c 0x11 0x0 + 0x269c 0x12 0x0 + 0x2808 0x0c 0x0 + 0x2814 0x03 0x0 + 0x2834 0x7f 0x0 + 0x2844 0x70 0x0 + 0x2860 0x30 0x0 + 0x2864 0x00 0x0 + 0x28d4 0x54 0x0 + 0x28d8 0x07 0x0 + 0x28dc 0x0d 0x0 + 0x28e8 0x00 0x0 + 0x28ec 0x0e 0x0 + 0x28f0 0x4a 0x0 + 0x28f4 0x0f 0x0 + 0x28f8 0xc0 0x0 + 0x28fc 0x00 0x0 + 0x2910 0x17 0x0 + 0x2918 0x1c 0x0 + 0x291c 0x03 0x0 + 0x2924 0x1e 0x0 + 0x2970 0xff 0x0 + 0x2974 0xff 0x0 + 0x2978 0xff 0x0 + 0x297c 0x7f 0x0 + 0x2980 0x66 0x0 + 0x2984 0x24 0x0 + 0x2988 0xe4 0x0 + 0x298c 0xec 0x0 + 0x2990 0x3b 0x0 + 0x2994 0x36 0x0 + 0x2998 0xd4 0x0 + 0x299c 0x54 0x0 + 0x29a0 0xdb 0x0 + 0x29a4 0x3b 0x0 + 0x29a8 0x31 0x0 + 0x29bc 0x0c 0x0 + 0x2adc 0x05 0x0 + 0x2b88 0x88 0x0 + 0x2b98 0x0b 0x0 + 0x2ba4 0x01 0x0 + 0x2bec 0x01 0x0 + 0x2e0c 0x0d 0x0 + 0x2e14 0x07 0x0 + 0x2e1c 0xc1 0x0 + 0x2e40 0x01 0x0 + 0x2e48 0x01 0x0 + 0x2e90 0x00 0x0 + 0x2ebc 0x00 0x0 + 0x2ee0 0x58 0x0 + 0x2eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_clkreq_default + &pcie3_perst_default + &pcie3_wake_default>; + + perst-gpio = <&tlmm 178 0>; + wake-gpio = <&tlmm 56 0>; + + gdsc-vdd-supply = <&pcie_3_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie3_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <3>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + dma-coherent; + qcom,bw-scale = ; /* Gen3 */ + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_3_pipe_clk", "pcie_3_ref_clk_src", + "pcie_3_aux_clk", "pcie_3_cfg_ahb_clk", + "pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk", + "pcie_3_ldo", "pcie_3_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_3_BCR>, + <&gcc GCC_PCIE_3_PHY_BCR>; + + reset-names = "pcie_3_core_reset", + "pcie_3_phy_reset"; + + pcie_rc3: pcie_rc3 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie3_msi: qcom,pcie3_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index a4157c692c36..dfa2d0d903ce 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -1,5 +1,6 @@ #include "sdmshrike-v2.dtsi" #include "sa8195-pmic.dtsi" +#include "sa8195p-pcie.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P"; @@ -41,3 +42,16 @@ status= "ok"; }; + +&usb2_phy0 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; + + +&usb2_phy1 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index c5e4ae02bc2f..56599e3baeed 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -2645,77 +2645,55 @@ }; }; - sdc2_clk_on: sdc2_clk_on { - config { + sdc2_on: sdc2_on { + clk { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + + sd-cd { + pins = "gpio96"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; }; - sdc2_clk_off: sdc2_clk_off { - config { + sdc2_off: sdc2_off { + clk { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { + cmd { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { + data { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_cd_on: cd_on { - mux { - pins = "gpio96"; /* sdcard_det */ - function = "gpio"; - }; - - config { + sd-cd { pins = "gpio96"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - sdc2_cd_off: cd_off { - mux { - pins = "gpio96"; - function = "gpio"; - }; - - config { - pins = "gpio96"; - drive-strength = <2>; - bias-disable; + bias-disable; /* pull up */ + drive-strength = <2>; /* 2 MA */ }; }; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index bff586f63aeb..006a1d4bb2a2 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -28,8 +28,9 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { - serial0 = &uart2; ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + serial0 = &qupv3_se12_2uart; + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ }; cpus { @@ -1409,19 +1410,60 @@ }; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x00ac0000 0x6000>; - ranges; - #address-cells = <2>; - #size-cells = <2>; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>,<100000 100000>, + /* 50 MB/s */ + <130718 200000>,<100000 100000>, + /* 100 MB/s */ + <261438 200000>,<130000 130000>, + /* 200 MB/s */ + <261438 400000>,<300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 25000000 50000000 + 100000000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + status = "disabled"; - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - interrupts = ; - status = "ok"; + qos0 { + mask = <0x0f>; + vote = <70>; + }; + + qos1 { + mask = <0xf0>; + vote = <70>; }; }; @@ -1435,6 +1477,9 @@ #include "msm-arm-smmu-sdmshrike.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sdmshrike-ion.dtsi" +#include "sa8195-qupv3.dtsi" +#include "sa8195-ssc-qupv3.dtsi" +#include "sa8195-usb.dtsi" &emac_gdsc { status = "ok"; From 7c73ddd1756aea2881b480fd1bcf6de58a4bc6c8 Mon Sep 17 00:00:00 2001 From: Ajit Kumar Date: Thu, 7 Jan 2021 15:12:01 +0530 Subject: [PATCH 0615/1809] bindings: Add device-tree bindings for slatecom SPI driver Add device-tree bindings documentation describing the properties for the slatecom SPI driver. Change-Id: Id6f5ad7f0bc30600f77eaa1b4246e5a47135f43f --- bindings/soc/qcom/qcom,slatecom_spi.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slatecom_spi.txt diff --git a/bindings/soc/qcom/qcom,slatecom_spi.txt b/bindings/soc/qcom/qcom,slatecom_spi.txt new file mode 100644 index 000000000000..c454151a1560 --- /dev/null +++ b/bindings/soc/qcom/qcom,slatecom_spi.txt @@ -0,0 +1,22 @@ +* Slate Coprocessor Communication Driver + +slatecom_spi driver provides a set of apis to perform +register, fifo, ahb read and write operations with slate +over spi interface. It also reads slate status and +sends events to the registered clients. + +Required properties: +- compatible: Must be "qcom,slate-spi" + +Optional properties: +- qcom,irq-gpio: IRQ used by the slate to inturrupt MSM. + +Example: + qcom,slate-spi { + compatible = "qcom,slate-spi"; + compatible = "qcom,slate-spi"; + interrupt-parent = <&tlmm>; + /* IRQ from slate */ + qcom,irq-gpio = <&tlmm 104 1>; + }; + From 5e41344a669d75c9ed71ffd2f50a0928a7b365a0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 7 Jan 2021 12:15:03 +0530 Subject: [PATCH 0616/1809] ARM: dts: msm: Mark GCC PCIE clocks as protected in YUPIK GCC PCIE clocks does not need to be controlled from HLOS in YUPIK, hence mark them as protected and remove support for PCIE GDSC's. Change-Id: I6111c9b37d1a90f4552560334fb5e963778b2921 --- qcom/yupik-rumi.dtsi | 2 -- qcom/yupik.dtsi | 29 +++++++++++++++-------------- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 2103affa18e3..a1b41edd11c9 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -169,8 +169,6 @@ &gcc { clocks = <&bi_tcxo>, <&sleep_clk>, - <&pcie_0_pipe_clk>, - <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 956f177295b5..1952cc44244d 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -900,14 +900,25 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <&pcie_0_pipe_clk>, - <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + + protected-clocks = , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -2754,16 +2765,6 @@ #include "yupik-regulators.dtsi" #include "yupik-thermal.dtsi" -&gcc_pcie_0_gdsc { - qcom,support-hw-trigger; - status = "ok"; -}; - -&gcc_pcie_1_gdsc { - qcom,support-hw-trigger; - status = "ok"; -}; - &gcc_ufs_phy_gdsc { qcom,support-hw-trigger; status = "ok"; From 809a8cfb9dcace881c39529e7865b7f14667cd56 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Fri, 8 Jan 2021 15:36:06 +0530 Subject: [PATCH 0617/1809] ARM: dts: msm: update apps smmu interrupt list It has been observed that multiple global combine fault is reported along with S1 fault. example: [<0000000023afa98c>] irq_default_primary_handler threaded [<000000002951795b>] arm_smmu_global_fault Disabling IRQ #55 arm-smmu c600000.apps-smmu: FAR = 0x0000000000000000 arm-smmu c600000.apps-smmu: PAR = 0x0000000000000000 arm-smmu c600000.apps-smmu: FSR = 0x40000402 [TF W SS ] arm-smmu c600000.apps-smmu: TTBR0 = 0x0000000000000000 arm-smmu c600000.apps-smmu: TTBR1 = 0x0000000000000000 arm-smmu c600000.apps-smmu: SCTLR = 0x00c000e7 ACTLR = 0x00000001 arm-smmu c600000.apps-smmu: CBAR = 0x0001f300 arm-smmu c600000.apps-smmu: MAIR0 = 0xf404ff44 MAIR1 = 0x000000e4 Fault count: IRQ 55 100001 arm-smmu global fault Remove unnecessary global interrupt from EL1 apps smmu interrupt list. Change-Id: Ifda67dc5aee92d09a48cdf31d5e22cc2e234ed7a --- qcom/msm-arm-smmu-holi.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 0b7fb0427195..b5011e9e547b 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -45,12 +45,11 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; - #global-interrupts = <2>; + #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; ranges; interrupts = , - , , , , From fc340212acca8eb02ccdb123544fba8abf10a140 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 8 Jan 2021 10:42:18 +0530 Subject: [PATCH 0618/1809] ARM: dts: msm: Add iommu and h/w reset support for yupik Add iommu devicetree property for eMMC and SD card. Also add h/w reset support for eMMC. Change-Id: I22e5a8d23f3edfc2c251cced8aced6f727a0b299 --- qcom/yupik.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 956f177295b5..8ff4ae741552 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1910,6 +1910,10 @@ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", "cqhci_ice_hwkm"; + iommus = <&apps_smmu 0xc0 0x0>; + dma-coherent; + qcom,iommu-dma = "bypass"; + interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -1929,6 +1933,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + bus-width = <8>; non-removable; supports-cqe; @@ -1936,6 +1942,10 @@ qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { @@ -1954,6 +1964,10 @@ reg = <0x08804000 0x1000>; reg-names = "hc_mem"; + iommus = <&apps_smmu 0x100 0x0>; + dma-coherent; + qcom,iommu-dma = "bypass"; + interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; From 64d7119b9a85ed0f564dcf59b7d51226135b5574 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Fri, 18 Dec 2020 21:14:55 +0530 Subject: [PATCH 0619/1809] ARM: dts: msm: Add pin configuration for USB3 PHY portselect on Yupik TLMM pin 81 is used to indicate to the USB3/DP Combo PHY the orientation that which the PMIC detected a USB-C connection. Select this pinctrl from the usb_qmp_dp_phy device and ensure it is selecting the "usb_phy" pin function. Change-Id: I169bf35434aa2667338089a71ad8a5f90f92d62b --- qcom/yupik-pinctrl.dtsi | 15 +++++++++++++++ qcom/yupik-usb.dtsi | 3 +++ 2 files changed, 18 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index fadbe85ab0ad..a5b78841832c 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -2793,5 +2793,20 @@ }; }; }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio140"; + function = "usb_phy"; + }; + + config { + pins = "gpio140"; + bias-disable; + drive-strength = <2>; + }; + }; + }; }; }; diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 137e2b4bcd91..67b822bf441d 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -131,6 +131,9 @@ <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = Date: Wed, 30 Dec 2020 10:17:11 +0530 Subject: [PATCH 0620/1809] ARM: dts: msm: Add audio overlay for yupik Add audio overlay for yupik idp and atp platforms. Change-Id: Ia2e01cdb68a37f6ba33cc20b1856b1e22b251151 --- qcom/yupik-atp.dtsi | 111 ++++++++++++++++++++++++++++++++++ qcom/yupik-audio-overlay.dtsi | 5 +- qcom/yupik-idp.dtsi | 1 + qcom/yupik-qrd.dtsi | 2 +- 4 files changed, 115 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 1d6b5e173e81..f5f6a58d70e7 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -2,6 +2,7 @@ #include #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" +#include "yupik-audio-overlay.dtsi" &soc { gpio_keys { @@ -222,3 +223,113 @@ status = "ok"; }; + +&wsa883x_0221 { + status = "disabled"; +}; + +&swr2 { + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; +}; + +&wcd938x_rx_slave { + status = "okay"; +}; + +&wcd938x_tx_slave { + status = "okay"; +}; + +&wcd938x_codec { + status = "okay"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&swr_haptics { + status = "okay"; +}; + +&yupik_snd { + qcom,model = "lahaina-yupikqrd-snd-card"; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS1", + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS3", + "TX DMIC4", "Digital Mic4", + "Digital Mic4", "MIC BIAS4", + "TX DMIC5", "Digital Mic5", + "Digital Mic5", "MIC BIAS4", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS4", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC4", "VA MIC BIAS3", + "VA DMIC5", "VA MIC BIAS4"; + qcom,swr-dmic-max-devs = <0>; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&swr_haptics>, + <&wsa883x_0222>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "swr-haptics", + "wsa-codec2"; + qcom,wsa-max-devs = <1>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index 19050be88416..54f9aa6379d1 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -121,7 +121,6 @@ status = "disabled"; compatible = "qcom,pm8350b-swr-haptics"; reg = <0x01 0xf0170220>; - swr-slave-supply = <&hap_swr_slave_reg>; qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>; }; @@ -367,10 +366,10 @@ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; asoc-codec = <&stub_codec>, <&bolero>, - <&wcd937x_codec>, <&swr_haptics>, + <&wcd937x_codec>, <&wsa883x_0221>, <&wsa883x_0222>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", - "wcd937x_codec", "swr-haptics", + "wcd937x_codec", "wsa-codec1", "wsa-codec2"; qcom,wsa-max-devs = <2>; qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index b3ee0ab1052e..7d8e855ee0b2 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -3,6 +3,7 @@ #include #include "yupik-pmic-overlay.dtsi" #include "pm7325b.dtsi" +#include "yupik-audio-overlay.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 047a505724fd..b2423ab243d6 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -317,7 +317,7 @@ swr-slave-supply = <&hap_swr_slave_reg>; }; -&tx_macro { +&swr2 { qcom,swr-phy-dev-addr = <0x0D 0x01170223>, <0x08 0x58350223>, <0x08 0x58350222>, From 98ba6ad3ba0eb1ad5602ed716d2bddd561dee21d Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 4 Jan 2021 14:24:39 +0530 Subject: [PATCH 0621/1809] ARM: dts: qcom: Enable haptics node for yupik atp Enable haptics node for yupik atp. Change-Id: Icce086b7e35da4e532f091c834a06e8eb5f304a7 --- qcom/yupik-atp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index f5f6a58d70e7..a46e5486d8f1 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -262,6 +262,7 @@ &swr_haptics { status = "okay"; + swr-slave-supply = <&hap_swr_slave_reg>; }; &yupik_snd { From 0e026ff26e2ba1f76bc80f4e004a83248baa0777 Mon Sep 17 00:00:00 2001 From: Sandeep Neerudu Date: Tue, 5 Jan 2021 12:51:46 +0530 Subject: [PATCH 0622/1809] ARM: dts: msm: Add smp2p sleepstate node for yupik Add device node for the smp2p sleepstate entry and the device node for the smp2p sleep driver to notify dsps of apps power state changes. Change-Id: I6af351908939ba90e196e25d3515cb5b02df7cdf --- qcom/yupik.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..ff3dfd7a3cdf 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2195,6 +2195,25 @@ interrupt-controller; #interrupt-cells = <2>; }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; }; qcom,smp2p-nsp { From 295913cbd840725123e8b54bb3735af4a8911a41 Mon Sep 17 00:00:00 2001 From: Ajit Kumar Date: Sat, 9 Jan 2021 15:08:08 +0530 Subject: [PATCH 0623/1809] bindings: Add device-tree bindings for slatecom interface driver Add device-tree bindings documentation describing the properties for the slatecom interface driver. Change-Id: I0851e7e232067dc625142a5fd7de85190eedbd49 --- bindings/soc/qcom/qcom,slatecom_interface.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slatecom_interface.txt diff --git a/bindings/soc/qcom/qcom,slatecom_interface.txt b/bindings/soc/qcom/qcom,slatecom_interface.txt new file mode 100644 index 000000000000..2731a7957510 --- /dev/null +++ b/bindings/soc/qcom/qcom,slatecom_interface.txt @@ -0,0 +1,16 @@ +* Slatecom Interface Driver + +slatecom_interface driver creates a slate_com_dev device +node for user space communication. Single user space +client can open device node for communication from hardware. +Hardware will provide access to read/write registers or AHB +memory in the device. + +Required properties: +- compatible: Must be "qcom,slate-daemon" + +Example: + qcom,slate-daemon { + compatible = "qcom,slate-daemon"; + }; + From 36a0f1c95da5590b16155ffc42c2ae70c412ce40 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Mon, 21 Dec 2020 10:31:46 +0530 Subject: [PATCH 0624/1809] ARM: dts: msm: Remove pmic dependency on Yupik Remove the dependency on adsp charger detection on Yupik. Please note that USB HOST MODE would not be working with this patch included. Change-Id: I3679b4a2ba5e50a7eacbcce6a8067d57a0ed7958 --- qcom/yupik-usb.dtsi | 10 +--------- qcom/yupik.dtsi | 5 ----- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 67b822bf441d..474485e8348c 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -49,8 +49,6 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - usb-role-switch; - extcon = <&eud>; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -75,13 +73,7 @@ snps,ssp-u3-u0-quirk; tx-fifo-resize; maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - - port { - usb_port0: endpoint { - remote-endpoint = <&usb_port0_connector>; - }; + dr_mode = "peripheral"; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..1db8a4404438 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2072,11 +2072,6 @@ qcom,ucsi { compatible = "qcom,ucsi-glink"; - port { - usb_port0_connector: endpoint { - remote-endpoint = <&usb_port0>; - }; - }; }; altmode: qcom,altmode { From b77c2fed79eecc2e80c9563da91008c18b593b52 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 29 Dec 2020 13:07:17 +0530 Subject: [PATCH 0625/1809] ARM: dts: msm: Update DISPCC and debugcc clock nodes for YUPIK Update the display clock controller node to real from dummmy and add debug clock controller node for YUPIK. Change-Id: I2211792d6c26f7f234cc507129438e52106971f6 --- qcom/yupik-rumi.dtsi | 9 +++++++++ qcom/yupik.dtsi | 33 +++++++++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 83894d7154ca..5cc8fca9f758 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -191,3 +191,12 @@ clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>; status = "disabled"; }; + +&dispcc { + clocks = <&bi_tcxo>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_AHB_CLK>; +}; + +&debugcc { + clocks = <&bi_tcxo>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..22c0fff9524c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -951,8 +951,13 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,yupik-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk","cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -983,6 +988,30 @@ #reset-cells = <1>; }; + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90ba000 { + compatible = "syscon"; + reg = <0x90ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,yupik-debugcc"; + qcom,gcc = <&gcc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,videocc = <&videocc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw-epss"; reg = <0x18591000 0x1000>, <0x18592000 0x1000>, From 67f36f02fd93eb162655c4439f60c752a3cd480a Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Sun, 10 Jan 2021 10:03:44 +0530 Subject: [PATCH 0626/1809] ARM: dts: msm: Correct soc id for monaco Correct soc id, timer frequency and linux-boot reserved memory for monaco. Change-Id: I7196830c84abe97482fceb7029975a68752546db --- qcom/monaco-rumi.dts | 2 +- qcom/monaco-rumi.dtsi | 4 ++-- qcom/monaco.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/monaco-rumi.dts b/qcom/monaco-rumi.dts index cb90f9641935..0d778ef7b4c8 100644 --- a/qcom/monaco-rumi.dts +++ b/qcom/monaco-rumi.dts @@ -1,5 +1,5 @@ /dts-v1/; -/memreserve/ 0x90000000 0x00000100; +/memreserve/ 0x90f00000 0x00000100; #include "monaco.dtsi" #include "monaco-rumi.dtsi" diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index d6ea70d56500..aa3e9f57a73b 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -1,10 +1,10 @@ &soc { timer { - clock-frequency = <500000>; + clock-frequency = <5000000>; }; timer@f120000 { - clock-frequency = <500000>; + clock-frequency = <5000000>; }; wdog: qcom,wdt@f017000 { diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 0e42eb96e08f..61d0400287fc 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Monaco"; compatible = "qcom,monaco"; - qcom,msm-id = <459 0x10000>; + qcom,msm-id = <486 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; From 157c2c7a82893d927d054c5f8f66d27b1a018bd7 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 7 Jan 2021 18:29:02 +0530 Subject: [PATCH 0627/1809] dt-bindings: backlight: Add support for PM7325B WLED Add compatible string for PM7325B WLED device. Change-Id: I5d8a17bb4ce6c9be6a7aed38c82aef0116ede260 --- bindings/leds/backlight/qcom-spmi-wled.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/leds/backlight/qcom-spmi-wled.txt b/bindings/leds/backlight/qcom-spmi-wled.txt index 5ef7ce36d223..884d4e4a90f4 100644 --- a/bindings/leds/backlight/qcom-spmi-wled.txt +++ b/bindings/leds/backlight/qcom-spmi-wled.txt @@ -12,6 +12,7 @@ platforms. The PMIC is connected to the host processor via SPMI bus. "qcom,pm8150l-spmi-wled", "qcom,pm6150l-spmi-wled" "qcom,pm660l-spmi-wled" + "qcom,pm7325b-spmi-wled" - reg Usage: required From 891a3a69a226bff985c46f05f567d60e45b04f86 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 29 Dec 2020 14:23:41 +0530 Subject: [PATCH 0628/1809] ARM: dts: msm: Add cpufreq-hw-debug node for Lahaina To enable EPSS debugging, add the debug node. Change-Id: I2ec72a269a92bf09724bfce416ad150cf3885a55 --- qcom/lahaina.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 45d3ecd39f62..25926f595614 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2480,6 +2480,14 @@ #freq-domain-cells = <2>; }; + qcom,cpufreq-hw-debug@18591000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x18591000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; + /* CAM_CC GDSCs */ cam_cc_bps_gdsc: qcom,gdsc@ad07004 { compatible = "qcom,gdsc"; From ce7da1d5850ec60367e655054ab1c016aaea852d Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Fri, 27 Nov 2020 18:11:18 +0530 Subject: [PATCH 0629/1809] ARM: dts: msm: Add GPU properties for yupik GPU Add required GPU properties for yupik to enable graphics driver functionality. Change-Id: I0c6bfc11e0f42ace235e220501cdd7ce7ed5666f --- qcom/yupik-gpu.dtsi | 284 ++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 285 insertions(+) create mode 100644 qcom/yupik-gpu.dtsi diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi new file mode 100644 index 000000000000..c60e37b1de6e --- /dev/null +++ b/qcom/yupik-gpu.dtsi @@ -0,0 +1,284 @@ +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a660_zap"; + memory-region = <&pil_gpu_micro_code_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { + compatible = "qcom,kgsl-3d0"; + status = "ok"; + + reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, + <0x3de0000 0x10000>, <0x3d8b000 0x2000>, + <0x06900000 0x80000>; + + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", + "isense_cntl", "qdss_gfx"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&aopcc QDSS_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "apb_pclk", + "gpu_cc_hlos1_vote_gpu_smmu", + "gpu_cc_cx_gmu", + "gpu_cc_hub_aon", + "gpu_cc_hub_cx_int"; + + qcom,chipid = <0x06030500>; + qcom,no-nap; + qcom,initial-pwrlevel = <6>; + + qcom,min-access-length = <32>; + qcom,ubwc-mode = <4>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* index=1, LOW_SVS */ + , /* index=2, LOW_SVS */ + , /* index=3, LOW_SVS */ + , /* index=4, SVS */ + , /* index=5, SVS */ + , /* index=6, SVS */ + , /* index=7, NOM */ + , /* index=8, NOM */ + , /* index=9, NOM */ + , /* index=10, TURBO */ + ; /* index=11, TURBO */ + + qcom,bus-table-ddr8 = + , /* index=0 */ + , /* index=1, LOW_SVS */ + , /* index=2, LOW_SVS */ + , /* index=3, LOW_SVS */ + , /* index=4, SVS */ + , /* index=5, SVS */ + , /* index=6, SVS */ + , /* index=7, SVS_L1 */ + , /* index=8, NOM */ + , /* index=9, TURBO_L1 */ + ; /* index=10, TURBO_L1 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <812000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x03da0000 0x20000>; + + vddcx-supply = <&gpu_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x400>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d69000 { + compatible = "qcom,gpu-gmu"; + + reg = <0x3d6a000 0x34000>, + <0xb290000 0x10000>; + + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + regulator-names = "vddcx", "vdd"; + + iommus = <&kgsl_smmu 0x5 0x400>; + qcom,iommu-dma = "disabled"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..57ffa840b559 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3581,3 +3581,4 @@ #include "yupik-audio.dtsi" #include "camera/yupik-camera.dtsi" #include "msm-rdbg.dtsi" +#include "yupik-gpu.dtsi" From 4f67dae21b3070615d9543411bc6ccbd19cc7e65 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Mon, 4 Jan 2021 10:35:36 +0530 Subject: [PATCH 0630/1809] ARM: dts: msm: Add platform dt changes for yupik for ufs Add platform dt changes for yupik for ufs. Change-Id: Ia6039ec53242a23d6341587b531b139129dd7bed --- qcom/yupik-atp.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-idp.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-qrd.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 17 +++++++++++++++-- 4 files changed, 135 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 1d6b5e173e81..43bdc8a955a5 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -23,6 +23,46 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97500>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2952000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + /* + * Vccq2 voltage level should be 1.8V but in case of yupik + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. + */ + vccq2-supply = <&L9B>; + vccq2-voltage-level = <1200000 1200000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + &pmk8350_vadc { pm8350b_ref_gnd { reg = ; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index b3ee0ab1052e..cf92f97a0fe1 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -24,6 +24,46 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97500>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2952000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + /* + * Vccq2 voltage level should be 1.8V but in case of yupik + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. + */ + vccq2-supply = <&L9B>; + vccq2-voltage-level = <1200000 1200000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + &pmk8350_vadc { pm7325b_ref_gnd { reg = ; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 047a505724fd..b31159bbca29 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -25,6 +25,46 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97500>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2952000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + /* + * Vccq2 voltage level should be 1.8V but in case of yupik + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. + */ + vccq2-supply = <&L9B>; + vccq2-voltage-level = <1200000 1200000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + &pmk8350_vadc { pm8350b_ref_gnd { reg = ; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..47383e6977df 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1149,6 +1149,10 @@ <0 0>, <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <26>; qcom,ufs-bus-bw,num-paths = <2>; @@ -1209,21 +1213,30 @@ resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "fastmap"; dma-coherent; rpm-level = <3>; + /* + * UFS2.2 is drawing 40mA current during APPS PC. + * Issue is seen only if PX10 is turned off and Vccq2 is ON. + * Since Vccq2 is always-on supply we can't turn it off, + * so don't turn off PX10, by updating spm_lvl to 3. + * In sleep state (spm-lvl=3) its drawing only .5mA. + */ spm-level = <3>; status = "disabled"; qos0 { mask = <0xf0>; - vote = <59>; + vote = <65>; }; qos1 { mask = <0x0f>; - vote = <65>; + vote = <59>; }; }; From 494e97f126714851577226b0f3c54853ed57beb8 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 07:55:09 +0530 Subject: [PATCH 0631/1809] ARM: dts: msm: Add lpass device node for PIL on SM8150 Add PIL device tree node to load firmware images of lpass on sm8150. Change-Id: I72f4b7c49c1168cf1f8e0fed8efb4ef79c0f4079 --- qcom/sm8150.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2846681eda10..c48220bb615e 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1728,6 +1728,50 @@ mbox-names = "mss-pil"; }; + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + qcom,pil-force-shutdown; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 0 162 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + pil_ssc: qcom,ssc@5c00000 { compatible = "qcom,pil-tz-generic"; reg = <0x5c00000 0x4000>; From 04896ee4ec2d9bb8adfb4ac73fbef8210223f0e8 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Mon, 11 Jan 2021 15:46:25 +0530 Subject: [PATCH 0632/1809] ARM: dts: msm: Update max bus vote range for Holi Existing max bus vote range corresponds to low DDR frequency. Now when video hardware is made to run at maximum clock and the max bus vote, DDR is still running at low clock whereas video hardware runs at max speed. Update the max bandwidth so as to keep DDR to next corner. CRs-Fixed: 2858305 Change-Id: Ia20bb6c9ae999bbc75aed627bd200b08fb592bde --- qcom/holi-vidc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-vidc.dtsi b/qcom/holi-vidc.dtsi index 5b3aa57de254..3789d98f43e0 100644 --- a/qcom/holi-vidc.dtsi +++ b/qcom/holi-vidc.dtsi @@ -36,7 +36,7 @@ &bimc SLAVE_EBI>; /* Bus BW range (low, high) for each bus */ qcom,bus-range-kbps = <1000 1000 - 1000 2128000>; + 1000 6500000>; /* MMUs */ non_secure_cb { From 897493c8f89306715589d0bded58ee28a70b7d14 Mon Sep 17 00:00:00 2001 From: Piyush Dhyani Date: Mon, 11 Jan 2021 04:16:54 +0530 Subject: [PATCH 0633/1809] ARM: dts: msm: Modify IPA DT entry for sdxnightjar target Currently incorrect DT entry leading to NULL pointer dereference. So modifying IPA DT entry. Change-Id: I0630b143a199cb0d4fbed285beba1ccb4773ade6 --- qcom/sdxnightjar.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 9b5af63ebdbd..81e7fd68835b 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -785,13 +785,13 @@ qcom,ipa-tz-unlock-reg = <0x4043583c 0x1000>; /* 32-bit reg addr and size */ /* smp2p gpio information */ - qcom,smp2pgpio_map_ipa_1_out { + qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; - qcom,smp2pgpio_map_ipa_1_in { + qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; From 2a831963fbd2664db396a5acae4111f7ab9d86a9 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 11 Jan 2021 15:21:48 +0530 Subject: [PATCH 0634/1809] ARM: dts: msm: Add support for diff yupik sku Add support for different sku for yupik based on different adsp. Change-Id: Ie4c8fa09b556c37cd39f934a90a11ac73e5277d2 --- qcom/yupik-audio-overlay.dtsi | 6 ++++++ qcom/yupik.dtsi | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index 36cb0ea52c19..bd8bf6cfddd2 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -473,3 +473,9 @@ }; }; +&adsp_loader { + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; + adsp-fw-names = "adsp2"; + adsp-fw-bit-values = <0x4>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 9d764ae43244..72989f094c03 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3293,6 +3293,11 @@ feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; + + adsp_variant: adsp_variant@6020 { + reg = <0x6022 0x1>; + bits = <2 4>; + }; }; qfprom_sys: qfprom@0 { From 8c3735ba4f9332ab31fd92b26f37c835629e3fbf Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 23 Dec 2020 17:26:06 +0530 Subject: [PATCH 0635/1809] ARM: dts: msm: Update kgsl smmu clock for scuba Update clock and vdd for KGSL smmu for scuba. Change-Id: I2aabba837f2d32b90fdc9dbd313b286335cd9966 --- qcom/msm-arm-smmu-scuba.dtsi | 9 +++++++++ qcom/scuba-iot-idp.dtsi | 1 + 2 files changed, 10 insertions(+) diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi index bb960362ef1a..5703e8c00578 100644 --- a/qcom/msm-arm-smmu-scuba.dtsi +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -12,6 +12,15 @@ qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; ranges; interrupts = , diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi index 91456469df2f..44a660fd6ad2 100644 --- a/qcom/scuba-iot-idp.dtsi +++ b/qcom/scuba-iot-idp.dtsi @@ -1,5 +1,6 @@ #include #include +#include "msm-arm-smmu-scuba.dtsi" #include "scuba-ion.dtsi" &soc { From b97920307196dc2c1c17e16eda49d7c19389693e Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Mon, 11 Jan 2021 17:19:10 +0530 Subject: [PATCH 0636/1809] ARM: dts: msm: Add UFS ICE HW controlled clock for yupik This change adds support for UFS ICE HW controlled clock for yupik platform. Change-Id: I72e22d95c26b869e503bcd353ae428451d5b1338 --- qcom/yupik.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 47383e6977df..f74984866ba8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1124,6 +1124,7 @@ "iface_clk", "core_clk_unipro", "core_clk_ice", + "core_clk_ice_hw_ctl", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", @@ -1134,6 +1135,7 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, @@ -1144,6 +1146,7 @@ <0 0>, <75000000 300000000>, <75000000 300000000>, + <75000000 300000000>, <0 0>, <0 0>, <0 0>, From a80bb7dcdc68dd2108fe7e2acb2e557e38cad540 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 21 Dec 2020 23:35:20 +0530 Subject: [PATCH 0637/1809] ARM: dts: msm: Add CPU thermal configuration for yupik Add CPU frequency, CPU isolation and CPU hotplug cooling device configuration. Add thermal emergency mitigation configuration to mitigate CPU at high temperatures for YUPIK. Change-Id: Iffeb48eb415aa19fb31bfd7c46b44aaee22ce27e --- qcom/yupik-thermal.dtsi | 517 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 516 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index eb26ba324b6d..a782db14875d 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -32,6 +32,102 @@ }; }; +&cpufreq_hw { + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + + qcom,cpu-voltage-cdev { + compatible = "qcom,cc-cooling-devices"; + apc1_cluster: qcom,apc1-cluster { + qcom,cpus = <&CPU4 &CPU7>; + #cooling-cells = <2>; + }; + }; +}; + &thermal_zones { aoss-0-usr { polling-delay-passive = <0>; @@ -572,5 +668,424 @@ }; }; }; -}; + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + thermal-governor = "step_wise"; + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + thermal-governor = "step_wise"; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + thermal-governor = "step_wise"; + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu10_cdev1 { + trip = <&cpu10_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu11_cdev1 { + trip = <&cpu11_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu12_cdev1 { + trip = <&cpu12_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + trips { + cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu13_cdev1 { + trip = <&cpu13_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + trips { + cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu14_cdev1 { + trip = <&cpu14_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + trips { + cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu15_cdev1 { + trip = <&cpu15_config>; + cooling-device = <&apc1_cluster THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + trips { + cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + trips { + cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; +}; From 38e3fe776a2d47267bd599f70de4a86291df4dea Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 8 Jan 2021 16:14:33 +0530 Subject: [PATCH 0638/1809] ARM: dts: msm: Add QMI sensor and cdev configuration for YUPIK Add the list of modem, cdsp QMI sensors, QMI cooling devices and userspace thermal config available for yupik. Change-Id: I4b4aba40cb285fe115c2ede100bddeb735c5403b --- qcom/yupik-thermal.dtsi | 136 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index a782db14875d..12aacca763fe 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -1,4 +1,5 @@ #include +#include "lahaina-thermal-modem.dtsi" &soc { tsens0:tsens@c222000 { @@ -30,6 +31,69 @@ "tsens-0C"; #thermal-sensor-cells = <1>; }; + + qmi-ts-sensors { + modem { + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_wtr0", + "modem_tsens", + "qfe_mmw0", + "qfe_mmw1", + "qfe_mmw2", + "qfe_mmw3", + "xo_therm", + "qfe_mmw_streamer0", + "qfe_mmw0_mod", + "qfe_mmw1_mod", + "qfe_mmw2_mod", + "qfe_mmw3_mod", + "qfe_ret_pa0", + "qfe_wtr_pa0", + "qfe_wtr_pa1", + "qfe_wtr_pa2", + "qfe_wtr_pa3", + "sys_therm1", + "modem_tsens1", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", + "msm_skin_therm"; + }; + }; +}; + +&qmi_tmd { + modem { + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; + #cooling-cells = <2>; + }; + + modem_wlan_bw: modem_wlan_bw { + qcom,qmi-dev-name = "wlan_bw"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; }; &cpufreq_hw { @@ -129,6 +193,24 @@ }; &thermal_zones { + /delete-node/ modem-sdr-mmw-usr; + /delete-node/ modem-ambient-usr; + + msm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MSM_SKIN)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -1088,4 +1170,58 @@ }; }; }; + + nspss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 3>; + trips { + nspss0_trip: nspss0-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&nspss0_trip>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem-pa-cdev { + trip = <&nspss0_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + nspss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 4>; + trips { + nspss1_trip: nspss1-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&nspss1_trip>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem-pa-cdev { + trip = <&nspss1_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; }; From 6790b4faf5efddad1a3a2e6bc6a427c7af03c594 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 11 Jan 2021 18:20:09 +0530 Subject: [PATCH 0639/1809] ARM: dts: msm: Add GPU thermal zone configuration for YUPIK Add thermal zones for all GPU sensors individually to achieve better thermal control. Enable polling delay to one of the thermal zone to monitor the TSENS hardware functionality. Change-Id: I4174ca21744a89ede0d2e7e157d34dcae3a45d53 --- qcom/yupik-thermal.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 2 +- 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 12aacca763fe..d6326e668327 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -192,6 +192,10 @@ }; }; +&msm_gpu { + #cooling-cells = <2>; +}; + &thermal_zones { /delete-node/ modem-sdr-mmw-usr; /delete-node/ modem-ambient-usr; @@ -1171,6 +1175,50 @@ }; }; + gpuss-0-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 1>; + trips { + gpuss0_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss0_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 2>; + trips { + gpuss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss1_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + nspss-0-step { polling-delay-passive = <0>; polling-delay = <0>; @@ -1191,6 +1239,12 @@ THERMAL_MAX_LIMIT>; }; + gpu_cdev { + trip = <&nspss0_trip>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + modem-pa-cdev { trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; @@ -1218,6 +1272,12 @@ THERMAL_MAX_LIMIT>; }; + gpu_cdev { + trip = <&nspss1_trip>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + modem-pa-cdev { trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 9c22f571b73d..197c26b268b5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3681,7 +3681,6 @@ #include "yupik-pm.dtsi" #include "ipcc-test-yupik.dtsi" #include "yupik-regulators.dtsi" -#include "yupik-thermal.dtsi" &gcc_ufs_phy_gdsc { qcom,support-hw-trigger; @@ -3813,3 +3812,4 @@ #include "camera/yupik-camera.dtsi" #include "msm-rdbg.dtsi" #include "yupik-gpu.dtsi" +#include "yupik-thermal.dtsi" From 00b93edbe8731bb1659784c7eb61f86c4f38ae78 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 28 Dec 2020 21:19:08 +0530 Subject: [PATCH 0640/1809] ARM: dts: msm: Add BCL and PMIC die temperature mitigation for yupik Add BCL configuration to monitor battery current, level violation and state of charge depletion configuration for YUPIK. Add PMIC die temperature mitigation for YUPIK. The mitigation will trigger at the first PMIC alarm at 95C. Change-Id: Ife55eac7de58b0450e782b1106ec73db463a4707 --- qcom/pm7325b.dtsi | 108 +++++++++++ qcom/yupik-atp.dtsi | 1 + qcom/yupik-idp.dtsi | 1 + qcom/yupik-pmic-overlay.dtsi | 6 + qcom/yupik-qrd.dtsi | 1 + qcom/yupik-thermal-overlay-qrd.dtsi | 282 ++++++++++++++++++++++++++++ qcom/yupik-thermal-overlay.dtsi | 282 ++++++++++++++++++++++++++++ 7 files changed, 681 insertions(+) create mode 100644 qcom/yupik-thermal-overlay-qrd.dtsi create mode 100644 qcom/yupik-thermal-overlay.dtsi diff --git a/qcom/pm7325b.dtsi b/qcom/pm7325b.dtsi index 0ca5f7732a39..199c1fe23be9 100644 --- a/qcom/pm7325b.dtsi +++ b/qcom/pm7325b.dtsi @@ -29,6 +29,24 @@ #interrupt-cells = <2>; }; + pm7325b_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x3 0x47 0x0 IRQ_TYPE_NONE>, + <0x3 0x47 0x1 IRQ_TYPE_NONE>, + <0x3 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + pm7250b_vib: qcom,vibrator@df00 { compatible = "qcom,qpnp-vibrator-ldo"; reg = <0xdf00>; @@ -65,4 +83,94 @@ }; }; }; + + pm7325b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <6000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7325b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <7500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 5>; + + trips { + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 6>; + + trips { + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 7>; + + trips { + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_soc>; + + trips { + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index ad548e49cc53..22b41f6b4b60 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -3,6 +3,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay-qrd.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 92d4c51d29d2..b68e009e7a6e 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -4,6 +4,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm7325b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index 6737ee49d3a2..5cded5632a57 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -165,6 +165,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 2eaa1cad5480..ff6886b8f7a3 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -4,6 +4,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay-qrd.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi new file mode 100644 index 000000000000..7c1faae42457 --- /dev/null +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -0,0 +1,282 @@ +#include + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350b-bcl-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350b_tz { + cooling-maps { + battery_cdev { + trip = <&pm8350b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325_tz { + cooling-maps { + pm7325_gpu { + trip = <&pm7325_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm7325_cpu1 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm7325_cpu2 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm7325_cpu3 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm7325_cpu4 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm7325_cpu5 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm7325_cpu6 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm7325_cpu7 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_gpu { + trip = <&pm8350c_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + pmr735a_pa { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_pa_fr1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw0 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw2 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw3 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi new file mode 100644 index 000000000000..1abb1a64ab03 --- /dev/null +++ b/qcom/yupik-thermal-overlay.dtsi @@ -0,0 +1,282 @@ +#include + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7325b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm7325b-bcl-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm7325b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325b_tz { + cooling-maps { + battery_cdev { + trip = <&pm7325b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325_tz { + cooling-maps { + pm7325_gpu { + trip = <&pm7325_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm7325_cpu1 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm7325_cpu2 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm7325_cpu3 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm7325_cpu4 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm7325_cpu5 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm7325_cpu6 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm7325_cpu7 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_gpu { + trip = <&pm8350c_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + pmr735a_pa { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_pa_fr1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw0 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw2 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw3 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; From 71e7410be5077dfbbecaa94b4e5d9d2d5760de89 Mon Sep 17 00:00:00 2001 From: Biao Long Date: Tue, 10 Nov 2020 15:14:53 +0800 Subject: [PATCH 0641/1809] ARM: dts: msm: Add devfreq-cpufreq for SDXNIGHTJAR target Add devfreq-cpufreq node. Add clock for msm-cpufreq. Change-Id: I88812e3fdfc782f76e5a2350c3d2b94d8289327c --- qcom/sdxnightjar.dtsi | 45 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 3e91d4b919c5..d506fa6310f7 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -4,6 +4,10 @@ #include #include #include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} / { model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; @@ -193,9 +197,8 @@ qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; - /*TODO: Fix the clock when tree is available*/ - clock-names = "cpu0_clk", "cpu1_clk", - "cpu2_clk", "cpu3_clk"; + clocks = <&apsscc APCS_MUX_CLK>; + clock-names = "cpu0_clk"; qcom,cpufreq-table = < 200000 >, < 300000 >, @@ -209,8 +212,8 @@ ahb_clk: qcom,ahb-clk-src { compatible = "devfreq-simple-dev"; + clocks = <&gcc APSS_AHB_CLK_SRC>; clock-names = "devfreq_clk"; - /*TODO: Fix the clock when tree is available*/ governor = "powersave"; freq-tbl-khz = < 19200 >, @@ -219,6 +222,40 @@ < 133330 >; }; + cpubw: qcom,cpubw { + compatible = "qcom,devfreq-icc"; + governor = "cpufreq"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 202, 8); /* 1541 MB/s */ + BW_OPP_ENTRY( 404, 8); /* 3082 MB/s */ + BW_OPP_ENTRY( 518, 8); /* 3952 MB/s */ + }; + + devfreq-cpufreq { + cpubw-cpufreq { + target-dev = <&cpubw>; + cpu-to-dev-map = + < 600000 1541 >, + < 787200 3082 >, + < 1286400 3952 >; + }; + + cpuahb-cpufreq { + target-dev = <&ahb_clk>; + cpu-to-dev-map = + < 200000 19200 >, + < 384000 50000 >, + < 787200 100000 >, + < 1286400 133330 >; + }; + }; + restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>, From cd0de9bd8070421887f450e478d7b7631d4d6b99 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 10 Jan 2021 23:08:47 +0530 Subject: [PATCH 0642/1809] dt-bindings: qpnp-lcdb-regulator: Add support for PM7325B LCDB Add compatible string for PM7325B LCDB device. Remove pmic-revid property as it is not used on kernel 5.4. Add pwrup-delay-ms, qcom,bst-ps-threshold-mv and qcom,pwrup-config properties for PM7325B. Update qcom,bst-ilim-ma, qcom,ncp-ilim-ma and qcom,ldo-ilim-ma for PM7325B. Change-Id: I66b3bfd1782f41eb44cca08adce2a02bada0727c --- bindings/regulator/qpnp-lcdb-regulator.txt | 46 ++++++++++++++++------ 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/bindings/regulator/qpnp-lcdb-regulator.txt b/bindings/regulator/qpnp-lcdb-regulator.txt index 5016aacd157a..ca63521841e0 100644 --- a/bindings/regulator/qpnp-lcdb-regulator.txt +++ b/bindings/regulator/qpnp-lcdb-regulator.txt @@ -24,17 +24,13 @@ First Level Node - LCDB module "qcom,lcdb-pm660" "qcom,lcdb-pmi632" "qcom,lcdb-pm6150l" + "qcom,lcdb-pm7325b" - reg Usage: required Value type: Definition: Base address of the LCDB SPMI peripheral. -- qcom,pmic-revid - Usage: required - Value type: - Definition: Phandle to the PMIC's revid node - - qcom,voltage-step-ramp Usage: optional Value type: @@ -49,6 +45,23 @@ First Level Node - LCDB module Definition: Required to control the LDO power down delay. Possible values are 0, 1, 4, 8. +- qcom,pwrup-delay-ms + Usage: optional + Value type: + Definition: Required to control the LDO power up delay. + Possible values are 0, 1, 4, 8. + +- qcom,pwrup-config + Usage: optional + Value type: + Definition: Controls the order of powering up BOOST, LDO AND NCP + blocks. Appilcable for PM7325B. Possible values are: 0, 1, 2, 3, 4. + 0 - Boost, LDO, NCP + 1 - Boost, LDO + 2 - Boost, NCP + 3 - Boost only + 4 - Boost, NCP, LDO + Touch-to-wake (TTW) properties: TTW supports 2 modes of operation - HW and SW. In the HW mode the enable/disable @@ -141,8 +154,9 @@ Properties below are specific to LDO bias only. - qcom,ldo-ilim-ma Usage: optional Value type: - Definition: Current limit (in mA) of the LDO bias. - Possible values are 110, 160, 210, 260, 310, 360, 410, 460. + Definition: Current limit (in mA) of the LDO bias. For PM7325B, possible + values are 35, 175, 280, 420, 455, 595, 700, 840. For other PMICs, + possible values are 110, 160, 210, 260, 310, 360, 410, 460. - qcom,ldo-soft-start-us Usage: optional @@ -150,7 +164,6 @@ Properties below are specific to LDO bias only. Definition: Soft-start time (in uS) of the LDO bias. Possible values are 0, 500, 1000, 2000. - NCP subnode properties: Properties below are specific to NCP bias only. @@ -180,8 +193,9 @@ Properties below are specific to NCP bias only. - qcom,ncp-ilim-ma Usage: optional Value type: - Definition: Current limit (in mA) of the NCP bias. - Possible values are 260, 460, 640, 810. + Definition: Current limit (in mA) of the NCP bias. For PM7325B, possible + values are 700, 80, 900, 1000. For other PMICs, possible values + are 260, 460, 640, 810. - qcom,ncp-soft-start-us Usage: optional @@ -221,11 +235,19 @@ Properties below are specific to BOOST subnode only. Definition: Current threshold (in mA) at which pulse-skip is entered. Possible values are 50, 60, 70, 80. +- qcom,bst-ps-threshold-mv + Usage: optional + Value type: + Definition: Current threshold (in mv) at which pulse-skip is entered. + Applicable for PM7325B. Possible values are 360, 384, 408, 432, + 456, 480, 504, 528. + - qcom,bst-ilim-ma Usage: optional Value type: - Definition: Current limit (in mA) of the BOOST rail. - Possible values are 200 to 1600mA in 200mA steps. + Definition: Current limit (in mA) of the BOOST rail. For PM7325B, possible + possible values are 1130 to 2250mA in 160mA steps. For other PMICs, + possible values are 200 to 1600mA in 200mA steps. - qcom,bst-headroom-mv Usage: optional From d022bac3e7248341c7d2aa23edfca99c27876dcf Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 24 Dec 2020 10:34:30 +0530 Subject: [PATCH 0643/1809] ARM: dts: msm: Add LCDB and WLED devices for PM7325B Add LCDB and WLED devices for PM7325B with configurations required for yupik panel. Change-Id: Ie54f34737e4edeba6995c2272e7dfb4c76d556fe --- qcom/pm7325b.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik-idp.dtsi | 6 +++++ 2 files changed, 65 insertions(+) diff --git a/qcom/pm7325b.dtsi b/qcom/pm7325b.dtsi index 0ca5f7732a39..4fd41e4bdcd8 100644 --- a/qcom/pm7325b.dtsi +++ b/qcom/pm7325b.dtsi @@ -35,6 +35,65 @@ qcom,vib-ldo-volt-uv = <3000000>; qcom,disable-overdrive; }; + + pm7325b_lcdb: qcom,lcdb@fd00 { + compatible = "qcom,lcdb-pm7325b"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfd00>; + interrupts = <0x3 0xfd 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6400000>; + }; + }; + + pm7325b_wled: qcom,wled@d800 { + compatible = "qcom,pm7325b-spmi-wled"; + reg = <0xfb00>, <0xfc00>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x3 0xfb 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xfb 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xfb 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,auto-calibration; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; }; }; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 92d4c51d29d2..5081bc580461 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -181,6 +181,12 @@ }; }; +&pm7325b_wled { + qcom,string-cfg = <3>; + qcom,leds-per-string = <8>; + qcom,fs-current-limit = <22500>; +}; + &spmi_debug_bus { status = "ok"; }; From a6ca6d7d2c7176d4725eed93c73e112a20a4f7c6 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 30 Dec 2020 15:29:28 +0800 Subject: [PATCH 0644/1809] ARM: dts: msm: add mem_dump entry for sdxnightjar Add memory dump entry on sdxnightjar. Change-Id: Ic2494e6d1265deb4065fb429c9db863c5c103955 --- qcom/sdxnightjar.dtsi | 77 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 3e91d4b919c5..feb3b75c4d95 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -48,6 +48,13 @@ reg = <0x88000000 0x7300000>; label = "mss_mem"; }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + size = <0x400000>; + }; }; aliases { }; @@ -292,6 +299,76 @@ }; }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + cnss_wlan { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + tmc_etf { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0xf0>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + dbgui_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe5>; + }; + + etm_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xa0>; + }; + + log_buf { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x110>; + }; + + log_idx { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x111>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + pmic_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe4>; + }; + + vsense_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe9>; + }; + + rpm_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xea>; + }; + }; + qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; From 4eed6209033b140a8e04c0ce97e699d8699564b9 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Tue, 12 Jan 2021 12:27:34 +0530 Subject: [PATCH 0645/1809] ARM: dts: msm: Add a new pinctrl state for yupik This change adds new pinctrl state shutdown. Change-Id: I30fd0387c43d193ba1d1f8f9541e1601680eee73 --- qcom/yupik-qupv3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index 9bb6f89e0941..f71924ee5304 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -342,13 +342,15 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se7_default_cts>, <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, <&qupv3_se7_tx>; pinctrl-2 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, <&qupv3_se7_tx>; + pinctrl-3 = <&qupv3_se7_default_cts>, + <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; qcom,wakeup-byte = <0xFD>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; From 4b4dff2b916117a7f4d2a2be4c1e17ab1a75f4b8 Mon Sep 17 00:00:00 2001 From: Harsh Agarwal Date: Tue, 12 Jan 2021 12:23:23 +0530 Subject: [PATCH 0646/1809] dt-bindings: Document usage of qcom,ignore-wakeup-src-in-hostmode Add the documentation for "qcom,ignore-wakeup-src-in-hostmode". This property allows PM suspend/freeze irrespective of host runtimePM state. Change-Id: I4e5d10da6927ee4720244160f4f7ae8927ebe051 --- bindings/usb/msm-ssusb.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/bindings/usb/msm-ssusb.txt b/bindings/usb/msm-ssusb.txt index 74a930ba640f..c06374302acc 100644 --- a/bindings/usb/msm-ssusb.txt +++ b/bindings/usb/msm-ssusb.txt @@ -86,9 +86,12 @@ Optional properties : are supported. If omitted, assume HW supports "1.5". - qcom,reset-ep-after-lpm-resume: If present, dbm requires ep reset after going to lpm -- qcom,host-poweroff-in-pm-suspend: If present, allow PM suspend to happen - irrespective of runtimePM state of host and power collapse the core. - This also leads to reset-resume of connected devices on PM resume. +- qcom,ignore-wakeup-src-in-hostmode: If present, PM suspend/freeze allowed + irrespective of host runtimePM state. In PM suspend/resume case, core + will stay powered and connected devices will just be suspended/resumed. + In hibernation, core will power collapse and connected devices will + reset-resume on PM restore. Also, USB remote wakeup from system suspend + will not be supported. - qcom,default-mode-none: If present, do not start any mode on probe for an OTG capable DWC3 which does not have extcon handle. - qcom,default-mode-host: If present, start host mode on probe for an OTG From 3573d8902783ab0ed9c12f877e3977419e0e7766 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 12 Jan 2021 15:43:15 +0800 Subject: [PATCH 0647/1809] ARM: dts: msm: Correct dtsi file for Lahaina HHG non-overlay dts Correct the included dtsi file for Lahaina HHG. Change-Id: I921f16912f24d76d4fc2ddffb724f7cfaa01a7af --- qcom/lahaina-v2.1-hhg.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-v2.1-hhg.dts b/qcom/lahaina-v2.1-hhg.dts index a38a944022cb..5ecd7583c71f 100644 --- a/qcom/lahaina-v2.1-hhg.dts +++ b/qcom/lahaina-v2.1-hhg.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "lahainap-v2.1.dtsi" +#include "lahaina-v2.1.dtsi" #include "lahaina-hhg.dtsi" / { From 3cf57901b55c9da45bb5bc25f220dcccc3a1afc8 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 12 Jan 2021 16:19:04 +0530 Subject: [PATCH 0648/1809] ARM: dts: msm: Add support for sysdev on sdxnightjar Add support for sysdev on sdx12 which helps to populate dwc->sysdev which will be inherited from parent, to set the hardware / firmware parameters like dma. Change-Id: I075de4fc75363da4fc0dea7c99549c832783206f --- qcom/sdxnightjar-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index e274820066d5..6d90c50ed701 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -43,6 +43,7 @@ reg = <0x08a00000 0xcd00>; interrupts = ; usb-phy = <&qusb_phy>, <&ssphy>; + linux,sysdev_is_parent; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; From f09cf99925ee7f2f6a1022b2d29889fb383491a9 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Wed, 30 Dec 2020 19:27:32 +0530 Subject: [PATCH 0649/1809] ARM: dts: msm: Update extcon for USB on sdxnightjar Update extcon property for USB to support VBUS and ID notification through extcon framework on sdxnightjar. Change-Id: I43dcf76931176e03cd69d39346e90563095c3bc6 --- qcom/sdxnightjar.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 3009b39b50cc..3cb62621f2ed 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -835,3 +835,7 @@ dpdm-supply = <&qusb_phy>; }; }; + +&usb3 { + extcon = <&smb1351_otg_supply>; +}; From 6d04630ea1b5bcadf6dc04f18586ba830953abee Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 12 Jan 2021 20:15:51 +0530 Subject: [PATCH 0650/1809] ARM: dts: msm: update interconnect and global interuupts on yupik This change does the following: 1) Remove kgsl smmu interconnect node. For TCU config register access we shouldn't required DDR path votes. KGSL smmu already votes for clock and regulator. 2) Remove the tcu_comb_irpt_ns for both apps and kgsl smmu as the interrupt is OR of context interrupts, TBU perf interrupts and global fault interrupts. This interrupt is not really required and registering for the same can showup as the global faults in EL1. Change-Id: I4de4a866d936f1f7f053479dc00c72c46e84d80d --- qcom/msm-arm-smmu-yupik.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index f9dea0234c00..833995eda61c 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -10,7 +10,7 @@ qcom,skip-init; qcom,use-3-lvl-tables; qcom,split-tables; - #global-interrupts = <2>; + #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; ranges; @@ -33,10 +33,7 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; - interrupts = , - , , , , @@ -77,13 +74,12 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; - #global-interrupts = <2>; + #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; ranges; dma-coherent; interrupts = , - , , , , From 4ae1ae18331e54470999920f734e07ca28ce3541 Mon Sep 17 00:00:00 2001 From: Amir Levy Date: Wed, 16 Dec 2020 11:25:57 +0200 Subject: [PATCH 0651/1809] ARM: dts: msm: enable more SIDs Enable SIDs for eth/eth1/wlan1. Add max number of CB parameter. Change-Id: Ib1b1eb5d95cf5f407dc1d8229f52b631f54a94c9 --- bindings/platform/msm/ipa.txt | 7 +++++++ qcom/sdxlemur.dtsi | 20 ++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 9b8bc6cead21..8a083792725c 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -46,6 +46,12 @@ Optional: compatible "qcom,ipa-smmu-uc-cb" - ipa_smmu_11ad: 11AD SMMU device compatible "qcom,ipa-smmu-11ad-cb" +- ipa_smmu_wlan1: WDI (PINE) SMMU device + compatible "qcom,ipa-smmu-wlan1-cb" +- ipa_smmu_eth: ETH (AQC/RTK/NTN) SMMU device + compatible "qcom,ipa-smmu-eth-cb" +- ipa_smmu_eth1: ETH1 (WAN/CV2X) SMMU device + compatible "qcom,ipa-smmu-eth1-cb" - qcom,use-a2-service: determine if A2 service will be used - qcom,use-ipa-tethering-bridge: determine if tethering bridge will be used - qcom,use-ipa-in-mhi-mode: Boolean context flag to indicate whether @@ -127,6 +133,7 @@ memory allocation over a PCIe bridge 2 (override scm call as though it returned false) - qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event rings read pointer should be read from the ddr. +- qcom,max_num_smmu_cb: number of active smmu context banks for target. IPA pipe sub nodes (A2 static pipes configurations): diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 60d1be464806..d2590e07ba3b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1087,6 +1087,7 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; qcom,interconnect,num-paths = <4>; + qcom,max_num_smmu_cb = <6>; interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>, <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, <&system_noc MASTER_IPA &system_noc SLAVE_IMEM>, @@ -1142,11 +1143,22 @@ qcom,iommu-dma = "atomic"; }; - ipa_smmu_11ad: ipa_smmu_11ad { - compatible = "qcom,ipa-smmu-11ad-cb"; + ipa_smmu_eth: ipa_smmu_eth { + compatible = "qcom,ipa-smmu-eth-cb"; iommus = <&apps_smmu 0x5E3 0x0>; - qcom,shared-cb; - qcom,iommu-group = <>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_eth1: ipa_smmu_eth1 { + compatible = "qcom,ipa-smmu-eth1-cb"; + iommus = <&apps_smmu 0x5E4 0x0>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_wlan1: ipa_smmu_wlan1 { + compatible = "qcom,ipa-smmu-wlan1-cb"; + iommus = <&apps_smmu 0x5E5 0x0>; + qcom,iommu-dma = "atomic"; }; /* smp2p information */ From b4b927efd734c1c06dfb72ebf36080b97bc68c43 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Thu, 7 Jan 2021 16:18:18 +0800 Subject: [PATCH 0652/1809] ARM: dts: qcom: enable fan controller for Lahaina HHG Enabling Fan Controller driver for Lahaina HHG platform. Change-Id: Ifdb323cde18610b76662b1d305dc5af14dd2aa05 --- qcom/lahaina-hhg.dtsi | 53 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 833d8fd0c2fb..01346fc9df76 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -44,3 +44,56 @@ qcom,wsa-max-devs = <2>; }; + +&tlmm { + fan: fan_pin { + mux { + pins = "gpio107","gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio107","gpio108"; + bias-pull-up; + drive-strength = <16>; + }; + }; +}; + +&pm8008i_l7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3400000>; +}; + +&soc { + i2c@0 { + compatible = "i2c-gpio"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&fan>; + gpios = <&tlmm 107 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN) /* sda */>, + <&tlmm 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN) /* scl */>; + + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fancontroller: max31760@50 { + compatible = "maxim,max31760"; + reg = <0x50>; + maxim,vdd-supply = <&pm8008i_l7>; + regulator-names = "maxim,vdd"; + maxim,vdd-max-uv = <3400000>; + maxim,vdd-min-uv = <3300000>; + maxim,vdd-load-ua = <300000>; + maxim,vcca-supply = <&pm8350_s10>; + maxim,vcca-max-uv = <1800000>; + maxim,vcca-min-uv = <1800000>; + maxim,vcca-load-ua = <600000>; + maxim,fan_en_gpio = <&tlmm 48 0x00>; + status = "ok"; + }; + }; +}; From 91850032aeb36187abb011b46c45cba131b6c2af Mon Sep 17 00:00:00 2001 From: phaneendra Reddy Date: Mon, 11 Jan 2021 18:38:36 +0530 Subject: [PATCH 0653/1809] ARM: dts: msm: Add support for FM in yupik platform This patch adds support of RTC6226 Soc in yupik platform and enables se1_i2c. CRs-Fixed: 2852905 Change-Id: I9ddec09dfed428a5556bf2976e59290d783d7159 --- qcom/yupik.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index ba2f30811dfe..d383c8b05247 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3818,3 +3818,17 @@ #include "msm-rdbg.dtsi" #include "yupik-gpu.dtsi" #include "yupik-thermal.dtsi" + +&qupv3_se1_i2c { + status = "ok"; + nq@64 { + compatible = "rtc6226"; + reg = <0x64>; + fmint-gpio = <&tlmm 18 0>; + vdd-supply = <&L11C>; + rtc6226,vdd-supply-voltage = <2800000 2800000>; + rtc6226,vdd-load = <15000>; + vio-supply = <&L19B>; + rtc6226,vio-supply-voltage = <1800000 1800000>; + }; +}; From de18def007ffd416cb53430a8eda48a691e896d8 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 18 Dec 2020 15:29:12 +0800 Subject: [PATCH 0654/1809] ARM: dts: msm: Enable dcc for yupik Enable dcc for yupik since dcc virtualization is enabled. Change-Id: Ibe1f05d7bc0217696cd03d7b4d2783de49e5c10d --- qcom/yupik.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index ba2f30811dfe..c5551d663637 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -722,7 +722,6 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; - status = "disabled"; }; qcom,msm-imem@146aa000 { From 960a89d0fb14b0546bb45c2453e22e7a7c207688 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 12 Jan 2021 11:32:18 +0530 Subject: [PATCH 0655/1809] ARM: dts: msm: add touch support on yupik target This change adds touch support for yupik IDP platform. Change-Id: I9ec6adacf1f1c2bfb8a8266819bc4de01bc90a90 --- qcom/yupik-idp.dtsi | 27 +++++++++++++++++++ qcom/yupik-pinctrl.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index ba10bba6ac2c..f3d1774b6930 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -259,3 +259,30 @@ status = "ok"; }; + +&qupv3_se13_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active="novatek,NVT-ts"; + + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + + interrupt-parent = <&tlmm>; + interrupts = <81 0x2008>; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + novatek,reset-gpio = <&tlmm 105 0x00>; + novatek,irq-gpio = <&tlmm 81 0x2008>; + + }; +}; diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index b887f34b852a..a1006126a1bc 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -2868,5 +2868,65 @@ }; }; }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio105", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio105", "gpio81"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio105", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio105", "gpio81"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; }; From d28b0ddeb746b3d243a85005dfb579f3ee2cf098 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 5 Jan 2021 18:47:06 +0530 Subject: [PATCH 0656/1809] ARM: dts: msm: Include display nodes for yupik target This change includes display sde node and platform specific nodes in the corresponding platform DT files for Yupik target. Change-Id: I2d425fb55af625f91b964a58a3c61f9a690c44e9 --- qcom/yupik-idp.dtsi | 3 +++ qcom/yupik.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index f3d1774b6930..0ba3934cdcf4 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -5,6 +5,7 @@ #include "pm7325b.dtsi" #include "yupik-audio-overlay.dtsi" #include "yupik-thermal-overlay.dtsi" +#include "display/yupik-sde-display-idp.dtsi" &soc { gpio_keys { @@ -284,5 +285,7 @@ novatek,reset-gpio = <&tlmm 105 0x00>; novatek,irq-gpio = <&tlmm 81 0x2008>; + panel = <&dsi_nt36672e_fhd_plus_60_video + &dsi_nt36672e_fhd_plus_144_video>; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index ba2f30811dfe..51fabbe8f2cf 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3686,6 +3686,7 @@ #include "yupik-pm.dtsi" #include "ipcc-test-yupik.dtsi" #include "yupik-regulators.dtsi" +#include "display/yupik-sde.dtsi" &gcc_ufs_phy_gdsc { qcom,support-hw-trigger; From 96d4625595793887f6441f5a0ec4c0bdf3e4d004 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Wed, 13 Jan 2021 12:10:33 +0530 Subject: [PATCH 0657/1809] ARM: dts: msm: Add a new pinctrl state for lahaina This change adds new pinctrl state shutdown. Change-Id: Ifbaaeb6ef79ae1bb5d95d15b6961635f058cc7ee --- qcom/lahaina-qupv3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-qupv3.dtsi b/qcom/lahaina-qupv3.dtsi index 723b2eaab701..159c0977f21e 100644 --- a/qcom/lahaina-qupv3.dtsi +++ b/qcom/lahaina-qupv3.dtsi @@ -848,13 +848,15 @@ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se18_default_cts>, <&qupv3_se18_default_rtsrx>, <&qupv3_se18_default_tx>; pinctrl-1 = <&qupv3_se18_ctsrx>, <&qupv3_se18_rts>, <&qupv3_se18_tx>; pinctrl-2 = <&qupv3_se18_ctsrx>, <&qupv3_se18_rts>, <&qupv3_se18_tx>; + pinctrl-3 = <&qupv3_se18_default_cts>, + <&qupv3_se18_default_rtsrx>, <&qupv3_se18_default_tx>; interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 71 IRQ_TYPE_LEVEL_HIGH>; qcom,wrapper-core = <&qupv3_2>; From 16afe50bdbc49bd34d05ea4399ec3a9764add830 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Wed, 13 Jan 2021 06:24:29 +0530 Subject: [PATCH 0658/1809] ARM: dts: qcom: Update Audio dtsi entries Update Audio dtsi entries Change-Id: I9cda1d18ca23f1ab62e64b1d66f6e3aed3fd255b --- qcom/sdxlemur-audio-overlay.dtsi | 11 ++++++----- qcom/sdxlemur-audio.dtsi | 5 +---- qcom/sdxlemur-blsp.dtsi | 2 +- qcom/sdxlemur.dtsi | 4 ++-- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/qcom/sdxlemur-audio-overlay.dtsi b/qcom/sdxlemur-audio-overlay.dtsi index 172f7237318f..ee94ed76740b 100644 --- a/qcom/sdxlemur-audio-overlay.dtsi +++ b/qcom/sdxlemur-audio-overlay.dtsi @@ -24,22 +24,23 @@ "DMIC4", "MIC BIAS4", "DMIC5", "Digital Mic5", "DMIC5", "MIC BIAS4", - "SpkrLeft IN", "SPK2 OUT"; + "SpkrLeft IN", "SPK1 OUT"; qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; - qcom,cdc-ext-clk-rate = <19200000>; - qcom,tavil-mclk-clk-freq = <12288000>; + qcom,cdc-ext-clk-rate = <9600000>; + qcom,tavil-mclk-clk-freq = <9600000>; - asoc-codec = <&stub_codec>; - asoc-codec-names = "msm-stub-codec.1"; + asoc-codec = <&stub_codec>, <&wsa881x_0214>; + asoc-codec-names = "msm-stub-codec.1", "wsa-codec.1"; qcom,wsa-max-devs = <1>; qcom,swr-num-dev = <1>; qcom,wsa-devs = <&wsa881x_0214>; qcom,wsa-aux-dev-prefix = "SpkrLeft"; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&wcd934x_cdc>; }; &soc { diff --git a/qcom/sdxlemur-audio.dtsi b/qcom/sdxlemur-audio.dtsi index 30535b3a51d6..4f3cae1c280c 100644 --- a/qcom/sdxlemur-audio.dtsi +++ b/qcom/sdxlemur-audio.dtsi @@ -4,10 +4,7 @@ snd_934x: sound-tavil { compatible = "qcom,sdx-asoc-snd-tavil"; qcom,model = "sdx-tavil-i2s-snd-card"; - qcom,prim_mi2s_aux_master = <&prim_master>; - qcom,prim_mi2s_aux_slave = <&prim_slave>; - qcom,sec_mi2s_aux_master = <&sec_master>; - qcom,sec_mi2s_aux_slave = <&sec_slave>; + qcom,prim_mi2s_master = <&prim_master>; asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, <&loopback>, <&hostless>, <&afe>, <&routing>, diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi index 0a9b76bee5c0..cf8111d19fd6 100644 --- a/qcom/sdxlemur-blsp.dtsi +++ b/qcom/sdxlemur-blsp.dtsi @@ -91,7 +91,7 @@ pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; - status = "disabled"; + status = "ok"; }; i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 84,85 */ diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 9b43f3c57fbf..2ad0eec3e965 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -52,7 +52,7 @@ audio_mem: audio_region@0 { compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; + alloc-ranges = <0x00000000 0xffffffff>; reusable; size = <0x400000>; }; @@ -674,7 +674,7 @@ 0x4400 2>; }; - qcom,gpr { + audio_gpr: qcom,gpr { compatible = "qcom,gpr"; qcom,glink-channels = "modem_apps"; qcom,intents = <0x200 20>; From fe52ebcd922417ec02b45b88340b20c1b814ca08 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 07:58:12 +0530 Subject: [PATCH 0659/1809] ARM: dts: msm: Add spss device node for PIL SM8150 Add PIL device tree node to load firmware images of spss on sm8150. Change-Id: I6d4900f815a55f5728fb4d77880007105137b821 --- qcom/sm8150.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index beed59ee7e92..6637792cbc23 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1825,6 +1825,41 @@ mboxes = <&qmp_aop 0>; mbox-names = "slpi-pil"; }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mx-uV = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; }; &firmware { From d04482bb7cb6b85d995f06a93197dcb1baa81918 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:00:58 +0530 Subject: [PATCH 0660/1809] ARM: dts: msm: Add npu device node for PIL on SM8150 Add PIL device tree node to load firmware images of npu on sm8150. Change-Id: Ief00be65002f90191420b99ae7102897ee565f2b --- qcom/sm8150.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6637792cbc23..5227cbbfb2f7 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1860,6 +1860,17 @@ mboxes = <&qmp_aop 0>; mbox-names = "spss-pil"; }; + + qcom,npu@9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; }; &firmware { From f0b24ffd71bd9da84470633987bfe0d528fa3dac Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:04:22 +0530 Subject: [PATCH 0661/1809] ARM: dts: msm: Add turing device node for PIL on SM8150 Add PIL device tree node to load firmware images of turing on sm8150. Change-Id: I27ed87d799313ca6732ec71e81e523d9d455762f --- qcom/sm8150.dtsi | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 5227cbbfb2f7..79af9ff97269 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1871,6 +1871,56 @@ memory-region = <&pil_npu_mem>; }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; &firmware { From 3b0b3c18f731a07e90bae0f2bb6e37c68e8ac097 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:08:57 +0530 Subject: [PATCH 0662/1809] ARM: dts: msm: Add venus device node for PIL on SM8150 Add PIL device tree node to load firmware images of venus on sm8150. Change-Id: I7e9d723823447a3fcb22e93533a448e318d90574 --- qcom/sm8150.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 79af9ff97269..e457858a76e5 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1921,6 +1921,32 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&videocc VIDEO_CC_XO_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; &firmware { From eeda79ad102c5d6ed7a0c5f676999fd6e6395c26 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:14:25 +0530 Subject: [PATCH 0663/1809] ARM: dts: msm: Enable device nodes for PIL on SM8150 Enable PIL device tree nodes to load firmware images of venus, npu, lpass, spss, on sa8155. Change-Id: I8a5915e57fa208b6bc28475f0d097398f0b6afe5 --- qcom/sa8155-adp-common.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index fefcd3bad4be..d7156a1f25f0 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -61,3 +61,26 @@ &pil_modem { status = "disabled"; }; + +&soc { + qcom,lpass@17300000 { + status = "ok"; + qcom,pil-force-shutdown; + }; + + qcom,turing@8300000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,spss@1880000 { + status = "ok"; + }; + + qcom,npu@9800000 { + status = "ok"; + }; +}; From 94be92caece46ebb7eb67c25e50dc80475109546 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 29 Jul 2020 11:56:51 +0530 Subject: [PATCH 0664/1809] ARM: dts: msm: Fix wdog interrupts on pil subsystems for SM8150 On newer kernels PDC interrupt can only be requested if its actually routed through PDC HW. Update the pil subsystems interrupts to use intc interrupts when they are direct interrupts at GIC and only use PDC if it has routing to PDC HW. Also, add missing properties vdd_mx-supply and shutdown-ack to pil lpass node. Change-Id: Ie60515cd51e55ce0772d5d2c89a603b63ba44545 --- qcom/sm8150.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index e457858a76e5..2825173ad88c 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1712,7 +1712,7 @@ qcom,complete-ramdump; /* Inputs from mss */ - interrupts-extended = <&pdc 0 266 1>, + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, @@ -1740,7 +1740,9 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,vdd_cx-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; @@ -1755,20 +1757,21 @@ memory-region = <&pil_adsp_mem>; qcom,signal-aop; qcom,complete-ramdump; - qcom,pil-force-shutdown; /* Inputs from lpass */ - interrupts-extended = <&pdc 0 162 1>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", - "qcom,stop-ack"; + "qcom,stop-ack", + "qcom,shutdown-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -1806,7 +1809,7 @@ qcom,complete-ramdump; /* Inputs from ssc */ - interrupts-extended = <&pdc 0 494 1>, + interrupts-extended = <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&dsps_smp2p_in 0 0>, <&dsps_smp2p_in 2 0>, <&dsps_smp2p_in 1 0>, From 4e5cad47bf9554ef9970208c832c8095bdfdf896 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:07:31 +0530 Subject: [PATCH 0665/1809] ARM: dts: msm: Add scm & scm-pas device on SDMSHRIKE Add device nodes for scm & scm-pas for SDMSHRIKE SoC. This is needed to secure memory buffers, and protect them against unauthorized access. Change-Id: Ia7d57cd3b2ef520839d46a77da64fd0aa2ca1d6a --- qcom/sdmshrike.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 006a1d4bb2a2..f3ba2a28e8b3 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -503,6 +503,10 @@ compatible = "simple-bus"; }; + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + soc: soc { }; }; @@ -665,6 +669,12 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO + &mc_virt SLAVE_EBI1>; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; @@ -1481,6 +1491,12 @@ #include "sa8195-ssc-qupv3.dtsi" #include "sa8195-usb.dtsi" +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + &emac_gdsc { status = "ok"; }; From e71c756ffc0f6acb84912717fe2ce77abf81e9d7 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:45:45 +0530 Subject: [PATCH 0666/1809] ARM: dts: msm: Add lpass device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of lpass on SDMSHRIKE. Change-Id: Ic04366af333b8cb9292820539937df1d538c769d --- qcom/sdmshrike.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f3ba2a28e8b3..9ea6492e327f 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1463,7 +1463,6 @@ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; qcom,devfreq,freq-table = <50000000 200000000>; - status = "disabled"; qos0 { @@ -1477,6 +1476,49 @@ }; }; + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + qcom,pil-force-shutdown; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi" From e4a8c511b36accc01b88d42298a1aeccb2ed98d1 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:53:23 +0530 Subject: [PATCH 0667/1809] ARM: dts: msm: Add turing device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware image of turing on SDMSHRIKE. Change-Id: I1b3baa6587f738be5e7f7112c35a082bb6c2f317 --- qcom/sdmshrike.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 9ea6492e327f..c41aace55b9c 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1519,6 +1519,56 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi" From 6b11e0a44a647261d8ae2135591dbf24a2c889a6 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 14 Aug 2020 14:38:58 +0530 Subject: [PATCH 0668/1809] ARM: dts: msm: Add npu device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of npu on SDMSHRIKE. Change-Id: I8ec1d063fc79aad4759c573dca6fe8e933a109c2 --- qcom/sdmshrike.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index c41aace55b9c..35ea04de2ac4 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1569,6 +1569,17 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,npu@9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; }; #include "sdmshrike-pinctrl.dtsi" From 58bdea2c506dbf110878514c0dab6c908f9853b1 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 14 Aug 2020 15:07:15 +0530 Subject: [PATCH 0669/1809] ARM: dts: msm: Add venus device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of venus on SDMSHRIKE. Change-Id: I8df270d8b7ad00967f04c710d837be430ac7ef56 --- qcom/sdmshrike.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 51d4254d722b..bbaed2bd035b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1615,6 +1615,32 @@ mboxes = <&qmp_aop 0>; mbox-names = "spss-pil"; }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&videocc VIDEO_CC_XO_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "sdmshrike-pinctrl.dtsi" From bf71e319b638cc21aa7018e0dfb3b76214b88807 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 14 Aug 2020 14:51:03 +0530 Subject: [PATCH 0670/1809] ARM: dts: msm: Add spss device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of spss on SDMSHRIKE. Change-Id: I61acf03594390dbcdb47f38443b32969f10e9542 --- qcom/sdmshrike.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 35ea04de2ac4..51d4254d722b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1580,6 +1580,41 @@ memory-region = <&pil_npu_mem>; }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mx-uV = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi" From 3db82568f18ed659fbc89817d6e758f495952162 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 23:07:04 +0530 Subject: [PATCH 0671/1809] ARM: dts: msm: Enable device nodes for PIL on SDMSHRIKE Enable PIL device tree nodes to load firmware images of venus, npu, lpass, spss, on SDMSHRIKE. Change-Id: I8a117cc6e2275754f4277a8bd37708ea419303c1 --- qcom/sa8195p-adp-common.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 40b33a95405f..46f9f966e902 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -25,3 +25,26 @@ status = "ok"; }; + +&soc { + qcom,lpass@17300000 { + status = "ok"; + qcom,pil-force-shutdown; + }; + + qcom,turing@8300000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,spss@1880000 { + status = "ok"; + }; + + qcom,npu@9800000 { + status = "ok"; + }; +}; From b3664f4d62029b021e25bb649cec68a16c6febfe Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 13 Jan 2021 14:34:17 +0530 Subject: [PATCH 0672/1809] ARM: dts: msm: Add cooling-cells property in mdss_mdp device for yupik Add cooling-cells property to enable the mdss_mdp mitigation to be referenced in thermal zone devicetree configurations. Change-Id: I96d7a8b484a5288fc57c34f9d538dde0560c4be9 --- qcom/yupik-thermal-overlay-qrd.dtsi | 4 ++++ qcom/yupik-thermal-overlay.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 7c1faae42457..4d302f1cff41 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -1,5 +1,9 @@ #include +&mdss_mdp { + #cooling-cells = <2>; +}; + &battery_charger { #cooling-cells = <2>; }; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 1abb1a64ab03..247891c9ece0 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -1,5 +1,9 @@ #include +&mdss_mdp { + #cooling-cells = <2>; +}; + &battery_charger { #cooling-cells = <2>; }; From 1d647affae358c6ccc91f4ae609145e62ce3443c Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Wed, 13 Jan 2021 18:16:19 +0800 Subject: [PATCH 0673/1809] ARM: dts: msm: Correct bluetooth node name for sdxnightjar Change bluetooth node name form bt_qca6490 to bt_qca6174. CRs-Fixed: 2848490 Change-Id: I303465f4bc04b6399c6771b88c1b45617a4316da --- qcom/sdxnightjar-bluetooth.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar-bluetooth.dtsi b/qcom/sdxnightjar-bluetooth.dtsi index 578fd72d2fc9..37f5c7928774 100644 --- a/qcom/sdxnightjar-bluetooth.dtsi +++ b/qcom/sdxnightjar-bluetooth.dtsi @@ -12,7 +12,7 @@ }; &soc { - bluetooth: bt_qca6490 { + bluetooth: bt_qca6174 { compatible = "qcom,qca6174"; pinctrl-names = "default"; pinctrl-0 = <&bt_en_default>; From 34ec1d078c2521096cca1743ff19b9e832cfa45a Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Wed, 13 Jan 2021 23:45:09 +0530 Subject: [PATCH 0674/1809] ARM: dts: msm: Rectify DT flags and GPII mask for TUI VM usecase This change rectifies the GPII masks based on assigned GPII to TVM and also corrects other TUI usecase related flags on Yupik. Change-Id: Icd6d03dd237ac5d5c0a34747f93a54775fd53192 --- qcom/yupik-qupv3.dtsi | 2 +- qcom/yupik-vm.dtsi | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index b6e0ba1b3e4f..1f8412e719e3 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -391,7 +391,7 @@ , ; qcom,static-gpii-mask = <0x1>; - qcom,gpii-mask = <0x3f>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index e07023a4627a..11ed738c5647 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -251,10 +251,11 @@ , , ; - qcom,gpii-mask = <0x80>; + qcom,gpii-mask = <0x20>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; status = "ok"; }; @@ -263,8 +264,8 @@ reg = <0xa94000 0x4000>; #address-cells = <1>; #size-cells = <0>; - dmas = <&gpi_dma1 0 5 3 64 2>, - <&gpi_dma1 1 5 3 64 2>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; qcom,le-vm; @@ -277,8 +278,8 @@ #address-cells = <1>; #size-cells = <0>; reg-names = "se_phys"; - dmas = <&gpi_dma1 0 5 1 64 2>, - <&gpi_dma1 1 5 1 64 2>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; From fe8765fe7550355f8fb006de9cf74205c66cc3f9 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 2 Sep 2020 18:39:44 +0530 Subject: [PATCH 0675/1809] bindings: clock: Add support for SM6150 clock controllers Update the CAMCC, DEBUGCC, DISPCC, GCC, GPUCC, RPMHCC, SCC and VIDEOCC bindings for SM6150 device. Change-Id: Ie9acf4162552c4949c80fd21700342b5f237353e --- bindings/clock/qcom,camcc.txt | 2 ++ bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 2 ++ bindings/clock/qcom,gcc.txt | 2 ++ bindings/clock/qcom,gpucc.txt | 2 ++ bindings/clock/qcom,scc.txt | 2 ++ bindings/clock/qcom,videocc.txt | 2 ++ 7 files changed, 13 insertions(+) diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index 9eaa2b3d7618..40cc663f4f74 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -14,6 +14,8 @@ Required properties : "qcom,yupik-camcc" "qcom,scshrike-camcc" "qcom,scshrike-camcc-v2" + "qcom,sm6150-camcc" + "qcom,sa6155-camcc" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 4cc0522d7bdd..562d527e93cf 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -12,6 +12,7 @@ Required properties : "qcom,yupik-debugcc" "qcom,sdxnightjar-debugcc" "qcom,scshrike-debugcc" + "qcom,sm6150-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index ebd301af54b7..af3ebe5576e0 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -14,6 +14,8 @@ Required properties : "qcom,yupik-dispcc" "qcom,scshrike-dispcc" "qcom,scshrike-dispcc-v2" + "qcom,sm6150-dispcc" + "qcom,sa6155-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index e06b80ade895..db793721b6d4 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -35,6 +35,8 @@ Required properties : "qcom,sdxnightjar-gcc" "qcom,scshrike-gcc" "qcom,scshrike-gcc-v2" + "qcom,sm6150-gcc" + "qcom,sa6155-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 46fe5bd2eb84..9a62efc47ef6 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -10,6 +10,8 @@ Required properties : "qcom,sa8155-gpucc" "qcom,yupik-gpucc" "qcom,scshrike-gpucc" + "qcom,sm6150-gpucc", + "qcom,sa6155-gpucc". - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,scc.txt b/bindings/clock/qcom,scc.txt index 9794d7bf66ac..ae7f6e089ee9 100644 --- a/bindings/clock/qcom,scc.txt +++ b/bindings/clock/qcom,scc.txt @@ -8,6 +8,8 @@ Required properties: "qcom,sa8155-scc-v2" "qcom,sa8195-scc" "qcom,sa8195-scc-v2" + "qcom,sm6150-scc" + "qcom,sa6155-scc" - reg: shall contain base register location and length. - vdd_scc_cx-supply: the logic rail supply. diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index 64f41ad07942..8d8b09ea08ba 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -12,6 +12,8 @@ Required properties : "qcom,sa8155-videocc" "qcom,sa8155-videocc-v2" "qcom,yupik-videocc" + "qcom,sm6150-videocc" + "qcom,sa6155-videocc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. From 8bd79a44801c7e9b517fdd4c60d1faa4707fe216 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 12:31:13 +0530 Subject: [PATCH 0676/1809] dt-bindings: ufs: Add compitable string for V3 UFS PHY on SM6150 This change adds the compatible string for the V3 UFS PHY present on SM6150 chipset. Change-Id: I195388c027c6d40930242738e7eb0f210dc14ab5 --- bindings/ufs/ufs-qcom.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index ce95343f685b..054ac776fa0b 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -22,6 +22,9 @@ Required properties: on SM8150 chipset. "qcom,ufs-phy-qmp-v3" for V3 ufs phy present on holi chipset. + "qcom,ufs-phy-qmp-v3-660" for V3 ufs phy present + on SM6150 chipset. + - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. Required "reg-names" is "phy_mem". From 7c1fabee8b2c3b7109365e324ee3c500832e6df4 Mon Sep 17 00:00:00 2001 From: priyankar Date: Mon, 14 Dec 2020 13:48:44 +0530 Subject: [PATCH 0677/1809] ARM: dts: msm: Add support for Moselle (WCN6750) This patch contains changes for supporting moselle soc. Change-Id: Ibf07457c242973e0f54bcbc466cd4ee79d744578 --- bindings/bluetooth/btpower.txt | 1 + qcom/yupik-pinctrl.dtsi | 14 ++++++++++++++ qcom/yupik.dtsi | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 391361eef201..39c44d4ea365 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -10,6 +10,7 @@ Required properties: qcom,wcn3990 qcom,qca6390 qcom,qca6490 + qcom,wcn6750 - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index b887f34b852a..be642b025745 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1103,6 +1103,20 @@ }; }; + bt_en_sleep: bt_en_sleep { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + qupv3_se14_2uart_pins: qupv3_se14_2uart_pins { qupv3_se14_default_txrx: qupv3_se14_default_txrx { mux { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 61e804c9b521..774145e4524a 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1159,6 +1159,35 @@ }; }; + bluetooth: bt_wcn6750 { + compatible = "qcom,wcn6750"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_sleep>; + qcom,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */ + qcom,bt-sw-ctrl-gpio = <&tlmm 86 0>; /* SW_CTRL */ + qcom,wl-reset-gpio = <&tlmm 84 0>; /* WL_EN */ + + qcom,bt-vdd-io-supply = <&L19B>; /* IO */ + qcom,bt-vdd-aon-supply = <&S7B>; + qcom,bt-vdd-dig-supply = <&S7B>; + qcom,bt-vdd-rfacmn-supply = <&S7B>; + qcom,bt-vdd-rfa-0p8-supply = <&S7B>; + qcom,bt-vdd-rfa1-supply = <&S1B>; /*RFA 1p7*/ + qcom,bt-vdd-rfa2-supply = <&S8B>; /*RFA 1p2*/ + qcom,bt-vdd-ipa-2p2-supply = <&S1C>; /*IPA 2p2*/ + qcom,bt-vdd-asd-supply = <&L11C>; + + qcom,bt-vdd-io-config = <1800000 1800000 0 1>; + qcom,bt-vdd-aon-config = <824000 952000 0 1>; + qcom,bt-vdd-dig-config = <824000 952000 0 1>; + qcom,bt-vdd-rfacmn-config = <824000 952000 0 1>; + qcom,bt-vdd-rfa-0p8-config = <824000 952000 0 1>; + qcom,bt-vdd-rfa1-config = <1872000 1872000 0 1>; + qcom,bt-vdd-rfa2-config = <1256000 1352000 0 1>; + qcom,bt-vdd-ipa-2p2-config = <2200000 2210000 0 1>; + qcom,bt-vdd-asd-config = <2800000 3544000 0 1>; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, @@ -3832,6 +3861,11 @@ #include "yupik-gpu.dtsi" #include "yupik-thermal.dtsi" +/* HS UART */ +&qupv3_se7_4uart { + status = "ok"; +}; + &qupv3_se1_i2c { status = "ok"; nq@64 { From e4017af5d1d376f71081b5ea787a601e44d08e72 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 15 Jan 2021 16:39:01 +0800 Subject: [PATCH 0678/1809] ARM: dts: msm: disable tpdm sdcc on holi The clk of sdcc tpdm is not able to enable from kernel side, so disable it. Change-Id: I2cc4e791720910719689bf106c9c0157f81c9b09 --- qcom/holi-coresight.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 75f31bf5d45e..964ea4bece57 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -808,6 +808,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { tpdm_sdcc0_out_tpda_qdss29: endpoint { @@ -829,6 +830,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { tpdm_sdcc1_out_tpda_qdss30: endpoint { From 3f45d6a476c6ba9e21b2c8184d898933493ea3fc Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Tue, 19 May 2020 17:25:20 +0530 Subject: [PATCH 0679/1809] ARM: dts: msm: Add device node for llcc on sm8150 Add device node for last level cache controller on SM8150. Change-Id: I408fa74757a016ac57263f292a14e134bab33697 --- bindings/arm/msm/qcom,llcc.txt | 2 +- qcom/sm8150.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 64e1fe37e270..c7640f8bf122 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -13,7 +13,7 @@ Properties: Value type: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" - or "qcom,yupik-llcc" + or "qcom,yupik-llcc" or "qcom,sm8150-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2825173ad88c..fe7a0251dfd2 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1950,6 +1950,13 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + cache-controller@9200000 { + compatible = "qcom,sm8150-llcc"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; }; &firmware { From c97537f9ec4311739aa319b01de77ef6835284aa Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 5 Jan 2021 20:10:48 +0530 Subject: [PATCH 0680/1809] ARM: dts: msm: Add device node for llcc node on SDMSHRIKE Add device node for last level cache controller on SDMSHRIKE target. Change-Id: I33ef1895e9228cf897942051eb1f7fd7596d79a1 --- bindings/arm/msm/qcom,llcc.txt | 1 + qcom/sdmshrike.dtsi | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index c7640f8bf122..6bddb3cbb70c 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,6 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" + or "qcom,sdmshrike-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index bbaed2bd035b..6191c8b4045b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -621,6 +621,13 @@ }; }; + cache-controller@9200000 { + compatible = "qcom,sdmshrike-llcc"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; From 31f7661e9ead7f4ac3b1e250e8d814d136151569 Mon Sep 17 00:00:00 2001 From: sganda Date: Fri, 15 Jan 2021 19:16:49 +0530 Subject: [PATCH 0681/1809] ARM: dts: msm: Change QSEE,glink IRQs to level trigger Change the IRQ handlers from EDGE to level trigger to prevent missing rapid IRQs from SPU. Change-Id: I1b0a862edf26ca2540591ba866adb6498dd51b43 --- qcom/lahaina.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 25926f595614..d261cf1f5436 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2229,7 +2229,7 @@ interrupt-parent = <&ipcc_mproc>; interrupts = ; + IRQ_TYPE_LEVEL_HIGH>; label = "spss"; }; }; @@ -4376,7 +4376,7 @@ interrupt-parent = <&ipcc_mproc>; interrupts = ; + IRQ_TYPE_LEVEL_HIGH>; reg = <0x1885008 0x8>, <0x1885010 0x4>; From 00d232ff7901b9797a23e2c39f9bbb0e253c21cb Mon Sep 17 00:00:00 2001 From: Mahesh Kumar Sharma Date: Thu, 3 Dec 2020 16:18:33 -0800 Subject: [PATCH 0682/1809] ARM: dts: msm: Add entry to handle XO clock gpio In order to avoid leakage, GPIO 201 mapped to XO clock needs to be pulled high for 2 ms and pull it low to prevent leakage. Add an entry for GPIO201 in lahaina pro overlay files. Change-Id: I5311bf9bcd4bd624a46cce2a62ac65551fd76f06 --- qcom/lahaina-cdp-hsp-pro.dtsi | 4 ++++ qcom/lahaina-mtp-hsp-pro.dtsi | 4 ++++ qcom/lahaina-pinctrl.dtsi | 14 ++++++++++++++ qcom/lahaina-qrd-hsp-pro.dtsi | 4 ++++ 4 files changed, 26 insertions(+) diff --git a/qcom/lahaina-cdp-hsp-pro.dtsi b/qcom/lahaina-cdp-hsp-pro.dtsi index fdf9ed586642..e8144ecd531b 100644 --- a/qcom/lahaina-cdp-hsp-pro.dtsi +++ b/qcom/lahaina-cdp-hsp-pro.dtsi @@ -1 +1,5 @@ #include "lahaina-cdp.dtsi" +&bluetooth { + pinctrl-1 = <&wcnss_en_sleep>; + qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ +}; diff --git a/qcom/lahaina-mtp-hsp-pro.dtsi b/qcom/lahaina-mtp-hsp-pro.dtsi index af2a598d00ab..a4949402b4b8 100644 --- a/qcom/lahaina-mtp-hsp-pro.dtsi +++ b/qcom/lahaina-mtp-hsp-pro.dtsi @@ -1 +1,5 @@ #include "lahaina-mtp.dtsi" +&bluetooth { + pinctrl-1 = <&wcnss_en_sleep>; + qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ +}; diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi index 3c81288625d9..242b9485c6eb 100644 --- a/qcom/lahaina-pinctrl.dtsi +++ b/qcom/lahaina-pinctrl.dtsi @@ -13,6 +13,20 @@ }; }; + wcnss_en_sleep: wcnss_en_sleep { + mux { + pins = "gpio201"; + function = "gpio"; + }; + + config { + pins = "gpio201"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + trigout_a: trigout_a { mux { pins = "gpio14"; diff --git a/qcom/lahaina-qrd-hsp-pro.dtsi b/qcom/lahaina-qrd-hsp-pro.dtsi index 74843fc49873..cc529f0f8c8c 100644 --- a/qcom/lahaina-qrd-hsp-pro.dtsi +++ b/qcom/lahaina-qrd-hsp-pro.dtsi @@ -1 +1,5 @@ #include "lahaina-qrd.dtsi" +&bluetooth { + pinctrl-1 = <&wcnss_en_sleep>; + qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ +}; From 669c736845aaaf71c6539d77cd509dd76ab64c46 Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Thu, 3 Dec 2020 11:19:42 -0800 Subject: [PATCH 0683/1809] ARM: dts: msm: Add support for qca6490 xo clk gpio QCA6490 needs XO clock selection gpio for leakage prevention. Add GPIO configuration in cnss device tree node. Change-Id: I827f7335cf5b507c04d286b9bd7e3bcb95c071ed --- bindings/cnss/cnss-wlan.txt | 1 + qcom/lahaina-cdp-hsp-pro.dtsi | 4 ++++ qcom/lahaina-mtp-hsp-pro.dtsi | 4 ++++ qcom/lahaina-qrd-hsp-pro.dtsi | 4 ++++ 4 files changed, 13 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 5a77cba316b3..f9ab0e0b90a4 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -91,6 +91,7 @@ Optional properties: - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO enable to resolve PMU power up issues. Provide BT GPIO using this config param. + - qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention. Example: diff --git a/qcom/lahaina-cdp-hsp-pro.dtsi b/qcom/lahaina-cdp-hsp-pro.dtsi index e8144ecd531b..a2d3fbde299b 100644 --- a/qcom/lahaina-cdp-hsp-pro.dtsi +++ b/qcom/lahaina-cdp-hsp-pro.dtsi @@ -3,3 +3,7 @@ pinctrl-1 = <&wcnss_en_sleep>; qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ }; + +&wlan { + qcom,xo-clk-gpio = <&tlmm 201 0>; +}; diff --git a/qcom/lahaina-mtp-hsp-pro.dtsi b/qcom/lahaina-mtp-hsp-pro.dtsi index a4949402b4b8..391fe755a38c 100644 --- a/qcom/lahaina-mtp-hsp-pro.dtsi +++ b/qcom/lahaina-mtp-hsp-pro.dtsi @@ -3,3 +3,7 @@ pinctrl-1 = <&wcnss_en_sleep>; qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ }; + +&wlan { + qcom,xo-clk-gpio = <&tlmm 201 0>; +}; diff --git a/qcom/lahaina-qrd-hsp-pro.dtsi b/qcom/lahaina-qrd-hsp-pro.dtsi index cc529f0f8c8c..90755d78783b 100644 --- a/qcom/lahaina-qrd-hsp-pro.dtsi +++ b/qcom/lahaina-qrd-hsp-pro.dtsi @@ -3,3 +3,7 @@ pinctrl-1 = <&wcnss_en_sleep>; qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ }; + +&wlan { + qcom,xo-clk-gpio = <&tlmm 201 0>; +}; From e1f01895593785666647401b44cb758f44c89b83 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Sat, 16 Jan 2021 10:54:37 +0530 Subject: [PATCH 0684/1809] ARM: dts: msm: Map more no of redistributors for monaco As GIC is configured with more no of cores, So map all region of available redistributor, change monaco soc id and also correct syntax errors due to merge conflict. Change-Id: I832e4e4de9e74b2cdf9a20d1224f8e9a5f3ab7eb --- qcom/monaco-rumi-overlay.dts | 2 +- qcom/monaco.dtsi | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/qcom/monaco-rumi-overlay.dts b/qcom/monaco-rumi-overlay.dts index 4f3bb6574696..05c56ab9fafa 100644 --- a/qcom/monaco-rumi-overlay.dts +++ b/qcom/monaco-rumi-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Monaco RUMI"; compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; - qcom,msm-id = <459 0x10000>; + qcom,msm-id = <486 0x10000>; qcom,board-id = <15 0>; }; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 61d0400287fc..4d93eb062b7c 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -252,7 +252,7 @@ #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; reg = <0xf200000 0x10000>, /* GICD */ - <0xf300000 0x80000>; /* GICR * 4 */ + <0xf300000 0x100000>; /* GICR * 8 */ interrupts = ; }; @@ -783,7 +783,7 @@ interrupt-controller; #interrupt-cells = <2>; }; - } + }; clk_virt: interconnect { compatible = "qcom,monaco-clk_virt"; @@ -817,6 +817,7 @@ }; #include "monaco-pinctrl.dtsi" +#include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" #include "monaco-gdsc.dtsi" From f4e5232e5233c0cd6ebb74863e1d367b512997ae Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Tue, 1 Dec 2020 17:22:09 +0800 Subject: [PATCH 0685/1809] ARM: dts: msm: Add ion device for sdxnightjar Describe the available ion heaps. Change-Id: Ib6802ad7e58416db766923020aa4bbc2a04aa06d --- qcom/sdxnightjar-ion.dtsi | 15 +++++++++++++++ qcom/sdxnightjar.dtsi | 1 + 2 files changed, 16 insertions(+) create mode 100644 qcom/sdxnightjar-ion.dtsi diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi new file mode 100644 index 000000000000..5eb8ae2d48f1 --- /dev/null +++ b/qcom/sdxnightjar-ion.dtsi @@ -0,0 +1,15 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + }; +}; + diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index de70b9e22d80..58bd2eccccd7 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -983,6 +983,7 @@ #include "sdxnightjar-usb.dtsi" #include "sdxnightjar-coresight.dtsi" #include "sdxnightjar-pinctrl.dtsi" +#include "sdxnightjar-ion.dtsi" #include "sdxnightjar-blsp.dtsi" &i2c_3 { From 97474046111d28d91d24ee679ccbf233ec03cc46 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 18 Jan 2021 13:54:32 +0530 Subject: [PATCH 0686/1809] ARM: dts: msm: Update GPU speed bins for yupik Update the clock plan and speed bin value to support GPU speed bins for Yupik. Change-Id: I2a98bf68738e06710f2d3593d8aed75d18f9ba08 --- qcom/yupik-gpu.dtsi | 342 +++++++++++++++++++++++++++++++++----------- qcom/yupik.dtsi | 5 + 2 files changed, 265 insertions(+), 82 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c60e37b1de6e..21701059f411 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -42,7 +42,6 @@ qcom,chipid = <0x06030500>; qcom,no-nap; - qcom,initial-pwrlevel = <6>; qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; @@ -81,6 +80,9 @@ <0>, /* Off */ <100>; /* On */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + qcom,gpu-mempools { #address-cells = <1>; #size-cells = <0>; @@ -114,109 +116,285 @@ }; }; - /* Power levels */ - qcom,gpu-pwrlevels { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calculated as FMAX/4.8 MHz round up to zero + * decimal places plus two margin to account for + * clock jitters. + */ + qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,gpu-pwrlevels"; + compatible = "qcom,gpu-pwrlevel-bins"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <840000000>; - qcom,level = ; + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <5>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <812000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <10>; - qcom,bus-max-ddr8 = <10>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + }; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <812000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,speed-bin = <172>; + qcom,initial-pwrlevel = <5>; - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <9>; - qcom,bus-max-ddr8 = <10>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <812000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + }; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <700000000>; - qcom,level = ; + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <10>; - qcom,bus-max-ddr7 = <11>; + qcom,speed-bin = <117>; + qcom,initial-pwrlevel = <2>; - qcom,bus-freq-ddr8 = <9>; - qcom,bus-min-ddr8 = <8>; - qcom,bus-max-ddr8 = <10>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + }; }; + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <608000000>; - qcom,level = ; + qcom,speed-bin = <96>; + qcom,initial-pwrlevel = <1>; - qcom,bus-freq-ddr7 = <10>; - qcom,bus-min-ddr7 = <9>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <8>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <10>; - }; + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <550000000>; - qcom,level = ; + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; - qcom,bus-freq-ddr7 = <9>; - qcom,bus-min-ddr7 = <8>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <315000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <6>; - qcom,bus-max-ddr8 = <9>; - }; + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <450000000>; - qcom,level = ; - - qcom,bus-freq-ddr7 = <6>; - qcom,bus-min-ddr7 = <5>; - qcom,bus-max-ddr7 = <10>; - - qcom,bus-freq-ddr8 = <6>; - qcom,bus-min-ddr8 = <6>; - qcom,bus-max-ddr8 = <8>; - }; - - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <315000000>; - qcom,level = ; - - qcom,bus-freq-ddr7 = <3>; - qcom,bus-min-ddr7 = <2>; - qcom,bus-max-ddr7 = <9>; - - qcom,bus-freq-ddr8 = <3>; - qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + }; }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..3c4cd02f661e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3388,6 +3388,11 @@ read-only; ranges; + gpu_speed_bin: gpu_speed_bin@1e9 { + reg = <0x1e9 0x2>; + bits = <5 8>; + }; + feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; From 32fe01d52297d7cd8bf3037cfd83c0cac9caaf29 Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Mon, 18 Jan 2021 17:05:03 +0530 Subject: [PATCH 0687/1809] ARM: dts: msm: Enable smmu for eMMC on shima Enable smmu for eMMC on shima. Change-Id: I4e835c534be91de191a78ece2eb7a11ff047c8f1 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5ddd3ae5c358..1bd9b8c51413 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1768,7 +1768,7 @@ iommus = <&apps_smmu 0xc0 0x0>; dma-coherent; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; interrupts = , ; From 16e982f20195a68464ff6dbb3f9dea7042ce44f1 Mon Sep 17 00:00:00 2001 From: Chandrasekhar Mattaparthy Date: Mon, 18 Jan 2021 20:03:01 +0530 Subject: [PATCH 0688/1809] ARM: dts: msm: Early mount of vendor partition Add support to early mount vendor partition from device tree. This is required so that vendor modules can be loaded during early-init. Change-Id: I7700c1fd600b81f8c4665e8be50237db56713ab6 --- qcom/scuba-iot.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 3ac31cd6c8d9..14fc3b99340f 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -127,6 +127,29 @@ method = "smc"; }; + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = + "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From 095fb43fb49788de7d698c4fcfaaa0a4229c8506 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 25 Aug 2020 12:04:22 +0530 Subject: [PATCH 0689/1809] ARM: dts: msm: Add cmd_db, RSC and PDC devices for sm6150 This change adds three items. 1. cmd_db reserved memory area 2. apps and display RSC devices 3. PDC irqchip device cmd_db and RSC devices are required for communication with AOSS. PDC irqchip is required to wakeup device from deep sleep low power modes. Change-Id: Idae1cf07113978e66300954809e624d7289c7717 --- qcom/sm6150-pinctrl.dtsi | 11 ++++++++++- qcom/sm6150.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi index 71308852030e..bfebee7214a0 100644 --- a/qcom/sm6150-pinctrl.dtsi +++ b/qcom/sm6150-pinctrl.dtsi @@ -3,11 +3,20 @@ compatible = "qcom,sm6150-pinctrl"; reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>; reg-names = "pinctrl", "spi_cfg"; - interrupts = <0 208 0>; + interrupts = , + , + , + , + , + , + , + , + ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; ufs_dev_reset_assert: ufs_dev_reset_assert { config { diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 7cfff14ca003..523b6b482d69 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -362,6 +362,12 @@ reg = <0x0 0x85e00000 0x0 0x140000>; }; + aop_cmd_db: memory@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + sec_apps_mem: sec_apps_region@85fff000 { no-map; reg = <0x0 0x85fff000 0x0 0x1000>; @@ -592,6 +598,15 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm6150-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; @@ -677,6 +692,20 @@ compatible = "qcom,system-pm"; }; }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; }; #include "sm6150-qupv3.dtsi" From fcc0df464c0650a1c9a28ada6c673d410d563dc9 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 25 Aug 2020 12:16:32 +0530 Subject: [PATCH 0690/1809] ARM: dts: msm: Add cpuidle states and stats driver nodes for sm6150 Add LPM cpuidle states and stats driver nodes. Change-Id: Icf184cd3370c76192797b58c2909ca388c3b0bf1 --- qcom/sm6150-pm.dtsi | 174 ++++++++++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 9 +++ 2 files changed, 183 insertions(+) create mode 100644 qcom/sm6150-pm.dtsi diff --git a/qcom/sm6150-pm.dtsi b/qcom/sm6150-pm.dtsi new file mode 100644 index 000000000000..3a4852f6d946 --- /dev/null +++ b/qcom/sm6150-pm.dtsi @@ -0,0 +1,174 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L3"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l3-wfi"; + entry-latency-us = <660>; + exit-latency-us = <600>; + min-residency-us = <1260>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,is-reset; + qcom,min-child-idx = <2>; + }; + + CX_RET: qcom,pm-cluster-level@2 { /* Cx Ret */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + arm,psci-suspend-param = <0x1240>; + qcom,psci-mode = <0x124>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */ + reg = <3>; + compatible = "arm,idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3638>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + arm,psci-suspend-param = <0xb240>; + qcom,psci-mode = <0xb24>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <61>; + exit-latency-us = <60>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU6 &CPU7>; + + GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <55>; + exit-latency-us = <66>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 523b6b482d69..4e19271b626c 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -26,6 +26,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; @@ -63,6 +64,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_100>; @@ -95,6 +97,7 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_200>; @@ -126,6 +129,7 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_300>; @@ -157,6 +161,7 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_400>; @@ -188,6 +193,7 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_500>; @@ -219,6 +225,7 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; cache-size = <0x10000>; next-level-cache = <&L2_600>; @@ -259,6 +266,7 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; cache-size = <0x10000>; next-level-cache = <&L2_700>; @@ -710,3 +718,4 @@ #include "sm6150-qupv3.dtsi" #include "sm6150-pinctrl.dtsi" +#include "sm6150-pm.dtsi" From 2131009e4f31235a4d382394787baaf4767329d9 Mon Sep 17 00:00:00 2001 From: Anil Kumar Kanakanti Date: Thu, 7 Jan 2021 18:12:22 +0530 Subject: [PATCH 0691/1809] ARM: dts: msm: Add yupik camera sensor device tree to Yupik IDP Include camera sensor device tree nodes to enable camera sensor HW on Yupik IDP platform. Change-Id: Ibffd53b7ae0e7208649351379f37d6580a839b71 --- qcom/yupik-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index d0430ce04c84..291879aeb65d 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -329,3 +329,4 @@ &dsi_nt36672e_fhd_plus_144_video>; }; }; +#include "camera/yupik-camera-sensor-idp.dtsi" From 246370ccf78a22c168f7851636bf91ef76e85604 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Tue, 19 Jan 2021 11:10:02 +0530 Subject: [PATCH 0692/1809] ARM: dts: msm: Add pmic dependency back on Yupik This reverts commit 36a0f1c95da5 ("ARM: dts: msm: Remove pmic dependency on Yupik"). This was needed for Bring-up Day 0 as USB has a dependency on ADSP for the role communication, so if role communication fails, USB won't be able to come up in device mode. Now that ADSP is up role communication is taking place hence this change is not needed. Change-Id: I2cb35f8abb146688fbb00fc5872fd9df059989fe --- qcom/yupik-usb.dtsi | 10 +++++++++- qcom/yupik.dtsi | 5 +++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 474485e8348c..67b822bf441d 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -49,6 +49,8 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + usb-role-switch; + extcon = <&eud>; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -73,7 +75,13 @@ snps,ssp-u3-u0-quirk; tx-fifo-resize; maximum-speed = "super-speed"; - dr_mode = "peripheral"; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..dd36d03f8083 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2168,6 +2168,11 @@ qcom,ucsi { compatible = "qcom,ucsi-glink"; + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; }; altmode: qcom,altmode { From 3f7ca5d828aa125c7cf88f2b9651b73e3d88238d Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Mon, 14 Dec 2020 11:38:43 +0530 Subject: [PATCH 0693/1809] ARM: dts: msm: Limit max-frequency for eMMC and SD card Limiting max frequency for eMMC and SD card on kernel v5.4 based devices to avoid lower speed modes running with high clock rates. Change-Id: I91708def607a6a009a760dba5703158b0596ee34 --- qcom/holi.dtsi | 8 ++++++++ qcom/lahaina.dtsi | 4 ++++ qcom/sdxlemur-cdp.dtsi | 4 ++++ qcom/sdxlemur-mtp-mbb-emmc.dtsi | 4 ++++ qcom/sdxlemur-mtp.dtsi | 4 ++++ qcom/sdxlemur-rcm-pcie-ep.dtsi | 4 ++++ qcom/sdxlemur-rcm-rc.dtsi | 4 ++++ qcom/shima.dtsi | 8 ++++++++ qcom/yupik.dtsi | 8 ++++++++ 9 files changed, 48 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 8341ad465c55..61b576e64edb 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2799,6 +2799,10 @@ non-removable; supports-cqe; + no-sd; + no-sdio; + max-frequency = <192000000>; + qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2863,6 +2867,10 @@ iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "bypass"; + no-mmc; + no-sdio; + max-frequency = <202000000>; + qcom,devfreq,freq-table = <50000000 202000000>; status = "disabled"; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 25926f595614..edb825bdb16e 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3238,6 +3238,10 @@ <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; + no-mmc; + no-sdio; + max-frequency = <202000000>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642C 0xA800 0x10 0x2C010800 0x80040868>; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 4f802df82626..92c6a574449f 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -25,6 +25,10 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; + no-mmc; + no-sdio; + max-frequency = <200000000>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 7d4753791231..edaae4eaeac5 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -14,6 +14,10 @@ bus-width = <8>; non-removable; + no-sd; + no-sdio; + max-frequency = <192000000>; + vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 570000>; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 586d9c3fe0dd..ef9a62296e68 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -24,6 +24,10 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; + no-mmc; + no-sdio; + max-frequency = <200000000>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index e61e86ac8459..1ac4e8231be4 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -23,5 +23,9 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; + no-mmc; + no-sdio; + max-frequency = <200000000>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index aab84f4ef1c2..ba8bed5220c2 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -51,6 +51,10 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; + no-mmc; + no-sdio; + max-frequency = <200000000>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5ddd3ae5c358..223fb2320b8c 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1821,6 +1821,10 @@ non-removable; supports-cqe; + no-sd; + no-sdio; + max-frequency = <192000000>; + qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -1886,6 +1890,10 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + no-mmc; + no-sdio; + max-frequency = <202000000>; + qcom,devfreq,freq-table = <50000000 202000000>; status = "disabled"; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..e78d8ec554c2 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2728,6 +2728,10 @@ non-removable; supports-cqe; + no-sd; + no-sdio; + max-frequency = <192000000>; + qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2795,6 +2799,10 @@ qcom,devfreq,freq-table = <50000000 202000000>; + no-mmc; + no-sdio; + max-frequency = <202000000>; + status = "disabled"; qos0 { From 9d84b51d4590fd45d4ff1368af72d53b82f6681b Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 19 Jan 2021 11:54:59 +0530 Subject: [PATCH 0694/1809] ARM: dts: msm: Mark GCC USB30 secondary clocks as protected on YUPIK GCC USB30 secondary clocks are not required on YUPIK, hence mark them as protected and remove support for USB30 secondary GDSC. Change-Id: I80abe0f3c10fee6e63a15027f4bd13208e59a795 --- qcom/yupik.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..95bcc886b2e4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -942,7 +942,14 @@ , , , , , , - , ; + , , + , , + , , + , , + , , + , , + , , + ; #clock-cells = <1>; #reset-cells = <1>; @@ -3739,11 +3746,6 @@ status = "ok"; }; -&gcc_usb30_sec_gdsc { - qcom,support-hw-trigger; - status = "ok"; -}; - &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { status = "ok"; }; From 4686f48654c4337faf7399b3f7503b0807b7259a Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 19 Jan 2021 15:52:51 +0800 Subject: [PATCH 0695/1809] ARM: dts: msm: Disable SDCC TPDMs on shima Disable all SDCC TPDMs on shima first since there is SDCC internal clock issue. Change-Id: Iac18333769fa593a407b10eeed830e728d475c1a --- qcom/shima-coresight.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 90cccf9a0f3b..471a736d4b05 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -1210,6 +1210,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-4"; clocks = <&aopcc QDSS_CLK>; @@ -1372,6 +1373,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-1"; clocks = <&aopcc QDSS_CLK>; @@ -1394,6 +1396,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-2"; clocks = <&aopcc QDSS_CLK>; From 149fd91ae5a88adfceeb3def91ee83a2fb7f0df4 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 15 Jan 2021 11:37:11 +0800 Subject: [PATCH 0696/1809] ARM: dts: msm: Change some coresight component names Change some coresight component names, and make them corresponding to the names on IPCAT. Change-Id: I4e9b18206db6483ded14ca051a1f5cd43ab61474 --- qcom/yupik-coresight.dtsi | 55 +++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 5a75371c6b43..388e63aaa453 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -784,9 +784,9 @@ port@5 { reg = <5>; - tpda_dlct5_in_tpdm_dlct_1: endpoint { + tpda_dlct5_in_tpdm_dl_south: endpoint { remote-endpoint = - <&tpdm_dlct_1_out_tpda_dlct5>; + <&tpdm_dl_south_out_tpda_dlct5>; }; }; @@ -856,17 +856,17 @@ port@18 { reg = <27>; - tpda_dlct5_in_tpdm_dlct5_0: endpoint { + tpda_dlct5_in_tpdm_dlct: endpoint { remote-endpoint = - <&tpdm_dlct5_0_out_tpda_dlct5>; + <&tpdm_dlct_out_tpda_dlct5>; }; }; port@19 { reg = <28>; - tpda_dlct5_in_tpdm_dlct5_1: endpoint { + tpda_dlct5_in_tpdm_ipcc: endpoint { remote-endpoint = - <&tpdm_dlct5_1_out_tpda_dlct5>; + <&tpdm_ipcc_out_tpda_dlct5>; }; }; }; @@ -930,13 +930,13 @@ }; }; - tpdm_dlct_1: tpdm@6c08000 { + tpdm_dl_south: tpdm@6c08000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x6c08000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-dlct_1"; + coresight-name = "coresight-tpdm-dl-south"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -945,9 +945,9 @@ out-ports { port { - tpdm_dlct_1_out_tpda_dlct5: endpoint { + tpdm_dl_south_out_tpda_dlct5: endpoint { remote-endpoint = - <&tpda_dlct5_in_tpdm_dlct_1>; + <&tpda_dlct5_in_tpdm_dl_south>; }; }; }; @@ -1408,13 +1408,13 @@ }; }; - tpdm_dlct5_0: tpdm@6c30000 { + tpdm_dlct: tpdm@6c30000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x06c30000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-dlct5_0"; + coresight-name = "coresight-tpdm-dlct"; status = "disabled"; clocks = <&aopcc QDSS_CLK>; @@ -1424,23 +1424,22 @@ out-ports { port { - tpdm_dlct5_0_out_tpda_dlct5: endpoint { + tpdm_dlct_out_tpda_dlct5: endpoint { remote-endpoint = - <&tpda_dlct5_in_tpdm_dlct5_0>; + <&tpda_dlct5_in_tpdm_dlct>; }; }; }; }; - tpdm_dlct5_1: tpdm@6c31000 { + tpdm_ipcc: tpdm@6c31000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x06c31000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-dlct5_1"; + coresight-name = "coresight-tpdm-ipcc"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -1448,9 +1447,9 @@ out-ports { port { - tpdm_dlct5_1_out_tpda_dlct5: endpoint { + tpdm_ipcc_out_tpda_dlct5: endpoint { remote-endpoint = - <&tpda_dlct5_in_tpdm_dlct5_1>; + <&tpda_dlct5_in_tpdm_ipcc>; }; }; }; @@ -2202,23 +2201,23 @@ }; }; - tpdm_wpss_0: tpdm@6c70000 { + tpdm_wpss: tpdm@6c70000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x6c70000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-wpss-0"; + coresight-name = "coresight-tpdm-wpss"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; out-ports { port { - tpdm_wpss_0_out_funnel_wpss: endpoint { + tpdm_wpss_out_funnel_wpss: endpoint { remote-endpoint = - <&funnel_wpss_in_tpdm_wpss_0>; + <&funnel_wpss_in_tpdm_wpss>; }; }; }; @@ -2257,9 +2256,9 @@ #size-cells = <0>; port@0 { reg = <0>; - funnel_wpss_in_tpdm_wpss_0: endpoint { + funnel_wpss_in_tpdm_wpss: endpoint { remote-endpoint = - <&tpdm_wpss_0_out_funnel_wpss>; + <&tpdm_wpss_out_funnel_wpss>; }; }; @@ -2281,7 +2280,7 @@ funnel_wpss_out_tpda: endpoint { remote-endpoint = <&tpda_in_funnel_wpss>; - source = <&tpdm_wpss_0>; + source = <&tpdm_wpss>; }; }; @@ -2409,13 +2408,13 @@ }; }; - tpdm_dlet: tpdm@6c28000 { + tpdm_dl_east: tpdm@6c28000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x6c28000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-dlet"; + coresight-name = "coresight-tpdm-dl-east"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; From b0beb39c700a71ca017edbf7d8d0488275d201ed Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 19 Jan 2021 16:07:24 +0530 Subject: [PATCH 0697/1809] ARM: dts: msm: Enable forcce-hard-reset option for sdxnightjar Some (PON gen2) platforms still use legacy hard-reset offset [7:2] of the PON_RB_SPARE register. Enable it. Change-Id: Ib2f7118835fd5e8e9cee43b7e6d40c619b40cc54 --- bindings/input/qpnp-power-on.txt | 3 +++ qcom/pmd9650.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt index b1b16685dcb1..b9bb2bfea1ae 100644 --- a/bindings/input/qpnp-power-on.txt +++ b/bindings/input/qpnp-power-on.txt @@ -126,6 +126,9 @@ Optional properties: power off trigger during system shutdown case. - qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD power off trigger during system hard reset case. +- qcom,use-legacy-hard-reset-offset Boolean property to support legacy + hard-reset offset of the PON_RB_SPARE register for + some (PON gen2) platforms. Optional Sub-nodes: - qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features diff --git a/qcom/pmd9650.dtsi b/qcom/pmd9650.dtsi index 83ea13885ee3..23a437cb9494 100644 --- a/qcom/pmd9650.dtsi +++ b/qcom/pmd9650.dtsi @@ -24,6 +24,7 @@ interrupt-names = "kpdpwr"; qcom,system-reset; qcom,store-hard-reset-reason; + qcom,use-legacy-hard-reset-offset; qcom,pon_1 { qcom,pon-type = ; From 371da5c039b1d6f29696175b63ba566f289aa388 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 15 Jan 2021 14:48:28 +0530 Subject: [PATCH 0698/1809] ARM: dts: msm: Add bus voting support for sdxlemur Add bus voting support for eMMC/SD card for sdxlemur. Also add clk scaling support. Change-Id: I1b4e725233dca4350e4834a1fa62c4dbe127a51a --- qcom/sdxlemur.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f9c86274d0e1..be018e3c9f7b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -535,6 +535,22 @@ ; interrupt-names = "hc_irq", "pwr_irq"; + interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "sdhc-ddr"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */ + <273000 210000>, /* 400 KB/s*/ + <273000 210000>, /* 25 MB/s */ + <273000 210000>, /* 50 MB/s */ + <273000 210000>, /* 100 MB/s */ + <1057000 725000>, /* 200 MB/s */ + <2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; @@ -544,6 +560,8 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + qcom,devfreq,freq-table = <50000000 200000000>; + status = "disabled"; qos0 { From 580684a5a933e8641ee5ff0d47b39ce07a3a9dec Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 30 Dec 2020 17:46:03 +0530 Subject: [PATCH 0699/1809] ARM: dts: msm: Add thermal zone entries for pm8195 Add thermal zones for pm8195 and update pm8155 thermal zone entries. Change-Id: I33d777186d8909506393aebadabded06e6be57f3 --- qcom/pm8150.dtsi | 11 +++-- qcom/pm8195.dtsi | 3 -- qcom/sa8155-pmic-overlay.dtsi | 14 +++--- qcom/sa8195-pmic.dtsi | 83 +++++++++++++++++++++++++++++++++++ 4 files changed, 94 insertions(+), 17 deletions(-) diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi index 21683a4ecffb..bde21fc77a93 100644 --- a/qcom/pm8150.dtsi +++ b/qcom/pm8150.dtsi @@ -139,25 +139,24 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150_tz>; - wake-capable-sensor; trips { pm8150_trip0: trip0 { - temperature = <95000>; + temperature = <105000>; hysteresis = <0>; type = "passive"; }; pm8150_trip1: trip1 { - temperature = <115000>; + temperature = <125000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; trip2 { - temperature = <145000>; + temperature = <155000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/qcom/pm8195.dtsi b/qcom/pm8195.dtsi index 08ab33830f0f..99d7e03a84de 100644 --- a/qcom/pm8195.dtsi +++ b/qcom/pm8195.dtsi @@ -24,7 +24,6 @@ io-channels = <&pm8195_1_vadc ADC5_DIE_TEMP>; io-channel-names = "thermal"; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; pm8195_1_vadc: vadc@3100 { @@ -136,7 +135,6 @@ io-channels = <&pm8195_2_vadc ADC5_DIE_TEMP>; io-channel-names = "thermal"; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; pm8195_2_vadc: vadc@3100 { @@ -216,7 +214,6 @@ io-channels = <&pm8195_3_vadc ADC5_DIE_TEMP>; io-channel-names = "thermal"; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; pm8195_3_vadc: vadc@3100 { diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi index 4c4fd12fe728..bcfa20c8d95a 100644 --- a/qcom/sa8155-pmic-overlay.dtsi +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -30,11 +30,10 @@ pm8150_1_gpios: &pm8150_gpios { pm8150_2_tz: qcom,temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; - interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; io-channels = <&pm8150_2_vadc ADC5_DIE_TEMP>; io-channel-names = "thermal"; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; qcom,power-on@800 { @@ -142,25 +141,24 @@ pm8150_1_gpios: &pm8150_gpios { polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150_2_tz>; - wake-capable-sensor; trips { pm8150_2_trip0: trip0 { - temperature = <95000>; + temperature = <105000>; hysteresis = <0>; type = "passive"; }; pm8150_2_trip1: trip1 { - temperature = <115000>; + temperature = <125000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; trip2 { - temperature = <145000>; + temperature = <155000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index 959c0d0ce208..2ec01b703cc4 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -70,3 +70,86 @@ #include "sa8195p-regulator.dtsi" #include "pm8195.dtsi" + +&thermal_zones { + pm8195_1_temp_alarm: pm8195_1_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8195_1_tz>; + + trips { + pm8195_1_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8195_1_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8195_2_temp_alarm: pm8195_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8195_2_tz>; + + trips { + pm8195_2_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8195_2_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8195_3_temp_alarm: pm8195_3_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8195_3_tz>; + + trips { + pm8195_3_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8195_3_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From 80d0275371bcd8e64b8bb4e10c52e91fb83bdc82 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Wed, 20 Jan 2021 17:31:47 +0800 Subject: [PATCH 0700/1809] ARM: dts: msm: Enable dlct tpdm on yupik DLCT tpdm has been validated and enable it on yupik. Change-Id: Iecf88520c84b5bc1a01d4b7ec0945473b4c78f59 --- qcom/yupik-coresight.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 388e63aaa453..c910fe539c8d 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -1416,7 +1416,6 @@ coresight-name = "coresight-tpdm-dlct"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; From b178f62b88625af2a61e5dc713871950b0b0df5b Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 18 Dec 2020 17:57:17 +0530 Subject: [PATCH 0701/1809] ARM: dts: msm: Add necessary changes for CQE enablement on sdxlemur Add necessary changes for CQE enablement: 1) Add gpio based data lines (DAT[4:7]) to pinctrl file 2) Set VI recommended drive strength values for clk, cmd and data lines 3) Add clk scaling device tree support 4) Add CQE device tree flag. Change-Id: I3f616cc73a0cd91029e19ee5160a6c9ba847c0ac --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 4 +++ qcom/sdxlemur-pinctrl.dtsi | 60 +++++++++++++++++++++++++++++++-- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 7d4753791231..d1848edd40a0 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -13,6 +13,7 @@ bus-width = <8>; non-removable; + supports-cqe; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; @@ -24,6 +25,9 @@ qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <0 200000>; + qcom,devfreq,freq-table = <50000000 192000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index d336e3fa3eb4..d638723e2a75 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -50,13 +50,41 @@ cmd { pins = "sdc1_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; }; data { pins = "sdc1_data"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; + }; + + data_4 { + pins = "gpio98"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + + data_5 { + pins = "gpio99"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + + data_6 { + pins = "gpio100"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + + data_7 { + pins = "gpio101"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; }; }; @@ -78,6 +106,34 @@ bias-pull-up; drive-strength = <2>; }; + + data_4 { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + data_5 { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + data_6 { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + data_7 { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; sdc2_on: sdc2_on { From 6f5463b379607f8cf4a024d60449405738f1c052 Mon Sep 17 00:00:00 2001 From: Siva Kumar Akkireddi Date: Wed, 23 Dec 2020 01:21:43 +0530 Subject: [PATCH 0702/1809] ARM: dts: msm: Enable PCIe RC on sdxnightjar Add devicetree node to enable PCIe Root Complex on sdxnightjar. Change-Id: I95d155d9ffa9a4fe8c690b18fa8e4beaf94695f9 --- qcom/sdxnightjar-pcie.dtsi | 159 +++++++++++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 1 + 2 files changed, 160 insertions(+) create mode 100644 qcom/sdxnightjar-pcie.dtsi diff --git a/qcom/sdxnightjar-pcie.dtsi b/qcom/sdxnightjar-pcie.dtsi new file mode 100644 index 000000000000..e24376cf48c2 --- /dev/null +++ b/qcom/sdxnightjar-pcie.dtsi @@ -0,0 +1,159 @@ +&soc { + pcie0: qcom,pcie@80000 { + compatible = "qcom,pci-msm"; + + reg = <0x80000 0x2000>, + <0x86000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40100000 0x100000>, + <0x01956044 0x4>; + reg-names = "parf", "phy", "dm_core", "elbi", "conf", "tcsr"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm_pinmux 60 0>; + wake-gpio = <&tlmm_pinmux 61 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1p8-supply = <&pmd9650_l5>; + vreg-0p9-supply = <&pmd9650_l4>; + + qcom,vreg-0.9-voltage-level = <928000 928000 24000>; + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE &bimc SLAVE_EBI_CH0>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_AXI_MSTR_CLK>, + <&gcc GCC_PCIE_AXI_CLK>, + <&gcc GCC_PCIE_REF_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, + <0>, <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIEPHY_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_phy_reset"; + + qcom,aux-clk-freq = <0x14>; + qcom,ep-latency = <10>; + qcom,boot-option = <0x1>; + qcom,pcie-phy-ver = <0x10>; + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,phy-sequence = <0x800 0x01 0x0 + 0x804 0x03 0x0 + 0x034 0x18 0x0 + 0x038 0x10 0x0 + 0x294 0x06 0x0 + 0x0c8 0x01 0x0 + 0x128 0x00 0x0 + 0x144 0xff 0x0 + 0x148 0x1f 0x0 + 0x070 0x0f 0x0 + 0x048 0x0f 0x0 + 0x178 0x00 0x0 + 0x19c 0x01 0x0 + 0x18c 0x20 0x0 + 0x184 0x0a 0x0 + 0x00c 0x09 0x0 + 0x0ac 0x04 0x0 + 0x0d0 0x82 0x0 + 0x0e4 0x03 0x0 + 0x0e0 0x55 0x0 + 0x0dc 0x55 0x0 + 0x054 0x00 0x0 + 0x050 0x0d 0x0 + 0x04c 0x04 0x0 + 0x174 0x33 0x0 + 0x03c 0x02 0x0 + 0x040 0x1f 0x0 + 0x078 0x0b 0x0 + 0x084 0x16 0x0 + 0x090 0x28 0x0 + 0x10c 0x00 0x0 + 0x108 0x80 0x0 + 0x010 0x01 0x0 + 0x01c 0x31 0x0 + 0x020 0x01 0x0 + 0x014 0x02 0x0 + 0x018 0x00 0x0 + 0x024 0x2f 0x0 + 0x028 0x19 0x0 + 0x268 0x45 0x0 + 0x194 0x06 0x0 + 0x254 0x02 0x0 + 0x2ac 0x12 0x0 + 0x510 0x1c 0x0 + 0x51c 0x14 0x0 + 0x4d8 0x01 0x0 + 0x4dc 0x00 0x0 + 0x4e0 0xdb 0x0 + 0x448 0x4b 0x0 + 0x41c 0x04 0x0 + 0x410 0x04 0x0 + 0x074 0x19 0x0 + 0x854 0x04 0x0 + 0x9ac 0x00 0x0 + 0x8a0 0x40 0x0 + 0x9e0 0x00 0x0 + 0x9dc 0x40 0x0 + 0x9a8 0x00 0x0 + 0x8a4 0x40 0x0 + 0x8a8 0x73 0x0 + 0x518 0x99 0x0 + 0x824 0x15 0x0 + 0x828 0x0e 0x0 + 0x9b0 0x07 0x0 + 0x800 0x00 0x0 + 0x808 0x03 0x0>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index de70b9e22d80..fc6a9ccda1f0 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -984,6 +984,7 @@ #include "sdxnightjar-coresight.dtsi" #include "sdxnightjar-pinctrl.dtsi" #include "sdxnightjar-blsp.dtsi" +#include "sdxnightjar-pcie.dtsi" &i2c_3 { status = "ok"; From f86c0a00c6602167f966ebe7bce506dd0c0f4529 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Tue, 17 Nov 2020 18:20:45 +0530 Subject: [PATCH 0703/1809] ARM: dts: msm: Add i2c, spi, uart dtsi nodes for monaco Add i2c, spi, uart, common driver and gsi dtsi nodes for monaco. Change-Id: If1ce82a647e4302f0162b1c17507721c19157da9 --- qcom/monaco-pinctrl.dtsi | 738 +++++++++++++++++++++++++++++++++++++++ qcom/monaco-qupv3.dtsi | 481 +++++++++++++++++++++++++ qcom/monaco.dtsi | 10 + 3 files changed, 1229 insertions(+) create mode 100644 qcom/monaco-qupv3.dtsi diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 0008896c79a9..f98e24512fec 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -7,5 +7,743 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qupv3_se6_2uart_pins: qupv3_se6_2uart_pins { + qupv3_se6_2uart_active: qupv3_se6_2uart_active { + mux { + pins = "gpio30", "gpio31"; + function = "qup06"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup00"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup00"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio10", "gpio11"; + function = "qup01"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + function = "qup01"; + }; + + config { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup03"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "qup03"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup04"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup04"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio26", "gpio27"; + function = "qup05"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "qup05"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio30", "gpio31"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins_a: qupv3_se7_i2c_pins_a { + qupv3_se7_i2c_active_L0_a: qupv3_se7_i2c_active_L0_a { + mux { + pins = "gpio101"; + function = "QUP0_L0"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-pull-up; + }; + + }; + + qupv3_se7_i2c_active_L1_a: qupv3_se7_i2c_active_L1_a { + mux { + pins = "gpio102"; + function = "QUP0_L1"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep_a: qupv3_se7_i2c_sleep_a { + mux { + pins = "gpio101", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio101", "gpio102"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins_a: qupv3_se7_spi_pins_a { + qupv3_se7_spi_active_L0_a: qupv3_se7_spi_active_L0_a { + mux { + pins = "gpio101"; + function = "QUP0_L0"; + }; + + config { + pins = "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L1_a: qupv3_se7_spi_active_L1_a { + mux { + pins = "gpio102"; + function = "QUP0_L1"; + }; + + config { + pins = "gpio102"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L2_a: qupv3_se7_spi_active_L2_a { + mux { + pins = "gpio104"; + function = "QUP0_L2"; + }; + + config { + pins = "gpio104"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L3_a: qupv3_se7_spi_active_L3_a { + mux { + pins = "gpio105"; + function = "QUP0_L3"; + }; + + config { + pins = "gpio105"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep_a: qupv3_se7_spi_sleep_a { + mux { + pins = "gpio101", "gpio102", + "gpio104", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio101", "gpio102", + "gpio104", "gpio105"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins_b: qupv3_se7_i2c_pins_b { + qupv3_se7_i2c_active_L0_b: qupv3_se7_i2c_active_L0_b { + mux { + pins = "gpio104"; + function = "QUP0_L0"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + + }; + + qupv3_se7_i2c_active_L1_b: qupv3_se7_i2c_active_L1_b { + mux { + pins = "gpio105"; + function = "QUP0_L1"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep_b: qupv3_se7_i2c_sleep_b { + mux { + pins = "gpio104", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio104", "gpio105"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins_b: qupv3_se7_spi_pins_b { + qupv3_se7_spi_active_L0_b: qupv3_se7_spi_active_L0_b { + mux { + pins = "gpio104"; + function = "QUP0_L0"; + }; + + config { + pins = "gpio104"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L1_b: qupv3_se7_spi_active_L1_b { + mux { + pins = "gpio105"; + function = "QUP0_L1"; + }; + + config { + pins = "gpio105"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L2_b: qupv3_se7_spi_active_L2_b { + mux { + pins = "gpio101"; + function = "QUP0_L2"; + }; + + config { + pins = "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_active_L3_b: qupv3_se7_spi_active_L3_b { + mux { + pins = "gpio102"; + function = "QUP0_L3"; + }; + + config { + pins = "gpio102"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep_b: qupv3_se7_spi_sleep_b { + mux { + pins = "gpio104", "gpio105", + "gpio101", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio104", "gpio105", + "gpio101", "gpio102"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_4uart_pins: qupv3_se5_4uart_pins { + qupv3_se5_default_ctsrtsrx: + qupv3_se5_default_ctsrtsrx { + mux { + pins = "gpio26", "gpio27", "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", "gpio79"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_default_tx: qupv3_se5_default_tx { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_ctsrx: qupv3_se5_ctsrx { + mux { + pins = "gpio26", "gpio79"; + function = "qup05"; + }; + + config { + pins = "gpio26", "gpio79"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_rts: qupv3_se5_rts { + mux { + pins = "gpio27"; + function = "qup05"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_tx: qupv3_se5_tx { + mux { + pins = "gpio28"; + function = "qup05"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; }; }; diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi new file mode 100644 index 000000000000..2c249245c30b --- /dev/null +++ b/qcom/monaco-qupv3.dtsi @@ -0,0 +1,481 @@ +#include + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4ac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok" + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xf>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se6_2uart: qcom,qup_uart@4a98000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4a98000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_2uart_active>; + pinctrl-1 = <&qupv3_se6_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@4a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@4a8c000 { + compatible = "qcom,spi-geni"; + reg = <0x4a8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@4a90000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@4a90000 { + compatible = "qcom,spi-geni"; + reg = <0x4a90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@4a94000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@4a98000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@4a98000 { + compatible = "qcom,spi-geni"; + reg = <0x4a98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c_a: i2c@4a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active_L0_a + &qupv3_se7_i2c_active_L1_a>; + pinctrl-1 = <&qupv3_se7_i2c_sleep_a>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi_a: spi@4a9c000 { + compatible = "qcom,spi-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active_L0_a + &qupv3_se7_spi_active_L1_a &qupv3_se7_spi_active_L2_a + &qupv3_se7_spi_active_L3_a>; + pinctrl-1 = <&qupv3_se7_spi_sleep_a>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <75000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c_b: i2c@4a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active_L0_b + &qupv3_se7_i2c_active_L1_b>; + pinctrl-1 = <&qupv3_se7_i2c_sleep_b>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi_b: spi@4a9c000 { + compatible = "qcom,spi-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active_L0_b + &qupv3_se7_spi_active_L1_b &qupv3_se7_spi_active_L2_b + &qupv3_se7_spi_active_L3_b>; + pinctrl-1 = <&qupv3_se7_spi_sleep_b>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <75000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se5_4uart: qcom,qup_uart@4a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a94000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 29 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se5_default_ctsrtsrx>, + <&qupv3_se5_default_tx>; + pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>, + <&qupv3_se5_tx>; + pinctrl-2 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>, + <&qupv3_se5_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4d93eb062b7c..3742aa953dc7 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -17,6 +17,11 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + aliases { + serial0 = &qupv3_se6_2uart; + hsuart0 = &qupv3_se5_4uart; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -820,6 +825,11 @@ #include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" #include "monaco-gdsc.dtsi" +#include "monaco-qupv3.dtsi" + +&qupv3_se6_2uart { + status = "ok"; +}; &gcc_camss_top_gdsc { status = "ok"; From 01b52919ddd739974810849c3558c301a9d89753 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 15 Jan 2021 12:08:21 +0800 Subject: [PATCH 0704/1809] ARM: dts: msm: include display qrd nodes for yupik qrd This change includes display qrd file into yupik final qrd file. Change-Id: I335bd4334ead853f67607fbb71571fcbe0840193 --- qcom/yupik-qrd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 6ef06157b5ad..10ff47a51cdb 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -5,6 +5,7 @@ #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" #include "yupik-thermal-overlay-qrd.dtsi" +#include "display/yupik-sde-display-qrd.dtsi" &soc { gpio_keys { @@ -279,6 +280,10 @@ }; }; +&pm8350c_l12 { + qcom,init-voltage = <1800000>; +}; + &spmi_debug_bus { status = "ok"; }; From a39a4067aadfb1df240920d5df8ca42e1fab6796 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 20 Jan 2021 15:23:40 +0530 Subject: [PATCH 0705/1809] ARM: dts: msm: Add vreg.sp and gpio.sp resources for lahaina Add vreg.sp and gpio.sp resources for lahaina as RPMh XOB regulators to allow clients to vote for them. Change-Id: I0ebeb29270e2c1de90d179c065a07007815f4e27 --- qcom/lahaina-regulators.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/lahaina-regulators.dtsi b/qcom/lahaina-regulators.dtsi index 1f82a2472b4b..c85eba7a1371 100644 --- a/qcom/lahaina-regulators.dtsi +++ b/qcom/lahaina-regulators.dtsi @@ -969,6 +969,24 @@ qcom,init-mode = ; }; }; + + rpmh-regulator-vregsp { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "vreg.sp"; + spss_vreg: regulator-spss-vreg { + regulator-name = "spss_vreg"; + qcom,set = ; + }; + }; + + rpmh-regulator-gpiosp { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "gpio.sp"; + spss_gpio_vreg: regulator-spss-gpio-vreg { + regulator-name = "spss_gpio_vreg"; + qcom,set = ; + }; + }; }; &soc { From b4b5a065ed61f638f15c95fbe2013b6f1f908898 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Mon, 11 Jan 2021 15:31:41 +0800 Subject: [PATCH 0706/1809] ARM: dts: qcom: Add SPI touch node for QRD yupik Add touch node for QRD Yupik device. Change-Id: Ic3cbdded46a2ccc63ca599069a1b91f2a60de0e7 --- qcom/yupik-qrd.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 10ff47a51cdb..a8da2f964778 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -525,3 +525,34 @@ status = "ok"; }; + +&qupv3_se13_i2c { + status = "disabled"; +}; + +&qupv3_se13_spi { + status = "ok"; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + compatible = "focaltech,fts_ts"; + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <81 0x2008>; + focaltech,reset-gpio = <&tlmm 105 0x00>; + focaltech,irq-gpio = <&tlmm 81 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + + vdd-supply = <&L3C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy>; + }; + +}; From db14dadca53307d4e7f8afa251dfe97bf6556cd6 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 17 Jan 2021 11:28:31 +0530 Subject: [PATCH 0707/1809] ARM: dts: msm: Add Display and Touch support on yupik atp Add display and touch support on yupik atp platform. Change-Id: I306f6993d39049813a1a184b2b6ef32613704596 --- qcom/yupik-atp.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 9678e7ce7b0a..45631c00e0c6 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -4,6 +4,7 @@ #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" #include "yupik-thermal-overlay-qrd.dtsi" +#include "display/yupik-sde-display-qrd.dtsi" &soc { gpio_keys { @@ -399,3 +400,28 @@ <&bolero>; }; +&qupv3_se13_spi { + status = "ok"; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + compatible = "focaltech,fts_ts"; + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <81 0x2008>; + focaltech,reset-gpio = <&tlmm 105 0x00>; + focaltech,irq-gpio = <&tlmm 81 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + + vdd-supply = <&L3C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy>; + }; +}; From 3e59222b670d73516c8ca47df90286eed544d391 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 18 Aug 2020 16:44:16 +0530 Subject: [PATCH 0708/1809] ARM: dts: msm: Add devfreq device nodes for SM8150 Add bw_hwmon, memlat and compute devfreq device nodes along with other dependent nodes for SM8150. Change-Id: I106af39a7dc8199101931ed4d9d0a3eb404f6006 --- qcom/sm8150.dtsi | 269 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 269 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fe7a0251dfd2..288adf57c10f 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -16,6 +16,12 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + / { model = "Qualcomm Technologies, Inc. SM8150"; compatible = "qcom,sm8150"; @@ -721,6 +727,269 @@ }; }; + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 200, 16); /* 3051 MB/s */ + BW_OPP_ENTRY( 403, 16); /* 6149 MB/s */ + BW_OPP_ENTRY( 533, 16); /* 8132 MB/s */ + BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */ + BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 200, 4, 0x80); /* 762 MB/s */ + BW_OPP_ENTRY_DDR( 300, 4, 0x80); /* 1144 MB/s */ + BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */ + BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */ + BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */ + BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */ + BW_OPP_ENTRY_DDR(1017, 4, 0x80); /* 3879 MB/s */ + BW_OPP_ENTRY_DDR(1296, 4, 0x80); /* 4943 MB/s */ + BW_OPP_ENTRY_DDR(1555, 4, 0x80); /* 5931 MB/s */ + BW_OPP_ENTRY_DDR(1804, 4, 0x80); /* 6881 MB/s */ + BW_OPP_ENTRY_DDR(2092, 4, 0x80); /* 7980 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER0>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 480000 403200000 >, + < 672000 480000000 >, + < 768000 576000000 >, + < 864000 672000000 >, + < 979200 768000000 >, + < 1075200 864000000 >, + < 1267200 960000000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 768000 MHZ_TO_MBPS(200, 16) >, + < 1075200 MHZ_TO_MBPS(403, 16) >, + < 1267200 MHZ_TO_MBPS(403, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1075200 MHZ_TO_MBPS( 547, 4) >, + < 1267200 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER1>; + }; + + cpu4_cpu_l3_tbl: qcom,cpu4_cpu_l3_tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 768000 576000000 >, + < 1152000 768000000 >, + < 1344000 960000000 >, + < 1689600 1228800000 >, + < 2016000 1344000000 >; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER2>; + }; + + cpu7_cpu_l3_tbl: qcom,cpu7_cpu_l3_tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 768000 576000000 >, + < 1152000 768000000 >, + < 1344000 960000000 >, + < 1689600 1228800000 >, + < 2016000 1344000000 >; + }; + + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu7_cpu_l3_tbl>; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 768000 MHZ_TO_MBPS(403, 16) >, + < 960000 MHZ_TO_MBPS(403, 16) >, + < 1248000 MHZ_TO_MBPS(533, 16) >, + < 1728000 MHZ_TO_MBPS(666, 16) >, + < 2016000 MHZ_TO_MBPS(777, 16) >; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 768000 MHZ_TO_MBPS( 547, 4) >, + < 960000 MHZ_TO_MBPS( 768, 4) >, + < 1248000 MHZ_TO_MBPS(1017, 4) >, + < 1728000 MHZ_TO_MBPS(1555, 4) >, + < 2016000 MHZ_TO_MBPS(1804, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1593600 MHZ_TO_MBPS( 200, 4) >, + < 2016000 MHZ_TO_MBPS(1017, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From c3cd57581fdbef840f576b228d0276cf257d8100 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Fri, 22 Jan 2021 09:17:46 +0800 Subject: [PATCH 0709/1809] ARM: dts: msm: update widget name for Lahaina HHG device Update widget name for Lahaina HHG device. Change-Id: If0d17f616be72646248aa480f094f66a3723e00b --- qcom/lahaina-hhg.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 833d8fd0c2fb..2250733aa9e8 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -19,7 +19,7 @@ "TX DMIC2", "Digital Mic2", "Digital Mic2", "MIC BIAS3", "IN1_HPHL", "HPHL_OUT", - "IN2_HPHL", "HPHR_OUT", + "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", "HAP_IN", "PCM_OUT", "WSA SRC0_INP", "SRC0", From ffb26ccd6c7382c117e1f351624af1a2d18a6419 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 18 Jan 2021 17:05:15 +0800 Subject: [PATCH 0710/1809] ARM: dts: msm: Add hab and peripherals for sa8155 vm Add hab, pinctrl, qup, sdhci, usb and pcie for sa8155 virtual machine. Change-Id: I16d85f1d18f0e48fa76859f7fdc7092cc448ae13 --- qcom/quin-vm-common.dtsi | 97 ++++++++++- qcom/sa8155-vm-la.dtsi | 24 +++ qcom/sa8155-vm-lv-mt.dtsi | 24 +++ qcom/sa8155-vm-lv.dtsi | 24 +++ qcom/sa8155-vm-pcie.dtsi | 272 +++++++++++++++++++++++++++++ qcom/sa8155-vm-usb.dtsi | 351 ++++++++++++++++++++++++++++++++++++++ qcom/sa8155-vm.dtsi | 127 +++++++++++++- 7 files changed, 913 insertions(+), 6 deletions(-) create mode 100644 qcom/sa8155-vm-pcie.dtsi create mode 100644 qcom/sa8155-vm-usb.dtsi diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index a8993b0c00a1..2f1643b12a3d 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -21,7 +21,7 @@ ranges; /* global autoconfigured region for contiguous allocations */ - linux,cma { + linux_cma: linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; @@ -50,24 +50,34 @@ firmware: firmware { android { compatible = "android,firmware"; + boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk"; + vbmeta { compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; + parts = "vbmeta,system,vendor"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait"; + fsmgr_flags = "wait,avb"; status = "ok"; }; }; }; }; + + vdevs { + compatible = "simple-bus"; + virtio_input_keyboard@1c150000 { + compatible = "virtio,mmio"; + virtio,wakeup; + }; + }; }; &soc { @@ -115,7 +125,7 @@ system_heap: qcom,ion-heap@25 { reg = ; - qcom,ion-heap-type = "SYSTEM"; + qcom,ion-heap-type = "MSM_SYSTEM"; }; qcom,ion-heap@27 { /* QSEECOM HEAP */ @@ -131,6 +141,83 @@ }; }; + hab: qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmidgrp100: mmidgrp100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp200: mmidgrp200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp300: mmidgrp300 { + grp-start-id = <300>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp400: mmidgrp400 { + grp-start-id = <400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp500: mmidgrp500 { + grp-start-id = <500>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp600: mmidgrp600 { + grp-start-id = <600>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp700: mmidgrp700 { + grp-start-id = <700>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp800: mmidgrp800 { + grp-start-id = <800>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp900: mmidgrp900 { + grp-start-id = <900>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1000: mmidgrp1000 { + grp-start-id = <1000>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1100: mmidgrp1100 { + grp-start-id = <1100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1200: mmidgrp1200 { + grp-start-id = <1200>; + role = "fe"; + remote-vmids = <0>; + }; + }; + qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x14680000 0x1000>; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index c38dc4de64e2..ee0d8a882248 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -4,3 +4,27 @@ label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sdhc_2 { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-lv-mt.dtsi b/qcom/sa8155-vm-lv-mt.dtsi index 63e1d6eabba3..509403ae2ea3 100644 --- a/qcom/sa8155-vm-lv-mt.dtsi +++ b/qcom/sa8155-vm-lv-mt.dtsi @@ -1,6 +1,30 @@ +&hab { + vmid = <3>; +}; + &reserved_memory { pmem_shared: pmem_shared_region { reg = <0x1 0x2c200000 0x0 0x53e00000>; label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-lv.dtsi b/qcom/sa8155-vm-lv.dtsi index c38dc4de64e2..e1c40cd0133b 100644 --- a/qcom/sa8155-vm-lv.dtsi +++ b/qcom/sa8155-vm-lv.dtsi @@ -1,6 +1,30 @@ +&hab { + vmid = <3>; +}; + &reserved_memory { pmem_shared: pmem_shared_region { reg = <0x1 0x6a500000 0x0 0x51400000>; label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-pcie.dtsi b/qcom/sa8155-vm-pcie.dtsi new file mode 100644 index 000000000000..9f935edf9c43 --- /dev/null +++ b/qcom/sa8155-vm-pcie.dtsi @@ -0,0 +1,272 @@ +#include +#include + + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8150_2_l8>; + vreg-0p9-supply = <&pm8150_2_l18>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = ; + + qcom,no-l0s-supported; + msi-parent = <&pcie0_msi>; + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + qcom,core-preset = <0x77777777>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + +}; diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi new file mode 100644 index 000000000000..bab658611352 --- /dev/null +++ b/qcom/sa8155-vm-usb.dtsi @@ -0,0 +1,351 @@ +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "bypass"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + qcom,ignore-wakeup-src-in-hostmode; + + status = "disabled"; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + status = "disabled"; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en1_default>; + + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,ssp-u3-u0-quirk; + snps,usb3-u1u2-disable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; + + status = "disabled"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l8>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; +}; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 6c89f083c055..f4092adea4aa 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,5 +1,7 @@ #include +#include #include +#include #include #include #include "quin-vm-common.dtsi" @@ -8,10 +10,24 @@ model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; qcom,msm-name = "SA8155 V2"; qcom,msm-id = <362 0x20000>; + + aliases { + hsuart0 = &qupv3_se13_4uart; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; }; - &soc { + VDD_CX_LEVEL: VDD_MMCX_LEVEL: + S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s9_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -107,6 +123,80 @@ , ; }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>, <100000 100000>, + /* 50 MB/s */ + <130718 200000>, <133320 133320>, + /* 100 MB/s */ + <261438 200000>, <150000 150000>, + /* 200 MB/s */ + <261438 400000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 201500000>; + + vdd-supply = <&pm8150_1_l17>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150_2_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + broken-cd; + qcom,nonhotplug; + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <44>; + }; + + qos1 { + mask = <0xc0>; + vote = <44>; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 6>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; }; ®ulator { @@ -194,3 +284,38 @@ regulator-max-microvolt = <2040000>; }; }; + +#include "sm8150-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8155-vm-usb.dtsi" +#include "sa8155-vm-pcie.dtsi" +#include "sm8150-qupv3.dtsi" +#include "sm8150-ssc-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_2 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_3 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; From e04a574cc52c1cec35471806edc959e937d50553 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 26 Aug 2020 14:13:30 +0530 Subject: [PATCH 0711/1809] dt-bindings: interconnect: add interconnect bindings for sm6150 Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices for sm6150. Change-Id: I311b895a0356def9cc344264fe30b655e2f55117 --- bindings/interconnect/qcom,sm6150.txt | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 bindings/interconnect/qcom,sm6150.txt diff --git a/bindings/interconnect/qcom,sm6150.txt b/bindings/interconnect/qcom,sm6150.txt new file mode 100644 index 000000000000..dabfa5847d57 --- /dev/null +++ b/bindings/interconnect/qcom,sm6150.txt @@ -0,0 +1,29 @@ +Qualcomm Technologies, Inc. SM6150 Network-On-Chip interconnect driver binding +------------------------------------------------------------------------------ + +SM6150 interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sm6150-aggre1_noc"; + "qcom,sm6150-camnoc_virt"; + "qcom,sm6150-config_noc"; + "qcom,sm6150-dc_noc"; + "qcom,sm6150-gem_noc"; + "qcom,sm6150-ipa_virt"; + "qcom,sm6150-mc_virt"; + "qcom,sm6150-mmss_noc"; + "qcom,sm6150-system_noc"; +- #interconnect-cells : should contain 1 + +Examples: + +aggre1_noc: interconnect@1700000 { + compatible = "qcom,sm6150-aggre1_noc"; + interconnect-cells = <1>; +}; From a2098239b47b00e333498cb861a1c695537c2bb9 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Fri, 22 Jan 2021 14:24:02 +0530 Subject: [PATCH 0712/1809] ARM: dts: msm: Update GPU FMAX for yupik GPU As per new recommendation, GPU FMAX is 802 Mhz when ACD is disabled. Change-Id: Ie026be05f0714632658caa644982b5241d11f298 --- qcom/yupik-gpu.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 21701059f411..b7d17cf7b23a 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -137,7 +137,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <812000000>; + qcom,gpu-freq = <802000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; @@ -224,12 +224,13 @@ #address-cells = <1>; #size-cells = <0>; + /* Keeping speed bin for FMAX 812 */ qcom,speed-bin = <172>; qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <812000000>; + qcom,gpu-freq = <802000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; From 1c1e8d07d5568493c5811fb27206cc7909689f4d Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 22 Jan 2021 17:15:30 +0530 Subject: [PATCH 0713/1809] ARM: dts: msm: Enable L3 interconnect driver for Yupik Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: Id8a4e0680b6ea5e9f30a79d0126672922e698c1c --- qcom/yupik.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 88089101f67b..7fd298c90f76 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1476,7 +1476,6 @@ clock-names = "xo", "alternate"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - status = "disabled"; }; llcc_pmu: llcc-pmu@9095000 { From 54f529a317c990b516f099cd1bb6acaa866713b1 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 22 Jan 2021 19:43:27 +0530 Subject: [PATCH 0714/1809] ARM: dts: qcom: add sde-rsc-rpmh driver to disp_rsc node Add sde rsc rpmhdriver as a child of display RSC. Change-Id: I3b0c3084b0632ac3b7290b2ca1f9dff7d5e78710 --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..84cf3e91f403 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2083,6 +2083,11 @@ compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; }; + + sde_rsc_rpmh { + compatible = "qcom,sde-rsc-rpmh"; + cell-index = <0>; + }; }; spmi_bus: qcom,spmi@c440000 { From 36bb70246751507628fa7d121646ba07c3079ef2 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 4 Jan 2021 20:01:22 +0530 Subject: [PATCH 0715/1809] ARM: dts: msm: Enable wcn bt for yupik Enable wcn bt for yupik. Change-Id: I5881d750698bfbfe8c8dc33bcef880238e184585 --- qcom/yupik-audio.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-audio.dtsi b/qcom/yupik-audio.dtsi index 7092fd185013..be6ee9166221 100644 --- a/qcom/yupik-audio.dtsi +++ b/qcom/yupik-audio.dtsi @@ -161,7 +161,7 @@ compatible = "qcom,lahaina-asoc-snd"; qcom,mi2s-audio-intf = <1>; qcom,auxpcm-audio-intf = <1>; - qcom,wcn-bt = <0>; + qcom,wcn-bt = <1>; qcom,ext-disp-audio-rx = <0>; qcom,afe-rxtx-lb = <0>; From b9cac2bd53ae1e5913ff8b2596a81102cfd06d9b Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Thu, 21 Jan 2021 17:50:02 +0530 Subject: [PATCH 0716/1809] ARM: dts: msm: Add alias for serial device to ensure proper enumeration Add alias for serial device to ensure expected enumeration. Change-Id: Iee392cea27a2f8d48a11879bd955e9b50438a663 --- qcom/yupik.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a8247121452b..abcb2b782da8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -47,6 +47,8 @@ ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ sdhc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &qupv3_se5_2uart; + hsuart0 = &qupv3_se7_4uart; swr0 = &swr0; swr1 = &swr1; swr2 = &swr2; From bc3e866333cde789487f222ccbdc98fb9e6b3153 Mon Sep 17 00:00:00 2001 From: Ajay Prathi Date: Fri, 8 Jan 2021 16:39:36 +0530 Subject: [PATCH 0717/1809] ARM: dts: msm: Add SPS node for Yupik Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for Yupik. Change-Id: I13cef804d7df2b94cca7d2b0950e598df3794a00 --- qcom/yupik.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index abcb2b782da8..a5ea5979c4b1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3739,6 +3739,12 @@ qcom,iommu-group = <>; }; }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + }; #include "shima-gdsc.dtsi" From f3f32a0a4f9c9d41974d803961cb4cf6f8394715 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Sat, 23 Jan 2021 19:45:01 +0530 Subject: [PATCH 0718/1809] ARM: dts: msm: update cpu core frequency corners in mapping table Update the gold core frequency corners used in memlat and compute mapping tables with the updated corner values in yupik target. Change-Id: I4593cb637c019653e6b3c4a26da281499162d04d --- qcom/yupik.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..4f5bd609af32 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1919,7 +1919,7 @@ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,cachemiss-ev = <0x2A>; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 300, 16) >, + < 691200 MHZ_TO_MBPS( 300, 16) >, < 940800 MHZ_TO_MBPS( 466, 16) >, < 1228800 MHZ_TO_MBPS( 600, 16) >, < 1651200 MHZ_TO_MBPS( 806, 16) >, @@ -1935,10 +1935,10 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 451, 4) >, + < 691200 MHZ_TO_MBPS( 451, 4) >, < 940800 MHZ_TO_MBPS( 547, 4) >, < 1228800 MHZ_TO_MBPS(1017, 4) >, - < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, < 2380800 MHZ_TO_MBPS(1708, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; }; @@ -1946,10 +1946,10 @@ ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 451, 4) >, + < 691200 MHZ_TO_MBPS( 451, 4) >, < 940800 MHZ_TO_MBPS( 547, 4) >, < 1228800 MHZ_TO_MBPS( 768, 4) >, - < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, < 1900800 MHZ_TO_MBPS(1708, 4) >, < 2380800 MHZ_TO_MBPS(2092, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; @@ -1963,10 +1963,10 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 451, 4) >, + < 691200 MHZ_TO_MBPS( 451, 4) >, < 1228800 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651800 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1017, 4) >, < 1900800 MHZ_TO_MBPS(1555, 4) >, < 2400000 MHZ_TO_MBPS(1708, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; @@ -1975,10 +1975,10 @@ ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 451, 4) >, + < 691200 MHZ_TO_MBPS( 451, 4) >, < 1228800 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651800 MHZ_TO_MBPS(1555, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, < 1900800 MHZ_TO_MBPS(1708, 4) >, < 2400000 MHZ_TO_MBPS(2092, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; From 1457b48d4688c7be659107055fe7c892de72e58c Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Fri, 22 Jan 2021 16:17:22 +0530 Subject: [PATCH 0719/1809] ARM: dts: msm: add CMA heap allocation Add CMA heap allocation for yupik target. Change-Id: I627c5d0036cebe752e884399fcc0252c6ac7dd87 --- qcom/yupik-ion.dtsi | 6 ++++++ qcom/yupik.dtsi | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index d93227950c3a..003a0bd46c2c 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -48,6 +48,12 @@ memory-region = <&qseecom_mem>; qcom,ion-heap-type = "DMA"; }; + + qcom,ion-heap@5 { /* AUDIO ML HEAP */ + reg = ; + memory-region = <&audio_cma_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a5ea5979c4b1..bd240f756459 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -450,6 +450,14 @@ reusable; size = <0 0x2c00000>; }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; }; soc: soc { }; From 2cbdbf32c4b3a884429af21760dda3024c8005b0 Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Mon, 11 Jan 2021 13:42:41 +0800 Subject: [PATCH 0720/1809] ARM: dts: msm: Add yupik camera sensor device tree to Yupik QRD Include camera sensor device tree nodes to enable camera sensor HW on Yupik QRD platform. Change-Id: If2af814b124b6bc5ecf24ada2a8be01cda3780d7 --- qcom/yupik-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index a8da2f964778..0c1f84264f7a 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -6,6 +6,7 @@ #include "yupik-audio-overlay.dtsi" #include "yupik-thermal-overlay-qrd.dtsi" #include "display/yupik-sde-display-qrd.dtsi" +#include "camera/yupik-camera-sensor-qrd.dtsi" &soc { gpio_keys { From 98aa3886ba0daea51153ee49c06ee01194daf1d6 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Thu, 15 Oct 2020 11:05:44 +0800 Subject: [PATCH 0721/1809] ARM: dts: msm: add pm-qos-latency for Lahaina usb add pm-qos-latency = <44>. Change-Id: I97c1e19cb05698c64382277689a1917b68c5e665 --- qcom/lahaina-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 2c9df5d05fe1..b5ff1962fa3e 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -40,6 +40,7 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <44>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ From 3419c3acbb47d1a3f0fd6a6f375695e17dd56b9f Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Thu, 21 Jan 2021 16:53:25 +0530 Subject: [PATCH 0722/1809] ARM: dts: msm: Disable pmic thermal zone cofiguration Disable pmic thermal zone configuration. Change-Id: Ic0cfe0d748ec20cd74d1c172eceb3f7e74a216df --- qcom/yupik-thermal-overlay-qrd.dtsi | 8 ++++++++ qcom/yupik-thermal-overlay.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 4d302f1cff41..081e3cd5939b 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -10,6 +10,7 @@ &thermal_zones { socd { + disable-thermal-zone; cooling-maps { socd_cpu4 { trip = <&socd_trip>; @@ -34,6 +35,7 @@ }; pm8350b-bcl-lvl0 { + disable-thermal-zone; cooling-maps { vbat_cpu4 { trip = <&b_bcl_lvl0>; @@ -58,6 +60,7 @@ }; pm8350b-bcl-lvl1 { + disable-thermal-zone; cooling-maps { vbat_cpu6 { trip = <&b_bcl_lvl1>; @@ -82,6 +85,7 @@ }; pm8350b-bcl-lvl2 { + disable-thermal-zone; cooling-maps { vbat_gpu2 { trip = <&b_bcl_lvl2>; @@ -165,6 +169,7 @@ }; pm8350b_tz { + disable-thermal-zone; cooling-maps { battery_cdev { trip = <&pm8350b_trip0>; @@ -176,6 +181,7 @@ }; pm7325_tz { + disable-thermal-zone; cooling-maps { pm7325_gpu { trip = <&pm7325_trip0>; @@ -221,6 +227,7 @@ }; pm8350c_tz { + disable-thermal-zone; cooling-maps { pm8350c_gpu { trip = <&pm8350c_trip0>; @@ -243,6 +250,7 @@ }; pmr735a_tz { + disable-thermal-zone; cooling-maps { pmr735a_pa { trip = <&pmr735a_trip0>; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 247891c9ece0..bf264b627ebf 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -10,6 +10,7 @@ &thermal_zones { socd { + disable-thermal-zone; cooling-maps { socd_cpu4 { trip = <&socd_trip>; @@ -34,6 +35,7 @@ }; pm7325b-bcl-lvl0 { + disable-thermal-zone; cooling-maps { vbat_cpu4 { trip = <&b_bcl_lvl0>; @@ -58,6 +60,7 @@ }; pm7325b-bcl-lvl1 { + disable-thermal-zone; cooling-maps { vbat_cpu6 { trip = <&b_bcl_lvl1>; @@ -82,6 +85,7 @@ }; pm7325b-bcl-lvl2 { + disable-thermal-zone; cooling-maps { vbat_gpu2 { trip = <&b_bcl_lvl2>; @@ -165,6 +169,7 @@ }; pm7325b_tz { + disable-thermal-zone; cooling-maps { battery_cdev { trip = <&pm7325b_trip0>; @@ -176,6 +181,7 @@ }; pm7325_tz { + disable-thermal-zone; cooling-maps { pm7325_gpu { trip = <&pm7325_trip0>; @@ -221,6 +227,7 @@ }; pm8350c_tz { + disable-thermal-zone; cooling-maps { pm8350c_gpu { trip = <&pm8350c_trip0>; @@ -243,6 +250,7 @@ }; pmr735a_tz { + disable-thermal-zone; cooling-maps { pmr735a_pa { trip = <&pmr735a_trip0>; From 1f70be39c69d8266c456146d46fd5ce2b807527e Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Tue, 15 Dec 2020 14:29:48 +0530 Subject: [PATCH 0723/1809] ARM: dts: msm: Enable smmu s1 on sdxlemur V2 Enable smmu s1 for bslp uart, i2c, spi on sdxlemur V2. Change-Id: I1579d1169026111d88e11bfdf80d139ad1f16003 --- qcom/sdxlemur-v2.dtsi | 143 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 59cb20523cbd..75a7ba50ca15 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -6,3 +6,146 @@ qcom,msm-id = <458 0x20000>, <483 0x20000>; }; +&i2c_1 { + iommus = <&apps_smmu 0x148 0x0>, + <&apps_smmu 0x149 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_2 { + iommus = <&apps_smmu 0x14a 0x0>, + <&apps_smmu 0x14b 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_3 { + iommus = <&apps_smmu 0x14c 0x0>, + <&apps_smmu 0x14d 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_4 { + iommus = <&apps_smmu 0x14e 0x0>, + <&apps_smmu 0x14f 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_5 { + iommus = <&apps_smmu 0x148 0x0>, + <&apps_smmu 0x149 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_6 { + iommus = <&apps_smmu 0x14a 0x0>, + <&apps_smmu 0x14b 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&i2c_7 { + iommus = <&apps_smmu 0x14e 0x0>, + <&apps_smmu 0x14f 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&spi_1 { + iommus = <&apps_smmu 0x148 0x0>, + <&apps_smmu 0x149 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&spi_2 { + iommus = <&apps_smmu 0x14a 0x0>, + <&apps_smmu 0x14b 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&spi_3 { + iommus = <&apps_smmu 0x14c 0x0>, + <&apps_smmu 0x14d 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&spi_4 { + iommus = <&apps_smmu 0x14e 0x0>, + <&apps_smmu 0x14f 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart1a_hs { + iommus = <&apps_smmu 0x140 0x0>, + <&apps_smmu 0x141 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart1b_hs { + iommus = <&apps_smmu 0x140 0x0>, + <&apps_smmu 0x141 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart2a_hs { + iommus = <&apps_smmu 0x142 0x0>, + <&apps_smmu 0x143 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart2b_hs { + iommus = <&apps_smmu 0x142 0x0>, + <&apps_smmu 0x143 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart3_hs { + iommus = <&apps_smmu 0x144 0x0>, + <&apps_smmu 0x145 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart4a_hs { + iommus = <&apps_smmu 0x146 0x0>, + <&apps_smmu 0x147 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + +&blsp1_uart4b_hs { + iommus = <&apps_smmu 0x146 0x0>, + <&apps_smmu 0x147 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; From 059b00f5a7e98b78c879d7b78c26d8f8c0853cb3 Mon Sep 17 00:00:00 2001 From: Hui Li Date: Thu, 7 Jan 2021 14:07:27 +0800 Subject: [PATCH 0724/1809] ARM: dts: msm: Add support for kgsl driver on SA8155 Add support for GPU driver to perform graphics functionality on SA8155. Change-Id: I68efee76fe1016bdad5c59715b98c5be1c58142f --- qcom/sa8155-v2.dtsi | 68 +++++++++++ qcom/sm8150-gpu.dtsi | 276 +++++++++++++++++++++++++++++++++++++++++++ qcom/sm8150-v2.dtsi | 202 +++++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 1 + 4 files changed, 547 insertions(+) create mode 100644 qcom/sm8150-gpu.dtsi diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index 8862fd543d7f..bb97a5bc3ec3 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -255,6 +255,74 @@ 0x0a44 0x03 0x0>; }; +/* GPU power level overrides */ +&msm_gpu { + /delete-property/qcom,initial-pwrlevel; + qcom,initial-pwrlevel = <4>; + /delete-node/qcom,gpu-pwrlevels; + /delete-node/qcom,gpu-pwrlevel-bins; + + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <675000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <585000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <427000000>; + qcom,level = ; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + &scc { compatible = "qcom,sa8155-scc-v2", "syscon"; }; diff --git a/qcom/sm8150-gpu.dtsi b/qcom/sm8150-gpu.dtsi new file mode 100644 index 000000000000..5263fba4494d --- /dev/null +++ b/qcom/sm8150-gpu.dtsi @@ -0,0 +1,276 @@ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a640_zap"; + memory-region = <&pil_gpu_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@2C00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x2c00000 0x40000>, <0x2c61000 0x800>, + <0x6900000 0x44000>, <0x780000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", + "qdss_gfx", "qfprom_memory"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x06040000>; + + qcom,initial-pwrlevel = <5>; + + qcom,gpu-quirk-secvid-set-once; + qcom,gpu-quirk-cx-gdsc; + + qcom,idle-timeout = <80>; //msecs + qcom,no-nap; + + qcom,highest-bank-bit = <15>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <3>; + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size + + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + clock-names = "gcc_gpu_ahb", "rbbmtimer_clk", + "gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx", + "gmu_clk", "gpu_cc_ahb"; + + qcom,isense-clk-on-level = <1>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + , /* index=11 */ + ; /* index=12 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <864000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1344000000>; + }; + }; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <600000000>; + qcom,level = ; + + qcom,bus-freq = <12>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <553850000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <486460000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <379650000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <309110000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <215000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,level = ; + + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x02CA0000 0x10000>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0x401>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0x400>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@0x2C6A000 { + compatible = "qcom,gpu-gmu"; + + reg = <0x2c6a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + regulator-names = "vddcx", "vdd"; + + iommus = <&kgsl_smmu 0x5 0x400>; + qcom,iommu-dma = "disabled"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "gcc_gpu_memnoc_gfx_clk", "gpu_cc_ahb"; + + /* AOP mailbox for sending ACD enable and disable messages */ + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + + }; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index c2d7cb5fb7f2..7dc48e572c11 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -296,3 +296,205 @@ 0x0a00 0x00 0x0 0x0a44 0x03 0x0>; }; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x06040001>; + + /* Power level to start throttling */ + qcom,throttle-pwrlevel = <0>; + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + ; /* index=11 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,gpu-speed-bin = <0x4130 0xe0000000 29>; + + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <4>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <585000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <499200000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <427000000>; + qcom,level = ; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <345000000>; + qcom,level = ; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <257000000>; + qcom,level = ; + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <675000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <585000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <499200000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <427000000>; + qcom,level = ; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <345000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <257000000>; + qcom,level = ; + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <1344000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1612800000>; + }; + }; +}; + +&gmu { + reg = <0x2c6a000 0x30000>, + <0xb290000 0x10000>, + <0xb490000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 288adf57c10f..697e527629d4 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2401,3 +2401,4 @@ }; #include "sm8150-pcie.dtsi" #include "sm8150-usb.dtsi" +#include "sm8150-gpu.dtsi" From 64c44c2b99bf68077c96d9b29834e8f1baad5296 Mon Sep 17 00:00:00 2001 From: Hui Li Date: Thu, 7 Jan 2021 14:25:59 +0800 Subject: [PATCH 0725/1809] ARM: dts: msm: Add support for kgsl driver on sdmshrike Add support for GPU driver to perform graphics functionality on sdmshrike. Change-Id: I8f516b02f01f21003bf4b8d889b28ec3d8f47c50 --- bindings/gpu/adreno.txt | 4 + qcom/sdmshrike-gpu.dtsi | 229 ++++++++++++++++++++++++++++++++++++++++ qcom/sdmshrike-v2.dtsi | 122 +++++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + 4 files changed, 356 insertions(+) create mode 100644 qcom/sdmshrike-gpu.dtsi diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 12de7124472c..87789cf8d409 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -170,6 +170,10 @@ Optional Properties: Based on the ubwc mode, program the appropriate bit into certain protected registers and also pass to the user as a property. +- qcom,macrotiling-channels: + Specify the number of macrotiling channels for this chip. + This is programmed into certain registers and also pass to + the user as a property. - qcom,l2pc-cpu-mask: Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs. Bit 0 is for CPU-0, bit 1 is for CPU-1... diff --git a/qcom/sdmshrike-gpu.dtsi b/qcom/sdmshrike-gpu.dtsi new file mode 100644 index 000000000000..363b7c191dd0 --- /dev/null +++ b/qcom/sdmshrike-gpu.dtsi @@ -0,0 +1,229 @@ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a640_zap"; + memory-region = <&pil_gpu_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@2c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x2c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x6080000>; + + qcom,initial-pwrlevel = <5>; + + qcom,gpu-quirk-secvid-set-once; + qcom,gpu-quirk-cx-gdsc; + + qcom,idle-timeout = <80>; /* msecs */ + qcom,no-nap; + + qcom,highest-bank-bit = <16>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <3>; + + qcom,macrotiling-channels = <8>; + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + clock-names = "gcc_gpu_ahb", "rbbmtimer_clk", + "gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx", + "gmu_clk", "gpu_cc_ahb"; + + qcom,isense-clk-on-level = <1>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + , /* index=11 */ + ; /* index=12 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <514000000>; + qcom,level = ; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <12>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <461000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <405000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x2ca0000 0x10000>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0xC01>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0xC00>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@2c6a000 { + compatible = "qcom,gpu-gmu"; + + reg = <0x2c6a000 0x30000>, <0xb200000 0x300000>; + reg-names = "kgsl_gmu_reg", "kgsl_gmu_pdc_reg"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + regulator-names = "vddcx", "vdd"; + + iommus = <&kgsl_smmu 0x5 0xc00>; + qcom,iommu-dma = "disabled"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "gcc_gpu_memnoc_gfx_clk", "gpu_cc_ahb"; + }; +}; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index acbb61d0ecc6..83ef5838f7f3 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -31,3 +31,125 @@ &videocc { compatible = "qcom,sm8150-videocc-v2", "syscon"; }; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x6080001>; + + /* Power level to start throttling */ + qcom,throttle-pwrlevel = <3>; + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + ; /* index=11 */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,initial-pwrlevel = <4>; + /delete-node/qcom,gpu-pwrlevels; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <670000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <625000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <595000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <530000000>; + qcom,level = ; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <392000000>; + qcom,level = ; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <1344000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1612800000>; + }; + }; +}; + +&gmu { + reg = <0x2c6a000 0x30000>, + <0xb290000 0x10000>, + <0xb490000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6191c8b4045b..7c56d1ddd0f7 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1661,6 +1661,7 @@ #include "sa8195-qupv3.dtsi" #include "sa8195-ssc-qupv3.dtsi" #include "sa8195-usb.dtsi" +#include "sdmshrike-gpu.dtsi" &firmware { scm { From 318e1155f0116c6ee5ba3b66c52c3254b850319f Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 25 Jan 2021 09:55:37 +0530 Subject: [PATCH 0726/1809] ARM: dts: msm: add cont splash memory for yupik target Add cont splash memory node containing base address and size for yupik target. Change-Id: I069e838d727a410e195b282aec4c485f3d107f0f --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index cfa4fc4ac734..29f77964dc3c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -458,6 +458,11 @@ alignment = <0x0 0x400000>; size = <0x0 0x1C00000>; }; + + splash_memory:splash_region { + reg = <0x0 0xe1000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; }; soc: soc { }; From 331238b4877182931cf04ac19e715ec86e1b4005 Mon Sep 17 00:00:00 2001 From: priyankar Date: Sun, 24 Jan 2021 16:49:32 +0530 Subject: [PATCH 0727/1809] ARM: dts: msm: Update max voltage for each regulator This patch contains changes for setting max voltage for each regulator. Change-Id: I79d9d4c5c4006fdd57c68128943defc3f0cd1dc1 --- qcom/yupik.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index cfa4fc4ac734..88bbe9c0a0f3 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1193,13 +1193,14 @@ qcom,bt-vdd-ipa-2p2-supply = <&S1C>; /*IPA 2p2*/ qcom,bt-vdd-asd-supply = <&L11C>; - qcom,bt-vdd-io-config = <1800000 1800000 0 1>; - qcom,bt-vdd-aon-config = <824000 952000 0 1>; - qcom,bt-vdd-dig-config = <824000 952000 0 1>; - qcom,bt-vdd-rfacmn-config = <824000 952000 0 1>; - qcom,bt-vdd-rfa-0p8-config = <824000 952000 0 1>; - qcom,bt-vdd-rfa1-config = <1872000 1872000 0 1>; - qcom,bt-vdd-rfa2-config = <1256000 1352000 0 1>; + /* max voltage are set to regulator max voltage supported */ + qcom,bt-vdd-io-config = <1800000 2000000 0 1>; + qcom,bt-vdd-aon-config = <824000 1120000 0 1>; + qcom,bt-vdd-dig-config = <824000 1120000 0 1>; + qcom,bt-vdd-rfacmn-config = <824000 1120000 0 1>; + qcom,bt-vdd-rfa-0p8-config = <824000 1120000 0 1>; + qcom,bt-vdd-rfa1-config = <1872000 2040000 0 1>; + qcom,bt-vdd-rfa2-config = <1256000 1500000 0 1>; qcom,bt-vdd-ipa-2p2-config = <2200000 2210000 0 1>; qcom,bt-vdd-asd-config = <2800000 3544000 0 1>; }; From 3fbc552f68992d37f51cb1a44b7fd37da123dccf Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 25 Jan 2021 09:37:38 +0800 Subject: [PATCH 0728/1809] ARM: dts: msm: Add device trees for sa8195 virtual machine Add device tree files for sa8195 virtual machine. Change-Id: I252468bee7256b5a66944cadd4a345695a0c84c5 --- qcom/Makefile | 7 +- qcom/sa8195-vm-la-mt.dts | 11 + qcom/sa8195-vm-la-mt.dtsi | 6 + qcom/sa8195-vm-la.dts | 11 + qcom/sa8195-vm-la.dtsi | 30 + qcom/sa8195-vm-lv-lxc.dts | 11 + qcom/sa8195-vm-lv-lxc.dtsi | 39 ++ qcom/sa8195-vm-lv-mt.dts | 11 + qcom/sa8195-vm-lv-mt.dtsi | 34 + qcom/sa8195-vm-lv.dts | 11 + qcom/sa8195-vm-lv.dtsi | 30 + qcom/sa8195-vm-pcie.dtsi | 1303 ++++++++++++++++++++++++++++++++++++ qcom/sa8195-vm-usb.dtsi | 201 ++++++ qcom/sa8195-vm.dtsi | 468 +++++++++++++ 14 files changed, 2172 insertions(+), 1 deletion(-) create mode 100644 qcom/sa8195-vm-la-mt.dts create mode 100644 qcom/sa8195-vm-la-mt.dtsi create mode 100644 qcom/sa8195-vm-la.dts create mode 100644 qcom/sa8195-vm-la.dtsi create mode 100644 qcom/sa8195-vm-lv-lxc.dts create mode 100644 qcom/sa8195-vm-lv-lxc.dtsi create mode 100644 qcom/sa8195-vm-lv-mt.dts create mode 100644 qcom/sa8195-vm-lv-mt.dtsi create mode 100644 qcom/sa8195-vm-lv.dts create mode 100644 qcom/sa8195-vm-lv.dtsi create mode 100644 qcom/sa8195-vm-pcie.dtsi create mode 100644 qcom/sa8195-vm-usb.dtsi create mode 100644 qcom/sa8195-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 161b3dc1b925..ddee39dfa495 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -314,7 +314,12 @@ endif dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8155-vm-lv.dtb \ sa8155-vm-la-mt.dtb \ - sa8155-vm-lv-mt.dtb + sa8155-vm-lv-mt.dtb \ + sa8195-vm-la.dtb \ + sa8195-vm-lv.dtb \ + sa8195-vm-la-mt.dtb \ + sa8195-vm-lv-mt.dtb \ + sa8195-vm-lv-lxc.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/qcom/sa8195-vm-la-mt.dts b/qcom/sa8195-vm-la-mt.dts new file mode 100644 index 000000000000..caea45b3efe5 --- /dev/null +++ b/qcom/sa8195-vm-la-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-la-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LA Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000001 0>; +}; diff --git a/qcom/sa8195-vm-la-mt.dtsi b/qcom/sa8195-vm-la-mt.dtsi new file mode 100644 index 000000000000..e975abfa0bd4 --- /dev/null +++ b/qcom/sa8195-vm-la-mt.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8195-vm-la.dts b/qcom/sa8195-vm-la.dts new file mode 100644 index 000000000000..5413244629e4 --- /dev/null +++ b/qcom/sa8195-vm-la.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi new file mode 100644 index 000000000000..7d003a2eb6b1 --- /dev/null +++ b/qcom/sa8195-vm-la.dtsi @@ -0,0 +1,30 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sdhc_2 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv-lxc.dts b/qcom/sa8195-vm-lv-lxc.dts new file mode 100644 index 000000000000..d4b58dc6e970 --- /dev/null +++ b/qcom/sa8195-vm-lv-lxc.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv-lxc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000002 0>; +}; diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi new file mode 100644 index 000000000000..75228e2e38af --- /dev/null +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -0,0 +1,39 @@ +/ { + /delete-node/ cpus; +}; + +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb1 { + qcom,default-mode-host; + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&pcie2_msi { + status = "ok"; +}; + +&pcie2 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv-mt.dts b/qcom/sa8195-vm-lv-mt.dts new file mode 100644 index 000000000000..ee43c89ff38f --- /dev/null +++ b/qcom/sa8195-vm-lv-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000002 0>; +}; diff --git a/qcom/sa8195-vm-lv-mt.dtsi b/qcom/sa8195-vm-lv-mt.dtsi new file mode 100644 index 000000000000..35a59df5dedf --- /dev/null +++ b/qcom/sa8195-vm-lv-mt.dtsi @@ -0,0 +1,34 @@ +/ { + /delete-node/ cpus; +}; + +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv.dts b/qcom/sa8195-vm-lv.dts new file mode 100644 index 000000000000..9dd5fe872ef0 --- /dev/null +++ b/qcom/sa8195-vm-lv.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Single LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x1000002 0>; +}; diff --git a/qcom/sa8195-vm-lv.dtsi b/qcom/sa8195-vm-lv.dtsi new file mode 100644 index 000000000000..f7fd0e816130 --- /dev/null +++ b/qcom/sa8195-vm-lv.dtsi @@ -0,0 +1,30 @@ +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-pcie.dtsi b/qcom/sa8195-vm-pcie.dtsi new file mode 100644 index 000000000000..44c9d2b10f62 --- /dev/null +++ b/qcom/sa8195-vm-pcie.dtsi @@ -0,0 +1,1303 @@ +#include +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + status = "disabled"; + + pcie_rc0: pcie_rc0 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie1: qcom,pcie@1c10000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c10000 0x3000>, + <0x01c16000 0x2000>, + <0x68000000 0xf1d>, + <0x68000f20 0xa8>, + <0x68001000 0x1000>, + <0x68100000 0x100000>, + <0x68200000 0x100000>, + <0x68300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 175 0>; + wake-gpio = <&tlmm 177 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <2113>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1c80>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x200 &apps_smmu 0x1c82 0x1>, + <0x300 &apps_smmu 0x1c83 0x1>, + <0x400 &apps_smmu 0x1c84 0x1>, + <0x500 &apps_smmu 0x1c85 0x1>, + <0x600 &apps_smmu 0x1c86 0x1>, + <0x700 &apps_smmu 0x1c87 0x1>, + <0x800 &apps_smmu 0x1c88 0x1>, + <0x900 &apps_smmu 0x1c89 0x1>, + <0xa00 &apps_smmu 0x1c8a 0x1>, + <0xb00 &apps_smmu 0x1c8b 0x1>, + <0xc00 &apps_smmu 0x1c8c 0x1>, + <0xd00 &apps_smmu 0x1c8d 0x1>, + <0xe00 &apps_smmu 0x1c8e 0x1>, + <0xf00 &apps_smmu 0x1c8f 0x1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + status = "disabled"; + + pcie_rc1: pcie_rc1 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie2: qcom,pcie@1c18000 { + compatible = "qcom,pci-msm"; + cell-index = <2>; + + reg = <0x1c18000 0x3000>, + <0x01c1c000 0x2000>, + <0x70000000 0xf1d>, + <0x70000f20 0xa8>, + <0x70001000 0x1000>, + <0x70100000 0x100000>, + <0x70200000 0x100000>, + <0x70300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x70200000 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x70300000 0x0 0x3d00000>; + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_clkreq_default + &pcie2_perst_default + &pcie2_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_2_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie2_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <2>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d00>; + + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>, + <0x200 &apps_smmu 0x1d02 0x1>, + <0x300 &apps_smmu 0x1d03 0x1>, + <0x400 &apps_smmu 0x1d04 0x1>, + <0x500 &apps_smmu 0x1d05 0x1>, + <0x600 &apps_smmu 0x1d06 0x1>, + <0x700 &apps_smmu 0x1d07 0x1>, + <0x800 &apps_smmu 0x1d08 0x1>, + <0x900 &apps_smmu 0x1d09 0x1>, + <0xa00 &apps_smmu 0x1d0a 0x1>, + <0xb00 &apps_smmu 0x1d0b 0x1>, + <0xc00 &apps_smmu 0x1d0c 0x1>, + <0xd00 &apps_smmu 0x1d0d 0x1>, + <0xe00 &apps_smmu 0x1d0e 0x1>, + <0xf00 &apps_smmu 0x1d0f 0x1>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", + "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk", + "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk", + "pcie_2_ldo", "pcie_2_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_2_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + + reset-names = "pcie_2_core_reset", + "pcie_2_phy_reset"; + + status = "disabled"; + + pcie_rc2: pcie_rc2 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie2_msi: qcom,pcie2_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie3: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <3>; + + reg = <0x1c08000 0x3000>, + <0x1c0c000 0x4000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie3>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0044 0x1c 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x029c 0x12 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x0684 0x35 0x0 + 0x063c 0x11 0x0 + 0x069c 0x12 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x2a40 0x03 0x0 + 0x2010 0x00 0x0 + 0x201c 0x31 0x0 + 0x2020 0x01 0x0 + 0x2024 0xde 0x0 + 0x2028 0x07 0x0 + 0x2030 0x4c 0x0 + 0x2034 0x06 0x0 + 0x2048 0x90 0x0 + 0x2044 0x1c 0x0 + 0x2058 0x0f 0x0 + 0x2074 0x06 0x0 + 0x2078 0x06 0x0 + 0x207c 0x16 0x0 + 0x2080 0x16 0x0 + 0x2084 0x36 0x0 + 0x2088 0x36 0x0 + 0x2094 0x08 0x0 + 0x20a4 0x42 0x0 + 0x20ac 0x0a 0x0 + 0x20b0 0x1a 0x0 + 0x20b4 0x14 0x0 + 0x20b8 0x34 0x0 + 0x20bc 0x82 0x0 + 0x20c4 0x68 0x0 + 0x20cc 0x55 0x0 + 0x20d0 0x55 0x0 + 0x20d4 0x03 0x0 + 0x20d8 0xab 0x0 + 0x20dc 0xaa 0x0 + 0x20e0 0x02 0x0 + 0x210c 0x02 0x0 + 0x2110 0x24 0x0 + 0x2118 0xb4 0x0 + 0x211c 0x03 0x0 + 0x2154 0x34 0x0 + 0x2158 0x01 0x0 + 0x216c 0x08 0x0 + 0x21ac 0xb9 0x0 + 0x21b0 0x1e 0x0 + 0x21b4 0x94 0x0 + 0x21b8 0x18 0x0 + 0x21bc 0x11 0x0 + 0x2284 0x35 0x0 + 0x223c 0x11 0x0 + 0x229c 0x12 0x0 + 0x2408 0x0c 0x0 + 0x2414 0x03 0x0 + 0x2434 0x7f 0x0 + 0x2444 0x70 0x0 + 0x2460 0x30 0x0 + 0x2464 0x00 0x0 + 0x24d4 0x54 0x0 + 0x24d8 0x07 0x0 + 0x24dc 0x0d 0x0 + 0x24e8 0x00 0x0 + 0x24ec 0x0e 0x0 + 0x24f0 0x4a 0x0 + 0x24f4 0x0f 0x0 + 0x24f8 0xc0 0x0 + 0x24fc 0x00 0x0 + 0x2510 0x17 0x0 + 0x2518 0x1c 0x0 + 0x251c 0x03 0x0 + 0x2524 0x1e 0x0 + 0x2570 0xff 0x0 + 0x2574 0xff 0x0 + 0x2578 0xff 0x0 + 0x257c 0x7f 0x0 + 0x2580 0x66 0x0 + 0x2584 0x24 0x0 + 0x2588 0xe4 0x0 + 0x258c 0xec 0x0 + 0x2590 0x3b 0x0 + 0x2594 0x36 0x0 + 0x2598 0xd4 0x0 + 0x259c 0x54 0x0 + 0x25a0 0xdb 0x0 + 0x25a4 0x3b 0x0 + 0x25a8 0x31 0x0 + 0x25bc 0x0c 0x0 + 0x2684 0x35 0x0 + 0x263c 0x11 0x0 + 0x269c 0x12 0x0 + 0x2808 0x0c 0x0 + 0x2814 0x03 0x0 + 0x2834 0x7f 0x0 + 0x2844 0x70 0x0 + 0x2860 0x30 0x0 + 0x2864 0x00 0x0 + 0x28d4 0x54 0x0 + 0x28d8 0x07 0x0 + 0x28dc 0x0d 0x0 + 0x28e8 0x00 0x0 + 0x28ec 0x0e 0x0 + 0x28f0 0x4a 0x0 + 0x28f4 0x0f 0x0 + 0x28f8 0xc0 0x0 + 0x28fc 0x00 0x0 + 0x2910 0x17 0x0 + 0x2918 0x1c 0x0 + 0x291c 0x03 0x0 + 0x2924 0x1e 0x0 + 0x2970 0xff 0x0 + 0x2974 0xff 0x0 + 0x2978 0xff 0x0 + 0x297c 0x7f 0x0 + 0x2980 0x66 0x0 + 0x2984 0x24 0x0 + 0x2988 0xe4 0x0 + 0x298c 0xec 0x0 + 0x2990 0x3b 0x0 + 0x2994 0x36 0x0 + 0x2998 0xd4 0x0 + 0x299c 0x54 0x0 + 0x29a0 0xdb 0x0 + 0x29a4 0x3b 0x0 + 0x29a8 0x31 0x0 + 0x29bc 0x0c 0x0 + 0x2adc 0x05 0x0 + 0x2b88 0x88 0x0 + 0x2b98 0x0b 0x0 + 0x2ba4 0x01 0x0 + 0x2bec 0x01 0x0 + 0x2e0c 0x0d 0x0 + 0x2e14 0x07 0x0 + 0x2e1c 0xc1 0x0 + 0x2e40 0x01 0x0 + 0x2e48 0x01 0x0 + 0x2e90 0x00 0x0 + 0x2ebc 0x00 0x0 + 0x2ee0 0x58 0x0 + 0x2eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_clkreq_default + &pcie3_perst_default + &pcie3_wake_default>; + + perst-gpio = <&tlmm 178 0>; + wake-gpio = <&tlmm 56 0>; + + gdsc-vdd-supply = <&pcie_3_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie3_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <3>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_3_pipe_clk", "pcie_3_ref_clk_src", + "pcie_3_aux_clk", "pcie_3_cfg_ahb_clk", + "pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk", + "pcie_3_ldo", "pcie_3_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_3_BCR>, + <&gcc GCC_PCIE_3_PHY_BCR>; + + reset-names = "pcie_3_core_reset", + "pcie_3_phy_reset"; + + status = "disabled"; + + pcie_rc3: pcie_rc3 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie3_msi: qcom,pcie3_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-vm-usb.dtsi b/qcom/sa8195-vm-usb.dtsi new file mode 100644 index 000000000000..7d27d7c212d3 --- /dev/null +++ b/qcom/sa8195-vm-usb.dtsi @@ -0,0 +1,201 @@ +#include +#include +#include +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&dummycc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + qcom,charging-disabled; + qcom,ignore-wakeup-src-in-hostmode; + + status = "disabled"; + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&dummycc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi new file mode 100644 index 000000000000..19700893437d --- /dev/null +++ b/qcom/sa8195-vm.dtsi @@ -0,0 +1,468 @@ +#include +#include +#include +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; + aliases { + hsuart0 = &qupv3_se13_4uart; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + }; + + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x4>; + capacity-dmips-mhz = <306>; + }; + + CPU5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x5>; + capacity-dmips-mhz = <306>; + }; + + CPU6: cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x6>; + capacity-dmips-mhz = <306>; + }; + + CPU7: cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x7>; + capacity-dmips-mhz = <306>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>, <100000 100000>, + /* 50 MB/s */ + <130718 200000>, <100000 100000>, + /* 100 MB/s */ + <261438 200000>, <130000 130000>, + /* 200 MB/s */ + <261438 400000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + vdd-supply = <&pm8195_1_l10>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8195_1_l2>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + broken-cd; + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <70>; + }; + + qos1 { + mask = <0xf0>; + vote = <70>; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 6>, <30 510 1>, <40 520 1>, <46 526 1>, + <59 539 1>, <68 548 1>, <71 551 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + VDD_CX_LEVEL: + S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8195_3_s3_level"; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; +}; + +®ulator { + usb30_prim_gdsc: usb30_prim_gdsc { + regulator-name = "usb30_prim_gdsc"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + regulator-name = "usb30_sec_gdsc"; + }; + + pcie_0_gdsc: pcie_0_gdsc { + regulator-name = "pcie_0_gdsc"; + }; + + pcie_1_gdsc: pcie_1_gdsc { + regulator-name = "pcie_1_gdsc"; + }; + + pcie_2_gdsc: pcie_2_gdsc { + regulator-name = "pcie_2_gdsc"; + }; + + pcie_3_gdsc: pcie_3_gdsc { + regulator-name = "pcie_3_gdsc"; + }; + + L2A: pm8195_1_l2: regulator-pm8195-1-l2 { + regulator-name = "ldoa2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + L9A: pm8195_1_l9: regulator-pm8195-1-l9 { + regulator-name = "ldoa9"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-allow-set-load; + }; + + L10A: pm8195_1_l10: regulator-pm8195-1-l10 { + regulator-name = "ldoa10"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L12A: pm8195_1_l12: regulator-pm8195-1-l12 { + regulator-name = "ldoa12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + }; + + L7C: pm8195_2_l7: regulator-pm8195-2-l7 { + regulator-name = "ldoc7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2040000>; + }; + + L5E: pm8195_3_l5: regulator-pm8195-3-l5 { + regulator-name = "ldoe5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-allow-set-load; + }; + + L16E: pm8195_3_l16: regulator-pm8195-3-l16 { + regulator-name = "ldoe16"; + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + }; + + S2A: pm8195_1_s2: regulator-pm8195-1-s2 { + regulator-name = "smpa2"; + regulator-min-microvolt = <1179000>; + regulator-max-microvolt = <1379000>; + }; + + S5A: pm8195_1_s5: regulator-pm8195-1-s5 { + regulator-name = "smpa5"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + }; + + S5C: pm8195_2_s5: regulator-pm8195-2-s5 { + regulator-name = "smpc5"; + regulator-min-microvolt = <1713000>; + regulator-max-microvolt = <2040000>; + }; +}; + +#include "sdmshrike-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8195-vm-usb.dtsi" +#include "sa8195-vm-pcie.dtsi" +#include "sa8195-qupv3.dtsi" +#include "sa8195-ssc-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_2 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_3 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; From 018178a6668f79aeb2623c30f4bd49facda38fd5 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 28 Sep 2020 11:50:35 +0530 Subject: [PATCH 0729/1809] ARM: dts: msm: Add PMU device nodes for SM8150 Add CPU PMU and LLCC PMU device nodes for SM8150. Change-Id: I57f075796324dd4c27140504dc2ff9133dbda1cf --- qcom/sm8150.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 288adf57c10f..e8c7eba2c749 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -727,6 +727,12 @@ }; }; + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ @@ -990,6 +996,12 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 7d46fd53eafa4f766984310baebb76cd022eab58 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Sun, 27 Sep 2020 22:27:22 +0530 Subject: [PATCH 0730/1809] ARM: dts: msm: Add devfreq device nodes for SDMSHRIKE Add the bw_hwmon, memlat and compute devfreq device nodes along with other dependent nodes. Change-Id: I93eb2b46487f2e4e3c78582dec01df10cb180e48 --- qcom/sdmshrike.dtsi | 241 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6191c8b4045b..9741f5e74699 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -16,6 +16,12 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + / { model = "Qualcomm Technologies, Inc. SDMSHRIKE"; compatible = "qcom,sdmshrike"; @@ -605,6 +611,241 @@ }; }; + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 200, 16); /* 3051 MB/s */ + BW_OPP_ENTRY( 403, 16); /* 6149 MB/s */ + BW_OPP_ENTRY( 533, 16); /* 8132 MB/s */ + BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */ + BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 200, 4, 0x80); /* 762 MB/s */ + BW_OPP_ENTRY_DDR( 300, 4, 0x80); /* 1144 MB/s */ + BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */ + BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */ + BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */ + BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */ + BW_OPP_ENTRY_DDR(1017, 4, 0x80); /* 3879 MB/s */ + BW_OPP_ENTRY_DDR(1296, 4, 0x80); /* 4943 MB/s */ + BW_OPP_ENTRY_DDR(1555, 4, 0x80); /* 5931 MB/s */ + BW_OPP_ENTRY_DDR(1804, 4, 0x80); /* 6881 MB/s */ + BW_OPP_ENTRY_DDR(2092, 4, 0x80); /* 7980 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER0>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 576000 576000000 >, + < 672000 768000000 >, + < 864000 960000000 >, + < 1171200 1228800000 >, + < 1267200 1344000000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 672000 MHZ_TO_MBPS(403, 16) >, + < 864000 MHZ_TO_MBPS(533, 16) >, + < 1171200 MHZ_TO_MBPS(666, 16) >, + < 1267200 MHZ_TO_MBPS(777, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 672000 MHZ_TO_MBPS( 768, 4) >, + < 864000 MHZ_TO_MBPS(1017, 4) >, + < 1171200 MHZ_TO_MBPS(1555, 4) >, + < 1267200 MHZ_TO_MBPS(1804, 4) >; + }; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER1>; + }; + + cpu4_cpu_l3_tbl: qcom,cpu4_cpu_l3_tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 576000 576000000 >, + < 768000 768000000 >, + < 960000 960000000 >, + < 1248000 1228800000 >, + < 1593600 1344000000 >; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 768000 MHZ_TO_MBPS(403, 16) >, + < 960000 MHZ_TO_MBPS(533, 16) >, + < 1248000 MHZ_TO_MBPS(666, 16) >, + < 1593600 MHZ_TO_MBPS(777, 16) >; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 768000 MHZ_TO_MBPS( 768, 4) >, + < 960000 MHZ_TO_MBPS(1017, 4) >, + < 1248000 MHZ_TO_MBPS(1555, 4) >, + < 1593600 MHZ_TO_MBPS(1804, 4) >, + < 1689600 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1593600 MHZ_TO_MBPS( 200, 4) >, + < 2016000 MHZ_TO_MBPS(1017, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From 5b69f8f34d390a8828c4619457f210bf60f7dc1b Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 15 Oct 2020 20:37:55 +0530 Subject: [PATCH 0731/1809] ARM: dts: msm: Add PMU device nodes for SDMSHRIKE Add CPU PMU and LLCC PMU device nodes for SDMSHRIKE. Change-Id: I6729ea2bd2058585b35a8291b9721dc655bd2db2 --- qcom/sdmshrike.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 9741f5e74699..7f82759418e8 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -611,6 +611,12 @@ }; }; + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x090cc000 0x300>, <0x09648000 0x200>; + reg-names = "lagg-base", "beac-base"; + }; + llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ @@ -846,6 +852,12 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From 58066be786b011a0e2df4898952da88af6b3ad6d Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 25 Jan 2021 12:20:49 +0530 Subject: [PATCH 0732/1809] ARM: dts: msm: remove PON_PBS peripheral for yupik PON_PBS peripheral on PMK8350 is needed on HLOS for only v1 of the PMIC. Disable it for yupik as it is not needed. Change-Id: I5d56724a8e4848ef394141e8445c7a71f3e65493 --- qcom/yupik-pmic-overlay.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index 5cded5632a57..ac30b1c1045a 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -40,6 +40,12 @@ }; }; +&pmk8350 { + pon_pbs@800 { + status = "disabled"; + }; +}; + &pmk8350_vadc { /delete-node/ pm8350_ref_gnd; /delete-node/ pm8350_vref_1p25; From aad013cfc44d633fd1f7d353b56f18e70477a842 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 25 Jan 2021 15:32:59 +0800 Subject: [PATCH 0733/1809] ARM: dts: msm: Add qfprom for sa8155 Add qfprom to read fuse bits. Change-Id: Ie2812364ef9d4bff8f30a34008f3f37881b010b4 --- qcom/sa8155.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index ff361ab4427e..7f48b2dcd551 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -53,6 +53,17 @@ status = "ok"; }; +&soc { + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + &usb2_phy0 { vdd-supply = <&pm8150_1_l5>; vdda18-supply = <&pm8150_1_l12>; From 02283dec59a912c375d02963eeee341913af81c4 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 25 Jan 2021 15:37:53 +0800 Subject: [PATCH 0734/1809] ARM: dts: msm: Add qfprom for sa8195 Add qfprom to read fuse bits. Change-Id: Ia20ec6c1d55070670d4cefd84b0a97696df46120 --- qcom/sa8195p.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index dfa2d0d903ce..ee110fef6f8f 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -8,6 +8,17 @@ qcom,msm-id = <405 0x20000>; }; +&soc { + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + &scc { vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>; status = "ok"; From 36217c3953e13d4544e1441e93da7ac07998f799 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Wed, 28 Oct 2020 15:30:05 +0800 Subject: [PATCH 0735/1809] ARM: dts: msm: add hgsl to sa8155 vm for GPU doorbell hgsl device is for GPU doorbell feature which allows GVM to submit commands to GPU directly. Change-Id: I9a90e8cce249f764c8fd8126a8232c79a19dad34 --- qcom/sa8155-vm.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index f4092adea4aa..62c2facecd81 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -197,6 +197,66 @@ interrupt-parent = <&intc>; interrupt-controller; }; + + tcsr_compute_signal_glb: syscon@0x1fd8000 { + compatible = "syscon"; + reg = <0x1fd8000 0x1000>; + }; + + tcsr_compute_signal_sender0: syscon@0x1fd9000 { + compatible = "syscon"; + reg = <0x1fd9000 0x1000>; + }; + + tcsr_compute_signal_sender1: syscon@0x1fdd000 { + compatible = "syscon"; + reg = <0x1fdd000 0x1000>; + }; + + tcsr_compute_signal_receiver0: syscon@0x1fdb000 { + compatible = "syscon"; + reg = <0x1fdb000 0x1000>; + }; + + tcsr_compute_signal_receiver1: syscon@0x1fdf000 { + compatible = "syscon"; + reg = <0x1fdf000 0x1000>; + }; + + hgsl_tcsr_sender0: hgsl_tcsr_sender0 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender0>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_sender1: hgsl_tcsr_sender1 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender1>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver0>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + }; + + hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver1>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + }; + + msm_gpu_hyp: qcom,hgsl@0x2c00000 { + compatible = "qcom,hgsl"; + reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; + reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + + qcom,glb-db-senders = <&hgsl_tcsr_sender0 + &hgsl_tcsr_sender1>; + qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 + &hgsl_tcsr_receiver1>; + }; }; ®ulator { From 3d48b7d34cccb9412441bb2985ccb3127b3197a8 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Mon, 25 Jan 2021 18:22:03 +0800 Subject: [PATCH 0736/1809] ARM: dts: msm: disable bias for GPIO81 on Lahaina/Shima QRD GPIO81 receives CC_OUT signal from PMIC for type-c port orientation, keep it as bias-pull-up would cause the type-c analog audio adapter plug out event can't be detected because audio codec uses the same signal to detect type-c connection and orientation. Fix it by setting GPIO81 as bias-disabled. Change-Id: I90c8a6cacc01789a79e706cad031c5e1307c4506 --- qcom/lahaina-pinctrl.dtsi | 2 +- qcom/shima-pinctrl.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi index 242b9485c6eb..90ac81726e56 100644 --- a/qcom/lahaina-pinctrl.dtsi +++ b/qcom/lahaina-pinctrl.dtsi @@ -3672,7 +3672,7 @@ config { pins = "gpio81"; drive-strength = <2>; - bias-pull-up; + bias-disable; input-enable; }; }; diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 672784ffdbdd..2c4ab10ca6ec 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -3090,7 +3090,7 @@ config { pins = "gpio81"; drive-strength = <2>; - bias-pull-up; + bias-disable; input-enable; }; }; From a6d6dbd2b732e19524c30fd4dfd022113c0c9c57 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 25 Jan 2021 16:32:40 +0530 Subject: [PATCH 0737/1809] ARM: dts: msm: remove kgsl smmu interconnect node for Shima Remove kgsl smmu interconnect node for Shima. For TCU config register access we shouldn't required DDR path votes. KGSL smmu already votes for clock and regulator so it should be fine. Change-Id: I5e09725edaec9e5164dacb594c8437ed7e94f2ee --- qcom/msm-arm-smmu-shima.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index 4867686e4486..f5ce12811ba4 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -35,8 +35,6 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; - interrupts = , , , From d4b50c38f407deae2e9fe6063c1d195cc4e64479 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 25 Jan 2021 16:40:12 +0530 Subject: [PATCH 0738/1809] dt-bindings: qpnp-lcdb-regulator: Add support for NCP symmetry with LDO Add a device-tree property which enables NCP symmetry. This configuration in HW enables the NCP voltage to follow LDO. Change-Id: Ie97eb8b6a4eff96e78ef7f90688b1f5e3fd84133 --- bindings/regulator/qpnp-lcdb-regulator.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/regulator/qpnp-lcdb-regulator.txt b/bindings/regulator/qpnp-lcdb-regulator.txt index ca63521841e0..0a852ec29392 100644 --- a/bindings/regulator/qpnp-lcdb-regulator.txt +++ b/bindings/regulator/qpnp-lcdb-regulator.txt @@ -39,6 +39,12 @@ First Level Node - LCDB module to be enabled only on platforms where voltage needs to be ramped up with multiple steps. +- qcom,ncp-symmetry + Usage: optional + Value type: + Definition: Enabling this will make NCP voltage follow LDO voltage + directly. + - qcom,pwrdn-delay-ms Usage: optional Value type: From d8e7aa29cd4e4ba07ae124aafaaf6ede7d82dfab Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 24 Aug 2020 16:44:07 +0530 Subject: [PATCH 0739/1809] ARM: dts: msm: Add regulators for SA6155 Add regulator devices for sa6155 as RPMh regulators. This ensures that consumers are able to modify the physical state of the PMIC regulators. Change-Id: Ica5e8b2af3261333d875a07aa7d68cd968bb3f64 --- qcom/sa6155-pmic.dtsi | 42 +++ qcom/sa6155-regulator.dtsi | 496 ++++++++++++++++++++++++++ qcom/sa6155.dtsi | 1 + qcom/sa6155p.dtsi | 14 + qcom/sm6150-regulator.dtsi | 698 +++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 1 + 6 files changed, 1252 insertions(+) create mode 100644 qcom/sa6155-pmic.dtsi create mode 100644 qcom/sa6155-regulator.dtsi create mode 100644 qcom/sm6150-regulator.dtsi diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi new file mode 100644 index 000000000000..0f81ce8d1397 --- /dev/null +++ b/qcom/sa6155-pmic.dtsi @@ -0,0 +1,42 @@ +/* Remove regulator nodes specific to SM6150 */ +&apps_rsc { + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-smpc1; + /delete-node/ rpmh-regulator-smpc2; + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoa1; + /delete-node/ rpmh-regulator-ldoa2; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa4; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa10; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa14; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa17; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-ldoa19; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc5; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; +}; + +#include "sa6155-regulator.dtsi" diff --git a/qcom/sa6155-regulator.dtsi b/qcom/sa6155-regulator.dtsi new file mode 100644 index 000000000000..e2b264a7e844 --- /dev/null +++ b/qcom/sa6155-regulator.dtsi @@ -0,0 +1,496 @@ +#include + +&apps_rsc { + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + + VDD_CX_LEVEL: VDD_MX_LEVEL: + S2A_LEVEL: pm6155_1_s2_level: regulator-pm6155-1-s2-level { + regulator-name = "pm6155_1_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: VDD_MX_LEVEL_AO: S2A_LEVEL_AO: + pm6155_1_s2_level_ao: regulator-pm6155-1-s2-level-ao { + regulator-name = "pm6155_1_s2_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa3"; + S3A: pm6155_1_s3: regulator-pm6155-1-s3 { + regulator-name = "pm6155_1_s3"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <600000>; + }; + }; + + rpmh-regulator-smpa4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa4"; + S4A: pm6155_1_s4: regulator-pm6155-1-s4 { + regulator-name = "pm6155_1_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa5"; + S5A: pm6155_1_s5: regulator-pm6155-1-s5 { + regulator-name = "pm6155_1_s5"; + qcom,set = ; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1896000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa6"; + S6A: pm6155_1_s6: regulator-pm6155-1-s6 { + regulator-name = "pm6155_1_s6"; + qcom,set = ; + regulator-min-microvolt = <947000>; + regulator-max-microvolt = <1404000>; + qcom,init-voltage = <947000>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm6155_1_l1: regulator-pm6155-1-l1 { + regulator-name = "pm6155_1_l1"; + qcom,set = ; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + qcom,init-voltage = <488000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm6155_1_l2: regulator-pm6155-1-l2 { + regulator-name = "pm6155_1_l2"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm6155_1_l3: regulator-pm6155-1-l3 { + regulator-name = "pm6155_1_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm6155_1_l5: regulator-pm6155-1-l5 { + regulator-name = "pm6155_1_l5"; + qcom,set = ; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + qcom,init-voltage = <875000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm6155_1_l7: regulator-pm6155-1-l7 { + regulator-name = "pm6155_1_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8A: pm6155_1_l8: regulator-pm6155-1-l8 { + regulator-name = "pm6155_1_l8"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm6155_1_l9: regulator-pm6155-1-l9 { + regulator-name = "pm6155_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm6155_1_l10: regulator-pm6155-1-l10 { + regulator-name = "pm6155_1_l10"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm6155_1_l11: regulator-pm6155-1-l11 { + regulator-name = "pm6155_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm6155_1_l12: regulator-pm6155-1-l12 { + regulator-name = "pm6155_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm6155_1_l13: regulator-pm6155-1-l13 { + regulator-name = "pm6155_1_l13"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm6155_1_l15: regulator-pm6155-1-l15 { + regulator-name = "pm6155_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm6155_1_l16: regulator-pm6155-1-l16 { + regulator-name = "pm6155_1_l16"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm6155_1_l17: regulator-pm6155-1-l17 { + regulator-name = "pm6155_1_l17"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + /* PM6155 S1 - VDD_MSS supply */ + rpmh-regulator-modemlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + + VDD_MSS_LEVEL: + S1C_LEVEL: pm6155_2_s1_level: regulator-pm6155-2-s1-level { + regulator-name = "pm6155_2_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm6155_2_l2: regulator-pm6155-2-l2 { + regulator-name = "pm6155_2_l2"; + qcom,set = ; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2430000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3C: pm6155_2_l3: regulator-pm6155-2-l3 { + regulator-name = "pm6155_2_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm6155_2_l4: regulator-pm6155-2-l4 { + regulator-name = "pm6155_2_l4"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13C: pm6155_2_l13: regulator-pm6155-2-l13 { + regulator-name = "pm6155_2_l13"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14C: pm6155_2_l14: regulator-pm6155-2-l14 { + regulator-name = "pm6155_2_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16C: pm6155_2_l16: regulator-pm6155-2-l16 { + regulator-name = "pm6155_2_l16"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17C: pm6155_2_l17: regulator-pm6155-2-l17 { + regulator-name = "pm6155_2_l17"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18C: pm6155_2_l18: regulator-pm6155-2-l18 { + regulator-name = "pm6155_2_l18"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 3306572750b1..4765299d653f 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -1,4 +1,5 @@ #include "sm6150.dtsi" +#include "sa6155-pmic.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155"; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index b77b5f81a3d5..4b2c022d2cb4 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -1,7 +1,21 @@ #include "sm6150.dtsi" +#include "sa6155-pmic.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P"; qcom,msm-name = "SA6155P"; qcom,msm-id = <377 0>, <380 0>; }; + +&apps_rsc { + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc13; + /delete-node/ rpmh-regulator-ldoc14; + /delete-node/ rpmh-regulator-ldoc16; + /delete-node/ rpmh-regulator-ldoc17; + /delete-node/ rpmh-regulator-ldoc18; + /delete-node/ bt_wcn3990; +}; diff --git a/qcom/sm6150-regulator.dtsi b/qcom/sm6150-regulator.dtsi new file mode 100644 index 000000000000..05863973efe9 --- /dev/null +++ b/qcom/sm6150-regulator.dtsi @@ -0,0 +1,698 @@ +#include + +&apps_rsc { + /* RPMh regulators: */ + + /* pm6150 S3 - VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + regulator-name = "pm6150_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + regulator-name = "pm6150_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* pm6150 S1 - VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + pm6150_s1_level-parent-supply = <&VDD_MX_LEVEL>; + pm6150_s1_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: + S1A_LEVEL: pm6150_s1_level: regulator-pm6150-s1 { + regulator-name = "pm6150_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: + S1A_LEVEL_AO: pm6150_s1_level_ao: regulator-pm6150-s1-level-ao { + qcom,set = ; + regulator-name = "pm6150_s1_level_ao"; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc1"; + S1C: pm6150l_s1: regulator-pm6150l-s1 { + regulator-name = "pm6150l_s1"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + }; + }; + + rpmh-regulator-smpc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc2"; + S2C: pm6150l_s2: regulator-pm6150l-s2 { + regulator-name = "pm6150l_s2"; + qcom,set = ; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <648000>; + qcom,init-voltage = <348000>; + }; + }; + + /* pm6150l S7 - VDD_MSS supply */ + rpmh-regulator-modemlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + regulator-name = "pm6150l_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc8"; + S8C: pm6150l_s8: regulator-pm6150l-s8 { + regulator-name = "pm6150l_s8"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1200000>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm6150_l1: regulator-pm6150-l1 { + regulator-name = "pm6150_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm6150_l2: regulator-pm6150-l2 { + regulator-name = "pm6150_l2"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm6150_l3: regulator-pm6150-l3 { + regulator-name = "pm6150_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1060000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150_l4>; + L4A: pm6150_l4: regulator-pm6150-l4 { + regulator-name = "pm6150_l4"; + qcom,set = ; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + qcom,init-voltage = <875000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm6150_l5: regulator-pm6150-l5 { + regulator-name = "pm6150_l5"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6A: pm6150_l6: regulator-pm6150-l6 { + regulator-name = "pm6150_l6"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <600000>; + qcom,init-mode = ; + }; + }; + + /* pm6150 L7 - LPI_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 { + regulator-name = "pm6150_l7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* pm6150 L8 - LPI_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 { + regulator-name = "pm6150_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* pm6150 L9 - WCSS_CX supply */ + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm6150_l9: regulator-pm6150-l9 { + regulator-name = "pm6150_l9"; + qcom,set = ; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm6150_l10: regulator-pm6150-l10 { + regulator-name = "pm6150_l10"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm6150_l11: regulator-pm6150-l11 { + regulator-name = "pm6150_l11"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm6150_l12: regulator-pm6150-l12 { + regulator-name = "pm6150_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150_l13>; + L13A: pm6150_l13: regulator-pm6150-l13 { + regulator-name = "pm6150_l13"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <115000>; + }; + }; + + rpmh-regulator-ldoa14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14A: pm6150_l14: regulator-pm6150-l14 { + regulator-name = "pm6150_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm6150_l15: regulator-pm6150-l15 { + regulator-name = "pm6150_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm6150_l16: regulator-pm6150-l16 { + regulator-name = "pm6150_l16"; + qcom,set = ; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2430000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm6150_l17: regulator-pm6150-l17 { + regulator-name = "pm6150_l17"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm6150_l18: regulator-pm6150-l18 { + regulator-name = "pm6150_l18"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L19A: pm6150_l19: regulator-pm6150-l19 { + regulator-name = "pm6150_l19"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L1C: pm6150l_l1: regulator-pm6150l-l1 { + regulator-name = "pm6150l_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L2C: pm6150l_l2: regulator-pm6150l-l2 { + regulator-name = "pm6150l_l2"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150l_l3>; + L3C: pm6150l_l3: regulator-pm6150l-l3 { + regulator-name = "pm6150l_l3"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm6150l_l4: regulator-pm6150l-l4 { + regulator-name = "pm6150l_l4"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm6150l_l5: regulator-pm6150l-l5 { + regulator-name = "pm6150l_l5"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C: pm6150l_l6: regulator-pm6150l-l6 { + regulator-name = "pm6150l_l6"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm6150l_l7: regulator-pm6150l-l7 { + regulator-name = "pm6150l_l7"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8C: pm6150l_l8: regulator-pm6150l-l8 { + regulator-name = "pm6150l_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9C: pm6150l_l9: regulator-pm6150l-l9 { + regulator-name = "pm6150l_l9"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10C: pm6150l_l10: regulator-pm6150l-l10 { + regulator-name = "pm6150l_l10"; + qcom,set = ; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm6150l_l11: regulator-pm6150l-l11 { + regulator-name = "pm6150l_l11"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + qcom,send-defaults; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + regulator-name = "pm6150l_bob"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + regulator-name = "pm6150l_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 4e19271b626c..07921d34a10e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -719,3 +719,4 @@ #include "sm6150-qupv3.dtsi" #include "sm6150-pinctrl.dtsi" #include "sm6150-pm.dtsi" +#include "sm6150-regulator.dtsi" From 3dd52734776b50e598a2980316aae382be2e5f1c Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 25 Jan 2021 19:03:54 +0530 Subject: [PATCH 0740/1809] ARM: dts: qcom: Add GPU gaming bin support for Yupik Add provider bindings in qfprom and consumer bindings for enabling support to read the gaming bin fuse bit for Yupik GPU. Change-Id: Id39af50bdc2c26eee0f9a0a48b8c18a36124b7c6 --- qcom/yupik-gpu.dtsi | 4 ++-- qcom/yupik.dtsi | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 21701059f411..f6bb660a63ee 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -80,8 +80,8 @@ <0>, /* Off */ <100>; /* On */ - nvmem-cells = <&gpu_speed_bin>; - nvmem-cell-names = "speed_bin"; + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin"; qcom,gpu-mempools { #address-cells = <1>; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 29f77964dc3c..9bf7e1470090 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3427,6 +3427,11 @@ bits = <5 8>; }; + gpu_gaming_bin: gpu_gaming_bin@1f5 { + reg = <0x1f5 0x1>; + bits = <5 1>; + }; + feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; From 9cfbb8b5160bc6c286b464558f45c4325bfa68b0 Mon Sep 17 00:00:00 2001 From: priyankar Date: Mon, 25 Jan 2021 16:46:06 +0530 Subject: [PATCH 0741/1809] ARM: dts: msm: Update compatible string for moselle Update compatible string from qcom,wcn6750 to qcom,wcn6750-bt inorder to make it different from WLAN compatible string. This will help in removing probe warnings during bootup. Change-Id: I0f3993799d9222f3019195ebb1b29ca972c1222b --- bindings/bluetooth/btpower.txt | 2 +- qcom/yupik.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 39c44d4ea365..529d764c6da9 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -10,7 +10,7 @@ Required properties: qcom,wcn3990 qcom,qca6390 qcom,qca6490 - qcom,wcn6750 + qcom,wcn6750-bt - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index e48c3f5a51d2..2dd56a3087d8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1181,7 +1181,7 @@ }; bluetooth: bt_wcn6750 { - compatible = "qcom,wcn6750"; + compatible = "qcom,wcn6750-bt"; pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */ From 41c192d6c5e480d8a1b99014945388bce66e8bbc Mon Sep 17 00:00:00 2001 From: Paul Zhang Date: Wed, 13 Jan 2021 16:36:03 +0800 Subject: [PATCH 0742/1809] ARM: dts: msm: add cnss device tree Add device tree node for cnss driver for rome and TF. CRs-Fixed: 2854222 Change-Id: I2aba055bef033b57ceae6580e1a0c0b340592dbc --- bindings/cnss/cnss-wlan.txt | 1 + qcom/sdxnightjar-cnss.dtsi | 41 +++++++++++++++++++++++++++++++++ qcom/sdxnightjar-pinctrl.dtsi | 11 +++++++++ qcom/sdxnightjar-regulator.dtsi | 2 +- qcom/sdxnightjar.dtsi | 1 + 5 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxnightjar-cnss.dtsi diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index f9ab0e0b90a4..73828aaebeb9 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -12,6 +12,7 @@ provides the reserved RAM dump memory location and size. Required properties: - compatible: "qcom,cnss" for QCA6174 device + "qcom,cnss_sdio" for TF device "qcom,cnss-qca6290" for QCA6290 device "qcom,cnss-qca6390" for QCA6390 device "qcom,cnss-qca6490" for QCA6490 device diff --git a/qcom/sdxnightjar-cnss.dtsi b/qcom/sdxnightjar-cnss.dtsi new file mode 100644 index 000000000000..5d4c7bd08918 --- /dev/null +++ b/qcom/sdxnightjar-cnss.dtsi @@ -0,0 +1,41 @@ + +&soc { + cnss_pcie: qcom,cnss { + compatible = "qcom,cnss"; + wlan-en-gpio = <&tlmm_pinmux 95 0>; + vdd-wlan-supply = <&rome_vreg>; + vdd-wlan-xtal-supply = <&pmd9650_l5>; + vdd-wlan-io-supply = <&pmd9650_l6>; + vdd-wlan-xtal-aon-supply = <&pmd9650_l4>; + qcom,notify-modem-status; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x200000>; + + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + }; + + cnss_sdio: qcom,cnss_sdio { + compatible = "qcom,cnss_sdio"; + subsys-name = "AR6320_SDIO"; + vdd-wlan-xtal-supply = <&pmd9650_l5>; + vdd-wlan-io-supply = <&pmd9650_l6>; + qcom,wlan-ramdump-dynamic = <0x200000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&cnss_sdio_active>; + pinctrl-1 = <&cnss_sdio_sleep>; + qcom,is-antenna-shared; + }; +}; diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index ac2ca4510732..6f34c29c1b38 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -1400,4 +1400,15 @@ qcom,pull-up-strength = ; /* Pull up 1.5 uA */ power-source = <1>; /* 1.8 V */ }; + + gpio@c500 { /* GPIO 6 - Rome 3.3V control */ + status = "ok"; + qcom,mode = <1>; /* Digital output*/ + qcom,output-type = <0>; /* CMOS logic */ + qcom,invert = <1>; /* Output high */ + qcom,vin-sel = <0>; /* VPH_PWR */ + qcom,src-sel = <0>; /* Constant */ + qcom,out-strength = <1>; /* High drive strength */ + qcom,master-en = <1>; /* Enable GPIO */ + }; }; diff --git a/qcom/sdxnightjar-regulator.dtsi b/qcom/sdxnightjar-regulator.dtsi index 3de4186dbb5b..d381a0a2996a 100644 --- a/qcom/sdxnightjar-regulator.dtsi +++ b/qcom/sdxnightjar-regulator.dtsi @@ -263,7 +263,7 @@ regulator-name = "rome_vreg"; startup-delay-us = <4000>; enable-active-high; - gpio = <&pmd9650_gpios 6 0>; + gpios = <&pmd9650_gpios 6 0>; }; /* SD card 2.95 V supply */ diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 65b5885279f7..00ea3f6a2f57 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1022,6 +1022,7 @@ #include "sdxnightjar-pinctrl.dtsi" #include "sdxnightjar-ion.dtsi" #include "sdxnightjar-blsp.dtsi" +#include "sdxnightjar-cnss.dtsi" #include "sdxnightjar-pcie.dtsi" &i2c_3 { From da78b00d3fff3b7964698d47b884fbbfe1055513 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Tue, 12 Jan 2021 08:24:52 -0800 Subject: [PATCH 0743/1809] ARM: dts: msm: Add regulator and thermal node 1. Add support to vote regulators for WCN6750. 2. Add thermal node to support thermal mitigation. Change-Id: I3d918d38e0cb3bdada3128526caa8c68e047cd48 --- qcom/yupik.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 29f77964dc3c..00d97cf28a99 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1169,9 +1169,23 @@ qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; cnss-daemon-support; qcom,fw-prefix; + vdd-cx-mx-supply = <&S7B>; + qcom,vdd-cx-mx-config = <824000 1120000 0 0 1>; + vdd-1.8-xo-supply = <&S1B>; + qcom,vdd-1.8-xo-config = <1872000 2040000 0 0 0>; + vdd-1.3-rfa-supply = <&S8B>; + qcom,vdd-1.3-rfa-config = <1256000 1500000 0 0 0>; qcom,smem-states = <&smp2p_wlan_1_out 0>; qcom,smem-state-names = "wlan-smp2p-out"; + icnss_cdev_apss: qcom,icnss_cdev1 { + #cooling-cells = <2>; + }; + + icnss_cdev_wpss: qcom,icnss_cdev2 { + #cooling-cells = <2>; + }; + qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; @@ -2617,7 +2631,11 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; - /* Needs to add vdd_cx at SOD time.*/ + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; qcom,firmware-name = "wpss"; memory-region = <&pil_wpss_mem>; From 12249ceb4178c5e10e4d88202927bafd23e3e360 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Tue, 26 Jan 2021 16:08:23 +0800 Subject: [PATCH 0744/1809] ARM: dts: qcom: enable suspend for Lahaina HHG add qcom,ignore-wakeup-src-in-hostmode property. Change-Id: I05a4e7808b1f675bdf2ca4bce271d1ed34aad37d --- qcom/lahaina-hhg.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index b19e06ee65ff..aafe0bc3d6ea 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -97,3 +97,7 @@ }; }; }; + +&usb1 { + qcom,ignore-wakeup-src-in-hostmode; +}; From e74262fb4c45b5364cd732fc60c6aeefb860fb76 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 13 Jan 2021 11:42:50 -0800 Subject: [PATCH 0745/1809] bindings: smb1398: Add support for SMB1394 Add compatible strings for SMB1394, which is a variant of SMB1398. Change-Id: I3434c5a5522b3d1bb162ddff3aea4e66d1c8501d --- bindings/power/supply/qcom/smb1398-charger.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/power/supply/qcom/smb1398-charger.txt b/bindings/power/supply/qcom/smb1398-charger.txt index 869af88da4c5..a2ff8a0c16ff 100644 --- a/bindings/power/supply/qcom/smb1398-charger.txt +++ b/bindings/power/supply/qcom/smb1398-charger.txt @@ -28,6 +28,10 @@ Charger specific properties: mode (auto transition between DIV2 CP and 3-level buck) as a pre-regulator stand between wireless receiver and downstream chargers. + "qcom,smb1394-div2-cp-primary" for SMB1394 working in DIV2 mode as + a primary companion charger. + "qcom,smb1394-div2-cp-secondary" for SMB1394 working in DIV2 mode as + a secondary companion charger. - interrupts Usage: optional From b8b8cfb80264045d92db3f2d67582bc62bcc9041 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 26 Jan 2021 23:47:08 +0530 Subject: [PATCH 0746/1809] dt-bindings: Add support for GDSC flag to map single GDSCR Add new gdsc flag "qcom,no-config-gdscr" to map a single register for GDSC, as few legacy HW have support only for single GDSCR and don't contain config GDSCR's. Change-Id: I89996d05e6ee0fd321c63f0c91af6b5b3c313b0d --- bindings/regulator/gdsc-regulator.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/regulator/gdsc-regulator.txt b/bindings/regulator/gdsc-regulator.txt index 0234b27be56c..d78c7ba50ca5 100644 --- a/bindings/regulator/gdsc-regulator.txt +++ b/bindings/regulator/gdsc-regulator.txt @@ -58,6 +58,8 @@ Optional properties: - qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement to leave the GDSC on that has been enabled by an entity external to HLOS. + - qcom,no-config-gdscr: Presence denotes HW only supports a single register + per GDSC. Example: gdsc_oxili_gx: qcom,gdsc@fd8c4024 { From feeb43c1d2ecbbbffaa97998aed8c2f1ef1c3910 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 26 Jan 2021 10:19:39 -0800 Subject: [PATCH 0747/1809] ARM: dts: msm: Add SMB1394 device tree node Specify an SMB1394 node in the role of primary DIV 2 charger. Change-Id: Iff7abac2e969b8fc34ebe83646ca9047cb83ed73 --- qcom/smb1394.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 qcom/smb1394.dtsi diff --git a/qcom/smb1394.dtsi b/qcom/smb1394.dtsi new file mode 100644 index 000000000000..59b0bbfcc206 --- /dev/null +++ b/qcom/smb1394.dtsi @@ -0,0 +1,34 @@ +#include +#include + +smb1394: qcom,smb1394@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x6 0x26 0x27>; + status = "disabled"; + + smb1394_div2_cp_primary: qcom,div2_cp_pry { + compatible = "qcom,smb1394-div2-cp-primary"; + #io-channel-cells = <1>; + interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>, + <0x26 0x3 IRQ_TYPE_EDGE_RISING>, + <0x26 0x5 IRQ_TYPE_EDGE_RISING>, + <0x26 0x7 IRQ_TYPE_EDGE_RISING>, + <0x27 0x5 IRQ_TYPE_EDGE_RISING>, + <0x27 0x6 IRQ_TYPE_EDGE_RISING>, + <0x27 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "temp-shdwn", + "div2-irev", + "usbin-uv", + "usbin-ov", + "div2-ilim", + "div2-win-uv", + "div2-win-ov"; + qcom,div2-cp-min-ilim-ua = <1000000>; + status = "disabled"; + }; +}; From 06a64a404d7b4e7c0572ee49b17f2c0b2a370120 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 26 Jan 2021 11:06:12 -0800 Subject: [PATCH 0748/1809] ARM: dts: msm: Add PMIC and USB support for sdxlemur NTN3 board The sdxlemur NTN3 board contains the same PMICs as the sdxlemur MBB board, so include that file directly to make use of all its configured nodes. Change-Id: I23a34786ac0a829503d094cba852387425e1a34b --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 42f218547fd1..d628e771162b 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,7 +1,5 @@ -#include "sdxlemur-mtp.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-mtp-mbb.dtsi" &soc { }; - From 313bd117ec56afa4f3bfd9a6bfa414039433bd81 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Wed, 27 Jan 2021 11:45:42 +0800 Subject: [PATCH 0749/1809] ARM: dts: msm: set pm8350b_l1 init voltage for qrd yupik Set pm8350b_l1 init voltage to 1.2v for qrd yupik. Change-Id: I8019c6ab4eeacc153971e6e69371c2385692366d --- qcom/yupik-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 0c1f84264f7a..4d6aedc0a0ca 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -275,7 +275,7 @@ qcom,set = ; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; - qcom,init-voltage = <1100000>; + qcom,init-voltage = <1200000>; qcom,init-mode = ; }; }; From abad0027da81a008b1379309a62ba505aeff222a Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 24 Nov 2020 11:06:14 +0530 Subject: [PATCH 0750/1809] bindings: clock: Add support for MONACO clock controllers Update the GCC, GPUCC, DISPCC and debug clock controller bindings for MONACO. Change-Id: Ibb0c5723dd4ef99790655bf1258c1370de2a81cf --- bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 1 + bindings/clock/qcom,rpmcc.txt | 1 + 5 files changed, 5 insertions(+) diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 562d527e93cf..8e9b51d2ba60 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -13,6 +13,7 @@ Required properties : "qcom,sdxnightjar-debugcc" "qcom,scshrike-debugcc" "qcom,sm6150-debugcc" + "qcom,monaco-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index af3ebe5576e0..a8849c685c66 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,scshrike-dispcc-v2" "qcom,sm6150-dispcc" "qcom,sa6155-dispcc" + "qcom,monaco-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index db793721b6d4..fddfd6882952 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -37,6 +37,7 @@ Required properties : "qcom,scshrike-gcc-v2" "qcom,sm6150-gcc" "qcom,sa6155-gcc" + "qcom,monaco-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 9a62efc47ef6..bc6a3e2ce15a 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -12,6 +12,7 @@ Required properties : "qcom,scshrike-gpucc" "qcom,sm6150-gpucc", "qcom,sa6155-gpucc". + "qcom,monaco-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index dc0e0c697bdc..4799e44a087e 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -20,6 +20,7 @@ Required properties : "qcom,rpmcc-qcs404", "qcom,rpmcc" "qcom,rpmcc-holi", "qcom,rpmcc" "qcom,rpmcc-sdxnightjar", "qcom,rpmcc" + "qcom,rpmcc-monaco", "qcom,rpmcc" - #clock-cells : shall contain 1 From f331a89fafd378ea9f48b8c0353178e973f14fab Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Wed, 27 Jan 2021 15:33:13 +0530 Subject: [PATCH 0751/1809] dt-bindings: qpnp-smb5: Property to enable JEITA-ARB configuration "qcom,jeita-arb-enable" enable JEITA ARB sequence. Change-Id: Ie7089d0970444d0d9e4e6449a7b9799e680ed19f --- bindings/power/supply/qcom/qpnp-smb5.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/power/supply/qcom/qpnp-smb5.txt b/bindings/power/supply/qcom/qpnp-smb5.txt index 3b20b0c427d2..2ac6f198cf75 100644 --- a/bindings/power/supply/qcom/qpnp-smb5.txt +++ b/bindings/power/supply/qcom/qpnp-smb5.txt @@ -396,6 +396,12 @@ Charger specific properties: Value type: bool Definition: Boolean flag which when present disables FCC restriction. +- qcom,jeita-arb-enable + Usage: optional + Value type: bool + Definition: Boolean flag which indicates if JETIA ARB handling when + Vjeita > Vbatt is enabled. + ============================================= Second Level Nodes - SMB5 Charger Peripherals ============================================= From ee4a9ee90a5174847b3ba0ad081a25609ac1e883 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Wed, 27 Jan 2021 15:34:54 +0530 Subject: [PATCH 0752/1809] ARM: dts: msm: Add open loop CPR support Open loop CPR (core power reduction) is a power save feature that configs certain voltage for WLAN power rails at runtime. Firmware will read fuse and calculate the proper voltage and then send it to ICNSS driver. ICNSS driver then configs the voltage to WLAN PDC using TCS command through RPMh. This is to make sure the proper voltage can be updated during runtime instead just hardcode and vote fixed value for WLAN power rails. Change-Id: I6b04a1f840f8e7eca2a377dd7a39d16b910cde31 --- qcom/yupik.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f59b584b6c3b..cfa9d581739b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1127,8 +1127,9 @@ icnss2: qcom,wcn6750 { compatible = "qcom,wcn6750"; - reg = <0x17a10040 0x0>; - reg-names = "msi_addr"; + reg = <0x17a10040 0x0>, + <0xb2e5510 0x5c0>; + reg-names = "msi_addr", "tcs_cmd"; iommus = <&apps_smmu 0x1c00 0x1>; interrupts = , , @@ -1167,6 +1168,7 @@ qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; + qcom,cmd_db_name = "smpb7"; cnss-daemon-support; qcom,fw-prefix; vdd-cx-mx-supply = <&S7B>; From e600f3e63fb445c1e74b7a5a6030ee72ce34ace4 Mon Sep 17 00:00:00 2001 From: Gopala Krishnaiah Nuthaki Date: Wed, 27 Jan 2021 01:17:57 -0800 Subject: [PATCH 0753/1809] Revert "ARM: dts: msm: Disable pmic thermal zone cofiguration" This reverts commit 3419c3acbb47d1a3f0fd6a6f375695e17dd56b9f. Change-Id: Iaff15dd3bfbc0a87d062e59c728856d194079588 --- qcom/yupik-thermal-overlay-qrd.dtsi | 8 -------- qcom/yupik-thermal-overlay.dtsi | 8 -------- 2 files changed, 16 deletions(-) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 081e3cd5939b..4d302f1cff41 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -10,7 +10,6 @@ &thermal_zones { socd { - disable-thermal-zone; cooling-maps { socd_cpu4 { trip = <&socd_trip>; @@ -35,7 +34,6 @@ }; pm8350b-bcl-lvl0 { - disable-thermal-zone; cooling-maps { vbat_cpu4 { trip = <&b_bcl_lvl0>; @@ -60,7 +58,6 @@ }; pm8350b-bcl-lvl1 { - disable-thermal-zone; cooling-maps { vbat_cpu6 { trip = <&b_bcl_lvl1>; @@ -85,7 +82,6 @@ }; pm8350b-bcl-lvl2 { - disable-thermal-zone; cooling-maps { vbat_gpu2 { trip = <&b_bcl_lvl2>; @@ -169,7 +165,6 @@ }; pm8350b_tz { - disable-thermal-zone; cooling-maps { battery_cdev { trip = <&pm8350b_trip0>; @@ -181,7 +176,6 @@ }; pm7325_tz { - disable-thermal-zone; cooling-maps { pm7325_gpu { trip = <&pm7325_trip0>; @@ -227,7 +221,6 @@ }; pm8350c_tz { - disable-thermal-zone; cooling-maps { pm8350c_gpu { trip = <&pm8350c_trip0>; @@ -250,7 +243,6 @@ }; pmr735a_tz { - disable-thermal-zone; cooling-maps { pmr735a_pa { trip = <&pmr735a_trip0>; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index bf264b627ebf..247891c9ece0 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -10,7 +10,6 @@ &thermal_zones { socd { - disable-thermal-zone; cooling-maps { socd_cpu4 { trip = <&socd_trip>; @@ -35,7 +34,6 @@ }; pm7325b-bcl-lvl0 { - disable-thermal-zone; cooling-maps { vbat_cpu4 { trip = <&b_bcl_lvl0>; @@ -60,7 +58,6 @@ }; pm7325b-bcl-lvl1 { - disable-thermal-zone; cooling-maps { vbat_cpu6 { trip = <&b_bcl_lvl1>; @@ -85,7 +82,6 @@ }; pm7325b-bcl-lvl2 { - disable-thermal-zone; cooling-maps { vbat_gpu2 { trip = <&b_bcl_lvl2>; @@ -169,7 +165,6 @@ }; pm7325b_tz { - disable-thermal-zone; cooling-maps { battery_cdev { trip = <&pm7325b_trip0>; @@ -181,7 +176,6 @@ }; pm7325_tz { - disable-thermal-zone; cooling-maps { pm7325_gpu { trip = <&pm7325_trip0>; @@ -227,7 +221,6 @@ }; pm8350c_tz { - disable-thermal-zone; cooling-maps { pm8350c_gpu { trip = <&pm8350c_trip0>; @@ -250,7 +243,6 @@ }; pmr735a_tz { - disable-thermal-zone; cooling-maps { pmr735a_pa { trip = <&pmr735a_trip0>; From e87ce0600af8aaf4622b69192b3a54fc8e3c8435 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 29 Dec 2020 23:01:06 +0530 Subject: [PATCH 0754/1809] dt-bindings: batterydata: Add jeita-fcc-scaling related properties Add below propeties to enable and configure jeita-fcc-scaling algorithm : qcom,jeita-fcc-scaling qcom,jeita-fcc-scaling-temp-threshold qcom,jeita-scaling-min-fcc-ua All of this property needs to be set with valid values to enable jeita based fcc scaling. Change-Id: Ifa764a615f301136a1741ee412d9d10388718caa --- bindings/batterydata/batterydata.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/bindings/batterydata/batterydata.txt b/bindings/batterydata/batterydata.txt index 29b75cd47b57..734f7817d464 100644 --- a/bindings/batterydata/batterydata.txt +++ b/bindings/batterydata/batterydata.txt @@ -153,6 +153,21 @@ Profile data node optional properties: This should be in decidegree and if not specified default select value is 10 DeciDegC. +- qcom,jeita-fcc-scaling: A bool property to indicate if temperature based + jeita fcc scaling is enabled. If defined, enables + scaling of FCC based on battery-temperature. Scales + the FCC depending upon the granularity of increase in + battery temperature. +- qcom,jeita-fcc-scaling-temp-threshold: A tuple entry to allow configuring the + min and max battery temperature threshold (in DeciDegC) + for jeita fcc scaling algorithm to kick in. + +- qcom,jeita-scaling-min-fcc-ua : This value corresponds to the minimum FCC (in uA) of + the battery to be applied when battery temperature hits the max + temperature indicated it "qcom,jeita-fcc-scaling-temp-threshold". + This value is selected based on profiling after making sure that + the battery-temperature does not rise at this FCC. + Profile data node required subnodes: - qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes temperature to fcc lookup. The units for this lookup From 0e195d94836ddbe44eec32b8ab0f22d1aa8e3a34 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 3 Jun 2020 14:28:14 +0530 Subject: [PATCH 0755/1809] ARM: dts: msm: Add DT node for msm-watchdog in SM8150 Add device node for hardware msm-watchdog present in SM8150 SoC with proper bark and bite time configuration, this is needed to report bugs related to system lockups in the kernel. Change-Id: Ibf2c059278e7896cf8f625ea1f981d55a84690b8 --- qcom/sm8150.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index af788edb304f..debeed2eda24 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2238,6 +2238,18 @@ reg-names = "llcc_base", "llcc_broadcast_base"; cap-based-alloc-and-pwr-collapse; }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; }; &firmware { From 5b0090dd30279ff4344421be9d00e78cc9406ac8 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 3 Jun 2020 14:54:36 +0530 Subject: [PATCH 0756/1809] ARM: dts: msm: Add dt node for restart driver on SM8150 Add device node for msm-poweroff driver on SM8150 and populate pshold and tcsr register addresses needed for restarting the SoC. Change-Id: Iaf9524d53f501bdc3e4f5aa0966be8325dadfc16 --- qcom/sm8150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index debeed2eda24..a751493985ca 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1002,6 +1002,13 @@ interrupts = ; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 52d0e4d78faadcf4f66f6ee759375fccb44c4846 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Thu, 30 Jul 2020 21:21:46 +0530 Subject: [PATCH 0757/1809] ARM: dts: msm: Add DT node for msm-watchdog in SDMSHRIKE Add device node for hardware msm-watchdog present in SDMSHRIKE SoC with proper bark and bite time configuration, this is needed to report bugs related to system lockups in the kernel. Change-Id: I7d65fbcb6deb526fa8583af9a2f1c51cac57d436 --- qcom/sdmshrike.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index e2b30bc4fe10..5ad6c58e6051 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -881,6 +881,18 @@ cap-based-alloc-and-pwr-collapse; }; + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; From e1b682b88204c2a6f1a652aa08dca37a4ceb2b4b Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 30 Jul 2020 20:51:00 +0530 Subject: [PATCH 0758/1809] ARM: dts: msm: Add dt node for restart driver on SDMSHRIKE Add device node for msm-poweroff driver on SDMSHRIKE and populate pshold and tcsr register addresses needed for restarting the SoC. Change-Id: Iab7fa7e2000ca035b5ba79025c3eac6b7f8b6fd7 --- qcom/sdmshrike.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 5ad6c58e6051..284f386171f3 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -947,6 +947,13 @@ &mc_virt SLAVE_EBI1>; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; From ec3d4ce69ea961da0d51293fd41c557139947b59 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 16 Dec 2020 20:27:48 +0530 Subject: [PATCH 0759/1809] ARM: dts: msm: Update QSEECOM CMA region Update QSEECOM CMA region DT node to include the missing properties. Change-Id: I07ff420c21cefec77d0d20ac89dcb5de5d4651bf --- qcom/sdmshrike.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 284f386171f3..5cb3e27a8cc5 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -420,10 +420,12 @@ reg = <0x0 0x98900000 0x0 0x1400000>; }; - qseecom_mem: qseecom_region@0x9e400000 { + qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - no-map; - reg = <0x0 0x9e400000 0x0 0x1400000>; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; }; From bdb34249a279a14c84e5dfbc35b7edf5913fc4b4 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 11:48:07 +0530 Subject: [PATCH 0760/1809] ARM: dts: msm: Add core-hang detect nodes to SM8150 Add core-hang detect nodes for silver and gold cores on SM8150. Change-Id: Iccde8bfaeda5b88c205f28cbcec4af7f93ec196a --- qcom/sm8150.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index a751493985ca..67df8db0972d 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2257,6 +2257,24 @@ qcom,ipi-ping; qcom,wakeup-enable; }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18040058 0x18050058 + 0x18060058 0x18070058>; + qcom,config-arr = <0x18040060 0x18050060 + 0x18060060 0x18070060>; + }; }; &firmware { From fadc763191b37c7e481d409144bc814282b7154d Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 11:56:25 +0530 Subject: [PATCH 0761/1809] ARM: dts: msm: Add core-hang detect nodes to SDMSHRIKE Add core-hang detect nodes for silver and gold cores on SDMSHRIKE. Change-Id: Ie6f73a8bf3e5bf405b845089676fb4be0fd71cd1 --- qcom/sdmshrike.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 5cb3e27a8cc5..784e7684e9df 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1922,6 +1922,24 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18040058 0x18050058 + 0x18060058 0x18070058>; + qcom,config-arr = <0x18040060 0x18050060 + 0x18060060 0x18070060>; + }; }; #include "sdmshrike-pinctrl.dtsi" From f57cb3cf83c12e6757c74544468d367b1033749e Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 25 Jan 2021 19:36:32 +0530 Subject: [PATCH 0762/1809] ARM: dts: msm: Add support for sec mi2s for fm Add support for sec mi2s for fm in yupik. Change-Id: Ibb82de8bc1b8b9c38d6514241cd68521ed9ebf62 --- qcom/yupik-audio-overlay.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index bd8bf6cfddd2..6199203b913c 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -365,6 +365,7 @@ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,sec-mi2s-gpios = <&cdc_sec_mi2s_gpios>; asoc-codec = <&stub_codec>, <&bolero>, <&wcd937x_codec>, <&wsa883x_0221>, <&wsa883x_0222>; @@ -473,6 +474,23 @@ }; }; +&q6core { + cdc_sec_mi2s_gpios: msm_cdc_pinctrl_sec { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active + &sec_mi2s_sd0_active>; + pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep + &sec_mi2s_sd0_sleep>; + #gpio-cells = <0>; + }; +}; + +&dai_mi2s1 { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <1>; +}; + &adsp_loader { nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; From 95cfc3de4fbdd3436d4a876e1b0faeb1be147b83 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 26 Jan 2021 23:41:51 +0530 Subject: [PATCH 0763/1809] ARM: dts: msm: Add handles for PCIE clocks for Yupik PCIE cocks need to be enabled for QoS settings programming, so add PCIE clock handles. Change-Id: Iba060132a1645fb63dd75680b9a56d129966c1a0 --- qcom/yupik.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1093c241474..15b4b21b6403 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1450,7 +1450,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; @@ -1460,10 +1462,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { From 735284b9638bd2cacccc6362716f9b527a2b9b15 Mon Sep 17 00:00:00 2001 From: Laisheng Hu Date: Wed, 8 Jul 2020 18:53:14 +0800 Subject: [PATCH 0764/1809] ARM: dts: msm: Add vidc node for SM8150 Add sm8150 vidc nodes and update smmu SIDs for sm8150-v2. Change-Id: Id3860ad0d48cf96cf428b24a6c10221065d69853 --- bindings/media/video/msm-vidc.txt | 1 + qcom/sm8150-v2.dtsi | 18 +++++ qcom/sm8150-vidc.dtsi | 129 ++++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 1 + 4 files changed, 149 insertions(+) create mode 100644 qcom/sm8150-vidc.dtsi diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 80f10e86fbe2..b1f2380c06a8 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -10,6 +10,7 @@ Required properties: - "qcom,shima-vidc" : Invokes driver-specific data for SHIMA. - "qcom,holi-vidc" : Invokes driver-specific data for HOLI. - "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK. + - "qcom,sm8150-vidc" : Invokes driver specific data for SM8150. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 7dc48e572c11..d2877407f6e0 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -498,3 +498,21 @@ "kgsl_gmu_pdc_cfg", "kgsl_gmu_pdc_seq"; }; + +&msm_vidc { + qcom,allowed-clock-rates = <240000000 338000000 + 365000000 444000000 533000000>; + + non_secure_cb { + iommus = <&apps_smmu 0x2300 0x60>; + }; + secure_bitstream_cb { + iommus = <&apps_smmu 0x2301 0x4>; + }; + secure_pixel_cb { + iommus = <&apps_smmu 0x2303 0x20>; + }; + secure_non_pixel_cb { + iommus = <&apps_smmu 0x2304 0x60>; + }; +}; diff --git a/qcom/sm8150-vidc.dtsi b/qcom/sm8150-vidc.dtsi new file mode 100644 index 000000000000..06591993f109 --- /dev/null +++ b/qcom/sm8150-vidc.dtsi @@ -0,0 +1,129 @@ +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,sm8150-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* LLCC Info */ + cache-slice-names = "vidsc0", "vidsc1"; + + /* Supply */ + iris-ctl-supply = <&mvsc_gdsc>; + vcodec-supply = <&mvs0_gdsc>; + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axic", "gcc_video_axi0", + "gcc_video_axi1", "core_clk", "vcodec_clk", + "cvp_clk"; + clocks = <&gcc GCC_VIDEO_AXIC_CLK>, + <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_MVS1_CORE_CLK>; + + qcom,proxy-clock-names = "gcc_video_axic", + "gcc_video_axi0", "gcc_video_axi1", + "core_clk", "vcodec_clk", "cvp_clk"; + + resets = <&gcc GCC_VIDEO_AXIC_CLK_BCR>, + <&videocc VIDEO_CC_MVSC_CORE_CLK_BCR>, + <&gcc GCC_VIDEO_AXI0_CLK_BCR>, + <&gcc GCC_VIDEO_AXI1_CLK_BCR>; + + reset-names = "video_axi_reset", "video_core_reset", + "video_axi0_reset", "video_axi1_reset"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1>; + qcom,allowed-clock-rates = <225000000 300000000 + 365000000 432000000 480000000>; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr", "venus-arm9-ddr", "venus-llcc"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 + &gem_noc SLAVE_LLCC>; + + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 6533000 + 1000 1000 + 1000 6533000>; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x1300 0x60>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + dma-coherent-hint-cached; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x1304 0x60>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x1301 0x4>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x1303 0x20>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + /* Memory Heaps */ + qcom,msm-vidc,mem_cdsp { + compatible = "qcom,msm-vidc,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index af788edb304f..5cacb452132c 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2256,6 +2256,7 @@ #include "sm8150-smp2p.dtsi" #include "sm8150-gdsc.dtsi" #include "msm-arm-smmu-sm8150.dtsi" +#include "sm8150-vidc.dtsi" &emac_gdsc { status = "ok"; From 98697c2d65e4f6ebca7e255d161e09742ecc37c2 Mon Sep 17 00:00:00 2001 From: Laisheng Hu Date: Wed, 9 Sep 2020 12:30:24 +0800 Subject: [PATCH 0765/1809] ARM: dts: msm: Add vidc node for SA8195 Add sa8195 vidc nodes and update smmu SIDs for sa8195-v2. Change-Id: I9c597ec04e9e05f43446f94283b95baa7ee43989 --- bindings/media/video/msm-vidc.txt | 1 + qcom/sa8195-vidc.dtsi | 129 ++++++++++++++++++++++++++++++ qcom/sdmshrike-v2.dtsi | 18 +++++ qcom/sdmshrike.dtsi | 1 + 4 files changed, 149 insertions(+) create mode 100644 qcom/sa8195-vidc.dtsi diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index b1f2380c06a8..9e73df7c1eea 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -11,6 +11,7 @@ Required properties: - "qcom,holi-vidc" : Invokes driver-specific data for HOLI. - "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK. - "qcom,sm8150-vidc" : Invokes driver specific data for SM8150. + - "qcom,scshrike-vidc" : Invokes driver specific data for SA8195. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL diff --git a/qcom/sa8195-vidc.dtsi b/qcom/sa8195-vidc.dtsi new file mode 100644 index 000000000000..641aa7aa976a --- /dev/null +++ b/qcom/sa8195-vidc.dtsi @@ -0,0 +1,129 @@ +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,scshrike-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* LLCC Info */ + cache-slice-names = "vidsc0", "vidsc1"; + + /* Supply */ + iris-ctl-supply = <&mvsc_gdsc>; + vcodec-supply = <&mvs0_gdsc>; + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axic", "gcc_video_axi0", + "gcc_video_axi1", "core_clk", "vcodec_clk", + "cvp_clk"; + clocks = <&gcc GCC_VIDEO_AXIC_CLK>, + <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_MVS1_CORE_CLK>; + + qcom,proxy-clock-names = "gcc_video_axic", + "gcc_video_axi0", "gcc_video_axi1", + "core_clk", "vcodec_clk", "cvp_clk"; + + resets = <&gcc GCC_VIDEO_AXIC_CLK_BCR>, + <&videocc VIDEO_CC_MVSC_CORE_CLK_BCR>, + <&gcc GCC_VIDEO_AXI0_CLK_BCR>, + <&gcc GCC_VIDEO_AXI1_CLK_BCR>; + + reset-names = "video_axi_reset", "video_core_reset", + "video_axi0_reset", "video_axi1_reset"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1>; + qcom,allowed-clock-rates = <225000000 300000000 + 365000000 432000000 480000000>; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr", "venus-arm9-ddr", "venus-llcc"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 + &gem_noc SLAVE_LLCC>; + + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 6533000 + 1000 1000 + 1000 6533000>; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x1300 0x60>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + dma-coherent-hint-cached; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x1304 0x60>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x1301 0x4>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x1303 0x20>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + /* Memory Heaps */ + qcom,msm-vidc,mem_cdsp { + compatible = "qcom,msm-vidc,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; +}; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index 83ef5838f7f3..8390c82107c9 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -153,3 +153,21 @@ "kgsl_gmu_pdc_cfg", "kgsl_gmu_pdc_seq"; }; + +&msm_vidc { + qcom,allowed-clock-rates = <240000000 338000000 + 365000000 444000000 533000000>; + + non_secure_cb { + iommus = <&apps_smmu 0x2300 0x60>; + }; + secure_bitstream_cb { + iommus = <&apps_smmu 0x2301 0x4>; + }; + secure_pixel_cb { + iommus = <&apps_smmu 0x2303 0x20>; + }; + secure_non_pixel_cb { + iommus = <&apps_smmu 0x2304 0x60>; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index e2b30bc4fe10..2c40c5be64e5 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1915,6 +1915,7 @@ #include "sa8195-ssc-qupv3.dtsi" #include "sa8195-usb.dtsi" #include "sdmshrike-gpu.dtsi" +#include "sa8195-vidc.dtsi" &firmware { scm { From 44670bf62ab6ad467194d8f892615909156cc4a2 Mon Sep 17 00:00:00 2001 From: Yi Huang Date: Wed, 23 Sep 2020 16:30:09 +0800 Subject: [PATCH 0766/1809] ARM: dts: msm: include camera devicetree for sa8195 Add camera devicetree for sa8195 target. Change-Id: I4fc0d6d0015f67bf9baf4291ab32869a6e682b38 --- qcom/sa8195p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index ee110fef6f8f..3c30056eee9f 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -1,6 +1,8 @@ #include "sdmshrike-v2.dtsi" #include "sa8195-pmic.dtsi" #include "sa8195p-pcie.dtsi" +#include "camera/sa8195p-camera.dtsi" +#include "camera/sa8195p-camera-sensor.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P"; From f827086d62cb53047972b3b1fb89de81b1ca5cb9 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Fri, 18 Dec 2020 12:11:06 -0800 Subject: [PATCH 0767/1809] ARM: dts: msm: Disable PMX65 VBUS_DET on sdxlemur MTP-MBB and RCM-RC boards On these boards, VBUS detection is through PM7250B, so disable the VBUS_DET peripheral. Change-Id: Iddb2b3843238707d404e96203af231b696dadc7f --- qcom/sdxlemur-mtp-mbb.dtsi | 4 ++++ qcom/sdxlemur-rcm-rc.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7ef7a7462fd6..e3536f60a70b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -253,3 +253,7 @@ io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; io-channel-names = "chg_type"; }; + +&vbus_detect { + status = "disabled"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index ba8bed5220c2..25294b583251 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -278,3 +278,7 @@ io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; io-channel-names = "chg_type"; }; + +&vbus_detect { + status = "disabled"; +}; From 04430b635ceb0e294fbc7430070e390066388f83 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Wed, 27 Jan 2021 19:48:20 +0530 Subject: [PATCH 0768/1809] ARM: dts: msm: add yupik VM ion chages Add Yupik VM ion changes for the msm-buf sharing TUI usecases. Change-Id: I347a6692d6f59aa32fdcb9479a921843b84bc43a --- qcom/yupik-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index 11ed738c5647..121481de8b18 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -287,3 +287,4 @@ status = "disabled"; }; }; +#include "lahaina-vm-ion.dtsi" From f1d4871ea3dff96eb0a07c81df934020e73b8311 Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Thu, 28 Jan 2021 15:20:26 +0530 Subject: [PATCH 0769/1809] ARM: dts: msm: Enable io-coherence hw support for yupik Enable dma coherence cache hint for yupik. Change-Id: I70a12310211b9ea57c767206d4599ebf755655ce --- qcom/yupik-vidc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-vidc.dtsi b/qcom/yupik-vidc.dtsi index 8c207620b265..a562c3aca444 100644 --- a/qcom/yupik-vidc.dtsi +++ b/qcom/yupik-vidc.dtsi @@ -54,7 +54,7 @@ qcom,iommu-faults = "non-fatal"; buffer-types = <0xfff>; virtual-addr-pool = <0x25800000 0xba800000>; - #dma-coherent-hint-cached; + dma-coherent-hint-cached; }; secure_non_pixel_cb { From e9a8c911deb47ec3c8613b02c06b824b99e1d450 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Thu, 28 Jan 2021 15:14:40 +0800 Subject: [PATCH 0770/1809] ARM: dts: msm: Add support for Lahaina HHG HSP Pro Add device-tree support for Lahaina HHG HSP Pro platform. Change-Id: If278b60441c46bd7f6d5189128023ead76f3e406 --- qcom/Makefile | 3 +++ qcom/lahaina-hhg-hsp-pro-overlay.dts | 10 ++++++++++ qcom/lahaina-hhg-hsp-pro.dtsi | 9 +++++++++ qcom/lahaina-v2.1-hhg-hsp-pro.dts | 10 ++++++++++ 4 files changed, 32 insertions(+) create mode 100644 qcom/lahaina-hhg-hsp-pro-overlay.dts create mode 100644 qcom/lahaina-hhg-hsp-pro.dtsi create mode 100644 qcom/lahaina-v2.1-hhg-hsp-pro.dts diff --git a/qcom/Makefile b/qcom/Makefile index ddee39dfa495..cd23acc8198a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -8,6 +8,7 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \ lahaina-atp-overlay.dtbo \ lahaina-hdk-overlay.dtbo \ lahaina-hhg-overlay.dtbo \ + lahaina-hhg-hsp-pro-overlay.dtbo \ lahaina-qrd-hsp-overlay.dtbo \ lahaina-qrd-module-overlay.dtbo \ lahainap-mtp-overlay.dtbo \ @@ -28,6 +29,7 @@ lahaina-cdp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-atp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-hdk-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-hhg-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb +lahaina-hhg-hsp-pro-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-qrd-hsp-overlay.dtbo-base := lahaina.dtb lahaina-qrd-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-qrd-module-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb @@ -77,6 +79,7 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-v2.1-atp.dtb \ lahaina-v2.1-hdk.dtb \ lahaina-v2.1-hhg.dtb \ + lahaina-v2.1-hhg-hsp-pro.dtb \ lahaina-v2.1-qrd.dtb \ lahaina-v2.1-qrd-module.dtb \ lahainap-v2.1-mtp.dtb \ diff --git a/qcom/lahaina-hhg-hsp-pro-overlay.dts b/qcom/lahaina-hhg-hsp-pro-overlay.dts new file mode 100644 index 000000000000..0fd700376d25 --- /dev/null +++ b/qcom/lahaina-hhg-hsp-pro-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-hhg-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina HHG-HSP-PRO"; + compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; + qcom,board-id = <0x1001f 0x02>; +}; diff --git a/qcom/lahaina-hhg-hsp-pro.dtsi b/qcom/lahaina-hhg-hsp-pro.dtsi new file mode 100644 index 000000000000..d7ced990f842 --- /dev/null +++ b/qcom/lahaina-hhg-hsp-pro.dtsi @@ -0,0 +1,9 @@ +#include "lahaina-hhg.dtsi" +&bluetooth { + pinctrl-1 = <&wcnss_en_sleep>; + qcom,xo-reset-gpio = <&tlmm 201 0>; /* XO */ +}; + +&wlan { + qcom,xo-clk-gpio = <&tlmm 201 0>; +}; diff --git a/qcom/lahaina-v2.1-hhg-hsp-pro.dts b/qcom/lahaina-v2.1-hhg-hsp-pro.dts new file mode 100644 index 000000000000..dce431e5d4ed --- /dev/null +++ b/qcom/lahaina-v2.1-hhg-hsp-pro.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-v2.1.dtsi" +#include "lahaina-hhg-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina HHG-HSP-PRO"; + compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; + qcom,board-id = <0x1001f 0x02>; +}; From 64e07411e5351bab002304246da8c0d5d03ca5c4 Mon Sep 17 00:00:00 2001 From: Dundi Raviteja Date: Thu, 28 Jan 2021 18:37:22 +0530 Subject: [PATCH 0771/1809] ARM: dts: msm: Add icnss driver for scuba Add icnss driver for scuba platform. Change-Id: If6ecbc91a47d28b3f1aa7ef5014c72eb2353a50a --- qcom/scuba-iot.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 14fc3b99340f..109c060f6216 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -779,6 +779,11 @@ dcc: dcc_v2@1be2000 { interrupt-controller; #interrupt-cells = <2>; }; + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { @@ -877,6 +882,43 @@ dcc: dcc_v2@1be2000 { qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1A0 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + vdd-cx-mx-supply = <&L7A>; + vdd-1.8-xo-supply = <&L13A>; + vdd-1.3-rfa-supply = <&L10A>; + vdd-3.3-ch0-supply = <&L22A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; }; &pm2250_gpios { From 58097195c4d2b95aaad8679357c75b1f28d29e8b Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 28 Jan 2021 19:32:37 +0530 Subject: [PATCH 0772/1809] ARM: dts: msm: Change wsa spkr node for yupik wsa Enable proper wsa node for yupik wsa. Change-Id: I57156d3f295cd729f18d5e64d0bcb723e476f055 --- qcom/yupik-audio-overlay.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index bd8bf6cfddd2..e41be7128e65 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -172,7 +172,7 @@ wsa883x_0221: wsa883x@02170221 { compatible = "qcom,wsa883x"; reg = <0x2 0x2170221>; - qcom,spkr-sd-n-node = <&wsa_spkr_en2>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; qcom,bolero-handle = <&bolero>; cdc-vdd-1p8-supply = <&L18B>; @@ -185,7 +185,7 @@ wsa883x_0222: wsa883x@02170222 { compatible = "qcom,wsa883x"; reg = <0x2 0x2170222>; - qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + qcom,spkr-sd-n-node = <&wsa_spkr_en2>; qcom,bolero-handle = <&bolero>; cdc-vdd-1p8-supply = <&L18B>; From fa8c23554c87e790ba76622b202577010d464d03 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 4 Jan 2021 19:55:57 +0530 Subject: [PATCH 0773/1809] ARM: dts: msm: Enable display port for yupik Enable display port for yupik. Change-Id: Ib02b60b56aa40c28b8f463e86ba467e1367d156c --- qcom/yupik-audio-overlay.dtsi | 6 ++++-- qcom/yupik-audio.dtsi | 2 +- qcom/yupik-qrd.dtsi | 6 ++++-- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index bd8bf6cfddd2..e9e0119968ef 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -367,10 +367,12 @@ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; asoc-codec = <&stub_codec>, <&bolero>, <&wcd937x_codec>, - <&wsa883x_0221>, <&wsa883x_0222>; + <&wsa883x_0221>, <&wsa883x_0222>, + <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd937x_codec", - "wsa-codec1", "wsa-codec2"; + "wsa-codec1", "wsa-codec2", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <2>; qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>; diff --git a/qcom/yupik-audio.dtsi b/qcom/yupik-audio.dtsi index be6ee9166221..6800853aaaf6 100644 --- a/qcom/yupik-audio.dtsi +++ b/qcom/yupik-audio.dtsi @@ -162,7 +162,7 @@ qcom,mi2s-audio-intf = <1>; qcom,auxpcm-audio-intf = <1>; qcom,wcn-bt = <1>; - qcom,ext-disp-audio-rx = <0>; + qcom,ext-disp-audio-rx = <1>; qcom,afe-rxtx-lb = <0>; clock-names = "lpass_audio_hw_vote"; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 4d6aedc0a0ca..1739bd0ccf27 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -482,10 +482,12 @@ asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0222>; + <&wsa883x_0222>, + <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", - "wsa-codec2"; + "wsa-codec2", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <1>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; From 5551349faaafd250f66c4a427aeb6b03ef46602a Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 29 Jan 2021 11:26:43 +0800 Subject: [PATCH 0774/1809] ARM: dts: msm: Add dma-coherent for tmc-etr on yupik This is to enable dma-coherent for tmc-etr to aovid cache flush issue. Change-Id: Ic7a707572d4916fc330ba8663718deb0273573cb --- qcom/yupik-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index c910fe539c8d..f2b1e6fcdb65 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -153,6 +153,7 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + dma-coherent; qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; From fb7c056d38a2c85b2396fbaf47c1240c1b2c63cd Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Mon, 18 Jan 2021 17:16:14 +0800 Subject: [PATCH 0775/1809] ARM: dts: msm: Removed wdog for sdxnightjar pil modem Removed unrequested wdog interrupt for sdxnightjar. Change-Id: I42f9786b45715648b3b29b0affbd92c32701bfcd --- qcom/sdxnightjar.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 00ea3f6a2f57..07378eed1518 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -170,15 +170,13 @@ qcom,reset-clk; qcom,sequential-fw-load; - interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, - <&modem_smp2p_in 0 0>, + interrupts-extended = <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 3 0>, <&modem_smp2p_in 7 0>; - interrupt-names = "qcom,wdog", - "qcom,err-fatal", + interrupt-names = "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", From c90692d901769b4863c472abb0e405f58a45415e Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Fri, 29 Jan 2021 15:36:15 +0530 Subject: [PATCH 0776/1809] ARM: dts: msm: Enable pil nodes for scuba Add pil nodes for scuba on 5.4 kernel. Change-Id: Id86387e56ffb8730060c00be8717014f2dbf03c8 --- qcom/scuba-iot.dtsi | 98 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 14fc3b99340f..4af2e2999c90 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. SCUBA"; @@ -495,7 +496,6 @@ qcom,pet-time = <9360>; qcom,ipi-ping; qcom,wakeup-enable; - status = "disabled"; }; dcc: dcc_v2@1be2000 { @@ -661,6 +661,102 @@ dcc: dcc_v2@1be2000 { }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; + }; + + qcom,lpass@ab00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xab00000 0x00100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <1>; + qcom,minidump-id = <5>; + qcom,ssctl-instance-id = <0x14>; + qcom,pas-id = <1>; + qcom,smem-id = <423>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + pil_modem: qcom,mss@6080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x6080000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + qcom,sequential-fw-load; + + /* Inputs from mss */ + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom_scm: qcomscm { + compatible = "qcom,scm"; + }; + qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; From aa625017ef6d9c3c5cf2a11a642f7f2beb50d0da Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 21 Jan 2021 13:02:56 +0530 Subject: [PATCH 0777/1809] ARM: dts: msm: Vote vccq2 via vccq to support GKI vccq2 is supplied by eLDO and this eLDO is controlled via L9B regulator which only supports max 1.2V but since for gki build QTI flag is disabled vote for vccq2 regulator is taking default values from driver and not from dt. Hence use vccq to vote on L9B to enable eLDO for UFS2.2 devices since L9B is common regulator as both vccq & vccq2. Change-Id: Icf8c9f169d693a6dad608c16baa9ed9666905430 --- qcom/yupik-atp.dtsi | 26 ++++++++++++++++---------- qcom/yupik-idp.dtsi | 26 ++++++++++++++++---------- qcom/yupik-qrd.dtsi | 26 ++++++++++++++++---------- 3 files changed, 48 insertions(+), 30 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 45631c00e0c6..cbac0b4584c9 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -70,20 +70,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 291879aeb65d..7b366fdab1b2 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -71,20 +71,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 4d6aedc0a0ca..d95343329818 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -72,20 +72,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; From d39c394b1593c982e3a566d27e7729c9885962cf Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 29 Jan 2021 15:52:27 +0530 Subject: [PATCH 0778/1809] Revert "ARM: dts: msm: Limit max-frequency for eMMC and SD card" Running into issues in the deferred scaling path with this change. This reverts commit 3f7ca5d828aa125c7cf88f2b9651b73e3d88238d. Change-Id: Iaa9ef890770cdcb710584f3327254c6b7b8b5eb6 --- qcom/holi.dtsi | 8 -------- qcom/lahaina.dtsi | 4 ---- qcom/sdxlemur-cdp.dtsi | 4 ---- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 4 ---- qcom/sdxlemur-mtp.dtsi | 4 ---- qcom/sdxlemur-rcm-pcie-ep.dtsi | 4 ---- qcom/sdxlemur-rcm-rc.dtsi | 4 ---- qcom/shima.dtsi | 8 -------- qcom/yupik.dtsi | 8 -------- 9 files changed, 48 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 61b576e64edb..8341ad465c55 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2799,10 +2799,6 @@ non-removable; supports-cqe; - no-sd; - no-sdio; - max-frequency = <192000000>; - qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2867,10 +2863,6 @@ iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "bypass"; - no-mmc; - no-sdio; - max-frequency = <202000000>; - qcom,devfreq,freq-table = <50000000 202000000>; status = "disabled"; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 0026af8bfed0..d261cf1f5436 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3238,10 +3238,6 @@ <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; - no-mmc; - no-sdio; - max-frequency = <202000000>; - /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642C 0xA800 0x10 0x2C010800 0x80040868>; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 92c6a574449f..4f802df82626 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -25,10 +25,6 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - no-mmc; - no-sdio; - max-frequency = <200000000>; - cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index efb7a28127fe..d1848edd40a0 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -15,10 +15,6 @@ non-removable; supports-cqe; - no-sd; - no-sdio; - max-frequency = <192000000>; - vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 570000>; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index ef9a62296e68..586d9c3fe0dd 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -24,10 +24,6 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - no-mmc; - no-sdio; - max-frequency = <200000000>; - cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index 1ac4e8231be4..e61e86ac8459 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -23,9 +23,5 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - no-mmc; - no-sdio; - max-frequency = <200000000>; - cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index ba8bed5220c2..aab84f4ef1c2 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -51,10 +51,6 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - no-mmc; - no-sdio; - max-frequency = <200000000>; - cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 6f18769248ba..1bd9b8c51413 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1821,10 +1821,6 @@ non-removable; supports-cqe; - no-sd; - no-sdio; - max-frequency = <192000000>; - qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -1890,10 +1886,6 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; - no-mmc; - no-sdio; - max-frequency = <202000000>; - qcom,devfreq,freq-table = <50000000 202000000>; status = "disabled"; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a5ea5979c4b1..870ee25e854c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2734,10 +2734,6 @@ non-removable; supports-cqe; - no-sd; - no-sdio; - max-frequency = <192000000>; - qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2805,10 +2801,6 @@ qcom,devfreq,freq-table = <50000000 202000000>; - no-mmc; - no-sdio; - max-frequency = <202000000>; - status = "disabled"; qos0 { From 1355d4580d56555926d3f0f6c3848c8f12756b52 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sun, 30 Aug 2020 20:07:44 +0530 Subject: [PATCH 0779/1809] ARM: dts: msm: Add clock controllers and gdsc nodes for SM6150 Add camcc, dispcc, gcc, gpucc, videocc, scc clock controller nodes to facilitate clients to request and operate on clocks. Change-Id: I8f426b09ff6c6d13ab65f574cf669b53fd8f2ab1 --- qcom/sa6155.dtsi | 28 +++++ qcom/sa6155p.dtsi | 28 +++++ qcom/sm6150-gdsc.dtsi | 186 ++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 245 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 487 insertions(+) create mode 100644 qcom/sm6150-gdsc.dtsi diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 4765299d653f..5dad61ae51e4 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -7,3 +7,31 @@ qcom,msm-name = "SA6155"; qcom,msm-id = <384 0x10000>; }; + +&gcc { + compatible = "qcom,sa6155-gcc", "syscon"; + /delete-property/ protected-clocks; +}; + +&camcc { + compatible = "qcom,sa6155-camcc", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&dispcc { + compatible = "qcom,sa6155-dispcc", "syscon"; +}; + +&gpucc { + compatible = "qcom,sa6155-gpucc", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&scc { + vdd_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&videocc { + compatible = "qcom,sa6155-videocc", "syscon"; +}; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 4b2c022d2cb4..19bc2b109289 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -19,3 +19,31 @@ /delete-node/ rpmh-regulator-ldoc18; /delete-node/ bt_wcn3990; }; + +&gcc { + compatible = "qcom,sa6155-gcc", "syscon"; + /delete-property/ protected-clocks; +}; + +&camcc { + compatible = "qcom,sa6155-camcc", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&dispcc { + compatible = "qcom,sa6155-dispcc", "syscon"; +}; + +&gpucc { + compatible = "qcom,sa6155-gpucc", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&scc { + vdd_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&videocc { + compatible = "qcom,sa6155-videocc", "syscon"; +}; diff --git a/qcom/sm6150-gdsc.dtsi b/qcom/sm6150-gdsc.dtsi new file mode 100644 index 000000000000..da82010fa04f --- /dev/null +++ b/qcom/sm6150-gdsc.dtsi @@ -0,0 +1,186 @@ +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + reg = <0x106004 0x4>; + regulator-name = "emac_gdsc"; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "pcie_0_gdsc"; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "ufs_phy_gdsc"; + status = "disabled"; + }; + + usb20_sec_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + reg = <0x1a6004 0x4>; + regulator-name = "usb20_sec_gdsc"; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + regulator-name = "usb30_prim_gdsc"; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + reg = <0x17d040 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + reg = <0x17d044 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + reg = <0x17d048 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + reg = <0x17d04c 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "qcom,gdsc"; + reg = <0xad06004 0x4>; + regulator-name = "bps_gdsc"; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + reg = <0xad09004 0x4>; + regulator-name = "ife_0_gdsc"; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + reg = <0xad0a004 0x4>; + regulator-name = "ife_1_gdsc"; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + reg = <0xad07004 0x4>; + regulator-name = "ipe_0_gdsc"; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "qcom,gdsc"; + reg = <0xad0b134 0x4>; + regulator-name = "titan_top_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + reg = <0xaf03000 0x4>; + regulator-name = "mdss_core_gdsc"; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + reg = <0x509106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + reg = <0x509100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + reg = <0xab00874 0x4>; + regulator-name = "vcodec0_gdsc"; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + reg = <0xab00814 0x4>; + regulator-name = "venus_gdsc"; + status = "disabled"; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 07921d34a10e..930b10a2c3db 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1,5 +1,11 @@ #include #include +#include +#include +#include +#include +#include +#include #include / { @@ -615,6 +621,38 @@ interrupt-controller; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + scc_pll: scc_pll { + compatible = "fixed-clock"; + clock-frequency = <600000000>; + clock-output-names = "scc_pll"; + #clock-cells = <0>; + }; + + scc_pll_out_aux: scc_pll_out_aux { + compatible = "fixed-factor-clock"; + clock-output-names = "scc_pll_out_aux"; + clocks = <&scc_pll>; + clock-mult = <1>; + clock-div = <2>; + #clock-cells = <0>; + }; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; @@ -714,9 +752,216 @@ , ; }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm6150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + protected-clocks = , + , + , + , + , + , + ; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sm6150-gpucc", "syscon"; + reg = <0x5090000 0x9000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: clock-controller@62b10000 { + compatible = "qcom,sa6155-scc", "syscon"; + reg = <0x62b10000 0x30000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, <&scc_pll>, + <&scc_pll_out_aux>; + clock-names = "bi_tcxo", "sleep_clk", + "scc_pll", "scc_pll_out_aux"; + #clock-cells = <1>; + #reset-cells = <1>; + status = "disabled"; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm6150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm6150-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc>; + qcom,videocc = <&videocc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; }; #include "sm6150-qupv3.dtsi" #include "sm6150-pinctrl.dtsi" #include "sm6150-pm.dtsi" #include "sm6150-regulator.dtsi" +#include "sm6150-gdsc.dtsi" + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb20_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&titan_top_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + clock-names = "core_root_clk"; + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>; + qcom,force-enable-root-clk; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; From f7535ce9b8997f9b8b1816205f95691027426a05 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 3 Sep 2020 11:02:41 +0530 Subject: [PATCH 0780/1809] ARM: dts: msm: Add cpufreq HW device node SM6150 Add cpufreq HW device node to scale 6 domain-0 & 2 domain-1 cores on SM6150 SoCs. Change-Id: I8da676df93afabb9820e4a270e9cb401658152de --- qcom/sm6150.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 930b10a2c3db..92a12a3be8f3 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -36,6 +36,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -74,6 +75,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "arm,arch-cache"; @@ -107,6 +109,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "arm,arch-cache"; @@ -139,6 +142,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "arm,arch-cache"; @@ -171,6 +175,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "arm,arch-cache"; @@ -203,6 +208,7 @@ capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0 6>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "arm,arch-cache"; @@ -235,6 +241,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x10000>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1 2>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; @@ -276,6 +283,7 @@ capacity-dmips-mhz = <1740>; cache-size = <0x10000>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1 2>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "arm,arch-cache"; @@ -862,6 +870,15 @@ clock-names = "xo_clk_src"; #clock-cells = <1>; }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <2>; + }; }; #include "sm6150-qupv3.dtsi" From 8909f4988ec4039d21bb2be79fd011124c2cfb6b Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Wed, 25 Nov 2020 10:56:06 +0530 Subject: [PATCH 0781/1809] ARM: dts: msm: Add GCC clock node and GDSCs for MONACO GCC clock nodes is required for clocks client to request, so add support for the same. Also add the GDSCs required by clients for Monaco. Change-Id: Ifa435be1d6482c6472f2d1c1ce17e155c9a7021c --- qcom/monaco-gdsc.dtsi | 12 ++++++------ qcom/monaco-rumi.dtsi | 4 ++++ qcom/monaco.dtsi | 25 +++++++++++++++++++++---- 3 files changed, 31 insertions(+), 10 deletions(-) diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi index e1bf1597ede3..f527f93bf3b1 100644 --- a/qcom/monaco-gdsc.dtsi +++ b/qcom/monaco-gdsc.dtsi @@ -1,35 +1,35 @@ &soc { /* GDSCs in GCC */ gcc_camss_top_gdsc: qcom,gdsc@1458004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x1458004 0x4>; regulator-name = "gcc_camss_top_gdsc"; status = "disabled"; }; gcc_usb20_prim_gdsc: qcom,gdsc@141c004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x141c004 0x4>; regulator-name = "gcc_usb20_prim_gdsc"; status = "disabled"; }; gcc_vcodec0_gdsc: qcom,gdsc@14580a8 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x14580a8 0x4>; regulator-name = "gcc_vcodec0_gdsc"; status = "disabled"; }; gcc_venus_gdsc: qcom,gdsc@1458084 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x1458084 0x4>; regulator-name = "gcc_venus_gdsc"; status = "disabled"; }; hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x147d078 0x4>; regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; qcom,no-status-check-on-disable; @@ -37,7 +37,7 @@ }; hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x147d074 0x4>; regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; qcom,no-status-check-on-disable; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index aa3e9f57a73b..00444217e4c5 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -13,4 +13,8 @@ }; +&gcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; +}; + #include "monaco-stub-regulator.dtsi" diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3742aa953dc7..60a8d4f7089d 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -532,7 +532,7 @@ bi_tcxo: bi_tcxo { compatible = "fixed-factor-clock"; clock-mult = <1>; - clock-div = <1>; + clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; @@ -540,7 +540,7 @@ bi_tcxo_ao: bi_tcxo_ao { compatible = "fixed-factor-clock"; clock-mult = <1>; - clock-div = <1>; + clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; @@ -553,8 +553,15 @@ }; gcc: clock-controller@1410000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,monaco-gcc", "syscon"; + reg = <0x1400000 0x1e0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -824,6 +831,7 @@ #include "monaco-pinctrl.dtsi" #include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" +#include "monaco-stub-regulator.dtsi" #include "monaco-gdsc.dtsi" #include "monaco-qupv3.dtsi" @@ -832,38 +840,47 @@ }; &gcc_camss_top_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb20_prim_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_vcodec0_gdsc { qcom,support-hw-trigger; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_venus_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &mdss_core_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; From de4c8301e52a6a391e0fcaae96ab42da355c46d7 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Fri, 29 Jan 2021 20:19:04 +0530 Subject: [PATCH 0782/1809] ARM: dts: msm: Add tzone-names for yupik GPU Add GPU tzone-names to get the GPU temperature on yupik. Change-Id: Id28577422dabfe521d09ff6b4b32f6e8245e38d2 --- qcom/yupik-gpu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 322b32d31197..1ace5580b638 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -46,6 +46,8 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From 70a852171b3b6ced24cab23d46818ca8121954ed Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Fri, 29 Jan 2021 20:33:27 +0530 Subject: [PATCH 0783/1809] ARM: dts: msm: Add ddr qos devfreq device to yupik gpu This is used to set DDR qos level for GPU bandwidth votes for better performance. Change-Id: I553f57babc61db9a7fc1af9e1047df6f3240f270 --- qcom/yupik-gpu.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 322b32d31197..cc35a1394e48 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -8,6 +8,13 @@ memory-region = <&pil_gpu_micro_code_mem>; }; + kgsl_ddr_qos: qcom,kgsl-ddr-qos { + compatible = "qcom,devfreq-qoslat"; + governor = "powersave"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + msm_gpu: qcom,kgsl-3d0@3d00000 { compatible = "qcom,kgsl-3d0"; status = "ok"; From 5f43cec3656ab2d983f8b3bddad1159f66fa09fb Mon Sep 17 00:00:00 2001 From: Anil Kumar Kanakanti Date: Fri, 29 Jan 2021 22:51:07 +0530 Subject: [PATCH 0784/1809] ARM: dts: msm: Add camera mux gpio support Add camera mux gpio support to support JD1+GC630 DC. Change-Id: I600a6ed2ca50919337f6639e574ee26b8a326e99 --- qcom/yupik-pinctrl.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 7a6d1a6a7f15..14f5da4dad87 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1592,6 +1592,35 @@ }; }; + cam_sensor_active_mux: cam_sensor_active_mux { + /* GC630 bypass mux */ + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_mux: cam_sensor_suspend_mux { + /* GC630 bypass mux */ + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + cci0_active: cci0_active { mux { /* DATA, CLK */ From 376ea4e15651f73dbcb33860aa033bf8dfa2dff2 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Fri, 29 Jan 2021 11:58:18 +0530 Subject: [PATCH 0785/1809] ARM: dts: msm: Enable SMMU S1 for WLAN Enable SMMU S1 for WLAN adn add dma-coherent flag for enabling IO-coherency. Change-Id: I10b8dc81f94a3d77e517504dd07ab4eae9ed4e73 --- qcom/yupik.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6be910929dec..a30931465a30 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1128,8 +1128,9 @@ icnss2: qcom,wcn6750 { compatible = "qcom,wcn6750"; reg = <0x17a10040 0x0>, + <0xb0000000 0x10000>, <0xb2e5510 0x5c0>; - reg-names = "msi_addr", "tcs_cmd"; + reg-names = "msi_addr", "smmu_iova_ipa", "tcs_cmd"; iommus = <&apps_smmu 0x1c00 0x1>; interrupts = , , @@ -1164,12 +1165,13 @@ , ; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; qcom,cmd_db_name = "smpb7"; cnss-daemon-support; + dma-coherent; qcom,fw-prefix; vdd-cx-mx-supply = <&S7B>; qcom,vdd-cx-mx-config = <824000 1120000 0 0 1>; From d1969c710068445f827d716ebdf153a3fe7780e1 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Sat, 30 Jan 2021 07:21:42 +0800 Subject: [PATCH 0786/1809] dt-bindings: max31760: Add description for the fan cooling device Update the documentation to reflect the cooling device behavior of the max31760 fan controller. Change-Id: I7149329eae88c6f888e2cf383c186266d940b1cb --- bindings/thermal/max31760.txt | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/bindings/thermal/max31760.txt b/bindings/thermal/max31760.txt index db27cdbe5b0d..ee3e813ef7b5 100644 --- a/bindings/thermal/max31760.txt +++ b/bindings/thermal/max31760.txt @@ -1,10 +1,9 @@ Bindings for the Maxim MAX31760 Intelligent Fan Controller ========================================================== -The Maxim MAX31760 is a i2c device providing closed-loop, multi-channel fan -management with temperature. Various fan control features are provided, -including PWM frequency control, temperature hysteresis, dual tachometer -measurements, and fan health monitoring. +The Maxim MAX31760 is a i2c device and will register as a cooling device. +MAX31760 fan controller supports different PWM frequencies, which can be +used as cooling device levels by controlling the fan speed. Required properties: - compatible : should be "maxim,max31760". @@ -12,13 +11,7 @@ Required properties: Optional properties: - maxim,vdd-supply : regulator supplying the vdd pin -- maxim,vdd-max-uv : regulator max voltage -- maxim,vdd-min-uv : regulator min voltage -- maxim,vdd-load-ua : regulator load current output - maxim,vcca-supply : regulator supplying the vcca pin -- maxim,vcca-max-uv : regulator max voltage -- maxim,vcca-min-uv : regulator min voltage -- maxim,vcca-load-ua : regulator load current output - maxim,fan_en_gpio : fan enable gpio Example: @@ -27,12 +20,6 @@ Example: reg = <0x50>; maxim,vdd-supply = <&some_reg>; regulator-names = "maxim,vdd"; - maxim,vdd-max-uv = <3400000>; - maxim,vdd-min-uv = <3300000>; - maxim,vdd-load-ua = <300000>; maxim,vcca-supply = <&some_reg>; - maxim,vcca-max-uv = <1800000>; - maxim,vcca-min-uv = <1800000>; - maxim,vcca-load-ua = <600000>; maxim,fan_en_gpio = <&tlmm 10 0x00>; }; From 33ea5e3652a87976d162f23e8cfc1c1f0aaa2661 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Mon, 25 Jan 2021 18:30:23 +0530 Subject: [PATCH 0787/1809] ARM: dts: msm: Disable DB polling feature for yupik For yupik WDI3 DB polling workaround was not required, so removing the entry. Change-Id: I582637a1d798a28c8bc4cf8e4715f8eab9a6a6e8 --- qcom/yupik.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 29f77964dc3c..006ece23c8d8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3672,7 +3672,6 @@ qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; qcom,use-gsi-ipa-fw = "yupik_ipa_fws"; - qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; From 647c0d3217455802aa761aed5fb5463bbbc4dd17 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sun, 31 Jan 2021 12:10:05 +0530 Subject: [PATCH 0788/1809] ARM: dts: msm: Update BCL thermalzone configuration for SHIMA GPU driver monitors BCL irq on CB and mitigates GPU frequency. Remove GPU mitigation rules from BCL thermalzone config. Change-Id: I4019d59e7b7b280dda9be406537943b048a76c0a --- qcom/shima-thermal-overlay.dtsi | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/qcom/shima-thermal-overlay.dtsi b/qcom/shima-thermal-overlay.dtsi index e2f347492c47..058150744b19 100644 --- a/qcom/shima-thermal-overlay.dtsi +++ b/qcom/shima-thermal-overlay.dtsi @@ -45,11 +45,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vbat_cdsp0 { trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -69,11 +64,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vbat_cdsp1 { trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; @@ -83,12 +73,6 @@ pm8350b-bcl-lvl2 { cooling-maps { - vbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vbat_cdsp2 { trip = <&b_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -110,11 +94,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { - trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vph_cdsp0 { trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -135,11 +114,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vph_cdsp1 { trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; @@ -150,12 +124,6 @@ pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT From 37bdb71795da962574d25170382c258cbb4e95af Mon Sep 17 00:00:00 2001 From: Arun Prakash Date: Mon, 31 Aug 2020 18:50:25 +0530 Subject: [PATCH 0789/1809] ARM: dts: msm: Add glink support for SA6155 Add glink and its dependent device tree node to support SA6155 for automotive platforms. Change-Id: I80133d7020109182a0f9fd04b2e61d6f7cdc9e27 --- qcom/sm6150.dtsi | 376 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 376 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 92a12a3be8f3..83f3abf9cf12 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -879,6 +879,382 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <2>; }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apss_shared 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apss_shared 24>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apss_shared 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + /* qcom,target-dev = <&cdsp_cdsp_l3_lat>;*/ + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "sm6150-qupv3.dtsi" From a1aba6493aba56b8a63ff8ff6b0fc29d3777f9c9 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 21 Jan 2021 10:46:40 -0800 Subject: [PATCH 0790/1809] dt-bindings: clock: Add qcom,critical-* properties Add documentation for the qcom,critical-clocks and qcom,critical-devices properties. Change-Id: I3a03164d206644e8be1e0d846730d8183c333b52 --- bindings/clock/qcom,gcc.txt | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index fddfd6882952..89ee69d7d28d 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -53,6 +53,10 @@ For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt - protected-clocks : Protected clock specifier list as per common clock binding. +- qcom,critical-clocks : List of clock specifiers that should be enabled during + probe and not registered with the clock framework. +- qcom,critical-devices : List of device phandles whose associated clocks + should be enabled during probe and not registered with the clock framework. Example: clock-controller@900000 { @@ -87,3 +91,23 @@ Example of GCC with protected-clocks properties: , ; }; + +Example of GCC with qcom,critical-clocks properties: + clock-controller@100000 { + compatible = "qcom,waipio-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + qcom,critical-clocks = , + , + ; + }; + +Example of GCC with qcom,critical-devices properties: + clock-controller@100000 { + compatible = "qcom,waipio-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + qcom,critical-devices = <&qupv3_se5_i2c>; + }; From 721aa9c0335346f0c9948f7aa575f0cfa85c2266 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 1 Feb 2021 11:39:57 +0530 Subject: [PATCH 0791/1809] ARM: dts: msm: Mark PMIC QUPs as critical clock devices for YUPIK To prevent deadlocks between the clock and regulator frameworks, the QUP clocks used by I2C-connected PMICs must be enabled all the time and not registered with the clock framework. Skipping the registration short-circuits the I2C device's clock calls such that they return success before grabbing the clock locks. Achieve this behavior by setting GCC's qcom,critical-devices property. Change-Id: Ie5017022b2d2281d6754bb527ac40bbd050673fc --- qcom/yupik-pmic-overlay.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index ac30b1c1045a..4ba57dd658b0 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -241,6 +241,14 @@ }; }; +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se1_i2c>; +}; + &qupv3_se1_i2c { #address-cells = <1>; #size-cells = <0>; From 07f63c13049c30e774f4b09db5acda82f773952a Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Mon, 1 Feb 2021 12:13:04 +0530 Subject: [PATCH 0792/1809] dt-bindings: enable guest disks renaming Enable guest partitions renaming to boot la guest with avb 2.0 compliance. Change-Id: Ib5c58f028c0f0e6879eaf33ea02d2760df859f24 --- bindings/soc/qcom/blocknames.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 bindings/soc/qcom/blocknames.txt diff --git a/bindings/soc/qcom/blocknames.txt b/bindings/soc/qcom/blocknames.txt new file mode 100644 index 000000000000..db6fc05c5b61 --- /dev/null +++ b/bindings/soc/qcom/blocknames.txt @@ -0,0 +1,19 @@ +* rename block devices + +Required properties: + +- compatible: "qcom,blkdev-rename" compatibility string +- actual-dev: Name of the disk assigned by generic driver +- rename-dev: Re-name of the disk to set for disks + +Example: + +rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "la_system", "la_userdata", "la_vendor", + "la_persist", "modem", "bluetooth", + "la_misc", "vbmeta"; +}; From 63bbc751dcf76fe9f2d3608a06b996a62e7a032d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 29 Jan 2021 18:46:59 +0800 Subject: [PATCH 0793/1809] ARM: dts: msm: correct the size of etf_reg dump Correct the size of etf_reg dump on sdxlemur. Change-Id: I45ab539592d8b50b8c2e461609fb7d3ea24bb853 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index be018e3c9f7b..eabb378079be 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -260,7 +260,7 @@ }; tmc_etf { - qcom,dump-size = <0x4000>; + qcom,dump-size = <0x10000>; qcom,dump-id = <0xf1>; }; From 9603d417b70ceb48847e46c91939d843f7f004d9 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 1 Feb 2021 14:28:54 +0530 Subject: [PATCH 0794/1809] ARM: dts: msm: Add clocks needed for qos configuration To configure the qos registers, we need clocks required. Add the clocks needed so that we can turn on when we need them. Change-Id: I960dff66ab1849b42ffb953dfc77fec3c435cdcf --- qcom/sdmshrike.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index e2b30bc4fe10..6c6bbe0894b7 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1036,6 +1036,12 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -1068,6 +1074,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos", "disp"; qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; }; mc_virt: interconnect@2 { From d1f61b15be407898543b609b0aa49a05fb29da1a Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 1 Feb 2021 14:49:42 +0530 Subject: [PATCH 0795/1809] ARM: dts: msm: Add apb_pclk to GMU clock list for Shima apb_pclk is required to access QDSS registers. GMU need to add vote before access can be made. Change-Id: I26852622c0c453f56fe6d238a478283a0879e410 --- qcom/shima-gpu.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 7f15e0a95637..69e3fbc592f8 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -576,10 +576,12 @@ <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&aopcc QDSS_CLK>; clock-names = "gmu_clk", "cxo_clk", "axi_clk", - "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote", + "apb_pclk"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; From c249df0456059924d30c4dcce6f39146fb12822b Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 1 Feb 2021 14:02:07 +0530 Subject: [PATCH 0796/1809] ARM: dts: msm: Change the node location for optimization for Yupik Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Also, bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: Ic15be7556b888940aed2df4098f4c954889a1fea --- qcom/yupik.dtsi | 457 ++++++++++++++++++++++++------------------------ 1 file changed, 232 insertions(+), 225 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6be910929dec..3f494fe4b8cb 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -32,8 +32,15 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; + mem-offline { compatible = "qcom,mem-offline"; offline-sizes = <0x1 0x40000000 0x0 0x40000000>, @@ -54,32 +61,7 @@ swr2 = &swr2; }; - firmware: firmware { - scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; - }; - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; - }; - }; - }; + firmware: firmware {}; cpus { #address-cells = <2>; @@ -268,207 +250,232 @@ }; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_mem@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: cmd_db@80860000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - reserved_xbl_uefi: reserved_xbl_uefi@80880000 { - no-map; - reg = <0x0 0x80880000 0x0 0x14000>; - }; - - secdata_apss_mem: secdata_apss@808ff000 { - no-map; - reg = <0x0 0x808ff000 0x0 0x1000>; - }; - - smem_mem: smem@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - fw_mem: fw@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - wlan_fw_mem: wlan_fw@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0xc00000>; - }; - - cdsp_secure_heap_mem: cdsp_secure_heap@81800000 { - no-map; - reg = <0x0 0x81800000 0x0 0x1e00000>; - }; - - pil_cvp_mem: camera@86200000 { - no-map; - reg = <0x0 0x86200000 0x0 0x500000>; - }; - - pil_adsp_mem: adsp@86700000 { - no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; - }; - - pil_cdsp_mem: cdsp@88f00000 { - no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xC00000>; - }; - - pil_camera_mem: video@8ad00000 { - no-map; - reg = <0x0 0x8ad00000 0x0 0x500000>; - }; - - pil_video_mem: cvp@8b200000 { - no-map; - reg = <0x0 0x8b200000 0x0 0x500000>; - }; - - pil_ipa_fw_mem: ipa_fw@8b700000 { - no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: ipa_gsi@8b710000 { - no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; - }; - - pil_mpss_mem: mpss@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0xf600000>; - }; - - pil_wpss_mem: wlan@9ae00000 { - no-map; - reg = <0x0 0x9ae00000 0x0 0x1900000>; - }; - - removed_mem: removed_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x5100000>; - }; - - pil_trustedvm_mem: pil_trustedvm_region@d0800000 { - no-map; - reg = <0x0 0xd0800000 0x0 0x76f7000>; - }; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0xd7ef7000 0x0 0x9000>; - }; - - chan0_shbuf: neuron_block@0 { - no-map; - reg = <0x0 0xd7f00000 0x0 0x80000>; - }; - - chan1_shbuf: neuron_block@1 { - no-map; - reg = <0x0 0xd7f80000 0x0 0x80000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x8c00000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x2c00000>; - }; - - audio_cma_mem: audio_cma_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1C00000>; - }; - - splash_memory:splash_region { - reg = <0x0 0xe1000000 0x0 0x02400000>; - label = "cont_splash_region"; - }; - }; - soc: soc { }; - chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: cmd_db@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + secdata_apss_mem: secdata_apss@808ff000 { + no-map; + reg = <0x0 0x808ff000 0x0 0x1000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + wlan_fw_mem: wlan_fw@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0xc00000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap@81800000 { + no-map; + reg = <0x0 0x81800000 0x0 0x1e00000>; + }; + + pil_cvp_mem: camera@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + pil_camera_mem: video@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: cvp@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_mem: mpss@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0xf600000>; + }; + + pil_wpss_mem: wlan@9ae00000 { + no-map; + reg = <0x0 0x9ae00000 0x0 0x1900000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x2c00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + splash_memory:splash_region { + reg = <0x0 0xe1000000 0x0 0x02400000>; + label = "cont_splash_region"; }; }; From 9f472ba74a39f2a660b271250e43fa3134cbc6c6 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Mon, 1 Feb 2021 12:14:59 +0530 Subject: [PATCH 0797/1809] ARM: dts: msm: enable guest disks renaming Enable guest partitions renaming to boot la guest with avb 2.0 compliance. Change-Id: Iac0b627834cfe35c22b2466f8b243dcaae79568a --- qcom/sa8155-vm-la-mt.dtsi | 12 ++++++++++++ qcom/sa8155-vm-la.dtsi | 11 +++++++++++ qcom/sa8195-vm-la-mt.dtsi | 12 ++++++++++++ qcom/sa8195-vm-la.dtsi | 12 ++++++++++++ 4 files changed, 47 insertions(+) diff --git a/qcom/sa8155-vm-la-mt.dtsi b/qcom/sa8155-vm-la-mt.dtsi index 63e1d6eabba3..df8396983d51 100644 --- a/qcom/sa8155-vm-la-mt.dtsi +++ b/qcom/sa8155-vm-la-mt.dtsi @@ -4,3 +4,15 @@ label = "pmem_shared_mem"; }; }; + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index ee0d8a882248..1bdfe711879d 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -5,6 +5,17 @@ }; }; +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; &usb0 { status = "ok"; }; diff --git a/qcom/sa8195-vm-la-mt.dtsi b/qcom/sa8195-vm-la-mt.dtsi index e975abfa0bd4..75ca621962f9 100644 --- a/qcom/sa8195-vm-la-mt.dtsi +++ b/qcom/sa8195-vm-la-mt.dtsi @@ -4,3 +4,15 @@ label = "pmem_shared_mem"; }; }; + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 7d003a2eb6b1..6be2d077d42d 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -5,6 +5,18 @@ }; }; +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; + &usb0 { status = "ok"; }; From 9bc97d21cdeb0c3a21ba5ba1a3ea0fd9523929e8 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 1 Feb 2021 20:20:43 +0800 Subject: [PATCH 0798/1809] ARM: dts: msm: Correct ATID for tpda dlct Correct ATID for tpda dlct. Every TPDA should has its own unique ATID. Change-Id: I0cc5d8d0baafab4c2f2ad67e5c8e43d0139d52a2 --- qcom/yupik-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index c910fe539c8d..65a55175e82f 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -744,7 +744,7 @@ reg-names = "tpda-base"; coresight-name = "coresight-tpda-dlct_5"; - qcom,tpda-atid = <71>; + qcom,tpda-atid = <78>; qcom,cmb-elem-size = <11 64>, <12 64>, <15 32>, From 68fa71886ebf6cb213ddadc3e4e16e9034e20af2 Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Mon, 1 Feb 2021 18:12:28 -0800 Subject: [PATCH 0799/1809] ARM: dts: msm: update dtsi for wlan pipes holb timeout Dtsi file change to include both 2.4G and 5G WLAN pipes holb timeout. Change-Id: Ic440d687dcc219e237a07028b9f7bfa734faa986 --- bindings/platform/msm/ipa.txt | 2 ++ qcom/sdxlemur.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 8a083792725c..bcd61f0ff777 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -127,6 +127,8 @@ memory allocation over a PCIe bridge registers, collected upon crash, reside. - qcom,ipa-endp-delay-wa: Boolean context flag to indicate end point delay work around supported or not. +- qcom,ipa-wdi3-holb-2g: HOLB timeout in milliseconds for the WLAN 2g pipe. +- qcom,ipa-wdi3-holb-5g: HOLB timeout in milliseconds for the WLAN 5g pipe. - qcom,secure-debug-check-action: Drives secure memory debug check. Three values allowed: 0 (use scm call), 1 (override scm call as though it returned true), and diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 6e6a1c411820..fc6e8f28d88e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1077,6 +1077,8 @@ qcom,arm-smmu; qcom,smmu-fast-map; qcom,ipa-wdi3-over-gsi; + qcom,ipa-wdi3-holb-2g = <8>; + qcom,ipa-wdi3-holb-5g = <15>; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; qcom,ipa-uc-holb-monitor; From 7a7f823013748e22fce510d63ec35ec4f648f874 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Mon, 1 Feb 2021 19:25:42 -0800 Subject: [PATCH 0800/1809] ARM: dts: msm: Update the Uni Phy sequence for Olympic Update the Uni Phy init sequence to version 0.97 for Olympic. Change-Id: I64477cafbc86251ad644845ed97af1bff333adc3 --- qcom/sdxlemur-usb.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index aa23fec61d67..56d21ca7bfcc 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -190,7 +190,7 @@ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDB 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 @@ -226,8 +226,8 @@ USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0B 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 From c73600743bb06e948397db60bf0d973a223742db Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 1 Feb 2021 16:14:01 +0530 Subject: [PATCH 0801/1809] ARM: dts: msm: Add device trees for IDPS with AMOLED for Yupik and YupikP Add device tree support for IDPS with AMOLED configuration for Yupik and YupikP platforms. Change-Id: I7b2cd12c8d0058998984fa3bb10af919b48a2f6d --- qcom/Makefile | 10 ++++++++-- qcom/yupik-idps-amoled-overlay.dts | 11 +++++++++++ qcom/yupik-idps-amoled.dts | 10 ++++++++++ qcom/yupik-idps-amoled.dtsi | 4 ++++ qcom/yupikp-idps-amoled-overlay.dts | 11 +++++++++++ qcom/yupikp-idps-amoled.dts | 10 ++++++++++ qcom/yupikp-idps-amoled.dtsi | 1 + 7 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 qcom/yupik-idps-amoled-overlay.dts create mode 100644 qcom/yupik-idps-amoled.dts create mode 100644 qcom/yupik-idps-amoled.dtsi create mode 100644 qcom/yupikp-idps-amoled-overlay.dts create mode 100644 qcom/yupikp-idps-amoled.dts create mode 100644 qcom/yupikp-idps-amoled.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index ddee39dfa495..f19fffc49367 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -156,10 +156,12 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-atp-overlay.dtbo \ yupik-qrd-overlay.dtbo \ yupik-idps-digital-mics-overlay.dtbo \ + yupik-idps-amoled-overlay.dtbo \ yupikp-idp-overlay.dtbo \ yupikp-atp-overlay.dtbo \ yupikp-qrd-overlay.dtbo \ - yupikp-idps-digital-mics-overlay.dtbo + yupikp-idps-digital-mics-overlay.dtbo \ + yupikp-idps-amoled-overlay.dtbo yupik-rumi-overlay.dtbo-base := yupik.dtb @@ -167,20 +169,24 @@ yupik-idp-overlay.dtbo-base := yupik.dtb yupik-atp-overlay.dtbo-base := yupik.dtb yupik-qrd-overlay.dtbo-base := yupik.dtb yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb +yupik-idps-amoled-overlay.dtbo-base := yupik.dtb yupikp-idp-overlay.dtbo-base := yupikp.dtb yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-digital-mics-overlay.dtbo-base := yupikp.dtb +yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ yupik-atp.dtb \ yupik-qrd.dtb \ yupik-idps-digital-mics.dtb \ + yupik-idps-amoled.dtb \ yupikp-idp.dtb \ yupikp-atp.dtb \ yupikp-qrd.dtb \ - yupikp-idps-digital-mics.dtb + yupikp-idps-digital-mics.dtb \ + yupikp-idps-amoled.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/yupik-idps-amoled-overlay.dts b/qcom/yupik-idps-amoled-overlay.dts new file mode 100644 index 000000000000..31b5898f9e18 --- /dev/null +++ b/qcom/yupik-idps-amoled-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDPS + AMOLED"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupik-idps-amoled.dts b/qcom/yupik-idps-amoled.dts new file mode 100644 index 000000000000..26ca956de78e --- /dev/null +++ b/qcom/yupik-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDPS + AMOLED"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupik-idps-amoled.dtsi b/qcom/yupik-idps-amoled.dtsi new file mode 100644 index 000000000000..885e5af51402 --- /dev/null +++ b/qcom/yupik-idps-amoled.dtsi @@ -0,0 +1,4 @@ +#include "yupik-idp.dtsi" + +&soc { +}; diff --git a/qcom/yupikp-idps-amoled-overlay.dts b/qcom/yupikp-idps-amoled-overlay.dts new file mode 100644 index 000000000000..2c3be6da773d --- /dev/null +++ b/qcom/yupikp-idps-amoled-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDPS + AMOLED"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupikp-idps-amoled.dts b/qcom/yupikp-idps-amoled.dts new file mode 100644 index 000000000000..642405634864 --- /dev/null +++ b/qcom/yupikp-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDPS + AMOLED"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupikp-idps-amoled.dtsi b/qcom/yupikp-idps-amoled.dtsi new file mode 100644 index 000000000000..bfb95f0df27f --- /dev/null +++ b/qcom/yupikp-idps-amoled.dtsi @@ -0,0 +1 @@ +#include "yupik-idps-amoled.dtsi" From 4166b3c0b0b6e2fcf50f3fe5964a8b058dd2924a Mon Sep 17 00:00:00 2001 From: Prateek Sood Date: Thu, 21 Jan 2021 01:41:37 +0530 Subject: [PATCH 0802/1809] ARM: dts: msm: Add mpm wakeup control capability in yupik pinctrl Add DT property for selective enabling of mpm wakeup control capability. Change-Id: I5a92558c44ad54f5e4c9b4499e4421a8b5430063 --- bindings/pinctrl/qcom,yupik-pinctrl.txt | 5 +++++ qcom/yupik-pinctrl.dtsi | 1 + 2 files changed, 6 insertions(+) diff --git a/bindings/pinctrl/qcom,yupik-pinctrl.txt b/bindings/pinctrl/qcom,yupik-pinctrl.txt index 819fd937ecd8..0a875154d0e4 100644 --- a/bindings/pinctrl/qcom,yupik-pinctrl.txt +++ b/bindings/pinctrl/qcom,yupik-pinctrl.txt @@ -45,6 +45,11 @@ YUPIK platform. Value type: Definition: A phandle to the wakeup interrupt controller for the SoC. +- qcom,tlmm-mpm-wake-control: + Usage: optional + Value type: + Definition: provide mpm wake control capability for a pin. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 7a6d1a6a7f15..ea88e048ce04 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -8,6 +8,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qcom,tlmm-mpm-wake-control; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { qupv3_se0_i2c_active: qupv3_se0_i2c_active { From c4f6d4838b7d01dc992276384961d236c3c358a9 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 1 Feb 2021 16:37:13 +0530 Subject: [PATCH 0803/1809] ARM: dts: msm: Disable haptics for yupik atp Disable haptics for yupik atp and enable both wsa. Change-Id: I0fcfa71931aabcfdf075a765d287a1edfbd1b8a5 --- qcom/yupik-atp.dtsi | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 45631c00e0c6..e92d835c7d4d 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -326,11 +326,6 @@ status = "disabled"; }; -&swr_haptics { - status = "okay"; - swr-slave-supply = <&hap_swr_slave_reg>; -}; - &yupik_snd { qcom,model = "lahaina-yupikqrd-snd-card"; qcom,audio-routing = @@ -357,7 +352,6 @@ "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", - "HAP_IN", "PCM_OUT", "WSA SRC0_INP", "SRC0", "WSA_TX DEC0_INP", "TX DEC0 MUX", "WSA_TX DEC1_INP", "TX DEC1 MUX", @@ -390,11 +384,13 @@ qcom,msm-mbhc-gnd-swh = <1>; asoc-codec = <&stub_codec>, <&bolero>, - <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0222>; + <&wcd938x_codec>, + <&wsa883x_0222>, + <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", - "wcd938x_codec", "swr-haptics", - "wsa-codec2"; + "wcd938x_codec", + "wsa-codec2", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <1>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; From f40938d8ffd641725aad47f5a9bc00103113e06d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 6 Oct 2020 14:40:04 +0530 Subject: [PATCH 0804/1809] ARM: dts: msm: Add AOPCC for SM6150 Add aopcc node to facilitate clients to request and operate on clocks. Change-Id: Icca62a90b022d7d1f605dc85d736d60ab5854d9a --- qcom/sm6150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 83f3abf9cf12..84627ecdbace 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -761,6 +762,13 @@ ; }; + aopcc: qcom,aopcc@0 { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + gcc: clock-controller@100000 { compatible = "qcom,sm6150-gcc", "syscon"; reg = <0x100000 0x1f0000>; From d9131d381b1a1d8025460645d574e554e66c8ff6 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 19 Jan 2021 19:17:31 +0530 Subject: [PATCH 0805/1809] ARM: dts: msm: Update regulators LDO1C and LDO10C for yupik Add ACTIVE_ONLY and SLEEP_ONLY nodes for LDO1C and LDO10C as per the clients requirement to vote for ACTIVE and SLEEP votes. Change-Id: Ic4f3560f9b939b351ebf312b38192fea191a71b3 --- qcom/yupik-regulators.dtsi | 40 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index f408a6cd1a9f..f749bb55eeb7 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -549,6 +549,25 @@ qcom,init-voltage = <1800000>; qcom,init-mode = ; }; + + L1C_AO: pm8350c_l1_ao: regulator-pm8350c-l1-ao { + regulator-name = "pm8350c_l1_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L1C_SO: pm8350c_l1_so: regulator-pm8350c-l1-so { + regulator-name = "pm8350c_l1_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; }; rpmh-regulator-ldoc2 { @@ -720,6 +739,27 @@ qcom,init-voltage = <880000>; qcom,init-mode = ; }; + + L10C_AO: + pm8350c_l10_ao: regulator-pm8350c-l10-ao { + regulator-name = "pm8350c_l10_ao"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L10C_SO: + pm8350c_l10_so: regulator-pm8350c-l10-so { + regulator-name = "pm8350c_l10_so"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; }; rpmh-regulator-ldoc11 { From b83a8731bcf3370fa25382dfa43f3928e7f0a23f Mon Sep 17 00:00:00 2001 From: Ankur Bansal Date: Thu, 28 Jan 2021 09:46:23 +0530 Subject: [PATCH 0806/1809] ARM: dts: msm: Add L1 TLB node for holi Added L1 (instruction and data) TLB node for holi. Change-Id: I31c4ec07ddda5ea0bb653fd5442b303bf8636f40 --- qcom/holi.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 8341ad465c55..ffd8eb4d9d21 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -772,6 +772,26 @@ qcom,dump-id = <0x87>; }; + l1_itlb102 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb103 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb102 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb103 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x47>; + }; + l2_tlb0 { qcom,dump-size = <0x5a00>; qcom,dump-id = <0x120>; From d5f403f2f23dc3b4fb78f015b5aca77c4c942e05 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Tue, 2 Feb 2021 21:40:09 +0530 Subject: [PATCH 0807/1809] ARM: dts: msm: Update qpic nand bus vote to nominal voltage Update qpic nand interconnect bandwidth vote to fall in nominal voltage corners. Change-Id: Ia12f726277d93afcd0604fe3f7c3bc7997af8257 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 279d02c7ca5e..2d261d6c0959 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -455,7 +455,7 @@ qcom,msm-bus,vectors-KBps = <0 0>, /* Voting for max b/w on PNOC bus for now */ - <400000 400000>; + <1057800 725760>; status = "disabled"; }; From 3701183ee7cc518275e8c4b06d1240c0cd51a182 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Tue, 2 Feb 2021 15:01:06 -0800 Subject: [PATCH 0808/1809] ARM: dts: msm: Disable USB U1/U2 on Olympic Enabling u1/u2 can lead to link instability leading to enumeration failure. Disable u1u2 on Olympic. Change-Id: I03a893b14b2af2a366f822c4ca12aa46826ad431 --- qcom/sdxlemur-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index aa23fec61d67..28c9debfc87e 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -63,7 +63,8 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; snps,bus-suspend-enable; tx-fifo-resize; maximum-speed = "super-speed-plus"; From 6db0641bbdf1e485afb8dc77f68bccf9176c3811 Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Wed, 3 Feb 2021 09:14:24 +0530 Subject: [PATCH 0809/1809] bindings: Documentation: Add new SDK audio properties Add audio documentation for tasha based soundcard. Change-Id: Ic6cea4f4be5d425091782f76fb1353f3175b14d5 --- bindings/sound/qcom-audio-dev.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 1c9bc157da29..b7c1410440f0 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -2431,6 +2431,8 @@ Required properties: Required properties: - compatible : "qcom,sdx-asoc-snd-tavil" +- compatible : "qcom,mdm-audio-tasha" for SDXNIGHTJAR target. +- compatible : "qcom,tasha-i2c-pgd". - qcom,model : The user-visible name of this sound card. - qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations - qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations From 2b2e805fb228f54bb92e317e2db35bccaa8cb364 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 3 Feb 2021 13:35:32 +0530 Subject: [PATCH 0810/1809] Revert "ARM: dts: msm: Update kgsl smmu clock for scuba" This reverts commit 8c3735ba4f9332ab31fd92b26f37c835629e3fbf. Change-Id: Ic1460bfbaa974000c183e9082e26282366851e54 --- qcom/msm-arm-smmu-scuba.dtsi | 9 --------- qcom/scuba-iot-idp.dtsi | 1 - 2 files changed, 10 deletions(-) diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi index 5703e8c00578..bb960362ef1a 100644 --- a/qcom/msm-arm-smmu-scuba.dtsi +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -12,15 +12,6 @@ qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; - vdd-supply = <&gpu_cx_gdsc>; - clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; - clock-names = "gcc_gpu_memnoc_gfx", - "gcc_gpu_snoc_dvm_gfx", - "gpu_cc_ahb", - "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; ranges; interrupts = , diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi index 44a660fd6ad2..91456469df2f 100644 --- a/qcom/scuba-iot-idp.dtsi +++ b/qcom/scuba-iot-idp.dtsi @@ -1,6 +1,5 @@ #include #include -#include "msm-arm-smmu-scuba.dtsi" #include "scuba-ion.dtsi" &soc { From d3037df32f17bced3ddeb33af1ed83a2ffe218f2 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Wed, 3 Feb 2021 16:49:49 +0530 Subject: [PATCH 0811/1809] ARM: dts: msm: Add support for general interrupts on sdxnightjar Add support for general interrupts on sdxnightjar to support exit from low power mode. Change-Id: I05c93166cc3f179485e04bbb78360b6d364fbad4 --- qcom/sdxnightjar-usb.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 42fbb8fadc52..34a5cbe0cd9a 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -8,8 +8,11 @@ #size-cells = <1>; ranges; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + &intc GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + &intc GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq","pwr_event_irq"; + USB3_GDSC-supply = <&gdsc_usb30>; qcom,lpm-to-suspend-delay-ms = <2000>; From d9b05944c6e48aae019b2ea78885bd83251f2571 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 3 Feb 2021 17:32:19 +0530 Subject: [PATCH 0812/1809] ARM: dts: msm: Add display and touch support for Yupik Amoled IDP Add r66451 display cphy panel support and focaltech touch on Yupik target. Change-Id: I2d65e76e91e28b45abbb9bc9ee5eb0c127a6755e --- qcom/yupik-idps-amoled.dtsi | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/qcom/yupik-idps-amoled.dtsi b/qcom/yupik-idps-amoled.dtsi index 885e5af51402..5b336005b02f 100644 --- a/qcom/yupik-idps-amoled.dtsi +++ b/qcom/yupik-idps-amoled.dtsi @@ -2,3 +2,44 @@ &soc { }; + +&pm8350c_l12 { + qcom,init-voltage = <1800000>; +}; + +&sde_dsi { + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy>; +}; + +&qupv3_se13_i2c { + status = "disabled"; +}; + +&qupv3_se13_spi { + status = "ok"; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + compatible = "focaltech,fts_ts"; + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <81 0x2008>; + focaltech,reset-gpio = <&tlmm 105 0x00>; + focaltech,irq-gpio = <&tlmm 81 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + + vdd-supply = <&L3C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy>; + }; +}; From 4e8c32e5d4bc9bcb396445d7cf82223193e24532 Mon Sep 17 00:00:00 2001 From: Dheeraj Madiraju Date: Tue, 19 Jan 2021 14:59:40 +0530 Subject: [PATCH 0813/1809] ARM: dts: msm: Add fps entry for yupik Add fps detection entry for yupik. Change-Id: I2cd8e37d7f7e2fea04dc2bb332ccbff9233f4b49 --- qcom/yupik.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..7eba885f19fb 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3392,6 +3392,10 @@ reg = <0x6020 0x4>; }; + feat_conf_m9: feat_conf_m9@6028 { + reg = <0x6028 0x4>; + }; + adsp_variant: adsp_variant@6020 { reg = <0x6022 0x1>; bits = <2 4>; @@ -3401,8 +3405,10 @@ qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; - nvmem-cells = <&feat_conf_m7>; - nvmem-cell-names = "feat_conf_m7"; + nvmem-cells = <&feat_conf_m7>, + <&feat_conf_m9>; + nvmem-cell-names = "feat_conf_m7", + "feat_conf_m9"; }; qcom,msm-cdsp-loader { From 721b921cbc8b8aa1d0cb626524e829706f995d73 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 22 Jan 2021 15:30:13 +0530 Subject: [PATCH 0814/1809] ARM: dts: msm: Add trusted touch properties for yupik Add trusted touch properties to novatek touch LA node to support VM(virtual machine) enabled trusted touch on yupik idp platform. Change-Id: Ie7ffbdf9193d6834bc58c5129e0e10a7ffaccebb --- qcom/yupik-idp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 291879aeb65d..33d788c82528 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -327,6 +327,12 @@ panel = <&dsi_nt36672e_fhd_plus_60_video &dsi_nt36672e_fhd_plus_144_video>; + + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "pvm"; + novatek,trusted-touch-spi-irq = <601>; + novatek,trusted-touch-io-bases = <0xf134000 0xf135000 0xf169000 0xf151000 0xa94000 0x00a10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; #include "camera/yupik-camera-sensor-idp.dtsi" From cbaee27ef1ada43f6632c792438bdcd2e923a94a Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 1 Feb 2021 13:46:37 +0530 Subject: [PATCH 0815/1809] dt-bindings: Add novatek touch vendor name Add novatek vendor name in vendor prefix list. Change-Id: If3c090e7beb2fcabcf40a32a672263cf8c26d833 --- bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index 2b11450bfa7b..89869deb520d 100644 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -333,6 +333,8 @@ patternProperties: description: Firefly "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^novatek,.*": + description: NOVATEK Microelectronics Corporation "^friendlyarm,.*": description: Guangzhou FriendlyARM Computer Tech Co., Ltd "^fsl,.*": From 3c6bc0de65c7cb78b593606c1beccf795af81416 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 22 Jan 2021 15:39:54 +0530 Subject: [PATCH 0816/1809] ARM: dts: msm: Add novatek touch node in yupik trusted VM Add novatek touch node to enable trusted touch in yupik trusted VM. Change-Id: I5a745e74bf3b8af2fd27b5d0021b3f8252e8edb0 --- qcom/yupik-vm.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index 121481de8b18..46dcb20a5464 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -269,7 +269,16 @@ dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; qcom,le-vm; - status = "disabled"; + status = "ok"; + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "tvm"; + novatek,trusted-touch-spi-irq = <601>; + novatek,trusted-touch-io-bases = <0xf134000 0xf135000 0xf169000 0xf151000 0xa94000 0x00a10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; }; qupv3_se13_spi: spi@a94000 { From eafef2463ea1ba9f5b97c3370b896266bdb85625 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 26 Jan 2021 10:25:25 -0800 Subject: [PATCH 0817/1809] ARM: dts: msm: Enable charge pump on sdxlemur platforms Enable dual-path charging using SMB1394 DIV 2 charge pump on sdxlemur platforms. Change-Id: I6184385c89546b41d9b6b801f8c084afbf6c7b67 --- qcom/sdxlemur-mtp-mbb.dtsi | 78 ++++++++++++++++++++++++++++++++++++-- qcom/sdxlemur-rcm-rc.dtsi | 78 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 148 insertions(+), 8 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7ef7a7462fd6..2ffd918491a7 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-mtp.dtsi" #include "pm7250b.dtsi" #include +#include #include #include "sdxlemur-cnss.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" @@ -49,6 +50,10 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; }; &pm7250b_adc_tm { @@ -135,7 +140,14 @@ <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -159,8 +171,16 @@ "charge_counter", "cycle_count", "charge_full_design", - "time_to_full_now"; + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; qcom,battery-data = <&mbb_batterydata>; + qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; qcom,step-charging-enable; qcom,sw-jeita-enable; @@ -192,13 +212,15 @@ <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", "recharge_soc", "force_recharge", - "charge_done"; + "charge_done", + "cp_charging_enabled"; qcom,battery-data = <&mbb_batterydata>; qcom,qg-iterm-ma = <150>; qcom,hold-soc-while-full; @@ -208,6 +230,7 @@ qcom,fvss-enable; qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; + qcom,use-cp-iin-sns; }; &pm7250b_pdphy { @@ -246,6 +269,53 @@ "pe_start"; }; +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&i2c_3 { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + &usb { extcon = <&pm7250b_pdphy>, <&eud>; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index aab84f4ef1c2..122be3879915 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" #include +#include #include #include "sdxlemur-cnss.dtsi" @@ -70,6 +71,10 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; }; &pm7250b_adc_tm { @@ -156,7 +161,14 @@ <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -180,8 +192,16 @@ "charge_counter", "cycle_count", "charge_full_design", - "time_to_full_now"; + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; qcom,battery-data = <&rcm_batterydata>; + qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; qcom,step-charging-enable; qcom,sw-jeita-enable; @@ -213,13 +233,15 @@ <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", "recharge_soc", "force_recharge", - "charge_done"; + "charge_done", + "cp_charging_enabled"; qcom,battery-data = <&rcm_batterydata>; qcom,qg-iterm-ma = <150>; qcom,hold-soc-while-full; @@ -229,6 +251,7 @@ qcom,fvss-enable; qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; + qcom,use-cp-iin-sns; }; &pm7250b_pdphy { @@ -267,6 +290,53 @@ "pe_start"; }; +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&i2c_3 { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + &usb { extcon = <&pm7250b_pdphy>, <&eud>; From 490af969aaf186239cd91cb51e16e3a03480a8e9 Mon Sep 17 00:00:00 2001 From: Chunhuan Zhan Date: Wed, 20 May 2020 14:53:07 +0800 Subject: [PATCH 0818/1809] ARM: dts: msm: include camera devicetree for sm8150 Add camera devicetree for sm8150 target. Change-Id: I9b62fe71e7e63bc75ef682cde2e74b0a600e4e73 --- qcom/sa8155.dtsi | 3 +++ qcom/sm8150-v2.dtsi | 1 + qcom/sm8150.dtsi | 1 + 3 files changed, 5 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 7f48b2dcd551..5c439aeb1059 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -124,3 +124,6 @@ &ufsphy_mem { vdda-phy-supply = <&pm8150_2_l18>; }; + +#include "camera/sa8155-camera.dtsi" +#include "camera/sa8155-camera-sensor.dtsi" diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index d2877407f6e0..d527c3b2c2d9 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -516,3 +516,4 @@ iommus = <&apps_smmu 0x2304 0x60>; }; }; +#include "camera/sm8150-v2-camera.dtsi" diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 5cacb452132c..2acd77786a47 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2257,6 +2257,7 @@ #include "sm8150-gdsc.dtsi" #include "msm-arm-smmu-sm8150.dtsi" #include "sm8150-vidc.dtsi" +#include "camera/sm8150-camera.dtsi" &emac_gdsc { status = "ok"; From 19bdac6a188bebf8c1e99626856e3fa1bd344106 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Thu, 4 Feb 2021 10:39:13 +0530 Subject: [PATCH 0819/1809] ARM: dts: msm: Add support for secure-level-shifter on sdxnightjar QUSB2PHY_LVL_SHIFTER is required to be updated to clamp the signals from the QUSB PHY. And for certain platforms this register is secured. Hence, add support for secure level shifter so that scm_call can be used to do a secure write to the register on sdxnightjar. Change-Id: I3ee07276e5d7074f4e304fbf8850db360d39f62d --- qcom/sdxnightjar-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 57f09b75bfe3..04421b989586 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -107,6 +107,7 @@ phy_type = "utmi"; USB3_GDSC-supply = <&gdsc_usb30>; + qcom,secure-level-shifter; clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_QUSB_REF_CLK>, <&gcc GCC_USB_PHY_CFG_AHB_CLK>, From 2b6fafe8fa5fc73e43ee8452d105797ec583aa9b Mon Sep 17 00:00:00 2001 From: Zhiqiang Liu Date: Wed, 3 Feb 2021 16:38:51 +0800 Subject: [PATCH 0820/1809] ARM: dts: msm: include display device tree for sa8155/sa8195 Include display device tree for platform sa8155 and sa8195. Change-Id: I36efc8bb829aa0ebd57cb4c0a7c437c63fd71d0f --- qcom/sa8155-adp-star-overlay.dts | 1 + qcom/sa8155-adp-star.dts | 1 + qcom/sa8155-adp-star.dtsi | 1 + qcom/sa8155-v2-adp-air-overlay.dts | 2 ++ qcom/sa8155-v2-adp-air.dts | 2 ++ qcom/sa8155-v2-adp-star.dts | 1 + qcom/sa8155p-adp-star-overlay.dts | 1 + qcom/sa8155p-adp-star.dts | 1 + qcom/sa8155p-v2-adp-air-overlay.dts | 2 ++ qcom/sa8155p-v2-adp-air.dts | 2 ++ qcom/sa8155p-v2-adp-star.dts | 1 + qcom/sa8195p-adp-star-overlay.dts | 1 + qcom/sa8195p-adp-star.dts | 1 + qcom/sa8195p-adp-star.dtsi | 1 + qcom/sa8195p-v2-adp-air-overlay.dts | 2 ++ qcom/sa8195p-v2-adp-air.dts | 2 ++ qcom/sdmshrike.dtsi | 3 +++ qcom/sm8150.dtsi | 3 +++ 18 files changed, 28 insertions(+) diff --git a/qcom/sa8155-adp-star-overlay.dts b/qcom/sa8155-adp-star-overlay.dts index 13d64ac124da..7a9369b949a0 100644 --- a/qcom/sa8155-adp-star-overlay.dts +++ b/qcom/sa8155-adp-star-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "ADP-STAR"; diff --git a/qcom/sa8155-adp-star.dts b/qcom/sa8155-adp-star.dts index 1be5c92116a7..b6a703a985b5 100644 --- a/qcom/sa8155-adp-star.dts +++ b/qcom/sa8155-adp-star.dts @@ -2,6 +2,7 @@ #include "sa8155-v1.dtsi" #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 ADP-STAR"; diff --git a/qcom/sa8155-adp-star.dtsi b/qcom/sa8155-adp-star.dtsi index 3fd19bf8fb86..bf2bd25f3846 100644 --- a/qcom/sa8155-adp-star.dtsi +++ b/qcom/sa8155-adp-star.dtsi @@ -1 +1,2 @@ #include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" diff --git a/qcom/sa8155-v2-adp-air-overlay.dts b/qcom/sa8155-v2-adp-air-overlay.dts index a342483d71af..9512d6154682 100644 --- a/qcom/sa8155-v2-adp-air-overlay.dts +++ b/qcom/sa8155-v2-adp-air-overlay.dts @@ -2,6 +2,8 @@ /plugin/; #include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "ADP-AIR"; diff --git a/qcom/sa8155-v2-adp-air.dts b/qcom/sa8155-v2-adp-air.dts index c0c93a3a12ac..fb99004d2e49 100644 --- a/qcom/sa8155-v2-adp-air.dts +++ b/qcom/sa8155-v2-adp-air.dts @@ -2,6 +2,8 @@ #include "sa8155-v2.dtsi" #include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 V2 ADP AIR"; diff --git a/qcom/sa8155-v2-adp-star.dts b/qcom/sa8155-v2-adp-star.dts index bb5b257a53a3..59fd12b62ecb 100644 --- a/qcom/sa8155-v2-adp-star.dts +++ b/qcom/sa8155-v2-adp-star.dts @@ -2,6 +2,7 @@ #include "sa8155-v2.dtsi" #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 V2 ADP STAR"; diff --git a/qcom/sa8155p-adp-star-overlay.dts b/qcom/sa8155p-adp-star-overlay.dts index db8d3b48f01e..9c32e380748e 100644 --- a/qcom/sa8155p-adp-star-overlay.dts +++ b/qcom/sa8155p-adp-star-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "ADP-STAR"; diff --git a/qcom/sa8155p-adp-star.dts b/qcom/sa8155p-adp-star.dts index 3472b77f72c0..a6f77a6b13e2 100644 --- a/qcom/sa8155p-adp-star.dts +++ b/qcom/sa8155p-adp-star.dts @@ -2,6 +2,7 @@ #include "sa8155p.dtsi" #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P ADP-STAR"; diff --git a/qcom/sa8155p-v2-adp-air-overlay.dts b/qcom/sa8155p-v2-adp-air-overlay.dts index 57ac3cae9aff..fd881bfdaa06 100644 --- a/qcom/sa8155p-v2-adp-air-overlay.dts +++ b/qcom/sa8155p-v2-adp-air-overlay.dts @@ -2,6 +2,8 @@ /plugin/; #include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "ADP-AIR"; diff --git a/qcom/sa8155p-v2-adp-air.dts b/qcom/sa8155p-v2-adp-air.dts index 954e155b7673..56731ff9e3af 100644 --- a/qcom/sa8155p-v2-adp-air.dts +++ b/qcom/sa8155p-v2-adp-air.dts @@ -2,6 +2,8 @@ #include "sa8155p-v2.dtsi" #include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P V2 ADP AIR"; diff --git a/qcom/sa8155p-v2-adp-star.dts b/qcom/sa8155p-v2-adp-star.dts index ef21fb5e1883..4f9780a53a42 100644 --- a/qcom/sa8155p-v2-adp-star.dts +++ b/qcom/sa8155p-v2-adp-star.dts @@ -2,6 +2,7 @@ #include "sa8155p-v2.dtsi" #include "sa8155-adp-star.dtsi" +#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P V2 ADP STAR"; diff --git a/qcom/sa8195p-adp-star-overlay.dts b/qcom/sa8195p-adp-star-overlay.dts index e6ae85d95bf7..dc01d9417bc5 100644 --- a/qcom/sa8195p-adp-star-overlay.dts +++ b/qcom/sa8195p-adp-star-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa8195p-adp-star.dtsi" +#include "display/sa8195p-adp-star-display-shd.dtsi" / { model = "ADP-STAR"; diff --git a/qcom/sa8195p-adp-star.dts b/qcom/sa8195p-adp-star.dts index 6183b7cb3c68..6e00a1813e86 100644 --- a/qcom/sa8195p-adp-star.dts +++ b/qcom/sa8195p-adp-star.dts @@ -2,6 +2,7 @@ #include "sa8195p.dtsi" #include "sa8195p-adp-common.dtsi" +#include "display/sa8195p-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR"; diff --git a/qcom/sa8195p-adp-star.dtsi b/qcom/sa8195p-adp-star.dtsi index ec4afde21db4..91b92282255e 100644 --- a/qcom/sa8195p-adp-star.dtsi +++ b/qcom/sa8195p-adp-star.dtsi @@ -1 +1,2 @@ #include "sa8195p-adp-common.dtsi" +#include "display/sa8195p-adp-star-display.dtsi" diff --git a/qcom/sa8195p-v2-adp-air-overlay.dts b/qcom/sa8195p-v2-adp-air-overlay.dts index dd8060574532..9b3cf9300f5f 100644 --- a/qcom/sa8195p-v2-adp-air-overlay.dts +++ b/qcom/sa8195p-v2-adp-air-overlay.dts @@ -2,6 +2,8 @@ /plugin/; #include "sa8195p-v2-adp-air.dtsi" +#include "display/sa8195p-adp-star-display.dtsi" +#include "display/sa8195p-adp-star-display-shd.dtsi" / { model = "ADP-AIR"; diff --git a/qcom/sa8195p-v2-adp-air.dts b/qcom/sa8195p-v2-adp-air.dts index 398606ccb6e2..f2b96c2ca359 100644 --- a/qcom/sa8195p-v2-adp-air.dts +++ b/qcom/sa8195p-v2-adp-air.dts @@ -2,6 +2,8 @@ #include "sa8195p.dtsi" #include "sa8195p-adp-common.dtsi" +#include "display/sa8195p-adp-star-display.dtsi" +#include "display/sa8195p-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR"; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 2d15aff8059a..a2613e74c4a7 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -518,6 +518,9 @@ soc: soc { }; }; +#include "display/sdmshrike-sde-pll.dtsi" +#include "display/sdmshrike-sde.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 1108f8366fdd..0fa4025f4f08 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -589,6 +589,9 @@ }; }; +#include "display/sm8150-sde.dtsi" +#include "display/sm8150-sde-pll.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; From 16e82d6a0cd11d3d2f9e89738d135eb055738ae0 Mon Sep 17 00:00:00 2001 From: Zhiqiang Liu Date: Thu, 28 Jan 2021 11:23:14 +0800 Subject: [PATCH 0821/1809] ARM: dts: msm: add lxc overlay devicetree for Gen3 platform Create new lxc overlay devicetree for Gen3 platform, and add lxc multi-card configuration to these overlay devicetrees. Change-Id: Ic5ba96064413e062cba462d7fa0c78f9f07ae9c8 --- qcom/sa6155p-v2-adp-air-lxc-overlay.dts | 12 ++++++++++++ qcom/sa8155-v2-adp-air-lxc-overlay.dts | 13 +++++++++++++ qcom/sa8155p-v2-adp-air-lxc-overlay.dts | 13 +++++++++++++ qcom/sa8195p-v2-adp-air-lxc-overlay.dts | 19 +++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 qcom/sa6155p-v2-adp-air-lxc-overlay.dts create mode 100644 qcom/sa8155-v2-adp-air-lxc-overlay.dts create mode 100644 qcom/sa8155p-v2-adp-air-lxc-overlay.dts create mode 100644 qcom/sa8195p-v2-adp-air-lxc-overlay.dts diff --git a/qcom/sa6155p-v2-adp-air-lxc-overlay.dts b/qcom/sa6155p-v2-adp-air-lxc-overlay.dts new file mode 100644 index 000000000000..6e45ada0cdc8 --- /dev/null +++ b/qcom/sa6155p-v2-adp-air-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" +#include "display/sa6155p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03020019 0>; +}; diff --git a/qcom/sa8155-v2-adp-air-lxc-overlay.dts b/qcom/sa8155-v2-adp-air-lxc-overlay.dts new file mode 100644 index 000000000000..afc71383d737 --- /dev/null +++ b/qcom/sa8155-v2-adp-air-lxc-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155-v2-adp-air", "qcom,sa8155", + "qcom,adp-air"; + qcom,board-id = <0X01000019 0>; +}; diff --git a/qcom/sa8155p-v2-adp-air-lxc-overlay.dts b/qcom/sa8155p-v2-adp-air-lxc-overlay.dts new file mode 100644 index 000000000000..08e7c1a4b79a --- /dev/null +++ b/qcom/sa8155p-v2-adp-air-lxc-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" +#include "display/sa8155-adp-star-display.dtsi" +#include "display/sa8155-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155p-v2-adp-air", "qcom,sa8155p", + "qcom,adp-air"; + qcom,board-id = <0x01000019 0>; +}; diff --git a/qcom/sa8195p-v2-adp-air-lxc-overlay.dts b/qcom/sa8195p-v2-adp-air-lxc-overlay.dts new file mode 100644 index 000000000000..1d57b6a2338b --- /dev/null +++ b/qcom/sa8195p-v2-adp-air-lxc-overlay.dts @@ -0,0 +1,19 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-adp-common.dtsi" +#include "display/sa8195p-adp-star-display.dtsi" +#include "display/sa8195p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", + "qcom,adp-air"; + qcom,board-id = <0x02010019 0>; +}; + +&qupv3_se0_spi { + can-controller@0 { + status = "disabled"; + }; +}; From bdda9566f439bb364c97f0e9733cf22f9926a07d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 4 Feb 2021 11:12:43 +0800 Subject: [PATCH 0822/1809] ARM: dts: msm: correct name of etm0 Correct etm0 name to coresight-etm0 on sdxlemur. Change-Id: I1dc2c5cce8b491e259d6ca9546e658fe06372a9c --- qcom/sdxlemur-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 4cc7c33e6375..1253c39689f5 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -1223,7 +1223,7 @@ cpu = <&CPU0>; qcom,tupwr-disable; - coresight-name = "coresight-coresight-etm0"; + coresight-name = "coresight-etm0"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; From a309519fe0c353594fa7f90784b8090343e710ec Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Thu, 4 Feb 2021 18:08:42 +0800 Subject: [PATCH 0823/1809] ARM: dts: msm: Add irq type for uart, watchdog and pinctrl for sdxnightjar Add irq type for uart, watchdog and pinctrl to avoid excessive warning log for sdxnightjar. Change-Id: I3fa817c2f334da5939b1976fedbb5208f58a88de --- qcom/sdxnightjar-pinctrl.dtsi | 2 +- qcom/sdxnightjar.dtsi | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index f5a916ea293e..53260f855864 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -4,7 +4,7 @@ tlmm_pinmux: pinctrl@1000000 { compatible = "qcom,sdxnightjar-pinctrl"; reg = <0x1000000 0x300000>; - interrupts = <0 208 0>; + interrupts = <0 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 00ea3f6a2f57..676c8a2c807f 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -584,7 +584,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; - interrupts = <0 107 0>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -594,7 +594,7 @@ blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; - interrupts = <0 108 0>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -604,7 +604,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b1000 0x200>; - interrupts = <0 109 0>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -622,7 +622,8 @@ compatible = "qcom,msm-watchdog"; reg = <0xb017000 0x1000>; reg-names = "wdt-base"; - interrupts = <1 3 0>, <1 2 0>; + interrupts = <1 3 IRQ_TYPE_EDGE_RISING>, + <1 2 IRQ_TYPE_EDGE_RISING>; qcom,bark-time = <11000>; qcom,pet-time = <10000>; }; From 240b363f33f311d9296b7d6363214fa1c9711d98 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 3 Jun 2020 15:36:05 +0530 Subject: [PATCH 0824/1809] ARM: dts: msm: Add node for memory dump driver for SM8150 Add device node for memdump driver for SM8150. This is required to capture necessary debug information when system crashes. Change-Id: Ie2bd6d24d8a9996e19622b32d79e0a4dbc6869b1 --- qcom/sm8150.dtsi | 384 +++++++++++++++++++++++++++++------------------ 1 file changed, 236 insertions(+), 148 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 1108f8366fdd..67f6e7653491 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -65,20 +65,6 @@ cache-level = <3>; }; }; - - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_0: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU1: cpu@100 { @@ -95,20 +81,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_100: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU2: cpu@200 { @@ -125,20 +97,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_200: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_200: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_200: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU3: cpu@300 { @@ -155,20 +113,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_300: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_300: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_300: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU4: cpu@400 { @@ -184,29 +128,6 @@ compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x88000>; - }; - - L1_I_400: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_400: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_400: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_400: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_400: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -223,29 +144,6 @@ compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x88000>; - }; - - L1_I_500: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_500: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_500: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_500: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_500: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -262,29 +160,6 @@ compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x88000>; - }; - - L1_I_600: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_600: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_600: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_600: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_600: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -301,29 +176,6 @@ compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x110000>; - }; - - L1_I_700: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_700: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_700: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_700: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_700: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -546,6 +398,7 @@ dump_mem: mem_dump_region { compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; size = <0 0x2400000>; }; @@ -2275,6 +2128,241 @@ qcom,config-arr = <0x18040060 0x18050060 0x18060060 0x18070060>; }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; + + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb400 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb500 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x47>; + }; + + l2_cache400 { + qcom,dump-size = <0x88000>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0x88000>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0x88000>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x110000>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + }; }; &firmware { From 8b8279e0bc7a3c21a4bdfa115e6f6310b5db1d37 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 29 Oct 2020 17:07:01 +0530 Subject: [PATCH 0825/1809] ARM: dts: msm: Add node for memory dump driver for SDMSHRIKE Add device node for memdump driver for SDMSHRIKE. This is required to capture necessary debug information when system crashes. Change-Id: Idfa0fd6ec16740165a0367212c7b90fe37ecb548 --- qcom/sdmshrike.dtsi | 216 ++++++++++++++++++++++++++++---------------- 1 file changed, 136 insertions(+), 80 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 2d15aff8059a..998ff5dd5e3e 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -65,16 +65,6 @@ cache-level = <3>; }; }; - - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; - - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; }; CPU1: cpu@100 { @@ -93,16 +83,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; - - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; }; CPU2: cpu@200 { @@ -121,16 +101,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_200: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; - - L1_D_200: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; }; CPU3: cpu@300 { @@ -149,16 +119,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_300: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; - - L1_D_300: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0xa000>; - }; }; CPU4: cpu@400 { @@ -177,16 +137,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_400: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; - - L1_D_400: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; }; CPU5: cpu@500 { @@ -205,16 +155,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_500: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; - - L1_D_500: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; }; CPU6: cpu@600 { @@ -233,16 +173,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_600: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; - - L1_D_600: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; }; CPU7: cpu@700 { @@ -261,16 +191,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_700: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; - - L1_D_700: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x14000>; - }; }; cpu-map { @@ -489,6 +409,7 @@ dump_mem: mem_dump_region { compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; size = <0 0x2400000>; }; @@ -860,6 +781,141 @@ interrupts = ; }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0xa000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x14000>; + qcom,dump-id = <0x87>; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From a3ae2bd17a66bd2fb7404c5f5700bc7188aa83eb Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 4 Feb 2021 20:26:12 +0530 Subject: [PATCH 0826/1809] ARM: dts: msm: Add reserved memory for dfps data on yupik Add reserved memory region dfps_data_region on yupik target. Change-Id: I910afe515161ba77e787907fd8464bc8bd79202f --- qcom/yupik.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c437f4a7e9c0..f13a9782caf8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -474,9 +474,14 @@ }; splash_memory:splash_region { - reg = <0x0 0xe1000000 0x0 0x02400000>; + reg = <0x0 0xe1000000 0x0 0x02300000>; label = "cont_splash_region"; }; + + dfps_data_memory: dfps_data_memory { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_memory"; + }; }; &soc { From 63090da6fd7940ced7c9e92b18d131560dbed0fc Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Wed, 2 Dec 2020 22:46:25 +0800 Subject: [PATCH 0827/1809] ARM: dts: msm: add quat/quin slpi pinctrl info on sm615x platform Add Quaternary and Quinary SLPI pinctrl nodes for SCLK/SW/SD0/SD1 lines on sm615x platform. Change-Id: Ie14f74563ec1949a18dc61f44797168434952f9f --- qcom/sm6150-pinctrl.dtsi | 260 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi index bfebee7214a0..14df23e80f47 100644 --- a/qcom/sm6150-pinctrl.dtsi +++ b/qcom/sm6150-pinctrl.dtsi @@ -1381,6 +1381,266 @@ }; }; + quat_tdm_sclk_active: quat_tdm_sclk_active { + mux { + pins = "gpio23"; + function = "func3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + quat_tdm_sclk_sleep: quat_tdm_sclk_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_ws_active: quat_tdm_ws_active { + mux { + pins = "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + quat_tdm_ws_sleep: quat_tdm_ws_sleep { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data3_active: quat_tdm_data3_active { + mux { + pins = "gpio28"; + function = "func2"; + }; + + config { + pins = "gpio28"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data3_sleep: quat_tdm_data3_sleep { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data2_active: quat_tdm_data2_active { + mux { + pins = "gpio27"; + function = "func2"; + }; + + config { + pins = "gpio27"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data2_sleep: quat_tdm_data2_sleep { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data1_active: quat_tdm_data1_active { + mux { + pins = "gpio26"; + function = "func2"; + }; + + config { + pins = "gpio26"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data1_sleep: quat_tdm_data1_sleep { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data0_active: quat_tdm_data0_active { + mux { + pins = "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio25"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data0_sleep: quat_tdm_data0_sleep { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_sclk_active: quin_tdm_sclk_active { + mux { + pins = "gpio18"; + function = "func3"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_sclk_sleep: quin_tdm_sclk_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data0_active: quin_tdm_data0_active { + mux { + pins = "gpio20"; + function = "func3"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_data0_sleep: quin_tdm_data0_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_ws_active: quin_tdm_ws_active { + mux { + pins = "gpio21"; + function = "func3"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_ws_sleep: quin_tdm_ws_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data1_active: quin_tdm_data1_active { + mux { + pins = "gpio22"; + function = "func3"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; + bias-disable; + }; + }; + + quin_tdm_data1_sleep: quin_tdm_data1_sleep { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-down; + }; + }; + pmx_ts_int_active { ts_int_active: ts_int_active { mux { From 7e0b238dd5fc2de8f0752fd894972f973683263d Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Tue, 26 Jan 2021 14:09:33 +0800 Subject: [PATCH 0828/1809] ARM: dts: msm: Add device nodes for FastRPC and CDSP Loader for SA8155 Add fastrpc device tree nodes for CDSP, ADSP and SDSP for SA8155. Add cdsp loader device tree node for SA8155. Change-Id: I0714079ca6307b8dbc5b8e9aa0804306c2d05b07 --- qcom/sm8150-v2.dtsi | 38 +++++++++++ qcom/sm8150.dtsi | 161 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 199 insertions(+) diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index d2877407f6e0..0be2903440f7 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -297,6 +297,44 @@ 0x0a44 0x03 0x0>; }; +&msm_fastrpc { + qcom,msm_fastrpc_compute_cb1 { + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb2 { + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb3 { + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb4 { + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb5 { + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb6 { + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb7 { + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb8 { + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb9 { + iommus = <&apps_smmu 0x1009 0x0460>; + }; +}; + /* GPU overrides */ &msm_gpu { /* Updated chip ID */ diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 1108f8366fdd..f97e756b92bf 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1618,6 +1618,167 @@ }; }; + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x2040>, + <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x2001 0x420>, + <&apps_smmu 0x2041 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x4 0x3440>, + <&apps_smmu 0x24 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x5 0x3440>, + <&apps_smmu 0x25 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x6 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x7 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x8 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x2 0x3440>, + <&apps_smmu 0x22 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x3 0x3440>, + <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x2023 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x9 0x3460>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b23 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b24 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b25 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a1 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a2 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a3 0x0>; + shared-cb = <4>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + }; + qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; From eed50073dd9ed10830cf3620af91bdc22514e276 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Fri, 5 Feb 2021 09:50:38 +0530 Subject: [PATCH 0829/1809] ARM: dts: msm: Update EQU_ADAPTOR_CNTRL3 of SS PHY on holi Update EQU_ADAPTOR_CNTRL3 of SS PHY on holi to match the settings suggested in HPG to improve adaptation of PHY with longer channels. Change-Id: Ib15c5d617c2fc47bc769b77569a045c415bc7ef2 --- qcom/holi-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index cb7ee84ebdc2..c5ecb20a9142 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -214,7 +214,7 @@ USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 0 USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0 USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 - USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0 + USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0 USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0 USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 @@ -224,7 +224,7 @@ USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0 USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0 USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 - USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0 + USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0 USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0 USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 From 63ce1507ef9fe2bd67bc7123e9f27021354396ec Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Thu, 4 Feb 2021 18:11:03 +0530 Subject: [PATCH 0830/1809] ARM: dts: msm: add support for CPUCP l3 scaling on yupik target Add dcvs nodes for CPUCP mailbox, scmi and memlat configuration facilitating the CPUCP based L3 scaling in yupik target. Change-Id: I71253b39b911e6db077839e9eebfa2eed47147cd --- qcom/yupik.dtsi | 349 ++++++++++++++++++++---------------------------- 1 file changed, 147 insertions(+), 202 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c437f4a7e9c0..1b4c03c7f202 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -250,6 +250,20 @@ }; }; + sram: sram@18509400 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x0 0x18509400 0x0 0x400>; + ranges = <0x0 0x0 0x0 0x18509400 0x0 0x400>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x80>; + }; + }; + soc: soc { }; }; @@ -1629,96 +1643,6 @@ qcom,count-unit = <0x10000>; }; - cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU0>; - }; - - cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU1>; - }; - - cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU2>; - }; - - cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU3>; - }; - - cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU4>; - }; - - cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU5>; - }; - - cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU6>; - }; - - cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; - }; - - cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { - compatible = "qcom,devfreq-icc-l3"; - reg = <0x18590100 0xa0>; - reg-names = "ftbl-base"; - governor = "compute"; - interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; - }; - cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -1783,6 +1707,16 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; + cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "compute"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat { compatible = "qcom,devfreq-qoslat"; governor = "mem_latency"; @@ -1797,122 +1731,10 @@ mboxes = <&qmp_aop 0>; }; - cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { - qcom,core-dev-table = - < 300000 300000000 >, - < 691200 556800000 >, - < 806400 652800000 >, - < 940800 768000000 >, - < 1152000 844800000 >, - < 1324800 1065600000 >, - < 1516800 1190400000 >, - < 1651200 1305600000 >, - < 1804800 1516800000 >; - }; - - cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl { - qcom,core-dev-table = - < 940800 556800000 >, - < 12288000 768000000 >, - < 1651200 1190400000 >, - < 1900800 1401600000 >, - < 2400000 1516800000 >; - }; - - cpu7_cpu_l3_tbl: qcom,cpu7-cpu-l3-tbl { - qcom,core-dev-table = - < 1056000 556800000 >, - < 1324800 768000000 >, - < 1766400 1190400000 >, - < 2208000 1401600000 >, - < 2707200 1516800000 >; - }; - cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; - cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0>; - qcom,target-dev = <&cpu0_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU1>; - qcom,target-dev = <&cpu1_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU2>; - qcom,target-dev = <&cpu2_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU3>; - qcom,target-dev = <&cpu3_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4>; - qcom,target-dev = <&cpu4_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; - }; - - cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU5>; - qcom,target-dev = <&cpu5_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; - }; - - cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6>; - qcom,target-dev = <&cpu6_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; - }; - - cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu7_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu7_cpu_l3_tbl>; - }; - - cpu7_l3_computemon: qcom,cpu7-l3-computemon { - compatible = "qcom,arm-compute-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu7_cpu_l3_latfloor>; - qcom,core-dev-table = - < 2035200 300000000 >, - < 2707200 1516800000 >; - }; - cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,target-dev = <&cpu0_cpu_llcc_lat>; @@ -2058,6 +1880,15 @@ }; }; + cpu7_l3_computemon: qcom,cpu7-l3-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_latfloor>; + qcom,core-dev-table = + < 2035200 300000000 >, + < 2707200 1516800000 >; + }; + cpu4_qoslatmon: qcom,cpu4-qoslatmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; @@ -2079,6 +1910,120 @@ }; }; + rimps: qcom,rimps@17C00000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps"; + reg = <0x17C00000 0x10>, + <0x18590000 0x2000>; + #mbox-cells = <1>; + interrupts = <0 62 4>; + }; + + cpu0_grp: qcom,cpu0_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x185098E0 0x320>; + reg-names = "pmu-base"; + + cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cachemiss-ev = <0x17>; + reg = <0x18590100 0xa0>, <0x18590340 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 300000 300000000 >, + < 691200 556800000 >, + < 806400 652800000 >, + < 940800 768000000 >, + < 1152000 844800000 >, + < 1324800 1065600000 >, + < 1516800 1190400000 >, + < 1651200 1305600000 >, + < 1804800 1516800000 >; + }; + }; + + cpu4_grp: qcom,cpu4_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x185098E0 0x320>; + reg-names = "pmu-base"; + + cpu4_rimps_l3_latmon: qcom,cpu4-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + qcom,cachemiss-ev = <0x17>; + qcom,wb-ev = <0x18>; + qcom,access-ev = <0x2B>; + reg = <0x18590100 0xa0>, <0x18590340 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 940800 556800000 >, + < 12288000 768000000 >, + < 1651200 1190400000 >, + < 1900800 1401600000 >, + < 2400000 1516800000 >; + }; + }; + + cpu7_grp: qcom,cpu7_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x185098E0 0x320>; + reg-names = "pmu-base"; + + cpu7_rimps_l3_latmon: qcom,cpu7-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU7>; + qcom,cachemiss-ev = <0x17>; + qcom,wb-ev = <0x18>; + qcom,access-ev = <0x2B>; + reg = <0x18590100 0xa0>, <0x18590340 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 1056000 556800000 >, + < 1324800 768000000 >, + < 1766400 1190400000 >, + < 2208000 1401600000 >, + < 2707200 1516800000 >; + }; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&rimps 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_memlat: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + rimps_log: qcom,rimps_log@18509C00 { + compatible = "qcom,rimps-log"; + reg = <0x18509C00 0x200>, + <0x18509E00 0x200>; + mboxes = <&rimps 1>; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 585cdc501ca8028095b5e675f28e632f0adcbb23 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Fri, 5 Feb 2021 17:35:55 +0530 Subject: [PATCH 0831/1809] ARM: dts: msm: Add 120fps display and touch support Yupik Amoled IDPS This change adds display and touch support for r66451 dsc fhd plus 120fps command mode panel on yupik. Change-Id: If331abb695ef22103fdca51fa0a8a9dded69c6b5 --- qcom/yupik-idps-amoled.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-idps-amoled.dtsi b/qcom/yupik-idps-amoled.dtsi index 5b336005b02f..f86b5665cdde 100644 --- a/qcom/yupik-idps-amoled.dtsi +++ b/qcom/yupik-idps-amoled.dtsi @@ -10,7 +10,7 @@ &sde_dsi { vddio-supply = <&L12C>; vdd-supply = <&L13C>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_120hz_cmd_cphy>; }; &qupv3_se13_i2c { @@ -40,6 +40,8 @@ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; - panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy>; + panel = <&dsi_r66451_amoled_144hz_cmd_cphy + &dsi_r66451_amoled_120hz_cmd_cphy + &dsi_r66451_amoled_90hz_cmd_cphy>; }; }; From ac0d7281ce2e04be74adee6e1108bdb0eb732f83 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 5 Feb 2021 22:37:43 +0800 Subject: [PATCH 0832/1809] ARM: dts: msm: Correct the width of APSS TPDM APSS TPDM use DSB 32 as data width, correct it for yupik. Change-Id: Iaffa8a5806fd58014c7aefa0f5693fbdcf71d73d --- qcom/yupik-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index f2b1e6fcdb65..8fd83d1836db 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -2603,7 +2603,7 @@ coresight-name = "coresight-tpda-apss"; qcom,tpda-atid = <66>; - qcom,dsb-elem-size = <3 64>; + qcom,dsb-elem-size = <3 32>; qcom,cmb-elem-size = <0 32>, <1 32>, <2 64>; From 373f13220170f83b1922c325172f1340ab3eecad Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Tue, 2 Feb 2021 14:03:48 -0800 Subject: [PATCH 0833/1809] ARM: dts: msm: bypass new cb for pcie ep Bypass ETH/ETH1/WLAN1 CBs Change-Id: I4e6839903e7c7eadaa5f827f0ce3559e92bf659c --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index f60aa7a24536..af021815a43b 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -42,6 +42,19 @@ ipa_smmu_11ad { qcom,iommu-dma = "bypass"; }; + + ipa_smmu_eth { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_eth1 { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_wlan1 { + qcom,iommu-dma = "bypass"; + }; + }; &usb { From b95793d04b33bb7454781f946fe2a3f831777aef Mon Sep 17 00:00:00 2001 From: Piyush Dhyani Date: Fri, 5 Feb 2021 23:12:25 +0530 Subject: [PATCH 0834/1809] ARM: dts: msm: Modify IPA DT entry for sdxnightjar Modify Interrupt type for smp2p to avoid bootup logs warning. Change-Id: I4614c7f06ba155ad4a7b4b0d6e5fb161d0ce7fd7 --- qcom/sdxnightjar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 07378eed1518..1da6c56e1b9a 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1006,7 +1006,7 @@ qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; - interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupts-extended = <&smp2p_ipa_1_in 0 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ipa-smp2p-in"; }; }; From cbeaf6c08f229af76fab65db5fd0083ca408f00f Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 5 Feb 2021 11:19:53 -0800 Subject: [PATCH 0835/1809] ARM: dts: msm: add pci DT nodes for PCIe switch for sdxlemur If there is a switch connected to PCIe root complex, the devicetree hierarchy needs to correctly reflect the physical connection. Add pci DT nodes for each switch device such as switch upstream and downstream ports. Change-Id: Ic813867df68254b51ebdc365545058925fcff35d --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index d628e771162b..6511383a1fc6 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -3,3 +3,28 @@ &soc { }; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + /* BDF 1.0.0 */ + pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 { + reg = <0 0 0 0 0>; + + /* BDF 2.1.0 */ + pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 { + reg = <0x800 0x0 0x0 0x0 0x0>; + }; + + /* BDF 2.2.0 */ + pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 { + reg = <0x1000 0x0 0x0 0x0 0x0>; + }; + + /* BDF 2.3.0 */ + pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { + reg = <0x1800 0x0 0x0 0x0 0x0>; + }; + }; +}; From 940410fd6af13edd42cb4bf57619eb16ebecc9fa Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 26 Aug 2020 15:07:37 +0530 Subject: [PATCH 0836/1809] ARM: dts: msm: add interconnect devices for sm6150 Add interconnect devices for sm6150. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I22a398c60f5d43fbc014abe9d04697bf01b9ccb7 --- qcom/sm6150.dtsi | 79 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 84627ecdbace..01cad5dff47e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include / { @@ -760,6 +762,83 @@ , , ; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; + }; + + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1F300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3F200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; aopcc: qcom,aopcc@0 { From 844bcc5e6b4fdc25904954b01a2147d158a5697d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 3 Sep 2020 16:53:59 +0530 Subject: [PATCH 0837/1809] ARM: dts: msm: Enable L3 interconnect driver for SM6150 Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: Ib1cf078b3929f3802c51dfcd17076bc6494b5d2e --- qcom/sm6150.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 01cad5dff47e..b8ed48c57741 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -967,6 +968,83 @@ #freq-domain-cells = <2>; }; + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1F300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3F200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + osm_l3: interconnect@18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm6150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; From b433f97c834d5c486dcf3e67aa97ca079b9481e5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 12:28:48 +0530 Subject: [PATCH 0838/1809] ARM: dts: msm: Add UFS support for SA6155 Add UFS host controller and UFS PHY (attached to embedded UFS card) for SA6155 platform. Change-Id: Ic75617e3d8eb406f876cc71c8931bcfee545438d --- qcom/sa6155-adp-air.dtsi | 28 +++++++++ qcom/sa6155-adp-star.dtsi | 28 +++++++++ qcom/sm6150.dtsi | 118 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-air.dtsi +++ b/qcom/sa6155-adp-air.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sa6155-adp-star.dtsi b/qcom/sa6155-adp-star.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-star.dtsi +++ b/qcom/sa6155-adp-star.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b8ed48c57741..8e8abca5d5e6 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; }; @@ -1045,6 +1047,122 @@ #interconnect-cells = <1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <1>; + limit-phy-submode = <0>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <12>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + non-removable; + + status = "disabled"; + qos0 { + mask = <0xc0>; + vote = <67>; + }; + + qos1 { + mask = <0x3f>; + vote = <67>; + }; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; From 3b525e024b84b1972bac63fad8fd8915234e91fa Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 20:18:18 +0530 Subject: [PATCH 0839/1809] ARM: dts: msm: add PMIC devices for SA6150 Add top level SPMI slave devices for PM6155. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: Ia45d71820a70e7d244a94143a3358c7a5a98fe3b --- qcom/pm6155.dtsi | 171 ++++++++++++++++++++++++++++++++++++++++++ qcom/sa6155-pmic.dtsi | 1 + qcom/sa6155p.dtsi | 6 ++ qcom/sm6150.dtsi | 22 ++++++ 4 files changed, 200 insertions(+) create mode 100644 qcom/pm6155.dtsi diff --git a/qcom/pm6155.dtsi b/qcom/pm6155.dtsi new file mode 100644 index 000000000000..4666f0ad2626 --- /dev/null +++ b/qcom/pm6155.dtsi @@ -0,0 +1,171 @@ +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm6155@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6155_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm6155_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_1_div_clk1", + "pm6155_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_1_rtc: qcom,pm6155_1_rtc { + compatible = "qcom,pm8941-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm6155_1_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm6155_1_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm6155_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm6155_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100 0x100>; + }; + + }; + + qcom,pm6155@1 { + compatible ="qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm6155 */ + qcom,pm6155@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm6155_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_2_div_clk1", + "pm6155_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm6155@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&thermal_zones { + pm6155-1-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6155_1_tz>; + wake-capable-sensor; + + trips { + pm6155_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6155_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index 0f81ce8d1397..a8824ad1c37c 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -40,3 +40,4 @@ }; #include "sa6155-regulator.dtsi" +#include "pm6155.dtsi" diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 19bc2b109289..59ff2bc74431 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -7,6 +7,12 @@ qcom,msm-id = <377 0>, <380 0>; }; +/* Delete second instance of pm6155 definitions for APQ version */ +&spmi_bus { + /delete-node/ qcom,pm6155@4; + /delete-node/ qcom,pm6155@5; +}; + &apps_rsc { /delete-node/ rpmh-regulator-modemlvl; /delete-node/ rpmh-regulator-ldoc2; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 8e8abca5d5e6..3d2a49cb91a4 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1047,6 +1047,28 @@ #interconnect-cells = <1>; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; From 3cc57456e0fa1dadc45668ef335e2dfc5db8ce83 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Thu, 28 Jan 2021 17:03:10 +0530 Subject: [PATCH 0840/1809] ARM: dts: qcom: enable display on trusted vm for yupik Enable display on trusted vm for yupik target by including display dt files. Add entry to use non secure display heap memory for TUI usecase for yupik target. Change-Id: Iaf821ddf8017f1341e23bca3a8450f0797990b7a --- qcom/yupik-ion.dtsi | 6 ++++++ qcom/yupik-vm.dtsi | 5 +++++ qcom/yupik.dtsi | 13 +++++++++++++ 3 files changed, 24 insertions(+) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index 003a0bd46c2c..a2ed081c6d53 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -54,6 +54,12 @@ memory-region = <&audio_cma_mem>; qcom,ion-heap-type = "DMA"; }; + + qcom,ion-heap@3 { /* NON SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&non_secure_display_memory>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index 46dcb20a5464..0bd0c231c776 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -1,4 +1,7 @@ #include +#include +#include +#include / { #address-cells = <0x2>; @@ -297,3 +300,5 @@ }; }; #include "lahaina-vm-ion.dtsi" +#include "display/trustedvm-yupik-sde.dtsi" +#include "display/trustedvm-yupik-sde-display.dtsi" diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 2bb77e584aec..fa4c15391916 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -432,6 +432,19 @@ size = <0x0 0x1400000>; }; + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; + }; + + splash_memory:splash_region { + reg = <0x0 0xe1000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; + qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From 771a94bcba4c4bc6f58c937c6716fe08b774f1de Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Fri, 5 Feb 2021 17:23:54 +0800 Subject: [PATCH 0841/1809] ARM: dts: qcom: change ldo for fan controller on Lahaina HHG Change ldo to L7J and voltage/load range for fan controller. And add fan controller to cooling device and add thermal mitigation rules. Change-Id: I6c3c1df60ef435699c8b091399b4e2497b70405e --- qcom/lahaina-hhg.dtsi | 217 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 207 insertions(+), 10 deletions(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index aafe0bc3d6ea..62b988aa1121 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -60,9 +60,9 @@ }; }; -&pm8008i_l7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3400000>; +&pm8008j_l7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; }; &soc { @@ -83,15 +83,10 @@ fancontroller: max31760@50 { compatible = "maxim,max31760"; reg = <0x50>; - maxim,vdd-supply = <&pm8008i_l7>; + #cooling-cells = <2>; + maxim,vdd-supply = <&pm8008j_l7>; regulator-names = "maxim,vdd"; - maxim,vdd-max-uv = <3400000>; - maxim,vdd-min-uv = <3300000>; - maxim,vdd-load-ua = <300000>; maxim,vcca-supply = <&pm8350_s10>; - maxim,vcca-max-uv = <1800000>; - maxim,vcca-min-uv = <1800000>; - maxim,vcca-load-ua = <600000>; maxim,fan_en_gpio = <&tlmm 48 0x00>; status = "ok"; }; @@ -101,3 +96,205 @@ &usb1 { qcom,ignore-wakeup-src-in-hostmode; }; + +&thermal_zones { + cpu-1-6-step { + trips { + fan_cpu16_config0: fan-cpu16-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config1: fan-cpu16-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config2: fan-cpu16-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config3: fan-cpu16-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_cpu16_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_cpu16_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_cpu16_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_cpu16_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + cpu-1-7-step { + trips { + fan_cpu17_config0: fan-cpu17-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config1: fan-cpu17-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config2: fan-cpu17-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config3: fan-cpu17-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_cpu17_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_cpu17_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_cpu17_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_cpu17_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + gpuss-0-step { + trips { + fan_gpuss0_config0: fan-gpuss0-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config1: fan-gpuss0-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config2: fan-gpuss0-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config3: fan-gpuss0-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_gpuss0_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss0_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_gpuss0_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_gpuss0_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + gpuss-1-step { + trips { + fan_gpuss1_config0: fan-gpuss1-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config1: fan-gpuss1-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config2: fan-gpuss1-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config3: fan-gpuss1-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_gpuss1_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss1_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_gpuss1_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_gpuss1_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; +}; From 63f8d3540ef687630f45a99e954be26322d347b6 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 4 Feb 2021 20:17:47 +0530 Subject: [PATCH 0842/1809] ARM: dts: msm: Enable touch for 120Hz panel on yupik idp Enable touch for 120Hz Video mode panel on yupik idp platform. Change-Id: I31dcb9262b83184fcc6ddab72caaaa3773321c7b --- qcom/yupik-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 9737865647fe..c9aa771df6cc 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -332,6 +332,7 @@ novatek,irq-gpio = <&tlmm 81 0x2008>; panel = <&dsi_nt36672e_fhd_plus_60_video + &dsi_nt36672e_fhd_plus_120_video &dsi_nt36672e_fhd_plus_144_video>; novatek,trusted-touch-mode = "vm_mode"; From 757e2d525127d48a387ee6e2eb69d6d6403dab4f Mon Sep 17 00:00:00 2001 From: Derek Chen Date: Tue, 24 Mar 2020 23:36:28 -0700 Subject: [PATCH 0843/1809] ARM: dts: msm: add audio dt files for sax155 auto platforms Add audio device tree files for SA8155 and SA6155 based automotive platforms which contains automotive specific platform nodes and device node overlays as well as snd card definitions. Change-Id: Iba760f3577198dde1771326defc97b51bb5675c4 --- bindings/sound/qcom-audio-dev.txt | 121 ++++++ qcom/sa6155-audio.dtsi | 581 +++++++++++++++++++++++++++++ qcom/sa8155-audio.dtsi | 594 ++++++++++++++++++++++++++++++ qcom/sa8155-vm-audio.dtsi | 532 ++++++++++++++++++++++++++ 4 files changed, 1828 insertions(+) create mode 100644 qcom/sa6155-audio.dtsi create mode 100644 qcom/sa8155-audio.dtsi create mode 100644 qcom/sa8155-vm-audio.dtsi diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 1c9bc157da29..f88639384966 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1690,6 +1690,7 @@ Optional properties: - qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target - qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target - qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces +- qcom,msm_audio_ssr_devs: List the snd event framework clients Example: @@ -1778,6 +1779,7 @@ Example: "msm-dai-q6-tdm.36935"; asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; }; * BENGAL ASoC Machine driver @@ -2107,6 +2109,125 @@ Example: }; +* SA6155 ASoC Machine driver + +Required properties: +- compatible : "qcom,sa6155-asoc-snd-auto" for auto adp codec and + "qcom,sa6155-asoc-snd-auto-custom" for auto custom codec. +- qcom,model : The user-visible name of this sound card. +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order given + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". +Optional properties: +- qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target +- qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target +- qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces +- qcom,msm_audio_ssr_devs: List the snd event framework clients + +Example: + + sound-adp-star { + compatible = "qcom,sa6155-asoc-snd-adp-star"; + qcom,model = "sa6155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_tx_0>, <&dai_sec_tdm_tx_1>, + <&dai_sec_tdm_tx_2>, <&dai_sec_tdm_tx_3>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_rx_1>, + <&dai_tert_tdm_rx_2>, <&dai_tert_tdm_rx_3>, + <&dai_tert_tdm_rx_4>, <&dai_tert_tdm_tx_0>, + <&dai_tert_tdm_tx_1>, <&dai_tert_tdm_tx_2>, + <&dai_tert_tdm_tx_3>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_tx_1>, <&dai_quat_tdm_tx_2>, + <&dai_quat_tdm_tx_3>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36883", + "msm-dai-q6-tdm.36885", "msm-dai-q6-tdm.36887", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36898", + "msm-dai-q6-tdm.36900", "msm-dai-q6-tdm.36902", + "msm-dai-q6-tdm.36904", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36899", "msm-dai-q6-tdm.36901", + "msm-dai-q6-tdm.36903", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36915", "msm-dai-q6-tdm.36917", + "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; + * LAHAINA ASoC Machine driver Required properties: diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi new file mode 100644 index 000000000000..572081744fbf --- /dev/null +++ b/qcom/sa6155-audio.dtsi @@ -0,0 +1,581 @@ +#include "msm-audio-lpass.dtsi" + +/ { + aliases { + i2c7 = &qupv3_se8_i2c; + }; +}; + +&msm_audio_ion { + iommus = <&apps_smmu 0x1721 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + /delete-property/ qcom,iommu-dma-addr-pool; +}; + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ter_i2s_sck_active &ter_i2s_data0_active + &ter_i2s_data1_active>; + pinctrl-1 = <&ter_i2s_sck_sleep &ter_i2s_data0_sleep + &ter_i2s_data1_sleep>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <10>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_tdm_sclk_active &quat_tdm_ws_active + &quat_tdm_data0_active &quat_tdm_data1_active + &quat_tdm_data2_active &quat_tdm_data3_active>; + pinctrl-1 = <&quat_tdm_sclk_sleep &quat_tdm_ws_sleep + &quat_tdm_data0_sleep &quat_tdm_data1_sleep + &quat_tdm_data2_sleep &quat_tdm_data3_sleep>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quin_tdm_sclk_active &quin_tdm_ws_active + &quin_tdm_data0_active &quin_tdm_data1_active>; + pinctrl-1 = <&quin_tdm_sclk_sleep &quin_tdm_ws_sleep + &quin_tdm_data0_sleep &quin_tdm_data1_sleep>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_aux_pcm_sck_active &pri_aux_pcm_ws_active + &pri_aux_pcm_data0_active &pri_aux_pcm_data1_active>; + pinctrl-1 = <&pri_aux_pcm_sck_sleep &pri_aux_pcm_ws_sleep + &pri_aux_pcm_data0_sleep &pri_aux_pcm_data1_sleep>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + snd_6155: sound-adp-star { + compatible = "qcom,sa6155-asoc-snd-adp-star"; + qcom,model = "sa6155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,tert-tdm-gpios = <&tdm_tert_rx>; + qcom,quat-tdm-gpios = <&tdm_quat_rx>; + qcom,quin-tdm-gpios = <&tdm_quin_rx>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + +&qupv3_se10_spi { + status = "ok"; + spi_codec@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha; + }; +}; + +&qupv3_se8_i2c { + status = "ok"; +}; diff --git a/qcom/sa8155-audio.dtsi b/qcom/sa8155-audio.dtsi new file mode 100644 index 000000000000..d3864c9a5e60 --- /dev/null +++ b/qcom/sa8155-audio.dtsi @@ -0,0 +1,594 @@ +#include "msm-audio-lpass.dtsi" + +/ { + aliases { + i2c7 = &qupv3_se20_i2c; + }; +}; + +&msm_audio_ion { + iommus = <&apps_smmu 0x1b21 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + /delete-property/ qcom,iommu-dma-addr-pool; +}; + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_tdm_active &sec_tdm_din_active + &sec_tdm_dout_active>; + pinctrl-1 = <&sec_tdm_sleep &sec_tdm_din_sleep + &sec_tdm_dout_sleep>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_tdm_active &tert_tdm_din_active + &tert_tdm_dout_active>; + pinctrl-1 = <&tert_tdm_sleep &tert_tdm_din_sleep + &tert_tdm_dout_sleep>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <10>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_tdm_active &quat_tdm_din_active + &quat_tdm_dout_active>; + pinctrl-1 = <&quat_tdm_sleep &quat_tdm_din_sleep + &quat_tdm_dout_sleep>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quin_tdm_active &quin_tdm_din_active + &quin_tdm_dout_active>; + pinctrl-1 = <&quin_tdm_sleep &quin_tdm_din_sleep + &quin_tdm_dout_sleep>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_aux_pcm_clk_active &pri_aux_pcm_sync_active + &pri_aux_pcm_din_active &pri_aux_pcm_dout_active>; + pinctrl-1 = <&pri_aux_pcm_clk_sleep &pri_aux_pcm_sync_sleep + &pri_aux_pcm_din_sleep &pri_aux_pcm_dout_sleep>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + snd_8155: sound-adp-star { + compatible = "qcom,sa8155-asoc-snd-adp-star"; + qcom,model = "sa8155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,sec-tdm-gpios = <&tdm_sec_rx>; + qcom,tert-tdm-gpios = <&tdm_tert_rx>; + qcom,quat-tdm-gpios = <&tdm_quat_rx>; + qcom,quin-tdm-gpios = <&tdm_quin_rx>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + +&qupv3_se20_i2c { + status = "ok"; + + pinctrl-0 = <&qupv3_se20_i2c_active + &audio_ioexp_reset_active>; + + gpio@3e { + compatible = "semtech,sx1509q"; + reg = <0x3e>; + semtech,probe-reset; + }; +}; + +&qupv3_se22_spi { + status = "ok"; + spi_codec@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha; + }; +}; diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi new file mode 100644 index 000000000000..9c5a795cb9f8 --- /dev/null +++ b/qcom/sa8155-vm-audio.dtsi @@ -0,0 +1,532 @@ +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + /delete-property/ iommus; + /delete-property/ qcom,iommu-dma-addr-pool; +}; + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <3>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <12>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + snd_x155: sound-adp-star { + compatible = "qcom,sa8155-asoc-snd-adp-star"; + qcom,model = "sa8155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + From 5fa6f4f96033566a52c24f5c210240cb4d6be2b5 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Mon, 25 Jan 2021 15:46:22 +0530 Subject: [PATCH 0844/1809] ARM: dts: msm: Add pin control for HSP (WCN6850) Add WLAN EN pin control to power on HSP (WCN6850) card. Change-Id: I32352a0cc575ca5d3f16cf332085f7e948f3f77d --- qcom/yupik-pinctrl.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 69ddb1b18cef..9d3996f2b2a1 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -2972,5 +2972,35 @@ }; }; }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; }; }; From 361a951efc9009555d90ce0a02b5883b97409ef8 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Mon, 8 Feb 2021 13:40:54 +0530 Subject: [PATCH 0845/1809] ARM: dts: msm: Add GPII base and GPII IRQ for VM static configs This change provides designated GPII base address and GPII interrupt number for static mapping into the VM configs. Change-Id: Iac486eaeae2b1dece9658330d6e81e7dc7aef09a --- qcom/yupik-vm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index 46dcb20a5464..069d439edd06 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -100,7 +100,7 @@ image-name = "qcom,trustedvm"; qcom,pasid = <0x0 0x1c>; - iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0 + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1 0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1 0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1 @@ -108,7 +108,7 @@ 0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; - gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */ + gic-irq-ranges = <316 316>; /* PVM->SVM IRQ transfer */ memory { #address-cells = <0x2>; From e7238211dbbab498038da56dcc90c4ae08e1a496 Mon Sep 17 00:00:00 2001 From: Fei Tong Date: Fri, 10 Jul 2020 10:02:55 +0800 Subject: [PATCH 0846/1809] ARM: dts: msm: add se22 spi alias Add se22 spi alias for audio codec spi node Change-Id: Ie51451416c4db25008411e4a799166a423afb4dd --- qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index cee47b76149d..8c09825d7798 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -40,6 +40,7 @@ pci-domain1 = &pcie1; /* PCIe1 domain */ serial0 = &qupv3_se12_2uart; hsuart0 = &qupv3_se13_4uart; + spi2 = &qupv3_se22_spi; }; cpus { From 0669c47f29a5f0e0cc32d1855f1b2cec480a024e Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Mon, 8 Feb 2021 17:05:05 +0800 Subject: [PATCH 0847/1809] ARM: dts: msm: update wsa node for yupik qrd audio Update wsa node for yupik qrd audio. Change-Id: Ia683ea28c86ecf81b4e808ef67f6ee658087dca6 --- qcom/yupik-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index c3d55c5624f6..8c02fce25000 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -389,6 +389,10 @@ status = "disabled"; }; +&wsa883x_0222 { + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; +}; + &swr_haptics { status = "okay"; swr-slave-supply = <&hap_swr_slave_reg>; From 5f06aa0ac55f5f7f03e011c98bc4772388633b63 Mon Sep 17 00:00:00 2001 From: Chennakesava Raju Eluru Date: Tue, 2 Feb 2021 15:11:55 +0530 Subject: [PATCH 0848/1809] ARM: dts: msm: Update dtsi entries for fastrpc context banks Configure fastrpc context banks Change-Id: I58e50b82e277f348335fbbd32a15e2878141f8b3 --- qcom/scuba-iot.dtsi | 55 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 14fc3b99340f..cbdc56f032ff 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -647,6 +647,61 @@ dcc: dcc_v2@1be2000 { #mbox-cells = <1>; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + }; + rpm-glink { compatible = "qcom,glink-rpm"; interrupts = ; From 58486553d399d7f3f2192bbf07a5a431afe5d482 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Mon, 8 Feb 2021 23:03:44 +0530 Subject: [PATCH 0849/1809] ARM: dts: msm: disable masking MSI interrupts at EP side Disable masking MSI interrupts at EP side. Change-Id: I79965e7ad50ea21bf6503d8474e223f5094738ea --- qcom/shima-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index e5909870ea8e..679206758308 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -114,6 +114,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,msi_mask_disable; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; From 34ca1cf8152b7ae344155ca31d38d107160fb350 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Mon, 8 Feb 2021 23:13:48 +0530 Subject: [PATCH 0850/1809] dt-bindings: arm: msm: Add entry to disable masking MSI interrupts at EP Disable masking MSI interrupts at EP side. Change-Id: Idd7af1bcb6839964bf385158a75596c0978af6da --- bindings/pci/pci-msm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 27741ba20e1c..5998845151a4 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -400,6 +400,9 @@ interconnects: Value type: Definition: PCIe PHY initialization sequence +- qcom,msi_mask_disable: + Usage: optional + Definition: Disable masking MSI interrupts at EP side ============== Root port node From f614d8a2f5c8ed079950ed02b1612bcc969380be Mon Sep 17 00:00:00 2001 From: Xiaowen Wu Date: Mon, 8 Feb 2021 12:44:46 -0800 Subject: [PATCH 0851/1809] ARM: dts: msm: clean up display references for sa8155/sa8195 Clean up display references for sa8155/sa8195 and fix missing node when shd .dtsi is included. Change-Id: Ib7a9a559faef4f40a1ebd5f918c4da190b646e61 --- qcom/sa8155-adp-star.dts | 1 - qcom/sa8155-v2-adp-air.dts | 4 +--- qcom/sa8155-v2-adp-star.dts | 1 - qcom/sa8155p-adp-star.dts | 1 - qcom/sa8155p-v2-adp-air-lxc-overlay.dts | 3 +-- qcom/sa8155p-v2-adp-air-overlay.dts | 3 +-- qcom/sa8155p-v2-adp-air.dts | 4 +--- qcom/sa8155p-v2-adp-star.dts | 1 - qcom/sa8195p-adp-star.dts | 3 +-- qcom/sa8195p-v2-adp-air-lxc-overlay.dts | 3 +-- qcom/sa8195p-v2-adp-air-overlay.dts | 1 - qcom/sa8195p-v2-adp-air.dts | 4 +--- qcom/sa8195p-v2-adp-air.dtsi | 1 + qcom/sdmshrike.dtsi | 6 +++--- 14 files changed, 11 insertions(+), 25 deletions(-) diff --git a/qcom/sa8155-adp-star.dts b/qcom/sa8155-adp-star.dts index b6a703a985b5..1be5c92116a7 100644 --- a/qcom/sa8155-adp-star.dts +++ b/qcom/sa8155-adp-star.dts @@ -2,7 +2,6 @@ #include "sa8155-v1.dtsi" #include "sa8155-adp-star.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 ADP-STAR"; diff --git a/qcom/sa8155-v2-adp-air.dts b/qcom/sa8155-v2-adp-air.dts index fb99004d2e49..9877d0ab106f 100644 --- a/qcom/sa8155-v2-adp-air.dts +++ b/qcom/sa8155-v2-adp-air.dts @@ -1,9 +1,7 @@ /dts-v1/; #include "sa8155-v2.dtsi" -#include "sa8155-adp-common.dtsi" -#include "display/sa8155-adp-star-display.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" +#include "sa8155-adp-star.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 V2 ADP AIR"; diff --git a/qcom/sa8155-v2-adp-star.dts b/qcom/sa8155-v2-adp-star.dts index 59fd12b62ecb..bb5b257a53a3 100644 --- a/qcom/sa8155-v2-adp-star.dts +++ b/qcom/sa8155-v2-adp-star.dts @@ -2,7 +2,6 @@ #include "sa8155-v2.dtsi" #include "sa8155-adp-star.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 V2 ADP STAR"; diff --git a/qcom/sa8155p-adp-star.dts b/qcom/sa8155p-adp-star.dts index a6f77a6b13e2..3472b77f72c0 100644 --- a/qcom/sa8155p-adp-star.dts +++ b/qcom/sa8155p-adp-star.dts @@ -2,7 +2,6 @@ #include "sa8155p.dtsi" #include "sa8155-adp-star.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P ADP-STAR"; diff --git a/qcom/sa8155p-v2-adp-air-lxc-overlay.dts b/qcom/sa8155p-v2-adp-air-lxc-overlay.dts index 08e7c1a4b79a..3c257f42c1aa 100644 --- a/qcom/sa8155p-v2-adp-air-lxc-overlay.dts +++ b/qcom/sa8155p-v2-adp-air-lxc-overlay.dts @@ -1,8 +1,7 @@ /dts-v1/; /plugin/; -#include "sa8155-adp-common.dtsi" -#include "display/sa8155-adp-star-display.dtsi" +#include "sa8155-adp-star.dtsi" #include "display/sa8155-v2-adp-air-display-lxc-shd.dtsi" / { diff --git a/qcom/sa8155p-v2-adp-air-overlay.dts b/qcom/sa8155p-v2-adp-air-overlay.dts index fd881bfdaa06..91e2c7a5b513 100644 --- a/qcom/sa8155p-v2-adp-air-overlay.dts +++ b/qcom/sa8155p-v2-adp-air-overlay.dts @@ -1,8 +1,7 @@ /dts-v1/; /plugin/; -#include "sa8155-adp-common.dtsi" -#include "display/sa8155-adp-star-display.dtsi" +#include "sa8155-adp-star.dtsi" #include "display/sa8155-adp-star-display-shd.dtsi" / { diff --git a/qcom/sa8155p-v2-adp-air.dts b/qcom/sa8155p-v2-adp-air.dts index 56731ff9e3af..e1057725f2d5 100644 --- a/qcom/sa8155p-v2-adp-air.dts +++ b/qcom/sa8155p-v2-adp-air.dts @@ -1,9 +1,7 @@ /dts-v1/; #include "sa8155p-v2.dtsi" -#include "sa8155-adp-common.dtsi" -#include "display/sa8155-adp-star-display.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" +#include "sa8155-adp-star.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P V2 ADP AIR"; diff --git a/qcom/sa8155p-v2-adp-star.dts b/qcom/sa8155p-v2-adp-star.dts index 4f9780a53a42..ef21fb5e1883 100644 --- a/qcom/sa8155p-v2-adp-star.dts +++ b/qcom/sa8155p-v2-adp-star.dts @@ -2,7 +2,6 @@ #include "sa8155p-v2.dtsi" #include "sa8155-adp-star.dtsi" -#include "display/sa8155-adp-star-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155P V2 ADP STAR"; diff --git a/qcom/sa8195p-adp-star.dts b/qcom/sa8195p-adp-star.dts index 6e00a1813e86..967583803996 100644 --- a/qcom/sa8195p-adp-star.dts +++ b/qcom/sa8195p-adp-star.dts @@ -1,8 +1,7 @@ /dts-v1/; #include "sa8195p.dtsi" -#include "sa8195p-adp-common.dtsi" -#include "display/sa8195p-adp-star-display-shd.dtsi" +#include "sa8195p-adp-star.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR"; diff --git a/qcom/sa8195p-v2-adp-air-lxc-overlay.dts b/qcom/sa8195p-v2-adp-air-lxc-overlay.dts index 1d57b6a2338b..398eae1ad3cd 100644 --- a/qcom/sa8195p-v2-adp-air-lxc-overlay.dts +++ b/qcom/sa8195p-v2-adp-air-lxc-overlay.dts @@ -1,8 +1,7 @@ /dts-v1/; /plugin/; -#include "sa8195p-adp-common.dtsi" -#include "display/sa8195p-adp-star-display.dtsi" +#include "sa8195p-v2-adp-air.dtsi" #include "display/sa8195p-v2-adp-air-display-lxc-shd.dtsi" / { diff --git a/qcom/sa8195p-v2-adp-air-overlay.dts b/qcom/sa8195p-v2-adp-air-overlay.dts index 9b3cf9300f5f..99ea48278a27 100644 --- a/qcom/sa8195p-v2-adp-air-overlay.dts +++ b/qcom/sa8195p-v2-adp-air-overlay.dts @@ -2,7 +2,6 @@ /plugin/; #include "sa8195p-v2-adp-air.dtsi" -#include "display/sa8195p-adp-star-display.dtsi" #include "display/sa8195p-adp-star-display-shd.dtsi" / { diff --git a/qcom/sa8195p-v2-adp-air.dts b/qcom/sa8195p-v2-adp-air.dts index f2b96c2ca359..e128ecfdfd92 100644 --- a/qcom/sa8195p-v2-adp-air.dts +++ b/qcom/sa8195p-v2-adp-air.dts @@ -1,9 +1,7 @@ /dts-v1/; #include "sa8195p.dtsi" -#include "sa8195p-adp-common.dtsi" -#include "display/sa8195p-adp-star-display.dtsi" -#include "display/sa8195p-adp-star-display-shd.dtsi" +#include "sa8195p-v2-adp-air.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR"; diff --git a/qcom/sa8195p-v2-adp-air.dtsi b/qcom/sa8195p-v2-adp-air.dtsi index ec4afde21db4..91b92282255e 100644 --- a/qcom/sa8195p-v2-adp-air.dtsi +++ b/qcom/sa8195p-v2-adp-air.dtsi @@ -1 +1,2 @@ #include "sa8195p-adp-common.dtsi" +#include "display/sa8195p-adp-star-display.dtsi" diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7d54e7b22864..dfacdb101182 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -439,9 +439,6 @@ soc: soc { }; }; -#include "display/sdmshrike-sde-pll.dtsi" -#include "display/sdmshrike-sde.dtsi" - &soc { #address-cells = <1>; #size-cells = <1>; @@ -2022,6 +2019,9 @@ #include "sdmshrike-gpu.dtsi" #include "sa8195-vidc.dtsi" +#include "display/sdmshrike-sde-pll.dtsi" +#include "display/sdmshrike-sde.dtsi" + &firmware { scm { compatible = "qcom,scm"; From e44364c8b99da5829e354efc917c2dbe1a4ced7b Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Thu, 10 Sep 2020 22:37:57 +0530 Subject: [PATCH 0852/1809] ARM: dts: msm: Add dtsi entry for ssg hlos drivers The following changes are added: 1. Add qseecom node for sdmshrike 2. Enable QRNG driver for sdmshrike. 3. Add shmbridge node for sdmshrike. 4. Add smcinvoke node for sdmshrike. 5. Add tz_log node for sdmshrike. Change-Id: I1cb40f21fde0b52dba48bc342902f677d9dada46 --- qcom/sdmshrike.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7d54e7b22864..8d3aceb5a914 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1917,6 +1917,51 @@ mbox-names = "cdsp-pil"; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>; + clock-names = "km_clk_src"; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + }; + + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + }; + + qcom_tzlog: tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + qcom,npu@9800000 { compatible = "qcom,pil-tz-generic"; reg = <0x9800000 0x800000>; From dfe3cd6561ddebaea8090833197e5e8514e8cdc2 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Tue, 9 Feb 2021 12:23:39 +0800 Subject: [PATCH 0853/1809] ARM: dts: qcom: update usb2 phy setting on YUPIK QRD update override X1 and X2. Change-Id: Ia65524ec6360c1629a2e65548f0b5653dc439386 --- qcom/yupik-qrd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index c3d55c5624f6..8a872d8cce16 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -565,3 +565,8 @@ }; }; + +&usb2_phy0 { + qcom,param-override-seq = <0x0f 0x70 + 0x2c 0x74>; +}; From 1b7064299cdfae8bf4f495069a17c33da1883af1 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Tue, 9 Feb 2021 10:13:24 +0530 Subject: [PATCH 0854/1809] ARM: dts: msm: Add flag to disable the DMA mode Add "qcom,disable-dma" flag to change SE mode from DMA mode to FIFO mode for SSC QUP on SA8155 and S8195 platform. Change-Id: Ia9e553bef9dd68dc7539c472cdcf45211c1ebec1 --- qcom/sa8195-ssc-qupv3.dtsi | 3 +++ qcom/sm8150-ssc-qupv3.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/qcom/sa8195-ssc-qupv3.dtsi b/qcom/sa8195-ssc-qupv3.dtsi index cf0506dd1c30..03788ace6264 100644 --- a/qcom/sa8195-ssc-qupv3.dtsi +++ b/qcom/sa8195-ssc-qupv3.dtsi @@ -29,6 +29,7 @@ pinctrl-0 = <&qupv3_se20_i2c_active>; pinctrl-1 = <&qupv3_se20_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; @@ -46,6 +47,7 @@ pinctrl-0 = <&qupv3_se21_i2c_active>; pinctrl-1 = <&qupv3_se21_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; @@ -63,6 +65,7 @@ pinctrl-0 = <&qupv3_se22_i2c_active>; pinctrl-1 = <&qupv3_se22_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; diff --git a/qcom/sm8150-ssc-qupv3.dtsi b/qcom/sm8150-ssc-qupv3.dtsi index 33183503124e..f7497278802e 100644 --- a/qcom/sm8150-ssc-qupv3.dtsi +++ b/qcom/sm8150-ssc-qupv3.dtsi @@ -29,6 +29,7 @@ pinctrl-0 = <&qupv3_se20_i2c_active>; pinctrl-1 = <&qupv3_se20_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; @@ -46,6 +47,7 @@ pinctrl-0 = <&qupv3_se21_i2c_active>; pinctrl-1 = <&qupv3_se21_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; @@ -63,6 +65,7 @@ pinctrl-0 = <&qupv3_se22_i2c_active>; pinctrl-1 = <&qupv3_se22_i2c_sleep>; qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; status = "disabled"; }; From 7b224db0db269a116134f367b565723e0b01ff9b Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Thu, 10 Sep 2020 22:08:27 +0530 Subject: [PATCH 0855/1809] ARM: dts: msm: Add dtsi entry for ssg hlos drivers The following changes are added: 1. Add qseecom node for msmnile 2. Enable QRNG driver for msmnile. 3. Add shmbridge node for msmnile. 4. Add smcinvoke node for msmnile. 5. Add tz_log node for msmnile. Change-Id: I7573b3acead185dd0100f9862c2348ab25c2cf76 --- qcom/sm8150.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index cee47b76149d..695d937a5ee6 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -329,8 +329,10 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - no-map; - reg = <0x0 0x9e400000 0x0 0x1400000>; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions { @@ -2366,6 +2368,51 @@ qcom,dump-id = <0x127>; }; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>; + clock-names = "km_clk_src"; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + }; + + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + }; + + qcom_tzlog: tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + }; &firmware { From 5cb46307a4122c8856c9a0bd093b589f0ae313c3 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Fri, 11 Sep 2020 22:12:13 +0530 Subject: [PATCH 0856/1809] ARM: dts: msm: Add SMMU devices for SM6150 Add the device tree nodes that describe the APPS and graphics SMMU for SM6150. Change-Id: I1e8af4c7297294165a60d9acdf6ac450d5b0fd3f --- qcom/msm-arm-smmu-sm6150.dtsi | 249 ++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 2 + 2 files changed, 251 insertions(+) create mode 100644 qcom/msm-arm-smmu-sm6150.dtsi diff --git a/qcom/msm-arm-smmu-sm6150.dtsi b/qcom/msm-arm-smmu-sm6150.dtsi new file mode 100644 index 000000000000..ebf2aaeeaf3d --- /dev/null +++ b/qcom/msm-arm-smmu-sm6150.dtsi @@ -0,0 +1,249 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x50a0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x50a0000 0x10000>, + <0x50c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x50c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c5000 0x1000>, + <0x50c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x50c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c9000 0x1000>, + <0x50c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@0x150c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c5000 0x1000>, + <0x150c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_2_tbu: anoc_2_tbu@0x150c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c9000 0x1000>, + <0x150c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150cd000 0x1000>, + <0x150c2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d1000 0x1000>, + <0x150c2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; + }; + + compute_dsp_tbu: compute_dsp_tbu@0x150d5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d5000 0x1000>, + <0x150c2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + /* No GDSC */ + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + adsp_tbu: adsp_tbu@0x150d9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d9000 0x1000>, + <0x150c2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x7ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF and SF TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 3d2a49cb91a4..a11584c45c7f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1663,3 +1663,5 @@ &venus_gdsc { status = "ok"; }; + +#include "msm-arm-smmu-sm6150.dtsi" From 4cd166d1dbf3c7196a168839ad240664d7121dbc Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 12 Oct 2020 18:17:07 +0530 Subject: [PATCH 0857/1809] ARM: dts: msm: Add lpass device node for PIL on SM6150 Add PIL device tree node to load firmware images of lpass on SM6150. Change-Id: Ifd99f607bed9da77494d0b0f188bf4e23bfb5711 --- qcom/sa6155-pmic.dtsi | 6 ++++++ qcom/sm6150.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index a8824ad1c37c..313bd701ba65 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -39,5 +39,11 @@ /delete-node/ rpmh-regulator-bobc1; }; +&soc { + qcom,lpass@62400000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; +}; + #include "sa6155-regulator.dtsi" #include "pm6155.dtsi" diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a11584c45c7f..d5a5e22c57c6 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. SM6150"; @@ -1560,6 +1561,50 @@ #interrupt-cells = <2>; }; }; + + qcom,lpass@62400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x62400000 0x00100>; + + vdd_cx-supply = <&L8A_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "sm6150-qupv3.dtsi" From a5872a70b20f83ccd3b3ad6ae5e254297f4df0e3 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Tue, 13 Oct 2020 19:01:13 +0530 Subject: [PATCH 0858/1809] ARM: dts: msm: Add turing device node for PIL on SM6150 Add PIL device tree node to load firmware image of turing on SM6150. Change-Id: Id3f7b5aa613ff71eef4e6ec7588b72f97c5788cd --- qcom/sm6150.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index d5a5e22c57c6..a178bd4df490 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1605,6 +1605,50 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "sm6150-qupv3.dtsi" From 3a6586d2701788d788a3bd3a12b3965f1e021611 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Tue, 13 Oct 2020 19:15:06 +0530 Subject: [PATCH 0859/1809] ARM: dts: msm: Add venus device node for PIL on SM6150 Add PIL device tree node to load firmware images of venus on SM6150. Change-Id: I53e95d989f1a8e56d89cee5c9c15e3e5e03b7cc1 --- qcom/sm6150.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a178bd4df490..ecf2201756e0 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1649,6 +1649,28 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "sm6150-qupv3.dtsi" From 876d50d754f2066212f167caff6b92b8d00ad1a1 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 15 Oct 2020 19:19:46 +0530 Subject: [PATCH 0860/1809] ARM: dts: msm: Enable device nodes for PIL on SM6150 Enable PIL device tree nodes to load firmware images of venus, lpasss, turing on SM6150. Change-Id: I64ce4f777adf264c060ba2dab777bc690c90efef --- qcom/sa6155-adp-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index c2d9e07465c0..3cd8585afb01 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -3,3 +3,17 @@ &qupv3_0 { status = "ok"; }; + +&soc { + qcom,lpass@62400000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,turing@8300000 { + status = "ok"; + }; +}; From 4f062ac632a08e10d84a345f7cacfa4ff918e7bd Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Mon, 8 Feb 2021 14:59:40 +0530 Subject: [PATCH 0861/1809] ARM: dts: msm: Add devicetree support for HSP (WCN6850) Add devicetree changes for supporting HSP card (WCN6850). Change-Id: Ibeb7ccbe378338175e9f6027efc0a59b92d67c79 --- qcom/qcx6490-cnss.dtsi | 208 +++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 9 ++ 2 files changed, 217 insertions(+) create mode 100644 qcom/qcx6490-cnss.dtsi diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi new file mode 100644 index 000000000000..61287b0d4633 --- /dev/null +++ b/qcom/qcx6490-cnss.dtsi @@ -0,0 +1,208 @@ + +&soc { + wlan: qcom,cnss-qca6490@b0000000 { + compatible = "qcom,cnss-qca6490"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 84 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x420000>; + qcom,wlan-cbc-enabled; + + vdd-wlan-aon-supply = <&S7B>; + qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; + vdd-wlan-dig-supply = <&S7B>; + qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>; + vdd-wlan-io-supply = <&L19B>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-rfa1-supply = <&S1B>; + qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>; + vdd-wlan-rfa2-supply = <&S8B>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + wlan-ant-switch-supply = <&L11C>; + qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; + + interconnects = + <&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <7>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <2250 390000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <7500 390000>, + /* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <30000 790000>, + /* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <100000 790000>, + /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ + <175000 1600000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz + * ddr: 547.2 MHz + */ + <7500 390000>, + + /** ICC Path 2 **/ + <0 0>, + <2250 1804800>, + <7500 1804800>, + <30000 1804800>, + <100000 1804800>, + <175000 6220800>, + <7500 2188800>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <0>; + mhi,priority = <2>; + mhi,brstmode = <2>; + mhi,data-type = <3>; + }; + }; + + mhi_devices { + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + qcom,low-latency; + }; + }; + }; + +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + }; +}; + +&pil_wpss { + status = "disabled"; +}; + +&icnss2 { + status = "disabled"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index db12a24678dc..a9e0071e64ba 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -509,6 +509,15 @@ reg = <0x0 0xe3300000 0x0 0x0100000>; label = "dfps_data_memory"; }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + }; &soc { From 12000747f1f4b6762a179db5d695258cd3a5eb15 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sun, 31 Jan 2021 11:35:27 +0530 Subject: [PATCH 0862/1809] ARM: dts: msm: Add configuration for vref regulator vote for YUPIK Add regulator configuration for vref regulators so that LMH driver can place a active only vote for yupik. Change-Id: I4b8645201526a2baa2bdc2167d6b464925f047fd --- qcom/yupik-thermal.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index d6326e668327..09800af991a3 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -183,6 +183,14 @@ }; }; + qcom,limits-dcvs { + compatible = "qcom,msm-hw-limits"; + isens_vref_0p8-supply = <&pm8350c_l10_ao>; + isens-vref-0p8-settings = <880000 880000 30000>; + isens_vref_1p8-supply = <&pm8350c_l1_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; + qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; apc1_cluster: qcom,apc1-cluster { From da6330fe75dd9e2a85dc06fe38decce51c85c2d7 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 9 Feb 2021 17:19:41 +0530 Subject: [PATCH 0863/1809] ARM: dts: msm: Reorganize the apps_rsc and mxlvl node for sa8195 Move the 'apps_rsc' node to the beginning of the 'soc' node such that the rpmh-regulator devices are populated early in the boot process. As many consumers' probe depend on these regulator devices, placing 'apps_rsc' at the beginning would satisfy the consumer devices as soon as they are populated later in the boot. This way, the drivers no longer have to wait for the regulator devices to be populated, thus optimizing the boot performance. Change-Id: I8f760a8e3eb3c0e301e5866d83e828208743c183 --- qcom/sa8195-regulator.dtsi | 130 ++++++++++++++++++------------------- qcom/sdmshrike.dtsi | 64 +++++++++--------- 2 files changed, 97 insertions(+), 97 deletions(-) diff --git a/qcom/sa8195-regulator.dtsi b/qcom/sa8195-regulator.dtsi index 4317499b6ade..5f6d6bfe0bee 100644 --- a/qcom/sa8195-regulator.dtsi +++ b/qcom/sa8195-regulator.dtsi @@ -31,6 +31,71 @@ }; }; + /* PM8150C S3 + S4 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: S3C_LEVEL: + pm8150c_s3_level: regulator-pm8150c-s3-level { + regulator-name = "pm8150c_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S3C_LEVEL_AO: + pm8150c_s3_level_ao: regulator-pm8150c-s3-level-ao { + regulator-name = "pm8150c_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150_2 regulators */ + /* PM8150_2 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + pm8150_2_s3_level-parent-supply = <&VDD_MX_LEVEL>; + pm8150_2_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: S3E_LEVEL: + pm8150_2_s3_level: regulator-pm8150_2-s3-level { + regulator-name = "pm8150_2_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3E_LEVEL_AO: + pm8150_2_s3_level_ao: regulator-pm8150_2-s3-level-ao { + regulator-name = "pm8150_2_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + rpmh-regulator-ldoa3 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldoa3"; @@ -248,41 +313,6 @@ }; }; - /* PM8150_2 regulators */ - /* PM8150_2 S3 + S2 + S1 = VDD_CX supply */ - rpmh-regulator-cxlvl { - compatible = "qcom,rpmh-arc-regulator"; - qcom,resource-name = "cx.lvl"; - pm8150_2_s3_level-parent-supply = <&VDD_MX_LEVEL>; - pm8150_2_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; - - VDD_CX_LEVEL: S3E_LEVEL: - pm8150_2_s3_level: regulator-pm8150_2-s3-level { - regulator-name = "pm8150_2_s3_level"; - qcom,set = ; - regulator-min-microvolt - = ; - regulator-max-microvolt - = ; - qcom,init-voltage-level - = ; - qcom,min-dropout-voltage-level = <(-1)>; - }; - - VDD_CX_LEVEL_AO: S3E_LEVEL_AO: - pm8150_2_s3_level_ao: regulator-pm8150_2-s3-level-ao { - regulator-name = "pm8150_2_s3_level_ao"; - qcom,set = ; - regulator-min-microvolt - = ; - regulator-max-microvolt - = ; - qcom,init-voltage-level - = ; - qcom,min-dropout-voltage-level = <(-1)>; - }; - }; - rpmh-regulator-smpe4 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpe4"; @@ -585,36 +615,6 @@ }; }; - /* PM8150C S3 + S4 = VDD_MX supply */ - rpmh-regulator-mxlvl { - compatible = "qcom,rpmh-arc-regulator"; - qcom,resource-name = "mx.lvl"; - - VDD_MX_LEVEL: S3C_LEVEL: - pm8150c_s3_level: regulator-pm8150c-s3-level { - regulator-name = "pm8150c_s3_level"; - qcom,set = ; - regulator-min-microvolt - = ; - regulator-max-microvolt - = ; - qcom,init-voltage-level - = ; - }; - - VDD_MX_LEVEL_AO: S3C_LEVEL_AO: - pm8150c_s3_level_ao: regulator-pm8150c-s3-level-ao { - regulator-name = "pm8150c_s3_level_ao"; - qcom,set = ; - regulator-min-microvolt - = ; - regulator-max-microvolt - = ; - qcom,init-voltage-level - = ; - }; - }; - /* PM8150C S5 = VDDA_EBI supply */ rpmh-regulator-ebilvl { compatible = "qcom,rpmh-arc-regulator"; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7d54e7b22864..97c6d492208c 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -469,6 +469,38 @@ interrupt-controller; }; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; + + system_pm { + compatible = "qcom,system-pm"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, @@ -1021,38 +1053,6 @@ clock-frequency = <32768>; }; - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x18200000 0x10000>, - <0x18210000 0x10000>, - <0x18220000 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - status = "okay"; - }; - - system_pm { - compatible = "qcom,system-pm"; - }; - }; - disp_rsc: rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; From dd564c25771ee0c97673ee7faca10e6795bb8975 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Wed, 22 Apr 2020 12:47:55 -0400 Subject: [PATCH 0864/1809] ARM: dts: msm: add hgsl to sa8195 vm for GPU doorbell This change is to enable GPU doorbell feature on sa8195 Linux GVM. Change-Id: I7d9c6f63bbcc4d7507071d4a81de2f668ecf81cd --- qcom/sa8195-vm.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 19700893437d..55f0f5e93385 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -342,6 +342,66 @@ regulator-min-microvolt = ; regulator-max-microvolt = ; }; + + tcsr_compute_signal_glb: syscon@0x1fd8000 { + compatible = "syscon"; + reg = <0x1fd8000 0x1000>; + }; + + tcsr_compute_signal_sender0: syscon@0x1fd9000 { + compatible = "syscon"; + reg = <0x1fd9000 0x1000>; + }; + + tcsr_compute_signal_sender1: syscon@0x1fdd000 { + compatible = "syscon"; + reg = <0x1fdd000 0x1000>; + }; + + tcsr_compute_signal_receiver0: syscon@0x1fdb000 { + compatible = "syscon"; + reg = <0x1fdb000 0x1000>; + }; + + tcsr_compute_signal_receiver1: syscon@0x1fdf000 { + compatible = "syscon"; + reg = <0x1fdf000 0x1000>; + }; + + hgsl_tcsr_sender0: hgsl_tcsr_sender0 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender0>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_sender1: hgsl_tcsr_sender1 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender1>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver0>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + }; + + hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver1>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + }; + + msm_gpu_hyp: qcom,hgsl@0x2c00000 { + compatible = "qcom,hgsl"; + reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; + reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + + qcom,glb-db-senders = <&hgsl_tcsr_sender0 + &hgsl_tcsr_sender1>; + qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 + &hgsl_tcsr_receiver1>; + }; }; ®ulator { From 23f4a63fe4f9e47b48ab875bf697491532caaac9 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 9 Dec 2020 17:07:11 +0530 Subject: [PATCH 0865/1809] ARM: dts: msm: Enable smcinvoke and shmbridge This change adds dts entries for smcinvoke and shmbridge on olympic target. Change-Id: Ia65bd2774ab2eb88c633373358d2dbba03832f3b --- qcom/sdxlemur.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 8c8f85c9c5d5..4200b0293c6b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1350,6 +1350,15 @@ qcom,client-id = <0x00000001>; qcom,vm-nav-path; }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + qcom,support-legacy_smc; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; }; #include "sdxlemur-pinctrl.dtsi" From 8372ab4f1706ef3cf05a55abee91833604438795 Mon Sep 17 00:00:00 2001 From: NITHEESH MUTHURAJ Date: Tue, 19 Jan 2021 21:59:54 -0800 Subject: [PATCH 0866/1809] ARM: dts: msm: Add Additional speed bins for supported devices Add new speed bins nodes to support new efuse values. Change-Id: Idf5061579c5c3777859bd3a31aa2ee41e1e14faf --- qcom/lahaina-v2-gpu.dtsi | 517 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 517 insertions(+) diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 7b23189b324a..23b477a5fa54 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -382,5 +382,522 @@ qcom,acd-level = <0x882f5ffd>; }; }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <3>; + qcom,initial-pwrlevel = <10>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <5>; + qcom,initial-pwrlevel = <9>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <7>; + qcom,initial-pwrlevel = <9>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; }; }; From 5e000aa445cca86c36148ad59524eecec8bd8c4c Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 3 Feb 2021 10:30:14 +0530 Subject: [PATCH 0867/1809] ARM: dts: msm: Add PM8008 GPIO and regulators to scuba-iot Add PM8008 GPIOs and regulators to scuba-iot devicetree. Change-Id: Ic8d278e97aff99293fb1e753fd3486161eb7e387 --- qcom/scuba-iot.dtsi | 109 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 14fc3b99340f..6ca87482f2fd 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -824,6 +824,115 @@ dcc: dcc_v2@1be2000 { #include "scuba-ion.dtsi" #include "msm-arm-smmu-scuba.dtsi" +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + }; + + pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + pm8008_en-supply = <&PM8008_EN>; + + vdd_l1_l2-supply = <&S3A>; + + L1P: qcom,pm8008-l1@4000 { + reg = <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1256000>; + qcom,min-dropout-voltage = <75000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1144000>; + qcom,min-dropout-voltage = <187500>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4500 { + reg = <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4600 { + reg = <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1656000>; + regulator-max-microvolt = <1896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + }; + }; +}; + &pm2250_vadc { #address-cells = <1>; #size-cells = <0>; From 00fa966b6ba68bc9746f180df1df1b1a1e60a1b7 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Thu, 4 Feb 2021 23:06:44 +0800 Subject: [PATCH 0868/1809] ARM: dts: msm: Remove "msr-fix-req" label from some TPDMs Need to remove "msr-fix-req" label from some TPDMs since it will cause registers are not written properly. Change-Id: I2bb9827675b7cefc83e7779cb641d14f6b3b3cd8 --- qcom/yupik-coresight.dtsi | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 1f4f76565028..3ec1143b6fe8 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -450,8 +450,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_swao1_out_tpda_swao: endpoint { @@ -919,8 +917,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_lpass_out_funnel_lpass: endpoint { @@ -942,8 +938,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_dl_south_out_tpda_dlct5: endpoint { @@ -1082,8 +1076,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_turing_out_funnel_turing: endpoint { @@ -1244,8 +1236,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_ddr_ch01_out_funnel_ddr_ch01: endpoint { @@ -1268,8 +1258,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_ddr_out_funnel_ddr_0: endpoint { @@ -1292,8 +1280,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_shrm_out_funnel_ddr_0: endpoint { @@ -1420,8 +1406,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_dlct_out_tpda_dlct5: endpoint { @@ -1443,8 +1427,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_ipcc_out_tpda_dlct5: endpoint { @@ -1689,8 +1671,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; - out-ports { port { tpdm_modem_0_out_tpda_modem: endpoint { @@ -1712,7 +1692,6 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; - qcom,msr-fix-req; out-ports { port { tpdm_modem_1_out_tpda_modem: endpoint { From 3aec5aedafef6ce29838c3fdab2e4361656d4d8f Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 10 Feb 2021 00:15:37 +0530 Subject: [PATCH 0869/1809] bindings: update documentation for support-legacy_smc This change adds documenation for a newly added property for smcinvoke driver, qcom,support-legacy_smc. Change-Id: I8df90389901c4826031a841dd7f3decb90032384 --- bindings/smcinvoke/smcinvoke.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/smcinvoke/smcinvoke.txt b/bindings/smcinvoke/smcinvoke.txt index f605d4bf3f6f..4fa8d5e26d7f 100644 --- a/bindings/smcinvoke/smcinvoke.txt +++ b/bindings/smcinvoke/smcinvoke.txt @@ -2,8 +2,16 @@ Required properties: - compatible : Should be "qcom,smcinvoke" +- qcom,support-legacy_smc : indicates that secure side uses QCOM_SCM_SMCINVOKE_INVOKE_LEGACY (value = 0x00) for smcinvoke + functionality. Example: qcom_smcinvoke: smcinvoke@87900000 { compatible = "qcom,smcinvoke"; }; + +Example: For targets where secure side runs with QCOM_SCM_SMCINVOKE_INVOKE_LEGACY cmd id + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + qcom,support-legacy_smc; + }; From 85d314b818bdad16e41c12f0a371f7fefe360575 Mon Sep 17 00:00:00 2001 From: rajikuma Date: Wed, 7 Oct 2020 18:13:39 +0530 Subject: [PATCH 0870/1809] ARM: dts: msm: include audio dt files for sa8195 Include audio dts file in main dtsi to enable audio feature, Add spi-msm-codec-slave device as a subnode of spi se2 node on sa8195 platform. Change-Id: Iec599131825c5dcbb521d5b580bf717845ea3848 --- qcom/sdmshrike.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7d54e7b22864..40a8c1efa44b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -37,6 +37,7 @@ ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se12_2uart; sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + spi22 = &qupv3_se22_spi; }; cpus { @@ -2021,6 +2022,7 @@ #include "sa8195-usb.dtsi" #include "sdmshrike-gpu.dtsi" #include "sa8195-vidc.dtsi" +#include "sa8155-audio.dtsi" &firmware { scm { From a9bfef550f1047261fe7934974d5b1dcc1c9062c Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 29 Jan 2021 19:04:44 +0800 Subject: [PATCH 0871/1809] ARM: dts: msm: add touch support for more panels on qrd yupik Add touch support for r66451 60/120hz cphy command mode panels on qrd yupik. Change-Id: I0bfaeebe14b50ef74e52cbe7b92398c3c6fe12eb --- qcom/yupik-qrd.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index c3d55c5624f6..3f815594737e 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -561,7 +561,8 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; - panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy>; + panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_120hz_cmd_cphy + &dsi_r66451_amoled_90hz_cmd_cphy &dsi_r66451_amoled_60hz_cmd_cphy>; }; }; From 987d4ae0ccbf14e062dc186c00d955a1605f5b6d Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Wed, 10 Feb 2021 22:09:32 +0530 Subject: [PATCH 0872/1809] ARM: dts: msm: Add PMUV3 node for monaco Add pmu node for monaco. Change-Id: I5b4480e94527d5de314b82a6eff476961ce9586b --- qcom/monaco.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 60a8d4f7089d..ae59b314dcce 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -334,6 +334,12 @@ }; }; + cpu_pmu: cpu-pmu { + ompatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + qcom,msm-imem@c125000 { compatible = "qcom,msm-imem"; reg = <0xc125000 0x1000>; From 574775a92191f16c001c426e1f35288b69c5e960 Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Tue, 2 Feb 2021 09:32:58 +0530 Subject: [PATCH 0873/1809] ARM: dts: msm: Correct syntax error Fix syntax error. Change-Id: I3fd33366ab91172dd6b4900657cc137f6f795340 --- qcom/monaco-qupv3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 2c249245c30b..432c2acc8b84 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -25,7 +25,7 @@ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; - status = "ok" + status = "ok"; }; /* GPI Instance */ From 6dbc19b50b1ae53a89a03f6bc78cf06883f40789 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 7 Jan 2021 15:50:53 +0530 Subject: [PATCH 0874/1809] ARM: dts: msm: Enhanced flow control support to sdxlemur target Changes to support Enhanced flow control for sdxlemur target. Change-Id: Ia5c776cdf684928ef03915539ebf91f4ee792bea --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 8c8f85c9c5d5..9e12a43e2839 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1149,6 +1149,7 @@ qcom,ipa-wdi3-over-gsi; qcom,ipa-wdi3-holb-2g = <8>; qcom,ipa-wdi3-holb-5g = <15>; + qcom,ipa-endp-delay-wa-v2; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; qcom,ipa-uc-holb-monitor; From ccc85c30bc5cc65846417677e6f8bd490fd97738 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 28 Sep 2020 18:32:47 +0530 Subject: [PATCH 0875/1809] ARM: dts: msm: Add slpi pinctrl to SM6150 Add slpi pinctrl support for SM6150. Change-Id: I20c4f9f2648a0732c880c9e7edcd58afb6f995c5 --- qcom/sa6155.dtsi | 4 ++++ qcom/sa6155p.dtsi | 4 ++++ qcom/sm6150-slpi-pinctrl.dtsi | 11 +++++++++++ qcom/sm6150.dtsi | 1 + 4 files changed, 20 insertions(+) create mode 100644 qcom/sm6150-slpi-pinctrl.dtsi diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 5dad61ae51e4..7b5707a384aa 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -35,3 +35,7 @@ &videocc { compatible = "qcom,sa6155-videocc", "syscon"; }; + +&slpi_tlmm { + status = "ok"; +}; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 59ff2bc74431..946016505e0f 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -53,3 +53,7 @@ &videocc { compatible = "qcom,sa6155-videocc", "syscon"; }; + +&slpi_tlmm { + status = "ok"; +}; diff --git a/qcom/sm6150-slpi-pinctrl.dtsi b/qcom/sm6150-slpi-pinctrl.dtsi new file mode 100644 index 000000000000..e6b1a10033c7 --- /dev/null +++ b/qcom/sm6150-slpi-pinctrl.dtsi @@ -0,0 +1,11 @@ + +&soc { + slpi_tlmm: slpi_pinctrl@62B40000 { + compatible = "qcom,slpi-pinctrl"; + reg = <0x62B40000 0x20000>; + qcom,num-pins = <32>; + clock-names = "ssc-clk"; + clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; + status = "disabled"; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index ecf2201756e0..8bea8fb0a976 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1776,3 +1776,4 @@ }; #include "msm-arm-smmu-sm6150.dtsi" +#include "sm6150-slpi-pinctrl.dtsi" From e43dd844267ecf2fb1316871cd6bb7a218b131ac Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Thu, 11 Feb 2021 21:02:58 +0530 Subject: [PATCH 0876/1809] ARM: dts: msm: Enable smcinvoke and shmbridge on yupik Add the device tree entries for smcinvoke and shmbridge on yupik vm. Change-Id: I0cc466278af5ba1f760a061b32ae5a11d819ab54 --- qcom/yupik-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index c915bd830468..c189e1513776 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -228,6 +228,15 @@ ; }; + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,support-hypervisor; + }; + /* Qup3_1 SE5: se_13 */ qupv3_1: qcom,qupv3_1_geni_se@ac0000 { compatible = "qcom,qupv3-geni-se"; From a5a09c205df0cf90ba1ed1eb7f8f562d4d01ac7d Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 4 Feb 2021 22:10:07 -0800 Subject: [PATCH 0877/1809] ARM: dts: msm: Add new soc-id for sdxlemur Newer sdxlemur variants use a different soc-id, so add it to the devicetree. Change-Id: I9294681a61382b3962a3762dbb8895849de7c9ed --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f9c86274d0e1..0fcc3a6e3a2f 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -20,7 +20,7 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR"; compatible = "qcom,sdxlemur"; - qcom,msm-id = <458 0x10000>, <483 0x10000>; + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; interrupt-parent = <&intc>; aliases { From b18168c8b9c1ab44b894a9344576aaed1a1aee82 Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Tue, 26 Jan 2021 16:19:06 -0800 Subject: [PATCH 0878/1809] ARM: dts: msm: Fix IPA doorbell address for sdxlemur Update event ring doorbell address forwarding for the IPA microcontroller on sdxlemur. Change-Id: If0902818d535cf2c0aea59bd9bb17c8b0623a56f --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index be018e3c9f7b..24bc6e21a721 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1094,7 +1094,7 @@ compatible = "qcom,msm-mhi-dev"; reg = <0x1c03000 0x1000>, <0x3E28000 0x4>, - <0x3E28148 0x4>; + <0x3E28800 0x4>; reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", "ipa_uc_mbox_erdb"; qcom,mhi-ep-msi = <0>; From 57dd5d2214b54d3f6cfb816dd0bae86ac6d5079a Mon Sep 17 00:00:00 2001 From: Chandrasekhar Mattaparthy Date: Fri, 12 Feb 2021 01:49:49 +0530 Subject: [PATCH 0879/1809] ARM: dts: msm: Early mount of vendor partition Add support to early mount vendor partition from device tree. This is required so that vendor modules can be loaded during early-init for Monaco Target. Change-Id: I8ebc1c992d42eb810a29c4f57e1a9c0dbea0a309 --- qcom/monaco.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 60a8d4f7089d..6cea151c3348 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -127,6 +127,29 @@ soc: soc { }; + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = + "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From 0c069c43d73566725aafb99d932b6094b9e7fc39 Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Wed, 7 Oct 2020 23:54:47 +0530 Subject: [PATCH 0880/1809] ARM: dts: msm: Add dtsi entry for spss_utils, spcom drivers Add spss_utils node, spcom node for sdmshrike. Change-Id: I5d08e47213d02c053f137daf23f204c21d7bd5b7 --- qcom/sdmshrike.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index d62457e11f08..df7639116377 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1960,6 +1960,31 @@ hyplog-size-offset = <0x414>; }; + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* Boolean property to differentiate supported features*/ + qcom,no-cmac-and-iar-feature-support; + /* spss fuses physical address */ + qcom,spss-fuse1-addr = <0x007841c4>; + qcom,spss-fuse1-bit = <27>; + qcom,spss-fuse2-addr = <0x007841c4>; + qcom,spss-fuse2-bit = <26>; + qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-emul-type-reg-addr = <0x01fc8004>; + status = "ok"; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; + status = "ok"; + }; + qcom,npu@9800000 { compatible = "qcom,pil-tz-generic"; reg = <0x9800000 0x800000>; From 446fe40fd61114a4d7ec14811bff4659d03982f6 Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Thu, 1 Oct 2020 20:41:13 +0530 Subject: [PATCH 0881/1809] ARM: dts: msm: Add dtsi entry for spss_utils, spcom drivers Add spss_utils node,spcom node for msmnile. Change-Id: I0207781cfd7cc111e095206a8910454d2c531cb0 --- qcom/sm8150-v2.dtsi | 6 ++++++ qcom/sm8150.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 5c7d57267369..6ab80cc54442 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -10,6 +10,12 @@ /delete-node/ &apps_smmu; /delete-node/ &kgsl_smmu; +&spss_utils { + qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ +}; + &gcc { compatible = "qcom,sm8150-gcc-v2", "syscon"; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6043fe81f15a..eaf1029ae137 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2575,6 +2575,34 @@ hyplog-size-offset = <0x414>; }; + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* Boolean property to differentiate supported features*/ + qcom,no-cmac-and-iar-feature-support; + qcom,no-cmac-support; + /* spss fuses physical address */ + qcom,spss-fuse1-addr = <0x007841c4>; + qcom,spss-fuse1-bit = <27>; + qcom,spss-fuse2-addr = <0x007841c4>; + qcom,spss-fuse2-bit = <26>; + qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-emul-type-reg-addr = <0x01fc8004>; + pil-mem = <&pil_spss_mem>; + qcom,pil-size = <0x0F0000>; // padding to 960 KB + status = "ok"; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; + status = "ok"; + }; + }; &firmware { From cbc1d67c69dd6302873a2037cacf79db58f03892 Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Thu, 29 Oct 2020 16:18:16 +0530 Subject: [PATCH 0882/1809] ARM: dts: msm: Add dtsi entry for ssg hlos drivers The following changes are added: 1. Add qseecom node for msmsteppe 2. Enable QRNG driver for msmsteppe. 3. Add shmbridge node for msmsteppe. 4. Add smcinvoke node for msmsteppe. 5. Add tz_log node for msmsteppe. Change-Id: I668eb58ec9084365c1baf3ca0060c6cf309c87a0 --- qcom/sm6150.dtsi | 53 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 8bea8fb0a976..8eb508033abf 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -459,8 +459,10 @@ qseecom_mem: qseecom_region@0x9e400000 { compatible = "shared-dma-pool"; - no-map; - reg = <0x0 0x9e400000 0x0 0x1400000>; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { @@ -1671,6 +1673,53 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@86d00000 { + compatible = "qcom,smcinvoke"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>; + clock-names = "km_clk_src"; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + }; + + qcom_tzlog: tz-log@146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + }; #include "sm6150-qupv3.dtsi" From 5c99b0de877857af96ecb32f539f9ce416dfe813 Mon Sep 17 00:00:00 2001 From: Bavyasritha Alahari Date: Fri, 12 Feb 2021 13:15:51 +0530 Subject: [PATCH 0883/1809] ARM: dts: msm: Add cdsp rpmsg entry in yupik CDSPRM module relies on the rpmsg node to create a communication channel with CDSP. CDSPRM module implements a RPMSG interface to communicate with CDSP while provoding a way for CPU QoS to benefit CDSP applications performance. Change-Id: I253471848431dbc7ddf36de8ae32e32dbe8a7837 --- qcom/yupik.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a9e0071e64ba..b2f3ae3c9c4f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2539,6 +2539,18 @@ qcom,notify-edges = <&glink_adsp>, <&glink_wpss>; }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; }; glink_wpss: wpss { From 0ad8ebb0fcd19f3c78a1e156472abf07cfcb960f Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Fri, 12 Feb 2021 10:18:00 +0530 Subject: [PATCH 0884/1809] ARM: dts: msm: Add audio nodes for sdxnightjar Add soundcard support. Change-Id: I8fba31fa2d269a2031d6efdeea6e5b788591e99b --- qcom/sdx-audio-lpass-elite.dtsi | 341 ++++++++++++++++++++++++++++ qcom/sdxnightjar-audio-overlay.dtsi | 110 +++++++++ qcom/sdxnightjar-audio.dtsi | 83 +++++++ qcom/sdxnightjar-ion.dtsi | 6 + qcom/sdxnightjar-pinctrl.dtsi | 77 +++++++ qcom/sdxnightjar.dtsi | 9 + 6 files changed, 626 insertions(+) create mode 100644 qcom/sdx-audio-lpass-elite.dtsi create mode 100644 qcom/sdxnightjar-audio-overlay.dtsi create mode 100644 qcom/sdxnightjar-audio.dtsi diff --git a/qcom/sdx-audio-lpass-elite.dtsi b/qcom/sdx-audio-lpass-elite.dtsi new file mode 100644 index 000000000000..32841765a1e4 --- /dev/null +++ b/qcom/sdx-audio-lpass-elite.dtsi @@ -0,0 +1,341 @@ +&soc { + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "regular"; + }; + + pcm2: qcom,msm-ultra-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <2>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + pcm_noirq: qcom,msm-pcm-dsp-noirq { + compatible = "qcom,msm-pcm-dsp-noirq"; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_modem"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 2.9"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + }; + + prim_master: prim_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_master + &pri_sck_active_master + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + prim_slave: prim_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_slave + &pri_sck_active_slave + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_master: sec_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_master + &sec_sck_active_master + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_slave: sec_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; +}; diff --git a/qcom/sdxnightjar-audio-overlay.dtsi b/qcom/sdxnightjar-audio-overlay.dtsi new file mode 100644 index 000000000000..ae09715f9846 --- /dev/null +++ b/qcom/sdxnightjar-audio-overlay.dtsi @@ -0,0 +1,110 @@ +#include + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm_pinmux>; + qcom,gpio-connect = <&tlmm_pinmux 94 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio_up: audio_ext_clk_up { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <12288000>; + qcom,use-pinctrl = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&i2s_mclk_sleep>; + pinctrl-1 = <&i2s_mclk_active>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@90 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm_pinmux 90 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + spkr_1_wcd_en: spkr_1_wcd_en@81 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + +}; + +&i2c_3 { + status = "ok"; + tasha_codec: wcd9xxx_codec@d { + compatible = "qcom,tasha-i2c-pgd"; + reg = <0x0d>; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_up 0>; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + + cdc-vdd-buck-supply = <&codec_buck_vreg>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&codec_buck_vreg>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <200000>; + + cdc-vdd-tx-h-supply = <&pmd9650_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmd9650_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmd9650_l6>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-dmic-sample-rate = <4800000>; + + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr-num-dev = <1>; + + wsa881x_211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&spkr_1_wcd_en>; + qcom,wsa-prefix = "SpkrLeft"; + }; + }; + }; +}; diff --git a/qcom/sdxnightjar-audio.dtsi b/qcom/sdxnightjar-audio.dtsi new file mode 100644 index 000000000000..baab8538de66 --- /dev/null +++ b/qcom/sdxnightjar-audio.dtsi @@ -0,0 +1,83 @@ +#include "sdx-audio-lpass-elite.dtsi" + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&soc { + snd_9335: sound-tasha { + compatible = "qcom,mdm-audio-tasha"; + qcom,model = "sdx-tasha-i2s-snd-card"; + qcom,pri-mi2s-gpio = <&prim_master>; + qcom,sec-mi2s-gpio = <&sec_master>; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "Headset Mic", + "Headset Mic", "MIC BIAS2", + "AMIC3", "ANCRight Headset Mic", + "ANCRight Headset Mic", "MIC BIAS2", + "AMIC4", "ANCLeft Headset Mic", + "ANCLeft Headset Mic", "MIC BIAS2", + "AMIC5", "Handset Mic", + "Handset Mic", "MIC BIAS3", + "DMIC1", "Digital Mic1", + "DMIC1", "MIC BIAS1", + "DMIC2", "Digital Mic2", + "DMIC2", "MIC BIAS3", + "DMIC3", "Digital Mic3", + "DMIC3", "MIC BIAS3", + "DMIC4", "Digital Mic4", + "DMIC4", "MIC BIAS4", + "DMIC5", "Digital Mic5", + "DMIC5", "MIC BIAS4", + "SpkrLeft IN", "SPK1 OUT"; + + qcom,tasha-mclk-clk-freq = <12288000>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_sec_auxpcm>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-auxpcm.2"; + asoc-codec = <&stub_codec>, <&wsa881x_211>; + asoc-codec-names = "msm-stub-codec.1", "wsa-codec.1"; + qcom,wsa-max-devs = <1>; + qcom,swr-num-dev = <1>; + qcom,wsa-aux-dev-prefix = "SpkrLeft"; + qcom,wsa-devs = <&wsa881x_211>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&tasha_codec>; + }; +}; diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 5eb8ae2d48f1..177423c67e8a 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -10,6 +10,12 @@ reg = ; qcom,ion-heap-type = "MSM_SYSTEM"; }; + + audio_heap: qcom,ion-heap@8 { /* AUDIO HEAP */ + reg = ; + memory-region = <&audio_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index f5a916ea293e..add8b1544bc6 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -830,6 +830,52 @@ }; }; + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + spkr_1_wcd { + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + }; + i2s_mclk { i2s_mclk_sleep: i2s_mclk_sleep { mux { @@ -1299,6 +1345,37 @@ }; }; + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 07378eed1518..996289ba1276 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -59,6 +59,13 @@ reusable; size = <0x400000>; }; + + audio_mem: audio_region@0 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + size = <0x400000>; + }; }; aliases { }; @@ -1022,6 +1029,8 @@ #include "sdxnightjar-blsp.dtsi" #include "sdxnightjar-cnss.dtsi" #include "sdxnightjar-pcie.dtsi" +#include "sdxnightjar-audio.dtsi" +#include "sdxnightjar-audio-overlay.dtsi" &i2c_3 { status = "ok"; From 812403804e509b8999b96e3fbeee4e7bc322d48f Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 12 Feb 2021 09:22:08 -0800 Subject: [PATCH 0885/1809] ARM: dts: msm: expand iommu-map to support PCIe switch on sdxlemur Additional BDF to SID mappings are needed if a switch and mutliple endpoints are connected to PCIe root complex. Expand iommu-map for PCIe on sdxprarie to support such a usecase. Change-Id: I396c535af617c413962049c26209d6ecf30628c5 --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 6511383a1fc6..0a782562d79a 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -4,6 +4,18 @@ }; +&pcie0 { + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x208 &apps_smmu 0x0202 0x1>, + <0x210 &apps_smmu 0x0203 0x1>, + <0x218 &apps_smmu 0x0204 0x1>, + <0x300 &apps_smmu 0x0207 0x1>, + <0x400 &apps_smmu 0x0208 0x1>, + <0x500 &apps_smmu 0x020C 0x1>, + <0x501 &apps_smmu 0x020E 0x1>; +}; + &pcie0_rp { #address-cells = <5>; #size-cells = <0>; From a6dabf5ffbca6979931bf14e1169fe20a7dabed5 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Sat, 13 Feb 2021 07:42:48 +0530 Subject: [PATCH 0886/1809] ARM: dts: msm: Enable multiple WLAN drivers support for Lahaina Enable qcom,converged-dt for WLAN in Lahaina to indicate multiple WLAN drivers support is needed. Change-Id: I11252772589d5d35e3de176d16c64f77fc0a548f --- bindings/cnss/cnss-wlan.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 73828aaebeb9..f05e653181c4 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -93,6 +93,8 @@ Optional properties: enable to resolve PMU power up issues. Provide BT GPIO using this config param. - qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention. + - qcom,converged-dt: Boolean property to decide whether it supports multiple + WLAN devices. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index d261cf1f5436..6dcd70411e17 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5393,6 +5393,7 @@ qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>; use-pm-domain; cnss-enable-self-recovery; + qcom,converged-dt; vdd-wlan-aon-supply = <&S2E>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 212ccf64f2bbcf71b7a30821652fc920c8ff9b5a Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Sat, 13 Feb 2021 21:22:07 +0530 Subject: [PATCH 0887/1809] ARM: dts: msm: Add Buses,PCIe,USB and storage devices to SM6150 Add the device tree nodes that describe the PCIe, USB, Buses and storage devices for SM6150 target. Change-Id: Ic77eaa26e00cf577e297064cdca122394e3e0a2f --- qcom/sa6155-adp-air.dtsi | 36 ++++ qcom/sa6155-adp-common.dtsi | 2 +- qcom/sa6155-adp-star.dtsi | 50 +++++ qcom/sa6155-pcie.dtsi | 248 +++++++++++++++++++++ qcom/sa6155.dtsi | 22 ++ qcom/sa6155p.dtsi | 22 ++ qcom/sm6150-pinctrl.dtsi | 232 +++++++++----------- qcom/sm6150-qupv3.dtsi | 293 +++++++++++++++++++++++-- qcom/sm6150-slpi-pinctrl.dtsi | 232 ++++++++++++++++++++ qcom/sm6150-ssc-qupv3.dtsi | 164 ++++++++++++++ qcom/sm6150-usb.dtsi | 390 ++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 127 +++++++++++ 12 files changed, 1669 insertions(+), 149 deletions(-) create mode 100644 qcom/sa6155-pcie.dtsi create mode 100644 qcom/sm6150-ssc-qupv3.dtsi create mode 100644 qcom/sm6150-usb.dtsi diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi index 36c1103f0315..592769aa9478 100644 --- a/qcom/sa6155-adp-air.dtsi +++ b/qcom/sa6155-adp-air.dtsi @@ -27,3 +27,39 @@ status = "ok"; }; + +&sdhc_1 { + vdd-supply = <&pm6155_1_l17>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6155_1_s4>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + status= "ok"; +}; diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index 3cd8585afb01..3d5709476521 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -1,6 +1,6 @@ #include -&qupv3_0 { +&qupv3_se0_2uart { status = "ok"; }; diff --git a/qcom/sa6155-adp-star.dtsi b/qcom/sa6155-adp-star.dtsi index 36c1103f0315..1a1502e99672 100644 --- a/qcom/sa6155-adp-star.dtsi +++ b/qcom/sa6155-adp-star.dtsi @@ -27,3 +27,53 @@ status = "ok"; }; + +&sdhc_1 { + vdd-supply = <&pm6155_1_l17>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6155_1_s4>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&qusb_phy0 { + qcom,usb-hs-ac-bitmask = <0x30>; + qcom,usb-hs-ac-value = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_hs_ac_en_default>; +}; + +&qusb_phy1 { + qcom,usb-hs-ac-bitmask = <0xc0>; + qcom,usb-hs-ac-value = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_hs_ac_en_default>; +}; diff --git a/qcom/sa6155-pcie.dtsi b/qcom/sa6155-pcie.dtsi new file mode 100644 index 000000000000..26472a00ad05 --- /dev/null +++ b/qcom/sa6155-pcie.dtsi @@ -0,0 +1,248 @@ +#include + +&soc { + pcie0: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 101 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&L12A>; + vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0p9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + + dma-coherent; + qcom,bw-scale = ; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE &mc_virt SLAVE_EBI1>; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,max-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,core-preset = <0x77777777>; + + qcom,boot-option = <0x0>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:010a"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 7b5707a384aa..db6647568d6d 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -6,6 +6,27 @@ compatible = "qcom,sa6155"; qcom,msm-name = "SA6155"; qcom,msm-id = <384 0x10000>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; +}; + +&qusb_phy0 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&usb_qmp_phy { + vdd-supply = <&L5A>; + core-supply = <&L12A>; +}; + +&qusb_phy1 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; }; &gcc { @@ -36,6 +57,7 @@ compatible = "qcom,sa6155-videocc", "syscon"; }; +#include "sa6155-pcie.dtsi" &slpi_tlmm { status = "ok"; }; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 946016505e0f..803602fadcda 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -5,6 +5,10 @@ model = "Qualcomm Technologies, Inc. SA6155P"; qcom,msm-name = "SA6155P"; qcom,msm-id = <377 0>, <380 0>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; }; /* Delete second instance of pm6155 definitions for APQ version */ @@ -26,6 +30,23 @@ /delete-node/ bt_wcn3990; }; +&qusb_phy0 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&usb_qmp_phy { + vdd-supply = <&L5A>; + core-supply = <&L12A>; +}; + +&qusb_phy1 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + &gcc { compatible = "qcom,sa6155-gcc", "syscon"; /delete-property/ protected-clocks; @@ -54,6 +75,7 @@ compatible = "qcom,sa6155-videocc", "syscon"; }; +#include "sa6155-pcie.dtsi" &slpi_tlmm { status = "ok"; }; diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi index bfebee7214a0..894a4a0ac947 100644 --- a/qcom/sm6150-pinctrl.dtsi +++ b/qcom/sm6150-pinctrl.dtsi @@ -842,143 +842,105 @@ }; }; - - - /* SDC pin type */ - sdc1_clk_on: sdc1_clk_on { - config { + sdc1_on: sdc1_on { + clk { pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc1_clk_off: sdc1_clk_off { - config { - pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_cmd_on: sdc1_cmd_on { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc1_cmd_off: sdc1_cmd_off { - config { - pins = "sdc1_cmd"; - num-grp-pins = <1>; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_data_on: sdc1_data_on { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc1_data_off: sdc1_data_off { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_rclk_on: sdc1_rclk_on { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc1_rclk_off: sdc1_rclk_off { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cd_on: cd_on { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - sdc2_cd_off: cd_off { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <2>; bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + + sd-cd { + pins = "gpio99"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + sd-cd { + pins = "gpio99"; + bias-disable; /* pull up */ + drive-strength = <2>; /* 2 MA */ }; }; diff --git a/qcom/sm6150-qupv3.dtsi b/qcom/sm6150-qupv3.dtsi index fba310e3e2eb..60bdbae480bd 100644 --- a/qcom/sm6150-qupv3.dtsi +++ b/qcom/sm6150-qupv3.dtsi @@ -1,18 +1,285 @@ +#include &soc { - qupv3_0: qcom,qupv3_0_geni_se@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x008c0000 0x6000>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; + /* + * QUPv3 North & South Instances + * North 0 : SE 4 + * North 1 : SE 5 + * North 2 : SE 6 + * North 3 : SE 7 + * South 0 : SE 0 + * South 1 : SE 1 + * South 2 : SE 2 + * South 3 : SE 3 + */ - qupv3_se0_2uart: qcom,qup_uart@0x880000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00880000 0x0 0x4000>; - interrupts = ; - status = "ok"; - }; + /* QUPv3 South Instances */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0xc3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se0_2uart: qcom,qup_uart@0x880000 { + compatible = "qcom,msm-geni-console"; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_2uart_active>; + pinctrl-1 = <&qupv3_se0_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3 North instances */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x363 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + + /* I2C */ + qupv3_se4_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se4_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* + * HS UART instances. HS UART usecases can be supported on these + * instances only. + */ + qupv3_se7_4uart: qcom,qup_uart@0xa8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + interrupts-extended = <&intc GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 13 0>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; }; }; diff --git a/qcom/sm6150-slpi-pinctrl.dtsi b/qcom/sm6150-slpi-pinctrl.dtsi index e6b1a10033c7..58f609ab0c47 100644 --- a/qcom/sm6150-slpi-pinctrl.dtsi +++ b/qcom/sm6150-slpi-pinctrl.dtsi @@ -7,5 +7,237 @@ clock-names = "ssc-clk"; clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; status = "disabled"; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio2", "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "func3"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "func2"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "func2"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/sm6150-ssc-qupv3.dtsi b/qcom/sm6150-ssc-qupv3.dtsi new file mode 100644 index 000000000000..1395eb412ea6 --- /dev/null +++ b/qcom/sm6150-ssc-qupv3.dtsi @@ -0,0 +1,164 @@ +#include + +&soc { + + /* QUPv3 SSC Instances */ + qupv3_2: qcom,qupv3_2_geni_se@626c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x626c0000 0x6000>; + + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-bus-ids = + ; + iommus = <&apps_smmu 0x1783 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@62680000 { + compatible = "qcom,i2c-geni"; + reg = <0x62680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE0_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@62684000 { + compatible = "qcom,i2c-geni"; + reg = <0x62684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@62688000 { + compatible = "qcom,i2c-geni"; + reg = <0x62688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@6268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x6268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE3_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@62690000 { + compatible = "qcom,i2c-geni"; + reg = <0x62690000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE4_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@62694000 { + compatible = "qcom,i2c-geni"; + reg = <0x62694000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE5_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se9_spi: spi@62684000 { + compatible = "qcom,spi-geni"; + reg = <0x62684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE1_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + qcom,disable-dma; + status = "disabled"; + }; + + qupv3_se10_spi: spi@62688000 { + compatible = "qcom,spi-geni"; + reg = <0x62688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_SE2_CLK>, + <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + qcom,disable-dma; + status = "disabled"; + }; +}; + diff --git a/qcom/sm6150-usb.dtsi b/qcom/sm6150-usb.dtsi new file mode 100644 index 000000000000..f275a536c535 --- /dev/null +++ b/qcom/sm6150-usb.dtsi @@ -0,0 +1,390 @@ +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + qcom,ignore-wakeup-src-in-hostmode; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_qmp_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e2000 0x180>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x88e6000 0x1000>, + <0x01fcb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm6150_l4>; + core-supply = <&pm6150_l11>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x70 0x0f 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x194 0x06 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x564 0x00 0x00 + 0x964 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: hsusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb20_sec_gdsc>; + clocks = <&gcc GCC_USB20_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB20_SEC_SLEEP_CLK>, + <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB2>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = ; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + qusb_phy1: qusb@88e3000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e3000 0x180>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 8eb508033abf..f4c7ab4a979f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -28,6 +28,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; + sdhc1 = &sdhc_1; + sdhc2 = &sdhc_2; }; cpus { @@ -1720,9 +1722,133 @@ hyplog-size-offset = <0x414>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "ice_core"; + + qcom,ice-clk-rates = <300000000 75000000>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + bus-width = <8>; + qcom,restore-after-cx-collapse; + supports-cqe; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + + interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 50 MB/s */ + <130718 200000>,<133320 133320>, + /* 100 MB/s */ + <130718 200000>,<150000 150000>, + /* 200 MB/s */ + <261438 400000>,<300000 300000>, + /* 400 MB/s */ + <261438 2718822>,<300000 1359411>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 50000000 100750000 + 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <67>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>,<100000 100000>, + /* 50 MB/s */ + <130718 200000>,<133320 133320>, + /* 100 MB/s */ + <261438 200000>,<150000 150000>, + /* 200 MB/s */ + <261438 400000>,<300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 25000000 50000000 + 100750000 200000000 4294967295>; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <67>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; }; #include "sm6150-qupv3.dtsi" +#include "sm6150-ssc-qupv3.dtsi" #include "sm6150-pinctrl.dtsi" #include "sm6150-pm.dtsi" #include "sm6150-regulator.dtsi" @@ -1826,3 +1952,4 @@ #include "msm-arm-smmu-sm6150.dtsi" #include "sm6150-slpi-pinctrl.dtsi" +#include "sm6150-usb.dtsi" From 5640f80451050e70b44c0f159df3cc740ecc587f Mon Sep 17 00:00:00 2001 From: Amir Levy Date: Sun, 14 Feb 2021 09:54:06 +0200 Subject: [PATCH 0888/1809] ARM: dts: msm: Add ipa_eth_group1 Add new iommu-group to be shared between IPA and AQC or RTL. In first stage add Only AQC\RTL to this group. In the Next stage IPA shall be added to the group and CB will be shared between IPA and AQC\RTL. we assume that RTL and AQC are not attached together so only one of them is part of the group. Change-Id: Ic07529baf1c5ec4ecd0540336058209243887853 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 79f8c949ba0a..d3e924ece6de 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1124,6 +1124,11 @@ qcom,pil-force-shutdown; }; + ipa_eth_group1: ipa_eth_group1 { + qcom,iommu-dma-addr-pool = <0x80000000 0x0fe20000>; + qcom,iommu-dma = "atomic"; + }; + ipa_hw: qcom,ipa@03e00000 { compatible = "qcom,ipa"; mboxes = <&qmp_aop 0>; From 16333bdb7cadfc47b0fe3271e995e3a27f1d4fba Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 2 Feb 2021 22:14:30 +0530 Subject: [PATCH 0889/1809] dt-bindings: add documentation for leds-qcom-clk LED qcom clk driver provides support for the clients to configure duty cycle of the clock to get the required brightness. Add the bindings necessary to describe it. Change-Id: I24a67257c55dd8b0278261bf9cb04454eb80d1c1 --- bindings/leds/leds-qcom-clk.txt | 67 +++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 bindings/leds/leds-qcom-clk.txt diff --git a/bindings/leds/leds-qcom-clk.txt b/bindings/leds/leds-qcom-clk.txt new file mode 100644 index 000000000000..d3e4d95ef646 --- /dev/null +++ b/bindings/leds/leds-qcom-clk.txt @@ -0,0 +1,67 @@ +Qualcomm Technologies, Inc. clock controller based PWM driver +------------------------------------------------------------- + +Qualcomm Technologies, Inc. provides clock controller to be connected to LED +to generate PWM. This driver can configure duty-cycle of clock to get the +required brightness. The complete clock duty-cycle is 100 and brightness is +denoted by the period in which signal is active or high. + +Required properties: +- compatible: Should be "qcom,clk-led-pwm". +- clock_names: Should be "core". +- clocks: Should contain the phandle of the source clock. +- assgined-clocks: Phandle of the source clock. +- assinged-clock-rates: Desired frequency of the source clock. +- qcom,max_duty: Maximum duty cycle that can be set on the clock. + Should be less than 100. +- pinctrl-names: Property should contain "active" and "sleep" for the + pin configurations during the usecase and during idle. +- pinctrl-x: phandle to the default/sleep pin configurations. + +Optional properties: +- qcom,label: Label for the sysfs node. + + +Example: + +qcom_clk_led { + compatible = "qcom,clk-led-pwm"; + qcom,label = "led_clk_pwm"; + qcom,max_duty = <80>; + clocks = <&clock_gcc GCC_GP2_CLK>; + clock-names = "core"; + assigned-clocks = <&clock_gcc GCC_GP2_CLK>; + assigned-clock-rates = <80000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&qcom_clk_led_gp2_active>; + pinctrl-1 = <&qcom_clk_led_gp2_sleep>; +}; + +== Pinctrl configurations == +qcom_clk_led_gp2_pins: qcom_clk_led_gp2_pins { + qcom_clk_led_gp2_active: qcom_clk_led_gp2_active { + mux { + pins = "gpio21"; + function = "gcc_gp2"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qcom_clk_led_gp2_sleep: qqcom_clk_led_gp2_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; From abdc40c6169607da829389deb445366e3599d5bf Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 3 Feb 2021 06:50:18 +0530 Subject: [PATCH 0890/1809] ARM: dts: msm: Add device tree node for GP2 clock driven led Add device tree configurations for GP2 clock driven led. Change-Id: I9cd2584aa25f3c2011dcc0d0f6648bd84996d811 --- qcom/sm8150-pinctrl.dtsi | 29 +++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 14 ++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index e5391f4ffef5..56c504fcab24 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -5098,5 +5098,34 @@ output-high; }; }; + + qcom_clk_led_gp2_pins: qcom_clk_led_gp2_pins { + qcom_clk_led_gp2_active: qcom_clk_led_gp2_active { + mux { + pins = "gpio21"; + function = "gcc_gp2"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qcom_clk_led_gp2_sleep: qqcom_clk_led_gp2_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + }; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index eaf1029ae137..2b998b1e9732 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1073,6 +1073,20 @@ #freq-domain-cells = <2>; }; + qcom_clk_led: qcom_clk_led { + compatible = "qcom,clk-led-pwm"; + qcom,label = "led_clk_gp2"; + clocks = <&gcc GCC_GP2_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc GCC_GP2_CLK>; + assigned-clock-rates = <80000>; + qcom,max_duty = <53>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&qcom_clk_led_gp2_active>; + pinctrl-1 = <&qcom_clk_led_gp2_sleep>; + status = "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, From b40a4004d5f106886f79e55ae8131dcf0c60ddf0 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Thu, 11 Feb 2021 22:01:58 +0530 Subject: [PATCH 0891/1809] ARM: dts: msm: Add AQC to ipa_eth_group1 Create a DTS node for aquantia and add it to ipa_eth_group1 to allow CB sharing between IPA and AQC. Change-Id: I7f7d857440d7e0ec1d183848454c227219d57704 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index b5afaa63db11..80468154252f 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -9,6 +9,42 @@ #address-cells = <5>; #size-cells = <0>; + aquantia,aqc@pcie0_rp { + reg = <0 0 0 0 0>; + + /* ipa shares this group with aqc */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + + pci-ids = + "1d6a:0001", + "1d6a:d107", + "1d6a:07b1", + "1d6a:87b1", + "1d6a:d108", + "1d6a:08b1", + "1d6a:88b1", + "1d6a:d109", + "1d6a:09b1", + "1d6a:89b1", + "1d6a:d100", + "1d6a:00b1", + "1d6a:80b1", + "1d6a:11b1", + "1d6a:91b1", + "1d6a:12b1", + "1d6a:92b1", + "1d6a:00c0", + "1d6a:04c0", + "1d6a:12c0", + "1d6a:14c0", + "1d6a:93c0", + "1d6a:94c0"; + + }; + pcie0_generic_ep: pcie0_generic_ep { reg = <0 0 0 0 0>; qcom,iommu-group = <&pcie0_generic_ep_iommu_group>; From c885e4c1a6c59787c2cd08375abdbd164d9fcbd2 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 12 Feb 2021 15:50:20 +0530 Subject: [PATCH 0892/1809] ARM: dts: msm: Update noc reg sizes for sdmshrike Update the register sizes based on sdmsrhiek v2. Change-Id: I749b28299539dc91f4d1dffe09b144d835f44778 --- qcom/sdmshrike.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index df7639116377..6e7b1c5ec1a5 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1087,7 +1087,7 @@ }; system_noc: interconnect@1620000 { - reg = <0x1620000 0x29400>; + reg = <0x1620000 0x21400>; compatible = "qcom,scshrike-system_noc"; #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; @@ -1147,7 +1147,7 @@ }; gem_noc: interconnect@9680000 { - reg = <0x9680000 0x3E200>; + reg = <0x9680000 0x58200>; compatible = "qcom,scshrike-gem_noc"; #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos", "disp"; From f5ded962dcf01a98110b78bd7e98683e4bf04a9e Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Mon, 15 Feb 2021 16:20:58 +0530 Subject: [PATCH 0893/1809] ARM: dts: msm: Enable qrng on sdxlemur This change adds device tree entries for qrng driver on sdxlemur. Change-Id: Id3a330ec076fc8ee6ba477bf68437465f2717053 --- qcom/sdxlemur.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 79f8c949ba0a..f96c5e339acb 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1299,6 +1299,15 @@ reg = <0x1468F720 0x2000>; }; + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PRNG>; + qcom,no-clock-support; + }; + thermal_zones: thermal-zones { }; From 53eb0440cb33c63a51208a2e77706a9d06dc34fd Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 9 Dec 2020 17:29:30 +0530 Subject: [PATCH 0894/1809] ARM: dts: msm: Enable qseecom on sdxlemur Add device tree entries to enable qseecom on sdxlemur target. Change-Id: Idba0e66e50d55fa75b9cd762a1b1efde75863436 --- qcom/sdxlemur-ion.dtsi | 17 +++++++++++++++++ qcom/sdxlemur.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index 3ad735dd3ecb..81fca5839dc6 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -14,6 +14,23 @@ qcom,ion-heap@8 { /* AUDIO HEAP */ reg = ; memory-region = <&audio_mem>; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; qcom,ion-heap-type = "DMA"; }; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 79f8c949ba0a..067723731d36 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -53,6 +53,31 @@ linux,cma-default; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1000000>; + }; + + audio_mem: audio_region@0 { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; @@ -1344,6 +1369,21 @@ <&apps_smmu 0x0074 0x0011>; }; + qcom_qseecom: qseecom@90000000 { + compatible = "qcom,qseecom"; + reg = <0x90000000 0x500000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + }; + qcom,rmtfs_sharedmem@0 { compatible = "qcom,sharedmem-uio"; reg = <0x0 0x400000>; From 49e3b3a8ba89654647b3415b4d88ca5cfb5416c1 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 15 Feb 2021 22:58:15 +0530 Subject: [PATCH 0895/1809] ARM: dts: qcom: Update UBWC version to 3 for yupik gpu Use UWBC 3 for yupik GPU as per new recommendation. Change-Id: I7f8c84c19f94853c733e708b07ad6c5078b3f3a2 --- qcom/yupik-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 1ace5580b638..c90c9c78c049 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -44,7 +44,7 @@ qcom,no-nap; qcom,min-access-length = <32>; - qcom,ubwc-mode = <4>; + qcom,ubwc-mode = <3>; qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; From 2b3b55923e4b581f68d113130b1dd34761b95291 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 12 Feb 2021 11:31:56 +0530 Subject: [PATCH 0896/1809] ARM: dts: msm: Update NSP and skin sensor thermal config for YUPIK Update thermal zone config for NSP and quiet-therm sensors based on latest recommendation. Change-Id: I157704547fb428f4097647dea14f791f71da7864 --- qcom/yupik-qrd.dtsi | 35 +++++++++++++++++++++++++++++++++++ qcom/yupik-thermal.dtsi | 10 ++++++---- 2 files changed, 41 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 7797428256d9..a1423ec2a430 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -264,6 +264,41 @@ }; }; }; + + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; + + trips { + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev { + trip = <&quiet_cx_trip>; + /* throttle to 315000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cdsp-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + modem-pa-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; }; &apps_rsc { diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 09800af991a3..44d153ae5721 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -1243,12 +1243,13 @@ cooling-maps { cdsp-cdev { trip = <&nspss0_trip>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; }; gpu_cdev { trip = <&nspss0_trip>; + /* throttle to 315000000Hz */ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; @@ -1276,12 +1277,13 @@ cooling-maps { cdsp-cdev { trip = <&nspss1_trip>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; }; gpu_cdev { trip = <&nspss1_trip>; + /* throttle to 315000000Hz */ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; From 72b904f26bf9efd0304f23fe62ecefaf74e1e033 Mon Sep 17 00:00:00 2001 From: Laisheng Hu Date: Fri, 23 Oct 2020 08:27:18 +0800 Subject: [PATCH 0897/1809] ARM: dts: msm: Add vidc node for SA6155 add 6150 vidc node for sa6155. Change-Id: Icfa71d10342f56ef18a4552b9f79881046feaf8b --- bindings/media/video/msm-vidc.txt | 1 + qcom/sm6150-vidc.dtsi | 103 ++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 1 + 3 files changed, 105 insertions(+) create mode 100644 qcom/sm6150-vidc.dtsi diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 9e73df7c1eea..abaa26e4c0ce 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -12,6 +12,7 @@ Required properties: - "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK. - "qcom,sm8150-vidc" : Invokes driver specific data for SM8150. - "qcom,scshrike-vidc" : Invokes driver specific data for SA8195. + - "qcom,sm6150-vidc" : Invokes driver specific data for SA6155. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL diff --git a/qcom/sm6150-vidc.dtsi b/qcom/sm6150-vidc.dtsi new file mode 100644 index 000000000000..11e17d878a89 --- /dev/null +++ b/qcom/sm6150-vidc.dtsi @@ -0,0 +1,103 @@ +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,sm6150-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&venus_gdsc>; + venus-core0-supply = <&vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk"; + + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; + + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "core0_clk", "core0_bus_clk"; + + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0>; + qcom,allowed-clock-rates = <133330000 240000000 300000000 + 380000000 410000000>; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr", "venus-arm9-ddr"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 2128000 + 1000 1000>; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0xE40 0x20>; + qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + dma-coherent-hint-cached; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0xE61 0x4>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0xE63 0x0>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0xE44 0x20>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index f4c7ab4a979f..8d36ceb2b321 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1953,3 +1953,4 @@ #include "msm-arm-smmu-sm6150.dtsi" #include "sm6150-slpi-pinctrl.dtsi" #include "sm6150-usb.dtsi" +#include "sm6150-vidc.dtsi" From 3f1002b1d7d7bd8c6d5c748c5a69f356af7c36bc Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 15 Feb 2021 15:04:36 +0530 Subject: [PATCH 0898/1809] ARM: dts: msm: Remove the handles for PCIE clocks for Yupik QoS for PCIE masters is programmed in boot loader, so remove the clock handles for PCIE. Change-Id: If5914856702f750074ba61e7b61fa282f7c213e8 --- qcom/yupik.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b2f3ae3c9c4f..d27bcfa0a3ce 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1502,9 +1502,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; From 3e959cd67c0487d5226ac223851fec694a86615b Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Wed, 10 Feb 2021 18:38:08 -0800 Subject: [PATCH 0899/1809] ARM: dts: msm: Add pcie node for Realtek r8125 driver Add pcie entry for Realtek r8125 driver on sdxlemur platform. Change-Id: Ic098c96d608eca17d21faf5961655126fd1349f1 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 80468154252f..26c2d426d7a4 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -45,6 +45,21 @@ }; + realtek,rtl8125@pcie0_rp { + reg = <0 0 0 0 0>; + + /* ipa shares this group with rtl */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + + pci-ids = + "10ec:8125", + "10ec:3000"; + + }; + pcie0_generic_ep: pcie0_generic_ep { reg = <0 0 0 0 0>; qcom,iommu-group = <&pcie0_generic_ep_iommu_group>; From b57fbad678ee3a1baf88103366ac3007f4c7c4f3 Mon Sep 17 00:00:00 2001 From: Amir Levy Date: Wed, 10 Feb 2021 13:50:38 +0200 Subject: [PATCH 0900/1809] ARM: dts: msm: enable IPA-AQC\RTL CB sharing Add IPA to ipa_eth_group1 thus enabling context bank sharing between IPA and AQC\RTL. Change-Id: I30d11875ef3f8a9fea651446c7d41893a1c1b89e --- qcom/sdxlemur.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d3e924ece6de..54ae1e78dc4e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1224,7 +1224,8 @@ ipa_smmu_eth: ipa_smmu_eth { compatible = "qcom,ipa-smmu-eth-cb"; iommus = <&apps_smmu 0x5E3 0x0>; - qcom,iommu-dma = "atomic"; + qcom,shared-cb; + qcom,iommu-group = <&ipa_eth_group1>; }; ipa_smmu_eth1: ipa_smmu_eth1 { From 3ffb95353d09b64cf62d9327089cf4daa0b618ea Mon Sep 17 00:00:00 2001 From: Fei Tong Date: Fri, 3 Jul 2020 09:50:52 +0800 Subject: [PATCH 0901/1809] ARM: dts: msm: include audio dt files for sax155 auto platforms include audio dt file in main dtsi to enable audio feature Change-Id: Ia617b2a7259b1e8b7b812ef40cd946b820de50b8 --- qcom/sa8155.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 5c439aeb1059..844e753c908b 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -127,3 +127,4 @@ #include "camera/sa8155-camera.dtsi" #include "camera/sa8155-camera-sensor.dtsi" +#include "sa8155-audio.dtsi" From af4d2b1fd686783eda2bc6ebad96d7404f500328 Mon Sep 17 00:00:00 2001 From: Tahir Dawson Date: Fri, 23 Oct 2020 16:57:40 -0400 Subject: [PATCH 0902/1809] ARM: dts: qcom: Add device nodes for second AFE rx and proxy tx devices * Add afe_proxy_tx_2 node for proxy capture frontend device. * Add afe_pcm_rx_2 node for afe playback backend device. * Add the new nodes to the ADP soundcard. Change-Id: Id2433d813958537b023c326b2658c906b361e0fc --- qcom/sa6155-audio.dtsi | 24 ++++++++++++++++++++---- qcom/sa8155-audio.dtsi | 24 ++++++++++++++++++++---- 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index 572081744fbf..3f57b9d95342 100644 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -458,6 +458,20 @@ pinctrl-1 = <&pri_aux_pcm_sck_sleep &pri_aux_pcm_ws_sleep &pri_aux_pcm_data0_sleep &pri_aux_pcm_data1_sleep>; }; + +qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + afe_pcm_rx_1: qcom,msm-dai-q6-be-afe-pcm-rx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <226>; + }; + + afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <242>; + }; + }; }; &audio_apr { @@ -496,10 +510,11 @@ <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&afe_pcm_rx_1>, <&afe_proxy_tx_1>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, <&usb_audio_rx>, <&usb_audio_tx>, <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, @@ -533,6 +548,7 @@ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.226", "msm-dai-q6-dev.242", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", diff --git a/qcom/sa8155-audio.dtsi b/qcom/sa8155-audio.dtsi index d3864c9a5e60..2a4d9777df24 100644 --- a/qcom/sa8155-audio.dtsi +++ b/qcom/sa8155-audio.dtsi @@ -461,6 +461,20 @@ pinctrl-1 = <&pri_aux_pcm_clk_sleep &pri_aux_pcm_sync_sleep &pri_aux_pcm_din_sleep &pri_aux_pcm_dout_sleep>; }; + +qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + afe_pcm_rx_1: qcom,msm-dai-q6-be-afe-pcm-rx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <226>; + }; + + afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <242>; + }; + }; }; &audio_apr { @@ -500,10 +514,11 @@ <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&afe_pcm_rx_1>, <&afe_proxy_tx_1>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, <&usb_audio_rx>, <&usb_audio_tx>, <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, @@ -537,6 +552,7 @@ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.226", "msm-dai-q6-dev.242", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", From 6cfdddf910b03c0400afbdc96c39f034d48c7f9a Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 24 Aug 2020 19:49:29 +0530 Subject: [PATCH 0903/1809] ARM: dts: msm: Add device node for watchdog in SM6150 Add device node for hardware msm-watchdog, this is needed to report system lockups related bugs in the kernel. Change-Id: I9afbed8e89fa9c70c87978c4201214c752fd8e7a --- qcom/sm6150.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index f4c7ab4a979f..c4deb69159cb 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1845,6 +1845,18 @@ vote = <67>; }; }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; }; #include "sm6150-qupv3.dtsi" From c4a8e02055fad108df708e65512d9b4de391627a Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 18 Dec 2020 09:02:00 +0530 Subject: [PATCH 0904/1809] ARM: dts: msm: Add DCVS device nodes to SM6150 Add bw_hwmon and memlat device tree nodes to enable DCVS support to SM6150. Change-Id: I0b8fcdfa878df1cd8f0492114b65c9378656026b --- qcom/sm6150.dtsi | 256 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 256 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index c4deb69159cb..653ea995e5e8 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -14,6 +14,12 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + / { model = "Qualcomm Technologies, Inc. SM6150"; compatible = "qcom,sm6150"; @@ -631,6 +637,256 @@ }; }; + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6300 0x300>, <0x90b6200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER0>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 576000 300000000 >, + < 1017600 556800000 >, + < 1209660 806400000 >, + < 1516800 940800000 >, + < 1804800 1363200000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS(150, 16) >, + < 1209600 MHZ_TO_MBPS(300, 16) >, + < 1516800 MHZ_TO_MBPS(466, 16) >, + < 1804800 MHZ_TO_MBPS(600, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS( 300, 4) >, + < 1017600 MHZ_TO_MBPS( 451, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 748800 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 451, 4) >, + < 1593600 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER1>; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6_cpu_l3_tbl { + qcom,core-dev-table = + < 1017600 556800000 >, + < 1209600 806400000 >, + < 1516800 940800000 >, + < 1708800 1209600000 >, + < 2208000 1363200000 >; + }; + + cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu6_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS(300, 16) >, + < 1017600 MHZ_TO_MBPS(466, 16) >, + < 1209600 MHZ_TO_MBPS(600, 16) >, + < 1708800 MHZ_TO_MBPS(806, 16) >, + < 2208000 MHZ_TO_MBPS(933, 16) >; + }; + + cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1209600 MHZ_TO_MBPS(1017, 4) >, + < 1708800 MHZ_TO_MBPS(1555, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1708800 MHZ_TO_MBPS(1017, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6150-pdc"; reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; From 1501c9af554743e3ea60b3dfc772fd872343bd19 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 21 Jan 2021 18:43:48 +0530 Subject: [PATCH 0905/1809] ARM: dts: msm: Add PMU device nodes to SM6150 Add LLCC PMU, CPU PMU and DSU PMU device nodes to SM6150. Change-Id: I8985e8c8bcdd76bf2babacbf60c47c7f46b7c3d1 --- qcom/sm6150.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 653ea995e5e8..211d20ade731 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -637,6 +637,12 @@ }; }; + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ @@ -928,6 +934,19 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; From cf5f6f8f0ecce4be4379370cb6ab1e802fdc6658 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 25 Sep 2020 10:47:37 +0530 Subject: [PATCH 0906/1809] ARM: dts: msm: Add device node for llcc node on SM6150 Add device node for last level cache controller on SM6150. Change-Id: Id8e6c6ded90e02e594f583aac179222fae359bf5 --- bindings/arm/msm/qcom,llcc.txt | 2 +- qcom/sm6150.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 6bddb3cbb70c..bf052f36b6de 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,7 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" - or "qcom,sdmshrike-llcc" + or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 211d20ade731..6460aff6ac7e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1001,6 +1001,13 @@ clock-frequency = <32768>; }; + cache-controller@9200000 { + compatible = "qcom,sm6150-llcc"; + reg = <0x9200000 0x50000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 06b9ee95f93f50553457c7b1828b532fb98f487f Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 17:20:47 +0530 Subject: [PATCH 0907/1809] ARM: dts: msm: Add core-hang detect nodes to SM6150 Add core-hang detect nodes for silver and gold core on SM6150. Change-Id: Id7177bedd71eba6c4287602b3ac668e1f48bd396 --- qcom/sm6150.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 6460aff6ac7e..b9b30eea4ef0 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2139,6 +2139,23 @@ qcom,ipi-ping; qcom,wakeup-enable; }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 + 0x18030058 0x18040058 0x18050058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 + 0x18030060 0x18040060 0x18050060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18060058 0x18070058>; + qcom,config-arr = <0x18060060 0x18070060>; + }; + }; #include "sm6150-qupv3.dtsi" From 10e0744a3268028574d47bbc8b895793478bbb66 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 00:20:47 +0530 Subject: [PATCH 0908/1809] ARM: dts: msm: Add mem-dump and CPU dump nodes to SM6150 Add mem-dump and CPU memory dump nodes to SM6150. Change-Id: If38e0285007e59b35ade8f74d3a983b08a802562 --- qcom/sm6150.dtsi | 340 +++++++++++++++++++++++++++++------------------ 1 file changed, 210 insertions(+), 130 deletions(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b9b30eea4ef0..85ec4979f0c5 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -65,20 +65,6 @@ cache-level = <3>; }; }; - - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_0: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU1: cpu@100 { @@ -98,20 +84,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_100: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; @@ -132,20 +104,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_200: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_200: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_200: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU3: cpu@300 { @@ -165,20 +123,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_300: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_300: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_300: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU4: cpu@400 { @@ -198,20 +142,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_400: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_400: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_400: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU5: cpu@500 { @@ -231,20 +161,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_500: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_500: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_500: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU6: cpu@600 { @@ -263,29 +179,6 @@ cache-size = <0x40000>; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x48000>; - }; - - L1_I_600: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_600: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_600: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_600: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_600: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -305,29 +198,6 @@ cache-size = <0x40000>; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x48000>; - }; - - L1_I_700: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_700: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_700: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_700: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_700: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -1008,6 +878,216 @@ cap-based-alloc-and-pwr-collapse; }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x47>; + }; + + l2_cache600 { + qcom,dump-size = <0x48000>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x48000>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + + llcc1_d_cache { + qcom,dump-size = <0x6c000>; + qcom,dump-id = <0x140>; + }; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 15048bee5ec0493631b5ecc02480e3a12edf000d Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 12 Oct 2020 17:26:06 +0530 Subject: [PATCH 0909/1809] ARM: dts: msm: Add secure_buffer and qcom,scm device on SM6150 Add device nodes for secure buffer and scm for SM6150 SoC. This is needed to secure memory buffers, and protect them against unauthorized access. Change-Id: I44b78b96382133485b0d3eb45e07264dd04555b4 --- qcom/sm6150.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 85ec4979f0c5..2b04e0d68c73 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -419,6 +419,11 @@ linux,cma-default; }; }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + }; &soc { @@ -865,6 +870,12 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre1_noc MASTER_CRYPTO + &mc_virt SLAVE_EBI1>; + }; + qcom,mpm2-sleep-counter@0xc221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; @@ -2245,6 +2256,12 @@ #include "sm6150-regulator.dtsi" #include "sm6150-gdsc.dtsi" +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + &emac_gdsc { status = "ok"; }; From 3fef3a83cec04ac735d86da98315d1812d7edab4 Mon Sep 17 00:00:00 2001 From: Akshay Adiga Date: Wed, 18 Nov 2020 16:24:38 +0530 Subject: [PATCH 0910/1809] ARM: dts: msm: Add dt node for msm-poweroff on SM6150 Add dt node for msm-poweroff on SM6150. Change-Id: Ib219816131d8a951bdf4e6a86d0d77c5c22c1f31 --- qcom/sm6150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 2b04e0d68c73..32b3967c4faf 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -865,6 +865,13 @@ }; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 0d07190ed7b562a18410e04440e18e967496ee31 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Tue, 16 Feb 2021 23:55:16 +0530 Subject: [PATCH 0911/1809] ARM: dts: msm: Add DMIC0 support Add DMIC0 support. Change-Id: I29af88540f33f7a872823d4a01612ca3608a5927 --- qcom/sdx-audio-lpass-elite.dtsi | 2 ++ qcom/sdxnightjar-audio.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/qcom/sdx-audio-lpass-elite.dtsi b/qcom/sdx-audio-lpass-elite.dtsi index 32841765a1e4..598e16ed0b5a 100644 --- a/qcom/sdx-audio-lpass-elite.dtsi +++ b/qcom/sdx-audio-lpass-elite.dtsi @@ -7,6 +7,8 @@ qcom,msm-audio-ion { compatible = "qcom,msm-audio-ion"; + qcom,scm-mp-enabled; + memory-region = <&audio_mem>; }; pcm0: qcom,msm-pcm { diff --git a/qcom/sdxnightjar-audio.dtsi b/qcom/sdxnightjar-audio.dtsi index baab8538de66..c0b4b7cb941f 100644 --- a/qcom/sdxnightjar-audio.dtsi +++ b/qcom/sdxnightjar-audio.dtsi @@ -26,6 +26,8 @@ "ANCLeft Headset Mic", "MIC BIAS2", "AMIC5", "Handset Mic", "Handset Mic", "MIC BIAS3", + "DMIC0", "Digital Mic0", + "DMIC0", "MIC BIAS1", "DMIC1", "Digital Mic1", "DMIC1", "MIC BIAS1", "DMIC2", "Digital Mic2", From 292cb52d7db79d7581dbce33559eec2bdf5ed13e Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 16 Feb 2021 10:36:52 -0800 Subject: [PATCH 0912/1809] ARM: dts: msm: Correct parent regulator for sdxlemur VDD_CX_LEVEL_AO The VDD_CX_LEVEL_AO regulator node currently propagates its vote to VDD_MxA during Linux suspend. Correct this to make the node propagate it to VDD_MXA_LEVEL_AO so that APPS can vote for "OFF" in the absence of any other consumers. Change-Id: I37a60204a691841182ed7b5517a583c9d02d96c9 --- qcom/sdxlemur-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-regulators.dtsi b/qcom/sdxlemur-regulators.dtsi index 2fc8aaf2362f..e4ce28c0af99 100644 --- a/qcom/sdxlemur-regulators.dtsi +++ b/qcom/sdxlemur-regulators.dtsi @@ -117,7 +117,7 @@ S5B_LEVEL_AO: pmx65_s5_level_ao: regulator-pmx65-s5-level_ao { regulator-name = "pmx65_s5_level_ao"; qcom,set = ; - vin-supply = <&VDD_MXA_LEVEL>; + vin-supply = <&VDD_MXA_LEVEL_AO>; regulator-min-microvolt = ; regulator-max-microvolt = From a19ecb47bd4b153a0420249d58ce371d547f024e Mon Sep 17 00:00:00 2001 From: katamoni sai abhilash Date: Wed, 9 Sep 2020 06:25:51 +0530 Subject: [PATCH 0913/1809] ARM: dts: msm: Add qseecom node for sa8155 gvm Enable qseecom mode for SA8155 GVM platform. Change-Id: I9daea7199b5cf43dd6299dde0fa4364fc86c0982 --- qcom/sa8155-vm.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 62c2facecd81..d863c4d7229a 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -257,6 +257,24 @@ qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>; }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + }; ®ulator { @@ -345,6 +363,12 @@ }; }; +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + #include "sm8150-pinctrl.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sa8155-vm-usb.dtsi" From 957f13d7f34c1c948aa4add00b34840039f1859a Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 17 Feb 2021 11:26:40 +0530 Subject: [PATCH 0914/1809] ARM: dts: msm: Add Pmesg Reserved Memory for Yupik Add Pmesg reserved memory to enable the function to collect user-space log in pstore. Change-Id: I08e394c3083768148874bf4f344581fa34119230 --- qcom/yupik.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b2f3ae3c9c4f..45dc2b795223 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -475,6 +475,13 @@ size = <0 0x8c00000>; }; + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xa9000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From 6a9028e696918f0a940f19ed49a5fee78e1cf2f3 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Wed, 27 Jan 2021 12:02:11 +0530 Subject: [PATCH 0915/1809] ARM: dts: msm: Add RDPM register map for yupik GPU Add RDPM register ranges for yupik GPU to update CX and GX frequency changes to RDPM hardware. RDPM stands for Rail Digital Power Meter available for CX and MX to assist shared rails limits management for peak current. Change-Id: Icbea0bb2a1ad2a9755bb82e7cc53d97e5318d262 --- qcom/yupik-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 1ace5580b638..1569408892c7 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -14,10 +14,10 @@ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>; + <0x06900000 0x80000>, <0x0636000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx"; + "isense_cntl", "qdss_gfx", "rdpm_mx"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; From 12e5fc2af52732724a65c9a079a20df4d73d7348 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 8 Feb 2021 17:45:58 -0800 Subject: [PATCH 0916/1809] ARM: dts: msm: add MHI register space info for PCIe on sdxlemur Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on sdxlemur. Change-Id: I12c247b6e12134426d68ab4c7a3733136c877619 --- qcom/sdxlemur-pcie.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 50ca15604811..b433831ef634 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -7,8 +7,10 @@ <0x40000000 0xf1d>, <0x40000f20 0xa8>, <0x40001000 0x1000>, - <0x40100000 0x100000>; - reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + <0x40100000 0x100000>, + <0x1c03000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", + "mhi"; cell-index = <0>; linux,pci-domain = <0>; From a1cd70e4c4d3626fa38109b447c418d9f8af76e1 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 17 Feb 2021 14:39:09 -0800 Subject: [PATCH 0917/1809] dt-bindings: arm: msm: remove deprecated io and bar entries for PCIe PCIe root complex driver does not support io and bar entries as part of the resources which it will remap and access. These two resources are mapped and accessed directly by the device host driver. Also remove optional entries tcsr and rumi in the example code. Change-Id: I424ec43373f4aaf949a002f0ea69ec2bbccafe18 --- bindings/pci/pci-msm.txt | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 27741ba20e1c..c66bedf20c43 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -24,8 +24,6 @@ Main node - "elbi" External local bus interface registers - "iatu" Internal translation unit registers - "config" PCIe device configuration space - - "io" PCIe device I/O registers - - "bars" PCIe device base address registers - "tcsr" (opt) PCIe clock scheme register - "rumi" (opt) PCIe RUMI register @@ -440,11 +438,8 @@ Example <0x60000000 0xf1d>, <0x60000f20 0xa8>, <0x60001000 0x1000>, - <0x60100000 0x100000>, - <0x60200000 0x100000>, - <0x60300000 0x3d00000>; - reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", - "io", "bars", "tcsr", "rumi"; + <0x60100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; cell-index = <0>; device_type = "pci"; From d252283f7a16915076a1136bb4f1d6ba32debc7c Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 17 Feb 2021 14:46:44 -0800 Subject: [PATCH 0918/1809] dt-bindings: arm: msm: add mhi registers entry for PCIe RC PCIe root complex driver may need access to MHI registers for certain use case. Therefore, add an optional entry in the list of PCIe resources to provide access to MHI register space. Change-Id: Ifa704e198bc0e7b8f3dca9d726cfaa819973162e --- bindings/pci/pci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index c66bedf20c43..22f05045e34c 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -24,6 +24,7 @@ Main node - "elbi" External local bus interface registers - "iatu" Internal translation unit registers - "config" PCIe device configuration space + - "mhi" (opt) PCIe MHI registers - "tcsr" (opt) PCIe clock scheme register - "rumi" (opt) PCIe RUMI register From 4a7069643af7476a712ad113e34a7a3e9c3ac7db Mon Sep 17 00:00:00 2001 From: Hui Li Date: Thu, 7 Jan 2021 14:35:58 +0800 Subject: [PATCH 0919/1809] ARM: dts: msm: Add support for kgsl driver on SA6155 Add support for GPU driver to perform graphics functionality on SA6155. Change-Id: I052d3434203f8d7f2da6d3ab19c890f26b405e42 --- qcom/sa6155.dtsi | 338 ++++++++++++++++++++++ qcom/sa6155p.dtsi | 338 ++++++++++++++++++++++ qcom/sm6150-gpu.dtsi | 654 +++++++++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 1 + 4 files changed, 1331 insertions(+) create mode 100644 qcom/sm6150-gpu.dtsi diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index db6647568d6d..c198dd260d2a 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -61,3 +61,341 @@ &slpi_tlmm { status = "ok"; }; + +/* GPU power level overrides */ +&msm_gpu { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + + /delete-node/qcom,gpu-pwrlevel-bins; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <2>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <0>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 803602fadcda..0a609bc0c3e3 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -79,3 +79,341 @@ &slpi_tlmm { status = "ok"; }; + +/* GPU power level overrides */ +&msm_gpu { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + + /delete-node/qcom,gpu-pwrlevel-bins; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <2>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <0>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; diff --git a/qcom/sm6150-gpu.dtsi b/qcom/sm6150-gpu.dtsi new file mode 100644 index 000000000000..b878a008e0d8 --- /dev/null +++ b/qcom/sm6150-gpu.dtsi @@ -0,0 +1,654 @@ + +#define KHZ_TO_KBPS(khz, w) ((khz * 1000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a612_zap"; + memory-region = <&pil_gpu_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x90000>, + <0x780000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", + "qfprom_memory"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x06010200>; + + qcom,initial-pwrlevel = <5>; + + /* */ + qcom,idle-timeout = <80>; + qcom,no-nap; + + qcom,highest-bank-bit = <14>; + qcom,ubwc-mode = <2>; + qcom,min-access-length = <32>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "gcc_gpu_axi_clk", + "iface_clk", "gcc_gpu_memnoc_gfx", + "gpu_cc_hlos1_vote_gpu_smmu", "gmu_clk"; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 (Low SVS) */ + , /* index=2 (Low SVS) */ + , /* index=3 (Low SVS) */ + , /* index=4 (Low SVS) */ + , /* index=5 (Low SVS) */ + , /* index=6 (SVS) */ + , /* index=7 (SVS) */ + , /* index=8 (SVS L1) */ + , /* index=9 (NOM) */ + , /* index=10 (NOM) */ + ; /* index=11 (TURBO) */ + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <67>; + qcom,pm-qos-wakeup-latency = <67>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <3>; + + qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <187>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <4>; + + /* TURBO L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <895000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <845000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,level = ; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <2>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-6 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,level = ; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <290000000>; + qcom,level = ; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,level = ; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x050a0000 0x10000>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0x401>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0x400>; + qcom,iommu-dma = "disabled"; + }; + }; + + rgmu: qcom,rgmu@0x0506d000 { + label = "kgsl-rgmu"; + compatible = "qcom,gpu-rgmu"; + + reg = <0x506d000 0x31000>; + reg-names = "kgsl_rgmu"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_oob", "kgsl_rgmu"; + + regulator-names = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_GX_GFX3D_CLK>; + + clock-names = "gmu", "rbbmtimer", "mem", + "iface", "mem_iface", + "smmu_vote", "core"; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 81a6fc094f2f..cabf0c3bb6e7 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2367,5 +2367,6 @@ #include "msm-arm-smmu-sm6150.dtsi" #include "sm6150-slpi-pinctrl.dtsi" +#include "sm6150-gpu.dtsi" #include "sm6150-usb.dtsi" #include "sm6150-vidc.dtsi" From 2f2c5ca0aab285a60d7b4c80856caec19b969906 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Wed, 17 Feb 2021 11:28:13 +0530 Subject: [PATCH 0920/1809] ARM: dts: msm: Add IOSS v2 driver bindings Add devicetree bindings to support IOSS v2 driver. Change-Id: I31907aededf7e742953b3447f37179b6d7ac9395 --- bindings/platform/msm/ioss.txt | 18 ++++++++++++++++++ bindings/platform/msm/ioss_device.txt | 25 +++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 bindings/platform/msm/ioss.txt create mode 100644 bindings/platform/msm/ioss_device.txt diff --git a/bindings/platform/msm/ioss.txt b/bindings/platform/msm/ioss.txt new file mode 100644 index 000000000000..c7221ea845fb --- /dev/null +++ b/bindings/platform/msm/ioss.txt @@ -0,0 +1,18 @@ +Qualcomm Technologies Inc. IPA Offload Sub-System + +IPA Offload Sub-system is a generic kernel framework that enables a +third-party ethernet driver to attach an ethernet peripheral to IPA +for hardware offloading of tethered data paths. The framework +provides a generic API interface that ethernet drivers can use to +register their hardware functionality with the sub-system in order +to enable IPA offload. + +Required properties: + +- compatible : should be "qcom,ioss-v2" + +Example: + + ioss: qcom,ioss { + compatible = "qcom,ioss-v2"; + }; diff --git a/bindings/platform/msm/ioss_device.txt b/bindings/platform/msm/ioss_device.txt new file mode 100644 index 000000000000..85b9366f04a3 --- /dev/null +++ b/bindings/platform/msm/ioss_device.txt @@ -0,0 +1,25 @@ +Qualcomm Technologies Inc. IPA Offload Sub-System Device + +IPA Offload Sub-system is a generic kernel framework that enables a +third-party ethernet driver to attach an ethernet peripheral to IPA +for hardware offloading of tethered data paths. + +For each device attached to IOSS, we can define IPA offload data path +configuration through below devicetree properties. + +Required properties: + +- compatible : should be "qcom,ioss-v2-device" +- qcom,ioss : specify which IOSS platform device to be used +- qcom,ioss_interfaces : to specify interface names and its channel config + +Example: + +&pcie_rc1 { + aqc_x2: qcom,aqc@1 { + compatible = "qcom,ioss-v2-device"; + + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = + <&ioss_aqc_eth0>; +}; From f1d5024dee4f35233f7b253d648c730cc3addbf2 Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 17 Feb 2021 21:09:33 +0530 Subject: [PATCH 0921/1809] ARM: dts: msm: Add initial device tree for yupik-iot Add initial device tree to support yupik on IOT platform. Change-Id: I27ca5848ca9523aeae143d7835c90e9765670422 --- bindings/arm/msm/msm.txt | 10 ++++++++++ qcom/Makefile | 22 ++++++++++++++++++++-- qcom/yupik-iot-idp-overlay.dts | 11 +++++++++++ qcom/yupik-iot-idp.dts | 10 ++++++++++ qcom/yupik-iot-idp.dtsi | 1 + qcom/yupik-iot-idps-amoled-overlay.dts | 11 +++++++++++ qcom/yupik-iot-idps-amoled.dts | 10 ++++++++++ qcom/yupik-iot-idps-amoled.dtsi | 1 + qcom/yupik-iot-qrd-overlay.dts | 11 +++++++++++ qcom/yupik-iot-qrd.dts | 10 ++++++++++ qcom/yupik-iot-qrd.dtsi | 1 + qcom/yupik-iot.dts | 9 +++++++++ qcom/yupik-iot.dtsi | 7 +++++++ qcom/yupikp-iot-idp-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-idp.dts | 10 ++++++++++ qcom/yupikp-iot-idp.dtsi | 1 + qcom/yupikp-iot-idps-amoled-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-idps-amoled.dts | 10 ++++++++++ qcom/yupikp-iot-idps-amoled.dtsi | 1 + qcom/yupikp-iot-qrd-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-qrd.dts | 10 ++++++++++ qcom/yupikp-iot-qrd.dtsi | 1 + qcom/yupikp-iot.dts | 9 +++++++++ qcom/yupikp-iot.dtsi | 7 +++++++ 24 files changed, 194 insertions(+), 2 deletions(-) create mode 100644 qcom/yupik-iot-idp-overlay.dts create mode 100644 qcom/yupik-iot-idp.dts create mode 100644 qcom/yupik-iot-idp.dtsi create mode 100644 qcom/yupik-iot-idps-amoled-overlay.dts create mode 100644 qcom/yupik-iot-idps-amoled.dts create mode 100644 qcom/yupik-iot-idps-amoled.dtsi create mode 100644 qcom/yupik-iot-qrd-overlay.dts create mode 100644 qcom/yupik-iot-qrd.dts create mode 100644 qcom/yupik-iot-qrd.dtsi create mode 100644 qcom/yupik-iot.dts create mode 100644 qcom/yupik-iot.dtsi create mode 100644 qcom/yupikp-iot-idp-overlay.dts create mode 100644 qcom/yupikp-iot-idp.dts create mode 100644 qcom/yupikp-iot-idp.dtsi create mode 100644 qcom/yupikp-iot-idps-amoled-overlay.dts create mode 100644 qcom/yupikp-iot-idps-amoled.dts create mode 100644 qcom/yupikp-iot-idps-amoled.dtsi create mode 100644 qcom/yupikp-iot-qrd-overlay.dts create mode 100644 qcom/yupikp-iot-qrd.dts create mode 100644 qcom/yupikp-iot-qrd.dtsi create mode 100644 qcom/yupikp-iot.dts create mode 100644 qcom/yupikp-iot.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 725413636fb6..29112ab7ad27 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -62,6 +62,12 @@ SoCs: - YUPIKP compatible = "qcom,yupikp" +- YUPIK-IOT + compatible = "qcom,yupik-iot" + +- YUPIKP-IOT + compatible = "qcom,yupikp-iot" + - LITO compatible = "qcom,lito" @@ -228,9 +234,13 @@ compatible = "qcom,yupik-rumi" compatible = "qcom,yupik-idp" compatible = "qcom,yupik-atp" compatible = "qcom,yupik-qrd" +compatible = "qcom,yupik-iot-idp" +compatible = "qcom,yupik-iot-qrd" compatible = "qcom,yupikp-idp" compatible = "qcom,yupikp-atp" compatible = "qcom,yupikp-qrd" +compatible = "qcom,yupikp-iot-idp" +compatible = "qcom,yupikp-iot-qrd" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index dbf5ce930c97..c4fca42071c6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -164,7 +164,13 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupikp-atp-overlay.dtbo \ yupikp-qrd-overlay.dtbo \ yupikp-idps-digital-mics-overlay.dtbo \ - yupikp-idps-amoled-overlay.dtbo + yupikp-idps-amoled-overlay.dtbo \ + yupik-iot-idp-overlay.dtbo \ + yupik-iot-qrd-overlay.dtbo \ + yupik-iot-idps-amoled-overlay.dtbo \ + yupikp-iot-idp-overlay.dtbo \ + yupikp-iot-qrd-overlay.dtbo \ + yupikp-iot-idps-amoled-overlay.dtbo yupik-rumi-overlay.dtbo-base := yupik.dtb @@ -178,6 +184,12 @@ yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-digital-mics-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb +yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb +yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb +yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb +yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb +yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb +yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ @@ -189,7 +201,13 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupikp-atp.dtb \ yupikp-qrd.dtb \ yupikp-idps-digital-mics.dtb \ - yupikp-idps-amoled.dtb + yupikp-idps-amoled.dtb \ + yupik-iot-idp.dtb \ + yupik-iot-qrd.dtb \ + yupik-iot-idps-amoled.dtb \ + yupikp-iot-idp.dtb \ + yupikp-iot-qrd.dtb \ + yupikp-iot-idps-amoled.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/yupik-iot-idp-overlay.dts b/qcom/yupik-iot-idp-overlay.dts new file mode 100644 index 000000000000..359966e32f06 --- /dev/null +++ b/qcom/yupik-iot-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT IDP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-iot-idp.dts b/qcom/yupik-iot-idp.dts new file mode 100644 index 000000000000..8cbedefb7f2e --- /dev/null +++ b/qcom/yupik-iot-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT IDP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi new file mode 100644 index 000000000000..aeef58f4f289 --- /dev/null +++ b/qcom/yupik-iot-idp.dtsi @@ -0,0 +1 @@ +#include "yupik-idp.dtsi" diff --git a/qcom/yupik-iot-idps-amoled-overlay.dts b/qcom/yupik-iot-idps-amoled-overlay.dts new file mode 100644 index 000000000000..0f64f04e5599 --- /dev/null +++ b/qcom/yupik-iot-idps-amoled-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT IDPS + AMOLED"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupik-iot-idps-amoled.dts b/qcom/yupik-iot-idps-amoled.dts new file mode 100644 index 000000000000..e79ab2e046a4 --- /dev/null +++ b/qcom/yupik-iot-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT IDPS + AMOLED"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupik-iot-idps-amoled.dtsi b/qcom/yupik-iot-idps-amoled.dtsi new file mode 100644 index 000000000000..bfb95f0df27f --- /dev/null +++ b/qcom/yupik-iot-idps-amoled.dtsi @@ -0,0 +1 @@ +#include "yupik-idps-amoled.dtsi" diff --git a/qcom/yupik-iot-qrd-overlay.dts b/qcom/yupik-iot-qrd-overlay.dts new file mode 100644 index 000000000000..640be53957ac --- /dev/null +++ b/qcom/yupik-iot-qrd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT QRD"; + compatible = "qcom,yupik-iot-qrd", "qcom,yupik-iot", "qcom,qrd"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupik-iot-qrd.dts b/qcom/yupik-iot-qrd.dts new file mode 100644 index 000000000000..43d40b1d59cb --- /dev/null +++ b/qcom/yupik-iot-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT QRD"; + compatible = "qcom,yupik-iot-qrd", "qcom,yupik-iot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupik-iot-qrd.dtsi b/qcom/yupik-iot-qrd.dtsi new file mode 100644 index 000000000000..aa5635d74c44 --- /dev/null +++ b/qcom/yupik-iot-qrd.dtsi @@ -0,0 +1 @@ +#include "yupik-qrd.dtsi" diff --git a/qcom/yupik-iot.dts b/qcom/yupik-iot.dts new file mode 100644 index 000000000000..627c5e92daea --- /dev/null +++ b/qcom/yupik-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT SoC"; + compatible = "qcom,yupik-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi new file mode 100644 index 000000000000..6bbb816ba88b --- /dev/null +++ b/qcom/yupik-iot.dtsi @@ -0,0 +1,7 @@ +#include "yupik.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIK-IOT"; + compatible = "qcom,yupik-iot"; + qcom,msm-id = <497 0x10000>; +}; diff --git a/qcom/yupikp-iot-idp-overlay.dts b/qcom/yupikp-iot-idp-overlay.dts new file mode 100644 index 000000000000..01da5d563edd --- /dev/null +++ b/qcom/yupikp-iot-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-iot-idp.dts b/qcom/yupikp-iot-idp.dts new file mode 100644 index 000000000000..f2ff4b20dc7f --- /dev/null +++ b/qcom/yupikp-iot-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp.dtsi" +#include "yupikp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi new file mode 100644 index 000000000000..0790cb6d4444 --- /dev/null +++ b/qcom/yupikp-iot-idp.dtsi @@ -0,0 +1 @@ +#include "yupikp-idp.dtsi" diff --git a/qcom/yupikp-iot-idps-amoled-overlay.dts b/qcom/yupikp-iot-idps-amoled-overlay.dts new file mode 100644 index 000000000000..dfe1eae9874b --- /dev/null +++ b/qcom/yupikp-iot-idps-amoled-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDPS + AMOLED"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupikp-iot-idps-amoled.dts b/qcom/yupikp-iot-idps-amoled.dts new file mode 100644 index 000000000000..3e5c0643a7e0 --- /dev/null +++ b/qcom/yupikp-iot-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" +#include "yupikp-iot-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDPS + AMOLED"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/yupikp-iot-idps-amoled.dtsi b/qcom/yupikp-iot-idps-amoled.dtsi new file mode 100644 index 000000000000..e5dd0d176489 --- /dev/null +++ b/qcom/yupikp-iot-idps-amoled.dtsi @@ -0,0 +1 @@ +#include "yupikp-idps-amoled.dtsi" diff --git a/qcom/yupikp-iot-qrd-overlay.dts b/qcom/yupikp-iot-qrd-overlay.dts new file mode 100644 index 000000000000..1df03e9216a3 --- /dev/null +++ b/qcom/yupikp-iot-qrd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT QRD"; + compatible = "qcom,yupikp-iot-qrd", "qcom,yupikp-iot", "qcom,qrd"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupikp-iot-qrd.dts b/qcom/yupikp-iot-qrd.dts new file mode 100644 index 000000000000..40420074da33 --- /dev/null +++ b/qcom/yupikp-iot-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" +#include "yupikp-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT QRD"; + compatible = "qcom,yupikp-iot-qrd", "qcom,yupikp-iot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/yupikp-iot-qrd.dtsi b/qcom/yupikp-iot-qrd.dtsi new file mode 100644 index 000000000000..9119462f89dc --- /dev/null +++ b/qcom/yupikp-iot-qrd.dtsi @@ -0,0 +1 @@ +#include "yupikp-qrd.dtsi" diff --git a/qcom/yupikp-iot.dts b/qcom/yupikp-iot.dts new file mode 100644 index 000000000000..0c427cf162ae --- /dev/null +++ b/qcom/yupikp-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT SoC"; + compatible = "qcom,yupikp-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupikp-iot.dtsi b/qcom/yupikp-iot.dtsi new file mode 100644 index 000000000000..4c713241a0bc --- /dev/null +++ b/qcom/yupikp-iot.dtsi @@ -0,0 +1,7 @@ +#include "yupik-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YUPIKP-IOT"; + compatible = "qcom,yupikp-iot"; + qcom,msm-id = <498 0x10000>; +}; From 3d13ee788364df45f93cb2139f87c491a1b6b7d2 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Thu, 18 Feb 2021 10:42:31 +0530 Subject: [PATCH 0922/1809] ARM: dts: msm: Update MCLK rate Update MCLK rate Change-Id: I6fdb70bb95a4e805e86f7f31aa08c0a5d8dcf8b3 --- qcom/sdxnightjar-audio-overlay.dtsi | 2 +- qcom/sdxnightjar-audio.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxnightjar-audio-overlay.dtsi b/qcom/sdxnightjar-audio-overlay.dtsi index ae09715f9846..fdb9e34779f2 100644 --- a/qcom/sdxnightjar-audio-overlay.dtsi +++ b/qcom/sdxnightjar-audio-overlay.dtsi @@ -90,7 +90,7 @@ qcom,cdc-micbias2-mv = <1800>; qcom,cdc-micbias3-mv = <1800>; qcom,cdc-micbias4-mv = <1800>; - qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-mclk-clk-rate = <12288000>; qcom,cdc-dmic-sample-rate = <4800000>; swr_master { diff --git a/qcom/sdxnightjar-audio.dtsi b/qcom/sdxnightjar-audio.dtsi index c0b4b7cb941f..52b654e82655 100644 --- a/qcom/sdxnightjar-audio.dtsi +++ b/qcom/sdxnightjar-audio.dtsi @@ -41,8 +41,8 @@ "SpkrLeft IN", "SPK1 OUT"; qcom,tasha-mclk-clk-freq = <12288000>; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; From 3b62ebec37cc47774b9ac7eecd0e6f8d171d3be5 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 24 Aug 2020 18:55:02 +0530 Subject: [PATCH 0923/1809] ARM: dts: msm: Add ION support for SM6150 Add ION support for SM6150 target. Change-Id: I26c32957e860d79d8f349b150298998e13b5f1bf --- qcom/sm6150-ion.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 11 ++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 qcom/sm6150-ion.dtsi diff --git a/qcom/sm6150-ion.dtsi b/qcom/sm6150-ion.dtsi new file mode 100644 index 000000000000..b32c1fef4c51 --- /dev/null +++ b/qcom/sm6150-ion.dtsi @@ -0,0 +1,55 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap-sys { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + qcom,ion-heap-adsp { /* ADSP HEAP */ + reg = ; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-user { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-qsee { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-qseeta { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap-spss { /* SPSS HEAP */ + reg = ; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap-secdisp { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap-syssecure { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 81a6fc094f2f..fb05130d9fab 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -335,7 +335,7 @@ reg = <0x0 0x97715000 0x0 0x2000>; }; - qseecom_mem: qseecom_region@0x9e400000 { + qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; @@ -364,6 +364,14 @@ size = <0 0x400000>; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; @@ -2369,3 +2377,4 @@ #include "sm6150-slpi-pinctrl.dtsi" #include "sm6150-usb.dtsi" #include "sm6150-vidc.dtsi" +#include "sm6150-ion.dtsi" From 88ddefe72501d179a99b45a75e4ffd812e30987c Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 17 Feb 2021 20:56:04 +0530 Subject: [PATCH 0924/1809] ARM: dts: msm: Add proxy vote on display regulators on yupik Add proxy vote for L10C and L6B regulators on yupik target. Change-Id: Iea12abbefa2232c2d4e2417dd8768ad425710a2d --- qcom/yupik-regulators.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index f749bb55eeb7..f2feffa53383 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -153,6 +153,7 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm7325_l6>; L6B: pm7325_l6: regulator-pm7325-l6 { regulator-name = "pm7325_l6"; @@ -160,6 +161,8 @@ regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; qcom,init-voltage = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <8350>; qcom,init-mode = ; }; }; @@ -730,6 +733,7 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8350c_l10>; L10C: pm8350c_l10: regulator-pm8350c-l10 { regulator-name = "pm8350c_l10"; @@ -737,6 +741,8 @@ regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; qcom,init-voltage = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <37550>; qcom,init-mode = ; }; From 9e88abb2010ce3987c9e18994aa80d490abd3bb5 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Thu, 18 Feb 2021 18:40:32 +0530 Subject: [PATCH 0925/1809] ARM: dts: msm: updated memory map v5 for holi Updated memory map for holi inline with v5. Change-Id: Ib33a6450a4ffc8f11043c68d5f3b2044de9bd166 --- qcom/holi.dtsi | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index ffd8eb4d9d21..88cb863d8ac4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -322,37 +322,32 @@ pil_adsp_mem: adsp@86700000 { no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; + reg = <0x0 0x86700000 0x0 0x2000000>; }; - pil_cdsp_mem: cdsp@88f00000 { + pil_cdsp_mem: cdsp@88700000 { no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; + reg = <0x0 0x88700000 0x0 0x1e00000>; }; - pil_camera_mem: camera@8ad00000 { + pil_video_mem: video@8a500000 { no-map; - reg = <0x0 0x8ad00000 0x0 0x500000>; + reg = <0x0 0x8a500000 0x0 0x500000>; }; - pil_video_mem: video@8b200000 { + pil_ipa_fw_mem: ipa_fw@8aa00000 { no-map; - reg = <0x0 0x8b200000 0x0 0x500000>; + reg = <0x0 0x8aa00000 0x0 0x10000>; }; - pil_ipa_fw_mem: ipa_fw@8b700000 { + pil_ipa_gsi_mem: ipa_gsi@8aa10000 { no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; + reg = <0x0 0x8aa10000 0x0 0xa000>; }; - pil_ipa_gsi_mem: ipa_gsi@8b710000 { + pil_gpu_micro_code_mem: gpu_micro_code@8aa1a000 { no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; + reg = <0x0 0x8aa1a000 0x0 0x2000>; }; pil_mpss_wlan_mem: mpss_wlan@8b800000 { From 618d0e3db69680aa34b4e6d9cd6a3d2b9dffd845 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Thu, 18 Feb 2021 18:41:01 +0530 Subject: [PATCH 0926/1809] ARM: dts: msm: Update irq type for rtc and usb-id irq Update irq type for rtc and usb-id irq to avoid excessive warning log for sdxnightjar. Change-Id: Ic086f092dbc4df3db8fa0a56481594facbe9b623 --- qcom/pmd9650.dtsi | 2 +- qcom/sdxnightjar.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/pmd9650.dtsi b/qcom/pmd9650.dtsi index 23a437cb9494..03c2586b80de 100644 --- a/qcom/pmd9650.dtsi +++ b/qcom/pmd9650.dtsi @@ -73,7 +73,7 @@ qcom,pmd9650_rtc { compatible = "qcom,pm8941-rtc"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index de70b9e22d80..ab2aa4d2b994 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -992,9 +992,9 @@ reg = <0x55>; interrupt-parent = <&tlmm_pinmux>; interrupts = <83 IRQ_TYPE_LEVEL_LOW>; - interrupts-extended = <&tlmm_pinmux 83 IRQ_TYPE_LEVEL_LOW>, <&pmd9650_gpios 5 0>; + interrupts-extended = <&tlmm_pinmux 83 IRQ_TYPE_LEVEL_LOW>, <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "smb1351_chg_stat_irq","smb1351_usb_id_irq"; - qcom,usb-id-gpio = <&pmd9650_gpios 5 0>; + qcom,usb-id-gpio = <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>; qcom,float-voltage-mv = <4200>; qcom,charging-timeout = <1536>; qcom,recharge-thresh-mv = <200>; From 3540a3d03a53b694c28c7be2c1272df027476e58 Mon Sep 17 00:00:00 2001 From: Ramachandran Venkataramani Date: Thu, 21 Jan 2021 18:02:56 -0800 Subject: [PATCH 0927/1809] ARM: dts: msm: Update USB properties for SA8155 GVM - Add "snps,dis_u3_susphy_quirk" property to disable the SSPHY autosuspend. - Remove USB properties such as "snps,usb3-u1u2-disable", "usb-core-id" and "qcom,vbus-valid-override". - Clean up of "snps,hird-threshold" value. - Remove "qcom,charging-disabled". Change-Id: I2b2fd995e4b6d7fa0a00ce3677b2aa120db6f420 --- qcom/sa8155-vm-usb.dtsi | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi index bab658611352..9269e084ff3a 100644 --- a/qcom/sa8155-vm-usb.dtsi +++ b/qcom/sa8155-vm-usb.dtsi @@ -40,7 +40,6 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; - qcom,charging-disabled; qcom,ignore-wakeup-src-in-hostmode; status = "disabled"; @@ -53,9 +52,8 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - usb-core-id = <0>; - tx-fifo-resize; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -163,7 +161,6 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; - qcom,charging-disabled; status = "disabled"; @@ -175,10 +172,12 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; + snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; - usb-core-id = <1>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; @@ -224,7 +223,6 @@ qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&pm8150_2_l8>; - qcom,vbus-valid-override; qcom,qmp-phy-init-seq = /* */ Date: Wed, 10 Feb 2021 08:20:32 -0500 Subject: [PATCH 0928/1809] ARM: dts: msm: Enable IOSS v2 for sdxlemur Enable IOSS v2 driver for sdxlemur target. Change-Id: I132a0c165ed82f159b116d55d29b261680b5bf80 --- qcom/sdxlemur.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 1ef29a7bbc84..3bbd2e2996a3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -894,6 +894,9 @@ compatible = "qcom,msm_gsi"; }; + ioss: qcom,ioss { + compatible = "qcom,ioss-v2"; + }; pcie_ep: qcom,pcie@40002000 { compatible = "qcom,pcie-ep"; From 2eabb85fdfd0280bd66b3b8c9dc9da47543bc091 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 18 Feb 2021 18:28:13 -0800 Subject: [PATCH 0929/1809] ARM: dts: msm: Add qcom,usb-charger dt prop on sdxlemur Add qcom,usb-charger dt prop for setting the input current limit on sdxlemur. Change-Id: If94289075f2e0a632e551b6140753cc01b015663 --- qcom/sdxlemur-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 935727d619b3..fe9dab2a9c74 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -24,6 +24,7 @@ USB3_GDSC-supply = <&gcc_usb30_gdsc>; dpdm-supply = <&usb2_phy>; + qcom,usb-charger; clocks = <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, From fc5d81ca46542fd36ab0277c11bb17615a802a49 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Thu, 18 Feb 2021 19:39:50 -0800 Subject: [PATCH 0930/1809] ARM: dts: msm: Add virtual subsystem notification nodes for SA8155 VM Enable virtual subsystem notification for the ADSP and Wi-Fi subsystems on the SA8155 VM platform. Change-Id: Ia029d0308f1b49b01d332d11968ad990082beeaf --- bindings/arm/msm/subsystem_notif_virt.txt | 49 +++++++++++++++++++++++ qcom/sa8155-vm.dtsi | 18 +++++++++ 2 files changed, 67 insertions(+) create mode 100644 bindings/arm/msm/subsystem_notif_virt.txt diff --git a/bindings/arm/msm/subsystem_notif_virt.txt b/bindings/arm/msm/subsystem_notif_virt.txt new file mode 100644 index 000000000000..0fd0983b6250 --- /dev/null +++ b/bindings/arm/msm/subsystem_notif_virt.txt @@ -0,0 +1,49 @@ +Subsystem Notification Virtual Driver + +The guest VM uses this driver to communicate +subsystem state notifications to a backend driver +via the virtual device's registers. + +[Root level node] +Required Properties: +-compatible : Should be "qcom,subsys-notif-virt" +-reg : The start and size of the virtual device's + register set. +-reg-names : Should be "vdev_base" for virtual device's + base address. + +[Child nodes] +-subsys-names : The name of the subsystem that the + driver is registering to notifications for. +-offset : The offset from the virtual device's register + base where the subsystem state will be written. +-type : The type of the subsystem. + "virtual" - When the subsystem is loaded by the host VM. + "native" - When the subsystem is loaded by the guest VM. + +Required Property for "virtual" subsystem types: +-interrupts : Tuple defining the interrupt which the driver must + register for to receive subsystem state notifications + from the backend. +-interrupt-names: Must be "state-irq" + +Example: + + subsys_notif_virt: qcom,subsys_notif_virt@2D000000 { + compatible = "qcom,subsys-notif-virt"; + reg = <0x2D000000 0x400>; + reg-names = "vdev_base"; + adsp { + subsys-name = "adsp"; + interrupts = ; + interrupt-names = "state-irq"; + type = "virtual"; + offset = <0>; + }; + modem { + subsys-name = "modem"; + type = "native"; + offset = <256>; + }; + }; + diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index d863c4d7229a..7343bd1ff062 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -275,6 +275,24 @@ qcom,qsee-reentrancy-support = <2>; }; + subsys_notif_virt: qcom,subsys_notif_virt@2D000000 { + compatible = "qcom,subsys-notif-virt"; + reg = <0x2D000000 0x400>; + reg-names = "vdev_base"; + adsp { + subsys-name = "adsp"; + interrupts = ; + interrupt-names = "state-irq"; + type = "virtual"; + offset = <0>; + }; + + wlan { + subsys-name = "wlan"; + type = "native"; + offset = <512>; + }; + }; }; ®ulator { From 248eb30ef9dada485744318f4fe410c6fe84ea46 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Thu, 21 Jan 2021 18:09:59 +0530 Subject: [PATCH 0931/1809] ARM: dts: msm: Add AQC IPA offload configs Add AQC IPA offload configs for sdxlemur. Change-Id: I837c94d71c5febf08942b50a69e40c61f65eb77a --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 26c2d426d7a4..f8f1f84f6ce7 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -2,6 +2,38 @@ #include "sdxlemur-mtp-audio-overlay.dtsi" &soc { + ioss_aqc_eth0_rx: aqc_rx@eth0 { + qcom,dir-rx; + qcom,rx-filter-be; + + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <15>; + qcom,mod-count-max = <25>; + qcom,mod-usecs-min = <64>; + qcom,mod-usecs-max = <128>; + }; + + ioss_aqc_eth0_tx: aqc_tx@eth0 { + qcom,dir-tx; + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <15>; + qcom,mod-count-max = <25>; + qcom,mod-usecs-min = <64>; + qcom,mod-usecs-max = <128>; + }; + + ioss_aqc_eth0: aqc@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_aqc_eth0_rx>, + <&ioss_aqc_eth0_tx>; + }; }; @@ -12,8 +44,12 @@ aquantia,aqc@pcie0_rp { reg = <0 0 0 0 0>; + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; /* ipa shares this group with aqc */ qcom,iommu-group = <&ipa_eth_group1>; + qcom,ioss_interfaces = + <&ioss_aqc_eth0>; #address-cells = <1>; #size-cells = <1>; From 54a78f32166b7527dad145bc4881b8fd600e121b Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 19 Feb 2021 12:13:48 +0530 Subject: [PATCH 0932/1809] ARM: dts: msm: Update S1B and S8B min voltages on yupik Update the min voltages of SMPS1B and SMPS8B as per HW recommendation. Change-Id: I25a9a79cb139ec63b0643e1cb67ea2c3d803d2f4 --- qcom/yupik-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index f749bb55eeb7..a902f42d8be2 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -8,7 +8,7 @@ pm7325_s1: regulator-pm7325-s1 { regulator-name = "pm7325_s1"; qcom,set = ; - regulator-min-microvolt = <1856000>; + regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; qcom,init-voltage = <1872000>; }; @@ -50,7 +50,7 @@ pm7325_s8: regulator-pm7325-s8 { regulator-name = "pm7325_s8"; qcom,set = ; - regulator-min-microvolt = <1256000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; qcom,init-voltage = <1272000>; }; From 57ff53a3d98939ff42b4374f8c9c031802615833 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Fri, 19 Feb 2021 15:11:51 +0800 Subject: [PATCH 0933/1809] ARM: dts: qcom: disable thermal zone gpu-skin-avg-step on Lahaina HHG Thermal zone gpu-skin-avg-step is for Lahaina QRD and disable it on Lahaina HHG. Change-Id: I3bcc9abb826653dea04a0dc68bae11cde484a653 --- qcom/lahaina-hhg.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 62b988aa1121..ef489b1ebd86 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -297,4 +297,8 @@ }; }; }; + + gpu-skin-avg-step { + disable-thermal-zone; + }; }; From 983f5822e94dc5f578e8ec66146482a10f7173dc Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 19 Feb 2021 16:28:56 +0800 Subject: [PATCH 0934/1809] ARM: dts: msm: Disable SDCC TPDMs on yupik Disable all SDCC TPDMs on yupik first since there is SDCC internal clock issue. Change-Id: I029e8df0b6519805124a100e94f614790bae934c --- qcom/yupik-coresight.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 9cfb1d554902..9d0b985226b8 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -2351,6 +2351,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-1"; clocks = <&aopcc QDSS_CLK>; @@ -2373,6 +2374,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-4"; clocks = <&aopcc QDSS_CLK>; @@ -2538,6 +2540,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-2"; clocks = <&aopcc QDSS_CLK>; From a63fc865dda8964b0cf807ff82305f5ab4f29e9d Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Fri, 19 Feb 2021 13:46:10 +0530 Subject: [PATCH 0935/1809] ARM: dts: msm: Add firmware support for SA6150 Add firmware node which is parsed by android init to mount system and vendor partition. Change-Id: I575d8700d55399b66a7e9179325207db5aba1f9e --- qcom/sm6150.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index fb05130d9fab..553ccf642718 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -252,6 +252,26 @@ soc: soc { }; firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc + /1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; }; reserved_memory: reserved-memory { From 6fa6d138a6703b327d4a250d7b9e4a08df39f75b Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 29 Jan 2021 09:53:47 +0800 Subject: [PATCH 0936/1809] ARM: dts: msm: add panel in ECM device for yupik QRD platform Add panel information in amoled-ecm device node so that the driver can receive display off/on notification and disable/re-enable ECM accordingly. Change-Id: I25b2ec2c599a7484c56fcd07bc93bc056ef518b4 --- qcom/yupik-qrd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index a1423ec2a430..a32e7e7b4fae 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -415,6 +415,11 @@ 2500000 2000000 1500000 1000000 500000>; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_90hz_cmd_cphy + &dsi_r66451_amoled_144hz_cmd_cphy>; +}; + &pm8350b_tz { io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; io-channel-names = "thermal"; From c58b6b886aa034cb4c725b005ffa6fdc1e9dfd66 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Mon, 15 Feb 2021 18:23:16 +0530 Subject: [PATCH 0937/1809] ARM: dts: msm: Enable touch support on lahaina MTP 2.1 This change adds touch support for r66451 dsc fhd plus 60fps command mode panel on lahaina. Change-Id: I7b5e396bc52c02b8e879b1a947b40cea83aa3bbe --- qcom/lahaina-mtp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 9efb33e86994..237462e72971 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -103,6 +103,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_60hz_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; From ac1159b64617893bc3be9592fb1235c9bcf6e16f Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Sun, 21 Feb 2021 11:00:09 +0530 Subject: [PATCH 0938/1809] ARM: dts: msm: Add scm node for msmsteppe Add scm node under firmware for msmsteppe. Change-Id: I1aab35ff99c0fe1a1099c66376edb7c505d0b7d8 --- qcom/sm6150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b40eb0bb1ce9..122bcdc3c01e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2264,6 +2264,12 @@ }; +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + #include "sm6150-qupv3.dtsi" #include "sm6150-ssc-qupv3.dtsi" #include "sm6150-pinctrl.dtsi" From b2e6dabee765471986b3460a1193467a76893b67 Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Thu, 11 Feb 2021 20:28:40 +0530 Subject: [PATCH 0939/1809] ARM: dts: msm: Enable qseecom on sdxnightjar Add device tree entries to enable qseecom on sdxnightjar target. Change-Id: I50059575733e14b0935b68f42a01c409a34650ba --- qcom/sdxnightjar-ion.dtsi | 12 ++++++++++++ qcom/sdxnightjar.dtsi | 40 +++++++++++++++++++++++++++++++-------- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 177423c67e8a..173d5c56a634 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -16,6 +16,18 @@ memory-region = <&audio_mem>; qcom,ion-heap-type = "DMA"; }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 95eeafc47ad1..ba8c1d9387b7 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -53,6 +53,22 @@ label = "mss_mem"; }; + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x400000>; + }; + dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; @@ -75,6 +91,10 @@ compatible = "qcom,scm"; qcom,dload-mode = <&tcsr 0x6100>; }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; }; cpus { @@ -560,19 +580,23 @@ compatible = "qcom,qseecom"; reg = <0x87800000 0x200000>; reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; - qcom,msm-bus,name = "qseecom-noc"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <47 512 0 0>, - <47 512 200000 400000>, - <47 512 300000 800000>, - <47 512 400000 1000000>; + qcom,qsee-reentrancy-support = <2>; + qcom,support-bus-scaling; + qcom,appsbl-qseecom-support; + interconnect-names = "data_path"; + interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>; /*TODO: Fix the clock when tree is available*/ clock-names = "core_clk", "iface_clk", "bus_clk","core_clk_src"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; qcom,ce-opp-freq = <100000000>; }; From 07387e916ae7f31f40ec5163489c27be8f139b51 Mon Sep 17 00:00:00 2001 From: Anuj Garg Date: Wed, 13 Jan 2021 20:58:53 +0530 Subject: [PATCH 0940/1809] ARM: dts: msm: Add ADSP remoteheap vmlist for SA8155 This change add the remote heap vmid list in the device tree for dynamically hyp assign the memory. Change-Id: I7637a84cb0520367b02d951b6e5e88ef2a4e02ec --- qcom/sa8155.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 844e753c908b..a64466f5e6ad 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -125,6 +125,10 @@ vdda-phy-supply = <&pm8150_2_l18>; }; +&msm_fastrpc { + qcom,adsp-remoteheap-vmid = <3 5 6>; +}; + #include "camera/sa8155-camera.dtsi" #include "camera/sa8155-camera-sensor.dtsi" #include "sa8155-audio.dtsi" From 8cc3fb5ea6b2531b487700697e31d408c2ef7c87 Mon Sep 17 00:00:00 2001 From: Anuj Garg Date: Wed, 21 Oct 2020 12:04:25 +0530 Subject: [PATCH 0941/1809] ARM: dts: msm: Add device nodes for FastRPC and CDSP Loader for SA8195 Add fastrpc device tree nodes for CDSP, ADSP and SDSP for sa8195. Add cdsp loader device tree node for sa8195. Change-Id: Iac2cb70ceebceedd6adaea2efa41794c6034c350 --- qcom/sdmshrike-v2.dtsi | 39 ++++++++++ qcom/sdmshrike.dtsi | 162 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201 insertions(+) diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index 8390c82107c9..705d549d85a8 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -154,6 +154,45 @@ "kgsl_gmu_pdc_seq"; }; +&msm_fastrpc { + qcom,msm_fastrpc_compute_cb1 { + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb2 { + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb3 { + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb4 { + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb5 { + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb6 { + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb7 { + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb8 { + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb9 { + iommus = <&apps_smmu 0x1009 0x0460>; + }; +}; + + &msm_vidc { qcom,allowed-clock-rates = <240000000 338000000 365000000 444000000 533000000>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..006f734f9600 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1919,6 +1919,168 @@ compatible = "qcom,tee-shared-memory-bridge"; }; + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + qcom,adsp-remoteheap-vmid = <3 5 6>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x2040>, + <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x2001 0x420>, + <&apps_smmu 0x2041 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x4 0x3440>, + <&apps_smmu 0x24 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x5 0x3440>, + <&apps_smmu 0x25 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x6 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x7 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x8 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x2 0x3440>, + <&apps_smmu 0x22 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x3 0x3440>, + <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x2023 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x9 0x3460>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b23 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b24 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b25 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a1 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a2 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a3 0x0>; + shared-cb = <4>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + }; + qcom_qseecom: qseecom@87900000 { compatible = "qcom,qseecom"; reg = <0x87900000 0x2200000>; From be6673129207998bd9e538592078d8fec87fb1d0 Mon Sep 17 00:00:00 2001 From: Anuj Garg Date: Fri, 30 Oct 2020 11:56:44 +0530 Subject: [PATCH 0942/1809] ARM: dts: msm: Add device nodes for FastRPC and CDSP Loader for SM6150 Add fastrpc device tree nodes for CDSP, ADSP and SDSP for sm6150. Add cdsp loader device tree node for sm6150. Change-Id: Ia738b76525f3995dd731fd94f280abdfa7ed927b --- qcom/sm6150.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b40eb0bb1ce9..18a85ef67706 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1621,6 +1621,126 @@ #mbox-cells = <1>; }; + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1081 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1082 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1083 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1084 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1085 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1086 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1089 0x0>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1723 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1724 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1725 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1726 0x0>; + shared-cb = <5>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + }; + qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; From 47db0ca3cbe43f10ac63c12860aec32cea53b49c Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 22 Feb 2021 10:28:55 +0530 Subject: [PATCH 0943/1809] ARM: dts: msm: Add firmware support for SM8150 Add firmware node which is parsed by android init to mount system and vendor partition. Change-Id: I0417512750d485d034af311ce2d439e520875819 --- qcom/sm8150.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..36bbf3095ad3 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -230,7 +230,28 @@ soc: soc { }; - firmware: firmware { }; + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc + /1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; reserved_memory: reserved-memory { #address-cells = <2>; From e56ecdf7a8a14ecf4696f8a2362774a83aba73f3 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 22 Feb 2021 10:45:50 +0530 Subject: [PATCH 0944/1809] ARM: dts: msm: Add firmware support for SA8195 Add firmware node which is parsed by android init to mount system and vendor partition. Change-Id: Id32af33954fc91a1b00f281ce11fa121912a1747 --- qcom/sdmshrike.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..54f226ea0179 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -243,6 +243,26 @@ }; firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc + /1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; }; reserved_memory: reserved-memory { From 04421588f7d0e3eba99d78341f7f47bd54716efc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 18 Feb 2021 10:58:03 +0530 Subject: [PATCH 0945/1809] ARM: dts: msm: Add PCIE clocks to protected list for YUPIK The PCIE clocks are not required to be accessed, thus add them in protected list. Change-Id: I6af84f7b33af1ce695b8ccd14755b0ace23c2c75 --- qcom/yupik.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8ebfb94b891b..3c3a18758774 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1018,7 +1018,8 @@ , , , , , , - ; + , , + , ; #clock-cells = <1>; #reset-cells = <1>; From 87f1a3ee9f271b59525fda03b2993501eaeb8379 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 27 Aug 2020 10:15:30 +0530 Subject: [PATCH 0946/1809] ARM: dts: msm: Add mpm2 sleep counter for sm8150 Add mpm2 sleep counter to support boot time marker. Change-Id: I42949d9baadd2211ed2dbc08f22e2eb07e727675 --- qcom/sm8150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..0414ba2be13e 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -543,6 +543,12 @@ }; }; + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; From 16506136aafc04d94d76b3098f22d86e7b69025e Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Mon, 15 Feb 2021 21:23:41 +0530 Subject: [PATCH 0947/1809] ARM: dts: msm: add PCIe AUX clk freq for sa6155, sa8155, sa8195 Replace deprecated PCIe DT entry for PCIe AUX clock controller setting with the correct entry and value. PCIe core controller requires AUX clock to be 19.2MHz. Change-Id: Ia670d8e75f75939c2798d795e21771402d83569c --- qcom/sa6155-pcie.dtsi | 2 +- qcom/sa8195p-pcie.dtsi | 8 ++++---- qcom/sm8150-pcie.dtsi | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/qcom/sa6155-pcie.dtsi b/qcom/sa6155-pcie.dtsi index 26472a00ad05..67b8b1a46562 100644 --- a/qcom/sa6155-pcie.dtsi +++ b/qcom/sa6155-pcie.dtsi @@ -152,7 +152,7 @@ linux,pci-domain = <0>; qcom,pcie-phy-ver = <2609>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x0400>; diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi index e02c8da3cc37..c48ae1e75bc7 100644 --- a/qcom/sa8195p-pcie.dtsi +++ b/qcom/sa8195p-pcie.dtsi @@ -168,7 +168,7 @@ linux,pci-domain = <0>; qcom,pcie-phy-ver = <2110>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1d80>; @@ -476,7 +476,7 @@ linux,pci-domain = <1>; qcom,pcie-phy-ver = <2113>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1c80>; @@ -784,7 +784,7 @@ linux,pci-domain = <2>; qcom,pcie-phy-ver = <2105>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1d00>; @@ -1222,7 +1222,7 @@ linux,pci-domain = <3>; qcom,pcie-phy-ver = <2105>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1e00>; diff --git a/qcom/sm8150-pcie.dtsi b/qcom/sm8150-pcie.dtsi index 7547335577bb..367c832e495b 100644 --- a/qcom/sm8150-pcie.dtsi +++ b/qcom/sm8150-pcie.dtsi @@ -174,7 +174,7 @@ linux,pci-domain = <0>; qcom,pcie-phy-ver = <0x40>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1d80>; @@ -494,7 +494,7 @@ linux,pci-domain = <1>; qcom,pcie-phy-ver = <0x40>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,smmu-sid-base = <0x1e00>; From 5f94950b3e7a8e4d8180e37e96cd6677503b8888 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Sat, 26 Dec 2020 17:34:50 +0530 Subject: [PATCH 0948/1809] ARM: dts: msm: Add clock for SLPI pinctrl for SM8150 Add clock node to SLPI pinctrl driver for SM8150 target. Change-Id: I1cebf2f526e8e8a8815d13c984b5d304f57e250f --- bindings/pinctrl/qcom,slpi-pinctrl.txt | 6 ++++++ qcom/sm8150-slpi-pinctrl.dtsi | 2 ++ 2 files changed, 8 insertions(+) diff --git a/bindings/pinctrl/qcom,slpi-pinctrl.txt b/bindings/pinctrl/qcom,slpi-pinctrl.txt index 632bab8e5ad6..6992a03c8e72 100644 --- a/bindings/pinctrl/qcom,slpi-pinctrl.txt +++ b/bindings/pinctrl/qcom,slpi-pinctrl.txt @@ -20,6 +20,10 @@ Following properties are for SLPI Pin controller device main node. Value type: Definition: Number of PINs supported by the SLPI TLMM. +- clock-names: Should be "ssc-clk" + +- clocks: Handles to clocks specified in "clock-names" property. + Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". @@ -92,6 +96,8 @@ Example: slpi_tlmm: slpi_pinctrl@02b40000 { compatible = "qcom,slpi-pinctrl"; qcom,num-pins = <14>; + clock-names = "ssc-clk"; + clocks = <&clock_scc SCC_QUPV3_S_HCLK_CLK>; reg = <0x02b40000 0x20000>; slpi_mclk0_active: slpi_mclk0_active { diff --git a/qcom/sm8150-slpi-pinctrl.dtsi b/qcom/sm8150-slpi-pinctrl.dtsi index b31c153a9c41..b393c12ac079 100644 --- a/qcom/sm8150-slpi-pinctrl.dtsi +++ b/qcom/sm8150-slpi-pinctrl.dtsi @@ -2,6 +2,8 @@ slpi_tlmm: slpi_pinctrl@02B40000 { compatible = "qcom,slpi-pinctrl"; reg = <0x2B40000 0x20000>; + clock-names = "ssc-clk"; + clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; qcom,num-pins = <14>; status = "disabled"; From 386991061b566495fbb961eb45cee66a05e373a0 Mon Sep 17 00:00:00 2001 From: Hiren Gohel Date: Mon, 21 Dec 2020 13:34:30 +0530 Subject: [PATCH 0949/1809] ARM: dts: msm: Make sdhc aliases start from 0 Make sdhc aliases start from 0 to ennumerate block devices starting from mmcblk0 for emmc and mmcblk1 for sdcard. Change-Id: I911182f06b0d4540291501ab6352cfc01fc812c9 --- qcom/sm6150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b40eb0bb1ce9..09b930301d44 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -34,8 +34,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; - sdhc1 = &sdhc_1; - sdhc2 = &sdhc_2; + sdhc0 = &sdhc_1; + sdhc1 = &sdhc_2; }; cpus { From 883aedd4f7842f1550ad215714e5da2ef9f56fef Mon Sep 17 00:00:00 2001 From: Nitin LNU Date: Mon, 22 Feb 2021 17:56:50 +0530 Subject: [PATCH 0950/1809] ARM: dts: msm: Modify irq type for qcedev,qcrypto Modify irq type for qcedev and qcrypto for sdxnightjar to avoid excessive warning log for sdxnightjar. Change-Id: Idef2bbd8024779a8c9eb60effd675b1050275136 --- qcom/sdxnightjar.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 95eeafc47ad1..98d76d9df8d1 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -511,7 +511,7 @@ reg = <0x720000 0x20000>, <0x704000 0x20000>; reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 207 0>; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <1>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; @@ -533,7 +533,7 @@ reg = <0x720000 0x20000>, <0x704000 0x20000>; reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 207 0>; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; From ada56f0d988f9ca17549204c47c76ff7fd5a03c5 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 22 Feb 2021 14:10:55 -0800 Subject: [PATCH 0951/1809] ARM: dts: msm: expand iommu-map to support PCIe switch on sdxlemur CPE Additional BDF to SID mappings are needed if a switch and mutliple endpoints are connected to PCIe root complex. Expand iommu-map for PCIe on sdxprarie CPE to support such a usecase. Change-Id: Id7643ab574b1472649bb70121da70a40f31c806c --- qcom/sdxlemur-mtp-cpe.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 42f218547fd1..f3673cb5ec28 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -5,3 +5,14 @@ }; +&pcie0 { + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x208 &apps_smmu 0x0202 0x1>, + <0x210 &apps_smmu 0x0203 0x1>, + <0x218 &apps_smmu 0x0204 0x1>, + <0x300 &apps_smmu 0x0207 0x1>, + <0x400 &apps_smmu 0x0208 0x1>, + <0x500 &apps_smmu 0x020C 0x1>, + <0x501 &apps_smmu 0x020E 0x1>; +}; From dff71b3b8cf40da0775ee8adea6e6c81a39240a0 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 22 Feb 2021 14:13:55 -0800 Subject: [PATCH 0952/1809] ARM: dts: msm: add pci DT nodes for PCIe switch for sdxlemur CPE If there is a switch connected to PCIe root complex, the devicetree hierarchy needs to correctly reflect the physical connection. Add pci DT nodes for each switch device such as switch upstream and downstream ports for sdxlemur CPE. Change-Id: I04ddd33adc67f0ec689d014cd00ed5fa26d02a89 --- qcom/sdxlemur-mtp-cpe.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index f3673cb5ec28..e23998921bb7 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -16,3 +16,28 @@ <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; }; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + /* BDF 1.0.0 */ + pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 { + reg = <0 0 0 0 0>; + + /* BDF 2.1.0 */ + pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 { + reg = <0x800 0x0 0x0 0x0 0x0>; + }; + + /* BDF 2.2.0 */ + pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 { + reg = <0x1000 0x0 0x0 0x0 0x0>; + }; + + /* BDF 2.3.0 */ + pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { + reg = <0x1800 0x0 0x0 0x0 0x0>; + }; + }; +}; From a2239fe9fce9ededf22c177ea981691d5e1e64c1 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Tue, 23 Feb 2021 09:58:46 +0800 Subject: [PATCH 0953/1809] ARM: dts: qcom: thermal zones definition for thermistors on Lahaina HHG On Lahaina HHG quiet-therm-usr uses PM8350 AMUX2 channel, qtm-w-therm-usr uses PM8350 AMUX4 channel and qtm-n-therm-usr uses PM8350 GPIO1 channel. Meanwhile disable camera-therm-usr, rear-cam-therm-usr and tof-therm-usr using these channels. Change-Id: I4bf20074e2c4f8ef815667ff2e8c3e5574522e47 --- qcom/lahaina-hhg.dtsi | 57 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index ef489b1ebd86..34f46a9a2a32 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -301,4 +301,61 @@ gpu-skin-avg-step { disable-thermal-zone; }; + + camera-therm-usr { + disable-thermal-zone; + }; + + rear-cam-therm-usr { + disable-thermal-zone; + }; + + tof-therm-usr { + disable-thermal-zone; + }; + + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + qtm-w-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + qtm-n-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM5_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; From 6ecac82e65753f88e4292cf9d9068167eccaaa8c Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 22 Feb 2021 22:54:17 +0530 Subject: [PATCH 0954/1809] ARM: dts: msm: Remove PCIE clocks from protected list for YUPIK IOT The PCIE clocks are required to be accessed, thus remove them from the protected list. Change-Id: I4800f708fbb2a3502dc46ec7d33427c70391bfb3 --- qcom/yupik-iot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi index 6bbb816ba88b..d34b46f1c80a 100644 --- a/qcom/yupik-iot.dtsi +++ b/qcom/yupik-iot.dtsi @@ -5,3 +5,14 @@ compatible = "qcom,yupik-iot"; qcom,msm-id = <497 0x10000>; }; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk"; + + /delete-property/ protected-clocks; +}; From 9d836f929d0f2f63260b4d4d0c2525e8943f37c7 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 23 Feb 2021 10:40:00 +0530 Subject: [PATCH 0955/1809] ARM: dts: msm: Enable qcom,power-always-on for GPU SMMUs on GKI targets When unmapping memory, the SMMU driver must access the GPU SMMU's register space, so it must vote for power resources to access the TLB invalidation registers. When the GPU is in slumber, there aren't votes for the GPU SMMU's power resources, so the SMMU driver constantly ends up enabling/disabling the power resources, which takes a considerable amount of time. When paired with the suboptimal IOMMU page table management code, this leads to performance issues where the time taken to unmap memory is large. Thus, for all targets that support GKI, add the qcom,power-always-on property for the GPU SMMUs of these targets, to remove the latency incurred by having to enable/disable power resources in the GKI configuration. Change-Id: I403c9864705c50f7ce8b1118c3c75902708e647b --- qcom/msm-arm-smmu-yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index 833995eda61c..de5f1e65b6f5 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, From cc32cc1ef42b2223be9814214a683af8801f0045 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 22 Feb 2021 17:13:46 +0530 Subject: [PATCH 0956/1809] ARM: dts: msm: Add DT snapshots for pmi632 and pm6125 Add snapshot of pmi632 ,pm6125 and pm6125-rpm-regulators with base nodes for charger, QG, GPIOs, DIV_CLK, flash and other PMIC peripherals for pmi632 and pm6125. This snapshot is taken as of msm-4.19 commit c0c998ac0596 ("Merge "ARM: dts: msm: Enable diag channels for SDM429/439/QM215""). Change-Id: I67eea44d89f6e30824d71cd361fd4ffe90cbdec6 --- qcom/pm6125-rpm-regulator.dtsi | 509 ++++++++++++++++++++++++++++ qcom/pm6125.dtsi | 166 +++++++++ qcom/pmi632.dtsi | 599 +++++++++++++++++++++++++++++++++ 3 files changed, 1274 insertions(+) create mode 100644 qcom/pm6125-rpm-regulator.dtsi create mode 100644 qcom/pm6125.dtsi create mode 100644 qcom/pmi632.dtsi diff --git a/qcom/pm6125-rpm-regulator.dtsi b/qcom/pm6125-rpm-regulator.dtsi new file mode 100644 index 000000000000..b699d861d455 --- /dev/null +++ b/qcom/pm6125-rpm-regulator.dtsi @@ -0,0 +1,509 @@ +&rpm_bus { + /* VDD_APC supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_CX */ + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_MX */ + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <6>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <7>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <8>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_WCSS_CX */ + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi new file mode 100644 index 000000000000..fc8444727f6d --- /dev/null +++ b/qcom/pm6125.dtsi @@ -0,0 +1,166 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm6125@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm6125_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm6125_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6125_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6125_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6125_div_clk1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + assigned-clocks = <&pm6125_clkdiv 1>; + assigned-clock-rates = <9600000>; + }; + + pm6125_gpios: pinctrl@c000 { + compatible = "qcom,pm6125-gpio"; + reg = <0xc000>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6125_gpio1", "pm6125_gpio2", + "pm6125_gpio3", "pm6125_gpio4", + "pm6125_gpio5", "pm6125_gpio6", + "pm6125_gpio7", "pm6125_gpio8", + "pm6125_gpio9"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm6125_rtc: qcom,pm6125_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + qcom,pm6125@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + pm6125_pwm: qcom,pwms@b300 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xb300>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi new file mode 100644 index 000000000000..a1b0428668f9 --- /dev/null +++ b/qcom/pmi632.dtsi @@ -0,0 +1,599 @@ +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmi632@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + pmi632_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pmi632_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100>, <0x3700>; + reg-names = "adc5-usr-base", "adc5-cal-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + qcom,pmic-revid = <&pmi632_revid>; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + + v_i_int_ext { + reg = ; + label = "v_i_int_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_parallel { + reg = ; + label = "v_i_parallel_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + }; + + pmi632_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pmi632_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pmi632_gpios: pinctrl@c000 { + compatible = "qcom,pmi632-gpio"; + reg = <0xc000>; + interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, + <0x2 0xc1 0 IRQ_TYPE_NONE>, + <0x2 0xc2 0 IRQ_TYPE_NONE>, + <0x2 0xc3 0 IRQ_TYPE_NONE>, + <0x2 0xc4 0 IRQ_TYPE_NONE>, + <0x2 0xc5 0 IRQ_TYPE_NONE>, + <0x2 0xc6 0 IRQ_TYPE_NONE>, + <0x2 0xc7 0 IRQ_TYPE_NONE>; + interrupt-names = "pmi632_gpio1", "pmi632_gpio2", + "pmi632_gpio3", "pmi632_gpio4", + "pmi632_gpio5", "pmi632_gpio6", + "pmi632_gpio7", "pmi632_gpio8"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmi632_charger: qcom,qpnp-smb5 { + compatible = "qcom,qpnp-smb5"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pmi632_revid>; + io-channels = <&pmi632_vadc ADC_USB_IN_V_16>, + <&pmi632_vadc ADC_USB_IN_I>, + <&pmi632_vadc ADC_CHG_TEMP>, + <&pmi632_vadc ADC_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp"; + + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "fg-fvcal-qualified", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100>; + interrupts = + <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "bsm-active", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "all-chnl-conv-done", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500>; + interrupts = + <0x2 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "imp-trigger", + "temp-change", + "temp-change-smb"; + }; + + qcom,schgm-flash@a600 { + reg = <0xa600>; + interrupts = + <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + pmi632_qg: qpnp,qg { + compatible = "qcom,qpnp-qg"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,pmic-revid = <&pmi632_revid>; + io-channels = <&pmi632_vadc ADC_BAT_THERM_PU2>, + <&pmi632_vadc ADC_BAT_ID_PU2>; + io-channel-names = "batt-therm", + "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b100 { + status = "okay"; + reg = <0xb100>; + }; + }; + + pmi632_pbs_client3: qcom,pbs@7400 { + compatible = "qcom,qpnp-pbs"; + reg = <0x7400>; + }; + + pmi632_sdam7: qcom,sdam@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + }; + + bcl_sensor: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00>; + interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,ibat-use-qg-adc-5a; + #thermal-sensor-cells = <1>; + }; + + bcl_soc: bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; + + pmi632_3: qcom,pmi632@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + pmi632_vib: qcom,vibrator@5700 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5700>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pmi632_pwm: qcom,pwms@b300 { + compatible = "qcom,pwm-lpg"; + reg = <0xb300>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <5>; + nvmem-names = "ppg_sdam"; + nvmem = <&pmi632_sdam7>; + qcom,pbs-client = <&pmi632_pbs_client3>; + qcom,lut-sdam-base = <0x80>; + qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100 + 100 84 70 56 42 28 14 0 0 0>; + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pmi632_rgb: qcom,leds@d000 { + compatible = "qcom,tri-led"; + reg = <0xd000>; + red { + label = "red"; + pwms = <&pmi632_pwm 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pmi632_pwm 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pmi632_pwm 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pmi632_lcdb: qpnp-lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00>; + interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + + qcom,pmic-revid = <&pmi632_revid>; + qcom,voltage-step-ramp; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,pmi632-flash-led-v2"; + status = "okay"; + reg = <0xd300>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pmi632_revid>; + + pmi632_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi632_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + }; + + }; +}; From 05947dc436436818ecc568c5cb255ff956ffa6c4 Mon Sep 17 00:00:00 2001 From: wadesong Date: Mon, 14 Dec 2020 18:06:03 +0800 Subject: [PATCH 0957/1809] ARM: dts: msm: Enlarge the minidump cma area for SM8150 Enlarge the minidump cma area due to a number of new DTSI nodes (mainly related to CPU cache minidumps) have been added, which require more space. Change-Id: I8826f367433c6a26c5f1538166c4edc592996eb3 --- qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..a78fcb902e26 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -403,7 +403,7 @@ compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; - size = <0 0x2400000>; + size = <0 0x2800000>; }; /* global autoconfigured region for contiguous allocations */ From 3c080206fbdc8c481c335434b48baf5e6400a91e Mon Sep 17 00:00:00 2001 From: katamoni sai abhilash Date: Tue, 23 Feb 2021 14:46:18 +0530 Subject: [PATCH 0958/1809] ARM: dts: msm: Add qseecom node for sa8195 GVM Add dts entry for qseecom node for sa8195 Change-Id: I7c0b7f3581a5f23d7a125413fb76c2be081e1ec9 --- qcom/sa8195-vm.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 55f0f5e93385..fde9e1516c03 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -325,6 +325,25 @@ }; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + /*Boolean property to disable shmbridge*/ + qcom,disable-shmbridge-support; + }; + + qcom_qseecom: qseecom@87a00000 { + compatible = "qcom,qseecom"; + reg = <0x87a00000 0x2100000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc"; reg = <0xb220000 0x30000>; @@ -492,6 +511,12 @@ }; }; +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + #include "sdmshrike-pinctrl.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sa8195-vm-usb.dtsi" From 9d50a8c24efbfd0731f064a35c1d601065adcba0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 23 Feb 2021 18:17:49 +0530 Subject: [PATCH 0959/1809] ARM: dts: msm: Add qcom,no-accumulative-counter property for cpufreq Accumulative cycle counters are not supported, cycle counter needs to be read from the core-0 of the frequency domain. Add property to indicate the same. Change-Id: I503c4470824d29ee95a3c39a172ec716be77c61b --- qcom/sdmshrike.dtsi | 1 + qcom/sm6150.dtsi | 1 + qcom/sm8150.dtsi | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..eb071d23cb9a 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1331,6 +1331,7 @@ reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; #freq-domain-cells = <2>; }; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b40eb0bb1ce9..c2d68da84898 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1360,6 +1360,7 @@ reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; #freq-domain-cells = <2>; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..fd86394b8357 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1068,7 +1068,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + qcom,no-accumulative-counter; #freq-domain-cells = <2>; }; From f1d39ea45fef054b0a53f50d6e31b8deefa4e82a Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Tue, 23 Feb 2021 16:08:14 -0500 Subject: [PATCH 0960/1809] ARM: dts: msm: Add NPU device tree for sa8155/sa8195 Add NPU device tree to support NPU for sa8155/sa8195 Change-Id: I7f18d761ff40b7d2ed443f321aeab3cc65360e40 --- bindings/media/msm-npu-pwrlevels.txt | 164 +++++++++++++++++++ bindings/media/msm-npu.txt | 228 +++++++++++++++++++++++++++ qcom/sdmshrike-v2.dtsi | 159 +++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + qcom/sm8150-npu.dtsi | 192 ++++++++++++++++++++++ qcom/sm8150-v2.dtsi | 161 +++++++++++++++++++ qcom/sm8150.dtsi | 1 + 7 files changed, 906 insertions(+) create mode 100644 bindings/media/msm-npu-pwrlevels.txt create mode 100644 bindings/media/msm-npu.txt create mode 100644 qcom/sm8150-npu.dtsi diff --git a/bindings/media/msm-npu-pwrlevels.txt b/bindings/media/msm-npu-pwrlevels.txt new file mode 100644 index 000000000000..9a8a014c95d8 --- /dev/null +++ b/bindings/media/msm-npu-pwrlevels.txt @@ -0,0 +1,164 @@ +Qualcomm Technologies, Inc. NPU powerlevels + +Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines +a series of clock frequencies. These frequencies are for the corresponding +clocks in the clocks property of the msm_npu device. + +qcom,npu-pwrlevels bindings: + +Required Properties: +- #address-cells: Should be set to 1 +- #size-cells: Should be set to 0 +- compatible: Must be qcom,npu-pwrlevels +- initial-pwrlevel: NPU initial wakeup power level, this is the index of the + child node. + +qcom,npu-pwrlevel: This is a child node defining power levels. +qcom,npu-pwrlevels must contain at least one power level node. Each child node +has the following properties: + +Required Properties: +- reg: Index of the powerlevel (0 = lowest performance) +- clk-freq: List of clock frequencies (in Hz) of each clock for the current + powerlevel. List of clocks and order described in: + Documentation/devicetree/bindings/media/msm-npu.txt + +Example: + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; diff --git a/bindings/media/msm-npu.txt b/bindings/media/msm-npu.txt new file mode 100644 index 000000000000..f009650f728a --- /dev/null +++ b/bindings/media/msm-npu.txt @@ -0,0 +1,228 @@ +* Qualcomm Technologies, Inc. MSM NPU + +NPU (Neural Network Processing Unit) applies neural network processing + +Required properties: +- compatible: Must be "qcom,msm-npu" +- reg: Specify offset and length of the device register sets. +- reg-names: Names corresponding to the defined register sets. + - "npu_base": npu base registers +- interrupts: Specify the npu interrupts. +- interrupt-names: should specify relevant names to each interrupts + property defined. +- cache-slice-names: A set of names that identify the usecase names of a + client that uses cache slice. These strings are used to look up the + cache slice entries by name +- cache-slices: The tuple has phandle to llcc device as the first argument + and the second argument is the usecase id of the client +- clocks: clocks required for the device. +- clock-names: names of clocks required for the device. +- vdd-supply: Phandle for vdd regulator device node +- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding + 'reg' domain, e.g. vdd_cx-supply. +- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off + during proxy voting/unvoting. +- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator, + e.g. qcom,vdd_cx-uV-uA. +- mboxes: Phandle array for mailbox controllers to be used for IPC +- mbox-names: names of each mailboxes +- #cooling-cells: Should be set to 2 +- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements + (see devbw.txt) +- qcom,npu-pwrlevels: Container for NPU power levels + (see msm-npu-pwrlevels.txt) +Example: + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x800000>; + reg-names = "npu_base"; + interrupts = ; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + cache-slice-names = "npu"; + cache-slices = <&llcc 23>; + clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CLK_SRC>, + <&clock_npucc NPU_CC_XO_CLK>, + <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, + <&clock_npucc NPU_CC_BTO_CORE_CLK>, + <&clock_npucc NPU_CC_BWMON_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, + <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&clock_npucc NPU_CC_PERF_CNT_CLK>, + <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, + <&clock_npucc NPU_CC_SLEEP_CLK>; + clock-names = "cal_dp_clk", + "cal_dp_clk_src", + "xo_clk", + "armwic_core_clk", + "bto_core_clk", + "bwmon_clk", + "cal_dp_cdc_clk", + "comp_noc_axi_clk", + "conf_noc_ahb_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "perf_cnt_clk", + "qtimer_core_clk", + "sleep_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&pm8150l_s6_level>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>; + mbox-names = "npu_low", "npu_high"; + #cooling-cells = <2>; + qcom,npubw-dev = <&npu_npu_ddr_bw>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; + }; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index 8390c82107c9..eaa848dd6882 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -171,3 +171,162 @@ iommus = <&apps_smmu 0x2304 0x60>; }; }; + +&msm_npu { + iommus = <&apps_smmu 0x1481 0x400>, <&apps_smmu 0x1081 0x400>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <5>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 487000000 + 487000000 + 37500000 + 300000000 + 200000000 + 150000000 + 19200000 + 240000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 487000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 652000000 + 652000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 652000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 400000000 + 811000000 + 811000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 811000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@5 { + reg = <5>; + vreg = <7>; + clk-freq = <0 + 0 + 0 + 400000000 + 908000000 + 908000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 908000000 + 19200000 + 19200000>; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..da8593875777 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -2090,6 +2090,7 @@ #include "sdmshrike-gpu.dtsi" #include "sa8195-vidc.dtsi" #include "sa8155-audio.dtsi" +#include "sm8150-npu.dtsi" #include "display/sdmshrike-sde-pll.dtsi" #include "display/sdmshrike-sde.dtsi" diff --git a/qcom/sm8150-npu.dtsi b/qcom/sm8150-npu.dtsi new file mode 100644 index 000000000000..06bda61d35d8 --- /dev/null +++ b/qcom/sm8150-npu.dtsi @@ -0,0 +1,192 @@ +&soc { + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x40000>, + <0x9900000 0x10000>, + <0x9960200 0x600>; + reg-names = "tcm", "core", "bwmon"; + interrupts = , + , + ; + interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq"; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + clocks = <&aopcc QDSS_CLK>, + <&gcc GCC_NPU_AT_CLK>, + <&gcc GCC_NPU_TRIG_CLK>, + <&npucc NPU_CC_ARMWIC_CORE_CLK>, + <&npucc NPU_CC_CAL_DP_CLK>, + <&npucc NPU_CC_CAL_DP_CDC_CLK>, + <&npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&npucc NPU_CC_NPU_CORE_CLK>, + <&npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&npucc NPU_CC_NPU_CORE_APB_CLK>, + <&npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&npucc NPU_CC_NPU_CPC_CLK>, + <&npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&npucc NPU_CC_QTIMER_CORE_CLK>, + <&npucc NPU_CC_SLEEP_CLK>, + <&npucc NPU_CC_BWMON_CLK>, + <&npucc NPU_CC_PERF_CNT_CLK>, + <&npucc NPU_CC_BTO_CORE_CLK>, + <&npucc NPU_CC_XO_CLK>; + clock-names = "qdss_clk", + "at_clk", + "trig_clk", + "armwic_core_clk", + "cal_dp_clk", + "cal_dp_cdc_clk", + "conf_noc_ahb_clk", + "comp_noc_axi_clk", + "npu_core_clk", + "npu_core_cti_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "qtimer_core_clk", + "sleep_clk", + "bwmon_clk", + "perf_cnt_clk", + "bto_core_clk", + "xo_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + #cooling-cells = <2>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 350000000 + 350000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 350000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 400000000 + 400000000 + 37500000 + 300000000 + 200000000 + 75000000 + 19200000 + 120000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 600000000 + 600000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 600000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 350000000 + 715000000 + 715000000 + 75000000 + 533000000 + 350000000 + 150000000 + 19200000 + 240000000 + 350000000 + 19200000 + 19200000 + 0 + 19200000 + 715000000 + 19200000 + 19200000>; + }; + }; + }; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 6ab80cc54442..89f7cf5c1bfc 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -560,4 +560,165 @@ iommus = <&apps_smmu 0x2304 0x60>; }; }; + +/* NPU overrides */ +&msm_npu { + iommus = <&apps_smmu 0x1081 0x400>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <5>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 487000000 + 487000000 + 37500000 + 300000000 + 200000000 + 150000000 + 19200000 + 240000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 487000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 652000000 + 652000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 652000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 400000000 + 811000000 + 811000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 811000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@5 { + reg = <5>; + vreg = <7>; + clk-freq = <0 + 0 + 0 + 400000000 + 908000000 + 908000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 908000000 + 19200000 + 19200000>; + }; + }; +}; + #include "camera/sm8150-v2-camera.dtsi" diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..918fe64b6d84 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2795,3 +2795,4 @@ #include "sm8150-pcie.dtsi" #include "sm8150-usb.dtsi" #include "sm8150-gpu.dtsi" +#include "sm8150-npu.dtsi" From 7f8c9684ae05dbd8ab2634ef52ea8949ca4218ed Mon Sep 17 00:00:00 2001 From: Karthik Rudrapatna Date: Wed, 20 Jan 2021 17:20:08 -0800 Subject: [PATCH 0961/1809] ARM: dts: msm: Add IOSS config for Realtek R8125 Add IOSS config for Realtek R8125B NIC on sdxlemur platform. Change-Id: I03743995e84be98c74c46e64cd07766693ae5b02 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index f8f1f84f6ce7..df7cb688557d 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -35,6 +35,38 @@ <&ioss_aqc_eth0_tx>; }; + ioss_r8125_eth0_rx: r8125_rx@eth0 { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <32>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_r8125_eth0_tx: r8125_tx@eth0 { + qcom,dir-tx; + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <32>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_r8125_eth0: r8125@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_r8125_eth0_rx>, + <&ioss_r8125_eth0_tx>; + }; }; &pcie0_rp { @@ -84,6 +116,10 @@ realtek,rtl8125@pcie0_rp { reg = <0 0 0 0 0>; + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = <&ioss_r8125_eth0>; + /* ipa shares this group with rtl */ qcom,iommu-group = <&ipa_eth_group1>; From 44ffc5f62be365d527b662f0858071bd12e92358 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 19 Nov 2020 01:25:24 +0530 Subject: [PATCH 0962/1809] ARM: dts: qcom: Enable TSENS and thermal zone changes for sdxnightjar Enable TSENS driver, default userspace thermal zone rules for each TSENS, enable QMI cooling device, regulator cooling device and enable modem junction temperature mitigation thermal zone rule for sdxnightjar. Change-Id: I67efdb252e3fb59a6d6256b03613b14e8a5e2c56 --- qcom/sdxnightjar-regulator.dtsi | 8 ++ qcom/sdxnightjar-thermal.dtsi | 177 ++++++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 3 + 3 files changed, 188 insertions(+) create mode 100644 qcom/sdxnightjar-thermal.dtsi diff --git a/qcom/sdxnightjar-regulator.dtsi b/qcom/sdxnightjar-regulator.dtsi index d381a0a2996a..074adccb73c6 100644 --- a/qcom/sdxnightjar-regulator.dtsi +++ b/qcom/sdxnightjar-regulator.dtsi @@ -92,6 +92,14 @@ ; qcom,use-voltage-floor-level; }; + + cx_cdev: cx-cdev { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pmd9650_s5_floor_level>; + regulator-levels = ; + #cooling-cells = <2>; + }; }; rpm-regulator-ldoa1 { diff --git a/qcom/sdxnightjar-thermal.dtsi b/qcom/sdxnightjar-thermal.dtsi new file mode 100644 index 000000000000..657530c6180b --- /dev/null +++ b/qcom/sdxnightjar-thermal.dtsi @@ -0,0 +1,177 @@ +#include + +&soc { + tsens0: tsens@4a8000 { + compatible = "qcom,msm8996-tsens"; + reg = <0x4a8000 0x152>, + <0x4a9000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts-extended = <&intc GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + + modem_cpr_cold: modem_cpr_cold { + qcom,qmi-dev-name = "cpr_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ipa-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + trips { + tj_config0: active-config0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + tj_config1: active-config1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_proc_cdev1 { + trip = <&tj_config0>; + cooling-device = <&modem_proc 1 1>; + }; + + modem_proc_cdev2 { + trip = <&tj_config1>; + cooling-device = <&modem_proc 3 3>; + }; + }; + }; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 95eeafc47ad1..40213acab1b6 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -897,6 +897,8 @@ }; }; + thermal_zones: thermal-zones {}; + spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, @@ -1032,6 +1034,7 @@ #include "sdxnightjar-pcie.dtsi" #include "sdxnightjar-audio.dtsi" #include "sdxnightjar-audio-overlay.dtsi" +#include "sdxnightjar-thermal.dtsi" &i2c_3 { status = "ok"; From 52b8ab20bbec7252cac1afe4cf24a16d4a7ffd08 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 6 Jan 2021 11:29:40 +0530 Subject: [PATCH 0963/1809] ARM: dts: msm: Add NPU-DDR devfreq nodes to SA8155 Add NPU-DDR device tree nodes for devfreq support on target SA8155. Change-Id: I95f71ec7bd77dc7935571f96a70fcec030f1ec15 --- qcom/sm8150.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fa02382e5424..37dec501ad8a 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -882,6 +882,25 @@ }; }; + npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; + operating-points-v2 = <&ddr_bw_opp_table>; + qcom,active-only; + }; + + npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x9960300 0x300>, <0x9960200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&npu_npu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; From 65ba7f89e98f1b291f01044f93b92041ec6effdb Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 6 Jan 2021 11:30:52 +0530 Subject: [PATCH 0964/1809] ARM: dts: msm: Add NPU-DDR devfreq nodes to SA8195 Add NPU-DDR device tree nodes for devfreq support on target SA8195. Change-Id: Ibecfdc9a9b952a0fb520274fc6f3f7ff6ae1a68e --- qcom/sdmshrike.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 006f734f9600..bbe2d75485a5 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -808,6 +808,25 @@ }; }; + npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; + operating-points-v2 = <&ddr_bw_opp_table>; + qcom,active-only; + }; + + npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x9960300 0x300>, <0x9960200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&npu_npu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; From 2204751dd4d6215fe0e7d999661cd4158ac1778a Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Mon, 15 Feb 2021 17:39:50 +0800 Subject: [PATCH 0965/1809] ARM: dts: msm: Add virtual spmi device tree node for sa8155 Add virtual spmi pmic and its dependent device tree node to support SA8155 for automotive platforms. Change-Id: I4c4411a4d0cd2331ae62e46aed1ec9e054be4d88 --- qcom/pm8150-vm.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++ qcom/quin-vm-common.dtsi | 13 ++++++++++ qcom/sa8155-vm.dtsi | 1 + 3 files changed, 70 insertions(+) create mode 100644 qcom/pm8150-vm.dtsi diff --git a/qcom/pm8150-vm.dtsi b/qcom/pm8150-vm.dtsi new file mode 100644 index 000000000000..2139dee1ebeb --- /dev/null +++ b/qcom/pm8150-vm.dtsi @@ -0,0 +1,56 @@ +#include +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm8150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8150_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&pm8150_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 2f1643b12a3d..fe320ee1341b 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -266,4 +266,17 @@ reg = <0xc221000 0x1000>; clock-frequency = <32768>; }; + + spmi_bus: virtio-spmi@1c800000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1c800000 0x1100>; + interrupt-names = "periph_irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + status = "okay"; + }; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 7343bd1ff062..5cab1cb3be32 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -393,6 +393,7 @@ #include "sa8155-vm-pcie.dtsi" #include "sm8150-qupv3.dtsi" #include "sm8150-ssc-qupv3.dtsi" +#include "pm8150-vm.dtsi" &tlmm { /delete-property/ wakeup-parent; From d2971f2a29f225286c97f7acd9729c2f221c6094 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Thu, 6 Aug 2020 20:23:10 +0530 Subject: [PATCH 0966/1809] ARM: dts: msm: STMMAC binding Add support for STMMAC binding doc. Change-Id: I6292ee23e09f76267465d558799f754d15035064 --- bindings/net/qcom,sdxprairie-ethqos.txt | 179 ++++++++++++++++++++++++ bindings/net/qcom,stmmac-ethqos.txt | 179 ++++++++++++++++++++++++ 2 files changed, 358 insertions(+) create mode 100644 bindings/net/qcom,sdxprairie-ethqos.txt create mode 100644 bindings/net/qcom,stmmac-ethqos.txt diff --git a/bindings/net/qcom,sdxprairie-ethqos.txt b/bindings/net/qcom,sdxprairie-ethqos.txt new file mode 100644 index 000000000000..e8797eb611ee --- /dev/null +++ b/bindings/net/qcom,sdxprairie-ethqos.txt @@ -0,0 +1,179 @@ +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC) + +Required properties: +- compatible: Should be "qcom,sdxprairie-ethqos", + For backwards compatibility: "st,spear600-gmac" is also supported. +- reg: Address and length of the register set for the device +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the STMMAC interrupts +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: + - "macirq" (combined signal for various interrupt events) + - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) + - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state) +- phy-mode: See ethernet.txt file in the same directory. +- snps,reset-gpio gpio number for phy reset. +- snps,reset-active-low boolean flag to indicate if phy reset is active low. +- snps,reset-delays-us is triplet of delays + The 1st cell is reset pre-delay in micro seconds. + The 2nd cell is reset pulse in micro seconds. + The 3rd cell is reset post-delay in micro seconds. + +Optional properties: +- resets: Should contain a phandle to the STMMAC reset signal, if any +- reset-names: Should contain the reset signal name "stmmaceth", if a + reset phandle is given +- max-frame-size: See ethernet.txt file in the same directory +- clocks: If present, the first clock should be the GMAC main clock and + the second clock should be peripheral's register interface clock. Further + clocks may be specified in derived bindings. +- clock-names: One name for each entry in the clocks property, the + first one should be "stmmaceth" and the second one should be "pclk". +- ptp_ref: this is the PTP reference clock; in case of the PTP is available + this clock is used for programming the Timestamp Addend Register. If not + passed then the system clock will be used and this is fine on some + platforms. +- tx-fifo-depth: See ethernet.txt file in the same directory +- rx-fifo-depth: See ethernet.txt file in the same directory +- snps,pbl Programmable Burst Length (tx and rx) +- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. + If set, DMA tx will use this value rather than snps,pbl. +- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. + If set, DMA rx will use this value rather than snps,pbl. +- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. + For core rev < 3.50, don't multiply the values by 4. +- snps,aal Address-Aligned Beats +- snps,fixed-burst Program the DMA to use the fixed burst mode +- snps,mixed-burst Program the DMA to use the mixed burst mode +- snps,force_thresh_dma_mode Force DMA to use the threshold mode for + both tx and rx +- snps,force_sf_dma_mode Force DMA to use the Store and Forward + mode for both tx and rx. This flag is + ignored if force_thresh_dma_mode is set. +- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during + TX low-power mode +- snps,multicast-filter-bins: Number of multicast filter hash bins + supported by this device instance +- snps,perfect-filter-entries: Number of perfect filter entries supported + by this device instance +- snps,ps-speed: port selection speed that can be passed to the core when + PCS is supported. For example, this is used in case of SGMII + and MAC2MAC connection. +- snps,tso: this enables the TSO feature otherwise it will be managed by + MAC HW capability register. Only for GMAC4 and newer. +- AXI BUS Mode parameters: below the list of all the parameters to program the + AXI register inside the DMA module: + - snps,lpi_en: enable Low Power Interface + - snps,xit_frm: unlock on WoL + - snps,wr_osr_lmt: max write outstanding req. limit + - snps,rd_osr_lmt: max read outstanding req. limit + - snps,kbbe: do not cross 1KiB boundary. + - snps,blen: this is a vector of supported burst length. + - snps,fb: fixed-burst + - snps,mb: mixed-burst + - snps,rb: rebuild INCRx Burst +- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. +- Multiple RX Queues parameters: below the list of all the parameters to + configure the multiple RX queues: + - snps,rx-queues-to-use: number of RX queues to be used in the driver + - Choose one of these RX scheduling algorithms: + - snps,rx-sched-sp: Strict priority + - snps,rx-sched-wsp: Weighted Strict priority + - For each RX queue + - Choose one of these modes: + - snps,dcb-algorithm: Queue to be enabled as DCB + - snps,avb-algorithm: Queue to be enabled as AVB + - snps,map-to-dma-channel: Channel to map + - Specifiy specific packet routing: + - snps,route-avcp: AV Untagged Control packets + - snps,route-ptp: PTP Packets + - snps,route-dcbcp: DCB Control Packets + - snps,route-up: Untagged Packets + - snps,route-multi-broad: Multicast & Broadcast Packets + - snps,priority: RX queue priority (Range: 0x0 to 0xF) +- Multiple TX Queues parameters: below the list of all the parameters to + configure the multiple TX queues: + - snps,tx-queues-to-use: number of TX queues to be used in the driver + - Choose one of these TX scheduling algorithms: + - snps,tx-sched-wrr: Weighted Round Robin + - snps,tx-sched-wfq: Weighted Fair Queuing + - snps,tx-sched-dwrr: Deficit Weighted Round Robin + - snps,tx-sched-sp: Strict priority + - For each TX queue + - snps,weight: TX queue weight (if using a DCB weight algorithm) + - Choose one of these modes: + - snps,dcb-algorithm: TX queue will be working in DCB + - snps,avb-algorithm: TX queue will be working in AVB + [Attention] Queue 0 is reserved for legacy traffic + and so no AVB is available in this queue. + - Configure Credit Base Shaper (if AVB Mode selected): + - snps,send_slope: enable Low Power Interface + - snps,idle_slope: unlock on WoL + - snps,high_credit: max write outstanding req. limit + - snps,low_credit: max read outstanding req. limit + - snps,priority: TX queue priority (Range: 0x0 to 0xF) +Examples: + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + + queue1 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + snps,priority = <0x1>; + }; + }; + + gmac0: ethernet@e0800000 { + compatible = "qcom,sdxprairie-ethqos"; + reg = <0xe0800000 0x8000>; + interrupt-parent = <&vic1>; + interrupts = <24 23 22>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + max-frame-size = <3800>; + phy-mode = "gmii"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + clocks = <&clock>; + clock-names = "stmmaceth"; + snps,axi-config = <&stmmac_axi_setup>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@0 { + }; + }; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + }; diff --git a/bindings/net/qcom,stmmac-ethqos.txt b/bindings/net/qcom,stmmac-ethqos.txt new file mode 100644 index 000000000000..f910fb509396 --- /dev/null +++ b/bindings/net/qcom,stmmac-ethqos.txt @@ -0,0 +1,179 @@ +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC) + +Required properties: +- compatible: Should be "qcom,stmmac-ethqos", + For backwards compatibility: "st,spear600-gmac" is also supported. +- reg: Address and length of the register set for the device +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the STMMAC interrupts +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: + - "macirq" (combined signal for various interrupt events) + - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) + - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state) +- phy-mode: See ethernet.txt file in the same directory. +- snps,reset-gpio gpio number for phy reset. +- snps,reset-active-low boolean flag to indicate if phy reset is active low. +- snps,reset-delays-us is triplet of delays + The 1st cell is reset pre-delay in micro seconds. + The 2nd cell is reset pulse in micro seconds. + The 3rd cell is reset post-delay in micro seconds. + +Optional properties: +- resets: Should contain a phandle to the STMMAC reset signal, if any +- reset-names: Should contain the reset signal name "stmmaceth", if a + reset phandle is given +- max-frame-size: See ethernet.txt file in the same directory +- clocks: If present, the first clock should be the GMAC main clock and + the second clock should be peripheral's register interface clock. Further + clocks may be specified in derived bindings. +- clock-names: One name for each entry in the clocks property, the + first one should be "stmmaceth" and the second one should be "pclk". +- ptp_ref: this is the PTP reference clock; in case of the PTP is available + this clock is used for programming the Timestamp Addend Register. If not + passed then the system clock will be used and this is fine on some + platforms. +- tx-fifo-depth: See ethernet.txt file in the same directory +- rx-fifo-depth: See ethernet.txt file in the same directory +- snps,pbl Programmable Burst Length (tx and rx) +- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. + If set, DMA tx will use this value rather than snps,pbl. +- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. + If set, DMA rx will use this value rather than snps,pbl. +- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. + For core rev < 3.50, don't multiply the values by 4. +- snps,aal Address-Aligned Beats +- snps,fixed-burst Program the DMA to use the fixed burst mode +- snps,mixed-burst Program the DMA to use the mixed burst mode +- snps,force_thresh_dma_mode Force DMA to use the threshold mode for + both tx and rx +- snps,force_sf_dma_mode Force DMA to use the Store and Forward + mode for both tx and rx. This flag is + ignored if force_thresh_dma_mode is set. +- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during + TX low-power mode +- snps,multicast-filter-bins: Number of multicast filter hash bins + supported by this device instance +- snps,perfect-filter-entries: Number of perfect filter entries supported + by this device instance +- snps,ps-speed: port selection speed that can be passed to the core when + PCS is supported. For example, this is used in case of SGMII + and MAC2MAC connection. +- snps,tso: this enables the TSO feature otherwise it will be managed by + MAC HW capability register. Only for GMAC4 and newer. +- AXI BUS Mode parameters: below the list of all the parameters to program the + AXI register inside the DMA module: + - snps,lpi_en: enable Low Power Interface + - snps,xit_frm: unlock on WoL + - snps,wr_osr_lmt: max write outstanding req. limit + - snps,rd_osr_lmt: max read outstanding req. limit + - snps,kbbe: do not cross 1KiB boundary. + - snps,blen: this is a vector of supported burst length. + - snps,fb: fixed-burst + - snps,mb: mixed-burst + - snps,rb: rebuild INCRx Burst +- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. +- Multiple RX Queues parameters: below the list of all the parameters to + configure the multiple RX queues: + - snps,rx-queues-to-use: number of RX queues to be used in the driver + - Choose one of these RX scheduling algorithms: + - snps,rx-sched-sp: Strict priority + - snps,rx-sched-wsp: Weighted Strict priority + - For each RX queue + - Choose one of these modes: + - snps,dcb-algorithm: Queue to be enabled as DCB + - snps,avb-algorithm: Queue to be enabled as AVB + - snps,map-to-dma-channel: Channel to map + - Specifiy specific packet routing: + - snps,route-avcp: AV Untagged Control packets + - snps,route-ptp: PTP Packets + - snps,route-dcbcp: DCB Control Packets + - snps,route-up: Untagged Packets + - snps,route-multi-broad: Multicast & Broadcast Packets + - snps,priority: RX queue priority (Range: 0x0 to 0xF) +- Multiple TX Queues parameters: below the list of all the parameters to + configure the multiple TX queues: + - snps,tx-queues-to-use: number of TX queues to be used in the driver + - Choose one of these TX scheduling algorithms: + - snps,tx-sched-wrr: Weighted Round Robin + - snps,tx-sched-wfq: Weighted Fair Queuing + - snps,tx-sched-dwrr: Deficit Weighted Round Robin + - snps,tx-sched-sp: Strict priority + - For each TX queue + - snps,weight: TX queue weight (if using a DCB weight algorithm) + - Choose one of these modes: + - snps,dcb-algorithm: TX queue will be working in DCB + - snps,avb-algorithm: TX queue will be working in AVB + [Attention] Queue 0 is reserved for legacy traffic + and so no AVB is available in this queue. + - Configure Credit Base Shaper (if AVB Mode selected): + - snps,send_slope: enable Low Power Interface + - snps,idle_slope: unlock on WoL + - snps,high_credit: max write outstanding req. limit + - snps,low_credit: max read outstanding req. limit + - snps,priority: TX queue priority (Range: 0x0 to 0xF) +Examples: + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + + queue1 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + snps,priority = <0x1>; + }; + }; + + gmac0: ethernet@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupt-parent = <&vic1>; + interrupts = <24 23 22>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + max-frame-size = <3800>; + phy-mode = "gmii"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + clocks = <&clock>; + clock-names = "stmmaceth"; + snps,axi-config = <&stmmac_axi_setup>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@0 { + }; + }; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + }; From 28fac9499fa50e4236006bda6a6a94e3cc2ab7fd Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Wed, 24 Feb 2021 17:37:46 +0530 Subject: [PATCH 0967/1809] ARM: dts: msm: STMMAC Add doc for EMAC node Add EMAC node documentation. Change-Id: I38e0f580ac5b50f4dfbe2aeb41815eb142ff1453 --- bindings/net/qcom,emac-dwc-eqos.txt | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 bindings/net/qcom,emac-dwc-eqos.txt diff --git a/bindings/net/qcom,emac-dwc-eqos.txt b/bindings/net/qcom,emac-dwc-eqos.txt new file mode 100644 index 000000000000..9762c8440e07 --- /dev/null +++ b/bindings/net/qcom,emac-dwc-eqos.txt @@ -0,0 +1,90 @@ +Qualcomm Technologies Inc. EMAC Gigabit Ethernet controller + +This network controller consists of the MAC and +RGMII IO Macro for interfacing with PHY. + +Required properties: + +emac_hw node: +- compatible: Should be "qcom,emac-dwc-eqos" +- reg: Offset and length of the register regions for the mac and io-macro +- interrupts: Interrupt number used by this controller +- io-macro-info: Internal io-macro-info +- emac_emb_smmu: Internal emac smmu node +- qcom,phy-reset-delay-msecs is for delays + The 1st cell is reset pulse in milli seconds. + The 2nd cell is reset post-delay in milli seconds. + +Optional: +- qcom,msm-bus,name: String representing the client-name +- qcom,msm-bus,num-cases: Total number of usecases +- qcom,msm-bus,num-paths: Total number of master-slave pairs +- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing: + master-id, slave-id, arbitrated bandwidth + in KBps, instantaneous bandwidth in KBps +qcom,bus-vector-names: specifies string IDs for the corresponding bus vectors + in the same order as qcom,msm-bus,vectors-KBps property. +- qcom,arm-smmu: Boolean, if present enables EMAC SMMU support in sdxpoorwills. + +Internal io-macro-info: +- io-macro-bypass-mode: <0 or 1> internal or external delay configuration +- io-interface: PHY interface used + +Internal emac_emb_smmu: +- compatible: Should be "qcom,emac-smmu-embedded". +- qcom,smmu-s1-bypass: Boolean, if present S1 bypass is enabled. +- iommus: Includes the <&smmu_phandle stream_id size> pair for each context + bank. +- qcom,iova-mapping: of the smmu context bank. + +Example: + +soc { + emac_hw: qcom,emac@00020000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>; + <0x3D00000 0x300000>; + reg-names = "emac-base", "rgmii-base"; + interrupts = <0 62 4>, <0 60 4>, + <0 49 4>, <0 50 4>, + <0 51 4>, <0 52 4>, + <0 53 4>, <0 54 4>, + <0 55 4>, <0 56 4>, + <0 57 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "10", "100", "1000"; + clock-names = "emac_axi_clk", "emac_ptp_clk", + "emac_rgmii_clk", "emac_slv_ahb_clk"; + qcom,phy-reset = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + qcom,phy-reset-delay-msecs = <10 50>; + gdsc_emac-supply = <&emac_gdsc>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x3C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; +} From 3d0293056f81f2464379e52dcd41d85a5ce0994d Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 25 Feb 2021 12:15:07 +0530 Subject: [PATCH 0968/1809] ARM: dts: msm: Base device tree of SA6155 GVM Add base device tree of Sa6155 guest. Change-Id: I22ca9e59e8a4ddb2ae0a891814739eef4491aae5 --- qcom/Makefile | 3 +- qcom/sa6155p-vm-la.dts | 11 + qcom/sa6155p-vm-la.dtsi | 35 ++++ qcom/sa6155p-vm-pcie.dtsi | 249 +++++++++++++++++++++++ qcom/sa6155p-vm-usb.dtsi | 412 ++++++++++++++++++++++++++++++++++++++ qcom/sa6155p-vm.dtsi | 327 ++++++++++++++++++++++++++++++ 6 files changed, 1036 insertions(+), 1 deletion(-) create mode 100644 qcom/sa6155p-vm-la.dts create mode 100644 qcom/sa6155p-vm-la.dtsi create mode 100644 qcom/sa6155p-vm-pcie.dtsi create mode 100644 qcom/sa6155p-vm-usb.dtsi create mode 100644 qcom/sa6155p-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index c4fca42071c6..f99706b3ea28 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -346,7 +346,8 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8195-vm-lv.dtb \ sa8195-vm-la-mt.dtb \ sa8195-vm-lv-mt.dtb \ - sa8195-vm-lv-lxc.dtb + sa8195-vm-lv-lxc.dtb \ + sa6155p-vm-la.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/qcom/sa6155p-vm-la.dts b/qcom/sa6155p-vm-la.dts new file mode 100644 index 000000000000..f8c2d8176bab --- /dev/null +++ b/qcom/sa6155p-vm-la.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa6155p-vm.dtsi" +#include "sa6155p-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + compatible = "qcom,sa6155p"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/sa6155p-vm-la.dtsi b/qcom/sa6155p-vm-la.dtsi new file mode 100644 index 000000000000..96e830bab203 --- /dev/null +++ b/qcom/sa6155p-vm-la.dtsi @@ -0,0 +1,35 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a1600000 { + reg = <0x0 0xa1600000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; + +}; + +&usb0 { + status = "ok"; +}; + +&qusb_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa6155p-vm-pcie.dtsi b/qcom/sa6155p-vm-pcie.dtsi new file mode 100644 index 000000000000..406b50e5a14f --- /dev/null +++ b/qcom/sa6155p-vm-pcie.dtsi @@ -0,0 +1,249 @@ +#include +#include + +&soc { + pcie0: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 101 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&L12A>; + vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0p9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = ; + + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + msi-parent = <&pcie0_msi>; + + qcom,max-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,core-preset = <0x77777777>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + status = "disabled"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:010a"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + }; +}; diff --git a/qcom/sa6155p-vm-usb.dtsi b/qcom/sa6155p-vm-usb.dtsi new file mode 100644 index 000000000000..9fc20ab70033 --- /dev/null +++ b/qcom/sa6155p-vm-usb.dtsi @@ -0,0 +1,412 @@ +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "bypass"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <61>; + + qcom,ignore-wakeup-src-in-hostmode; + + + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + usbbam: qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + status = "disabled"; + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e2000 0x180>, + <0x01fcb250 0x4>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x88e6000 0x1000>, + <0x01fcb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&L5A>; + core-supply = <&L12A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x70 0x0f 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x194 0x06 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x564 0x00 0x00 + 0x964 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + status = "disabled"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x172f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: hsusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb20_sec_gdsc>; + clocks = <&gcc GCC_USB20_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB20_SEC_SLEEP_CLK>, + <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupts = ; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + qusb_phy1: qusb@88e3000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e3000 0x180>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + qcom,hold-reset; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + +}; + + + diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi new file mode 100644 index 000000000000..e00c1fdc6f3d --- /dev/null +++ b/qcom/sa6155p-vm.dtsi @@ -0,0 +1,327 @@ +#include +#include +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + qcom,msm-name = "SA6155P"; + qcom,msm-id = <377 0x0>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <347>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <347>; + }; + + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x4>; + capacity-dmips-mhz = <347>; + }; + + CPU5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x5>; + capacity-dmips-mhz = <347>; + }; + + CPU6: cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x6>; + capacity-dmips-mhz = <347>; + }; + + CPU7: cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x7>; + capacity-dmips-mhz = <347>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + + core2 { + cpu = <&CPU4>; + }; + + core3 { + cpu = <&CPU5>; + }; + + core4 { + cpu = <&CPU6>; + }; + + core5 { + cpu = <&CPU7>; + }; + }; + }; + }; +}; + + +&soc { + VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL: + pm6155_1_s2_level: regulator-pm6155-1-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_s2_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm6150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 1>, <8 488 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; +}; + +®ulator { + usb30_prim_gdsc: usb30_prim_gdsc { + regulator-name = "usb30_prim_gdsc"; + }; + + usb20_sec_gdsc: usb20_sec_gdsc { + regulator-name = "usb20_sec_gdsc"; + }; + + pcie_0_gdsc: pcie_0_gdsc { + regulator-name = "pcie_0_gdsc"; + }; + + L2A: pm6155_1_l2: regulator-pm6155-1-l2 { + regulator-name = "ldoa2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + }; + + L5A: pm6155_1_l5: regulator-pm6155-1-l5 { + regulator-name = "ldoa5"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + L10A: pm6155_1_l10: regulator-pm6155-1-l10 { + regulator-name = "ldoa10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + }; + + L12A: pm6155_1_l12: regulator-pm6155-1-l12 { + regulator-name = "ldoa12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + }; + + L13A: pm6155_1_l13: regulator-pm6155-1-l13 { + regulator-name = "ldoa13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + }; + + S6A: pm6155_1_s6: regulator-pm6155-1-s6 { + regulator-name = "smpa6"; + regulator-min-microvolt = <947000>; + regulator-max-microvolt = <1404000>; + }; + + S5A: pm6155_1_s5: regulator-pm6155-1-s5 { + regulator-name = "smpa5"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + }; + + L15A: pm6155_1_l15: regulator-pm6155-1-l15 { + regulator-name = "ldoa15"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <1904000>; + }; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + +#include "sm6150-pinctrl.dtsi" +#include "sa6155p-vm-usb.dtsi" +#include "sa6155p-vm-pcie.dtsi" +#include "sm6150-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + From 1e7a5aa3007782ddaa715a503c869e6761d6cb57 Mon Sep 17 00:00:00 2001 From: Fei Tong Date: Thu, 25 Feb 2021 17:41:00 +0800 Subject: [PATCH 0969/1809] ARM: dts: msm: use se22 spi alias instead of se2 Add se22 spi alias instead of se2 for audio codec spi node Change-Id: I4c8d9862e025bf78516867d9e8a6852482b8b59c --- qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 4fb77db22428..bda5282dd6ab 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -40,7 +40,7 @@ pci-domain1 = &pcie1; /* PCIe1 domain */ serial0 = &qupv3_se12_2uart; hsuart0 = &qupv3_se13_4uart; - spi2 = &qupv3_se22_spi; + spi22 = &qupv3_se22_spi; }; cpus { From 70f4f7771c963126d61cdc5141e54d7429f99940 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 25 Feb 2021 09:37:11 +0530 Subject: [PATCH 0970/1809] ARM: dts: msm: Add base DT for smb1390 nodes Add base DT for smb1390 support. Change-Id: If6af064937de64418f064fdb92ad33ee4e5e3ac4 --- qcom/smb1390.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 qcom/smb1390.dtsi diff --git a/qcom/smb1390.dtsi b/qcom/smb1390.dtsi new file mode 100644 index 000000000000..a273f89cf555 --- /dev/null +++ b/qcom/smb1390.dtsi @@ -0,0 +1,56 @@ +#include + +smb1390: qcom,smb1390@10 { + compatible = "qcom,i2c-pmic"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1390"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + #io-channel-cells = <1>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "tsd-fault", + "irev-fault", + "vph-ov-hard", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; + }; +}; + +smb1390_slave: qcom,smb1390_slave@18 { + compatible = "qcom,i2c-pmic"; + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_slave_charger: qcom,charge_pump_slave { + compatible = "qcom,smb1390-slave"; + #io-channel-cells = <1>; + status = "disabled"; + }; +}; From 78ec4c1f837d79d835d0a5aa71092f9c31ae3e54 Mon Sep 17 00:00:00 2001 From: raghavendar rao l Date: Tue, 16 Feb 2021 11:47:16 +0530 Subject: [PATCH 0971/1809] ARM: dts: msm: Add IPA device configuration for SA8195 Add IPA dtsi configurations for SA8195 target. Change-Id: I2ad36f3857ff72255a079b25977e08fdc3c31ca4 --- qcom/sa8195-vm-la.dtsi | 112 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 6be2d077d42d..7527d5a4b602 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -3,6 +3,17 @@ reg = <0x0 0xa0000000 0x0 0x20000000>; label = "pmem_shared_mem"; }; + + pil_ipa_fw_mem: pil_ipa_fw_region { + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region { + no-map; + reg = <0x0 0x98710000 0x0 0x7000>; + }; + }; / { @@ -40,3 +51,104 @@ &sdhc_2 { status = "ok"; }; +&soc { + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x28000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = + , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <15>; /* IPA core version = IPAv4.1 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <2>; /* APQ platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,use-ipa-pm; + qcom,ipa-config-is-auto; + qcom,bandwidth-vote-for-ipa; + qcom,ipa-wdi3-over-gsi; + qcom,manual-fw-load; + qcom,lan-rx-napi; + qcom,tx-wrapper-cache-max-size = <400>; + qcom,tx-napi; + qcom,max_num_smmu_cb = <3>; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <0>; + interconnects = <>; + /* No vote */ + qcom,no-vote = <>; + + /* SVS2 */ + qcom,svs2 = <>; + + /* SVS */ + qcom,svs = <>; + + /* NOMINAL */ + qcom,nominal = <>; + + /* TURBO */ + qcom,turbo = <>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x520 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x521 0x0>; + qcom,iommu-dma = "atomic"; + qcom,additional-mapping = + /* ipa-uc ram */ + <0x1E60000 0x1E60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x522 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x40400000 0x1FC00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_gsi_mem>; + }; + + qcom,ipa_uc { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0x1B>; + qcom,firmware-name = "ipa_uc"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + +}; From c371e02e69e73b3d77eb5e6ececdbe53f052662a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 25 Feb 2021 23:16:57 +0530 Subject: [PATCH 0972/1809] ARM: dts: msm: Enable the PCIE GDSC for YUPIK IOT Enable the pcie gdscs for consumers to be able to request for the same. Change-Id: I54fa6ae5971bf0a74ad3537e916cb78c07ccb227 --- qcom/yupik-iot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi index d34b46f1c80a..5667de65803a 100644 --- a/qcom/yupik-iot.dtsi +++ b/qcom/yupik-iot.dtsi @@ -16,3 +16,11 @@ /delete-property/ protected-clocks; }; + +&gcc_pcie_0_gdsc { + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + status = "ok"; +}; From e018deac06537395068a25d82158aa962883261d Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 26 Feb 2021 09:39:15 +0800 Subject: [PATCH 0973/1809] ARM: dts: msm: set qupv3 se15 i2c rate to 100khz Since it was used only for dsi-hdmi bridge chipset, the chipset could not support higher rate, so set it to 100khz. Change-Id: Ieeede3aabb0698270bf0d9eec920c787c11ecf83 --- qcom/lahaina-hdk.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 1302ac8c52d3..e0c3d0395416 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -85,7 +85,9 @@ &qupv3_se15_i2c { status = "ok"; - + qcom,clk-freq-out = <100000>; + #address-cells = <1>; + #size-cells = <0>; lt9611: lt,lt9611@2b { compatible = "lt,lt9611uxc"; reg = <0x2b>; From 961d91c4947ccb55a2858a48190e7ffe8511d9ab Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Tue, 23 Feb 2021 11:32:38 +0530 Subject: [PATCH 0974/1809] dt-bindings: msm: rpmh-master-stats: Update reg as optional property This change updates reg as optional property so that same driver can be used for RPM based targets where profiling unit register is not present. This enables rpmh_master_stats driver to read different subsystem master stats data from SMEM for RPM based targets. Change-Id: Ib5ccfd5d688fe0f8d69dbdb9c9408ce8970eb576 --- bindings/arm/msm/rpmh-master-stats.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/rpmh-master-stats.txt b/bindings/arm/msm/rpmh-master-stats.txt index 6ec06cb8db40..07a3838ac86c 100644 --- a/bindings/arm/msm/rpmh-master-stats.txt +++ b/bindings/arm/msm/rpmh-master-stats.txt @@ -11,6 +11,10 @@ Additionally, RPMH master stats also maintains application processor's master stats. It uses profiling units to calculate power down and power up stats. +Same driver can be used for RPM based targets where Different Subsystems master +stats data can be read from SMEM. Such targets do not have profiling unit +register. + The required properties for rpmh-master-stats are: - compatible: @@ -19,7 +23,7 @@ The required properties for rpmh-master-stats are: Definition: Should be "qcom,rpmh-master-stats-v1". - reg: - Usage: required + Usage: optional Value type: Definition: Specifies physical address of start of profiling unit. From 9894322b1d97d7641e9055ee31883b7edea5e2e2 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Fri, 5 Feb 2021 15:44:05 +0530 Subject: [PATCH 0975/1809] ARM: dts: msm: Enable rpmh_master_stats to read master stats for holi This change adds support to read master stats for rpm based target. Change-Id: I2a3dadb7d85ae657a9ec5d06d71bcdda27163845 --- qcom/holi-pm.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi-pm.dtsi b/qcom/holi-pm.dtsi index 1beb1fb123fd..1c5ea74bea5f 100644 --- a/qcom/holi-pm.dtsi +++ b/qcom/holi-pm.dtsi @@ -153,6 +153,10 @@ reg = <0x04690000 0x400>; }; + rpmh-master-stats { + compatible = "qcom,rpmh-master-stats-v1"; + }; + qcom,rpm-master-stats@45f0150 { compatible = "qcom,rpm-master-stats"; reg = <0x45f0150 0x5000>; From 65b274d4e021408469fe20a3f3e39f950c152ca2 Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Fri, 26 Feb 2021 13:32:21 +0800 Subject: [PATCH 0976/1809] ARM: dts: msm: Add secure buffer device for sdxnightjar Allow clients to create secure memory. Change-Id: I0318dc4dee605fbe968df70d3b9e3e92ce11a645 --- qcom/sdxnightjar.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 5cc3ffd86cbc..deaab04b4b42 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -502,6 +502,10 @@ qcom,pipe-attr-ee; }; + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; From 8f429c4526752a12045de81c988153537dc62719 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Thu, 24 Sep 2020 16:33:58 +0530 Subject: [PATCH 0977/1809] ARM: dts: msm: STMMAC changes for SA8195 Add support for STMMAC in SA8195 dts. Change-Id: Idd79ff6b9eeb0e10dbf6550a8d44f546ed700585 --- qcom/sa8195p-adp-common.dtsi | 136 +++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 46f9f966e902..1978f4be2810 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,4 +1,5 @@ #include +#include &qupv3_3 { status = "ok"; @@ -47,4 +48,139 @@ qcom,npu@9800000 { status = "ok"; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + }; + + ethqos_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos"; + qcom,arm-smmu; + emac-core-version = <0x20010001>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "stmmaceth", "rgmii","tlmm-central-base"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + interrupts-extended = <&intc 0 689 4>, <&intc 0 700 4>, + <&tlmm 124 2>; + interrupt-names = "macirq", "eth_lpi", + "phy-intr"; + + snps,tso; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + snps,reset-delays-us = <0 11000 70000>; + phy-mode = "rgmii"; + ethqos_emb_smmu: ethqos_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x7C0 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; }; From c902c442f1af4776bdf94afc4445522b3edb3075 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Tue, 14 Jul 2020 15:03:25 +0530 Subject: [PATCH 0978/1809] ARM: dts: msm: STMMAC changes for SA8155 LV Add support for STMMAC in SA8155 dts. Change-Id: I68855a9bb8492abdf366e07959c398534b28788e --- qcom/sa8155-v2.dtsi | 4 ++ qcom/sa8155.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++ qcom/sm8150-pinctrl.dtsi | 28 +++++++------- 3 files changed, 100 insertions(+), 14 deletions(-) diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index bb97a5bc3ec3..70cfeff90489 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -342,3 +342,7 @@ &camcc { compatible = "qcom,sa8155-camcc-v2", "syscon"; }; + +ðqos_hw { + emac-core-version = <0x20010002>; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index a64466f5e6ad..7bab1ef03a9e 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -62,6 +62,88 @@ read-only; ranges; }; + ethqos_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "stmmaceth", "rgmii","tlmm-central-base"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + interrupts-extended = <&intc 0 689 4>, <&intc 0 699 4>, + <&tlmm 124 2>; + interrupt-names = "macirq", "eth_lpi", + "phy-intr"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + snps,reset-delays-us = <0 11000 70000>; + phy-mode = "rgmii"; + + ethqos_emb_smmu: ethqos_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x3C0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; + }; &usb2_phy0 { diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index 56c504fcab24..33a90ce5e00e 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -4802,7 +4802,7 @@ emac_mdc: emac_mdc { mux { pins = "gpio7"; - function = "rgmii_mdc"; + function = "rgmii"; }; config { @@ -4814,7 +4814,7 @@ emac_mdio: emac_mdio { mux { pins = "gpio59"; - function = "rgmii_mdio"; + function = "rgmii"; }; config { @@ -4826,7 +4826,7 @@ emac_rgmii_txd0: emac_rgmii_txd0 { mux { pins = "gpio122"; - function = "rgmii_txd0"; + function = "rgmii"; }; config { @@ -4839,7 +4839,7 @@ emac_rgmii_txd1: emac_rgmii_txd1 { mux { pins = "gpio4"; - function = "rgmii_txd1"; + function = "rgmii"; }; config { @@ -4852,7 +4852,7 @@ emac_rgmii_txd2: emac_rgmii_txd2 { mux { pins = "gpio5"; - function = "rgmii_txd2"; + function = "rgmii"; }; config { @@ -4865,7 +4865,7 @@ emac_rgmii_txd3: emac_rgmii_txd3 { mux { pins = "gpio6"; - function = "rgmii_txd3"; + function = "rgmii"; }; config { @@ -4878,7 +4878,7 @@ emac_rgmii_txc: emac_rgmii_txc { mux { pins = "gpio114"; - function = "rgmii_txc"; + function = "rgmii"; }; config { @@ -4891,7 +4891,7 @@ emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { mux { pins = "gpio121"; - function = "rgmii_tx"; + function = "rgmii"; }; config { @@ -4905,7 +4905,7 @@ emac_rgmii_rxd0: emac_rgmii_rxd0 { mux { pins = "gpio117"; - function = "rgmii_rxd0"; + function = "rgmii"; }; config { @@ -4918,7 +4918,7 @@ emac_rgmii_rxd1: emac_rgmii_rxd1 { mux { pins = "gpio118"; - function = "rgmii_rxd1"; + function = "rgmii"; }; config { @@ -4931,7 +4931,7 @@ emac_rgmii_rxd2: emac_rgmii_rxd2 { mux { pins = "gpio119"; - function = "rgmii_rxd2"; + function = "rgmii"; }; config { @@ -4944,7 +4944,7 @@ emac_rgmii_rxd3: emac_rgmii_rxd3 { mux { pins = "gpio120"; - function = "rgmii_rxd3"; + function = "rgmii"; }; config { @@ -4957,7 +4957,7 @@ emac_rgmii_rxc: emac_rgmii_rxc { mux { pins = "gpio115"; - function = "rgmii_rxc"; + function = "rgmii"; }; config { @@ -4970,7 +4970,7 @@ emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { mux { pins = "gpio116"; - function = "rgmii_rx"; + function = "rgmii"; }; config { From 148a0b5161d0356f04a381c6b789a3db8113c82d Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Tue, 29 Dec 2020 15:16:05 +0530 Subject: [PATCH 0979/1809] ARM: dts: msm: STMMAC changes for SA6155 Add support for STMMAC in SA6155 dts. Change-Id: I544772d7ca02aa78dfd80915f127ea17b6838068 --- qcom/sa6155-adp-common.dtsi | 136 ++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index 3d5709476521..1b00deb39e43 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -1,4 +1,5 @@ #include +#include &qupv3_se0_2uart { status = "ok"; @@ -16,4 +17,139 @@ qcom,turing@8300000 { status = "ok"; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + }; + + ethqos_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos"; + qcom,arm-smmu; + emac-core-version = <0x20030001>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "stmmaceth", "rgmii","tlmm-central-base"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + interrupts-extended = <&intc 0 660 4>, <&intc 0 700 4>, + <&tlmm 121 2>; + interrupt-names = "macirq", "eth_lpi", + "phy-intr"; + + snps,tso; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,reset-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 121 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + snps,reset-delays-us = <0 11000 70000>; + phy-mode = "rgmii"; + ethqos_emb_smmu: ethqos_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; }; From 0c3613d1074f2cd0c251f760bf52ec54d873f9c2 Mon Sep 17 00:00:00 2001 From: Xiaoning Ma Date: Tue, 23 Feb 2021 15:41:27 +0800 Subject: [PATCH 0980/1809] ARM: dts: msm: add bt power node for sa81x5 add bt power node for sa81x5 and add new bt compatible string for automotive BT SoCS QCA6574/QCA6595/QCA6696. Change-Id: I015e1ab6e6ed2f8ec5ee9c1a659bd351aa7cdad3 --- bindings/bluetooth/btpower.txt | 1 + qcom/sa8155-adp-common.dtsi | 1 + qcom/sa8155-cnss.dtsi | 52 ++++++++++++++++++++++++++++++++++ qcom/sa8195p-adp-common.dtsi | 2 ++ qcom/sa8195p-cnss.dtsi | 50 ++++++++++++++++++++++++++++++++ qcom/sa8195p.dtsi | 3 ++ 6 files changed, 109 insertions(+) create mode 100644 qcom/sa8155-cnss.dtsi create mode 100644 qcom/sa8195p-cnss.dtsi diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 529d764c6da9..648f3a4cf512 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -11,6 +11,7 @@ Required properties: qcom,qca6390 qcom,qca6490 qcom,wcn6750-bt + qcom,qca-auto-converged - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index d7156a1f25f0..544919ee0573 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -2,6 +2,7 @@ #include #include "sa8155-pmic-overlay.dtsi" +#include "sa8155-cnss.dtsi" &qupv3_3 { status = "ok"; diff --git a/qcom/sa8155-cnss.dtsi b/qcom/sa8155-cnss.dtsi new file mode 100644 index 000000000000..c6189b4e6c29 --- /dev/null +++ b/qcom/sa8155-cnss.dtsi @@ -0,0 +1,52 @@ + +&soc { + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pm8150_1_s6>; + qcom,bt-vdd-rfa1-supply = <&pm8150_2_s4>; + qcom,bt-vdd-rfa2-supply = <&pm8150_2_s5>; + qcom,bt-vdd-rfa3-supply = <&pm8150_2_l15>; + + /* */ + qcom,bt-vdd-aon-config = <1055000 1055000 0 0>; + qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; + }; + +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 46f9f966e902..a2e060eacbf6 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1,7 @@ #include +#include "sa8195p-cnss.dtsi" + &qupv3_3 { status = "ok"; }; diff --git a/qcom/sa8195p-cnss.dtsi b/qcom/sa8195p-cnss.dtsi new file mode 100644 index 000000000000..9739eeb3f339 --- /dev/null +++ b/qcom/sa8195p-cnss.dtsi @@ -0,0 +1,50 @@ + +&soc { + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + + bluetooth_ext: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pm8195_1_s5>; + qcom,bt-vdd-rfa1-supply = <&pm8195_1_s2>; + qcom,bt-vdd-rfa2-supply = <&pm8195_2_l7>; + + /* */ + qcom,bt-vdd-aon-config = <1000000 1000000 0 0>; + qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>; + qcom,bt-vdd-rfa2-config = <1900000 1900000 450000 0>; + }; + +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 3c30056eee9f..13616c51d925 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -8,6 +8,9 @@ model = "Qualcomm Technologies, Inc. SA8195P"; qcom,msm-name = "SA8195P"; qcom,msm-id = <405 0x20000>; + aliases { + hsuart0 = &qupv3_se13_4uart; + }; }; &soc { From 3b2249f3cc878713e3f601272bdaa44d35287593 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 12:52:29 +0530 Subject: [PATCH 0981/1809] ARM: dts: msm: Add DPC property for SM8150 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I9cc9f97116b5aa9cdf9f3b6e250b30a170db910c --- qcom/sm8150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 012119a96c3a..5bde3d947bf8 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -54,6 +54,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { @@ -75,6 +76,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_1: l2-cache { @@ -91,6 +93,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_2: l2-cache { @@ -107,6 +110,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_3: l2-cache { @@ -123,6 +127,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_4: l2-cache { @@ -139,6 +144,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_5: l2-cache { @@ -155,6 +161,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_6: l2-cache { @@ -171,6 +178,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; L2_7: l2-cache { From 341d78c97813219a1482bf38536f80a10740f3d3 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 13:17:54 +0530 Subject: [PATCH 0982/1809] ARM: dts: msm: Add DPC property for SA8195 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I56f0f7bd6a623dcfd2cbf2dca370681011aa876b --- qcom/sdmshrike.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index b4ba25a47ad4..203300f196d1 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -50,6 +50,7 @@ reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -74,6 +75,7 @@ reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -92,6 +94,7 @@ reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -110,6 +113,7 @@ reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; @@ -128,6 +132,7 @@ reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -146,6 +151,7 @@ reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -164,6 +170,7 @@ reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; @@ -182,6 +189,7 @@ reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; cache-size = <0x20000>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 1 4>; From 704b584258466bfb46b29cef710a8f0cc3f82795 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 13:20:26 +0530 Subject: [PATCH 0983/1809] ARM: dts: msm: Add DPC property for SM6150 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: Ieed91b03a482e3e23af6b63656bb52245f149379 --- qcom/sm6150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index d13d12a975e5..fea0881c7a01 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -49,6 +49,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -74,6 +75,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -94,6 +96,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -113,6 +116,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -132,6 +136,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -151,6 +156,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0 6>; @@ -170,6 +176,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1 2>; @@ -189,6 +196,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1 2>; From cda6c2ddfa88a5a316456d9d8ad8f4ae6d703054 Mon Sep 17 00:00:00 2001 From: Gaurav Singh Date: Tue, 23 Feb 2021 13:47:09 +0530 Subject: [PATCH 0984/1809] ARM: dts: msm: enable scmi plh protocol Enable SCMI PLH protocol to allow communication with CPUCP PLH module. Change-Id: If0f829ee781964a41dc0ad9127c79319e523b380 --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c3a18758774..31e4bdb26dc3 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2048,6 +2048,11 @@ reg = <0x80>; #clock-cells = <1>; }; + + scmi_perf_lock: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; }; rimps_log: qcom,rimps_log@18509C00 { From 3c771d72f2ef7be7a4e867398cb56769ba080884 Mon Sep 17 00:00:00 2001 From: Sandeep Sadula Date: Fri, 26 Feb 2021 17:51:13 +0530 Subject: [PATCH 0985/1809] ARM: dts: msm: Removing appsbl-qseecom-support appsbl-qseecom-support is removed to allow TZ APP region Notification from kernel level. Change-Id: Ia1e1730d15c3d9b58becdc0c27d64e80b4e293cb --- qcom/sdxnightjar.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index deaab04b4b42..91d8df73c135 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -590,7 +590,6 @@ qcom,qsee-ce-hw-instance = <0>; qcom,qsee-reentrancy-support = <2>; qcom,support-bus-scaling; - qcom,appsbl-qseecom-support; interconnect-names = "data_path"; interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>; /*TODO: Fix the clock when tree is available*/ From 123b22b45c7d10f3f95fb129cf2e37d3b3d4a156 Mon Sep 17 00:00:00 2001 From: Zhiqiang Liu Date: Wed, 4 Nov 2020 14:39:36 +0800 Subject: [PATCH 0986/1809] ARM: dts: msm: include sa6155 display devicetree Include display devicetree for sa6155. Change-Id: I3221165dc883bd5731b67dc892a34fd21850f23e --- qcom/sa6155-pmic.dtsi | 14 ++++++++++++++ qcom/sa6155.dtsi | 5 +++++ qcom/sa6155p-adp-air-overlay.dts | 1 + qcom/sa6155p-adp-star-overlay.dts | 1 + qcom/sa6155p-v2-adp-air-overlay.dts | 1 + qcom/sa6155p-v2-adp-star-overlay.dts | 1 + qcom/sa6155p.dtsi | 5 +++++ qcom/sm6150.dtsi | 3 +++ 8 files changed, 31 insertions(+) diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index 313bd701ba65..c777340b5c4b 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -47,3 +47,17 @@ #include "sa6155-regulator.dtsi" #include "pm6155.dtsi" + +&mdss_dsi0 { + vdda-1p2-supply = <&pm6155_1_l11>; +}; + +&sde_dp { + vdda-1p2-supply = <&pm6155_1_l11>; + vdda-0p9-supply = <&pm6155_1_l5>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm6155_1_l5>; +}; + diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index c198dd260d2a..8f5b05cc8966 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -1,5 +1,6 @@ #include "sm6150.dtsi" #include "sa6155-pmic.dtsi" +#include "display/sa6155-display.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155"; @@ -399,3 +400,7 @@ }; }; }; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; diff --git a/qcom/sa6155p-adp-air-overlay.dts b/qcom/sa6155p-adp-air-overlay.dts index c584ca4a7946..b0e01173deb5 100644 --- a/qcom/sa6155p-adp-air-overlay.dts +++ b/qcom/sa6155p-adp-air-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa6155-adp-air.dtsi" +#include "display/sa6155-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; diff --git a/qcom/sa6155p-adp-star-overlay.dts b/qcom/sa6155p-adp-star-overlay.dts index 0a49f5baca76..427ebe285044 100644 --- a/qcom/sa6155p-adp-star-overlay.dts +++ b/qcom/sa6155p-adp-star-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa6155-adp-star.dtsi" +#include "display/sa6155-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; diff --git a/qcom/sa6155p-v2-adp-air-overlay.dts b/qcom/sa6155p-v2-adp-air-overlay.dts index c86c51cf35ae..9adb8cbe640b 100644 --- a/qcom/sa6155p-v2-adp-air-overlay.dts +++ b/qcom/sa6155p-v2-adp-air-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa6155-adp-air.dtsi" +#include "display/sa6155-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; diff --git a/qcom/sa6155p-v2-adp-star-overlay.dts b/qcom/sa6155p-v2-adp-star-overlay.dts index 238de97a680d..f566d21dc5a3 100644 --- a/qcom/sa6155p-v2-adp-star-overlay.dts +++ b/qcom/sa6155p-v2-adp-star-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "sa6155-adp-star.dtsi" +#include "display/sa6155-display-shd.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 0a609bc0c3e3..f4d21e3b21d7 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -1,5 +1,6 @@ #include "sm6150.dtsi" #include "sa6155-pmic.dtsi" +#include "display/sa6155-display.dtsi" / { model = "Qualcomm Technologies, Inc. SA6155P"; @@ -417,3 +418,7 @@ }; }; }; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index d13d12a975e5..2b52cd9f9d4e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -454,6 +454,9 @@ }; +#include "display/sm6150-sde-pll.dtsi" +#include "display/sm6150-sde.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; From 33563d8e207566704752410fb186e0c7a3aeaa73 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sat, 27 Feb 2021 16:35:31 +0530 Subject: [PATCH 0987/1809] dt-bindings: leds: qcom-clk: Add qcom,default-clk-trigger property Add property to configure the default trigger for the LED. This will allow clients to use trigger APIs to configure the brightness of the LED if needed. Change-Id: I44dc751f5057233db1f412c067817c80f2a157b6 --- bindings/leds/leds-qcom-clk.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/leds/leds-qcom-clk.txt b/bindings/leds/leds-qcom-clk.txt index d3e4d95ef646..cf0cc094b728 100644 --- a/bindings/leds/leds-qcom-clk.txt +++ b/bindings/leds/leds-qcom-clk.txt @@ -20,13 +20,15 @@ Required properties: Optional properties: - qcom,label: Label for the sysfs node. - +- qcom,default-clk-trigger: This parameter, if present, is a string + defining the trigger assigned to the LED. Example: qcom_clk_led { compatible = "qcom,clk-led-pwm"; qcom,label = "led_clk_pwm"; + qcom,default-clk-trigger = "led_clk_pwm"; qcom,max_duty = <80>; clocks = <&clock_gcc GCC_GP2_CLK>; clock-names = "core"; From c87aa24d05fae14e47338e65fb4755795dc2c7da Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 24 Feb 2021 16:21:30 +0530 Subject: [PATCH 0988/1809] bindings: arm: msm: Add documentation for subsystem sleep_stats_driver This change adds bindings for subsystem_sleep_stats driver. Change-Id: Icf3d32ad8be0541cc6821f8a8c6bf9cf8dea5a0a --- bindings/arm/msm/subsystem-sleep-stats.yaml | 31 +++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 bindings/arm/msm/subsystem-sleep-stats.yaml diff --git a/bindings/arm/msm/subsystem-sleep-stats.yaml b/bindings/arm/msm/subsystem-sleep-stats.yaml new file mode 100644 index 000000000000..53e038718b83 --- /dev/null +++ b/bindings/arm/msm/subsystem-sleep-stats.yaml @@ -0,0 +1,31 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/msm/subsystem-sleep-stats.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The document describes the device tree binding for subsystem-sleep-stats + +maintainers: + - Tushar Nimkar + +description: |+ + Differet Subsystems maintains stats data in SMEM. + It tells about the individual subsystem information at any given + time like system sleep counts, system sleep last entered at + and accumulated duration etc. This drive provide a IOCTL way + to read those stats from respective SMEMs. + +The required properties for subsystem stats driver is: + +properties: + compatible: + Usage: required + Value type: + Definition: Should be "qcom,subsystem-sleep-stats". + + +example: + - | + subsystem-sleep-stats { + compatible = "qcom,subsystem-sleep-stats"; + }; From 109ad3c497c7a0f2dc25b585f47aded738c6a0ff Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 24 Feb 2021 13:59:31 +0530 Subject: [PATCH 0989/1809] ARM: dts: msm: Enable subsystem sleep stats driver for holi This change adds node for subsystem_sleep_stats driver to read stats information from smem. Change-Id: I424e3f6bb3e2b205df16415b761865b844551677 --- qcom/holi-pm.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi-pm.dtsi b/qcom/holi-pm.dtsi index 1c5ea74bea5f..d95b77d896d9 100644 --- a/qcom/holi-pm.dtsi +++ b/qcom/holi-pm.dtsi @@ -157,6 +157,10 @@ compatible = "qcom,rpmh-master-stats-v1"; }; + subsystem-sleep-stats { + compatible = "qcom,subsystem-sleep-stats"; + }; + qcom,rpm-master-stats@45f0150 { compatible = "qcom,rpm-master-stats"; reg = <0x45f0150 0x5000>; From 994dc07f420a829f81f5039d1c7fdd52a4424720 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Fri, 29 Jan 2021 20:45:50 +0530 Subject: [PATCH 0990/1809] ARM: dts: msm: Add l3 endpoints and pwrlevels for yupik gpu Add the l3 endpoints as well as the frequency table to be able to vote for l3 for gpu usecases that need l3 scaling. Change-Id: I48789c3f7b387f7cb2e24f179678307e3516b300 --- qcom/yupik-gpu.dtsi | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index d5e981c7300f..4a7357b398a3 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -46,10 +46,14 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin"; + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; - interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; - interconnect-names = "gpu_icc_path"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>, + <&epss_l3_cpu MASTER_EPSS_L3_APPS &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + interconnect-names = "gpu_icc_path", "l3_path"; qcom,bus-table-ddr7 = , /* index=0 */ @@ -82,8 +86,27 @@ <0>, /* Off */ <100>; /* On */ - nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; - nvmem-cell-names = "speed_bin", "gaming_bin"; + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <614400000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1516800000>; + }; + }; qcom,gpu-mempools { #address-cells = <1>; From 470b7d29fafc6b84e95750222fa4735506c1d73f Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Mon, 1 Mar 2021 13:11:21 +0530 Subject: [PATCH 0991/1809] ARM: dts: msm: Enable SMMU S1 support for eMMC on Yupik Enable SMMU S1 support for eMMC on Yupik with geometry property for memory saving (512MB). Change-Id: I5c37581993a3b885e5d44814fb47abf6f86e8a6c --- qcom/yupik.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a5ea5979c4b1..3c52d9f293d4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2681,7 +2681,9 @@ iommus = <&apps_smmu 0xc0 0x0>; dma-coherent; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>; + qcom,iommu-geometry = <0x40000000 0x20000000>; interrupts = , ; From af6b21775ed7b3f830d804510c5ecfa782d7490f Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Thu, 24 Sep 2020 22:57:06 -0700 Subject: [PATCH 0992/1809] dt-bindings: msm: Add compatbile strings for direwolf Add compatible strings for the direwolf platform, that includes SoC, RUMI, IVI, ADAS, and ADP-STAR entries. Change-Id: I08673d51e5aff755236da2377d34e66b79520377 --- bindings/arm/msm/msm.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 29112ab7ad27..85b2a7958bff 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -107,6 +107,9 @@ SoCs: - SDXNIGHTJAR compatible = "qcom,sdxnightjar" +- DIREWOLF + compatible = "qcom,direwolf" + Generic board variants: - CDP device: @@ -286,3 +289,9 @@ compatible = "qcom,monaco-rumi" compatible = "qcom,sdxnightjar-mtp" compatible = "qcom,sdxnightjar-cdp" compatible = "qcom,sdxnightjar-qrd" +compatible = "qcom,direwolf-ivi" +compatible = "qcom,direwolf-ivi-rumi" +compatible = "qcom,direwolf-ivi-adp-star" +compatible = "qcom,direwolf-adas" +compatible = "qcom,direwolf-adas-rumi" +compatible = "qcom,direwolf-adas-adp-star" From a5d707c3432265450a3e79c0bc4d3bd7c0614bed Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Thu, 22 Oct 2020 12:03:08 +0800 Subject: [PATCH 0993/1809] ARM: dts: msm: add se10 spi alias for sa6155 auto platform Add spi-msm-codec-slave device as a subnode of spi se10 node on sa6155 platform. Change-Id: I22d6aa9b1de15869b824c598c6f02cbb932e35b7 --- qcom/sm6150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 5e8fdc9c0bcd..935c44cbcc3e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -36,6 +36,7 @@ serial0 = &qupv3_se0_2uart; sdhc0 = &sdhc_1; sdhc1 = &sdhc_2; + spi10 = &qupv3_se10_spi; }; cpus { From 152ce212dd48645ea0b1c9ebeeb0e15e8a74ac19 Mon Sep 17 00:00:00 2001 From: raghavendar rao l Date: Mon, 1 Mar 2021 11:54:53 +0530 Subject: [PATCH 0994/1809] ARM: dts: msm: Disable uC hold monitor Disable uC hold monitor feature for yupik target. Change-Id: Iddfa1bfa652abd85c8fce29590e745a5cdb0bd1b --- qcom/yupik.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 8ebfb94b891b..285434601217 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3695,12 +3695,7 @@ qcom,tx-napi; qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; - qcom,ipa-uc-holb-monitor; qcom,use-gsi-ipa-fw = "yupik_ipa_fws"; - qcom,ipa-holb-monitor-poll-period = <5>; - qcom,ipa-holb-monitor-max-cnt-wlan = <10>; - qcom,ipa-holb-monitor-max-cnt-usb = <10>; - qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; From 550878935fb3c4dabede847b09ae7f39044bd72e Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 1 Mar 2021 15:49:03 +0530 Subject: [PATCH 0995/1809] ARM: dts: qcom: update scaling ratios for SMB_ICHG and SMB_IIN channels Update scaling ratios for SMB_ICHG and SMB_IIN ADC channels on lahaina, shima and yupik, following HW recommendation. Change-Id: Ib1d6e4d4d8a78f02d6c779ce6d70cac0f5eaeed6 --- qcom/lahaina-pmic-overlay.dtsi | 8 ++++---- qcom/shima-pmic-overlay.dtsi | 8 ++++---- qcom/yupik-qrd.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 7146731f2773..43cdb6d6a80a 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -359,13 +359,13 @@ smb139x_1_ichg_smb { reg = ; label = "smb139x_1_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_1_iin_smb { reg = ; label = "smb139x_1_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; smb139x_2_smb_temp { @@ -377,13 +377,13 @@ smb139x_2_ichg_smb { reg = ; label = "smb139x_2_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_2_iin_smb { reg = ; label = "smb139x_2_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; }; diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index 3869c2791578..f9a6b808d651 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -145,7 +145,7 @@ smb139x_1_ichg_smb { reg = ; label = "smb139x_1_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_1_ichg_smb_pt { @@ -157,7 +157,7 @@ smb139x_1_iin_smb { reg = ; label = "smb139x_1_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; smb139x_2_smb_temp { @@ -169,7 +169,7 @@ smb139x_2_ichg_smb { reg = ; label = "smb139x_2_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_2_ichg_smb_pt { @@ -181,7 +181,7 @@ smb139x_2_iin_smb { reg = ; label = "smb139x_2_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; }; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index a32e7e7b4fae..a6e7bdab2c0d 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -172,7 +172,7 @@ smb139x_1_ichg_smb { reg = ; label = "smb139x_1_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_1_ichg_smb_pt { @@ -184,7 +184,7 @@ smb139x_1_iin_smb { reg = ; label = "smb139x_1_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; smb139x_2_smb_temp { @@ -196,7 +196,7 @@ smb139x_2_ichg_smb { reg = ; label = "smb139x_2_ichg_smb"; - qcom,pre-scaling = <14 100>; + qcom,pre-scaling = <16 100>; }; smb139x_2_ichg_smb_pt { @@ -208,7 +208,7 @@ smb139x_2_iin_smb { reg = ; label = "smb139x_2_iin_smb"; - qcom,pre-scaling = <28 100>; + qcom,pre-scaling = <32 100>; }; }; From 5c11d275fd400761a888e27efa4c9808bb034a04 Mon Sep 17 00:00:00 2001 From: rajikuma Date: Thu, 15 Oct 2020 09:39:57 +0530 Subject: [PATCH 0996/1809] ARM: dts: msm: include audio dt files for sa6155p-vm auto platforms Include audio dts file in main dtsi to enable audio feature. Change-Id: I422ed112430d3f613f7f5a1d5cd62c12e4983aeb --- qcom/sa6155p-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index e00c1fdc6f3d..7f553d16dfe2 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -310,6 +310,7 @@ #include "sa6155p-vm-usb.dtsi" #include "sa6155p-vm-pcie.dtsi" #include "sm6150-qupv3.dtsi" +#include "sa8155-vm-audio.dtsi" &tlmm { /delete-property/ wakeup-parent; From 535c258dfdeea28bbb8a88f16c24e4b9ddb49fd8 Mon Sep 17 00:00:00 2001 From: Guodong Hu Date: Thu, 20 Aug 2020 16:12:51 +0800 Subject: [PATCH 0997/1809] ARM: dts: msm: include audio dt files for sa8155-vm auto platforms Include audio dts file in main dtsi to enable audio feature. Change-Id: I6060f2bd25f9af5ca812faf569d216930075523e --- qcom/sa8155-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 5cab1cb3be32..56933993038e 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -394,6 +394,7 @@ #include "sm8150-qupv3.dtsi" #include "sm8150-ssc-qupv3.dtsi" #include "pm8150-vm.dtsi" +#include "sa8155-vm-audio.dtsi" &tlmm { /delete-property/ wakeup-parent; From 86663827416b796ea1102ad79dc8ae367017818c Mon Sep 17 00:00:00 2001 From: rajikuma Date: Mon, 1 Mar 2021 22:29:06 +0530 Subject: [PATCH 0998/1809] ARM: dts: msm: include audio dt files for sa8195-vm auto platforms Include audio dts file in main dtsi to enable audio feature. Change-Id: Iaa3e61959f4281d5bf0f46d4b41aaa8ceb3b0870 --- qcom/sa8195-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index fde9e1516c03..a8210dfbd45c 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -523,6 +523,7 @@ #include "sa8195-vm-pcie.dtsi" #include "sa8195-qupv3.dtsi" #include "sa8195-ssc-qupv3.dtsi" +#include "sa8155-vm-audio.dtsi" &tlmm { /delete-property/ wakeup-parent; From 38fc9612c3ff14ff8228c3339f3a4f025201bf2e Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Mon, 1 Mar 2021 18:07:53 -0800 Subject: [PATCH 0999/1809] ARM: dts: msm: Use separate property for multiple WLAN support qcom,converged-dt is meant to use one DT node which has multiple sub-nodes to support multiple devices. For Lahaina it is a simple scenario that the same DT node can be directly used by multiple devices without creating sub-nodes. Use a separate DT entry qcom,same-dt-multi-dev for such case to simplify implementation and avoid conflicts. Change-Id: If0dd195b8dd41eb4aa978bd86d690e6dbb18118d --- bindings/cnss/cnss-wlan.txt | 5 ++++- qcom/lahaina.dtsi | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index f05e653181c4..bc7df786903c 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -93,8 +93,11 @@ Optional properties: enable to resolve PMU power up issues. Provide BT GPIO using this config param. - qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention. + - qcom,same-dt-multi-dev: Boolean property to decide whether it supports + multiple WLAN devices using the same DT node + without sub-nodes. - qcom,converged-dt: Boolean property to decide whether it supports multiple - WLAN devices. + WLAN devices using the same DT node with sub-nodes. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 6dcd70411e17..9c50d2d9fc3f 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5393,7 +5393,7 @@ qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>; use-pm-domain; cnss-enable-self-recovery; - qcom,converged-dt; + qcom,same-dt-multi-dev; vdd-wlan-aon-supply = <&S2E>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From f494459cd234e73952faf34d50d6f712706784bc Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Thu, 22 Oct 2020 11:58:09 +0800 Subject: [PATCH 1000/1809] ARM: dts: msm: include audio dt files for sa6155 auto platforms Include audio dts file in main dtsi to enable audio feature. Change-Id: I17dc981a5cc2daed357a9bbe1b4fd44e82d1cb6b --- qcom/sa6155p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index f4d21e3b21d7..a45e48a86479 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -422,3 +422,5 @@ &mdss_dsi0_pll { /delete-property/ qcom,dsi-pll-ssc-en; }; + +#include "sa6155-audio.dtsi" From 136174e6a549b8f5cac469453f54efce2d081a5e Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 1 Mar 2021 18:54:16 +0800 Subject: [PATCH 1001/1809] ARM: dts: msm: disable tpdm sdcc on sdxlemur The clk of sdcc tpdm is not able to enable from kernel side, so disable it. Change-Id: Iaf91c8751e351c49ba9cf062bab641383cf303ca --- qcom/sdxlemur-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 1253c39689f5..2455c9fccd20 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -1105,6 +1105,7 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; + status = "disabled"; qcom,cmb-msr-skip; out-ports { port { From 3247e682cb4017f271dd7a620137d5941bcf6be9 Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Fri, 26 Feb 2021 18:46:48 +0530 Subject: [PATCH 1002/1809] ARM: dts: msm: Add support for new subtype id for yupik-iot Add support for HSP variant on yupik IoT platform. Change-Id: I331f3c5ebf387c25790e76cd65df336d2395ba09 --- qcom/Makefile | 6 ++++++ qcom/yupik-iot-hsp-overlay.dts | 11 +++++++++++ qcom/yupik-iot-hsp.dts | 10 ++++++++++ qcom/yupik-iot-hsp.dtsi | 4 ++++ qcom/yupikp-iot-hsp-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-hsp.dts | 10 ++++++++++ qcom/yupikp-iot-hsp.dtsi | 1 + 7 files changed, 53 insertions(+) create mode 100644 qcom/yupik-iot-hsp-overlay.dts create mode 100644 qcom/yupik-iot-hsp.dts create mode 100644 qcom/yupik-iot-hsp.dtsi create mode 100644 qcom/yupikp-iot-hsp-overlay.dts create mode 100644 qcom/yupikp-iot-hsp.dts create mode 100644 qcom/yupikp-iot-hsp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index c4fca42071c6..8fda09a944c5 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -167,9 +167,11 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupikp-idps-amoled-overlay.dtbo \ yupik-iot-idp-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ + yupik-iot-hsp-overlay.dtbo \ yupik-iot-idps-amoled-overlay.dtbo \ yupikp-iot-idp-overlay.dtbo \ yupikp-iot-qrd-overlay.dtbo \ + yupikp-iot-hsp-overlay.dtbo \ yupikp-iot-idps-amoled-overlay.dtbo @@ -186,9 +188,11 @@ yupikp-idps-digital-mics-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb +yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb +yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ @@ -204,9 +208,11 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupikp-idps-amoled.dtb \ yupik-iot-idp.dtb \ yupik-iot-qrd.dtb \ + yupik-iot-hsp.dtb \ yupik-iot-idps-amoled.dtb \ yupikp-iot-idp.dtb \ yupikp-iot-qrd.dtb \ + yupikp-iot-hsp.dtb \ yupikp-iot-idps-amoled.dtb endif diff --git a/qcom/yupik-iot-hsp-overlay.dts b/qcom/yupik-iot-hsp-overlay.dts new file mode 100644 index 000000000000..24ffe035be8e --- /dev/null +++ b/qcom/yupik-iot-hsp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IoT HSP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-iot-hsp.dts b/qcom/yupik-iot-hsp.dts new file mode 100644 index 000000000000..93b8c3d5e60a --- /dev/null +++ b/qcom/yupik-iot-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IoT HSP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-iot-hsp.dtsi b/qcom/yupik-iot-hsp.dtsi new file mode 100644 index 000000000000..f87450ed785b --- /dev/null +++ b/qcom/yupik-iot-hsp.dtsi @@ -0,0 +1,4 @@ +#include "yupik-iot-idp.dtsi" + +&soc { +}; diff --git a/qcom/yupikp-iot-hsp-overlay.dts b/qcom/yupikp-iot-hsp-overlay.dts new file mode 100644 index 000000000000..9d08f6544d7f --- /dev/null +++ b/qcom/yupikp-iot-hsp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IoT HSP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-iot-hsp.dts b/qcom/yupikp-iot-hsp.dts new file mode 100644 index 000000000000..5459f5d1ac2b --- /dev/null +++ b/qcom/yupikp-iot-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" +#include "yupikp-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IoT HSP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-iot-hsp.dtsi b/qcom/yupikp-iot-hsp.dtsi new file mode 100644 index 000000000000..b5ec1077fad6 --- /dev/null +++ b/qcom/yupikp-iot-hsp.dtsi @@ -0,0 +1 @@ +#include "yupikp-iot-idp.dtsi" From e9ff546612d7e82d836b98b011a23ceb74be80eb Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 3 Feb 2021 11:59:03 +0530 Subject: [PATCH 1003/1809] ARM: dts: msm: Add changes for PCIe0 RC enablement for yupik Add required dtsi changes for PCIe0 RC enablement for yupik. Change-Id: I323eb39d39f1bc4df9540c71a79f2e1c5fe3a2c4 --- qcom/yupik-pcie.dtsi | 272 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-pinctrl.dtsi | 54 ++++++++ qcom/yupik.dtsi | 1 + 3 files changed, 327 insertions(+) create mode 100644 qcom/yupik-pcie.dtsi diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi new file mode 100644 index 000000000000..a724fab080a6 --- /dev/null +++ b/qcom/yupik-pcie.dtsi @@ -0,0 +1,272 @@ +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x01c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 87 0>; + wake-gpio = <&tlmm 89 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p8-supply = <&L6B>; + vreg-0p9-supply = <&L10C>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <880000 880000 47900>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie_0_pipe_clk>; + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_0_axi_clk", + "pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src"; + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1C00>; + iommu-map = <0x0 &apps_smmu 0x1C00 0x1>, + <0x100 &apps_smmu 0x1C01 0x1>; + + qcom,boot-option = <0x1>; + qcom,drv-supported; + qcom,drv-l1ss-timeout-us = <10000>; + qcom,use-19p2mhz-aux-clk; + qcom,no-l0s-supported; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + + qcom,phy-manage-pll = <1>; + qcom,phy-resetsm-cntrl2 = <0xa0>; + qcom,phy-core-pll-en-mux = <7>; + qcom,phy-c-ready-status = <0x178>; + + qcom,pcie-phy-ver = <1003>; + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0x3f 0x0 + 0x0574 0x3f 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x14 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x1b 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x05b8 0x30 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cb4 0x33 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0ca4 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x77 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x12 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a10040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a10040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 7a6d1a6a7f15..33b95d965673 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1218,6 +1218,60 @@ }; }; + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio88"; + function = "pcie0_clkreqn"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK0 */ mux { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a30931465a30..6fe3de79b4f1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3801,6 +3801,7 @@ #include "ipcc-test-yupik.dtsi" #include "yupik-regulators.dtsi" #include "display/yupik-sde.dtsi" +#include "yupik-pcie.dtsi" &gcc_ufs_phy_gdsc { qcom,support-hw-trigger; From 3254cb4316eeee046dff2ba515365d331caddb51 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Fri, 11 Dec 2020 13:12:32 +0800 Subject: [PATCH 1004/1809] dt-bindings: Add device-tree bindings for virtual minidump driver Add the device-tree bindings documentation for virtual minidump. Change-Id: I5c5b8d5a9eb07deaa538e945f4553611ac854bd8 --- bindings/soc/qcom/qcom,virt-minidump.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 bindings/soc/qcom/qcom,virt-minidump.txt diff --git a/bindings/soc/qcom/qcom,virt-minidump.txt b/bindings/soc/qcom/qcom,virt-minidump.txt new file mode 100644 index 000000000000..b225845b46f7 --- /dev/null +++ b/bindings/soc/qcom/qcom,virt-minidump.txt @@ -0,0 +1,14 @@ +Qualcomm Technologies, Inc. Virtual Minidump + +Virtual minidump allows various clients on virtual machine to register memory +regions that need to be collected at system bad state. + +Required properties: +- compatible: Must be "qcom,virt-minidump". +- reg: Must contain register address and length. + +Example: + virt_minidump@1cb00000 { + compatible = "qcom,virt-minidump"; + reg = <0x1cb00000 0x1000>; + } From a82172fbee8a5f4269c4c62522983dd2e67228d2 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 2 Mar 2021 16:24:29 +0530 Subject: [PATCH 1005/1809] ARM: dts: msm: update charger ADC channels for yupik IDP Update charger ADC channels for PM7325B on yupik IDP, following HW recommendation. Change-Id: I62a746197a9be94da9d4e5738b88a3bd40ae86b0 --- qcom/yupik-idp.dtsi | 42 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index c9aa771df6cc..1464b7dc7159 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -150,6 +150,12 @@ qcom,pre-scaling = <1 1>; }; + pm7325b_iin_fb { + reg = ; + label = "pm7325b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; + pm7325b_ichg_fb { reg = ; label = "pm7325b_ichg_fb"; @@ -168,9 +174,39 @@ qcom,pre-scaling = <1 1>; }; - pm7325b_iin_fb { - reg = ; - label = "pm7325b_iin_fb"; + smb139x_1_iin_smb { + reg = ; + label = "smb139x_1_iin_smb"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_2_iin_smb { + reg = ; + label = "smb139x_2_iin_smb"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_1_ichg_smb { + reg = ; + label = "smb139x_1_ichg_smb"; + qcom,pre-scaling = <16 100>; + }; + + smb139x_1_ichg_smb_pt { + reg = ; + label = "smb139x_1_ichg_smb_pt"; + qcom,pre-scaling = <32 100>; + }; + + smb139x_2_ichg_smb { + reg = ; + label = "smb139x_2_ichg_smb"; + qcom,pre-scaling = <16 100>; + }; + + smb139x_2_ichg_smb_pt { + reg = ; + label = "smb139x_2_ichg_smb_pt"; qcom,pre-scaling = <32 100>; }; }; From 220a9e97136cbc9e8d7055377cc7987c8e9409ea Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 3 Mar 2021 19:04:24 +0800 Subject: [PATCH 1006/1809] ARM: dts: msm: correct dcc offset on sdxlemur The first 2KB should be reserved for TZ, so correct the offset to 0x800. Change-Id: I1f4b0ad01865e3374252a54074c5bd1f5fa02b7e --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7c1f15927966..010f9865d0de 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -221,12 +221,12 @@ dcc: dcc_v2@117f000 { compatible = "qcom,dcc-v2"; reg = <0x117f000 0x1000>, - <0x1100000 0x2000>; + <0x1100800 0x1800>; qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; - dcc-ram-offset = <0x12000>; + dcc-ram-offset = <0x800>; link_list1 { qcom,curr-link-list = <2>; From 66fd35ad95ed88e57576860291dd4731f0390427 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 17 Feb 2021 10:08:33 +0530 Subject: [PATCH 1007/1809] ARM: dts: msm: Add RPM SMD controlled PMIC regulators for Monaco Add RPM SMD regulator device nodes for PM5100 regulators. This ensures that consumers are able to modify the physical state of these PMIC regulators. Change-Id: I9a59c661c3aefe9326165614424f2987d1e81b11 --- qcom/monaco-regulators.dtsi | 510 ++++++++++++++++++++++++++++ qcom/pm5100-rpm-regulator.dtsi | 598 +++++++++++++++++++++++++++++++++ qcom/pm8010-rpm-regulator.dtsi | 120 +++++++ 3 files changed, 1228 insertions(+) create mode 100644 qcom/monaco-regulators.dtsi create mode 100644 qcom/pm5100-rpm-regulator.dtsi create mode 100644 qcom/pm8010-rpm-regulator.dtsi diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi new file mode 100644 index 000000000000..ff520cff6add --- /dev/null +++ b/qcom/monaco-regulators.dtsi @@ -0,0 +1,510 @@ +#include +#include + +&rpm_bus { + /* PM5100 L1 - VDD_CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S1A_LEVEL: pm5100_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + S1A_FLOOR_LEVEL: + pm5100_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + S1A_LEVEL_AO: pm5100_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + S3A: pm5100_s3: regulator-s3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1320000>; + qcom,init-voltage = <1320000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + S4A: pm5100_s4: regulator-s4 { + regulator-min-microvolt = <1816000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1904000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + S5A: pm5100_s5: regulator-s5 { + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <952000>; + qcom,init-voltage = <952000>; + status = "okay"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa4 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + VDD_LPI_CX_LEVEL: + L4A_LEVEL: pm5100_l4_level: regulator-l4-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l4_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa5 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + VDD_LPI_MX_LEVEL: + L5A_LEVEL: pm5100_l5_level: regulator-l5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + L1A: pm5100_l1: regulator-l1 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <504000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm5100_l2: regulator-l2 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <888000>; + qcom,init-voltage = <824000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: + VDD_EBI_LEVEL: + L3A_LEVEL: + pm5100_l3_level: regulator-pm5100-l3-level { + regulator-name = "pm5100_l3_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + qcom,use-voltage-level; + }; + + VDD_MXA_LEVEL_AO: + VDD_EBI_LEVEL_AO: + L3A_LEVEL_AO: + pm5100_l3_level_ao: regulator-pm5100-l3-level-ao { + regulator-name = "pm5100_l3_level_ao"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,use-voltage-level; + }; + + }; + + rpm-regulator-ldoa7 { + status = "okay"; + L7A: pm5100_l7: regulator-l7 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <624000>; + qcom,init-voltage = <624000>; + status = "okay"; + }; + }; + + /* WCSS_CX and WCSS_MX */ + rpm-regulator-ldoa8 { + status = "okay"; + WCSS_CX: + WCSS_MX: + L8A: pm5100_l8: regulator-l8 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <752000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + L9A: pm5100_l9: regulator-l9 { + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + qcom,init-voltage = <1232000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm5100_l10: regulator-l10 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm5100_l11: regulator-l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm5100_l12: regulator-l12 { + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + qcom,init-voltage = <904000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm5100_l13: regulator-l13 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm5100_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm5100_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm5100_l16: regulator-l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm5100_l17: regulator-l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm5100_l18: regulator-l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm5100_l19: regulator-l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm5100_l20: regulator-l20 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm5100_l21: regulator-l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm5100_l22: regulator-l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + L23A: pm5100_l23: regulator-l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + L24A: pm5100_l24: regulator-l24 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3304000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa25 { + status = "okay"; + L25A: pm5100_l25: regulator-l25 { + regulator-min-microvolt = <3080000>; + regulator-max-microvolt = <3080000>; + qcom,init-voltage = <3080000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa26 { + status = "okay"; + L26A: pm5100_l26: regulator-l26 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3304000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa27 { + status = "okay"; + L27A: pm5100_l27: regulator-l27 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa28 { + status = "okay"; + L28A: pm5100_l28: regulator-l28 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + qcom,init-voltage = <2904000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa29 { + status = "okay"; + L29A: pm5100_l29: regulator-l29 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-boba { + status = "okay"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + + BOB: pm5100a_bob: regulator-pm5100a-bob { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <4800000>; + qcom,init-voltage = <3300000>; + qcom,init-bob-mode = ; + status = "okay"; + }; + + BOB_AO: pm5100a_bob_ao: regulator-pm5100a-bob-ao { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <4800000>; + qcom,init-voltage = <3300000>; + qcom,init-bob-mode = ; + status = "okay"; + }; + }; + + rpm-regulator-ldoc1 { + status = "okay"; + L1C: pm8010_l1: regulator-l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc2 { + status = "okay"; + L2C: pm8010_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc3 { + status = "okay"; + L3C: pm8010_l3: regulator-l3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc4 { + status = "okay"; + L4C: pm8010_l4: regulator-l4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc5 { + status = "okay"; + L5C: pm8010_l5: regulator-l5 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc6 { + status = "okay"; + L6C: pm8010_l6: regulator-l6 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoc7 { + status = "okay"; + L7C: pm8010_l7: regulator-l7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; +}; diff --git a/qcom/pm5100-rpm-regulator.dtsi b/qcom/pm5100-rpm-regulator.dtsi new file mode 100644 index 000000000000..fd97369e4dfb --- /dev/null +++ b/qcom/pm5100-rpm-regulator.dtsi @@ -0,0 +1,598 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <30000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa25 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <25>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l25 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l25"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa26 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <26>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l26 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l26"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa27 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <27>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l27 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l27"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa28 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <28>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l28 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l28"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa29 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <29>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l29 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100_l29"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-boba { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "boba"; + qcom,resource-id = <1>; + qcom,regulator-type = <4>; + qcom,regulator-hw-type = "pmic5-bob"; + qcom,send-defaults; + status = "disabled"; + + regulator-pm5100a-bob { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100a_bob"; + qcom,set = <3>; + status = "disabled"; + }; + + regulator-pm5100a-bob-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm5100a_bob_ao"; + qcom,set = <1>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm8010-rpm-regulator.dtsi b/qcom/pm8010-rpm-regulator.dtsi new file mode 100644 index 000000000000..24b8f5b90e33 --- /dev/null +++ b/qcom/pm8010-rpm-regulator.dtsi @@ -0,0 +1,120 @@ +&rpm_bus { + rpm-regulator-ldoc1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoc7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoc"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8010_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; From 48da5e079acddc2d19d97ec8aabb62700b3f7503 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 4 Mar 2021 11:08:14 +0530 Subject: [PATCH 1008/1809] ARM: dts: msm: Add support to disable PDC wakeup for gpios for lahaina Add optional property to list gpios for which PDC wakeup is not needed. Such GPIOs will ignore PDC direct connect mapping and will continue to use tlmm for interrupt. Change-Id: Iffa050d5e880c250d85ddf825a2f2b90de2c55a4 --- bindings/pinctrl/qcom,lahaina-pinctrl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/pinctrl/qcom,lahaina-pinctrl.yaml b/bindings/pinctrl/qcom,lahaina-pinctrl.yaml index 64b386b2d2b5..21f93bc20e0c 100644 --- a/bindings/pinctrl/qcom,lahaina-pinctrl.yaml +++ b/bindings/pinctrl/qcom,lahaina-pinctrl.yaml @@ -55,6 +55,11 @@ properties: Value type: Definition: A phandle to the wakeup interrupt controller for the SoC. + no-wake-gpios: + Usage: optional + Value type: + Definition: List of gpios to not use for wakeup. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -196,4 +201,5 @@ examples: interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + no-wake-gpios = <2 7 11>; }; From 360a787561990c1d2829cda23d82ca70514467d9 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 25 Feb 2021 00:39:58 +0530 Subject: [PATCH 1009/1809] ARM: dts: msm: include quin-vm-display.dtsi The change includes quin-vm-display.dtsi that adds a new node sde_kms_hyp so that the display driver for hypervisor builds can be probed. Change-Id: Id94a1c516ed568d4d6fa219b67a222e5c4532940 --- qcom/quin-vm-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index fe320ee1341b..d22cc6ba3537 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -80,6 +80,8 @@ }; }; +#include "display/quin-vm-display.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; From 212bc759985358ca59b51df1443a7cbc9c6ca895 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Sun, 25 Oct 2020 21:02:07 +0800 Subject: [PATCH 1010/1809] ARM: dts: msm: Add qfprom for sa6155 Add QFPROM for sa6155. Change-Id: Ie62d9a3c80ebe2a398d1a0fc3024448b3380ec29 --- qcom/sa6155.dtsi | 11 +++++++++++ qcom/sa6155p.dtsi | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 8f5b05cc8966..25b695cba9ad 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -13,6 +13,17 @@ }; }; +&soc { + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + &qusb_phy0 { vdd-supply = <&L5A>; vdda18-supply = <&L12A>; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index a45e48a86479..470c7f12a7d2 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -31,6 +31,17 @@ /delete-node/ bt_wcn3990; }; +&soc { + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + &qusb_phy0 { vdd-supply = <&L5A>; vdda18-supply = <&L12A>; From b80f177e9f99dd3704d431ea9bbc39f96985a9e1 Mon Sep 17 00:00:00 2001 From: Amit Blay Date: Thu, 4 Mar 2021 11:09:59 +0200 Subject: [PATCH 1011/1809] ARM: dts: msm: Enable rename_blk device for Linux guest For LV guest VM, rename the vda virtual device to system. This is needed for supporting standard kernel command line generated in AVB2.0 vbmeta, which refers to the rootfs as /dev/system. Change-Id: I5905bf740a6aca30c4e898fc012d6b04a9d4c9f5 --- qcom/sa8155-vm-lv.dtsi | 8 ++++++++ qcom/sa8195-vm-lv.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/sa8155-vm-lv.dtsi b/qcom/sa8155-vm-lv.dtsi index e1c40cd0133b..5a72eaee7189 100644 --- a/qcom/sa8155-vm-lv.dtsi +++ b/qcom/sa8155-vm-lv.dtsi @@ -1,3 +1,11 @@ +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda"; + rename-dev = "system"; + }; +}; + &hab { vmid = <3>; }; diff --git a/qcom/sa8195-vm-lv.dtsi b/qcom/sa8195-vm-lv.dtsi index f7fd0e816130..39c87adf303c 100644 --- a/qcom/sa8195-vm-lv.dtsi +++ b/qcom/sa8195-vm-lv.dtsi @@ -9,6 +9,14 @@ }; }; +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda"; + rename-dev = "system"; + }; +}; + &usb0 { status = "ok"; }; From e797faa33b2b5276476a2d052330b46852dd905d Mon Sep 17 00:00:00 2001 From: Amit Blay Date: Thu, 4 Mar 2021 14:04:17 +0200 Subject: [PATCH 1012/1809] ARM: dts: msm: Change board-id for sa8195 lxc gvm As current board-id is already taken by lv gvm. Change-Id: I010012e79137d07c98090e2054aed6b554c58412 --- qcom/sa8195-vm-lv-lxc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sa8195-vm-lv-lxc.dts b/qcom/sa8195-vm-lv-lxc.dts index d4b58dc6e970..b90c72ae3093 100644 --- a/qcom/sa8195-vm-lv-lxc.dts +++ b/qcom/sa8195-vm-lv-lxc.dts @@ -4,8 +4,8 @@ #include "sa8195-vm-lv-lxc.dtsi" / { - model = "Qualcomm Technologies, Inc. SA8195 Multi LV Virtual Machine"; + model = "Qualcomm Technologies, Inc. SA8195 Single LV LXC Virtual Machine"; compatible = "qcom,sa8195p"; qcom,pmic-name = "PM8195"; - qcom,board-id = <0x2000002 0>; + qcom,board-id = <0x1000003 0>; }; From b8be93250644a8cdac6ffb7348a9216bd357aa53 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 3 Mar 2021 17:27:37 +0530 Subject: [PATCH 1013/1809] ARM: dts: msm: Add support for YUPIK LTE platform Add support for YUPIK LTE platform. Change-Id: I7e08afce968d5ac0b8508586ef510416ad248749 --- qcom/yupik-atp-overlay.dts | 2 +- qcom/yupik-idp-overlay.dts | 2 +- qcom/yupik-idps-amoled-overlay.dts | 2 +- qcom/yupik-idps-digital-mics-overlay.dts | 2 +- qcom/yupik-qrd-overlay.dts | 2 +- qcom/yupik-rumi-overlay.dts | 2 +- qcom/yupik-vm.dtsi | 2 +- qcom/yupik.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/yupik-atp-overlay.dts b/qcom/yupik-atp-overlay.dts index f237148be030..06bf11b9deab 100644 --- a/qcom/yupik-atp-overlay.dts +++ b/qcom/yupik-atp-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik ATP"; compatible = "qcom,yupik-atp", "qcom,yupik", "qcom,atp"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <0x10021 0>; }; diff --git a/qcom/yupik-idp-overlay.dts b/qcom/yupik-idp-overlay.dts index efa85633b394..1ccedd3fe57a 100644 --- a/qcom/yupik-idp-overlay.dts +++ b/qcom/yupik-idp-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDP"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/yupik-idps-amoled-overlay.dts b/qcom/yupik-idps-amoled-overlay.dts index 31b5898f9e18..49bc456343e7 100644 --- a/qcom/yupik-idps-amoled-overlay.dts +++ b/qcom/yupik-idps-amoled-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDPS + AMOLED"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <34 2>; }; diff --git a/qcom/yupik-idps-digital-mics-overlay.dts b/qcom/yupik-idps-digital-mics-overlay.dts index 5ee602b037e0..4f1b65e661ff 100644 --- a/qcom/yupik-idps-digital-mics-overlay.dts +++ b/qcom/yupik-idps-digital-mics-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDPS + DIGITAL MICS"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <34 1>; }; diff --git a/qcom/yupik-qrd-overlay.dts b/qcom/yupik-qrd-overlay.dts index 34be33030649..16c3269cfcdf 100644 --- a/qcom/yupik-qrd-overlay.dts +++ b/qcom/yupik-qrd-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik QRD"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,qrd"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <0x1000B 0>; }; diff --git a/qcom/yupik-rumi-overlay.dts b/qcom/yupik-rumi-overlay.dts index 45ef5d896d3f..f32a932f6bf2 100644 --- a/qcom/yupik-rumi-overlay.dts +++ b/qcom/yupik-rumi-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik RUMI"; compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; qcom,board-id = <0x1000f 0>; }; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index c189e1513776..c3e4356bd0fb 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -6,7 +6,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; interrupt-parent = <&vgic>; qcom-mem-buf { diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 52f53872bedb..9c9c3aadfb57 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -27,7 +27,7 @@ / { model = "Qualcomm Technologies, Inc. Yupik"; compatible = "qcom,yupik"; - qcom,msm-id = <475 0x10000>; + qcom,msm-id = <475 0x10000>, <515 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; From 7b03f086aed0691ffd6d0fc405dfbbaa5b95c577 Mon Sep 17 00:00:00 2001 From: Ajit Vaishya Date: Tue, 2 Mar 2021 19:30:36 +0530 Subject: [PATCH 1014/1809] ARM: dts: msm: Remove interconnect aggregation noc binding Remove interconnect aggregation noc binding from cnss for Yupik IOT. Change-Id: Ie299b1f1e041dbeb14fdc97f93e16f85202d826c CRs-Fixed: 2890856 --- qcom/qcx6490-cnss.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi index 61287b0d4633..3566a62551b4 100644 --- a/qcom/qcx6490-cnss.dtsi +++ b/qcom/qcx6490-cnss.dtsi @@ -25,11 +25,6 @@ wlan-ant-switch-supply = <&L11C>; qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; - interconnects = - <&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>, - <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; - interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; - qcom,icc-path-count = <2>; qcom,bus-bw-cfg-count = <7>; qcom,bus-bw-cfg = From 9742af860e930511cb2a6e1c787fc2cd9e1bdaef Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Wed, 3 Mar 2021 19:05:53 +0530 Subject: [PATCH 1015/1809] ARM: dts: msm: Increase max voltage range for S1B S1B is shared with camera and WLAN in Yupik IoT. Increase max voltage range for S1B to avoid any voting failure from different consumers. Change-Id: Ia4f36fd83bf24755dcc55eae7013ec72ca301db8 --- qcom/qcx6490-cnss.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi index 3566a62551b4..3e503af89451 100644 --- a/qcom/qcx6490-cnss.dtsi +++ b/qcom/qcx6490-cnss.dtsi @@ -19,7 +19,7 @@ vdd-wlan-io-supply = <&L19B>; qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; vdd-wlan-rfa1-supply = <&S1B>; - qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1880000 2040000 0 0 1>; vdd-wlan-rfa2-supply = <&S8B>; qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; wlan-ant-switch-supply = <&L11C>; From a1ed370541821490fe08459439a8f14cddb62fe5 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Tue, 2 Mar 2021 09:06:23 +0530 Subject: [PATCH 1016/1809] ARM: dts: msm: Add cnss devicetree node for Yupik IoT Add HSP(WCN6850) device tree node for Yupik IoT platform. Change-Id: I5e5824f379069653c1af3bfccc15228089315515 --- qcom/yupik-iot-idp.dtsi | 1 + qcom/yupikp-iot-idp.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index aeef58f4f289..31da5af1d4e3 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -1 +1,2 @@ #include "yupik-idp.dtsi" +#include "qcx6490-cnss.dtsi" diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi index 0790cb6d4444..90377734afa9 100644 --- a/qcom/yupikp-iot-idp.dtsi +++ b/qcom/yupikp-iot-idp.dtsi @@ -1 +1,2 @@ #include "yupikp-idp.dtsi" +#include "qcx6490-cnss.dtsi" From eaa6e050d005cb2d309680f1facff8fd20da4e8d Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 4 Mar 2021 15:47:42 +0800 Subject: [PATCH 1017/1809] ARM: dts: msm: add fixed-regulator to supply USB2 VBUS on Lahaina HHG Lahaina HHG device has a built-in joystick connected on USB2 port, the VBUS is supplied by a fixed-regulator controlled by PM8350 GPIO8 and its output voltage needs to be enabled always. Add the regulator device node and config it as always-on. Change-Id: I4877be73294939e4823965795a00053ebd84e572 --- qcom/lahaina-hhg.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 34f46a9a2a32..81240c4e035c 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -91,6 +91,19 @@ status = "ok"; }; }; + + joystick_usb_vbus: joystick_usb_vbus_regulator { + compatible = "regulator-fixed"; + regulator-name = "joystick_usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <600>; + gpio = <&pm8350_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; }; &usb1 { From aed3258ef3ffe9cf6b9c853ea7696507a0832eef Mon Sep 17 00:00:00 2001 From: Tahir Dawson Date: Wed, 28 Oct 2020 17:49:13 -0400 Subject: [PATCH 1018/1809] ARM: dts: qcom: vm: Add device nodes for second AFE rx and proxy tx devices * Add afe_proxy_tx_2 node for proxy capture frontend device. * Add afe_pcm_rx_2 node for afe playback backend device. * Add the new nodes to the ADP soundcard. Change-Id: I178b197766b05a65a3da0605cc1e6b1f4296d8b6 --- qcom/sa8155-vm-audio.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi index 9c5a795cb9f8..712ec64d98d2 100644 --- a/qcom/sa8155-vm-audio.dtsi +++ b/qcom/sa8155-vm-audio.dtsi @@ -426,6 +426,20 @@ qcom,msm-cpudai-tdm-data-align = <0>; }; }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + afe_pcm_rx_1: qcom,msm-dai-q6-be-afe-pcm-rx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <226>; + }; + + afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <242>; + }; + }; }; &audio_apr { @@ -460,10 +474,11 @@ <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&afe_pcm_rx_1>, <&afe_proxy_tx_1>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, <&usb_audio_rx>, <&usb_audio_tx>, <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, @@ -497,6 +512,7 @@ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.226", "msm-dai-q6-dev.242", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", From 24b66a11c1198c3fd47460390e3226e18531f486 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Fri, 5 Mar 2021 14:30:34 +0530 Subject: [PATCH 1019/1809] ARM: dts: msm: Add the iommu property on SA8155 Add the "qcom,iommu-dma-addr-pool" property for SA8155 target. Change-Id: I293d85b28cb519755ceb73624b7ecfaca5d2cacd --- qcom/sm8150-qupv3.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi index 1dbbcbf1bde8..e900d34b19e7 100644 --- a/qcom/sm8150-qupv3.dtsi +++ b/qcom/sm8150-qupv3.dtsi @@ -33,6 +33,7 @@ qcom,msm-bus,vectors-bus-ids = ; iommus = <&apps_smmu 0xc3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; @@ -334,6 +335,7 @@ qcom,msm-bus,vectors-bus-ids = ; iommus = <&apps_smmu 0x603 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; @@ -568,6 +570,7 @@ qcom,msm-bus,vectors-bus-ids = ; iommus = <&apps_smmu 0x7a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; From 76de0da122a6284549c4068e12824eb5e9e32df3 Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Thu, 4 Mar 2021 15:02:17 +0800 Subject: [PATCH 1020/1809] ARM: dts: msm: Add power reset and watchdog nodes for sa8155 quin vm Enables virtual power reset and watchdog, adds related configuration for SA8155 GVM platform. Change-Id: Iccfcfec3e728e6a4c2da5c6c8877b5c3eafbe313 --- bindings/soc/qcom/qcom,vm-restart.txt | 12 ++++++++++++ qcom/quin-vm-common.dtsi | 17 +++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 bindings/soc/qcom/qcom,vm-restart.txt diff --git a/bindings/soc/qcom/qcom,vm-restart.txt b/bindings/soc/qcom/qcom,vm-restart.txt new file mode 100644 index 000000000000..486d6b104098 --- /dev/null +++ b/bindings/soc/qcom/qcom,vm-restart.txt @@ -0,0 +1,12 @@ +* VM Restart Driver + +VM restart driver supports virtual machine power down and restart. + +Required properties: +- compatible: Must be "qcom,vm-restart" + +Example: + vm_restart: restart { + compatible = "qcom,vm-restart"; + }; + diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index fe320ee1341b..60b86e1baeb6 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -279,4 +279,21 @@ cell-index = <0>; status = "okay"; }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + vm_restart: restart { + compatible = "qcom,vm-restart"; + status = "ok"; + }; }; From dd0f1949b0a04a3c62bfa2e4d915e6dd5bbd407c Mon Sep 17 00:00:00 2001 From: Victor Date: Fri, 5 Mar 2021 09:49:23 +0200 Subject: [PATCH 1021/1809] dt-bindings: arm: msm: Add UFS ICE HW Node for SA8195 and SM8150 Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150. Change-Id: I6183a169eef5dbb20dbdf235ce1243297431bffa --- bindings/crypto/msm/ice.txt | 51 +++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 bindings/crypto/msm/ice.txt diff --git a/bindings/crypto/msm/ice.txt b/bindings/crypto/msm/ice.txt new file mode 100644 index 000000000000..0686a21513de --- /dev/null +++ b/bindings/crypto/msm/ice.txt @@ -0,0 +1,51 @@ +* Inline Crypto Engine (ICE) + +Required properties: + - compatible : should be "qcom,ice" + - reg : + +Optional properties: + - interrupt-names : name describing the interrupts for ICE IRQ + - interrupts : + - qcom,enable-ice-clk : should enable clocks for ICE HW + - clocks : List of phandle and clock specifier pairs + - clock-names : List of clock input name strings sorted in the same + order as the clocks property. + - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks + property. + - qcom,instance-type : describe the storage type for which ICE node is defined + currently, only "ufs" and "sdcc" are supported storage type + - vdd-hba-supply : regulated supply to be used by ICE HW + - qcom,bus-vector-names : bus vectors mapping + +Example: + ufs_ice: ufsice@630000 { + compatible = "qcom,ice"; + reg = <0x630000 0x8000>; + interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; + interrupts = <0 258 0>, <0 257 0>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk"; + clocks = <&clock_gcc clk_ufs_ice_core_clk_src>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <300000000>, <0>; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs_card_ice: ufscardice@1db0000 { + compatible = "qcom,ice_card"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>, + <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>, + <&clock_gcc GCC_UFS_CARD_AHB_CLK>, + <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_card_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs_card"; + }; From b80d5e6948d270d1c570c1bf6d7313ea9cdf1768 Mon Sep 17 00:00:00 2001 From: Victor Zaharchuk Date: Sun, 28 Feb 2021 21:28:55 +0200 Subject: [PATCH 1022/1809] ARM: dts: msm: Add UFS ICE HW Node for SA8195 and SM8150 Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150. Change-Id: I0cf94e9d87cf3785ecf2d99c273694f8c44e2645 --- qcom/sdmshrike.dtsi | 16 ++++++++++++++++ qcom/sm8150.dtsi | 20 ++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 233b0219f67e..6333ee3f9bdf 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1098,6 +1098,22 @@ clock-frequency = <32768>; }; + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + disp_rsc: rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6ab0bcce7f5c..3e8cba84ed8b 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1501,6 +1501,26 @@ reg = <0x17c0000c 0x4>; }; + + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + apss_shared: mailbox@17c00000 { compatible = "qcom,sm8150-apss-shared"; reg = <0x17c00000 0x1000>; From 2ca7b7c5c1ddab3aa104f4fbca022c397d4d58fd Mon Sep 17 00:00:00 2001 From: Kasin Li Date: Sat, 6 Mar 2021 10:54:15 +0800 Subject: [PATCH 1023/1809] ARM: dts: msm: Add hgsl support in 6155 6155 have no doorbell, but ifence still works. Change-Id: I598e5b215a7bc1186d1a9fb7547a118069c261ae --- bindings/soc/qcom/hgsl.txt | 2 ++ qcom/sa6155p-vm.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/bindings/soc/qcom/hgsl.txt b/bindings/soc/qcom/hgsl.txt index 4b608005b5ce..cbbed4be17de 100644 --- a/bindings/soc/qcom/hgsl.txt +++ b/bindings/soc/qcom/hgsl.txt @@ -12,6 +12,7 @@ Required properties: reg_doorbell_idx: address of GMUAO_DOORBELL_IDX Optional properties: +- db-off: Disable Doorbell feature but keep hgsl for ifence service - qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select which sender to use. The driver will use TCSR compute signal to send signal to GPU. @@ -25,6 +26,7 @@ Example: reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + db-off = <0>; qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>; qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>; }; diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index e00c1fdc6f3d..fa56ad422a9a 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -236,6 +236,13 @@ interrupt-parent = <&intc>; interrupt-controller; }; + + msm_gpu_hyp: qcom,hgsl { + compatible = "qcom,hgsl"; + + /* 6155 have no Doorbell, only keep ifence */ + db-off = <1>; + }; }; ®ulator { From 5d48d588fd33fa06760c73db5f918c2671cf4d10 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 5 Mar 2021 21:49:03 +0530 Subject: [PATCH 1024/1809] ARM: dts: qcom: keep all step wise rules before userspace rules for lahaina The multiple thermal zone trip violations are handled in same order as in thermal zone configuration in devicetree for a sensor. The userspace thermal zone handling might be slower because of multiple factors like uevent broadcast, low priority userspace process etc. It leads to a case where high priority stepwise thermal zone mitigation will be waiting for userspace thermal zone handling to complete. Keep userspace thermal zone as last thermal zone for each sensor so that step wise rules will be handled first. Change-Id: Ide6b14bbcdce239d7958b82d81272c3a2206748f --- qcom/lahaina-thermal.dtsi | 1224 ++++++++++++++++++------------------- 1 file changed, 612 insertions(+), 612 deletions(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 676ee997f091..69d4886a81f6 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -183,6 +183,618 @@ }; &thermal_zones { + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu10_cdev1 { + trip = <&cpu10_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu11_cdev1 { + trip = <&cpu11_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu12_cdev1 { + trip = <&cpu12_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + trips { + cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu13_cdev1 { + trip = <&cpu13_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + trips { + cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu14_cdev1 { + trip = <&cpu14_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + trips { + cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu15_cdev1 { + trip = <&cpu15_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + trips { + cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu16_cdev1 { + trip = <&cpu16_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + trips { + cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu17_cdev1 { + trip = <&cpu17_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + gpuss-0-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 1>; + trips { + gpuss0_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss0_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 2>; + trips { + gpuss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss1_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nspss-0-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 3>; + trips { + nspss0_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss0_config1: active-config1 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss0_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + nsp_cdev1 { + trip = <&nspss0_config1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + nspss-1-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 4>; + trips { + nspss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss1_config1: active-config1 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss1_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + nsp_cdev1 { + trip = <&nspss1_config1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + nspss-2-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 5>; + trips { + nspss2_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss2_config1: active-config1 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss2_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + nsp_cdev1 { + trip = <&nspss2_config1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pop-mem-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "step_wise"; + trips { + pop_trip: pop-trip { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + + pop_trip1: pop-trip1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pop_cdev { + trip = <&pop_trip>; + cooling-device = + <&apc1_cluster THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + pop_cdev1 { + trip = <&pop_trip1>; + cooling-device = <&ddr_cdev 5 5>; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -763,618 +1375,6 @@ }; }; - pop-mem-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - thermal-governor = "step_wise"; - trips { - pop_trip: pop-trip { - temperature = <90000>; - hysteresis = <0>; - type = "passive"; - }; - - pop_trip1: pop-trip1 { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - pop_cdev { - trip = <&pop_trip>; - cooling-device = - <&apc1_cluster THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - pop_cdev1 { - trip = <&pop_trip1>; - cooling-device = <&ddr_cdev 5 5>; - }; - }; - }; - - cpu-0-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 1>; - trips { - cpu00_config: cpu00-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu00_config1: cpu00-config1 { - temperature = <112000>; - hysteresis = <12000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu00_cdev { - trip = <&cpu00_config>; - cooling-device = <&cpu0_isolate 1 1>; - }; - - cpu00_cdev2 { - trip = <&cpu00_config1>; - cooling-device = <&cpu0_hotplug 1 1>; - }; - }; - }; - - cpu-0-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 2>; - trips { - cpu01_config: cpu01-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu01_config1: cpu01-config1 { - temperature = <112000>; - hysteresis = <12000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu01_cdev { - trip = <&cpu01_config>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - cpu01_cdev2 { - trip = <&cpu01_config1>; - cooling-device = <&cpu1_hotplug 1 1>; - }; - }; - }; - - cpu-0-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 3>; - trips { - cpu02_config: cpu02-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu02_config1: cpu02-config1 { - temperature = <112000>; - hysteresis = <12000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu02_cdev { - trip = <&cpu02_config>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - cpu02_cdev2 { - trip = <&cpu02_config1>; - cooling-device = <&cpu2_hotplug 1 1>; - }; - }; - }; - - cpu-0-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - thermal-governor = "step_wise"; - trips { - cpu03_config: cpu03-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu03_config1: cpu03-config1 { - temperature = <112000>; - hysteresis = <12000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu03_cdev { - trip = <&cpu03_config>; - cooling-device = <&cpu3_isolate 1 1>; - }; - - cpu03_cdev2 { - trip = <&cpu03_config1>; - cooling-device = <&cpu3_hotplug 1 1>; - }; - }; - }; - - cpu-1-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - thermal-governor = "step_wise"; - trips { - cpu10_config: cpu10-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu10_config1: cpu10-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu10_cdev { - trip = <&cpu10_config>; - cooling-device = <&cpu4_isolate 1 1>; - }; - - cpu10_cdev1 { - trip = <&cpu10_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu10_cdev2 { - trip = <&cpu10_config1>; - cooling-device = <&cpu4_hotplug 1 1>; - }; - }; - }; - - cpu-1-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - thermal-governor = "step_wise"; - trips { - cpu11_config: cpu11-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu11_config1: cpu11-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu11_cdev { - trip = <&cpu11_config>; - cooling-device = <&cpu4_isolate 1 1>; - }; - - cpu11_cdev1 { - trip = <&cpu11_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu11_cdev2 { - trip = <&cpu11_config1>; - cooling-device = <&cpu4_hotplug 1 1>; - }; - }; - }; - - cpu-1-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - thermal-governor = "step_wise"; - trips { - cpu12_config: cpu12-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu12_config1: cpu12-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu12_cdev { - trip = <&cpu12_config>; - cooling-device = <&cpu5_isolate 1 1>; - }; - - cpu12_cdev1 { - trip = <&cpu12_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu12_cdev2 { - trip = <&cpu12_config1>; - cooling-device = <&cpu5_hotplug 1 1>; - }; - }; - }; - - cpu-1-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - thermal-governor = "step_wise"; - trips { - cpu13_config: cpu13-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu13_config1: cpu13-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu13_cdev { - trip = <&cpu13_config>; - cooling-device = <&cpu5_isolate 1 1>; - }; - - cpu13_cdev1 { - trip = <&cpu13_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu13_cdev2 { - trip = <&cpu13_config1>; - cooling-device = <&cpu5_hotplug 1 1>; - }; - }; - }; - - cpu-1-4-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - thermal-governor = "step_wise"; - trips { - cpu14_config: cpu14-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu14_config1: cpu14-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu14_cdev { - trip = <&cpu14_config>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - cpu14_cdev1 { - trip = <&cpu14_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu14_cdev2 { - trip = <&cpu14_config1>; - cooling-device = <&cpu6_hotplug 1 1>; - }; - }; - }; - - cpu-1-5-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - thermal-governor = "step_wise"; - trips { - cpu15_config: cpu15-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu15_config1: cpu15-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu15_cdev { - trip = <&cpu15_config>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - cpu15_cdev1 { - trip = <&cpu15_config>; - cooling-device = <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu15_cdev2 { - trip = <&cpu15_config1>; - cooling-device = <&cpu6_hotplug 1 1>; - }; - }; - }; - - cpu-1-6-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - thermal-governor = "step_wise"; - trips { - cpu16_config: cpu16-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu16_config1: cpu16-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu16_cdev { - trip = <&cpu16_config>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - cpu16_cdev1 { - trip = <&cpu16_config>; - cooling-device = <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu16_cdev2 { - trip = <&cpu16_config1>; - cooling-device = <&cpu7_hotplug 1 1>; - }; - }; - }; - - cpu-1-7-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - thermal-governor = "step_wise"; - trips { - cpu17_config: cpu17-config { - temperature = <108000>; - hysteresis = <8000>; - type = "passive"; - }; - - cpu17_config1: cpu17-config1 { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu17_cdev { - trip = <&cpu17_config>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - cpu17_cdev1 { - trip = <&cpu17_config>; - cooling-device = <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - cpu17_cdev2 { - trip = <&cpu17_config1>; - cooling-device = <&cpu7_hotplug 1 1>; - }; - }; - }; - - gpuss-0-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 1>; - trips { - gpuss0_config: active-config0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - gpu_cdev { - trip = <&gpuss0_config>; - cooling-device = <&msm_gpu THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - gpuss-1-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 2>; - trips { - gpuss1_config: active-config0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - gpu_cdev { - trip = <&gpuss1_config>; - cooling-device = <&msm_gpu THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - nspss-0-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 3>; - trips { - nspss0_config: active-config0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss0_config1: active-config1 { - temperature = <105000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - nsp_cdev { - trip = <&nspss0_config>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - nsp_cdev1 { - trip = <&nspss0_config1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - nspss-1-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 4>; - trips { - nspss1_config: active-config0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss1_config1: active-config1 { - temperature = <105000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - nsp_cdev { - trip = <&nspss1_config>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - nsp_cdev1 { - trip = <&nspss1_config1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - nspss-2-step { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 5>; - trips { - nspss2_config: active-config0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss2_config1: active-config1 { - temperature = <105000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - nsp_cdev { - trip = <&nspss2_config>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - nsp_cdev1 { - trip = <&nspss2_config1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - mx-pe-step { polling-delay-passive = <0>; polling-delay = <0>; From 1e5ee1e8a527baa952af5c285f51e17570d4690c Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 5 Mar 2021 20:56:50 +0530 Subject: [PATCH 1025/1809] ARM: dts: qcom: enable modem mitigations for bcl thermal zones for yupik Enable modem qmi mitigations like modem_tj and modem_pa for bcl thermal zones for yupik. Change-Id: Iab20c153baa63b5ce92a992a9b5da24d7d9b8e32 --- qcom/yupik-thermal-overlay.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 247891c9ece0..6e1e1f9389e4 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -54,6 +54,16 @@ trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; @@ -78,6 +88,11 @@ trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vbat_modem0 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; @@ -119,6 +134,16 @@ trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vbat_modem0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; @@ -144,6 +169,11 @@ trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vbat_modem0 { + trip = <&c_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; From 5c5d2fcf7f0302aa5bb0ecd35e88180bd5d375ce Mon Sep 17 00:00:00 2001 From: Jing Li Date: Thu, 7 Jan 2021 11:13:40 +0800 Subject: [PATCH 1026/1809] ARM: dts: msm: Add camera device tree inclusions for lahaina hhg Need update camera sensor node for lahaina hhg platform. Change-Id: I51bbd415be7ae34bd30744e982fcaa05adbc8736 --- qcom/lahaina-hhg.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 34f46a9a2a32..ab960c6e8f95 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -1,4 +1,5 @@ #include "lahaina-hdk.dtsi" +#include "camera/lahaina-camera-sensor-hhg.dtsi" &wsa883x_0222 { status = "ok"; From 3f3a8c6d92b4e2408e15a2d0d80b4782fb936f28 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Mon, 8 Mar 2021 11:23:49 +0530 Subject: [PATCH 1027/1809] ARM: dts: msm: Reduce the CMA region sizes for sdxlemur Reduce the CMA region sizes of qseecom for sdxlemur keeping in view its a low memory target. Change-Id: I3156cf0f6bb12bf5caaa07505b7ddc1e1bff2077 --- qcom/sdxlemur-ion.dtsi | 6 ------ qcom/sdxlemur.dtsi | 10 +--------- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index 81fca5839dc6..e4a0057726dc 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -16,12 +16,6 @@ memory-region = <&audio_mem>; }; - qcom,ion-heap@26 { /* USER CONTIG HEAP */ - reg = ; - memory-region = <&user_contig_mem>; - qcom,ion-heap-type = "DMA"; - }; - qcom,ion-heap@27 { /* QSEECOM HEAP */ reg = ; memory-region = <&qseecom_mem>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7c1f15927966..99678ce50275 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -53,14 +53,6 @@ linux,cma-default; }; - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x1400000>; - }; - qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; @@ -74,7 +66,7 @@ alloc-ranges = <0x00000000 0xffffffff>; reusable; alignment = <0x400000>; - size = <0x1000000>; + size = <0x400000>; }; From 4ea75b9ec5e90f398ca94c4a49fa1f47306e5024 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Fri, 5 Mar 2021 11:32:42 +0530 Subject: [PATCH 1028/1809] ARM: dts: msm: Enable HMP for SA8195 and SA8155 VM Add HMP CPU data for SA8195 and SA8155 VM. Change-Id: I996a7d63c180f8afe3c028a5a94a603b6b7e654f --- qcom/sa8155-vm-la-mt.dtsi | 2 + qcom/sa8155-vm-lv-mt.dtsi | 4 ++ qcom/sa8155-vm.dtsi | 101 ++++++++++++++++++++++++++++++++++++++ qcom/sa8195-vm-la-mt.dtsi | 2 + 4 files changed, 109 insertions(+) diff --git a/qcom/sa8155-vm-la-mt.dtsi b/qcom/sa8155-vm-la-mt.dtsi index df8396983d51..eb7d489fffca 100644 --- a/qcom/sa8155-vm-la-mt.dtsi +++ b/qcom/sa8155-vm-la-mt.dtsi @@ -15,4 +15,6 @@ "persist", "modem", "bluetooth", "misc", "vbmeta"; }; + + /delete-node/ cpus; }; diff --git a/qcom/sa8155-vm-lv-mt.dtsi b/qcom/sa8155-vm-lv-mt.dtsi index 509403ae2ea3..6c91ca97915a 100644 --- a/qcom/sa8155-vm-lv-mt.dtsi +++ b/qcom/sa8155-vm-lv-mt.dtsi @@ -1,3 +1,7 @@ +/ { + /delete-node/ cpus; +}; + &hab { vmid = <3>; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 56933993038e..9b8a33d19093 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -15,6 +15,107 @@ hsuart0 = &qupv3_se13_4uart; sdhc2 = &sdhc_2; /* SDC2 SD card slot */ }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <902>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <902>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <902>; + }; + + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x4>; + capacity-dmips-mhz = <320>; + }; + + CPU5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x5>; + capacity-dmips-mhz = <320>; + }; + + CPU6: cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x6>; + capacity-dmips-mhz = <320>; + }; + + CPU7: cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x7>; + capacity-dmips-mhz = <320>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU1>; + }; + + core1 { + cpu = <&CPU2>; + }; + + core2 { + cpu = <&CPU3>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; }; &soc { diff --git a/qcom/sa8195-vm-la-mt.dtsi b/qcom/sa8195-vm-la-mt.dtsi index 75ca621962f9..a96127954046 100644 --- a/qcom/sa8195-vm-la-mt.dtsi +++ b/qcom/sa8195-vm-la-mt.dtsi @@ -15,4 +15,6 @@ "persist", "modem", "bluetooth", "misc", "vbmeta"; }; + + /delete-node/ cpus; }; From e3270d4ab71ce21ff25eb8f3be37546e7ed1754d Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Mon, 23 Nov 2020 18:02:26 -0800 Subject: [PATCH 1029/1809] ARM: dts: msm: Add initial device tree for Direwolf Add initial device trees to support the Direwolf platform on RUMI and ADP-STAR platforms. Change-Id: Ic5bf0d8221182c28a7ae136a16689ae836573026 --- qcom/Makefile | 17 ++ qcom/direwolf-adas-adp-star-overlay.dts | 12 ++ qcom/direwolf-adas-adp-star.dts | 11 + qcom/direwolf-adas-rumi-overlay.dts | 12 ++ qcom/direwolf-adas-rumi.dts | 11 + qcom/direwolf-adas.dts | 9 + qcom/direwolf-adas.dtsi | 7 + qcom/direwolf-adp-common.dtsi | 3 + qcom/direwolf-ivi-adp-star-overlay.dts | 12 ++ qcom/direwolf-ivi-adp-star.dts | 11 + qcom/direwolf-ivi-rumi-overlay.dts | 12 ++ qcom/direwolf-ivi-rumi.dts | 11 + qcom/direwolf-ivi.dts | 9 + qcom/direwolf-ivi.dtsi | 7 + qcom/direwolf-rumi-common.dtsi | 3 + qcom/direwolf.dtsi | 266 ++++++++++++++++++++++++ 16 files changed, 413 insertions(+) create mode 100644 qcom/direwolf-adas-adp-star-overlay.dts create mode 100644 qcom/direwolf-adas-adp-star.dts create mode 100644 qcom/direwolf-adas-rumi-overlay.dts create mode 100644 qcom/direwolf-adas-rumi.dts create mode 100644 qcom/direwolf-adas.dts create mode 100644 qcom/direwolf-adas.dtsi create mode 100644 qcom/direwolf-adp-common.dtsi create mode 100644 qcom/direwolf-ivi-adp-star-overlay.dts create mode 100644 qcom/direwolf-ivi-adp-star.dts create mode 100644 qcom/direwolf-ivi-rumi-overlay.dts create mode 100644 qcom/direwolf-ivi-rumi.dts create mode 100644 qcom/direwolf-ivi.dts create mode 100644 qcom/direwolf-ivi.dtsi create mode 100644 qcom/direwolf-rumi-common.dtsi create mode 100644 qcom/direwolf.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index be22d9cbddd1..d7d88aff5c88 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -355,6 +355,23 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8195-vm-lv-lxc.dtb \ sa6155p-vm-la.dtb +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi-overlay.dtbo \ + direwolf-ivi-adp-star-overlay.dtbo \ + direwolf-adas-rumi-overlay.dtbo \ + direwolf-adas-adp-star-overlay.dtbo + +direwolf-ivi-rumi-overlay.dtbo-base := direwolf-ivi.dtb +direwolf-ivi-adp-star-overlay.dtbo-base := direwolf-ivi.dtb +direwolf-adas-rumi-overlay.dtbo-base := direwolf-adas.dtb +direwolf-adas-adp-star-overlay.dtbo-base := direwolf-adas.dtb +else +dtb-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi.dtb \ + direwolf-ivi-adp-star.dtb \ + direwolf-adas-rumi.dtb \ + direwolf-adas-adp-star.dtb +endif + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/direwolf-adas-adp-star-overlay.dts b/qcom/direwolf-adas-adp-star-overlay.dts new file mode 100644 index 000000000000..807fd3c2bca2 --- /dev/null +++ b/qcom/direwolf-adas-adp-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU ADAS ADP-STAR"; + compatible = "qcom,direwolf-adas-adp-star", "qcom,direwolf-adas", + "qcom,direwolf", "qcom,adp-star"; + qcom,msm-id = <461 0x10000>; + qcom,board-id = <25 0>; +}; diff --git a/qcom/direwolf-adas-adp-star.dts b/qcom/direwolf-adas-adp-star.dts new file mode 100644 index 000000000000..534ad3fe07f4 --- /dev/null +++ b/qcom/direwolf-adas-adp-star.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-adas.dtsi" +#include "direwolf-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU ADAS ADP-STAR"; + compatible = "qcom,direwolf-adas-adp-star", "qcom,direwolf-adas", + "qcom,direwolf", "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/direwolf-adas-rumi-overlay.dts b/qcom/direwolf-adas-rumi-overlay.dts new file mode 100644 index 000000000000..8a1636584854 --- /dev/null +++ b/qcom/direwolf-adas-rumi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-rumi-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU Rumi"; + compatible = "qcom,direwolf-adas-rumi", "qcom,direwolf-adas", + "qcom,direwolf", "qcom,rumi"; + qcom,msm-id = <461 0x10000>; + qcom,board-id = <0xF 0>; +}; diff --git a/qcom/direwolf-adas-rumi.dts b/qcom/direwolf-adas-rumi.dts new file mode 100644 index 000000000000..c37c9584471d --- /dev/null +++ b/qcom/direwolf-adas-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-adas.dtsi" +#include "direwolf-rumi-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU ADAS SoC RUMI"; + compatible = "qcom,direwolf-adas-rumi", "qcom,direwolf-adas", + "qcom,direwolf", "qcom,rumi"; + qcom,board-id = <0xF 0>; +}; diff --git a/qcom/direwolf-adas.dts b/qcom/direwolf-adas.dts new file mode 100644 index 000000000000..790ab1ab6ab8 --- /dev/null +++ b/qcom/direwolf-adas.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "direwolf-adas.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU v1 ADAS SoC"; + compatible = "qcom,direwolf-adas", "qcom,direwolf"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/direwolf-adas.dtsi b/qcom/direwolf-adas.dtsi new file mode 100644 index 000000000000..589458f88196 --- /dev/null +++ b/qcom/direwolf-adas.dtsi @@ -0,0 +1,7 @@ +#include "direwolf.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU ADAS SoC"; + compatible = "qcom,direwolf-adas", "qcom,direwolf"; + qcom,msm-id = <461 0x10000>; +}; diff --git a/qcom/direwolf-adp-common.dtsi b/qcom/direwolf-adp-common.dtsi new file mode 100644 index 000000000000..23df450781cf --- /dev/null +++ b/qcom/direwolf-adp-common.dtsi @@ -0,0 +1,3 @@ +&soc { + +}; diff --git a/qcom/direwolf-ivi-adp-star-overlay.dts b/qcom/direwolf-ivi-adp-star-overlay.dts new file mode 100644 index 000000000000..ae08d0b75f14 --- /dev/null +++ b/qcom/direwolf-ivi-adp-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI ADP-STAR"; + compatible = "qcom,direwolf-ivi-adp-star", "qcom,direwolf-ivi", + "qcom,direwolf", "qcom,adp-star"; + qcom,msm-id = <460 0x10000>; + qcom,board-id = <25 0>; +}; diff --git a/qcom/direwolf-ivi-adp-star.dts b/qcom/direwolf-ivi-adp-star.dts new file mode 100644 index 000000000000..dea7557bf4ee --- /dev/null +++ b/qcom/direwolf-ivi-adp-star.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-ivi.dtsi" +#include "direwolf-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI ADP-STAR"; + compatible = "qcom,direwolf-ivi-adp-star", "qcom,direwolf-ivi", + "qcom,direwolf", "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/direwolf-ivi-rumi-overlay.dts b/qcom/direwolf-ivi-rumi-overlay.dts new file mode 100644 index 000000000000..b429cb8f61c9 --- /dev/null +++ b/qcom/direwolf-ivi-rumi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-rumi-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI Rumi"; + compatible = "qcom,direwolf-ivi-rumi", "qcom,direwolf-ivi", + "qcom,direwolf", "qcom,rumi"; + qcom,msm-id = <460 0x10000>; + qcom,board-id = <0xF 0>; +}; diff --git a/qcom/direwolf-ivi-rumi.dts b/qcom/direwolf-ivi-rumi.dts new file mode 100644 index 000000000000..6087fea20246 --- /dev/null +++ b/qcom/direwolf-ivi-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-ivi.dtsi" +#include "direwolf-rumi-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI SoC RUMI"; + compatible = "qcom,direwolf-ivi-rumi", "qcom,direwolf-ivi", + "qcom,direwolf", "qcom,rumi"; + qcom,board-id = <0xF 0>; +}; diff --git a/qcom/direwolf-ivi.dts b/qcom/direwolf-ivi.dts new file mode 100644 index 000000000000..8848c29b12f2 --- /dev/null +++ b/qcom/direwolf-ivi.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "direwolf-ivi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI SoC"; + compatible = "qcom,direwolf-ivi", "qcom,direwolf"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/direwolf-ivi.dtsi b/qcom/direwolf-ivi.dtsi new file mode 100644 index 000000000000..d69dedfd0352 --- /dev/null +++ b/qcom/direwolf-ivi.dtsi @@ -0,0 +1,7 @@ +#include "direwolf.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DirewolfAU IVI SoC"; + compatible = "qcom,direwolf-ivi", "qcom,direwolf"; + qcom,msm-id = <460 0x10000>; +}; diff --git a/qcom/direwolf-rumi-common.dtsi b/qcom/direwolf-rumi-common.dtsi new file mode 100644 index 000000000000..23df450781cf --- /dev/null +++ b/qcom/direwolf-rumi-common.dtsi @@ -0,0 +1,3 @@ +&soc { + +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi new file mode 100644 index 000000000000..a5f21349c880 --- /dev/null +++ b/qcom/direwolf.dtsi @@ -0,0 +1,266 @@ +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Direwolf"; + compatible = "qcom,direwolf"; + qcom,msm-name = "Direwolf V1"; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { }; + + reserved_memory: reserved-memory { }; + + chosen { }; + + vendor: vendor { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <500000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; +}; From 4a28ffca6e158eee236f2ca81c538d5c8683c85b Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 10:24:31 +0530 Subject: [PATCH 1030/1809] ARM: dts: msm: Populate reserved memory regions for Direwolf Populate the reserved memory node with carveout regions based on the memory map for Direwolf. Change-Id: Ib30f369876487f28e6d754cddde10f6e202f9926 --- qcom/direwolf.dtsi | 152 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index a5f21349c880..1f9eb37a4afa 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -172,7 +172,157 @@ soc: soc { }; - reserved_memory: reserved-memory { }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_boot: xbl_boot_region@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x200000>; + }; + + xbl_aop_mem: xbl_aop_region@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + cmd_db: reserved-memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + gpu_prr: gpu_prr_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x10000>; + }; + + tpm_control: tmp_control@80890000 { + no-map; + reg = <0x0 0x80890000 0x0 0x10000>; + }; + + reserved_0: reserved_0_region@808F0000 { + no-map; + reg = <0x0 0x808F0000 0x0 0xF000>; + }; + + secdata: secdata_region@808FF000 { + no-map; + reg = <0x0 0x808FF000 0x0 0x1000>; + }; + + smem_mem: smem_mem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw: cpucp_fw_region@80B00000 { + no-map; + reg = <0x0 0x80B00000 0x0 0x100000>; + }; + + lpass_ml: lpass_ml_region@0x83B00000 { + no-map; + reg = <0x0 0x83B00000 0x0 0xF00000>; + }; + + adsp_rpc: adsp_rpc_remote_heap@0x84A00000 { + no-map; + reg = <0x0 0x84A00000 0x0 0x800000>; + }; + + pil_camera_mem: pil_camera_region@85200000 { + no-map; + reg = <0x0 0x85200000 0x0 0x500000>; + }; + + pil_spss_mem: pil_spss_mem_region@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x400000>; + }; + + pil_adsp_boot_mem: pil_adsp_boot_region@85B00000 { + no-map; + reg = <0x0 0x85B00000 0x0 0xA00000>; + }; + + pil_video_mem: pil_video_region@86500000 { + no-map; + reg = <0x0 0x86500000 0x0 0x500000>; + }; + + pil_adsp_mem: pil_adsp_region@86A00000 { + no-map; + reg = <0x0 0x86A00000 0x0 0x2000000>; + }; + + pil_slpi_mem: pil_slpi_region@88A00000 { + no-map; + reg = <0x0 0x88A00000 0x0 0x1500000>; + }; + + pil_cdsp_mem: pil_cdsp_region@89F00000 { + no-map; + reg = <0x0 0x89F00000 0x0 0x1e00000>; + }; + + pil_gpu_mem: pil_gpu_region@8BD00000 { + no-map; + reg = <0x0 0x8BD00000 0x0 0x2000>; + }; + + pil_smss_mem: pil_smss_region@8BE00000 { + no-map; + reg = <0x0 0x8BE00000 0x0 0x300000>; + }; + + pil_reserved_mem: pil_reserved_region@8C100000 { + no-map; + reg = <0x0 0x8C100000 0x0 0x500000>; + }; + + pil_cdsp1_mem: pil_cdsp1_region@8C600000 { + no-map; + reg = <0x0 0x8C600000 0x0 0x1E00000>; + }; + + uefi_mem: uefi_mem_region@9F000000 { + no-map; + reg = <0x0 0x9F000000 0x0 0x1000000>; + }; + + hyp_tz_mem: hyp_tz_mem_region@AEB00000 { + no-map; + reg = <0x0 0xAEB00000 0x0 0x11500000>; + }; + + tz_stat_mem: adsp_rpc_mem_region@C0000000 { + no-map; + reg = <0x0 0xC0000000 0x0 0x100000>; + }; + + pIMEM: pIMEM_valut_mem_region@C0100000 { + no-map; + reg = <0x0 0xC0100000 0x0 0x5000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; chosen { }; From 42e2132dba4637346f23922c46758b4aaa7e3c40 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 10:53:12 +0530 Subject: [PATCH 1031/1809] ARM: dts: msm: Add pinctrl node for TLMM on Direwolf SoC Add pinctrl node with compatiability of qcom,direwolf-pinctrl, to enable Top Level Mode Multiplexer block(TLMM) on Direwolf SoC. Change-Id: I5cf4c487a59d5d38958a15f0c9f1ef8877e254c1 --- bindings/pinctrl/qcom,direwolf-pinctrl.yaml | 148 ++++++++++++++++++++ qcom/direwolf-pinctrl.dtsi | 1 + qcom/direwolf.dtsi | 13 ++ 3 files changed, 162 insertions(+) create mode 100644 bindings/pinctrl/qcom,direwolf-pinctrl.yaml create mode 100644 qcom/direwolf-pinctrl.dtsi diff --git a/bindings/pinctrl/qcom,direwolf-pinctrl.yaml b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml new file mode 100644 index 000000000000..33cc8e59e26f --- /dev/null +++ b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml @@ -0,0 +1,148 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,direwolf-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. DIREWOLF TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + Direwolf platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,direwolf-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio227 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@03000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi new file mode 100644 index 000000000000..8b7b9bd9baa8 --- /dev/null +++ b/qcom/direwolf-pinctrl.dtsi @@ -0,0 +1 @@ +&tlmm { }; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 1f9eb37a4afa..a75072d5dcde 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -413,4 +413,17 @@ status = "disabled"; }; }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x0F000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + +#include "direwolf-pinctrl.dtsi" From 2356c682aa28631a0803838c0fcc761b1fd445a3 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 11:08:34 +0530 Subject: [PATCH 1032/1809] ARM: dts: msm: Add device-tree entry for IMEM for Direwolf SoC Add device-tree entry for system IMEM to read or write various system level configurations for Direwolf. Change-Id: Id16806eb9a7202c72d6980ec9109e3adb3be9e0c --- qcom/direwolf.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index a75072d5dcde..b779e0798746 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -414,6 +414,49 @@ }; }; + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; From 4c97800b3181332440fe1fb812c6b13e469eb8d5 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 11:17:24 +0530 Subject: [PATCH 1033/1809] ARM: dts: msm: Add WDT node for Direwolf Add WDT node with compatible qcom,msm-watchdog, to enable watchdog driver on Direwolf. Change-Id: Ia598e8b54c509795cd005755b7091b6ae584fab7 --- qcom/direwolf.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index b779e0798746..26ee750ae18a 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -467,6 +467,18 @@ #interrupt-cells = <2>; }; + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + }; #include "direwolf-pinctrl.dtsi" From 9d4148035006780932528b1dee48667aaacce780 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 11:22:37 +0530 Subject: [PATCH 1034/1809] ARM: dts: msm: Add pshold dt node for Direwolf Add pshold device tree node for Direwolf to enable msm-poweroff driver to populate required cookies when the SoC resets. Change-Id: I984fccfdb0fde3e52f83bae1ad6dd5584da35602 --- qcom/direwolf.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 26ee750ae18a..61c7df619c7a 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -457,6 +457,12 @@ }; }; + restart: restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; From 8dd3f8a87c0170c1e5d68ddb942439423895320a Mon Sep 17 00:00:00 2001 From: Ajit Vaishya Date: Mon, 8 Mar 2021 00:11:32 -0800 Subject: [PATCH 1035/1809] ARM: dts: msm: Add interconnect aggregation noc - This fix Adds interconnect binding to aggre1_noc for cnss node. - Includes yupik.h in all iot yupik overlay dts file. Change-Id: I36bcd11ab02384cccb0b4a42a707ca6822b51c6b CRs-Fixed: 2894446 --- qcom/qcx6490-cnss.dtsi | 5 +++++ qcom/yupik-iot-hsp-overlay.dts | 1 + qcom/yupik-iot-idp-overlay.dts | 1 + qcom/yupikp-iot-hsp-overlay.dts | 1 + qcom/yupikp-iot-idp-overlay.dts | 1 + 5 files changed, 9 insertions(+) diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi index 3e503af89451..6a3f68c6e68b 100644 --- a/qcom/qcx6490-cnss.dtsi +++ b/qcom/qcx6490-cnss.dtsi @@ -25,6 +25,11 @@ wlan-ant-switch-supply = <&L11C>; qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; + interconnects = + <&aggre1_noc MASTER_PCIE_0 &aggre1_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + qcom,icc-path-count = <2>; qcom,bus-bw-cfg-count = <7>; qcom,bus-bw-cfg = diff --git a/qcom/yupik-iot-hsp-overlay.dts b/qcom/yupik-iot-hsp-overlay.dts index 24ffe035be8e..ff3f722b20fc 100644 --- a/qcom/yupik-iot-hsp-overlay.dts +++ b/qcom/yupik-iot-hsp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupik-iot-hsp.dtsi" / { diff --git a/qcom/yupik-iot-idp-overlay.dts b/qcom/yupik-iot-idp-overlay.dts index 359966e32f06..fcf60a41d2d6 100644 --- a/qcom/yupik-iot-idp-overlay.dts +++ b/qcom/yupik-iot-idp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupik-iot-idp.dtsi" / { diff --git a/qcom/yupikp-iot-hsp-overlay.dts b/qcom/yupikp-iot-hsp-overlay.dts index 9d08f6544d7f..5bce4a9f4d0f 100644 --- a/qcom/yupikp-iot-hsp-overlay.dts +++ b/qcom/yupikp-iot-hsp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupikp-iot-hsp.dtsi" / { diff --git a/qcom/yupikp-iot-idp-overlay.dts b/qcom/yupikp-iot-idp-overlay.dts index 01da5d563edd..b90731fe0dfb 100644 --- a/qcom/yupikp-iot-idp-overlay.dts +++ b/qcom/yupikp-iot-idp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupikp-idp.dtsi" / { From e19ece624b01c826462d7f47e03d28ce6f732fdb Mon Sep 17 00:00:00 2001 From: Akshay Pandit Date: Tue, 27 Oct 2020 18:52:21 +0530 Subject: [PATCH 1036/1809] ARM: dts: msm: Add veth ipa documentation for device node Add documentation for veth_ipa dev node . Add documentation for ipa dt entry to track num of smmu cb present. Change-Id: If64a961af0642549898aa8b5349514373cc148e1 --- bindings/platform/msm/ipa.txt | 2 +- bindings/platform/msm/veth_ipa.txt | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 bindings/platform/msm/veth_ipa.txt diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index bcd61f0ff777..6939190e3d42 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -135,7 +135,7 @@ memory allocation over a PCIe bridge 2 (override scm call as though it returned false) - qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event rings read pointer should be read from the ddr. -- qcom,max_num_smmu_cb: number of active smmu context banks for target. +- qcom,max_num_smmu_cb: Total number of context banks used for the target IPA pipe sub nodes (A2 static pipes configurations): diff --git a/bindings/platform/msm/veth_ipa.txt b/bindings/platform/msm/veth_ipa.txt new file mode 100644 index 000000000000..e59975d62996 --- /dev/null +++ b/bindings/platform/msm/veth_ipa.txt @@ -0,0 +1,14 @@ +Qualcomm Technologies, Inc. Veth IPA device + +This specifies the bindings for QTI VETH_IPA that provides backhaul +connectivity. + +Required properties: +- compatible: Must be "qcom,veth-ipa" + + +Example: + qcom,veth-ipa { + compatible = "qcom,veth-ipa"; + }; + From d1dbb8e7ae687808479468a436742af08452ee60 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 9 Mar 2021 11:18:47 +0530 Subject: [PATCH 1037/1809] ARM: dts: msm: Fix cache dump sizes for SM8150 Fix the cache dump sizes according to the hardware specification. Change-Id: Ifd592225c1cdb21a24aa41a79a93f0fb37fbe593 --- qcom/sm8150.dtsi | 72 ++++++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 3e8cba84ed8b..c67b62140c99 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2439,182 +2439,182 @@ }; l1_icache0 { - qcom,dump-size = <0x8800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x60>; }; l1_icache100 { - qcom,dump-size = <0x8800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x61>; }; l1_icache200 { - qcom,dump-size = <0x8800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x62>; }; l1_icache300 { - qcom,dump-size = <0x8800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x63>; }; l1_icache400 { - qcom,dump-size = <0x11000>; + qcom,dump-size = <0x11100>; qcom,dump-id = <0x64>; }; l1_icache500 { - qcom,dump-size = <0x11000>; + qcom,dump-size = <0x11100>; qcom,dump-id = <0x65>; }; l1_icache600 { - qcom,dump-size = <0x11000>; + qcom,dump-size = <0x11100>; qcom,dump-id = <0x66>; }; l1_icache700 { - qcom,dump-size = <0x11000>; + qcom,dump-size = <0x11100>; qcom,dump-id = <0x67>; }; l1_dcache0 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x80>; }; l1_dcache100 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x81>; }; l1_dcache200 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x82>; }; l1_dcache300 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x83>; }; l1_dcache400 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x12100>; qcom,dump-id = <0x84>; }; l1_dcache500 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x12100>; qcom,dump-id = <0x85>; }; l1_dcache600 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x12100>; qcom,dump-id = <0x86>; }; l1_dcache700 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x12100>; qcom,dump-id = <0x87>; }; l1_itlb400 { - qcom,dump-size = <0x300>; + qcom,dump-size = <0x400>; qcom,dump-id = <0x24>; }; l1_itlb500 { - qcom,dump-size = <0x300>; + qcom,dump-size = <0x400>; qcom,dump-id = <0x25>; }; l1_itlb600 { - qcom,dump-size = <0x300>; + qcom,dump-size = <0x400>; qcom,dump-id = <0x26>; }; l1_itlb700 { - qcom,dump-size = <0x300>; + qcom,dump-size = <0x400>; qcom,dump-id = <0x27>; }; l1_dtlb400 { - qcom,dump-size = <0x480>; + qcom,dump-size = <0x580>; qcom,dump-id = <0x44>; }; l1_dtlb500 { - qcom,dump-size = <0x480>; + qcom,dump-size = <0x580>; qcom,dump-id = <0x45>; }; l1_dtlb600 { - qcom,dump-size = <0x480>; + qcom,dump-size = <0x580>; qcom,dump-id = <0x46>; }; l1_dtlb700 { - qcom,dump-size = <0x480>; + qcom,dump-size = <0x580>; qcom,dump-id = <0x47>; }; l2_cache400 { - qcom,dump-size = <0x88000>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc4>; }; l2_cache500 { - qcom,dump-size = <0x88000>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc5>; }; l2_cache600 { - qcom,dump-size = <0x88000>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc6>; }; l2_cache700 { - qcom,dump-size = <0x110000>; + qcom,dump-size = <0x90100>; qcom,dump-id = <0xc7>; }; l2_tlb0 { - qcom,dump-size = <0x5000>; + qcom,dump-size = <0x5B00>; qcom,dump-id = <0x120>; }; l2_tlb100 { - qcom,dump-size = <0x5000>; + qcom,dump-size = <0x5B00>; qcom,dump-id = <0x121>; }; l2_tlb200 { - qcom,dump-size = <0x5000>; + qcom,dump-size = <0x5B00>; qcom,dump-id = <0x122>; }; l2_tlb300 { - qcom,dump-size = <0x5000>; + qcom,dump-size = <0x5B00>; qcom,dump-id = <0x123>; }; l2_tlb400 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x7900>; qcom,dump-id = <0x124>; }; l2_tlb500 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x7900>; qcom,dump-id = <0x125>; }; l2_tlb600 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x7900>; qcom,dump-id = <0x126>; }; l2_tlb700 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x7900>; qcom,dump-id = <0x127>; }; }; From 1139a0b43cac3b9419dbde201794edb420071569 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Tue, 9 Mar 2021 11:42:59 +0530 Subject: [PATCH 1038/1809] ARM: dts: msm: Add the iommu property for SSC QUP Add the "qcom,iommu-dma-addr-pool" property for SA8155 target. Change-Id: Id2e02b83d9b376bc53c9265ac2b3975ebabf474d --- qcom/sm8150-ssc-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sm8150-ssc-qupv3.dtsi b/qcom/sm8150-ssc-qupv3.dtsi index f7497278802e..17308b8be877 100644 --- a/qcom/sm8150-ssc-qupv3.dtsi +++ b/qcom/sm8150-ssc-qupv3.dtsi @@ -10,6 +10,7 @@ qcom,msm-bus,vectors-bus-ids = ; iommus = <&apps_smmu 0x4e3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; status = "disabled"; }; From bdad4b417ea1e68848fe5d4e43915c668a83206d Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 9 Mar 2021 12:19:47 +0530 Subject: [PATCH 1039/1809] ARM: dts: msm: Add missing CPUSS dump nodes to SDMSHRIKE Add missing CPUSS dump nodes for L2 TLB, L1 D-TLB, L1 I-TLB, L2 Cache. Change-Id: I3d24bb7bb7346154712efafa7aa767af3f62234c --- qcom/sdmshrike.dtsi | 100 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6333ee3f9bdf..24fdc41cdabb 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -994,6 +994,106 @@ qcom,dump-size = <0x14000>; qcom,dump-id = <0x87>; }; + + l1_itlb400 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x24>; + }; + + l1_itlb500 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x25>; + }; + + l1_itlb600 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb400 { + qcom,dump-size = <0x580>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb500 { + qcom,dump-size = <0x580>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x580>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x580>; + qcom,dump-id = <0x47>; + }; + + l2_cache400 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5B00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5B00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5B00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5B00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x127>; + }; }; clocks { From a0a581f72ce7ef60c3de466b65a814a58a06d5e3 Mon Sep 17 00:00:00 2001 From: nishant chaubey Date: Tue, 9 Mar 2021 15:50:55 +0530 Subject: [PATCH 1040/1809] ARM: dts: msm: Add qos-cores for fastrpc Add qos-cores to control RPC latency using PM-QoS. Change-Id: I8991bba29fbf0d9cddb1539e4579a5d17649f167 --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index bb0057560333..5822ed605940 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3498,6 +3498,7 @@ qcom,fastrpc-adsp-sensors-pdr; qcom,rpc-latency-us = <235>; qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; qcom,msm_fastrpc_compute_cb1 { compatible = "qcom,msm-fastrpc-compute-cb"; From f518271295ff78ed09972ed427593d1311416c53 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Wed, 3 Mar 2021 19:46:57 +0530 Subject: [PATCH 1041/1809] ARM: dts: msm: Workaround till all IPA changes are merged Disabling IPA for compilation as interim solution. Change-Id: Ifd75450a787dbd39ada88f283d75d0ea1662e626 --- qcom/sa8195-vm-la.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 7527d5a4b602..51d73bc5fead 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -54,10 +54,12 @@ &soc { pil_scm_pas { compatible = "qcom,pil-tz-scm-pas"; + status = "disabled"; }; qcom,msm_gsi { compatible = "qcom,msm_gsi"; + status = "disabled"; }; ipa_hw: qcom,ipa@1e00000 { @@ -110,6 +112,7 @@ "TURBO"; qcom,throughput-threshold = <310 600 1000>; qcom,scaling-exceptions = <>; + status = "disabled"; }; ipa_smmu_ap: ipa_smmu_ap { @@ -141,6 +144,7 @@ qcom,firmware-name = "ipa_fws"; qcom,pil-force-shutdown; memory-region = <&pil_ipa_gsi_mem>; + status = "disabled"; }; qcom,ipa_uc { @@ -149,6 +153,7 @@ qcom,firmware-name = "ipa_uc"; qcom,pil-force-shutdown; memory-region = <&pil_ipa_fw_mem>; + status = "disabled"; }; }; From e71c62801945d22cc021c557ea379cf94aa424f9 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Fri, 20 Nov 2020 16:26:08 +0530 Subject: [PATCH 1042/1809] ARM: dts: msm: Add IPCC node for Direwolf Add IPCC node with compatible of qcom,ipcc to enable the IPCC driver on Direwolf target. Change-Id: I622bfaa61d11d0de27e547d770ac934173b67c3a --- qcom/direwolf.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 26ee750ae18a..cddcdd412f29 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { model = "Qualcomm Technologies, Inc. Direwolf"; @@ -479,6 +480,14 @@ qcom,wakeup-enable; }; + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; }; #include "direwolf-pinctrl.dtsi" From 3273ad8aef5f0951e45ea094280748031e9b58a2 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Tue, 9 Mar 2021 13:29:26 +0530 Subject: [PATCH 1043/1809] ARM: dts: msm: Correct the audio ion node heap type Correct the audio ion node head type. Change-Id: I6ada6d403a67eeb6f15a8eb8daac6f1932f0ba13 --- qcom/sdxlemur-ion.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index e4a0057726dc..dbf4220881a9 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -14,6 +14,7 @@ qcom,ion-heap@8 { /* AUDIO HEAP */ reg = ; memory-region = <&audio_mem>; + qcom,ion-heap-type = "DMA"; }; qcom,ion-heap@27 { /* QSEECOM HEAP */ From 272ab7a1dc37b063c84c38af2f56ecabd1cd59f0 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Fri, 15 Jan 2021 11:48:44 +0530 Subject: [PATCH 1044/1809] ARM: dts: msm: Disable SSPHY autosuspend for Gen3 Auto platforms Add "snps,dis_u3_susphy_quirk" property to disable the SSPHY autosuspend on Gen3 Automotive platforms in order to allow proper host mode system suspend and resume. Change-Id: I509ae6ad6aa6e85eab65c313dc70f0088c0368b7 --- qcom/sm8150-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 81c724f22e49..399606752da6 100644 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -182,6 +182,7 @@ snps,is-utmi-l1-suspend; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; From 1599b5320e4e3a11fc1bad3a267774ea62cac687 Mon Sep 17 00:00:00 2001 From: Harsh Agarwal Date: Thu, 31 Dec 2020 15:27:09 +0530 Subject: [PATCH 1045/1809] ARM: dts: msm: Add multiport USB support for SA8195 This change adds multiport USB controller and PHYs related configuration for the SA8195 platform. Change-Id: I69519d7c58df0262a2d8be3ff60fd4597574e63d --- qcom/sa8195-usb.dtsi | 384 ++++++++++++++++++++++++++++++++++++++++++- qcom/sa8195p.dtsi | 22 +++ 2 files changed, 404 insertions(+), 2 deletions(-) diff --git a/qcom/sa8195-usb.dtsi b/qcom/sa8195-usb.dtsi index 72f24f8fb7cc..e0af3a9f5973 100644 --- a/qcom/sa8195-usb.dtsi +++ b/qcom/sa8195-usb.dtsi @@ -1,5 +1,5 @@ #include - +#include &soc { /* Primary USB port related controller */ usb0: ssusb@a600000 { @@ -183,7 +183,7 @@ usb2_phy1: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e3000 0x110>, - <0x007801f8 0x4>; + <0x007801f8 0x4>; reg-names = "hsusb_phy_base", "phy_rcal_reg"; @@ -200,4 +200,384 @@ qcom,param-override-seq = <0x43 0x70>; qcom,rcal-mask = <0x1e00000>; }; + + /* Tertiary USB port related controller */ + usb2: ssusb@a400000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a400000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + interrupts-extended = <&pdc 59 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_EDGE_RISING>, + <&pdc 71 IRQ_TYPE_EDGE_RISING>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq1", + "ss_phy_irq1", "dm_hs_phy_irq1"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_mp_gdsc>; + clocks = <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_MP_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,ignore-wakeup-src-in-hostmode; + qcom,dual-port; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_2>; + + dwc3@a400000 { + compatible = "snps,dwc3"; + reg = <0x0a400000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, + <&usb2_phy3>, <&usb_qmp_phy1>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,ssp-u3-u0-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed-plus"; + dr_mode = "host"; + }; + }; + + /* Tertiary USB port 0 related High Speed PHY */ + usb2_phy2: hsphy@88e4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + /* Tertiary USB port 0 related QMP PHY */ + usb_qmp_phy0: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l16>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + /* Tertiary USB port 1 related High Speed PHY */ + usb2_phy3: hsphy@88e5000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e5000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + /* Tertiary USB port 1 related QMP PHY */ + usb_qmp_phy1: ssphy@88ec000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ec000 0x1000>, + <0x088ec88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l16>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; }; + diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 13616c51d925..10532f45caff 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -71,3 +71,25 @@ vdda18-supply = <&pm8195_1_l12>; vdda33-supply = <&pm8195_3_l16>; }; + +&usb2_phy2 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; + +&usb_qmp_phy0 { + vdd-supply = <&pm8195_3_l9>; + core-supply = <&pm8195_1_l9>; +}; + +&usb2_phy3 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; + +&usb_qmp_phy1 { + vdd-supply = <&pm8195_3_l9>; + core-supply = <&pm8195_1_l9>; +}; From 1aa1fbb0286fcd3f5ec9eab7e436cdec253ac891 Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Wed, 14 Oct 2020 21:32:29 +0530 Subject: [PATCH 1046/1809] ARM: dts: msm: Add SPS node for sa6155 Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for sa6155. Change-Id: Iba8aaa25b68b218321d544e62f41f95a8ed853e0 --- qcom/sm6150.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 9432834f0e72..b273ebb1a19f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -917,6 +917,11 @@ qcom,rtb-size = <0x100000>; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + pil_scm_pas { compatible = "qcom,pil-tz-scm-pas"; interconnects = <&aggre1_noc MASTER_CRYPTO From 65201c8e8014aba57a91369381b96ebd7328c03e Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Tue, 20 Oct 2020 21:46:02 +0530 Subject: [PATCH 1047/1809] ARM: dts: msm: Add SPS node for sm8150 Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for sm8150. Change-Id: I6b634a4ae2a8e6d9c0281f96e492e907092fc209 --- qcom/sm8150.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 3e8cba84ed8b..f65502372558 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -922,6 +922,11 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 85c0de52eed2dff5c61dce04a3ccb4d6ac94ec8b Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Tue, 9 Feb 2021 18:04:57 -0800 Subject: [PATCH 1048/1809] ARM: dts: msm: Add aux clock property for PCIe EP on sdxlemur PCIe EP Gen4 controller requires the aux clock to run at 16.6MHz instead of 19.2MHz. Add aux clock property to specify the frequency to program to support the Gen4 controller speeds. Change-Id: I04e7520f27334d4a6aa03a72508f500b1175b21c --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 1ef29a7bbc84..3fd3ff3b34ed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -973,6 +973,7 @@ qcom,phy-status-reg2 = <0x1214>; qcom,mhi-soc-reset-offset = <0xb01b8>; qcom,aoss-rst-clr; + qcom,aux-clk = <0x11>; qcom,phy-init = <0x1240 0x01 0x0 0x100c 0x02 0x0 From ab0460954f6aa97e99aaf39608cbdebc97b341eb Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 9 Mar 2021 18:19:44 -0800 Subject: [PATCH 1049/1809] ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur On sdxlemur, PCIe L1.2 exit is about 150us. Therefore update PCIe so that it will program all PCI devices LTR register with 150us. Devices can use this value to deterine if L1.2 should be entered or not based on their latency requirement. Change-Id: Ife11959879bd7c09b9cbe256b5e46933124ad6b1 --- qcom/sdxlemur-mtp-mbb.dtsi | 2 -- qcom/sdxlemur-pcie.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index a88fe19912ae..b0249a0ff28d 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -30,8 +30,6 @@ &pcie0 { qcom,boot-option = <0x1>; - qcom,l1-2-th-scale = <2>; /* 1us */ - qcom,l1-2-th-value = <70>; }; &pm7250b_vadc { diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index b433831ef634..9834159a1112 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -109,6 +109,8 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <150>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From 92018e70f70f7bb9ae4c11f1ce18b3af5c89064f Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 9 Mar 2021 18:25:33 -0800 Subject: [PATCH 1050/1809] ARM: dts: msm: Add version 1 of the memory map for sdxlemur CPE Add the first version of the memory map for the sdxlemur CPE target. This memory map builds off of the existing 1 GB memory map for sdxlemur, but adds 32 MB to the MPSS memory carveout. Change-Id: Ieeb9fd2784b69d5b191bed391492ef31a748c848 --- qcom/sdxlemur-1024mb-cpe.dtsi | 5 +++++ qcom/sdxlemur-mtp-cpe.dts | 2 +- qcom/sdxlemur-v2-mtp-cpe.dts | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) create mode 100644 qcom/sdxlemur-1024mb-cpe.dtsi diff --git a/qcom/sdxlemur-1024mb-cpe.dtsi b/qcom/sdxlemur-1024mb-cpe.dtsi new file mode 100644 index 000000000000..a775863c53c5 --- /dev/null +++ b/qcom/sdxlemur-1024mb-cpe.dtsi @@ -0,0 +1,5 @@ +#include "sdxlemur-1024mb.dtsi" + +&mpss_adsp_mem { + reg = <0x90800000 0x12000000>; +}; diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 0ae7ce387e8f..1c89cc28e220 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -2,7 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" -#include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-1024mb-cpe.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; diff --git a/qcom/sdxlemur-v2-mtp-cpe.dts b/qcom/sdxlemur-v2-mtp-cpe.dts index 42e5d0a51d6b..cfa97dea9bbf 100644 --- a/qcom/sdxlemur-v2-mtp-cpe.dts +++ b/qcom/sdxlemur-v2-mtp-cpe.dts @@ -2,7 +2,7 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-cpe.dtsi" -#include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-1024mb-cpe.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE V2"; From 4f8fa86eae4f6e55d54556c84f29bc7148098d14 Mon Sep 17 00:00:00 2001 From: Akshay Pandit Date: Thu, 27 Aug 2020 17:36:41 +0530 Subject: [PATCH 1051/1809] ARM: dts: msm: Add IPA device configuration for SA8155 Add IPA dtsi configurations for SA8155 gvm target. Change-Id: I5ac51f2271c5f8e531db2a614c1cee29c963e7d6 --- qcom/sa8155-vm-la.dtsi | 110 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 1bdfe711879d..773fd6dd8bd9 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -3,6 +3,16 @@ reg = <0x1 0x6a500000 0x0 0x51400000>; label = "pmem_shared_mem"; }; + + pil_ipa_fw_mem: pil_ipa_fw_region { + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region { + no-map; + reg = <0x0 0x98710000 0x0 0x7000>; + }; }; / { @@ -39,3 +49,103 @@ &sdhc_2 { status = "ok"; }; + +&soc { + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x28000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = + <0 311 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <15>; /* IPA core version = IPAv4.1 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <2>; /* APQ platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,use-ipa-pm; + qcom,ipa-config-is-auto; + qcom,bandwidth-vote-for-ipa; + qcom,manual-fw-load; + qcom,lan-rx-napi; + qcom,tx-wrapper-cache-max-size = <400>; + qcom,tx-napi; + qcom,max_num_smmu_cb = <3>; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <0>; + interconnects = <>; + /* No vote */ + qcom,no-vote = <>; + + /* SVS2 */ + qcom,svs2 = <>; + + /* SVS */ + qcom,svs = <>; + + /* NOMINAL */ + qcom,nominal = <>; + + /* TURBO */ + qcom,turbo = <>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x520 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x521 0x0>; + qcom,iommu-dma = "atomic"; + qcom,additional-mapping = + /* ipa-uc ram */ + <0x1E60000 0x1E60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x522 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x40400000 0x1FC00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_gsi_mem>; + }; + + qcom,ipa_uc { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0x1B>; + qcom,firmware-name = "ipa_uc"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + qcom,veth-ipa { + compatible = "qcom,veth-ipa"; + }; +}; From 35d474bb50f129f3024861a7d5bc723e78f86a59 Mon Sep 17 00:00:00 2001 From: Akshay Pandit Date: Tue, 10 Nov 2020 22:54:32 +0530 Subject: [PATCH 1052/1809] ARM: dts: msm: Specify the irq type and trigger level Specify irq type and trigger level in dtsi as per kernel 5_4 guidelines. Remove support for manua fw load. Change-Id: I1fc5d9e2f6aa7f8193a088de95373779c779de07 --- qcom/sa8155-vm-la.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 773fd6dd8bd9..6370fd731c82 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -61,8 +61,8 @@ <0x1e04000 0x28000>; reg-names = "ipa-base", "gsi-base"; interrupts = - <0 311 0>, - <0 432 0>; + , + ; interrupt-names = "ipa-irq", "gsi-irq"; qcom,ipa-hw-ver = <15>; /* IPA core version = IPAv4.1 */ qcom,ipa-hw-mode = <0>; @@ -70,11 +70,11 @@ qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,use-64-bit-dma-mask; + qcom,ipa-wdi3-over-gsi; qcom,arm-smmu; qcom,use-ipa-pm; qcom,ipa-config-is-auto; qcom,bandwidth-vote-for-ipa; - qcom,manual-fw-load; qcom,lan-rx-napi; qcom,tx-wrapper-cache-max-size = <400>; qcom,tx-napi; From 5165b7a021cb231fbc670fdf4ab1501712a24074 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Mon, 8 Mar 2021 21:31:41 -0800 Subject: [PATCH 1053/1809] ARM: dts: msm: Add pil scm pass node Add the PIL scm pass node for msmnile_gvmq Change-Id: Ia69fe83065a8303250b951422c14240caa00ec43 --- qcom/sa8155-vm-la.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 773fd6dd8bd9..fa18f4f70d7d 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -51,6 +51,10 @@ }; &soc { + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + }; + qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; From 557c875ada3489885bca234a7c5d99cbbf507ddc Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 9 Mar 2021 12:03:21 +0530 Subject: [PATCH 1054/1809] ARM: dts: msm: Enable PCIe0 nodes only for iot variant Enable PCIe0 nodes only for iot variant as HSP attach over PCIe is required to support for IOT variants. Change-Id: I6bc3b5325b40381f4fa4bfc3631a9bbaccba5265 --- qcom/yupik-iot-idp.dtsi | 8 ++++++++ qcom/yupik-pcie.dtsi | 5 +++++ qcom/yupikp-iot-idp.dtsi | 8 ++++++++ 3 files changed, 21 insertions(+) diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 31da5af1d4e3..55e5d0e3bf91 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -1,2 +1,10 @@ #include "yupik-idp.dtsi" #include "qcx6490-cnss.dtsi" + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index a724fab080a6..72baf84b90a6 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -226,6 +226,8 @@ 0x0800 0x00 0x0 0x0844 0x03 0x0>; + status = "disabled"; + pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; }; @@ -268,5 +270,8 @@ , , ; + + status = "disabled"; + }; }; diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi index 90377734afa9..bc2beeb0b0ff 100644 --- a/qcom/yupikp-iot-idp.dtsi +++ b/qcom/yupikp-iot-idp.dtsi @@ -1,2 +1,10 @@ #include "yupikp-idp.dtsi" #include "qcx6490-cnss.dtsi" + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; From ea29705fb0e3ecf1955c73a2aae783e2c9ebb3c5 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 10 Mar 2021 14:23:03 +0530 Subject: [PATCH 1055/1809] ARM: dts: msm: Add Wakeup interrupt controller for sdxnightjar Add wakeup interrupt controller node to support wakeup- capabale interrupts. Change-Id: Ib4b78d2527ea68901dcae949781a1fabbc33cc3a --- bindings/interrupt-controller/qcom,mpm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index 257f2a7da9fc..b998c94d89f1 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -25,6 +25,7 @@ Properties: target compatible flag from below ones. "qcom,mpm-gic-holi" "qcom,mpm-gic-scuba" + "qcom,mpm-gic-sdxnightjar" - interrupts: Usage: required From 9010968e4008336cfca86b1946181f321ba85bc3 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 10 Mar 2021 14:45:09 +0530 Subject: [PATCH 1056/1809] bindings: arm: msm: Add documentation for spm-v2 This change adds binding information for spm-v2. Change-Id: Id1f9e27b28e8da9e0a4351a69b0de77665ac63f5 --- bindings/arm/msm/spm-v2.txt | 173 ++++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 bindings/arm/msm/spm-v2.txt diff --git a/bindings/arm/msm/spm-v2.txt b/bindings/arm/msm/spm-v2.txt new file mode 100644 index 000000000000..d44ab56b9f48 --- /dev/null +++ b/bindings/arm/msm/spm-v2.txt @@ -0,0 +1,173 @@ +* MSM Subsystem Power Manager (spm-v2) + +S4 generation of MSMs have SPM hardware blocks to control the Application +Processor Sub-System power. These SPM blocks run individual state machine +to determine what the core (L2 or Krait/Scorpion) would do when the WFI +instruction is executed by the core. The SAW hardware block handles SPM and +AVS functionality for the cores. + +The devicetree representation of the SPM block should be: + +Required properties + +- compatible: "qcom,spm-v2" +- reg: The physical address and the size of the SPM's memory mapped registers +- qcom,cpu: phandle for the CPU that the SPM block is attached to. This field +is required on only for SPMs that control the CPU. This field is not required +for SPMs that control L2/CCI/L3 +- qcom,saw2-ver-reg: The location of the version register +- qcom,name: The name with which a SPM device is identified by the power +management code. + +---------------------------------------------------- +Non-PSCI targets should follow the rules shown below +---------------------------------------------------- +Required properties for only Non-PSCI targets: + +- qcom,saw2-cfg: SAW2 configuration register +- qcom,saw2-spm-ctl: The SPM control register +- qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM + sequence + +Optional properties for only Non-PSCI targets +- reg-names: Register names for the physical address required if spm device + has more than one physical addressed to be mapped. Allowed register + names are: "saw-base", "q2s", "hw-flush", "slpreq" +- qcom,saw2-avs-ctl: The AVS control register +- qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS + controller requests +- qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change + after sending the voltage command to the PMIC +- qcom,saw2-avs-limit: The AVS limit register +- qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values + between AVS controller requests +- qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS + index to send the PMIC data to +- qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing + voltage +- qcom,vctl-port-ub: The PVC (PMIC Virtual Channel) port used for changing + voltage +- qcom,phase-port: The PVC port used for changing the number of phases +- qcom,pfm-port: The PVC port used for enabling PWM/PFM modes +- qcom,cpu-vctl-mask: Mask of cpus, whose voltage the spm device can control. + Depricated: Replaced with cpu-vctl-list when cpu phandles are available. +- qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device + can control. +- qcom,use-qchannel-for-pc: Boolean property to specify if qchannel should be + ignored when entering power collapse. If this property is set qchannel + will not be ignored in power collapse. +- qcom,supports-rpm-hs: Indicates that this SPM instance allow handshake with +RPM processor when executing the sleep command in the SPM sequence. Supported +only on SAW2 v3.0 and above. +- qcom,use-spm-clock-gating: This boolean property is used to indicate that + the SPM needs to be used for clock gating. Using the SPM for clock + gating would result in auto clock gating being disabled. Use this on + targets that do not support or do not use auto clock gating. +- qcom,use-qchannel-for-wfi: This boolean property is used to indicate + that the SPM gets triggerd by the qchannel and not by means of + wfi. So a wfe could trigger a spm for clock gating as well. +- modes: Lists all the available low power modes for the device + +Second level properties for modes + +Required properties (if modes node is available) +- qcom,label: Specifies the mode name such as: + qcom,saw2-spm-cmd-wfi: WFI mode + qcom,saw2-spm-cmd-ret: Retention mode + qcom,saw2-spm-cmd-spc: Standalone PC mode + qcom,saw2-spm-cmd-pc: Power Collapse mode + qcom,saw2-spm-cmd-gdhs: GDHS mode +- qcom,sequence: Specifies sequence for the low power mode +Optional properties +- qcom,pc_mode: Specifies pc_mode bit should be set in the SPM control register +- qcom,ret_mode: Specifies ret_mode bit should be set in the SPM control register +- qcom,spm_en: Specifies spm_en bit should be set in the SPM control register +- qcom,isar: Specifies isar bit should be set in the SPM control register + Specify this property only if SPM should retain its start address at + the end of the program. +- qcom,slp_cmd_mode: Specifies slp_cmd_mode bit should be set in SPM control register. + Adding this property results in SPM handshaking with RPM. Please remove + the RPM handshake command from the sleep sequence, replace that with + Sleep without RPM handshake command. +- qcom,event_sync: Specifies event_sync byte should be set in SPM control + register. + +---------------------------------------------------- +PSCI targets should follow the rules shown below +---------------------------------------------------- +Optional properties for only PSCI targets: + +- qcom,saw2-avs-ctl: The AVS control register +- qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS + controller requests +- qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change + after sending the voltage command to the PMIC +- qcom,saw2-avs-limit: The AVS limit register +- qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values + between AVS controller requests +- qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing + voltage +- qcom,vctl-port-ub: The PVC (PMIC Virtual Channel) port used for changing + voltage +- qcom,phase-port: The PVC port used for changing the number of phases +- qcom,pfm-port: The PVC port used for enabling PWM/PFM modes +- qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device + can control. + + +Example 1: + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,cpu = <&CPU0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x1b>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,mode0 { + qcom,label = "qcom,saw2-spm-cmd-wfi"; + qcom,sequence = [03 0b 0f]; + qcom,spm_en; + }; + + qcom,mode1 { + qcom,label = "qcom,saw2-spm-cmd-spc"; + qcom,sequence = [00 20 50 80 60 70 10 92 + a0 b0 03 68 70 3b 92 a0 b0 + 82 2b 50 10 30 02 22 30 0f]; + qcom,spm_en; + qcom,pc_mode; + }; + + qcom,mode2 { + qcom,label = "qcom,saw2-spm-cmd-pc"; + qcom,sequence = [00 20 10 92 a0 b0 07 3b 92 + a0 b0 82 10 30 02 22 30 0f]; + qcom,spm_en; + qcom,pc_mode; + }; + }; + +Example 2: + qcom,spm@9A10000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x9A10000 0x1000>; + qcom,name = "system-cbf"; /* CBF SAW */ + qcom,saw2-ver-reg = <0xFD0>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1100>; + qcom,pfm-port = <0x2>; +}; + From 2e35bdb99339066ff9cade54ef411fa219904a7e Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 15 Feb 2021 13:19:21 +0530 Subject: [PATCH 1057/1809] ARM: dts: msm: Adding support to send messages to AOP using QMP transport This is require to set Cap frequency of DDR based on SKU. Change-Id: I7ed8906693c6fbe93f007bbaabe31906fe759cf1 --- bindings/arm/msm/aop-set-ddr.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 bindings/arm/msm/aop-set-ddr.txt diff --git a/bindings/arm/msm/aop-set-ddr.txt b/bindings/arm/msm/aop-set-ddr.txt new file mode 100644 index 000000000000..df029d1844ff --- /dev/null +++ b/bindings/arm/msm/aop-set-ddr.txt @@ -0,0 +1,17 @@ +AOP set ddr interface: +----------------- + +AOP set ddr is an interface to send data to the Always on +processor using QMP. + +Required properties : +- compatible : must be "qcom,aop-set-ddr-freq" +- mboxes : list of QMP mailbox phandle and channel identifier tuples +- mbox-names : names of the listed mboxes + +Example : + aop-set-ddr-freq { + compatible = "qcom,aop-set-ddr-freq"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; From 982bac1080505b6f9550ebfa90cc2f11cf0f63db Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 8 Mar 2021 17:19:05 +0530 Subject: [PATCH 1058/1809] ARM: dts: msm: Add set_ddr_capped_freq device node interface for SA8155 Add set_ddr_capped_freq interface to send data to the AOP. Change-Id: I54bfff0425a3a14a9ab6600a9ef3bcaa2c64b4bb --- qcom/sa8155.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 7bab1ef03a9e..e3e25b528d3a 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -144,6 +144,11 @@ }; }; + aop-set-ddr-freq { + compatible = "qcom,aop-set-ddr-freq"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; &usb2_phy0 { From d46aff0da5206fec13f4fdc89e0c2b633ab39d36 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Wed, 10 Mar 2021 18:08:09 +0530 Subject: [PATCH 1059/1809] ARM: dts: msm: STMMAC crash fix stmmac fix crash due to voting by the Ethernet smmmu atomic attribute. Change-Id: Iacb90b0816505e1ca73658c09e813c63d672a0d0 --- qcom/sa8155.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 7bab1ef03a9e..ce4c6df8b466 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -78,15 +78,6 @@ <&tlmm 124 2>; interrupt-names = "macirq", "eth_lpi", "phy-intr"; - qcom,msm-bus,name = "emac"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <98 512 0 0>, <1 781 0 0>, /* No vote */ - <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ - <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ - <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ - qcom,bus-vector-names = "0", "10", "100", "1000"; snps,tso; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; @@ -139,7 +130,6 @@ ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; iommus = <&apps_smmu 0x3C0 0x0>; - qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; }; From f7919185e58087b9ebb975dd0cdf6fd169cbe968 Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Wed, 10 Mar 2021 22:45:23 +0530 Subject: [PATCH 1060/1809] ARM: dts: msm: Remove pwr_evt_irq for SA6155 and SA8155 USB3 cores SA6155 and SA8155 USB3 cores have SSPHY autosuspend disabled. Remove pwr_evt_irq for these cores to avoid race with forceful suspend. Change-Id: Ibd4024933c38778e96bd9fd6d7c75f6b010c0340 --- qcom/sm6150-usb.dtsi | 3 +-- qcom/sm8150-usb.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/sm6150-usb.dtsi b/qcom/sm6150-usb.dtsi index f275a536c535..471a6f58f6eb 100644 --- a/qcom/sm6150-usb.dtsi +++ b/qcom/sm6150-usb.dtsi @@ -18,10 +18,9 @@ dma-ranges; interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 399606752da6..347a8db118aa 100644 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -139,10 +139,9 @@ dma-ranges; interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; qcom,default-mode-host; From 413bc64a129e1c59f60d6e8fbd5996ce3b792642 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Tue, 9 Mar 2021 22:50:52 +0530 Subject: [PATCH 1061/1809] ARM: dts: msm:Reduce CMA region size Reduce CMA region size for qseecom. Change-Id: I54a5ca994aa526151205477a9d67c8db3520fd7e --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 99678ce50275..2f8710fd492c 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -58,7 +58,7 @@ alloc-ranges = <0x00000000 0xffffffff>; reusable; alignment = <0x400000>; - size = <0x1400000>; + size = <0x400000>; }; qseecom_ta_mem: qseecom_ta_region { From 3316b460f79da34e193d99cc10d81c89da738791 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Wed, 24 Jun 2020 15:19:48 +0800 Subject: [PATCH 1062/1809] bindings: can: Add device-tree bindings for qti-can driver Add documentation describing the device-tree properties for qti-can driver. This documentation is ported from msm-4.14 commit "984fcad2". Change-Id: Iea1bb507adb0ab6654c992efa9d1a5610a449555 --- bindings/net/can/qti-can.txt | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 bindings/net/can/qti-can.txt diff --git a/bindings/net/can/qti-can.txt b/bindings/net/can/qti-can.txt new file mode 100644 index 000000000000..cbb4376be0fe --- /dev/null +++ b/bindings/net/can/qti-can.txt @@ -0,0 +1,51 @@ +* QTI CAN driver * + + +Required properties: + - compatible: Should be "qcom,renesas,rh850" or "qcom,nxp,mpc5746c". + - reg: Should contain SPI chip select. + - interrupt-parent: Should specify interrupt controller for the interrupt. + - interrupts: Should contain IRQ line for the CAN controller. + - spi-max-frequency: Should contain maximum spi clock frequency for slave device + - qcom,clk-freq-mhz : The frequency at which the CAN clock should be configured. + - qcom,max-can-channels : Maximum number of CAN channels supported by the controller. + + +Optional properties: + - qcom,reset-gpio: Reference to the GPIO connected to the reset input. + - pinctrl-names : Names corresponding to the numbered pinctrl states. + - pinctrl-0 : This explains the active state of the GPIO line. + - pinctrl-1 : This explains the suspend state of the GPIO line. + - qcom,bits-per-word: Indicate how many bits are in a SPI frame. e.g.: 8, 16, 32. + Default to 16. + - qcom,reset-delay-msec: Delay in milliseconds to be applied after resetting the chip. + This is applicable only if the reset-gpio is specified. Default value is 1 ms. + - qcom,support-can-fd: Whether CAN FD mode is supported or not. + - qcom,can-fw-cmd-timeout-req: Whether a timeout is required if we don't get a response from + the firmware after flash write. + - qcom,can-fw-cmd-timeout-ms: The duration after which timeout will happen if we don't get a + response from the firmware. + - qcom,rem-all-buffering-timeout-ms: The duration after which timeout will happen if we don't get a + response from the firmware while trying to remove all the buffered frames IDs from flash. + + +Example: + +can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + spi-max-frequency = <9600000>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <87 0>; + qcom,reset-gpio = <&tlmm_pinmux 89 0x1>; + qcom,clk-freq-mhz = <20000000>; + qcom,max-can-channels = <2>; + qcom,bits-per-word = <8>; + qcom,reset-delay-msec = <150>; + qcom,can-fw-cmd-timeout-req; + qcom,can-fw-cmd-timeout-ms = <400>; + qcom,rem-all-buffering-timeout-ms = <2000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&can_rst_on>; + pinctrl-1 = <&can_rst_off>; +}; From 3c6d14c7a923235c3603966f480edd8ecddf39e9 Mon Sep 17 00:00:00 2001 From: Wei Yang Date: Thu, 13 Aug 2020 17:52:31 +0800 Subject: [PATCH 1063/1809] ARM: dts: msm: add wlan converged node for SA81x5 Add cnss-qca-converged node for SA81x5 to support QCA6574/QCA6595/QCA6696. Change-Id: Idabe95d7dcc68cb4336da127bb5b0b2fc7943efc --- bindings/cnss/cnss-wlan.txt | 37 +++++ qcom/sa8155-cnss.dtsi | 287 ++++++++++++++++++++++++++++++++++++ qcom/sa8195p-cnss.dtsi | 285 +++++++++++++++++++++++++++++++++++ 3 files changed, 609 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index bc7df786903c..05e7db9fd7f5 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -17,6 +17,7 @@ Required properties: "qcom,cnss-qca6390" for QCA6390 device "qcom,cnss-qca6490" for QCA6490 device "qcom,cnss-wcn7850" for WCN7850 device + "qcom,cnss-qca-converged" for converged QCA devices - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications - vdd-wlan-supply: phandle to the regulator device tree node - pinctrl-names: Names corresponding to the numbered pinctrl states @@ -98,6 +99,18 @@ Optional properties: without sub-nodes. - qcom,converged-dt: Boolean property to decide whether it supports multiple WLAN devices using the same DT node with sub-nodes. + - qcom,bus-type: U32 property to specify the bus type, is required when + 'qcom,converged-dt' being present. + - wlan_vregs: String array to decide which vregs are required, is required + when 'qcom,converged-dt' being present. + +List of chip specific sub nodes: + - chip_cfg@X: represent chip specific configurations + Each sub node has the following required properties: + - wlan_vregs: String array to decide which vregs are required, property + being present but no values means no additional vregs. + - supported-ids: U32 array to decide which device ids are supported by + sub node. Example: @@ -117,3 +130,27 @@ Example: qcom,mhi = <&mhi_wlan>; qcom,cap-tsf-gpio = <&tlmm 126 1>; }; + + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + qcom,converged-dt; + qcom,bus-type=<0>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + + chip_cfg@1 { + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + }; + }; diff --git a/qcom/sa8155-cnss.dtsi b/qcom/sa8155-cnss.dtsi index c6189b4e6c29..ee72cce892d3 100644 --- a/qcom/sa8155-cnss.dtsi +++ b/qcom/sa8155-cnss.dtsi @@ -1,5 +1,11 @@ &soc { + /* Rome 3.3V supply */ + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + /* PWR_CTR2_VDD_1P8 supply */ vreg_conn_1p8: vreg_conn_1p8 { compatible = "regulator-fixed"; @@ -44,9 +50,290 @@ qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; }; + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8150_1_s6>; + vdd-wlan-rfa1-supply = <&pm8150_2_s4>; + vdd-wlan-rfa2-supply = <&pm8150_2_s5>; + vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10 1>; + + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + }; }; &qupv3_se13_4uart { status = "ok"; }; +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; diff --git a/qcom/sa8195p-cnss.dtsi b/qcom/sa8195p-cnss.dtsi index 9739eeb3f339..251800fa1cf6 100644 --- a/qcom/sa8195p-cnss.dtsi +++ b/qcom/sa8195p-cnss.dtsi @@ -42,9 +42,294 @@ qcom,bt-vdd-rfa2-config = <1900000 1900000 450000 0>; }; + /* Rome 3.3V supply */ + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8195_1_s5>; + vdd-wlan-rfa1-supply = <&pm8195_1_s2>; + vdd-wlan-rfa2-supply = <&pm8195_2_s5>; + vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10 1>; + + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; }; &qupv3_se13_4uart { status = "ok"; }; +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; From a9d7a8c8cb7b09a0501b5b9dbf3b11acdda1835a Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Mon, 17 Aug 2020 13:06:18 +0800 Subject: [PATCH 1064/1809] dt-bindings: ptp: Add virtual ptp memory entry Add virtual ptp memory address and size. Change-Id: Ib448c16c3b6fba8983e1ec4df5a0efdd250aaf18 --- bindings/ptp/qcom,ptp_virtual.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 bindings/ptp/qcom,ptp_virtual.txt diff --git a/bindings/ptp/qcom,ptp_virtual.txt b/bindings/ptp/qcom,ptp_virtual.txt new file mode 100644 index 000000000000..5f48df0bb6f2 --- /dev/null +++ b/bindings/ptp/qcom,ptp_virtual.txt @@ -0,0 +1,17 @@ +* Qcom virtual gPTP Data based shared memory IPC + +Required properties: +- compatible: should contain the core compatibility string + and the SoC compatibility string. The SoC + compatibility string is to handle SoC specific + hardware differences. + Core compatibility string: + "qcom,ptp_virtual" +- reg: address and length of the shared memory for gPTP data + +Example: + +ptp_virtual { + compatible = "qcom,ptp_virtual"; + reg = <0xeb600000 0x1000>; +}; From e3824d74a82fd290a80bf1443d58601d3c682b3a Mon Sep 17 00:00:00 2001 From: ngong Date: Wed, 18 Nov 2020 18:52:59 +0800 Subject: [PATCH 1065/1809] ARM: dts: msm: Add wlan device tree for SA8195 VM Add wlan device tree to support wlan for SA8195 VM. Change-Id: I910a693dc0fa41005cf5fbe042af24105d5244e9 --- qcom/sa8195-vm.dtsi | 311 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 311 insertions(+) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index a8210dfbd45c..9560d2c19ed9 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -117,6 +117,300 @@ }; &soc { + /* Rome 3.3V supply */ + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8195_1_s5>; + vdd-wlan-rfa1-supply = <&pm8195_1_s2>; + vdd-wlan-rfa2-supply = <&pm8195_2_s5>; + vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -533,6 +827,23 @@ status = "ok"; }; +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "bypass"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; + &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; From 15633c4068e4cbb4819af93be9f41e6e1b67b3c6 Mon Sep 17 00:00:00 2001 From: Yingjie Zhu Date: Wed, 18 Nov 2020 22:02:28 +0800 Subject: [PATCH 1066/1809] ARM: dts: msm: Add Bluetooth power node for SA8195 VM Add Bluetooth device tree to support blueooth for SA8195 VM. Change-Id: I6a3c8e4c6ebd5ff2be7057b051f16ecde27e7cec --- qcom/sa8195-vm.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index a8210dfbd45c..d4ed8b3c1417 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -421,6 +421,28 @@ qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>; }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pm8195_1_s5>; + qcom,bt-vdd-rfa1-supply = <&pm8195_1_s2>; + qcom,bt-vdd-rfa2-supply = <&pm8195_2_s5>; + qcom,bt-vdd-rfa3-supply = <&pm8195_2_l7>; + + /* */ + qcom,bt-vdd-aon-config = <1000000 1000000 0 0>; + qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; + }; }; ®ulator { From 6fe876f46ad0c26d614c4eb3660e2c46d26808d6 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Mon, 1 Mar 2021 20:50:33 +0530 Subject: [PATCH 1067/1809] ARM: dts: msm: Increase the S11B/S2E max voltage for Lahaina Increase the smps11b max voltage to 1.012V and smps2e max voltage to 1.020V as per the WLAN/BT consumer requirement. Change-Id: Ia9b9a6826e65d64d240ede834bdf0f02edb1a54b --- qcom/lahaina-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-regulators.dtsi b/qcom/lahaina-regulators.dtsi index c85eba7a1371..315753d192ca 100644 --- a/qcom/lahaina-regulators.dtsi +++ b/qcom/lahaina-regulators.dtsi @@ -134,7 +134,7 @@ regulator-name = "pm8350_s11"; qcom,set = ; regulator-min-microvolt = <752000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <1012000>; qcom,init-voltage = <952000>; }; }; @@ -827,7 +827,7 @@ regulator-name = "pmr735a_s2"; qcom,set = ; regulator-min-microvolt = <500000>; - regulator-max-microvolt = <976000>; + regulator-max-microvolt = <1020000>; qcom,init-voltage = <852000>; }; }; From 7804ef86dc5e58efb7fbcdff80efd44d7ab55d4f Mon Sep 17 00:00:00 2001 From: Sandeep Sadula Date: Fri, 26 Feb 2021 18:16:18 +0530 Subject: [PATCH 1068/1809] ARM: dts: msm: Qseecom_ta_region removed from CMA Qseecom_ta_region removed from CMA to gain free memory optimization. Change-Id: I368655a5e1605d3f8c493b8c825edc4bae351b05 --- qcom/sdxnightjar-ion.dtsi | 5 ----- qcom/sdxnightjar.dtsi | 8 -------- 2 files changed, 13 deletions(-) diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 173d5c56a634..1a35044d6b30 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -23,11 +23,6 @@ qcom,ion-heap-type = "DMA"; }; - qcom,ion-heap@19 { /* QSEECOM TA HEAP */ - reg = ; - memory-region = <&qseecom_ta_mem>; - qcom,ion-heap-type = "DMA"; - }; }; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 6967e0c66845..1238ce10e2af 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -61,14 +61,6 @@ size = <0x400000>; }; - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x400000>; - }; - dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; From 4e8bc51c1d9626cb17376b764118bfc2d3fb1b37 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 3 Mar 2021 11:27:11 +0530 Subject: [PATCH 1069/1809] ARM: dts: msm: Superset common regulators votes change for Lahaina These changes are required to have superset common voltages for HST and HSP for Lahaina HST attachment. It is recommended from pmic team to use INT_MAX for max voltage vote. So max voltage vote for S1C & S12B is updated to INT_MAX. Change-Id: Ic613b74a8a768a6a55a9bf506440788f873c5f1b --- qcom/lahaina.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 9c50d2d9fc3f..63c090bc6d1f 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5396,15 +5396,15 @@ qcom,same-dt-multi-dev; vdd-wlan-aon-supply = <&S2E>; - qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; + qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>; vdd-wlan-dig-supply = <&S11B>; - qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>; + qcom,vdd-wlan-dig-config = <1012000 1012000 0 0 1>; vdd-wlan-io-supply = <&S10B>; qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; vdd-wlan-rfa1-supply = <&S1C>; - qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1900000 1952000 0 0 1>; vdd-wlan-rfa2-supply = <&S12B>; - qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <1350000 1360000 0 0 1>; wlan-ant-switch-supply = <&L7E>; qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; From 9894bfa15922661836acace3c9c8b024cf034b1a Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Fri, 12 Mar 2021 14:06:06 +0530 Subject: [PATCH 1070/1809] ARM: dts: msm: Enable IOMMU Geometry for WLAN Enable IOMMU Geometry for WLAN. Change-Id: I2260a3df62418d4668dbf0c8540ecd89619f21e8 --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 5822ed605940..aa56014a707f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1224,6 +1224,7 @@ qcom,iommu-dma = "fastmap"; qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; qcom,cmd_db_name = "smpb7"; cnss-daemon-support; From 606c477f9ba37141f7ad54611a3cc0890b5e9b1e Mon Sep 17 00:00:00 2001 From: Song Gao Date: Fri, 14 Aug 2020 16:49:58 +0800 Subject: [PATCH 1071/1809] ARM: dts: msm: Add bluetooth power node for sa8155 virtual machine Add bluetooth device tree to support bluetooth for SA8155 VM. Change-Id: Idf5d546067c200fcce6344f97f92cb8a27d49e4a --- qcom/sa8155-vm.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 9b8a33d19093..9bbe5ccbbec3 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -394,6 +394,28 @@ offset = <512>; }; }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pm8150_1_s6>; + qcom,bt-vdd-rfa1-supply = <&pm8150_2_s4>; + qcom,bt-vdd-rfa2-supply = <&pm8150_2_s5>; + qcom,bt-vdd-rfa3-supply = <&pm8150_2_l15>; + + /* */ + qcom,bt-vdd-aon-config = <1055000 1055000 0 0>; + qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; + }; }; ®ulator { From 11a56625356c8342bf55f2d8bde9cd7c344a18d1 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 23 Dec 2020 17:06:48 +0530 Subject: [PATCH 1072/1809] ARM: dts: qcom: Enable thermal zones and cooling devices for sa8155 Enable TSENS different thermal zones like userspace thermal zones, CPU isolation thermal zones, gpu max thermal zones, CDSP, NPU thermal zones and pmic alarm thermal zones etc. and different cooling devices for sa8155. Change-Id: Ibdeef073eb40e00c34b5b838907f762b69a5539c --- qcom/sa8155-pmic-overlay.dtsi | 108 +++- qcom/sa8155.dtsi | 135 +++++ qcom/sm8150-gpu.dtsi | 2 + qcom/sm8150-thermal.dtsi | 922 ++++++++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 12 + 5 files changed, 1178 insertions(+), 1 deletion(-) create mode 100644 qcom/sm8150-thermal.dtsi diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi index bcfa20c8d95a..8c84740ed630 100644 --- a/qcom/sa8155-pmic-overlay.dtsi +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -133,7 +133,7 @@ pm8150_1_gpios: &pm8150_gpios { }; }; -#include +#include &thermal_zones { pm8150_2_temp_alarm: pm8150_2_tz { @@ -162,6 +162,112 @@ pm8150_1_gpios: &pm8150_gpios { }; }; + cooling-maps { + /* + * trip0 cooling map is dummy node to enable + * passive polling on trip0 violation. + */ + trip0_cpu0 { + trip = <&pm8150_2_trip0>; + cooling-device = <&CPU0 0 0>; + }; + + trip1_cpu0 { + trip = <&pm8150_2_trip1>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm8150_2_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; }; + pm8150_tz { + cooling-maps { + /* + * trip0 cooling map is dummy node to enable + * passive polling on trip0 violation. + */ + trip0_cpu0 { + trip = <&pm8150_trip0>; + cooling-device = <&CPU0 0 0>; + }; + + trip1_cpu0 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm8150_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; }; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index ce4c6df8b466..c20c54172917 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -204,3 +204,138 @@ #include "camera/sa8155-camera.dtsi" #include "camera/sa8155-camera-sensor.dtsi" #include "sa8155-audio.dtsi" + +&lmh_dcvs1 { + isens_vref_0p8-supply = <&pm8150_1_l5_ao>; + isens_vref_1p8-supply = <&pm8150_1_l12_ao>; +}; + +&thermal_zones { + gpuss-max-step { + trips { + gpu-trip0 { + temperature = <105000>; + }; + }; + }; + + pop-mem-step { + status = "disabled"; + }; + + npu-step { + trips { + npu-trip0 { + temperature = <105000>; + }; + }; + }; + + cpu-0-0-step { + trips { + cpu00-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-1-step { + trips { + cpu01-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-2-step { + trips { + cpu02-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-3-step { + trips { + cpu03-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-0-step { + trips { + cpu10-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-1-step { + trips { + cpu11-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-2-step { + trips { + cpu12-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-3-step { + trips { + cpu13-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-4-step { + trips { + cpu14-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-5-step { + trips { + cpu15-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-6-step { + trips { + cpu16-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-7-step { + trips { + cpu17-config { + temperature = <115000>; + }; + }; + }; + + q6-hvx-step { + trips { + q6-hvx-step0 { + temperature = <105000>; + }; + + q6-hvx-step1 { + temperature = <115000>; + }; + }; + }; +}; diff --git a/qcom/sm8150-gpu.dtsi b/qcom/sm8150-gpu.dtsi index 5263fba4494d..6538058362f5 100644 --- a/qcom/sm8150-gpu.dtsi +++ b/qcom/sm8150-gpu.dtsi @@ -39,6 +39,8 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size + #cooling-cells = <2>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, diff --git a/qcom/sm8150-thermal.dtsi b/qcom/sm8150-thermal.dtsi new file mode 100644 index 000000000000..2b86a5af85a7 --- /dev/null +++ b/qcom/sm8150-thermal.dtsi @@ -0,0 +1,922 @@ +#include + +&cpufreq_hw { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + isens_vref_0p8-supply = <&pm8150_l5_ao>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8150_l12_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; + +&soc { + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x8>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x8>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem0 { + qcom,instance-id = <0x0>; + + modem0_pa: modem0_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem0_proc: modem0_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem0_current: modem0_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem0_skin: modem0_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem0_vdd: modem0_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + slpi { + qcom,instance-id = <0x53>; + + slpi_vdd: slpi_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cmpss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-vec-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-scl-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpuss-max-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 15>, <&tsens1 11>; + sensor-aggregation = ; + + trips { + gpu_trip0: gpu-trip0 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_trip0>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + pop-mem-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "step_wise"; + + trips { + pop_trip: pop-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + pop_cdev4 { + trip = <&pop_trip>; + cooling-device = + <&CPU4 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + npu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "step_wise"; + + trips { + npu_trip0: npu-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + npu_cdev { + trip = <&npu_trip0>; + cooling-device = + <&msm_npu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + + trips { + cpu10_config: cpu10-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + + trips { + cpu11_config: cpu11-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + + trips { + cpu12_config: cpu12-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + + trips { + cpu13_config: cpu13-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + + trips { + cpu14_config: cpu14-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + + trips { + cpu15_config: cpu15-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + + trips { + cpu16_config: cpu16-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + + trips { + cpu17_config: cpu17-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + + trips { + q6_hvx_step0: q6-hvx-step0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_step1: q6-hvx-step1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + hvx_cdev_lvl0 { + trip = <&q6_hvx_step0>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 6>; + }; + + hvx_cdev_lvl1 { + trip = <&q6_hvx_step1>; + cooling-device = <&msm_cdsp_rm 6 6>; + }; + }; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index f65502372558..9984e6058bf7 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -57,6 +57,8 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -79,6 +81,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -96,6 +99,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -113,6 +117,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -130,6 +135,8 @@ dynamic-power-coefficient = <374>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -147,6 +154,7 @@ dynamic-power-coefficient = <374>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -164,6 +172,7 @@ dynamic-power-coefficient = <374>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -181,6 +190,8 @@ dynamic-power-coefficient = <431>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -2875,3 +2886,4 @@ #include "sm8150-usb.dtsi" #include "sm8150-gpu.dtsi" #include "sm8150-npu.dtsi" +#include "sm8150-thermal.dtsi" From 836e490a13eaab21195a5f664ec9070110381b8e Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 1 Mar 2021 17:15:27 +0530 Subject: [PATCH 1073/1809] ARM: dts: msm: Add CX and MX SDPM configuration for YUPIK Add CX SDPM configuration to monitor Camera, Display clocks. Add MX SDPM configuration to monitor Camera, Display clocks. Change-Id: I8c08a41e5d37f8768c661a79967b0e7e3509a489 --- qcom/yupik-thermal.dtsi | 156 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 44d153ae5721..c177df006ec2 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -61,6 +61,40 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <1 4>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <0 2>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &qmi_tmd { @@ -1294,4 +1328,126 @@ }; }; }; + + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_cpu4 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu4_isolate 0 0>; + }; + + mx_pe_cdev_cpu5 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu5_isolate 0 0>; + }; + + mx_pe_cdev_cpu6 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu6_isolate 0 0>; + }; + + mx_pe_cdev_cpu7 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu7_isolate 0 0>; + }; + + mx_pe_cdev_cdsp { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_gpu { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_modem { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config4>; + cooling-device = <&msm_gpu 0 0>; + }; + }; + }; }; From c7128aa64135b719c2199900bfaeab1f27a01c28 Mon Sep 17 00:00:00 2001 From: Amir Samuelov Date: Thu, 11 Mar 2021 14:25:24 +0200 Subject: [PATCH 1074/1809] ARM: dts: msm: spcom: add vreg_sp and gpio_sp Add SPU regulators. Change-Id: Ic40460282cf5e4963d7de99a8c2363693e09e35e --- qcom/lahaina.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 9c50d2d9fc3f..97dc222da440 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5258,6 +5258,9 @@ qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>; qcom,boot-enabled; status = "ok"; + + vreg_sp-supply = <&spss_vreg>; + gpio_sp-supply = <&spss_gpio_vreg>; }; spss_utils: qcom,spss_utils { From bc4e5faf78b541189dde04593ed4fdabf7ee97ca Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Mon, 17 Aug 2020 13:08:32 +0800 Subject: [PATCH 1075/1809] ARM: dts: qcom: Add virtual ptp for sa8155 vm Add virtual ptp for sa8155 vm. Change-Id: Ib9d03a021241f4d0077ddaa4ac28635dd8730ab5 --- qcom/sa8155-vm.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 9b8a33d19093..995c58dc6860 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -225,6 +225,11 @@ ; }; + ptp_virtual { + compatible = "qcom,ptp_virtual"; + reg = <0xeb600000 0x1000>; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; From 892c127242bd1b2c0fa9ff1016b2f839c315d153 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Wed, 24 Jun 2020 10:54:38 +0800 Subject: [PATCH 1076/1809] ARM: dts: qcom: Add qti-can device tree node for sa8155 Add qti-can device node for sa8155. Change-Id: I0f3a813f61b4f8e8efa0bfb0793aac24e9a570f0 --- qcom/sa8155-adp-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index 544919ee0573..9f83b3860f0f 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -8,6 +8,23 @@ status = "ok"; }; +&qupv3_se0_spi { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; From a26d629ecdea64922f05929f08f90d5ba3254e13 Mon Sep 17 00:00:00 2001 From: ngong Date: Thu, 17 Sep 2020 15:53:07 +0800 Subject: [PATCH 1077/1809] ARM: dts: msm: Add wlan device tree for SA8155 VM Add wlan device tree to support wlan for SA8155 VM. Change-Id: I9a7c51721205194adbcfe92552bc9e43ee4311d7 --- qcom/sa8155-vm.dtsi | 307 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 307 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 9b8a33d19093..7349875a86f2 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -119,6 +119,34 @@ }; &soc { + /* Rome 3.3V supply */ + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + VDD_CX_LEVEL: VDD_MMCX_LEVEL: S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { compatible = "qcom,stub-regulator"; @@ -129,6 +157,285 @@ = ; }; + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8150_1_s6>; + vdd-wlan-rfa1-supply = <&pm8150_2_s4>; + vdd-wlan-rfa2-supply = <&pm8150_2_s5>; + vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, From 42311f1c814030bb27975493d230df52021c7af1 Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Mon, 15 Mar 2021 08:26:37 +0530 Subject: [PATCH 1078/1809] ARM: dts: qcom: remove audio drivers not used for sdxnightjar Remove msm-pcm-no-irq driver. Change-Id: I196306b80d6a6ed0b65ce5cf371464cd252f5f36 --- qcom/sdxnightjar-audio.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/sdxnightjar-audio.dtsi b/qcom/sdxnightjar-audio.dtsi index 52b654e82655..4716f395a3a2 100644 --- a/qcom/sdxnightjar-audio.dtsi +++ b/qcom/sdxnightjar-audio.dtsi @@ -48,15 +48,13 @@ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, <&loopback>, <&hostless>, <&afe>, <&routing>, - <&pcm_dtmf>, <&host_pcm>, - <&pcm_noirq>; + <&pcm_dtmf>, <&host_pcm>; asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-pcm-hostless", "msm-pcm-afe", "msm-pcm-routing", - "msm-pcm-dtmf", "msm-voice-host-pcm", - "msm-pcm-dsp-noirq"; + "msm-pcm-dtmf", "msm-voice-host-pcm"; asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, <&dtmf_tx>, <&rx_capture_tx>, <&rx_playback_rx>, From e49751d657143aa3ba0c4aff0e9a072d02633d19 Mon Sep 17 00:00:00 2001 From: priyankar Date: Mon, 1 Mar 2021 15:55:24 +0530 Subject: [PATCH 1079/1809] ARM: dts: msm: Increase voltage for S11B and S1C These changes are required to have common voltages for HST and HSP w.r.t lahaina. Change-Id: I9d4ccd5635a16bb4a1fde0ec225ab553da184f0b --- qcom/lahaina.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 97dc222da440..f545a643d3bd 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5658,10 +5658,10 @@ qcom,bt-vdd-rfa2-supply = <&S12B>; qcom,bt-vdd-asd-supply = <&L7E>; - qcom,bt-vdd-aon-config = <950000 950000 0 1>; - qcom,bt-vdd-dig-config = <950000 950000 0 1>; - qcom,bt-vdd-rfa1-config = <1880000 1880000 0 1>; - qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>; + qcom,bt-vdd-aon-config = <1012000 1012000 0 1>; + qcom,bt-vdd-dig-config = <1012000 1012000 0 1>; + qcom,bt-vdd-rfa1-config = <1900000 1952000 0 1>; + qcom,bt-vdd-rfa2-config = <1350000 1360000 0 1>; qcom,bt-vdd-asd-config = <2800000 2800000 0 1>; }; From a6b81968b96c03b0996b0432a9574be56caf596b Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Thu, 11 Mar 2021 17:34:57 +0530 Subject: [PATCH 1080/1809] ARM: dts: msm: Add memshare for yupik Memshare driver allocates and share the memory with the modem clients for their use. The device tree information for memshare driver on yupik are added to specify client details. Change-Id: Iabb9036668e36bb7d0fe1bc937e5a86935642712 --- qcom/yupik.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 5822ed605940..2661de21cfdf 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -517,6 +517,19 @@ label = "dfps_data_memory"; }; + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + /* + * Memory shared with modem needs to be outside of + * the CLADE address space, which begins at + * 0xE0000000 and spans 512 MB. + */ + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + cnss_wlan_mem: cnss_wlan_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -942,6 +955,34 @@ status = "ok"; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From 9c0352d0b419081694c1df79bd9841eed052453d Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 10 Mar 2021 19:43:55 +0530 Subject: [PATCH 1081/1809] dt-bindings: Update soc sleep stats to read legacy device data This change adds support to for legacy device to read sleep stats information. Change-Id: I43db91cf7aa7dd68debb1d5d9ed7747e0ea48f63 --- bindings/soc/qcom/soc-sleep-stats.txt | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/bindings/soc/qcom/soc-sleep-stats.txt b/bindings/soc/qcom/soc-sleep-stats.txt index 4c5ade89abbb..725a2ccb5505 100644 --- a/bindings/soc/qcom/soc-sleep-stats.txt +++ b/bindings/soc/qcom/soc-sleep-stats.txt @@ -13,7 +13,8 @@ Properties: - compatible: Usage: required Value type: - Definition: Should be "qcom,rpmh-sleep-stats" or "qcom,rpm-sleep-stats". + Definition: Should be "qcom,rpmh-sleep-stats" or "qcom,rpm-sleep-stats" + or "qcom,legacy-rpm-sleep-stats". - reg: Usage: required @@ -34,3 +35,11 @@ EXAMPLE 2: compatible = "qcom,rpm-sleep-stats"; reg = <0 0x04690000 0 0x400>; }; + +EXAMPLE 3: + + rpm_sleep_stats: soc-sleep-stats@29dba0 { + compatible = "qcom,legacy-rpm-sleep-stats"; + reg = <0x2a1ba0 0x1000>; + }; + From 9f6abfe616548803b63906a1254a38d8cd790516 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 10 Mar 2021 19:57:22 +0530 Subject: [PATCH 1082/1809] bindings: arm: msm: Added documentation for ipc spinlock This adds bindings for ipc-spinlock. Change-Id: I2543ac6d8a61d9bc06c12f4c76284aaa1500e2b0 --- bindings/arm/msm/ipc-spinlock.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 bindings/arm/msm/ipc-spinlock.txt diff --git a/bindings/arm/msm/ipc-spinlock.txt b/bindings/arm/msm/ipc-spinlock.txt new file mode 100644 index 000000000000..6460a70a74af --- /dev/null +++ b/bindings/arm/msm/ipc-spinlock.txt @@ -0,0 +1,27 @@ +Interprocessor Communication Spinlock + +--Dedicated Hardware Implementation-- +Required properties: +- compatible : should be "qcom,ipc-spinlock-sfpb" +- reg : the location and size of the spinlock hardware +- qcom,num-locks : the number of locks supported + +Example: + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x1000>; + qcom,num-locks = <32>; + }; + +--LDREX Implementation-- +Required properties: +- compatible : should be "qcom,ipc-spinlock-ldrex" +- reg : the location and size of the shared lock memory + +Example: + + qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + }; From ffbd96aa79176ab1e445d2af4c80fc8e6ea314f7 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 3 Dec 2020 11:03:44 +0530 Subject: [PATCH 1083/1809] ARM: dts: msm: Add rpm-smd node for Monaco Add rpm-smd node to enable APSS communication with RPM. Change-Id: Ia0225d650dc751acfdef6d998a46186657ee952d --- qcom/monaco.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 5193afbc42ef..4dcfa5c02af6 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -855,6 +855,13 @@ compatible = "qcom,monaco-bimc"; #interconnect-cells = <1>; }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; }; #include "monaco-pinctrl.dtsi" From 4ddf5c2f0f30e65030a121ad07044a3836927c8c Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 8 Mar 2021 17:16:50 +0530 Subject: [PATCH 1084/1809] ARM: dts: msm: Add set_ddr_capped_freq device node interface for SA6155 Add set_ddr_capped_freq interface to send data to the AOP. Change-Id: I63ddb91a5979e5c0b722970f03d709b3e7f38562 --- qcom/sm6150.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b273ebb1a19f..2c1055968029 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2420,6 +2420,11 @@ qcom,config-arr = <0x18060060 0x18070060>; }; + aop-set-ddr-freq { + compatible = "qcom,aop-set-ddr-freq"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; &firmware { From 65f86e7861ba20a6f2bfe1ee916944e54f5f4723 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 28 Jan 2021 23:19:29 +0530 Subject: [PATCH 1085/1809] ARM: dts: msm: Add the LPM and mpm node Add the LPM and MPM nodes for sdxnightjar. Change-Id: Ib131c4a2c51be5358011ad81b1c4441af18962f8 --- qcom/sdxnightjar-pm.dtsi | 130 +++++++++++++++++++++++++++++++++++++++ qcom/sdxnightjar.dtsi | 23 +++++++ 2 files changed, 153 insertions(+) create mode 100644 qcom/sdxnightjar-pm.dtsi diff --git a/qcom/sdxnightjar-pm.dtsi b/qcom/sdxnightjar-pm.dtsi new file mode 100644 index 000000000000..38faa981f8fa --- /dev/null +++ b/qcom/sdxnightjar-pm.dtsi @@ -0,0 +1,130 @@ +&soc { + qcom,spm@b009000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb009000 0x1000>; + qcom,name = "cpu0"; + qcom,cpu = <&CPU0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x1>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0xe>; + qcom,mode0 { + qcom,label = "qcom,saw2-spm-cmd-wfi"; + qcom,sequence = [04 03 04 0f]; + qcom,spm_en; + }; + + qcom,mode1 { + qcom,label = "qcom,saw2-spm-cmd-spc"; + qcom,sequence = [1f 34 04 44 24 54 03 + 54 44 04 24 34 0f]; + qcom,spm_en; + qcom,pc_mode; + }; + + qcom,mode2 { + qcom,label = "qcom,saw2-spm-cmd-pc"; + qcom,sequence = [1f 34 04 44 14 24 54 03 + 54 44 14 04 04 24 04 34 0f]; + qcom,spm_en; + qcom,pc_mode; + qcom,slp_cmd_mode; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "system"; + qcom,default-level=<0>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "l2-active"; + qcom,latency-us = <270>; + qcom,ss-power = <455>; + qcom,energy-overhead = <270621>; + qcom,time-overhead = <500>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "l2-pc"; + qcom,latency-us = <285>; + qcom,ss-power = <442>; + qcom,energy-overhead = <306621>; + qcom,time-overhead = <540>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,reset-level = <3>; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cpu-level@0 { + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,latency-us = <1>; + qcom,ss-power = <473>; + qcom,energy-overhead = <100000>; + qcom,time-overhead = <25>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + qcom,spm-cpu-mode ="standalone_pc"; + qcom,latency-us = <240>; + qcom,ss-power = <467>; + qcom,energy-overhead = <202781>; + qcom,time-overhead = <420>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = <3>; + }; + + qcom,pm-cpu-level@2 { + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,latency-us = <270>; + qcom,ss-power = <455>; + qcom,energy-overhead = <270621>; + qcom,time-overhead = <500>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = <3>; + }; + }; + }; + }; + + qcom,pm@8600664 { + compatible = "qcom,pm"; + reg = <0x8600664 0x40>; + qcom,use-sync-timer; + qcom,synced-clocks; + qcom,tz-flushes-cache; + }; + + qcom,rpm-stats@29dba0 { + compatible = "qcom,legacy-rpm-sleep-stats"; + reg = <0x2a1ba0 0x1000>; + }; + + qcom,rpm-master-stats@60150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x60150 0x2030>; + qcom,masters = "APSS", "MPSS", "PRONTO"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 6967e0c66845..759bb1c4f55f 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -124,6 +124,22 @@ <0x0b002000 0x1000>; }; + wakegic: wake-gic { + compatible = "qcom,mpm-gic-sdxnightjar", "qcom,mpm"; + interrupts = ; + reg = <0x601b8 0x1000>, + <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + system_pm_rpm { + compatible = "qcom,system-pm-rpm"; + }; + qcom,mpm2-sleep-counter@4a3000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0x004a3000 0x1000>; @@ -704,6 +720,12 @@ reg = <0x60000 0x6000>; }; + qcom,ipc-spinlock@1905000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1905000 0x8000>; + qcom,num-locks = <8>; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -1056,6 +1078,7 @@ #include "sdxnightjar-coresight.dtsi" #include "sdxnightjar-pinctrl.dtsi" #include "sdxnightjar-ion.dtsi" +#include "sdxnightjar-pm.dtsi" #include "sdxnightjar-blsp.dtsi" #include "sdxnightjar-cnss.dtsi" #include "sdxnightjar-pcie.dtsi" From 3d248908c2a95778ad9d92321fc5fabbb9a4ec51 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Fri, 5 Feb 2021 22:06:43 +0530 Subject: [PATCH 1086/1809] ARM: dts: msm: Add support for mpm interrupts on sdxnightjar Add support for MPM interrupts to support usb suspend on sdxnightjar. Change-Id: I51ccb023d7225df3923c9ee5e9bebbb6bbaecbba --- qcom/sdxnightjar-usb.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 3113ff4e13e3..4e9da9272e2d 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -8,11 +8,10 @@ #size-cells = <1>; ranges; - interrupts-extended = <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH - &intc GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH - &intc GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq","pwr_event_irq"; - + interrupts-extended = <&intc GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 54 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq","ss_phy_irq", "hs_phy_irq"; USB3_GDSC-supply = <&gdsc_usb30>; qcom,lpm-to-suspend-delay-ms = <2000>; From bbd1fae265ea8277322a375abf2e79435122450d Mon Sep 17 00:00:00 2001 From: Haseeb Khan Date: Mon, 15 Mar 2021 10:50:37 +0530 Subject: [PATCH 1087/1809] ARM: dts: msm: Enable CVP SMMU fault tolerance and Stall disable "non-fatal" -> smmu will not bug_on for s1 fault. Avoid system crash when CVP SMMU fault happens. CVP SSR can recover SMMU fault now "stall-disable" -> smmu terminates pending transaction Invokes smmu_fault_handler and triggers vnoc interrupt independently. So firmware can quickly write sys_error pkt(previous transactions were not stalled for that CB) to message queue. Change-Id: I749741801dcf2599ccd3b51b53c326629adaebfb --- qcom/shima-cvp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/shima-cvp.dtsi b/qcom/shima-cvp.dtsi index 88cf07273c01..6153ac780406 100644 --- a/qcom/shima-cvp.dtsi +++ b/qcom/shima-cvp.dtsi @@ -64,6 +64,7 @@ buffer-types = <0xfff>; dma-coherent-hint-cached; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; @@ -75,6 +76,7 @@ buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; cvp_secure_pixel_cb { @@ -85,6 +87,7 @@ buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; /* Memory Heaps */ From fcb20cd729cbf4de93c71f652626445576e0e426 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Tue, 2 Feb 2021 15:43:27 +0530 Subject: [PATCH 1088/1809] ARM: dts: msm: Add initial device tree for Blair Adding initial device tree support for Blair target. Change-Id: I9ffe2a86e2a6710968600653fdc7427dacf9b158 --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 8 + qcom/blair-rumi-overlay.dts | 11 + qcom/blair-rumi.dts | 11 + qcom/blair-rumi.dtsi | 122 ++ qcom/blair.dts | 9 + qcom/blair.dtsi | 3428 +++++++++++++++++++++++++++++++++++ 7 files changed, 3593 insertions(+) create mode 100644 qcom/blair-rumi-overlay.dts create mode 100644 qcom/blair-rumi.dts create mode 100644 qcom/blair-rumi.dtsi create mode 100644 qcom/blair.dts create mode 100644 qcom/blair.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 85b2a7958bff..e5d16d2541b1 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -101,6 +101,9 @@ SoCs: - HOLI compatible = "qcom,holi" +- BLAIR + compatible = "qcom,blair" + - MONACO compatible = "qcom,monaco" @@ -284,6 +287,7 @@ compatible = "qcom,holi-mtp" compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" +compatible = "qcom,blair-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" compatible = "qcom,sdxnightjar-mtp" diff --git a/qcom/Makefile b/qcom/Makefile index d7d88aff5c88..e61b0efc9314 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -125,6 +125,14 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-mtp-usbc.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo + +blair-rumi-overlay.dtbo-base := blair.dtb +else +dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ diff --git a/qcom/blair-rumi-overlay.dts b/qcom/blair-rumi-overlay.dts new file mode 100644 index 000000000000..36113587bdfb --- /dev/null +++ b/qcom/blair-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "blair-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair RUMI"; + compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/blair-rumi.dts b/qcom/blair-rumi.dts new file mode 100644 index 000000000000..e055b7fdffa9 --- /dev/null +++ b/qcom/blair-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x50000000 0x00000100; + +#include "blair.dtsi" +#include "blair-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair RUMI"; + compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi new file mode 100644 index 000000000000..3527407618aa --- /dev/null +++ b/qcom/blair-rumi.dtsi @@ -0,0 +1,122 @@ +#include +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f420000 { + clock-frequency = <500000>; + }; + + wdog { + status = "disabled"; + }; + + usb_emu_phy_0: usb_emu_phy@0x04f20000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x04f20000 0x9500>; + + qcom,emu-init-seq = <0xffff 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; +}; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; + +&sdhc_1 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + cap-mmc-highspeed; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cap-sd-highspeed; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <1>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +/* Debug UART Console */ +&qupv3_se9_2uart { + qcom,rumi_platform; +}; + +&qupv3_se10_i2c { + status = "disabled"; +}; diff --git a/qcom/blair.dts b/qcom/blair.dts new file mode 100644 index 000000000000..57b1e25b8c40 --- /dev/null +++ b/qcom/blair.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "blair.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair SoC"; + compatible = "qcom,blair"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi new file mode 100644 index 000000000000..c7927c8abf55 --- /dev/null +++ b/qcom/blair.dtsi @@ -0,0 +1,3428 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. Blair "; + compatible = "qcom,blair"; + qcom,msm-id = <507 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &qupv3_se9_2uart; + hsuart0 = &qupv3_se1_4uart; + swr0 = &swr0; + swr1 = &swr1; + }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + + }; + }; + + soc: soc { }; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x1e00000>; + }; + + pil_wlan_mem: wlan@86500000 { + no-map; + reg = <0x0 0x86500000 0x0 0x200000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: camera@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: video@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + splash_memory: splash_region@0x85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@85e00000 { + reg = <0x0 0x85e00000 0x0 0x00100000>; + label = "dfps_data_region"; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical", "slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x3b0>; + status = "ok"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L11A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf240000 0x100000>; /* GICR * 8 */ + interrupts = ; + #gpio-cells = <0>; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones {}; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f420000 0x1000>; + clock-frequency = <19200000>; + + frame@f421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + }; + + frame@f423000 { + frame-number = <1>; + interrupts = ; + reg = <0xf243000 0x1000>; + status = "disabled"; + }; + + frame@f425000 { + frame-number = <2>; + interrupts = ; + reg = <0xf425000 0x1000>; + status = "disabled"; + }; + + frame@f427000 { + frame-number = <3>; + interrupts = ; + reg = <0xf427000 0x1000>; + status = "disabled"; + }; + + frame@f429000 { + frame-number = <4>; + interrupts = ; + reg = <0xf429000 0x1000>; + status = "disabled"; + }; + + frame@f42b000 { + frame-number = <5>; + interrupts = ; + reg = <0xf42b000 0x1000>; + status = "disabled"; + }; + + frame@f42d000 { + frame-number = <6>; + interrupts = ; + reg = <0xf42d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c101_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c102_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c103_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c1_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c2_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c3_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c100_scandump: c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x134>; + }; + + c101_scandump: c101_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x135>; + }; + + c102_scandump: c102_scandump { + qcom,dump-size = <0x25900>; + qcom,dump-id = <0x136>; + }; + + c103_scandump: c103_scandump { + qcom,dump-size = <0x25900>; + qcom,dump-id = <0x137>; + }; + + l1_icache0 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x63>; + }; + + l1_icache100 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x64>; + }; + + l1_icache101 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x65>; + }; + + l1_icache102 { + qcom,dump-size = <0x21000>; + qcom,dump-id = <0x66>; + }; + + l1_icache103 { + qcom,dump-size = <0x21000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache101 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache102 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache103 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x124>; + }; + + l2_tlb101 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x125>; + }; + + l2_tlb102 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb103 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + rpm_sw { + qcom,dump-size = <0x2c000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@0x4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + wdog: qcom,wdt@f410000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf410000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-holi", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + system_pm_rpm { + compatible = "qcom,system-pm-rpm"; + }; + + ipcc_mproc: qcom,ipcc@208000 { + compatible = "qcom,ipcc"; + reg = <0x208000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + clk_virt: interconnect { + compatible = "qcom,holi-clk_virt"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_QUP_CLK>, + <&rpmcc RPM_SMD_QUP_A_CLK>; + }; + + mmnrt_virt: interconnect@0 { + compatible = "qcom,holi-mmnrt_virt"; + #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, + <&rpmcc RPM_SMD_MMNRT_A_CLK>; + }; + + mmrt_virt: interconnect@1 { + compatible = "qcom,holi-mmrt_virt"; + #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMRT_CLK>, + <&rpmcc RPM_SMD_MMRT_A_CLK>; + }; + + system_noc: interconnect@1880000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01880000 0x5f080>; + compatible = "qcom,holi-system_noc"; + #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x01900000 0x6200>; + compatible = "qcom,holi-config_noc"; + #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + bimc: interconnect@4480000 { + reg = <0x04480000 0x80000>; + compatible = "qcom,holi-bimc"; + #interconnect-cells = <1>; + qcom,util-factor = <151>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + cpucp_l3_cpu: l3_cpu@fd90000 { + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-holi"; + qcom,bimc-log-stop; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,holi-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg_names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,holi-dispcc", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,holi-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_gx-supply = <&VDD_GFX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "gcc_gpu_snoc_dvm_gfx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpucc: syscon@faa0018 { + compatible = "syscon"; + reg = <0x0faa0018 0x4>; + }; + + mccc: syscon@0447d200 { + compatible = "syscon"; + reg = <0x0447d200 0x100>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,holi-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>, + <0x0fd04504 0x4>, <0x0fd04508 0x4>; + reg-names = "freq-domain0", "freq-domain1", + "pdmem-domain0", "pdmem-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,lut-row-size = <4>; + qcom,max-lut-entries = <12>; + qcom,skip-enable-check; + qcom,perf-lock-support; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@0fd91000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x0fd91000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devfreq-icc"; + governor = "bw_hwmon"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@4520300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x4520300 0x300>, <0x4520200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; + }; + + cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 940800 MHZ_TO_MBPS( 451, 4) >, + < 1190400 MHZ_TO_MBPS( 547, 4) >, + < 1478400 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS( 1017, 4) >; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 1190400 MHZ_TO_MBPS( 451, 4) >, + < 1478400 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1248000 MHZ_TO_MBPS(1017, 4) >, + < 1536000 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1248800 MHZ_TO_MBPS( 547, 4) >, + < 1401600 MHZ_TO_MBPS( 768, 4) >, + < 1536000 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + }; + + tcsr_mutex_block: syscon@340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + dcc: dcc_v2@16db000 { + compatible = "qcom,dcc-v2"; + reg = <0x16db000 0x1000>, + <0x1662000 0x2000>; + + qcom,transaction_timeout = <0>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x6000>; + + link_list1 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "rpm_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "dsps_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x0F800058 0x0F810058 0x0F820058 0x0F830058 + 0x0F840058 0x0F850058 0x0F860058 0x0F870058>; + qcom,config-arr = <0x0F800060 0x0F810060 0x0F820060 0x0F830060 + 0x0F840060 0x0F850060 0x0F860060 0x0F870060>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + qcom,venus@5ab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ab0000 0x20000>; + + vdd-supply = <&gcc_venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + + qcom,core-freq = <240000000>; + qcom,ahb-freq = <240000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; + + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xDDC>; + reg-names = "phy_mem"; + #phy-cells = <0>; + lanes-per-direction = <1>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1001 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1002 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1006 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1009 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A3 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A4 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A5 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A6 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A7 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>, + <0x4808000 0x8000>, + <0x4810000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + limit-phy-submode = <0>; + spm-level = <5>; + rpm-level = <3>; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + + interconnects = <&system_noc MASTER_UFS_MEM &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <12>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "fastmap"; + + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <59>; + }; + + qos1 { + mask = <0xc0>; + vote = <65>; + }; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, + <0x04748000 0x8000>, <0x04750000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; + + iommus = <&apps_smmu 0x20 0x0>; + qcom,iommu-dma = "fastmap"; + + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>, <1600 1600>, + /* 25 MB/s */ + <25600 250000>, <50000 133320>, + /* 50 MB/s */ + <51200 250000>, <65000 133320>, + /* 100 MB/s */ + <102400 250000>, <65000 133320>, + /* 200 MB/s */ + <204800 800000>, <200000 300000>, + /* 400 MB/s */ + <204800 800000>, <200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + cap-mmc-hw-reset; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + max-frequency = <192000000>; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 3200>, <1600 1600>, + /* 25 MB/s */ + <65360 250000>, <100000 133320>, + /* 50 MB/s */ + <130718 250000>, <133320 133320>, + /* 100 MB/s */ + <261438 250000>, <150000 133320>, + /* 200 MB/s */ + <261438 800000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + + bus-width = <4>; + + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + + no-mmc; + no-sdio; + max-frequency = <202000000>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; + + qcom,lpass@a400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xa400000 0x00100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,minidump-id = <5>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom,turing@b000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xb000000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,minidump-id = <7>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + pil_modem: qcom,mss@06000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x06000000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_mpss_wlan_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom_qseecom: qseecom@c1800000 { + compatible = "qcom,qseecom"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,smmu-s1-enable; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + iommus = <&apps_smmu 0x0486 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x492 0>, + <&apps_smmu 0x498 0x0001>, + <&apps_smmu 0x49F 0>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x493 0>, + <&apps_smmu 0x49C 0x0001>, + <&apps_smmu 0x49E 0>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + iommus = <&apps_smmu 0x0484 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qcom_rng: qrng@4453000 { + compatible = "qcom,msm-rng"; + reg = <0x4453000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM>; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + }; + + qcom_hwkm: hwkm@4440000 { + compatible = "qcom,hwkm"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>; + reg-names = "km_master", "ice_slave"; + qcom,enable-hwkm-clk; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + qcom,op-freq-hz = <75000000>; + }; + + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + eud: qcom,msm-eud@1628000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1628000 0x2000>, + <0x162A000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + status = "ok"; + }; + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + vdd-cx-mx-supply = <&L4A>; + vdd-1.8-xo-supply = <&L7A>; + vdd-1.3-rfa-supply = <&L2E>; + vdd-3.3-ch1-supply = <&L11E>; + vdd-3.3-ch0-supply = <&L10E>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + ipa_hw: qcom,ipa@0x5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x84000>, + <0x5804000 0x23000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,arm-smmu; + qcom,use-64-bit-dma-mask; + qcom,lan-rx-napi; + qcom,wan-use-skb-page; + qcom,rmnet-ctl-enable; + qcom,ipa-endp-delay-wa; + qcom,tx-wrapper-cache-max-size = <400>; + clock-names = "core_clk"; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <80000 465000 80000 68570 80000 30>; + + /* SVS */ + qcom,svs = + <80000 2000000 80000 267461 80000 109890>; + + /* NOMINAL */ + qcom,nominal = + <206000 4000000 206000 712961 206000 491520>; + + /* TURBO */ + qcom,turbo = + <206000 5598900 206000 1436481 206000 491520>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x04A0 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x0C123000 0x0C123000 0x2000>; + qcom,iommu-dma = "fastmap"; + qcom,ipa-q6-smem-size = <36864>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x04A1 0x0>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x04A2 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_11ad: ipa_smmu_11ad { + compatible = "qcom,ipa-smmu-11ad-cb"; + iommus = <&apps_smmu 0x04A3 0x0>; + qcom,shared-cb; + qcom,iommu-group = <>; + }; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@6015 { + reg = <0x6015 0x1>; + bits = <0 8>; + }; + + adsp_variant: adsp_variant@1E6 { + reg = <0x1E6 0x2>; + bits = <6 4>; + }; + + feat_conf8: feat_conf8@6024 { + reg = <0x6024 0x4>; + }; + + gpu_gaming_bin: gpu_gaming_bin@6026 { + reg = <0x6026 0x1>; + bits = <5 1>; + }; + + feat_conf9: feat_conf9@6028 { + reg = <0x6028 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&adsp_variant>, + <&feat_conf8>, + <&gpu_gaming_bin>, + <&feat_conf9>; + nvmem-cell-names = "gpu_speed_bin", + "adsp_variant", + "feat_conf8", + "gpu_gaming_bin", + "feat_conf9"; + }; +}; + +#include "holi-gpu.dtsi" +#include "holi-pinctrl.dtsi" +#include "pm6350-rpm-regulator.dtsi" +#include "pm6150l-rpm-regulator.dtsi" +#include "holi-regulators.dtsi" +#include "holi-gdsc.dtsi" +#include "holi-ion.dtsi" +#include "msm-arm-smmu-holi.dtsi" +#include "holi-coresight.dtsi" +#include "holi-pm.dtsi" +#include "holi-vidc.dtsi" +#include "camera/holi-camera.dtsi" +#include "holi-thermal.dtsi" +#include "holi-pinctrl.dtsi" +#include "holi-qupv3.dtsi" +#include "display/holi-sde.dtsi" +#include "holi-audio.dtsi" +#include "ipcc-test-holi.dtsi" + +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&qupv3_se1_4uart { + status = "ok"; +}; + +&qupv3_se9_2uart { + status = "ok"; +}; + +#include "msm-rdbg.dtsi" + From 887d4b7a742e5fe99a0e13b31d5256124c24920d Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Fri, 5 Feb 2021 13:34:42 +0530 Subject: [PATCH 1089/1809] dt-bindings: Adding pinctrl devicetree binding for Blair Adding pinctrl devicetree binding for Blair platform. Change-Id: Iacc43a1580653b382779b98b139c0d9a8b9dcd22 --- bindings/pinctrl/qcom,blair-pinctrl.yaml | 195 +++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 bindings/pinctrl/qcom,blair-pinctrl.yaml diff --git a/bindings/pinctrl/qcom,blair-pinctrl.yaml b/bindings/pinctrl/qcom,blair-pinctrl.yaml new file mode 100644 index 000000000000..1b1ce0249781 --- /dev/null +++ b/bindings/pinctrl/qcom,blair-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,blair-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. BLAIR TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + HOLI platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,blair-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@400000 { + compatible = "qcom,blair-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; From a7ec1d2deb83a638bef7e350e30ca9e89656934b Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Fri, 5 Feb 2021 13:41:40 +0530 Subject: [PATCH 1090/1809] ARM: dts: msm: Adding device tree node for Blair pinctrl Adding device tree node for enabling Blair pinctrl. Change-Id: I31b123c320e6ec3b1636b030facbf9b0ade90f63 --- qcom/blair-pinctrl.dtsi | 1111 +++++++++++++++++++++++++++++++++++++++ qcom/blair.dtsi | 4 +- 2 files changed, 1112 insertions(+), 3 deletions(-) create mode 100644 qcom/blair-pinctrl.dtsi diff --git a/qcom/blair-pinctrl.dtsi b/qcom/blair-pinctrl.dtsi new file mode 100644 index 000000000000..9cb472d3e943 --- /dev/null +++ b/qcom/blair-pinctrl.dtsi @@ -0,0 +1,1111 @@ +&soc { + tlmm: pinctrl@400000 { + compatible = "qcom,blair-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&wakegic>; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 9: NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 9: NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* 6: Enable, 8: Firmware, 7: CLOCK */ + pins = "gpio6", "gpio8", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + /* 6: Enable, 8: Firmware, 7: CLOCK */ + pins = "gpio6", "gpio8", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_4uart_pins: qupv3_se1_4uart_pins { + qupv3_se1_default_cts: + qupv3_se1_default_cts { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_rtsrx: + qupv3_se1_default_rtsrx { + mux { + pins = "gpio62", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio62", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_tx: + qupv3_se1_default_tx { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_ctsrx: qupv3_se1_ctsrx { + mux { + pins = "gpio61", "gpio64"; + function = "qup01"; + }; + + config { + pins = "gpio61", "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_rts: qupv3_se1_rts { + mux { + pins = "gpio62"; + function = "qup01"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_tx: qupv3_se1_tx { + mux { + pins = "gpio63"; + function = "qup01"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio45", "gpio46"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio45", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio13", "gpio14"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio13", "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup11"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio19", "gpio20"; + function = "qup12"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio25", "gpio26"; + function = "qup13_f2"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio25", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup14"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio94"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio94"; + bias-disable; + drive-strength = <2>; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd937x_reset_active: wcd937x_reset_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + output-high; + }; + }; + + wcd937x_reset_sleep: wcd937x_reset_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio23"; + function = "MDP_VSYNC"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio23"; + function = "MDP_VSYNC"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + pmx_ts_release: pmx_ts_release { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* Camera GPIOs CCI*/ + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio41", "gpio42"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio41", "gpio42"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio41", "gpio42"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio41", "gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio43", "gpio44"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio43", "gpio44"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio43", "gpio44"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio43", "gpio44"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK 3*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK 3*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK 4*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK 4*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_reset_active: cam_sensor_rear2_reset_active { + /* RESET2 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_reset_suspend: cam_sensor_rear2_reset_suspend { + /* RESET2 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_reset4_active: cam_sensor_reset4_active { + /* RESET4 */ + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_reset4_suspend: cam_sensor_reset4_suspend { + /* RESET4 */ + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio58"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + }; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c7927c8abf55..96d87849cfe1 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3346,7 +3346,7 @@ }; #include "holi-gpu.dtsi" -#include "holi-pinctrl.dtsi" +#include "blair-pinctrl.dtsi" #include "pm6350-rpm-regulator.dtsi" #include "pm6150l-rpm-regulator.dtsi" #include "holi-regulators.dtsi" @@ -3358,7 +3358,6 @@ #include "holi-vidc.dtsi" #include "camera/holi-camera.dtsi" #include "holi-thermal.dtsi" -#include "holi-pinctrl.dtsi" #include "holi-qupv3.dtsi" #include "display/holi-sde.dtsi" #include "holi-audio.dtsi" @@ -3425,4 +3424,3 @@ }; #include "msm-rdbg.dtsi" - From d2e6dd0db7bad593157ff7cf0d3b59e3a5ddfc46 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 15 Mar 2021 18:40:48 +0530 Subject: [PATCH 1091/1809] ARM: dts: msm: Update WLED support for yupik Add an exponential dimming table with brightness values for WLED to use if exponential dimming is enabled. Also set the slew rate time to 256ms explicitly. Change-Id: Id209041442f5fa1d96acdc2b14caa135dc62ed6f --- qcom/yupik-idp.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index c9aa771df6cc..c81200fb15a4 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -233,6 +233,42 @@ qcom,string-cfg = <3>; qcom,leds-per-string = <8>; qcom,fs-current-limit = <22500>; + qcom,slew-ramp-time = <256>; + + qcom,exp-dimming-map = < + 0x1A 0x1B 0x1C 0x1D 0x1E 0x1E 0x1F 0x20 + 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 + 0x29 0x2A 0x2C 0x2D 0x2E 0x30 0x31 0x32 + 0x34 0x35 0x37 0x38 0x3A 0x3B 0x3D 0x3F + 0x41 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4F + 0x51 0x53 0x55 0x58 0x5A 0x5D 0x60 0x62 + 0x65 0x68 0x6B 0x6E 0x71 0x74 0x77 0x7B + 0x7E 0x82 0x86 0x89 0x8D 0x91 0x95 0x9A + 0x9E 0xA2 0xA7 0xAC 0xB1 0xB6 0xBB 0xC0 + 0xC5 0xCB 0xD1 0xD7 0xDD 0xE3 0xE9 0xF0 + 0xF7 0xFE 0x105 0x10C 0x114 0x11C 0x124 0x12C + 0x135 0x13D 0x146 0x150 0x159 0x163 0x16D 0x177 + 0x182 0x18D 0x198 0x1A4 0x1B0 0x1BC 0x1C8 0x1D5 + 0x1E3 0x1F0 0x1FE 0x20D 0x21C 0x22B 0x23B 0x24B + 0x25C 0x26D 0x27E 0x290 0x2A3 0x2B6 0x2CA 0x2DE + 0x2F3 0x308 0x31E 0x335 0x34C 0x364 0x37C 0x396 + 0x3B0 0x3CA 0x3E6 0x402 0x41F 0x43D 0x45C 0x47B + 0x49C 0x4BD 0x4E0 0x503 0x527 0x54D 0x573 0x59B + 0x5C3 0x5ED 0x618 0x644 0x672 0x6A0 0x6D0 0x702 + 0x735 0x769 0x79F 0x7D6 0x80F 0x849 0x885 0x8C3 + 0x903 0x944 0x987 0x9CC 0xA13 0xA5C 0xAA8 0xAF5 + 0xB44 0xB96 0xBEA 0xC40 0xC99 0xCF5 0xD52 0xDB3 + 0xE16 0xE7D 0xEE6 0xF52 0xFC1 0x1033 0x10A8 0x1121 + 0x119D 0x121D 0x12A1 0x1328 0x13B3 0x1441 0x14D4 0x156B + 0x1607 0x16A6 0x174B 0x17F4 0x18A1 0x1954 0x1A0B 0x1AC8 + 0x1B8B 0x1C52 0x1D20 0x1DF3 0x1ECC 0x1FAB 0x2091 0x217D + 0x2270 0x236A 0x246B 0x2573 0x2682 0x2799 0x28B9 0x29E0 + 0x2B10 0x2C48 0x2D89 0x2ED3 0x3027 0x3184 0x32EB 0x345C + 0x35D8 0x375E 0x38F0 0x3A8D 0x3C35 0x3DEA 0x3FAB 0x4179 + 0x4353 0x453C 0x4732 0x4936 0x4B49 0x4D6B 0x4F9C 0x51DD + 0x542F 0x5692 0x5905 0x5B8B 0x5E23 0x60CD 0x638B 0x665D + 0x6944 0x6C3F 0x6F50 0x7277 0x75B5 0x790B 0x7C78 0x7FFF + >; }; &spmi_debug_bus { From 3429e906a5c10b053ae72a416cb0f821a4651f43 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 8 Mar 2021 18:16:14 +0530 Subject: [PATCH 1092/1809] ARM: dts: msm: Enable two_pass_use_wfi quirk for yupik GPU Enable two_pass_mode_wfi quirk to set TWOPASSUSEWFI in PC_DBG_ECO_CTL for yupik GPU. Change-Id: I7fdef91ffddfe3a3f5578ae93c7323ad90f860ba --- qcom/yupik-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index d516d638b7a7..67f2eb0010ed 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -52,6 +52,7 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; + qcom,gpu-quirk-two-pass-use-wfi; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; From e701b635563fd5bcc518b8a530e5d25c3f3b095a Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Tue, 16 Mar 2021 10:43:01 +0800 Subject: [PATCH 1093/1809] ARM: dts: msm: disable super speed phy of USB1 on Lahaina HHG also set max usb speed to full speed. Change-Id: I731690e912357e803f6ed44d93a2edaace34b39c --- qcom/lahaina-hhg.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 386367957b73..08df90a06f49 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -109,6 +109,11 @@ &usb1 { qcom,ignore-wakeup-src-in-hostmode; + + dwc3@a800000 { + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + maximum-speed = "full-speed"; + }; }; &thermal_zones { From 1aab8de5636b8ef958d85d321f34d05af0974b73 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Tue, 16 Mar 2021 12:22:44 +0800 Subject: [PATCH 1094/1809] ARM: dts: msm: Add new dts files for 512MB support for sdxnightjar Add new device tree files for sdxnightjar 512MB memory support. Change-Id: Ifc23415a6d1748b3be540011ce3cb5b65b64547c --- qcom/Makefile | 4 +++- qcom/sdxnightjar-512mb-mtp.dts | 12 ++++++++++ qcom/sdxnightjar-dualwifi-512mb-mtp.dts | 29 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxnightjar-512mb-mtp.dts create mode 100644 qcom/sdxnightjar-dualwifi-512mb-mtp.dts diff --git a/qcom/Makefile b/qcom/Makefile index d7d88aff5c88..9595b50e9adf 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -333,7 +333,9 @@ endif dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ sdxnightjar-cdp.dtb \ sdxnightjar-qrd.dtb \ - sdxnightjar-dualwifi-mtp.dtb + sdxnightjar-dualwifi-mtp.dtb \ + sdxnightjar-512mb-mtp.dtb \ + sdxnightjar-dualwifi-512mb-mtp.dtb ifeq ($(CONFIG_ARCH_YUPIK), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) diff --git a/qcom/sdxnightjar-512mb-mtp.dts b/qcom/sdxnightjar-512mb-mtp.dts new file mode 100644 index 000000000000..33ac3169908f --- /dev/null +++ b/qcom/sdxnightjar-512mb-mtp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" +#include "sdxnightjar-bluetooth.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR 512MB MTP"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 0x100>; +}; diff --git a/qcom/sdxnightjar-dualwifi-512mb-mtp.dts b/qcom/sdxnightjar-dualwifi-512mb-mtp.dts new file mode 100644 index 000000000000..512e1fc1b7d3 --- /dev/null +++ b/qcom/sdxnightjar-dualwifi-512mb-mtp.dts @@ -0,0 +1,29 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" +#include "sdxnightjar-bluetooth.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR 512MB MTP - DWIFI"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 0x103>; +}; + +&sdhc_1 { + vdd-io-supply = <&pmd9650_l7>; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-always-on; + qcom,vdd-io-current-level = <0 10000>; + + keep-power-in-suspend; + qcom,core_3_0v_support; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_wlan_gpio_active>; + pinctrl-1 = <&sdc2_off &sdc2_wlan_gpio_sleep>; + + status = "ok"; +}; From 0c4b79359f95787a89c248bda9d06ab10752c2da Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 15 Mar 2021 15:05:57 +0530 Subject: [PATCH 1095/1809] ARM: dts: msm: Update SPMI PMIC ARB IRQ for sdxnightjar Update SPMI PMIC ARB IRQ interrupt configurations with correct parent and MPM pin number for sdxnightjar. Change-Id: Ia473872228baa08d35aace841622737d629bf6d7 --- qcom/sdxnightjar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 759bb1c4f55f..6c7d8f1fd242 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -957,7 +957,7 @@ <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = ; + interrupts-extended = <&wakegic 88 IRQ_TYPE_LEVEL_HIGH>; qcom,channel = <0>; qcom,ee = <0>; #interrupt-cells = <4>; From a1b882fdb143cc645834c656b42fa84404bda6f5 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Tue, 16 Mar 2021 10:35:59 +0530 Subject: [PATCH 1096/1809] dt-bindings: arm: msm: devicetree documentation for PCIe EDMA Adding devicetree documentation for PCIe EDMA. Change-Id: I817539e96fef65294ac853dbe51f303d7bf341f1 --- bindings/dma/qcom-pci-edma.txt | 79 ++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 bindings/dma/qcom-pci-edma.txt diff --git a/bindings/dma/qcom-pci-edma.txt b/bindings/dma/qcom-pci-edma.txt new file mode 100644 index 000000000000..4e2a43e39d07 --- /dev/null +++ b/bindings/dma/qcom-pci-edma.txt @@ -0,0 +1,79 @@ +Qualcomm Technologies Inc PCIe eDMA controller + +QCOM PCIe eDMA controller provides DMA capabilities for +peripheral connected and uses PCIe to transfer data. + +============== +Node Structure +============== + +Main node properties: + +- compatible + Usage: required + Value type: + Definition: "qcom,pci-edma" + +- #dma-cells + Usage: required + Value type: + Definition: Number of parameters client will provide. Must be set to 2. + 1st parameter: channel index, 0 for TX, 1 for RX + 2nd parameter: event processing priority, set to 0 for highest priority + +- reg + Usage: required + Value type: Array (2-cell) of + Definition: First cell is eDMA register base address. Second cell is size of + eDMA register space. + +- interrupts + Usage: required + Value type: Array of + Definition: Array of tuples which describe interrupt lines for eDMA. + +- interrupts-names + Usage: required + Value type: Array of + Definition: Array of names which map to interrupt lines for eDMA. + +- interrupt-parent + Usage: required + Value type: + Definition: phandle of the interrupt controller that services interrupts for + this device + +- qcom,n-tl-init + Usage: optional + Value type: + Definition: Number of transfer and descriptor arrays to start with. If this + entry is not presetn, default value is 2. + +- qcom,n-tl-ele + Usage: optional + Value type: + Definition: Number of elements for each transfer and descriptor array. If this + entry is not present, default value is 1024. + +- qcom,n-max-ev-ch + Usage: optional + Value type: + Definition: Total number of virtual (client) eDMA channels available. If this + entry is not present, default value is 32. + +======= +Example +======= + +pci_edma: qcom,pci-edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupts = ; + interrupt-names = "pci-edma-int"; + interrupt-parent = <&intc>; + qcom,n-max-ev-ch = <32>; + qcom,n-tl-init = <2>; + qcom,n-tl-ele = <1024>; + status = "ok"; +}; From baa7478f19f3f2584b9997984821f2ff754fe8c9 Mon Sep 17 00:00:00 2001 From: raghavendar rao l Date: Mon, 8 Mar 2021 22:56:08 +0530 Subject: [PATCH 1097/1809] ARM: dts: msm: Add IPA dtsi configuration for SA8195 Add veth IPA dtsi configuration for sa8195. Change-Id: I55d7ebd4839ffafcf4128e672e7bb57e80987b61 --- qcom/sa8195-vm-la.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 7527d5a4b602..4a06ec6ecd31 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -151,4 +151,8 @@ memory-region = <&pil_ipa_fw_mem>; }; + qcom,veth-ipa { + compatible = "qcom,veth-ipa"; + }; + }; From c07d5a041952234079e29408b28768b292e03553 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 24 Dec 2020 15:57:33 +0530 Subject: [PATCH 1098/1809] ARM: dts: qcom: Enable thermal zones and cooling devices for sa8195 Enable TSENS different thermal zones like userspace thermal zones, CPU isolation thermal zones, gpu max thermal zones, CDSP, NPU thermal zones and pmic alarm thermal zones etc. and different cooling devices for sa8195. Change-Id: I9cabba6e2d11875c869480e11501a24ff2eb7327 --- qcom/sa8195-pmic.dtsi | 166 ++++++ qcom/sa8195-thermal.dtsi | 1092 ++++++++++++++++++++++++++++++++++++++ qcom/sdmshrike-gpu.dtsi | 2 + qcom/sdmshrike.dtsi | 15 +- 4 files changed, 1269 insertions(+), 6 deletions(-) create mode 100644 qcom/sa8195-thermal.dtsi diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index 2ec01b703cc4..dc28f097358b 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -59,6 +59,13 @@ /delete-node/ refgen; }; +&lmh_dcvs1 { + isens_vref_0p8-supply = <&pm8195_3_l5>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8195_1_l12>; + isens-vref-1p8-settings = <1800000 1800000 20000>; +}; + &camcc { vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mm-supply = <&VDD_MMCX_LEVEL>; @@ -97,6 +104,59 @@ type = "critical"; }; }; + + cooling-maps { + /* + * trip0 cooling map is dummy node to enable + * passive polling on trip0 violation. + */ + trip0_cpu0 { + trip = <&pm8195_1_trip0>; + cooling-device = <&CPU0 0 0>; + }; + + trip1_cpu0 { + trip = <&pm8195_1_trip1>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm8195_1_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; }; pm8195_2_temp_alarm: pm8195_2_tz { @@ -124,6 +184,59 @@ type = "critical"; }; }; + + cooling-maps { + /* + * trip0 cooling map is dummy node to enable + * passive polling on trip0 violation. + */ + trip0_cpu0 { + trip = <&pm8195_2_trip0>; + cooling-device = <&CPU0 0 0>; + }; + + trip1_cpu0 { + trip = <&pm8195_2_trip1>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm8195_2_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; }; pm8195_3_temp_alarm: pm8195_3_tz { @@ -151,5 +264,58 @@ type = "critical"; }; }; + + cooling-maps { + /* + * trip0 cooling map is dummy node to enable + * passive polling on trip0 violation. + */ + trip0_cpu0 { + trip = <&pm8195_3_trip0>; + cooling-device = <&CPU0 0 0>; + }; + + trip1_cpu0 { + trip = <&pm8195_3_trip1>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm8195_3_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; }; }; diff --git a/qcom/sa8195-thermal.dtsi b/qcom/sa8195-thermal.dtsi new file mode 100644 index 000000000000..61b17cf0e965 --- /dev/null +++ b/qcom/sa8195-thermal.dtsi @@ -0,0 +1,1092 @@ +#include + +&cpufreq_hw { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + isens_vref_0p8-supply = <&pm8150_2_l5_ao>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8150_1_l12_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; + +&soc { + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x4>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x4>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: hvx { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + + slpi { + qcom,instance-id = <0x53>; + + slpi_vdd: slpi_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cmpss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-vec-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-scl-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 12>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 13>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddrss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 14>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 15>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + quad-gpuss-max-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 15>, <&tsens1 11>, + <&tsens1 12>, <&tsens1 13>; + sensor-aggregation = ; + trips { + gpu_trip0: gpu-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_trip0>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + trips { + cpu00_config: cpu00-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + trips { + cpu01_config: cpu01-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + trips { + cpu02_config: cpu02-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + trips { + cpu03_config: cpu03-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpu10_config: cpu10-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpu11_config: cpu11-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + cpu12_config: cpu12-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + trips { + cpu13_config: cpu13-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + trips { + cpu14_config: cpu14-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + trips { + cpu15_config: cpu15-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + trips { + cpu16_config: cpu16-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + trips { + cpu17_config: cpu17-config { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + trips { + q6_hvx_trip0: q6-hvx-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_trip1: q6-hvx-trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev0 { + trip = <&q6_hvx_trip0>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + cdsp-cx-cdev0 { + trip = <&q6_hvx_trip1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + npu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "step_wise"; + trips { + npu_trip0: npu-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + npu_cdev { + trip = <&npu_trip0>; + cooling-device = + <&msm_npu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/sdmshrike-gpu.dtsi b/qcom/sdmshrike-gpu.dtsi index 363b7c191dd0..49c49699aad3 100644 --- a/qcom/sdmshrike-gpu.dtsi +++ b/qcom/sdmshrike-gpu.dtsi @@ -39,6 +39,8 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + #cooling-cells = <2>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6333ee3f9bdf..93aa6711af72 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -54,6 +54,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -79,7 +80,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x20000>; @@ -98,7 +99,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x20000>; @@ -117,7 +118,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x20000>; @@ -136,6 +137,7 @@ cache-size = <0x20000>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -155,7 +157,7 @@ cache-size = <0x20000>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; @@ -174,7 +176,7 @@ cache-size = <0x20000>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; @@ -193,7 +195,7 @@ cache-size = <0x20000>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 1 4>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; @@ -2317,6 +2319,7 @@ #include "sa8195-vidc.dtsi" #include "sa8155-audio.dtsi" #include "sm8150-npu.dtsi" +#include "sa8195-thermal.dtsi" #include "display/sdmshrike-sde-pll.dtsi" #include "display/sdmshrike-sde.dtsi" From cdc1575ac4c5fbfd7f775eb73c143820e04ec5ec Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 1 Feb 2021 12:24:16 +0530 Subject: [PATCH 1099/1809] ARM: dts: qcom: update pmic alarm thermal zone mitigation for sa8155/sa8195 The Pmic alarm sensor threshold is updated based on latest recommendation for sa8155/sa8195. Update pmic alarm thermal zone mitigation configuration accordingly for these targets. Change-Id: I4bd7165cc9b93665514396909f66104bf83259a1 --- qcom/sa8155-pmic-overlay.dtsi | 74 +++++++++-------------- qcom/sa8195-pmic.dtsi | 111 +++++++++++++--------------------- 2 files changed, 70 insertions(+), 115 deletions(-) diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi index 8c84740ed630..10ecbbf260bb 100644 --- a/qcom/sa8155-pmic-overlay.dtsi +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -163,54 +163,45 @@ pm8150_1_gpios: &pm8150_gpios { }; cooling-maps { - /* - * trip0 cooling map is dummy node to enable - * passive polling on trip0 violation. - */ trip0_cpu0 { trip = <&pm8150_2_trip0>; - cooling-device = <&CPU0 0 0>; - }; - - trip1_cpu0 { - trip = <&pm8150_2_trip1>; cooling-device = <&CPU0 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - trip1_cpu1 { - trip = <&pm8150_2_trip1>; + trip0_cpu1 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu1_isolate 1 1>; }; - trip1_cpu2 { - trip = <&pm8150_2_trip1>; + trip0_cpu2 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu2_isolate 1 1>; }; - trip1_cpu3 { - trip = <&pm8150_2_trip1>; + trip0_cpu3 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu3_isolate 1 1>; }; - trip1_cpu4 { - trip = <&pm8150_2_trip1>; + trip0_cpu4 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu4_isolate 1 1>; }; - trip1_cpu5 { - trip = <&pm8150_2_trip1>; + trip0_cpu5 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu5_isolate 1 1>; }; - trip1_cpu6 { - trip = <&pm8150_2_trip1>; + trip0_cpu6 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu6_isolate 1 1>; }; - trip1_cpu7 { - trip = <&pm8150_2_trip1>; + trip0_cpu7 { + trip = <&pm8150_2_trip0>; cooling-device = <&cpu7_isolate 1 1>; }; }; @@ -218,54 +209,45 @@ pm8150_1_gpios: &pm8150_gpios { pm8150_tz { cooling-maps { - /* - * trip0 cooling map is dummy node to enable - * passive polling on trip0 violation. - */ trip0_cpu0 { trip = <&pm8150_trip0>; - cooling-device = <&CPU0 0 0>; - }; - - trip1_cpu0 { - trip = <&pm8150_trip1>; cooling-device = <&CPU0 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - trip1_cpu1 { - trip = <&pm8150_trip1>; + trip0_cpu1 { + trip = <&pm8150_trip0>; cooling-device = <&cpu1_isolate 1 1>; }; - trip1_cpu2 { - trip = <&pm8150_trip1>; + trip0_cpu2 { + trip = <&pm8150_trip0>; cooling-device = <&cpu2_isolate 1 1>; }; - trip1_cpu3 { - trip = <&pm8150_trip1>; + trip0_cpu3 { + trip = <&pm8150_trip0>; cooling-device = <&cpu3_isolate 1 1>; }; - trip1_cpu4 { - trip = <&pm8150_trip1>; + trip0_cpu4 { + trip = <&pm8150_trip0>; cooling-device = <&cpu4_isolate 1 1>; }; - trip1_cpu5 { - trip = <&pm8150_trip1>; + trip0_cpu5 { + trip = <&pm8150_trip0>; cooling-device = <&cpu5_isolate 1 1>; }; - trip1_cpu6 { - trip = <&pm8150_trip1>; + trip0_cpu6 { + trip = <&pm8150_trip0>; cooling-device = <&cpu6_isolate 1 1>; }; - trip1_cpu7 { - trip = <&pm8150_trip1>; + trip0_cpu7 { + trip = <&pm8150_trip0>; cooling-device = <&cpu7_isolate 1 1>; }; }; diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index dc28f097358b..facbca2ecc34 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -106,54 +106,45 @@ }; cooling-maps { - /* - * trip0 cooling map is dummy node to enable - * passive polling on trip0 violation. - */ trip0_cpu0 { trip = <&pm8195_1_trip0>; - cooling-device = <&CPU0 0 0>; - }; - - trip1_cpu0 { - trip = <&pm8195_1_trip1>; cooling-device = <&CPU0 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - trip1_cpu1 { - trip = <&pm8195_1_trip1>; + trip0_cpu1 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu1_isolate 1 1>; }; - trip1_cpu2 { - trip = <&pm8195_1_trip1>; + trip0_cpu2 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu2_isolate 1 1>; }; - trip1_cpu3 { - trip = <&pm8195_1_trip1>; + trip0_cpu3 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu3_isolate 1 1>; }; - trip1_cpu4 { - trip = <&pm8195_1_trip1>; + trip0_cpu4 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu4_isolate 1 1>; }; - trip1_cpu5 { - trip = <&pm8195_1_trip1>; + trip0_cpu5 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu5_isolate 1 1>; }; - trip1_cpu6 { - trip = <&pm8195_1_trip1>; + trip0_cpu6 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu6_isolate 1 1>; }; - trip1_cpu7 { - trip = <&pm8195_1_trip1>; + trip0_cpu7 { + trip = <&pm8195_1_trip0>; cooling-device = <&cpu7_isolate 1 1>; }; }; @@ -186,54 +177,45 @@ }; cooling-maps { - /* - * trip0 cooling map is dummy node to enable - * passive polling on trip0 violation. - */ trip0_cpu0 { trip = <&pm8195_2_trip0>; - cooling-device = <&CPU0 0 0>; - }; - - trip1_cpu0 { - trip = <&pm8195_2_trip1>; cooling-device = <&CPU0 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - trip1_cpu1 { - trip = <&pm8195_2_trip1>; + trip0_cpu1 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu1_isolate 1 1>; }; - trip1_cpu2 { - trip = <&pm8195_2_trip1>; + trip0_cpu2 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu2_isolate 1 1>; }; - trip1_cpu3 { - trip = <&pm8195_2_trip1>; + trip0_cpu3 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu3_isolate 1 1>; }; - trip1_cpu4 { - trip = <&pm8195_2_trip1>; + trip0_cpu4 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu4_isolate 1 1>; }; - trip1_cpu5 { - trip = <&pm8195_2_trip1>; + trip0_cpu5 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu5_isolate 1 1>; }; - trip1_cpu6 { - trip = <&pm8195_2_trip1>; + trip0_cpu6 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu6_isolate 1 1>; }; - trip1_cpu7 { - trip = <&pm8195_2_trip1>; + trip0_cpu7 { + trip = <&pm8195_2_trip0>; cooling-device = <&cpu7_isolate 1 1>; }; }; @@ -266,54 +248,45 @@ }; cooling-maps { - /* - * trip0 cooling map is dummy node to enable - * passive polling on trip0 violation. - */ trip0_cpu0 { trip = <&pm8195_3_trip0>; - cooling-device = <&CPU0 0 0>; - }; - - trip1_cpu0 { - trip = <&pm8195_3_trip1>; cooling-device = <&CPU0 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - trip1_cpu1 { - trip = <&pm8195_3_trip1>; + trip0_cpu1 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu1_isolate 1 1>; }; - trip1_cpu2 { - trip = <&pm8195_3_trip1>; + trip0_cpu2 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu2_isolate 1 1>; }; - trip1_cpu3 { - trip = <&pm8195_3_trip1>; + trip0_cpu3 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu3_isolate 1 1>; }; - trip1_cpu4 { - trip = <&pm8195_3_trip1>; + trip0_cpu4 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu4_isolate 1 1>; }; - trip1_cpu5 { - trip = <&pm8195_3_trip1>; + trip0_cpu5 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu5_isolate 1 1>; }; - trip1_cpu6 { - trip = <&pm8195_3_trip1>; + trip0_cpu6 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu6_isolate 1 1>; }; - trip1_cpu7 { - trip = <&pm8195_3_trip1>; + trip0_cpu7 { + trip = <&pm8195_3_trip0>; cooling-device = <&cpu7_isolate 1 1>; }; }; From ae206c2805531b00555572e5adcc7c7897fb7414 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 1 Feb 2021 12:11:54 +0530 Subject: [PATCH 1100/1809] ARM: dts: qcom: Enable thermal zones and cooling devices for sa6155 Enable TSENS different thermal zones like userspace thermal zones, CPU isolation thermal zones, gpu max thermal zones, CDSP thermal zones and pmic alarm thermal zones etc. and different cooling devices for sa6155. Change-Id: I1c22a41bfaab72e64d1c170d65667a3617d59313 --- qcom/pm6155.dtsi | 2 - qcom/sa6155-pmic.dtsi | 47 ++ qcom/sa6155.dtsi | 127 +++++ qcom/sm6150-thermal.dtsi | 996 +++++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 18 +- 5 files changed, 1182 insertions(+), 8 deletions(-) create mode 100644 qcom/sm6150-thermal.dtsi diff --git a/qcom/pm6155.dtsi b/qcom/pm6155.dtsi index 4666f0ad2626..cda605b20b87 100644 --- a/qcom/pm6155.dtsi +++ b/qcom/pm6155.dtsi @@ -22,7 +22,6 @@ reg = <0x2400>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; qcom,power-on@800 { @@ -146,7 +145,6 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6155_1_tz>; - wake-capable-sensor; trips { pm6155_trip0: trip0 { diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index c777340b5c4b..f5c3cb70b5ff 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -61,3 +61,50 @@ vdda-0p9-supply = <&pm6155_1_l5>; }; +&thermal_zones { + pm6155-1-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm6155_trip0>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip0_cpu1 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip0_cpu2 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip0_cpu3 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip0_cpu4 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip0_cpu5 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip0_cpu6 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip0_cpu7 { + trip = <&pm6155_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; +}; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 25b695cba9ad..a564ea555b26 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -69,6 +69,133 @@ compatible = "qcom,sa6155-videocc", "syscon"; }; +&thermal_zones { + cpuss-0-step { + trips { + cpu45-config { + temperature = <115000>; + }; + }; + }; + + cpuss-1-step { + trips { + cpu23-config { + temperature = <115000>; + }; + }; + }; + + cpuss-2-step { + trips { + cpu01-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-0-step { + trips { + cpu6-0-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-1-step { + trips { + cpu6-1-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-2-step { + trips { + cpu7-0-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-3-step { + trips { + cpu7-1-config { + temperature = <115000>; + }; + }; + }; + + gpu-step { + trips { + gpu-trip { + temperature = <105000>; + }; + + gpu-cx-mon { + temperature = <110000>; + }; + }; + }; + + q6-hvx-step { + trips { + q6-hvx-config { + temperature = <105000>; + }; + + q6-hvx-trip1 { + temperature = <105000>; + }; + + q6-hvx-cx-mon { + temperature = <110000>; + }; + }; + }; + + mdm-core-step { + trips { + mdm-core-cx-mon { + temperature = <110000>; + }; + }; + }; + + camera-step { + trips { + camera-cx-mon { + temperature = <110000>; + }; + }; + }; + + wlan-step { + trips { + wlan-cx-mon { + temperature = <110000>; + }; + }; + }; + + display-step { + trips { + display-cx-mon { + temperature = <110000>; + }; + }; + }; + + video-step { + trips { + video-cx-mon { + temperature = <110000>; + }; + }; + }; +}; + + #include "sa6155-pcie.dtsi" &slpi_tlmm { status = "ok"; diff --git a/qcom/sm6150-thermal.dtsi b/qcom/sm6150-thermal.dtsi new file mode 100644 index 000000000000..06ac667f7e83 --- /dev/null +++ b/qcom/sm6150-thermal.dtsi @@ -0,0 +1,996 @@ +#include + +&cpufreq_hw { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + }; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; + +&soc { + tsens0: tsens@c222000 { + compatible = "qcom,sm6150-tsens"; + reg = <0xc222000 0x8>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + display-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 9>; + trips { + gpu_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + gpu_cx_mon: gpu-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + gpu-cx-cdev0 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + gpu-cx-cdev1 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + gpu-cx-cdev2 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + gpu-cx-cdev3 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + trips { + cpu45_config: cpu45-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu4_cdev { + trip = <&cpu45_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu5_cdev { + trip = <&cpu45_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + trips { + cpu23_config: cpu23-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu2_cdev { + trip = <&cpu23_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + cpu3_cdev { + trip = <&cpu23_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpuss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + thermal-governor = "step_wise"; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + + cpu1_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "step_wise"; + trips { + cpu6_0_config: cpu6-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu6_cdev { + trip = <&cpu6_0_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + trips { + cpu6_1_config: cpu6-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu6_cdev { + trip = <&cpu6_1_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpu7_0_config: cpu7-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu7_cdev { + trip = <&cpu7_0_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpu7_1_config: cpu7-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu7_cdev { + trip = <&cpu7_1_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + + trips { + q6_hvx_therm: q6-hvx-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_cx_mon: q6-hvx-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&q6_hvx_therm>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 5>; + }; + + hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + hvx-cx-cdev3 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + mdm-core-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + trips { + mdm_core_cx_mon: mdm-core-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm-cx-cdev0 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm-cx-cdev1 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + mdm-cx-cdev2 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + mdm-cx-cdev3 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + camera-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + trips { + camera_cx_mon: camera-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + camera-cx-cdev0 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + camera-cx-cdev1 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + camera-cx-cdev2 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + camera-cx-cdev3 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + wlan-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + trips { + wlan_cx_mon: wlan-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + wlan-cx-cdev0 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + wlan-cx-cdev1 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + wlan-cx-cdev2 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + wlan-cx-cdev3 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + display-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + trips { + dispaly_cx_mon: display-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + display-cx-cdev0 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + display-cx-cdev1 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + display-cx-cdev2 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + display-cx-cdev3 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "step_wise"; + + trips { + video_cx_mon: video-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + video-cx-cdev0 { + trip = <&video_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + video-cx-cdev1 { + trip = <&video_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + video-cx-cdev2 { + trip = <&video_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + video-cx-cdev3 { + trip = <&video_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b273ebb1a19f..7c963503b96e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -54,6 +54,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 6>; + qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -80,7 +81,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0 6>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -101,7 +102,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0 6>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -121,7 +122,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0 6>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -141,7 +142,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0 6>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -161,7 +162,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0 6>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -181,6 +182,7 @@ cache-size = <0x10000>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1 2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; @@ -201,7 +203,7 @@ cache-size = <0x10000>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1 2>; - #cooling-cells = <2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -1518,6 +1520,9 @@ status = "disabled"; }; + thermal_zones: thermal-zones { + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, @@ -2543,3 +2548,4 @@ #include "sm6150-usb.dtsi" #include "sm6150-vidc.dtsi" #include "sm6150-ion.dtsi" +#include "sm6150-thermal.dtsi" From cac4e1c5eb03558bfaf8e7b36675a9cba64c3436 Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Tue, 16 Mar 2021 21:31:56 +0530 Subject: [PATCH 1101/1809] ARM: dts: msm: Add SPS node for sdmshrike Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for sdmshrike. Change-Id: Id3be45719590635dbbd75adaec14fc998427b886 --- qcom/sdmshrike.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6333ee3f9bdf..9196009b8cf7 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -861,6 +861,11 @@ interrupts = ; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; From 7e3c1770c9181010dc5d024af114473d1b50e2ba Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 16 Oct 2020 12:47:17 +0530 Subject: [PATCH 1102/1809] ARM: dts: msm: Add RSC devices for direwolf This change adds apps RSC device. Change-Id: I3fcabf42790e3217cedbfc06f15273c31f060c6f --- qcom/direwolf.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index bd198aa657d5..b7f6d9dd40e8 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Direwolf"; @@ -356,6 +357,28 @@ clock-frequency = <19200000>; }; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + system_pm { + compatible = "qcom,system-pm"; + }; + }; + memtimer: timer@17c20000 { #address-cells = <1>; #size-cells = <1>; From c1cc9ddc15c583a290e7758d72d1323858bfda19 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 16 Oct 2020 13:37:37 +0530 Subject: [PATCH 1103/1809] ARM: dts: msm: Add PDC interrupt controller device for direwolf This change adds PDC irqchip device. Change-Id: Ida7cc0c7b8ffb5f92e03587425b96bb06ecdebae --- qcom/direwolf.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index b7f6d9dd40e8..bedeba2fed68 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -379,6 +379,33 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,direwolf-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x64>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, + <55 306 4>, <59 312 3>, <62 374 2>, + <64 434 2>, <66 438 3>, <69 86 1>, + <70 520 54>, <124 609 28>, <159 638 1>, + <160 720 8>, <168 801 1>, <169 728 30>, + <199 416 2>, <201 449 1>, <202 89 1>, + <203 451 1>, <204 462 1>, <205 264 1>, + <206 579 1>, <207 653 1>, <208 656 1>, + <209 659 1>, <210 122 1>, <211 699 1>, + <212 705 1>, <213 450 1>, <214 643 2>, + <216 646 5>, <221 390 5>, <226 700 3>, + <229 240 3>, <232 269 1>, <233 377 1>, + <234 372 1>, <235 138 1>, <236 857 1>, + <237 860 1>, <238 137 1>, <239 668 1>, + <240 366 1>, <241 949 1>, <242 815 5>, + <247 769 1>, <248 768 1>, <249 663 1>, + <250 799 2>, <252 798 1>, <253 765 1>, + <254 763 1>, <255 454 3>, <258 139 1>, + <259 786 2>, <261 370 2>, <263 158 2>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + memtimer: timer@17c20000 { #address-cells = <1>; #size-cells = <1>; @@ -495,6 +522,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; }; wdog: qcom,wdt@17c10000 { From d3490f36e7bab1dc3bef91026a4d5901018829a0 Mon Sep 17 00:00:00 2001 From: Ashish Kori Date: Mon, 16 Nov 2020 13:33:48 +0530 Subject: [PATCH 1104/1809] dt-bindings: spi-msm-geni: Add flag for SPI responder MISO-MOSI connection Add DT flag entry to support SPI responder MISO<->MOSI(Criss-Cross) connection. Change-Id: I9c83dbb54446134ead9035987561859c55430dd5 --- bindings/spi/qcom,spi-msm-geni.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/spi/qcom,spi-msm-geni.txt b/bindings/spi/qcom,spi-msm-geni.txt index 6805a394b530..813661f42da7 100644 --- a/bindings/spi/qcom,spi-msm-geni.txt +++ b/bindings/spi/qcom,spi-msm-geni.txt @@ -56,6 +56,8 @@ Optional properties: shifted clock phase (CPHA) mode. - qcom,slv-ctrl : Set this flag to configure QUPV3 as SPI slave controller. +- slv-cross-connected : Set this flag only when SPI-Slave MISO pin is connected + to SPI-Master MOSI and vice-versa. Other optional properties described in Documentation/devicetree/bindings/spi/spi-bus.txt From 37ffa2c07c19e0c10e7d79d5b2594d7abc654eee Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Wed, 17 Mar 2021 15:30:43 +0800 Subject: [PATCH 1105/1809] ARM: dts: qcom: Update CPU and GPU mitigation rules on Lahaina HHG Update cpu-1-6-step and cpu-1-7-step thermal zone mitigation rules with CPU and gpuss-0-step and gpuss-1-step thermal zone mitigation rules with GPU based on the latest recommendation. Change-Id: I5721575cac197b976867aa78b98ed5694316d6f0 --- qcom/lahaina-hhg.dtsi | 108 +++++++++++++----------------------------- 1 file changed, 32 insertions(+), 76 deletions(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 386367957b73..4205dd82791d 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -115,25 +115,19 @@ cpu-1-6-step { trips { fan_cpu16_config0: fan-cpu16-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <80000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu16_config1: fan-cpu16-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu16_config2: fan-cpu16-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_cpu16_config3: fan-cpu16-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -142,22 +136,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_cpu16_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_cpu16_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_cpu16_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_cpu16_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -165,25 +154,19 @@ cpu-1-7-step { trips { fan_cpu17_config0: fan-cpu17-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <80000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu17_config1: fan-cpu17-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu17_config2: fan-cpu17-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_cpu17_config3: fan-cpu17-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -192,22 +175,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_cpu17_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_cpu17_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_cpu17_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_cpu17_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -215,25 +193,19 @@ gpuss-0-step { trips { fan_gpuss0_config0: fan-gpuss0-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <85000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss0_config1: fan-gpuss0-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss0_config2: fan-gpuss0-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_gpuss0_config3: fan-gpuss0-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -242,22 +214,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss0_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_gpuss0_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_gpuss0_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_gpuss0_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -265,25 +232,19 @@ gpuss-1-step { trips { fan_gpuss1_config0: fan-gpuss1-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <85000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss1_config1: fan-gpuss1-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss1_config2: fan-gpuss1-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_gpuss1_config3: fan-gpuss1-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -292,22 +253,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss1_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_gpuss1_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_gpuss1_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_gpuss1_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; From 0c1eefcb63121ce8c7a9c6bb7be342ae2a95d5d1 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 8 Mar 2021 17:11:57 +0530 Subject: [PATCH 1106/1809] ARM: dts: msm: Add set_ddr_capped_freq device node interface for SA8195 Add set_ddr_capped_freq interface to send data to the AOP. Change-Id: Iaa6ee564cabe3209f7e89d9ee2c1002b3d53e9dc --- qcom/sdmshrike.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6333ee3f9bdf..88d414e242a5 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -2300,6 +2300,12 @@ qcom,config-arr = <0x18040060 0x18050060 0x18060060 0x18070060>; }; + + aop-set-ddr-freq { + compatible = "qcom,aop-set-ddr-freq"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; #include "sdmshrike-pinctrl.dtsi" From 8491f014f778bd3b931abe02912b0bff92581423 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Wed, 17 Mar 2021 14:31:34 +0530 Subject: [PATCH 1107/1809] ARM: dts: msm: Enable uefi_log memory for sdmshrike Enable uefi_log reserved memory node to read uefi log buffer. Change-Id: I811da1594144464c269ddb83c05a93f1314a98bf --- qcom/sdmshrike.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6333ee3f9bdf..bc979052b5a1 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -443,6 +443,11 @@ size = <0 0x2400000>; }; + uefi_log: uefi_log@0x8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x10000>; + label = "uefi_log"; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From d33d29ecb93bf18c53f10e16170a33db33adae01 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 17 Mar 2021 15:00:35 +0530 Subject: [PATCH 1108/1809] ARM: dts: msm: Add mpm as gpio wakeup parent for sdxnightjar This change adds support to enable wakeup capabilities for gpios. Change-Id: I014b3d439be834ce17fa74eeb2993fc4bf9dd207 --- qcom/sdxnightjar-pinctrl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi index b9546a67ea42..213b46da69a2 100644 --- a/qcom/sdxnightjar-pinctrl.dtsi +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -9,6 +9,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&wakegic>; uart1_console_active: uart1_console_active { mux { From 889f0972db81711a3fa02dad5e5df742a25228d5 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 16 Feb 2021 10:55:04 +0530 Subject: [PATCH 1109/1809] ARM: dts: msm: Enable rpm standalone mode for blair Enable rpm-standalone mode for blair rumi targets. Change-Id: I90a574c4bbe80510c5097ee08a754327536f2638 --- qcom/blair-rumi.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 3527407618aa..903075da46cd 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -120,3 +120,7 @@ &qupv3_se10_i2c { status = "disabled"; }; + +&rpm_bus { + rpm-standalone; +}; From 3abd6cfdc9021f1cc03030d952498b64ace95c89 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 26 Feb 2021 13:12:27 +0530 Subject: [PATCH 1110/1809] dt-bindings: backlight: Add support for exponential dimming Add support to enable writing a lookup table of brightness values into WLED_SINK peripheral to enable more granular control over brightness, to help end user see brightness change smoothly instead of in visible steps. Change-Id: Ieecd52f2af5f8b3d2daea8ff1cd5e8b51e2ad5c6 --- bindings/leds/backlight/qcom-spmi-wled.txt | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/bindings/leds/backlight/qcom-spmi-wled.txt b/bindings/leds/backlight/qcom-spmi-wled.txt index 884d4e4a90f4..de3ea8558edf 100644 --- a/bindings/leds/backlight/qcom-spmi-wled.txt +++ b/bindings/leds/backlight/qcom-spmi-wled.txt @@ -10,9 +10,9 @@ platforms. The PMIC is connected to the host processor via SPMI bus. Definition: should be one of the below. "qcom,pmi8998-spmi-wled", "qcom,pm8150l-spmi-wled", - "qcom,pm6150l-spmi-wled" - "qcom,pm660l-spmi-wled" - "qcom,pm7325b-spmi-wled" + "qcom,pm6150l-spmi-wled", + "qcom,pm660l-spmi-wled", + "qcom,pm7325b-spmi-wled", - reg Usage: required @@ -158,6 +158,22 @@ platforms. The PMIC is connected to the host processor via SPMI bus. For details about IIO bindings see: Documentation/devicetree/bindings/iio/iio-bindings.txt +- qcom,use-exp-dimming + Usage: optional + Value type: + Definition: Specifies that exponential dimming lookup table values + should be used. + +- qcom,exp-dimming-map + Usage: optional + Value type: + Definition: It specifies a table of brightness values that can be programmed + into WLED_SINK for exponential dimming which provides smooth brightness + change. There should be exactly 256 values in the table and they should + be at most 15 bits long. This table would be used only if the + "qcom,use-exp-dimming" property is set. This feature is supported from + PM7325B onwards. + Following properties are for child subnodes that are needed for WLED preflash (or torch), flash and switch. These child subnodes can be specified only for PMICs that has WLED5 (e.g. PM8150L). From 072c0d540508ea72651cca38a1fccafd62c304fe Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 15 Mar 2021 15:33:35 +0530 Subject: [PATCH 1111/1809] dt-bindings: backlight: Add support to configure slew ramp time Add support to configure slew ramp time for brightness change by adding a DT property named "qcom,slew-ramp-time". Change-Id: I1264e120c84cf0f0b339ff883c9de589f058403f --- bindings/leds/backlight/qcom-spmi-wled.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/leds/backlight/qcom-spmi-wled.txt b/bindings/leds/backlight/qcom-spmi-wled.txt index de3ea8558edf..35685ecc9f40 100644 --- a/bindings/leds/backlight/qcom-spmi-wled.txt +++ b/bindings/leds/backlight/qcom-spmi-wled.txt @@ -174,6 +174,15 @@ platforms. The PMIC is connected to the host processor via SPMI bus. "qcom,use-exp-dimming" property is set. This feature is supported from PM7325B onwards. +- qcom,slew-ramp-time + Usage: optional + Value type: + Definition: Software brightness slew ramp time values in ms. This is supported from + PM7325B onwards. + Valid values are 2, 4, 8, 64, 128, 192, 256, 320, 384, 448, 512, 704, 896, + 1024, 2048, 4096. + Default: 256 + Following properties are for child subnodes that are needed for WLED preflash (or torch), flash and switch. These child subnodes can be specified only for PMICs that has WLED5 (e.g. PM8150L). From 3e1e54a30922f8d1ef8b1efcb68ab0eb65b39f33 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Fri, 5 Mar 2021 23:00:48 +0530 Subject: [PATCH 1112/1809] ARM: dts: msm: Enable pil and dload support for Monaco Add lpass, modem and download mode nodes for Monaco. Change-Id: I6fc30d3d79c855172aba55199b283a7e48088587 --- qcom/monaco.dtsi | 174 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 147 insertions(+), 27 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4dcfa5c02af6..4e8849fa427f 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include / { @@ -22,6 +23,8 @@ hsuart0 = &qupv3_se5_4uart; }; + firmware: firmware {}; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -127,27 +130,8 @@ soc: soc { }; - firmware: firmware { - android { - compatible = "android,firmware"; - vbmeta { - compatible="android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo,recovery"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = - "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; - }; - }; + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; reserved-memory { @@ -260,9 +244,33 @@ linux,cma-default; }; }; +}; - chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = + "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; }; }; @@ -406,10 +414,8 @@ }; }; - restart@440b000 { - compatible = "qcom,pshold"; - reg = <0x440b000 0x4>, <0x03d3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; + dload_mode { + compatible = "qcom,dload-mode"; }; qcom,mpm2-slepp-counter@4403000 { @@ -444,6 +450,23 @@ qcom,wakeup-enable; }; + eud: qcom,msm-eud@1610000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1610000 0x2000>, + <0x1612000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + qcom,eud-clock-vote-req; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; @@ -542,6 +565,98 @@ }; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; + }; + + qcom,lpass@ab00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xab00000 0x00100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <1>; + qcom,minidump-id = <5>; + qcom,ssctl-instance-id = <0x14>; + qcom,pas-id = <1>; + qcom,smem-id = <423>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + pil_modem: qcom,mss@6080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x6080000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + qcom,sequential-fw-load; + + /* Inputs from mss */ + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -654,6 +769,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@03c0000 { + compatible = "syscon"; + reg = <0x03c0000 0x30000>; + }; + smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_region>; From 9405d30b3d9ea564b225c7c2e35e7fc58a264981 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Thu, 25 Feb 2021 14:07:47 +0530 Subject: [PATCH 1113/1809] ARM: dts: msm: Add 128k and 265k pools for Lahaina Add additional pools of size 128k and 256k to mempool. Change-Id: Ibf563430d4b882dd0bece47b46af12ae00fccc0e --- qcom/lahaina-gpu.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index b95afe9c0a9a..925edea2b353 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -133,14 +133,12 @@ reg = <0>; qcom,mempool-page-size = <4096>; qcom,mempool-reserved = <2048>; - qcom,mempool-allocate; }; /* 8K Page Pool configuration */ qcom,gpu-mempool@1 { reg = <1>; qcom,mempool-page-size = <8192>; qcom,mempool-reserved = <1024>; - qcom,mempool-allocate; }; /* 64K Page Pool configuration */ qcom,gpu-mempool@2 { @@ -148,9 +146,21 @@ qcom,mempool-page-size = <65536>; qcom,mempool-reserved = <256>; }; - /* 1M Page Pool configuration */ + /* 128K Page Pool configuration */ qcom,gpu-mempool@3 { reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; qcom,mempool-page-size = <1048576>; qcom,mempool-reserved = <32>; }; From 1141b39b8e9c86e14b2e8970d8495c93edde6876 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Wed, 17 Mar 2021 14:36:13 +0530 Subject: [PATCH 1114/1809] ARM: dts: msm: Enable uefi_log memory for SA6155 Enable uefi_log reserved memory node to read uefi log buffer. Change-Id: I3a2f498a2c7ff5ba3811dee292bf42533e4a2655 --- qcom/sa6155.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index a564ea555b26..e092a8907c96 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -195,6 +195,12 @@ }; }; +&reserved_memory { + uefi_log: uefi_log@0x9241C000 { + reg = <0x0 0x9241C000 0x0 0x10000>; + label = "uefi_log"; + }; +}; #include "sa6155-pcie.dtsi" &slpi_tlmm { From 7cb7f5595d0c0fe846b5a2653ec4c3306b220ef1 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Wed, 10 Feb 2021 23:33:30 +0530 Subject: [PATCH 1115/1809] ARM: dts: msm: Fix compilation errors for monaco Remove Scube dts compilation for monaco as it is breaking compilation for monaco. Change-Id: I537f253eefbf8a3579d6a7166b1d8c6eaecd3471 --- qcom/Makefile | 6 ------ 1 file changed, 6 deletions(-) diff --git a/qcom/Makefile b/qcom/Makefile index d7d88aff5c88..f96e365eb746 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -93,12 +93,6 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-v2.1-qrd-hsp-pro.dts endif -ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) -dtbo-$(CONFIG_ARCH_SCUBA) += scuba-iot-idp-overlay.dtbo - -scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb -endif - ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-mtp-overlay.dtbo \ From 0fd1f90a0857a8a458322819e31c52b82e1a6e4b Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 18 Mar 2021 11:21:21 +0530 Subject: [PATCH 1116/1809] ARM: dts: msm: Remove PCIE clock from YUPIK IOT QRD The PCIE clocks are not controlled from HLOS, thus move them to protected list on QRD platform. Change-Id: Ib93386bf3b29c2cbaa8b04dc76da8f8f5918ae74 --- qcom/yupik-iot-qrd.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/qcom/yupik-iot-qrd.dtsi b/qcom/yupik-iot-qrd.dtsi index aa5635d74c44..8964f1cca55d 100644 --- a/qcom/yupik-iot-qrd.dtsi +++ b/qcom/yupik-iot-qrd.dtsi @@ -1 +1,40 @@ #include "yupik-qrd.dtsi" +#include +#include + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + + protected-clocks = , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; +}; + +&gcc_pcie_0_gdsc { + status = "disabled"; +}; + +&gcc_pcie_1_gdsc { + status = "disabled"; +}; From 7c4889dd688fff08af26f46f70ff0f822f8b2a12 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 20 Jan 2021 22:05:35 +0530 Subject: [PATCH 1117/1809] ARM: dts: qcom: Enable the second UFS instance Enable the second UFS instance and also configure vddp-ref-clk supply, rpm-level, spm-level. Keep L17A and L10E always on and configure the L17A to run always in HPM mode, we need this regulator settings to avoid crash when rebooting. Change-Id: Ib3c9563c4a7fb3121c8e4d17e93a81a5c3a6fef7 --- qcom/sa8195p-regulator.dtsi | 7 +- qcom/sa8195p.dtsi | 30 ++++++++ qcom/sdmshrike.dtsi | 137 ++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 2 deletions(-) diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi index 5d480a9a464b..2554e103dc92 100644 --- a/qcom/sa8195p-regulator.dtsi +++ b/qcom/sa8195p-regulator.dtsi @@ -336,10 +336,12 @@ L17A: pm8195_1_l17: regulator-pm8195-1-l17 { regulator-name = "pm8195_1_l17"; qcom,set = ; - regulator-min-microvolt = <1700000>; + regulator-min-microvolt = <2504000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <1700000>; + qcom,init-voltage = <2904000>; qcom,init-mode = ; + regulator-system-load = <1>; + regulator-always-on; }; }; @@ -694,6 +696,7 @@ regulator-max-microvolt = <3544000>; qcom,init-voltage = <2500000>; qcom,init-mode = ; + regulator-always-on; }; }; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 10532f45caff..9ed8062fb621 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -59,6 +59,36 @@ status= "ok"; }; +&ufs2phy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + vdda-phy-supply = <&pm8195_3_l5>; + vdda-pll-supply = <&pm8195_1_l9>; + vdda-phy-max-microamp = <138000>; + vdda-pll-max-microamp = <65100>; + + status = "ok"; +}; + +&ufshc2_mem { + vdd-hba-supply = <&ufs_card_2_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8195_1_l17>; + vcc-voltage-level = <2894000 2904000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8195_2_l5>; + vccq2-supply = <&pm8195_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vccq-parent-supply = <&pm8195_1_s2>; + qcom,vccq-parent-max-microamp = <210000>; + + status= "ok"; +}; + &usb2_phy0 { vdd-supply = <&pm8195_3_l5>; vdda18-supply = <&pm8195_1_l12>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 300784e45dbf..500293df7983 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -35,6 +35,7 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */ serial0 = &qupv3_se12_2uart; sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ spi22 = &qupv3_se22_spi; @@ -1431,6 +1432,8 @@ interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + spm-level = <5>; + rpm-level = <1>; #reset-cells = <1>; lanes-per-direction = <2>; @@ -1536,6 +1539,140 @@ status = "disabled"; }; + ufs2phy_mem: ufsphy_mem@1d67000 { + reg = <0x1d67000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>; + + resets = <&ufshc2_mem 0>; + status = "disabled"; + }; + + ufshc2_mem: ufshc@1d64000 { + compatible = "qcom,ufshc"; + reg = <0x1d64000 0x3000>, + <0x1d70000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufs2phy_mem>; + phy-names = "ufsphy"; + spm-level = <5>; + rpm-level = <1>; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_CARD_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>, + <&gcc GCC_UFS_CARD_2_AHB_CLK>, + <&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = + <&aggre1_noc MASTER_UFS_GEN4 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_UFS_MEM_1_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_CARD_2_BCR>; + reset-names = "rst"; + + secondary-storage; + status = "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1000>, From aa7a99f54bb1541008633b62b03292ea88ed26d8 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Fri, 19 Mar 2021 16:55:12 +0530 Subject: [PATCH 1118/1809] ARM: dts: msm: Update correct masters for sdxnightjar This change updates master with supported subsystems in master stats node. Change-Id: Iac77f1dad0847cee76618ea4e4b172bd32f44ec4 --- qcom/sdxnightjar-pm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar-pm.dtsi b/qcom/sdxnightjar-pm.dtsi index 38faa981f8fa..aa6afdbc5301 100644 --- a/qcom/sdxnightjar-pm.dtsi +++ b/qcom/sdxnightjar-pm.dtsi @@ -123,7 +123,7 @@ qcom,rpm-master-stats@60150 { compatible = "qcom,rpm-master-stats"; reg = <0x60150 0x2030>; - qcom,masters = "APSS", "MPSS", "PRONTO"; + qcom,masters = "APSS", "MPSS"; qcom,master-stats-version = <2>; qcom,master-offset = <4096>; }; From 66fca01b1e4bd5f43166f633e447d4ab8007e061 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 15 Mar 2021 14:58:19 +0530 Subject: [PATCH 1119/1809] ARM: dts: msm: Add spmi device tree node Add spmi pmic and its dependent device tree node to support SA6155P for automotive platforms. Change-Id: I91acb8db1ef080ffdcb040cd3b56a5ce1bb1556d --- qcom/sa6155p-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 9b4451e48293..4665c31c8df1 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -318,6 +318,7 @@ #include "sa6155p-vm-pcie.dtsi" #include "sm6150-qupv3.dtsi" #include "sa8155-vm-audio.dtsi" +#include "pm6155-vm.dtsi" &tlmm { /delete-property/ wakeup-parent; From d7e86a736f008a3d05ce3f8a6910fe195245aeca Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 18 Mar 2021 16:11:45 -0700 Subject: [PATCH 1120/1809] ARM: dts: msm: Fix phandle lookup failures for apsscc on sdxlemur Fix typo in apsscc that causes clock phandle lookups to fail. Change-Id: Ibc0c2f73bbedcbe8bdcb34418c790ba7a467778a --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 2f8710fd492c..a90d8dd61418 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -601,7 +601,7 @@ < 576000000 RPMH_REGULATOR_LEVEL_SVS>, < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, < 1497600000 RPMH_REGULATOR_LEVEL_TURBO>; - #reset-cells = <1>; + #clock-cells = <1>; }; apps_rsc: rsc@17830000 { From 7510bb8092d9626ffa861c0e53a51a9790ee6d9f Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 18 Mar 2021 15:52:43 -0700 Subject: [PATCH 1121/1809] ARM: dts: msm: Add bindings for cpufreq Add device tree node for cpufreq. Change-Id: I5aef58aad39a26544d670fdd7fe6d56d3bb5b16f --- qcom/sdxlemur.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..2bc203b1f120 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -246,6 +246,17 @@ interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clocks = <&apsscc APCS_MUX_CLK>; + clock-names = "cpu0_clk"; + qcom,cpufreq-table = + < 345600 >, + < 576000 >, + < 1094400 >, + < 1497600 >; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From a48a052dc19f569090cdfec6ed0bf3c36561eab9 Mon Sep 17 00:00:00 2001 From: katamoni sai abhilash Date: Thu, 11 Mar 2021 09:35:17 +0530 Subject: [PATCH 1122/1809] ARM: dts: msm: Remove disable shmbridge property sa8195 GVM Removed boolean property to disable shmbridge. Change-Id: I95b31f549bc4cbddd17b37930509ff200b146024 --- qcom/sa8195-vm.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index befd55eb94c2..3733dcb5b112 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -621,8 +621,6 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; - /*Boolean property to disable shmbridge*/ - qcom,disable-shmbridge-support; }; qcom_qseecom: qseecom@87a00000 { From 67fad824b7e9ea7aad4481ee6cad8609e2eb353e Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 9 Oct 2020 07:04:24 +0530 Subject: [PATCH 1123/1809] ARM: dts: msm: Add RPMh controlled PMIC regulators for direwolf Add regulator devices for direwolf as RPMh regulators. This ensures that consumers are able to modify the physical state of the PMIC regulators. Change-Id: Ia9cdaa0f389457196f1cef8e1e459df9e8ccca95 --- qcom/direwolf-ivi-regulators.dtsi | 97 ++++ qcom/direwolf-ivi.dtsi | 1 + qcom/direwolf-regulators.dtsi | 731 ++++++++++++++++++++++++++++++ qcom/direwolf.dtsi | 1 + 4 files changed, 830 insertions(+) create mode 100644 qcom/direwolf-ivi-regulators.dtsi create mode 100644 qcom/direwolf-regulators.dtsi diff --git a/qcom/direwolf-ivi-regulators.dtsi b/qcom/direwolf-ivi-regulators.dtsi new file mode 100644 index 000000000000..0dbc0e2fefc0 --- /dev/null +++ b/qcom/direwolf-ivi-regulators.dtsi @@ -0,0 +1,97 @@ +#include + +&apps_rsc { + rpmh-regulator-ldoa015 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A0: + pm8540_a0_l15: regulator-pm8540_a0-l15 { + regulator-name = "pm8540_a0_l15"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc012 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12C0: + pm8540_c0_l12: regulator-pm8540_c0-l12 { + regulator-name = "pm8540_c0_l12"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-smpe04 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe4"; + S4E0: + pm8540_e0_s4: regulator-pm8540_e0-s4 { + regulator-name = "pm8540_e0_s4"; + qcom,set = ; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <320000>; + }; + }; + + rpmh-regulator-ldog06 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6G0: + pm8540_g0_l6: regulator-pm8540_g0-l6 { + regulator-name = "pm8540_g0_l6"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <312000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldog011 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11G0: + pm8540_g0_l11: regulator-pm8540_g0-l11 { + regulator-name = "pm8540_g0_l11"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <830000>; + qcom,init-mode = + ; + }; + }; + +}; diff --git a/qcom/direwolf-ivi.dtsi b/qcom/direwolf-ivi.dtsi index d69dedfd0352..9f12fa8801c1 100644 --- a/qcom/direwolf-ivi.dtsi +++ b/qcom/direwolf-ivi.dtsi @@ -1,4 +1,5 @@ #include "direwolf.dtsi" +#include "direwolf-ivi-regulators.dtsi" / { model = "Qualcomm Technologies, Inc. DirewolfAU IVI SoC"; diff --git a/qcom/direwolf-regulators.dtsi b/qcom/direwolf-regulators.dtsi new file mode 100644 index 000000000000..de3fed27f77c --- /dev/null +++ b/qcom/direwolf-regulators.dtsi @@ -0,0 +1,731 @@ +#include + +&apps_rsc { + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: + S1A0_LEVEL: + pm8540_a0_s1_level: regulator-pm8540_a0-s1-level { + regulator-name = "pm8540_a0_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S1A0_LEVEL_AO: + pm8540_a0_s1_level_ao: regulator-pm8540_a0-s1-level-ao { + regulator-name = "pm8540_a0_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mmcx.lvl"; + proxy-supply = <&VDD_MMCX_LEVEL>; + + VDD_MMCX_LEVEL: + S7A0_LEVEL: + pm8540_a0_s7_level: regulator-pm8540_a0-s7-level { + regulator-name = "pm8540_a0_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MMCX_LEVEL_AO: + S7A0_LEVEL_AO: + pm8540_a0_s7_level_ao: regulator-pm8540_a0-s7-level-ao { + regulator-name = "pm8540_a0_s7_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + + VDD_LPI_MX_LEVEL: + L6A0_LEVEL: + pm8540_a0_l6_level: regulator-pm8540_a0-l6-level { + regulator-name = "pm8540_a0_l6_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + + VDD_LPI_CX_LEVEL: + L9A0_LEVEL: + pm8540_a0_l9_level: regulator-pm8540_a0-l9-level { + regulator-name = "pm8540_a0_l9_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: + S7C0_LEVEL: + pm8540_c0_s7_level: regulator-pm8540_c0-s7-level { + regulator-name = "pm8540_c0_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: + S7C0_LEVEL_AO: + pm8540_c0_s7_level_ao: regulator-pm8540_c0-s7-level-ao { + regulator-name = "pm8540_c0_s7_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + + VDD_EBI_LEVEL: + S3E0_LEVEL: + pm8540_e0_s3_level: regulator-pm8540_e0-s3-level { + regulator-name = "pm8540_e0_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + proxy-supply = <&VDD_MXC_LEVEL>; + + VDD_MXC_LEVEL: + S8E0_LEVEL: + pm8540_e0_s8_level: regulator-pm8540_e0-s8-level { + regulator-name = "pm8540_e0_s8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXC_LEVEL_AO: + S8E0_LEVEL_AO: + pm8540_e0_s8_level_ao: regulator-pm8540_e0-s8-level-ao { + regulator-name = "pm8540_e0_s8_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpa03 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa3"; + S3A0: + pm8540_a0_s3: regulator-pm8540_a0-s3 { + regulator-name = "pm8540_a0_s3"; + qcom,set = ; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1060000>; + }; + }; + + rpmh-regulator-smpa04 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa4"; + S4A0: + pm8540_a0_s4: regulator-pm8540_a0-s4 { + regulator-name = "pm8540_a0_s4"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1620000>; + }; + }; + + rpmh-regulator-smpa05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa5"; + S5A0: + pm8540_a0_s5: regulator-pm8540_a0-s5 { + regulator-name = "pm8540_a0_s5"; + qcom,set = ; + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1574000>; + }; + }; + + rpmh-regulator-ldoa02 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A0: + pm8540_a0_l2: regulator-pm8540_a0-l2 { + regulator-name = "pm8540_a0_l2"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa03 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A0: + pm8540_a0_l3: regulator-pm8540_a0-l3 { + regulator-name = "pm8540_a0_l3"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1140000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A0: + pm8540_a0_l5: regulator-pm8540_a0-l5 { + regulator-name = "pm8540_a0_l5"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <720000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa07 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A0: + pm8540_a0_l7: regulator-pm8540_a0-l7 { + regulator-name = "pm8540_a0_l7"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa011 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A0: + pm8540_a0_l11: regulator-pm8540_a0-l11 { + regulator-name = "pm8540_a0_l11"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <830000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa012 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A0: + pm8540_a0_l12: regulator-pm8540_a0-l12 { + regulator-name = "pm8540_a0_l12"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoa013 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A0: + pm8540_a0_l13: regulator-pm8540_a0-l13 { + regulator-name = "pm8540_a0_l13"; + qcom,set = ; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2970000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-smpc04 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc4"; + S4C0: + pm8540_c0_s4: regulator-pm8540_c0-s4 { + regulator-name = "pm8540_c0_s4"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpc05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc5"; + S5C0: + pm8540_c0_s5: regulator-pm8540_c0-s5 { + regulator-name = "pm8540_c0_s5"; + qcom,set = ; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1374000>; + qcom,init-voltage = <382000>; + }; + }; + + rpmh-regulator-ldoc01 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1C0: + pm8540_c0_l1: regulator-pm8540_c0-l1 { + regulator-name = "pm8540_c0_l1"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <720000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc02 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C0: + pm8540_c0_l2: regulator-pm8540_c0-l2 { + regulator-name = "pm8540_c0_l2"; + qcom,set = ; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2970000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc03 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3C0: + pm8540_c0_l3: regulator-pm8540_c0-l3 { + regulator-name = "pm8540_c0_l3"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc04 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C0: + pm8540_c0_l4: regulator-pm8540_c0-l4 { + regulator-name = "pm8540_c0_l4"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1140000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C0: + pm8540_c0_l5: regulator-pm8540_c0-l5 { + regulator-name = "pm8540_c0_l5"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1140000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc06 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C0: + pm8540_c0_l6: regulator-pm8540_c0-l6 { + regulator-name = "pm8540_c0_l6"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc07 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C0: + pm8540_c0_l7: regulator-pm8540_c0-l7 { + regulator-name = "pm8540_c0_l7"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldoc017 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17C0: + pm8540_c0_l17: regulator-pm8540_c0-l17 { + regulator-name = "pm8540_c0_l17"; + qcom,set = ; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2400000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-smpe05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe5"; + S5E0: + pm8540_e0_s5: regulator-pm8540_e0-s5 { + regulator-name = "pm8540_e0_s5"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + }; + }; + + rpmh-regulator-smpe09 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe9"; + S9E0: + pm8540_e0_s9: regulator-pm8540_e0-s9 { + regulator-name = "pm8540_e0_s9"; + qcom,set = ; + regulator-min-microvolt = <370000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <370000>; + }; + }; + + rpmh-regulator-ldoe02 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2E0: + pm8540_e0_l2: regulator-pm8540_e0-l2 { + regulator-name = "pm8540_e0_l2"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-smpg03 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg3"; + S3G0: + pm8540_g0_s3: regulator-pm8540_g0-s3 { + regulator-name = "pm8540_g0_s3"; + qcom,set = ; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <968000>; + qcom,init-voltage = <352000>; + }; + }; + + rpmh-regulator-smpg04 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg4"; + S4G0: + pm8540_g0_s4: regulator-pm8540_g0-s4 { + regulator-name = "pm8540_g0_s4"; + qcom,set = ; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1374000>; + qcom,init-voltage = <382000>; + }; + }; + + rpmh-regulator-smpg05 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg5"; + S5G0: + pm8540_g0_s5: regulator-pm8540_g0-s5 { + regulator-name = "pm8540_g0_s5"; + qcom,set = ; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <995000>; + qcom,init-voltage = <382000>; + }; + }; + + rpmh-regulator-ldog02 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2G0: + pm8540_g0_l2: regulator-pm8540_g0-l2 { + regulator-name = "pm8540_g0_l2"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldog03 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3G0: + pm8540_g0_l3: regulator-pm8540_g0-l3 { + regulator-name = "pm8540_g0_l3"; + qcom,set = ; + regulator-min-microvolt = <1130000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1130000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldog07 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7G0: + pm8540_g0_l7: regulator-pm8540_g0-l7 { + regulator-name = "pm8540_g0_l7"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = + ; + }; + }; + + rpmh-regulator-ldog08 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8G0: + pm8540_g0_l8: regulator-pm8540_g0-l8 { + regulator-name = "pm8540_g0_l8"; + qcom,set = ; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + qcom,init-voltage = <825000>; + qcom,init-mode = + ; + }; + }; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index bedeba2fed68..05a81d24c952 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -548,3 +548,4 @@ }; #include "direwolf-pinctrl.dtsi" +#include "direwolf-regulators.dtsi" From 5cc35f2295bdf6766d8db4f2c3f5eb26a18e466c Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 10 Mar 2021 15:49:20 +0530 Subject: [PATCH 1124/1809] ARM: dts: msm: Add iio support for pmi632 Add charger and QG support for the targets using pmi632 and pm6125. While at it, also update the pm6125 and pmi632 nodes for msm-5.4. Change-Id: I79641b72c5424708a971273de740233767efd5aa --- qcom/pm6125.dtsi | 41 ++++-------- qcom/pmi632.dtsi | 81 ++++++++--------------- qcom/pmi632_pm6125_iio.dtsi | 127 ++++++++++++++++++++++++++++++++++++ 3 files changed, 168 insertions(+), 81 deletions(-) create mode 100644 qcom/pmi632_pm6125_iio.dtsi diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index fc8444727f6d..bc79c4423abf 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include &spmi_bus { #address-cells = <2>; @@ -13,7 +14,7 @@ qcom,pm6125@0 { compatible = "qcom,spmi-pmic"; reg = <0x0 0x0>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; qcom,power-on@800 { @@ -29,13 +30,13 @@ qcom,pon_1 { qcom,pon-type = ; - qcom,pull-up = <1>; + qcom,pull-up; linux,code = ; }; qcom,pon_2 { qcom,pon-type = ; - qcom,pull-up = <1>; + qcom,pull-up; linux,code = ; }; }; @@ -47,43 +48,42 @@ #size-cells = <0>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eoc-int-en-set"; - qcom,adc-vdd-reference = <1875>; #io-channel-cells = <1>; io-channel-ranges; /* Channel nodes */ ref_gnd { - reg = ; + reg = ; label = "ref_gnd"; qcom,pre-scaling = <1 1>; }; vref_1p25 { - reg = ; + reg = ; label = "vref_1p25"; qcom,pre-scaling = <1 1>; }; die_temp { - reg = ; + reg = ; label = "die_temp"; qcom,pre-scaling = <1 1>; }; vph_pwr { - reg = ; + reg = ; label = "vph_pwr"; qcom,pre-scaling = <1 3>; }; vcoin { - reg = ; + reg = ; label = "vcoin"; qcom,pre-scaling = <1 3>; }; xo_therm { - reg = ; + reg = ; label = "xo_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -105,8 +105,9 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm6125_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; - qcom,temperature-threshold-set = <1>; }; pm6125_clkdiv: clock-controller@5b00 { @@ -117,29 +118,15 @@ clock-output-names = "pm6125_div_clk1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; - assigned-clocks = <&pm6125_clkdiv 1>; - assigned-clock-rates = <9600000>; }; pm6125_gpios: pinctrl@c000 { compatible = "qcom,pm6125-gpio"; reg = <0xc000>; - interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, - <0x0 0xc1 0 IRQ_TYPE_NONE>, - <0x0 0xc2 0 IRQ_TYPE_NONE>, - <0x0 0xc3 0 IRQ_TYPE_NONE>, - <0x0 0xc4 0 IRQ_TYPE_NONE>, - <0x0 0xc5 0 IRQ_TYPE_NONE>, - <0x0 0xc6 0 IRQ_TYPE_NONE>, - <0x0 0xc7 0 IRQ_TYPE_NONE>, - <0x0 0xc8 0 IRQ_TYPE_NONE>; - interrupt-names = "pm6125_gpio1", "pm6125_gpio2", - "pm6125_gpio3", "pm6125_gpio4", - "pm6125_gpio5", "pm6125_gpio6", - "pm6125_gpio7", "pm6125_gpio8", - "pm6125_gpio9"; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + interrupt-cells = <2>; }; pm6125_rtc: qcom,pm6125_rtc { diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index a1b0428668f9..dcab23df597b 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -11,7 +11,7 @@ qcom,pmi632@2 { compatible = "qcom,spmi-pmic"; reg = <0x2 0x0>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; pmi632_pon: qcom,power-on@800 { @@ -21,68 +21,65 @@ pmi632_vadc: vadc@3100 { compatible = "qcom,spmi-adc5-lite"; - reg = <0x3100>, <0x3700>; - reg-names = "adc5-usr-base", "adc5-cal-base"; + reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eoc-int-en-set"; - qcom,adc-vdd-reference = <1875>; #io-channel-cells = <1>; io-channel-ranges; - qcom,pmic-revid = <&pmi632_revid>; /* Channel nodes */ ref_gnd { - reg = ; + reg = ; label = "ref_gnd"; qcom,pre-scaling = <1 1>; }; vref_1p25 { - reg = ; + reg = ; label = "vref_1p25"; qcom,pre-scaling = <1 1>; }; die_temp { - reg = ; + reg = ; label = "die_temp"; qcom,pre-scaling = <1 1>; }; vph_pwr { - reg = ; + reg = ; label = "vph_pwr"; qcom,pre-scaling = <1 3>; }; vbat_sns { - reg = ; + reg = ; label = "vbat_sns"; qcom,pre-scaling = <1 3>; }; usb_in_i_uv { - reg = ; + reg = ; label = "usb_in_i_uv"; qcom,pre-scaling = <1 1>; }; usb_in_v_div_16 { - reg = ; + reg = ; label = "usb_in_v_div_16"; qcom,pre-scaling = <1 16>; }; chg_temp { - reg = ; + reg = ; label = "chg_temp"; qcom,pre-scaling = <1 1>; }; bat_therm { - reg = ; + reg = ; label = "bat_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -90,7 +87,7 @@ }; bat_therm_30k { - reg = ; + reg = ; label = "bat_therm_30k"; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -98,7 +95,7 @@ }; bat_therm_400k { - reg = ; + reg = ; label = "bat_therm_400k"; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -106,7 +103,7 @@ }; bat_id { - reg = ; + reg = ; label = "bat_id"; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -114,23 +111,11 @@ }; i_parallel { - reg = ; + reg = ; label = "i_parallel"; qcom,pre-scaling = <1 1>; }; - v_i_int_ext { - reg = ; - label = "v_i_int_vbat_vdata"; - qcom,pre-scaling = <1 1>; - }; - - v_i_parallel { - reg = ; - label = "v_i_parallel_vbat_vdata"; - qcom,pre-scaling = <1 1>; - }; - }; pmi632_adc_tm: adc_tm@3500 { @@ -147,6 +132,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmi632_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; qcom,temperature-threshold-set = <1>; }; @@ -154,33 +141,22 @@ pmi632_gpios: pinctrl@c000 { compatible = "qcom,pmi632-gpio"; reg = <0xc000>; - interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, - <0x2 0xc1 0 IRQ_TYPE_NONE>, - <0x2 0xc2 0 IRQ_TYPE_NONE>, - <0x2 0xc3 0 IRQ_TYPE_NONE>, - <0x2 0xc4 0 IRQ_TYPE_NONE>, - <0x2 0xc5 0 IRQ_TYPE_NONE>, - <0x2 0xc6 0 IRQ_TYPE_NONE>, - <0x2 0xc7 0 IRQ_TYPE_NONE>; - interrupt-names = "pmi632_gpio1", "pmi632_gpio2", - "pmi632_gpio3", "pmi632_gpio4", - "pmi632_gpio5", "pmi632_gpio6", - "pmi632_gpio7", "pmi632_gpio8"; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + interrupt-cells = <2>; }; pmi632_charger: qcom,qpnp-smb5 { compatible = "qcom,qpnp-smb5"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #cooling-cells = <2>; - qcom,pmic-revid = <&pmi632_revid>; - io-channels = <&pmi632_vadc ADC_USB_IN_V_16>, - <&pmi632_vadc ADC_USB_IN_I>, - <&pmi632_vadc ADC_CHG_TEMP>, - <&pmi632_vadc ADC_DIE_TEMP>; + io-channels = <&pmi632_vadc ADC5_USB_IN_V_16>, + <&pmi632_vadc ADC5_USB_IN_I>, + <&pmi632_vadc ADC5_CHG_TEMP>, + <&pmi632_vadc ADC5_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -340,11 +316,10 @@ pmi632_qg: qpnp,qg { compatible = "qcom,qpnp-qg"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; - qcom,pmic-revid = <&pmi632_revid>; - io-channels = <&pmi632_vadc ADC_BAT_THERM_PU2>, - <&pmi632_vadc ADC_BAT_ID_PU2>; + io-channels = <&pmi632_vadc ADC5_BAT_THERM_100K_PU>, + <&pmi632_vadc ADC5_BAT_ID_100K_PU>; io-channel-names = "batt-therm", "batt-id"; @@ -485,7 +460,6 @@ interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "sc-irq"; - qcom,pmic-revid = <&pmi632_revid>; qcom,voltage-step-ramp; lcdb_ldo_vreg: ldo { @@ -527,7 +501,6 @@ qcom,thermal-derate-en; qcom,thermal-derate-current = <200 500 1000>; qcom,isc-delay = <192>; - qcom,pmic-revid = <&pmi632_revid>; pmi632_flash0: qcom,flash_0 { label = "flash"; diff --git a/qcom/pmi632_pm6125_iio.dtsi b/qcom/pmi632_pm6125_iio.dtsi new file mode 100644 index 000000000000..8e5da5b359ab --- /dev/null +++ b/qcom/pmi632_pm6125_iio.dtsi @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include "pmi632.dtsi" +#include "pm6125.dtsi" + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&pmi632_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pmi632_vadc ADC5_USB_IN_V_16>, + <&pmi632_vadc ADC5_USB_IN_I>, + <&pmi632_vadc ADC5_CHG_TEMP>, + <&pmi632_vadc ADC5_DIE_TEMP>; + <&pmi632_qg PSY_IIO_RESISTANCE_ID>, + <&pmi632_qg PSY_IIO_VOLTAGE_NOW>, + <&pmi632_qg PSY_IIO_TEMP>, + <&pmi632_qg PSY_IIO_CAPACITY>, + <&pmi632_qg PSY_IIO_VOLTAGE_OCV>, + <&pmi632_qg PSY_IIO_VOLTAGE_AVG>, + <&pmi632_qg PSY_IIO_DEBUG_BATTERY>, + <&pmi632_qg PSY_IIO_REAL_CAPACITY>, + <&pmi632_qg PSY_IIO_CC_SOC>, + <&pmi632_qg PSY_IIO_CURRENT_NOW>, + <&pmi632_qg PSY_IIO_VOLTAGE_MAX>, + <&pmi632_qg PSY_IIO_CHARGE_FULL>, + <&pmi632_qg PSY_IIO_CHARGE_COUNTER>, + <&pmi632_qg PSY_IIO_CYCLE_COUNT>, + <&pmi632_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pmi632_qg PSY_IIO_TIME_TO_FULL_NOW>, + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,hvdcp2-max-icl-ua = <2000000>; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,float-option = <1>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; +}; + +&pmi632_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pmi632_vadc ADC5_BAT_THERM_100K_PU>, + <&pmi632_vadc ADC5_BAT_ID_100K_PU>; + <&pmi632_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pmi632_charger PSY_IIO_RECHARGE_SOC>, + <&pmi632_charger PSY_IIO_FORCE_RECHARGE>, + <&pmi632_charger PSY_IIO_CHARGE_DONE>, + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,qg-use-s7-ocv; +}; From ee683fa55f976045d459b8224ab71ffb55a7e68d Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Mon, 22 Mar 2021 19:09:09 +0530 Subject: [PATCH 1125/1809] ARM: dts: msm: Update 0.9 vreg property for PCIe on sdxnightjar Update DT property such that driver can parse 0.9 vreg configuration for PCIe on sdxnightjar. Change-Id: I8980383959eb91ed820a71a63bd0d2edbbc3a0e9 --- qcom/sdxnightjar-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar-pcie.dtsi b/qcom/sdxnightjar-pcie.dtsi index e24376cf48c2..91640288ef9a 100644 --- a/qcom/sdxnightjar-pcie.dtsi +++ b/qcom/sdxnightjar-pcie.dtsi @@ -43,7 +43,7 @@ vreg-1p8-supply = <&pmd9650_l5>; vreg-0p9-supply = <&pmd9650_l4>; - qcom,vreg-0.9-voltage-level = <928000 928000 24000>; + qcom,vreg-0p9-voltage-level = <928000 928000 24000>; interconnect-names = "icc_path"; interconnects = <&system_noc MASTER_PCIE &bimc SLAVE_EBI_CH0>; From 7d8ed3e95e374bacefa7ae5b5a8c226ce8f12b2d Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Mon, 22 Mar 2021 19:03:39 +0530 Subject: [PATCH 1126/1809] ARM: dts: msm: Add LA specific TVM flag in respective SPI node Add LA specific TVM usecase flag under respective SPI node. This flag helps to bypass pinctrl resources from driver when not called by client with put_sync(). Note that client always controls the runtime PM of TVM usecase. Change-Id: I30b7944d93c307f7e6b1820b83a8c7da65eba4be --- qcom/yupik-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index 9b80a8e36999..446d7a5f6d7a 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -667,6 +667,7 @@ dma-names = "tx", "rx"; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; + qcom,la-vm; status = "disabled"; }; From 15ae541dba35f0dd765171fb80682a13216c1586 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 22 Mar 2021 10:57:32 -0700 Subject: [PATCH 1127/1809] ARM: dts: msm: Update USB IOVA start address on sdxlemur USB shares pair for tethered functionality related buffers and TRB ring with IPA. Although USB IOVA is using atomic property but IPA is using fastmap functionality. This results into USB mapping also becomes fastmap. Fastmap functionality uses static page table which increases overall memory requirement for page table. To reduce page table related memory update USB IOVA start address from 0x90000000 to 0x40000000 on sdxlemur. Change-Id: I7aefa20cd05414abb585cb6a7588344ef77a08ca --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index fe9dab2a9c74..7eba656d4638 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -8,7 +8,7 @@ iommus = <&apps_smmu 0x1a0 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; From 3b5ded26ddcf3846c0f865ddc13dd953eb012cd5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 17 Sep 2020 10:43:57 +0530 Subject: [PATCH 1128/1809] dt-bindings: interconnect: add interconnect bindings for direwolf Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices for direwolf. Change-Id: I33cb88c0a34f51277ddb9eec5ff26da4a487b516 --- bindings/interconnect/qcom,direwolf.txt | 31 +++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 bindings/interconnect/qcom,direwolf.txt diff --git a/bindings/interconnect/qcom,direwolf.txt b/bindings/interconnect/qcom,direwolf.txt new file mode 100644 index 000000000000..d74d3f7ff285 --- /dev/null +++ b/bindings/interconnect/qcom,direwolf.txt @@ -0,0 +1,31 @@ +Qualcomm Technologies, Inc. Direwolf Network-On-Chip interconnect driver binding +------------------------------------------------------------------------------ +Direwolf interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,direwolf-aggre1_noc"; + "qcom,direwolf-aggre2_noc"; + "qcom,direwolf-clk_virt"; + "qcom,direwolf-config_noc"; + "qcom,direwolf-dc_noc"; + "qcom,direwolf-gem_noc"; + "qcom,direwolf-lpass_ag_noc"; + "qcom,direwolf-mc_virt"; + "qcom,direwolf-mmss_noc"; + "qcom,direwolf-nspa_noc"; + "qcom,direwolf-nspb_noc"; + "qcom,direwolf-system_noc_main"; +- #interconnect-cells : should contain 1 + +Examples: + +aggre1_noc: interconnect@16c0000 { + "qcom,direwolf-aggre1_noc"; + interconnect-cells = <1>; +}; From 748300269559ec0df91773a22fef62369df8d3fd Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Mon, 22 Mar 2021 20:19:42 -0700 Subject: [PATCH 1129/1809] ARM: dts: msm: Fix IPA doorbell address for sdxlemur Update the event ring doorbell address forwarding for the IPA microcontroller on the chip. Change-Id: Ife4ccacc6f13ccf0b308e1986fb48e8e67905f7a --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..5f1dacf1365d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1114,7 +1114,7 @@ compatible = "qcom,msm-mhi-dev"; reg = <0x1c03000 0x1000>, <0x3E28000 0x4>, - <0x3E28800 0x4>; + <0x3E28848 0x4>; reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", "ipa_uc_mbox_erdb"; qcom,mhi-ep-msi = <0>; From c8500bcd6b25a3aba76bed788e4bed1d20098477 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 13 Feb 2021 14:44:11 +0530 Subject: [PATCH 1130/1809] ARM: dts: msm: Add focaltech spi touch node in yupik qrd svm Add focaltech spi trusted touch node in yupik qrd trusted vm. Change-Id: Ie7907d3054bb399238ab07008f4af64679adc453 --- qcom/yupik-vm-idp.dtsi | 17 +++++++++++++++++ qcom/yupik-vm-qrd.dtsi | 21 +++++++++++++++++++++ qcom/yupik-vm.dtsi | 11 +---------- 3 files changed, 39 insertions(+), 10 deletions(-) diff --git a/qcom/yupik-vm-idp.dtsi b/qcom/yupik-vm-idp.dtsi index 17f1e228977f..4b35423120b9 100644 --- a/qcom/yupik-vm-idp.dtsi +++ b/qcom/yupik-vm-idp.dtsi @@ -1,2 +1,19 @@ &soc { }; + +&qupv3_se13_i2c { + status = "ok"; + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "tvm"; + novatek,trusted-touch-spi-irq = <601>; + novatek,trusted-touch-io-bases = <0xf134000 0xf135000 0xf169000 0xf151000 0xa94000 0x00a10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +&qupv3_se13_spi { + status = "disabled"; +}; diff --git a/qcom/yupik-vm-qrd.dtsi b/qcom/yupik-vm-qrd.dtsi index 17f1e228977f..663740454ebd 100644 --- a/qcom/yupik-vm-qrd.dtsi +++ b/qcom/yupik-vm-qrd.dtsi @@ -1,2 +1,23 @@ &soc { }; + +&qupv3_se13_i2c { + status = "disabled"; +}; + +&qupv3_se13_spi { + status = "ok"; + focaltech@0 { + compatible = "focaltech,fts_ts"; + reg = <0x0>; + spi-max-frequency = <6000000>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,ic-type = <0x3658D488>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-spi-irq = <601>; + focaltech,trusted-touch-io-bases = <0xf134000 0xf135000 0xf136000 0xf137000 0xf169000 0xf151000 0xa94000 0x00a10000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; diff --git a/qcom/yupik-vm.dtsi b/qcom/yupik-vm.dtsi index c3e4356bd0fb..2d7ee6a5baf8 100644 --- a/qcom/yupik-vm.dtsi +++ b/qcom/yupik-vm.dtsi @@ -281,16 +281,7 @@ dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; qcom,le-vm; - status = "ok"; - novatek@62 { - compatible = "novatek,NVT-ts"; - reg = <0x62>; - novatek,trusted-touch-mode = "vm_mode"; - novatek,touch-environment = "tvm"; - novatek,trusted-touch-spi-irq = <601>; - novatek,trusted-touch-io-bases = <0xf134000 0xf135000 0xf169000 0xf151000 0xa94000 0x00a10000>; - novatek,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; - }; + status = "disabled"; }; qupv3_se13_spi: spi@a94000 { From 2c37971eeca0f90125cc7760e0270557c3113712 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 13 Feb 2021 14:48:26 +0530 Subject: [PATCH 1131/1809] ARM: dts: msm: Add trusted touch entries on yupik qrd Add focaltech trusted touch entries on yupik qrd. Change-Id: Ibfc25489dbf9d95859cf10a0ff50044c7fe48ed5 --- qcom/yupik-qrd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index a6e7bdab2c0d..6d36276bfd34 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -605,6 +605,11 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <601>; + focaltech,trusted-touch-io-bases = <0xf134000 0xf135000 0xf136000 0xf137000 0xf169000 0xf151000 0xa94000 0x00a10000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; panel = <&dsi_r66451_amoled_144hz_cmd_cphy &dsi_r66451_amoled_120hz_cmd_cphy &dsi_r66451_amoled_90hz_cmd_cphy &dsi_r66451_amoled_60hz_cmd_cphy>; }; From d641513439dcc428df6d25942ef7f23d8a10cac9 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 1 Mar 2021 13:23:04 +0530 Subject: [PATCH 1132/1809] ARM: dts: msm: Disable NPU DCVS support on SM8150 There are stability issues seen if NPU DCVS support is enabled. Disable it as temporary fix. Change-Id: I66062d14f1915e8b80ac01da9eacc47a8700abf0 --- qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 9984e6058bf7..2be716074974 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -907,6 +907,7 @@ interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&ddr_bw_opp_table>; qcom,active-only; + status = "disabled"; }; npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { @@ -918,6 +919,7 @@ qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&npu_npu_ddr_bw>; qcom,count-unit = <0x10000>; + status = "disabled"; }; cpu_pmu: cpu-pmu { From 55a720075994173b16bbc6796a153290948883a8 Mon Sep 17 00:00:00 2001 From: Arun Prakash Date: Thu, 29 Oct 2020 23:43:35 +0530 Subject: [PATCH 1133/1809] ARM: dts: msm: Add qmp aop voting support for direwolf Add qmp aop voting support for direwolf. Change-Id: I1537e5dcaad699671d914e6ba7573ecbc7262a08 --- qcom/direwolf.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 05a81d24c952..0aabc3988d91 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -545,6 +545,25 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "aop_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + reg = <0xc300000 0x400>; + reg-names = "msgram"; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; }; #include "direwolf-pinctrl.dtsi" From 719f42461db7006550934fbc69ea37f0a92c3554 Mon Sep 17 00:00:00 2001 From: Mohit Aggarwal Date: Tue, 23 Mar 2021 10:04:46 +0530 Subject: [PATCH 1134/1809] dt-bindings: rtc: rtc-pm8xxx: Add binding documentation for pm5100 rtc Add binding documentation for qcom,pm5100-rtc which is used on Qualcomm Technologies, Inc. boards. Change-Id: Id6c0924ca8a936555bc8ed73fa15e2674689f34a --- bindings/mfd/qcom-pm8xxx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/mfd/qcom-pm8xxx.txt b/bindings/mfd/qcom-pm8xxx.txt index 07f49254f366..0d9780fedfcb 100644 --- a/bindings/mfd/qcom-pm8xxx.txt +++ b/bindings/mfd/qcom-pm8xxx.txt @@ -65,6 +65,7 @@ The below bindings specify the set of valid subnodes. "qcom,pm8941-rtc" "qcom,pm8018-rtc" "qcom,pmk8350-rtc" + "qcom,pm5100-rtc" - reg: Usage: required From 04c4d7b16a64843f551409a26ad4028a98b2f2b2 Mon Sep 17 00:00:00 2001 From: Mohit Aggarwal Date: Wed, 17 Mar 2021 16:54:38 +0530 Subject: [PATCH 1135/1809] ARM: dts: msm: Add pm8xxx rtc device for monaco The patch adds pm8xxx rtc device to support rtc driver for monaco. The rtc driver supports using the PMIC RTC peripheral to wake a device up from suspend or to wake it up from power-off. Change-Id: I7fb79d68e0c61c66114569c03c73d46c847bab34 --- qcom/pm5100.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 8a163724775f..2496b5de4175 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -48,9 +48,11 @@ #interrupt-cells = <2>; }; - pm5100_rtc: qcom,pm5100_rtc { - compatible = "qcom,pm8941-rtc"; - interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>; + pm5100_rtc: rtc@6400 { + compatible = "qcom,pm5100-rtc"; + reg = <0x6400>, <0x6500>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; }; }; From 90df9e4a91b5a46b59b5779b5faa70522c0ad533 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 4 Mar 2021 11:53:48 +0530 Subject: [PATCH 1136/1809] ARM: dts: msm: Change drive strength for swr tx to 2MA for yupik Change drive strength for swr tx to 2MA for yupik to resolve swr tx rise time failure. Change-Id: I8f62feef56b2c22bba0ac7985a14abea21a46f0f --- qcom/yupik-lpi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-lpi.dtsi b/qcom/yupik-lpi.dtsi index a5714d6f05e2..596d4e5063ef 100644 --- a/qcom/yupik-lpi.dtsi +++ b/qcom/yupik-lpi.dtsi @@ -1341,7 +1341,7 @@ config { pins = "gpio0"; - drive-strength = <4>; + drive-strength = <2>; slew-rate = <1>; bias-disable; }; @@ -1369,7 +1369,7 @@ config { pins = "gpio1"; - drive-strength = <4>; + drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; @@ -1397,7 +1397,7 @@ config { pins = "gpio2"; - drive-strength = <4>; + drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; @@ -1425,7 +1425,7 @@ config { pins = "gpio14"; - drive-strength = <4>; + drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; From 05a10245371c374fe9e5a52cefe13ce79ecb4a19 Mon Sep 17 00:00:00 2001 From: Ramachandran Venkataramani Date: Mon, 22 Mar 2021 22:45:28 -0700 Subject: [PATCH 1137/1809] ARM: dts: msm: Add multiport USB support for SA8195 autogvm - Add USB multiport controller and phys. - Add GDSCs and regulators for USB multiport. - Update a few properties of USB0 and USB1. Change-Id: Ief27ccd969735bffc735748137fd1bea704d883e --- qcom/sa8195-vm-usb.dtsi | 401 +++++++++++++++++++++++++++++++++++++++- qcom/sa8195-vm.dtsi | 14 ++ 2 files changed, 405 insertions(+), 10 deletions(-) diff --git a/qcom/sa8195-vm-usb.dtsi b/qcom/sa8195-vm-usb.dtsi index 7d27d7c212d3..83dfbfacd778 100644 --- a/qcom/sa8195-vm-usb.dtsi +++ b/qcom/sa8195-vm-usb.dtsi @@ -42,7 +42,6 @@ qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; - qcom,charging-disabled; qcom,ignore-wakeup-src-in-hostmode; status = "disabled"; @@ -54,10 +53,8 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - usb-core-id = <0>; - tx-fifo-resize; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -109,6 +106,8 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; + + status = "disabled"; }; usb_nop_phy: usb_nop_phy { @@ -157,7 +156,6 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; - qcom,charging-disabled; status = "disabled"; @@ -169,10 +167,8 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - usb-core-id = <1>; - tx-fifo-resize; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -198,4 +194,389 @@ status = "disabled"; }; + + /* Tertiary USB port related controller */ + usb2: ssusb@a400000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a400000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + interrupts-extended = <&pdc 59 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_EDGE_RISING>, + <&pdc 71 IRQ_TYPE_EDGE_RISING>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq1", + "ss_phy_irq1", "dm_hs_phy_irq1"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_mp_gdsc>; + clocks = <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&dummycc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_MP_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,ignore-wakeup-src-in-hostmode; + qcom,dual-port; + + status = "disabled"; + dwc3@a400000 { + compatible = "snps,dwc3"; + reg = <0x0a400000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, + <&usb2_phy3>, <&usb_qmp_phy1>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,ssp-u3-u0-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed-plus"; + dr_mode = "host"; + }; + }; + + /* Tertiary USB port 0 related High Speed PHY */ + usb2_phy2: hsphy@88e4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + + status = "disabled"; + }; + + /* Tertiary USB port 0 related QMP PHY */ + usb_qmp_phy0: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8195_3_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8195_1_l9>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; + + /* Tertiary USB port 1 related High Speed PHY */ + usb2_phy3: hsphy@88e5000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e5000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + + status = "disabled"; + }; + + /* Tertiary USB port 1 related QMP PHY */ + usb_qmp_phy1: ssphy@88ec000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ec000 0x1000>, + <0x088ec88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8195_3_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8195_1_l9>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; }; diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 3733dcb5b112..334e1c14d6e9 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -746,6 +746,14 @@ regulator-name = "usb30_sec_gdsc"; }; + usb30_mp_gdsc: qcom,gdsc@1a6004 { + regulator-name = "usb30_mp_gdsc"; + }; + + ufs_card_2_gdsc: ufs_card_2_gdsc { + regulator-name = "ufs_card_2_gdsc"; + }; + pcie_0_gdsc: pcie_0_gdsc { regulator-name = "pcie_0_gdsc"; }; @@ -800,6 +808,12 @@ regulator-allow-set-load; }; + L9E: pm8195_3_l9: regulator-pm8195-3-l9 { + regulator-name = "ldoe9"; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + L16E: pm8195_3_l16: regulator-pm8195-3-l16 { regulator-name = "ldoe16"; regulator-min-microvolt = <2921000>; From b7bc1b20099a64209320482722f836676be2133a Mon Sep 17 00:00:00 2001 From: Wu Gao Date: Mon, 22 Mar 2021 19:31:05 +0800 Subject: [PATCH 1138/1809] ARM: dts: qcom: Move cnss_wlan_mem to sdxlemur-cnss.dtsi Move cnss_wlan_mem to sdxlemur-cnss.dtsi since sdx65 512M doesn't support wlan. Change-Id: Ic5f32ff078cc0c11b0bc438cdbc52e9d2139bc51 --- qcom/sdxlemur-cnss.dtsi | 14 ++++++++++++++ qcom/sdxlemur.dtsi | 8 -------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi index bcbdd6ec0501..5fe1c865efd8 100644 --- a/qcom/sdxlemur-cnss.dtsi +++ b/qcom/sdxlemur-cnss.dtsi @@ -1,4 +1,18 @@ +&reserved_memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; +}; + &soc { wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..167737c2ac67 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -76,14 +76,6 @@ reusable; size = <0x400000>; }; - - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x1400000>; - }; }; cpus { From d964572ef086d827415b6c18ff86a67ed4a6ac5c Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 23 Mar 2021 12:39:10 +0530 Subject: [PATCH 1139/1809] ARM: dts: msm: Add interconnect data for USB on sdxnightjar Add interconnect data for the USB DT node on sdxnightjar. Also, add bus votes for NOM and SVS. Change-Id: I4ff61bf96ee6aad590226cb01d039ccfe02ea873 --- qcom/sdxnightjar-usb.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 3113ff4e13e3..422b8fe1b824 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -31,6 +31,21 @@ reset-names = "core_reset"; qcom,core-clk-rate = <120000000>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &pc_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &system_noc SLAVE_USB3>; + + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <0 680000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <0 680000>, + <0 2400>, + <0 40000>; + qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ From e5a23c500dcb566ad632660fd1d18c6ce720018d Mon Sep 17 00:00:00 2001 From: Singa Reddy Dasari Date: Wed, 10 Mar 2021 16:58:32 +0530 Subject: [PATCH 1140/1809] ARM: dts: msm: Add sdhc_2 for SA6155P Quin virtual machine Add SDHC_2 for SA6155P Quin virtual machine. Change-Id: If6cd1eea61827aae32ff791302490511aa4071c8 --- qcom/sa6155p-vm-la.dtsi | 4 +++ qcom/sa6155p-vm.dtsi | 67 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/qcom/sa6155p-vm-la.dtsi b/qcom/sa6155p-vm-la.dtsi index 96e830bab203..02f6c060618b 100644 --- a/qcom/sa6155p-vm-la.dtsi +++ b/qcom/sa6155p-vm-la.dtsi @@ -33,3 +33,7 @@ &pcie0 { status = "ok"; }; + +&sdhc_2 { + status = "ok"; +}; diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 9b4451e48293..d8658d39a80d 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -109,6 +109,10 @@ }; }; }; + + aliases { + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + }; }; @@ -237,6 +241,69 @@ interrupt-controller; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>, <100000 100000>, + /* 50 MB/s */ + <130718 200000>, <133320 133320>, + /* 100 MB/s */ + <261438 200000>, <150000 150000>, + /* 200 MB/s */ + <261438 400000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 201500000>; + + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + broken-cd; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <44>; + }; + + qos1 { + mask = <0xc0>; + vote = <44>; + }; + }; + msm_gpu_hyp: qcom,hgsl { compatible = "qcom,hgsl"; From a54926d5e01d5836d0d2d3c6a5f2922bd3b35d8e Mon Sep 17 00:00:00 2001 From: Kuichu Ni Date: Thu, 18 Mar 2021 15:31:51 +0800 Subject: [PATCH 1141/1809] ARM: dts: qcom: Adjust configs in wlan node for SA8155 VM Some items were wrong configs in cnss-qca-converged node for Kernel 5.4, so correct them. Change-Id: Iad920ef9cf88ec1f7582b1ffca69ca6d4b42bacb --- qcom/sa8155-vm.dtsi | 58 +++++++++++++++++++++++++++------------------ 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index bec54a3fb29c..1001ab82bb39 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -178,10 +178,7 @@ #address-cells=<1>; #size-cells=<1>; - ranges = <0x10000000 0x10000000 0x10000000>, - <0x20000000 0x20000000 0x10000>, - <0xa0000000 0xa0000000 0x10000000>, - <0xb0000000 0xb0000000 0x10000>; + ranges = <0xb0000000 0xb0000000 0x10000>; vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; @@ -192,17 +189,16 @@ vdd-wlan-rfa3-supply = <&pm8150_2_l15>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; - qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; - qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; wlan-en-gpio = <&tlmm 169 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; chip_cfg@0 { - reg = <0x10000000 0x10000000>, - <0x20000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; @@ -213,21 +209,21 @@ }; chip_cfg@1 { - reg = <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; - qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; - qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; - qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; mhi_channels { #address-cells = <1>; @@ -323,17 +319,16 @@ }; chip_cfg@2 { - reg = <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; - qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>; - qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; - qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; qcom,wlan-ramdump-dynamic = <0x300000>; mhi,max-channels = <30>; @@ -839,6 +834,23 @@ status = "ok"; }; +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; + &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; From a206d2ead74694730f247721fde78db8958a81e9 Mon Sep 17 00:00:00 2001 From: Zhaoyang Liu Date: Thu, 24 Sep 2020 17:37:48 +0800 Subject: [PATCH 1142/1809] ARM: dts: msm: configure iommu for pci wlan This change is to configure iommu for wlan. Mark iommu dma attribution as bypass. Change-Id: I6aa3c8b201d481fae25e6c51658d14875feedd8a --- qcom/sa8155-vm.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index bec54a3fb29c..7ac17c043afc 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -858,3 +858,21 @@ /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; }; + +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "bypass"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; From ac65c7d162f89a6ba8ea608863bbe14bddb4d187 Mon Sep 17 00:00:00 2001 From: Zhaoyang Liu Date: Thu, 5 Nov 2020 18:59:23 +0800 Subject: [PATCH 1143/1809] ARM: dts: msm: enable smmu s1 for wlan on sa8155 vm Set iommu flag fastmap to enable SMMU S1 for wlan. Remove coherent definition for iommu pagetable. Change-Id: Ib6269e6dddec349aef49329d2889a32c756fce27 --- qcom/sa8155-vm.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 7ac17c043afc..ad26a37eb609 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -869,8 +869,7 @@ cnss_pci_iommu_group: cnss_pci_iommu_group { qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; - qcom,iommu-dma = "bypass"; - qcom,iommu-pagetable = "coherent"; + qcom,iommu-dma = "fastmap"; qcom,iommu-faults = "stall-disable", "no-CFRE", "non-fatal"; }; From 6ef4b0361ce30963d48540827364917e036d8a96 Mon Sep 17 00:00:00 2001 From: Zhaoyang Liu Date: Mon, 16 Nov 2020 16:13:01 +0800 Subject: [PATCH 1144/1809] ARM: dts: msm: update smmu ipa iova on sa8155 vm Update smmu ipa iova configuration on sa8155 vm for cnss. Change-Id: I3fe1c681670bfd13adab6544add158cdaf34753b --- qcom/sa8155-vm.dtsi | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index bec54a3fb29c..36f0c9c33974 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -178,10 +178,7 @@ #address-cells=<1>; #size-cells=<1>; - ranges = <0x10000000 0x10000000 0x10000000>, - <0x20000000 0x20000000 0x10000>, - <0xa0000000 0xa0000000 0x10000000>, - <0xb0000000 0xb0000000 0x10000>; + ranges = <0xb0000000 0xb0000000 0x10000>; vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; @@ -200,9 +197,8 @@ pinctrl-1 = <&cnss_wlan_en_sleep>; chip_cfg@0 { - reg = <0x10000000 0x10000000>, - <0x20000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; @@ -213,9 +209,8 @@ }; chip_cfg@1 { - reg = <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", @@ -323,9 +318,8 @@ }; chip_cfg@2 { - reg = <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", From 45371b2ab2df857a849009ca00eed47f8e76a856 Mon Sep 17 00:00:00 2001 From: Yu Ouyang Date: Wed, 21 Oct 2020 16:38:32 +0800 Subject: [PATCH 1145/1809] ARM: dts: msm: Correct wlan_vregs config name Correct wlan_vregs config name for Hastings and Genoa. Kernel 5.4 WLAN cnss driver function cnss_get_vreg() try to get vregs by name "*-config", not "*-info". And it has 5 elements, not 4. It is different with Kernel 4.14. Change-Id: I9d8889da7b39712bf7cd4fa799ddff000931461b --- qcom/sa8155-vm.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index bec54a3fb29c..68735700b547 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -192,8 +192,8 @@ vdd-wlan-rfa3-supply = <&pm8150_2_l15>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; - qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; - qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; wlan-en-gpio = <&tlmm 169 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; @@ -220,10 +220,10 @@ supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; - qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; - qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; - qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -330,10 +330,10 @@ supported-ids = <0x1102>; wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; - qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>; - qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; - qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; qcom,wlan-ramdump-dynamic = <0x300000>; mhi,max-channels = <30>; From 5cd82aeb9a2ed2c0c6d17326f7bd7975a21bc97f Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Wed, 3 Feb 2021 22:10:06 +0800 Subject: [PATCH 1146/1809] ARM: dts: qcom: add pinctrl for audio internal mclk2 on sa6155 platform enable GPIO122 as MCLK2 for externel AMP on sa6155 auto platform Change-Id: I140fbd24e6bec97f5749934394c9f2f9dd21e5b4 --- qcom/sa6155-audio.dtsi | 8 ++++++++ qcom/sm6150-pinctrl.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index 3f57b9d95342..a2aedec0d0ec 100644 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -459,6 +459,13 @@ &pri_aux_pcm_data0_sleep &pri_aux_pcm_data1_sleep>; }; + internal_mclk2: qcom,msm-internal-mclk2 { + compatible = "qcom,msm-pcm-routing"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&audio_internal_mclk2_active>; + pinctrl-1 = <&audio_internal_mclk2_sleep>; + }; + qcom,msm-dai-q6 { compatible = "qcom,msm-dai-q6"; @@ -491,6 +498,7 @@ qcom,msm-dai-q6 { qcom,tert-tdm-gpios = <&tdm_tert_rx>; qcom,quat-tdm-gpios = <&tdm_quat_rx>; qcom,quin-tdm-gpios = <&tdm_quin_rx>; + qcom,internal-mclk2-gpios = <&internal_mclk2>; asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, <&loopback>, <&compress>, <&hostless>, diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi index 402854a4952f..fe39f680b9f4 100644 --- a/qcom/sm6150-pinctrl.dtsi +++ b/qcom/sm6150-pinctrl.dtsi @@ -1603,6 +1603,32 @@ }; }; + audio_internal_mclk2_active: audio_internal_mclk2_active { + mux { + pins = "gpio122"; + function = "mclk2"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + + audio_internal_mclk2_sleep: audio_internal_mclk2_sleep { + mux { + pins = "gpio122"; + function = "mclk2"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; + pmx_ts_int_active { ts_int_active: ts_int_active { mux { From 512c962683ed518ad6e0b8ff0ed6c372d16b3409 Mon Sep 17 00:00:00 2001 From: Mohit Aggarwal Date: Wed, 24 Mar 2021 09:54:00 +0530 Subject: [PATCH 1147/1809] ARM: dts: msm: Correct interrupt specification for RTC PM5100 has different base addresses for RTC so need to correct the interrupt specification. Change-Id: I90433ceb35311a1417a48dad49ec7557a2fa084e --- qcom/pm5100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 2496b5de4175..a64f48feccfd 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -52,7 +52,7 @@ compatible = "qcom,pm5100-rtc"; reg = <0x6400>, <0x6500>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; }; }; }; From 24507c9e952a22fe043e8d712cbe4286ef9807a5 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 23 Mar 2021 00:20:08 +0530 Subject: [PATCH 1148/1809] ARM: dts: msm: Update skin and modem junction thermal config for YUPIK Update skin and modem junction thermal config for YUPIK as per latest recommendation. Change-Id: Ib2984cab805c3cacbfc3f4ef9fdb53711a125572 --- qcom/yupik-qrd.dtsi | 42 +++++++++- qcom/yupik-thermal.dtsi | 180 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 215 insertions(+), 7 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index a6e7bdab2c0d..eaaab1a7e37f 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -272,6 +272,24 @@ thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; trips { + quiet_apc_trip: quiet-apc-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_gpu_trip: quiet-gpu-trip { + temperature = <52000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_silver_trip: quiet-silver-trip { + temperature = <55000>; + hysteresis = <0>; + type = "passive"; + }; + quiet_cx_trip: quiet-cx-trip { temperature = <55000>; hysteresis = <5000>; @@ -280,7 +298,26 @@ }; cooling-maps { - gpu-cdev { + apc_cluster_cdev:apc-cluster-cdev { + trip = <&quiet_apc_trip>; + cooling-device = <&apc1_cluster THERMAL_NO_LIMIT 5>; + }; + + cpu_silver_cdev:cpu-silver-cdev { + trip = <&quiet_silver_trip>; + /* throttle to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-6)>; + }; + + gpu-cdev_0 { + trip = <&quiet_gpu_trip>; + /* throttle to 555000000Hz */ + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + gpu-cdev_1 { trip = <&quiet_cx_trip>; /* throttle to 315000000Hz */ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT @@ -289,8 +326,7 @@ cdsp-cdev { trip = <&quiet_cx_trip>; - cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) - (THERMAL_MAX_LIMIT-2)>; + cooling-device = <&cdsp_sw 4 4>; }; modem-pa-cdev { diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index c177df006ec2..644d307e781d 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -241,6 +241,8 @@ &thermal_zones { /delete-node/ modem-sdr-mmw-usr; /delete-node/ modem-ambient-usr; + /delete-node/ mdmss-1-step; + /delete-node/ mdmss-2-step; msm-skin-therm-usr { polling-delay-passive = <0>; @@ -1277,8 +1279,7 @@ cooling-maps { cdsp-cdev { trip = <&nspss0_trip>; - cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) - (THERMAL_MAX_LIMIT-2)>; + cooling-device = <&cdsp_sw 4 4>; }; gpu_cdev { @@ -1311,8 +1312,7 @@ cooling-maps { cdsp-cdev { trip = <&nspss1_trip>; - cooling-device = <&cdsp_sw (THERMAL_MAX_LIMIT-2) - (THERMAL_MAX_LIMIT-2)>; + cooling-device = <&cdsp_sw 4 4>; }; gpu_cdev { @@ -1329,6 +1329,178 @@ }; }; + mdmss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 7>; + trips { + mdmss0_trip0: mdmss0-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip1: mdmss0-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip2: mdmss0-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss0_cdev0 { + trip = <&mdmss0_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss0_cdev1 { + trip = <&mdmss0_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss0_cdev2 { + trip = <&mdmss0_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 8>; + trips { + mdmss1_trip0: mdmss1-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip1: mdmss1-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip2: mdmss1-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss1_cdev0 { + trip = <&mdmss1_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss1_cdev1 { + trip = <&mdmss1_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss1_cdev2 { + trip = <&mdmss1_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 9>; + trips { + mdmss2_trip0: mdmss2-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip1: mdmss2-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip2: mdmss2-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss2_cdev0 { + trip = <&mdmss2_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss2_cdev1 { + trip = <&mdmss2_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss2_cdev2 { + trip = <&mdmss2_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 10>; + trips { + mdmss3_trip0: mdmss3-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip1: mdmss3-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip2: mdmss3-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss3_cdev0 { + trip = <&mdmss3_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss3_cdev1 { + trip = <&mdmss3_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss3_cdev2 { + trip = <&mdmss3_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + mx-pe-step { polling-delay-passive = <0>; polling-delay = <0>; From de06464be9ccd68364175e265b4a9976b57ad145 Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Wed, 24 Mar 2021 11:01:38 +0530 Subject: [PATCH 1149/1809] bindings: mproc: Add support for glink-slatecom strings Update bindings for glink slatecom driver. Change-Id: Ie8b7eaa5bf37cdb489d80f2e440a31c6165a3fef --- .../soc/qcom/qcom,glink-slatecom-xprt.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 bindings/soc/qcom/qcom,glink-slatecom-xprt.txt diff --git a/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt new file mode 100644 index 000000000000..b4ae09def9b2 --- /dev/null +++ b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt @@ -0,0 +1,24 @@ +Qualcomm Technologies, Inc GLINK SLATECOM transport (glink_slatecom_xprt) binding + +This binding describes the Qualcomm Technologies, Inc glink slatecom transport +driver, a slatecom-spi based communication channel for sending data between the +various subsystems in Qualcomm Technologies, Inc platforms. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,glink-slatecom-xprt" + +- label: + Usage: required + Value type: + Definition: must be "slate" + += EXAMPLE + +The following example reprsents a glink_slatecom node. + + qcom,glink-slatecom-xprt-slate { + compatible = "qcom,glink-slatecom-xprt"; + label = "slate"; + }; From 2fde442fd6d522c65295423aed21cf039ecbdff3 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Wed, 24 Mar 2021 13:34:05 +0530 Subject: [PATCH 1150/1809] ARM: dts: msm: Add capacity and DPC properties for Blair The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I0fc08f354514e9c1dbaadd0fdb6ba8806eff39e7 --- qcom/blair.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 96d87849cfe1..e777a23f447e 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -64,6 +64,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -83,6 +85,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_1>; L2_1: l2-cache { @@ -97,6 +101,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_2>; L2_2: l2-cache { @@ -111,6 +117,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_3>; L2_3: l2-cache { @@ -125,6 +133,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_4>; L2_4: l2-cache { @@ -139,6 +149,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_5>; L2_5: l2-cache { @@ -153,6 +165,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_6>; L2_6: l2-cache { @@ -167,6 +181,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_7>; L2_7: l2-cache { From f122cbb9a24bb52ae18ead90842e53c516261710 Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Wed, 3 Mar 2021 15:21:13 +0530 Subject: [PATCH 1151/1809] ARM: dts: qcom: add audio device tree source files Add audio device tree source files for bengal. Add audio device tree header file inclusion in base dtsi. Add audio_gpr node. dt-bindings: sound: Add Documentation for rouleur. Change-Id: I9169112bd19476a8e82418552bb240b2f8210815 --- bindings/sound/wcd_codec.txt | 124 +++ qcom/pm2250.dtsi | 4 + qcom/scuba-audio-overlay.dtsi | 309 ++++++ qcom/scuba-audio.dtsi | 178 +++ qcom/scuba-iot-idp.dtsi | 1 + qcom/scuba-iot.dtsi | 34 + qcom/scuba-lpi.dtsi | 1963 +++++++++++++++++++++++++++++++++ 7 files changed, 2613 insertions(+) create mode 100644 qcom/scuba-audio-overlay.dtsi create mode 100644 qcom/scuba-audio.dtsi create mode 100644 qcom/scuba-lpi.dtsi diff --git a/bindings/sound/wcd_codec.txt b/bindings/sound/wcd_codec.txt index 6aee6910b8ac..b23079a85418 100644 --- a/bindings/sound/wcd_codec.txt +++ b/bindings/sound/wcd_codec.txt @@ -68,6 +68,11 @@ Optional properties: This property is required if qcom,va-clk-mux-select is provided - qcom,disable-afe-wakeup-event-listener : If enabled wakeup event listener will not be called from VA macro. + - compatible = "qcom,swr-mstr"; + - Child of VA macro represent VA SWR master. + - qcom,swrm-hctl-reg: HW_CTL and CLK_ENABLE bits of SWR module. + Need Disable HW_CTL bit(to gate HW control) + for particular Soundwire master version as SW workaround. Example: @@ -84,6 +89,13 @@ Example: qcom,va-dmic-sample-rate = <4800000>; qcom,va-clk-mux-select = <1>; qcom,va-island-mode-muxsel = <0x033A0000>; + swr0: va_swr_master { + compatible = "qcom,swr-mstr"; + qcom,swrm-hctl-reg = <0x0a7ec100>; + rouleur_tx_slave: rouleur-tx-slave { + compatible = "qcom,rouleur-slave"; + }; + }; }; }; @@ -120,6 +132,9 @@ Example: wcd938x_rx_slave: wcd938x-rx-slave { compatible = "qcom,wcd938x-slave"; }; + rouleur_rx_slave: rouleur-rx-slave { + compatible = "qcom,rouleur-slave"; + }; }; }; }; @@ -478,3 +493,112 @@ swr_dmic_01: dmic_swr@58350220 { qcom,swr-dmic-supply = "MIC BIAS1 Standalone"; qcom,wcd-handle = <&wcd938x_codec>; }; + +PM2250 SPMI node + +pm2250_spmi: Child node of SPMI bus required for rouleur codec + in order to access SPMI register to reset the peripheral. + +Required properties: + -compatible: "qcom,pm2250-spmi"; + +&spmi_bus { + pm2250_cdc: qcom,pm2250-cdc { + compatible = "qcom,pm2250-spmi"; + }; +}; + + +Rouleur Codec + +Required properties: + - compatible: "qcom,rouleur-codec"; + - qcom,split-codec: Property to check on split codec support. + - qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also + corresponding master port type it need to attach. + format: + same port_id configurations have to be grouped, and in ascending order. + - qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also + corresponding master port type it need to attach. + format: + same port_id configurations have to be grouped, and in ascending order. + - qcom,pmic-spmi-node: Phandle reference to the PMIC SPMI DT node. + - qcom,wcd-reset-reg: Reset register address in PMIC for rouleur codec. + - qcom,rx-slave: phandle reference of Soundwire Rx slave device. + - qcom,tx-slave: phandle reference of Soundwire Tx slave device. + +Optional properties: + + - cdc-pa-vpos-supply: phandle of pa vpos supply's regulator device tree node. + - qcom,cdc-pa-vpos-voltage: pa vpos supply's voltage level min and max in mV. + - qcom,cdc-pa-vpos-current: pa vpos supply's max current in mA. + + - cdc-vdd-io-supply: phandle of io supply's regulator device tree node. + - qcom,cdc-vdd-io-voltage: io supply's voltage level min and max in mV. + - qcom,cdc-vdd-io-current: io supply's max current in mA. + + - cdc-vdd-cp-supply: phandle of vdd cp supply's regulator device tree node. + - qcom,cdc-vdd-cp-voltage: vdd cp supply's voltage level min and max in mV. + - qcom,cdc-vdd-cp-current: vdd cp supply's max current in mA. + + - cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node. + - qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV. + - qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA. + - qcom,cdc-vdd-mic-bias-lpm-supported: mic bias supply's LPM mode. + + - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec + hardware probe. Supplies in this list will be + stay enabled. + + - qcom,cdc-on-demand-supplies: List of supplies which can be enabled + dynamically. + Supplies in this list are off by default. + +Example: + + rouleur_codec: rouleur-codec { + compatible = "qcom,rouleur-codec"; + qcom,split-codec = <1>; + qcom,pmic-spmi-node = <&pm2250_cdc>; + qcom,wcd-reset-reg = <0x0000F3DB>; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, + <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, + <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, + <4 DSD_R 0x2 0 DSD_R>; + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, + <0 ADC2 0x2 0 ADC2>, <0 DMIC0 0x4 0 ADC3>, + <0 MBHC 0x8 0 ADC4>, <1 DMIC0 0x1 0 DMIC0>, + <1 DMIC1 0x2 0 DMIC1>, <1 ADC1 0x4 0 DMIC2>, + <1 MBHC 0x8 0 DMIC3>; + + qcom,rx-slave = <&rouleur_rx_slave>; + qcom,tx-slave = <&rouleur_tx_slave>; + + cdc-vdd-io-supply = <&L15A>; + qcom,cdc-vdd-io-voltage = <1800000 1800000>; + qcom,cdc-vdd-io-current = <10000>; + + cdc-vdd-cp-supply = <&S4A>; + qcom,cdc-vdd-cp-voltage = <2040000 2040000>; + qcom,cdc-vdd-cp-current = <300000>; + + cdc-pa-vpos-supply = <&S4A>; + qcom,cdc-pa-vpos-voltage = <2040000 2040000>; + qcom,cdc-pa-vpos-current = <2400000>; + + cdc-vdd-mic-bias-supply = <&L22A>; + qcom,cdc-vdd-mic-bias-voltage = <3304000 3304000>; + qcom,cdc-vdd-mic-bias-current = <50000>; + qcom,cdc-vdd-mic-bias-lpm-supported = <1>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-cp", + "cdc-vdd-io", + "cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-pa-vpos"; + }; +}; diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index 7865afd38967..31f95b7f09e6 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -170,6 +170,10 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; + pm2250_cdc: qcom,pm2250-cdc { + compatible = "qcom,pm2250-spmi"; + }; + pm2250_qg: qpnp,qg { compatible = "qcom,qpnp-qg-lite"; #address-cells = <1>; diff --git a/qcom/scuba-audio-overlay.dtsi b/qcom/scuba-audio-overlay.dtsi new file mode 100644 index 000000000000..b75371c5ab9c --- /dev/null +++ b/qcom/scuba-audio-overlay.dtsi @@ -0,0 +1,309 @@ +#include +#include +#include +#include + +&bolero { + qcom,num-macros = <3>; + qcom,bolero-version = <5>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,va_mclk_mode_muxsel = <0x0a7a0000>; + clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", + "va_core_clk", "va_npl_clk"; + clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, + <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, + <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; + }; + + tx_macro: tx-macro@0a620000 { + compatible = "qcom,tx-macro"; + reg = <0x0a620000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-dmic-sample-rate = <2400000>; + qcom,is-used-swr-gpio = <0>; + }; + + rx_macro: rx-macro@0a600000 { + compatible = "qcom,rx-macro"; + reg = <0x0a600000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; + qcom,default-clk-id = ; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <2>; + qcom,swrm-hctl-reg = <0x0a6a9098>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a610000 0x0>; + interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <5>; + qcom,disable-div2-clk-switch = <1>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + rouleur_rx_slave: rouleur-rx-slave { + compatible = "qcom,rouleur-slave"; + reg = <0x0C 0x01170224>; + }; + }; + }; + + va_macro: va-macro@0a730000 { + compatible = "qcom,va-macro"; + reg = <0x0a730000 0x0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,va-dmic-sample-rate = <600000>; + qcom,va-clk-mux-select = <1>; + qcom,va-island-mode-muxsel = <0x0a7a0000>; + qcom,default-clk-id = ; + qcom,is-used-swr-gpio = <1>; + qcom,va-swr-gpios = <&va_swr_gpios>; + swr0: va_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <3>; + qcom,swrm-hctl-reg = <0x0a7ec100>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a740000 0x0>; + interrupts = + <0 296 IRQ_TYPE_LEVEL_HIGH>, + <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + qcom,swr-wakeup-required = <1>; + qcom,swr-num-ports = <3>; + qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>, + <1 ADC3 0x4>, <1 ADC4 0x8>, + <2 DMIC0 0x1>, <2 DMIC1 0x2>, + <2 DMIC2 0x4>, <2 DMIC3 0x8>, + <3 DMIC4 0x1>, <3 DMIC5 0x2>, + <3 DMIC6 0x4>, <3 DMIC7 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-mstr-irq-wakeup-capable = <1>; + rouleur_tx_slave: rouleur-tx-slave { + compatible = "qcom,rouleur-slave"; + reg = <0x0C 0x01170223>; + }; + }; + }; + + rouleur_codec: rouleur-codec { + compatible = "qcom,rouleur-codec"; + qcom,split-codec = <1>; + qcom,pmic-spmi-node = <&pm2250_cdc>; + qcom,wcd-reset-reg = <0x0000F3DB>; + qcom,foundry-id-reg = <0x0000704D>; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, + <1 COMP_L 0x1 0 COMP_L>, <1 COMP_R 0x2 0 COMP_R>; + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, + <0 ADC2 0x2 0 ADC2>, <0 DMIC0 0x4 0 ADC3>, + <0 MBHC 0x8 0 ADC4>, <1 DMIC0 0x1 0 DMIC0>, + <1 DMIC1 0x2 0 DMIC1>, <1 ADC1 0x4 0 DMIC2>, + <1 MBHC 0x8 0 DMIC3>; + + qcom,rx-slave = <&rouleur_rx_slave>; + qcom,tx-slave = <&rouleur_tx_slave>; + + cdc-vdd-io-supply = <&L15A>; + qcom,cdc-vdd-io-voltage = <1800000 1800000>; + qcom,cdc-vdd-io-current = <10000>; + + cdc-vdd-cp-supply = <&S4A>; + qcom,cdc-vdd-cp-voltage = <2040000 2040000>; + qcom,cdc-vdd-cp-current = <300000>; + + cdc-pa-vpos-supply = <&S4A>; + qcom,cdc-pa-vpos-voltage = <2040000 2040000>; + qcom,cdc-pa-vpos-current = <2400000>; + + cdc-vdd-mic-bias-supply = <&L22A>; + qcom,cdc-vdd-mic-bias-voltage = <3000000 3304000>; + qcom,cdc-vdd-mic-bias-current = <50000>; + qcom,cdc-vdd-mic-bias-lpm-supported = <1>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-cp", + "cdc-vdd-io", + "cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-pa-vpos"; + }; +}; + +&scuba_snd { + qcom,model = "bengal-scubaidp-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,va-bolero-codec = <1>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1","MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS3", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS1", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS1", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "SpkrMono WSA_IN", "LO", + "TX SWR_INPUT", "VA_TX_SWR_CLK", + "TX SWR_INPUT", "ADC1_OUTPUT", + "TX SWR_INPUT", "ADC2_OUTPUT", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "TX_AIF1 CAP", "VA_TX_SWR_CLK", + "TX_AIF2 CAP", "VA_TX_SWR_CLK", + "TX_AIF3 CAP", "VA_TX_SWR_CLK", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "VA SWR_INPUT", "ADC1_OUTPUT", + "VA SWR_INPUT", "ADC2_OUTPUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; + asoc-codec = <&stub_codec>, <&bolero>, + <&rouleur_codec>, <&wsa881x_i2c_e>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "rouleur_codec", "wsa-codec0"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_i2c_e>; + qcom,wsa-aux-dev-prefix = "SpkrMono"; + qcom,codec-max-aux-devs = <0>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; +}; + +&qupv3_se1_i2c { + wsa881x_i2c_e: wsa881x-i2c-codec@e { + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x0e>; + clock-names = "wsa_mclk"; + clocks = <&wsa881x_analog_clk 0>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; + qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; + qcom,wsa-prefix = "SpkrMono"; + }; + + wsa881x_i2c_44: wsa881x-i2c-codec@44 { + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x044>; + }; +}; + +&soc { + wsa881x_analog_reset_gpio: msm_cdc_pinctrl@106 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa881x_analog_clk: wsa_ana_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,codec-lpass-clk-id = <0x301>; + #clock-cells = <1>; + }; + + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + clock_audio_va_1: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x307>; + #clock-cells = <1>; + }; + + clock_audio_va_2: va_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x308>; + #clock-cells = <1>; + }; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/qcom/scuba-audio.dtsi b/qcom/scuba-audio.dtsi new file mode 100644 index 000000000000..56907c9efea1 --- /dev/null +++ b/qcom/scuba-audio.dtsi @@ -0,0 +1,178 @@ +#include +#include "msm-audio-lpass.dtsi" + +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; + + audio_pkt_core_platform: qcom,audio-pkt-core-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; +}; + +#include "scuba-lpi.dtsi" + +&spf_core_platform { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active + &rx_swr_data1_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep + &rx_swr_data1_sleep>; + qcom,lpi-gpios; + }; + + va_swr_gpios: va_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + qcom,lpi-gpios; + qcom,chip-wakeup-reg = <0x003ca064>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; + }; + + wsa881x_analog_clk_gpio: msm_cdc_pinctrl@18 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_mclk_active>; + pinctrl-1 = <&wsa_mclk_sleep>; + qcom,lpi-gpios; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@0a730000 { + swr0: va_swr_master { + }; + }; + + rx_macro: rx-macro@0a600000 { + swr1: rx_swr_master { + }; + }; + }; + + scuba_snd: sound { + compatible = "qcom,bengal-asoc-snd"; + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; + +&msm_audio_ion { + iommus = <&apps_smmu 0x01c1 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&qupv3_se1_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + }; +}; diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi index 91456469df2f..89efbf73fef7 100644 --- a/qcom/scuba-iot-idp.dtsi +++ b/qcom/scuba-iot-idp.dtsi @@ -1,6 +1,7 @@ #include #include #include "scuba-ion.dtsi" +#include "scuba-audio-overlay.dtsi" &soc { scuba_batterydata: qcom,battery-data { diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index dc7dcf378c6e..4e20bf61373f 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1,3 +1,4 @@ +#include #include #include #include @@ -22,6 +23,11 @@ granule = <512>; }; + aliases { + swr0 = &swr0; + swr1 = &swr1; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -484,6 +490,11 @@ reg = <0x6018 0x4>; }; + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; + }; wdog: qcom,wdt@f017000 { @@ -865,6 +876,28 @@ dcc: dcc_v2@1be2000 { 0x4400 2>; }; + audio_gpr: qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,intents = <0x200 20>; + reg = ; + spf_core { + compatible = "qcom,spf_core"; + reg = ; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = ; + }; + + audio_prm: q6prm { + compatible = "qcom,audio_prm"; + reg = ; + }; + }; + qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>; @@ -979,6 +1012,7 @@ dcc: dcc_v2@1be2000 { #include "scuba-iot-pinctrl.dtsi" #include "scuba-ion.dtsi" #include "msm-arm-smmu-scuba.dtsi" +#include "scuba-audio.dtsi" &qupv3_se1_i2c { #address-cells = <1>; diff --git a/qcom/scuba-lpi.dtsi b/qcom/scuba-lpi.dtsi new file mode 100644 index 000000000000..009ba3b613d2 --- /dev/null +++ b/qcom/scuba-lpi.dtsi @@ -0,0 +1,1963 @@ +&spf_core_platform { + lpass_audio_hw_vote: vote_lpass_audio_hw { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; + + lpi_tlmm: lpi_pinctrl@0a7c0000 { + compatible = "qcom,lpi-pinctrl"; + reg = <0x0a7c0000 0x0>; + qcom,slew-reg = <0x0a95a000 0x0>; + qcom,gpios-count = <19>; + gpio-controller; + #gpio-cells = <2>; + qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>, + <0x00002000>, <0x00003000>, + <0x00004000>, <0x00005000>, + <0x00006000>, <0x00007000>, + <0x00008000>, <0x00009000>, + <0x0000A000>, <0x0000B000>, + <0x0000C000>, <0x0000D000>, + <0x0000E000>, <0x0000F000>, + <0x00010000>, <0x00011000>, + <0x00012000>; + qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, + <0x00000004>, <0x00000008>, + <0x0000000A>, <0x0000000C>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000014>; + + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + + quat_mi2s_sck { + quat_mi2s_sck_sleep: quat_mi2s_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sck_active: quat_mi2s_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_ws { + quat_mi2s_ws_sleep: quat_mi2s_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_ws_active: quat_mi2s_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sck { + lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sck_active: lpi_i2s1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_ws { + lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_ws_active: lpi_i2s1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd0 { + lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd0_active: lpi_i2s1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd1 { + lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd1_active: lpi_i2s1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sck { + lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sck_active: lpi_i2s2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_ws { + lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_ws_active: lpi_i2s2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sd0 { + lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sd0_active: lpi_i2s2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s2_sd1 { + lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s2_sd1_active: lpi_i2s2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s3_sck { + lpi_i2s3_sck_sleep: lpi_i2s3_sck_sleep { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s3_sck_active: lpi_i2s3_sck_active { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s3_ws { + lpi_i2s3_ws_sleep: lpi_i2s3_ws_sleep { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s3_ws_active: lpi_i2s3_ws_active { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s3_sd0 { + lpi_i2s3_sd0_sleep: lpi_i2s3_sd0_sleep { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s3_sd0_active: lpi_i2s3_sd0_active { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s3_sd1 { + lpi_i2s3_sd1_sleep: lpi_i2s3_sd1_sleep { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s3_sd1_active: lpi_i2s3_sd1_active { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sck { + quat_tdm_sck_sleep: quat_tdm_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sck_active: quat_tdm_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_ws { + quat_tdm_ws_sleep: quat_tdm_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_ws_active: quat_tdm_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd0 { + quat_tdm_sd0_sleep: quat_tdm_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd0_active: quat_tdm_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd1 { + quat_tdm_sd1_sleep: quat_tdm_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd1_active: quat_tdm_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd2 { + quat_tdm_sd2_sleep: quat_tdm_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd2_active: quat_tdm_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_sd3 { + quat_tdm_sd3_sleep: quat_tdm_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_sd3_active: quat_tdm_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sck { + lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sck_active: lpi_tdm1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_ws { + lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_ws_active: lpi_tdm1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sd0 { + lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sd0_active: lpi_tdm1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm1_sd1 { + lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm1_sd1_active: lpi_tdm1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sck { + lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sck_active: lpi_tdm2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_ws { + lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_ws_active: lpi_tdm2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sd0 { + lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sd0_active: lpi_tdm2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm2_sd1 { + lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm2_sd1_active: lpi_tdm2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm3_sck { + lpi_tdm3_sck_sleep: lpi_tdm3_sck_sleep { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm3_sck_active: lpi_tdm3_sck_active { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm3_ws { + lpi_tdm3_ws_sleep: lpi_tdm3_ws_sleep { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm3_ws_active: lpi_tdm3_ws_active { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm3_sd0 { + lpi_tdm3_sd0_sleep: lpi_tdm3_sd0_sleep { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm3_sd0_active: lpi_tdm3_sd0_active { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_tdm3_sd1 { + lpi_tdm3_sd1_sleep: lpi_tdm3_sd1_sleep { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_tdm3_sd1_active: lpi_tdm3_sd1_active { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sck { + quat_aux_sck_sleep: quat_aux_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sck_active: quat_aux_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_ws { + quat_aux_ws_sleep: quat_aux_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_ws_active: quat_aux_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd0 { + quat_aux_sd0_sleep: quat_aux_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd0_active: quat_aux_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd1 { + quat_aux_sd1_sleep: quat_aux_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd1_active: quat_aux_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd2 { + quat_aux_sd2_sleep: quat_aux_sd2_sleep { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd2_active: quat_aux_sd2_active { + mux { + pins = "gpio4"; + function = "func2"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_sd3 { + quat_aux_sd3_sleep: quat_aux_sd3_sleep { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_sd3_active: quat_aux_sd3_active { + mux { + pins = "gpio5"; + function = "func3"; + }; + + config { + pins = "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sck { + lpi_aux1_sck_sleep: lpi_aux1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sck_active: lpi_aux1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_ws { + lpi_aux1_ws_sleep: lpi_aux1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_ws_active: lpi_aux1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sd0 { + lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sd0_active: lpi_aux1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux1_sd1 { + lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux1_sd1_active: lpi_aux1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sck { + lpi_aux2_sck_sleep: lpi_aux2_sck_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sck_active: lpi_aux2_sck_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_ws { + lpi_aux2_ws_sleep: lpi_aux2_ws_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_ws_active: lpi_aux2_ws_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sd0 { + lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sd0_active: lpi_aux2_sd0_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux2_sd1 { + lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux2_sd1_active: lpi_aux2_sd1_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux3_sck { + lpi_aux3_sck_sleep: lpi_aux3_sck_sleep { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux3_sck_active: lpi_aux3_sck_active { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux3_ws { + lpi_aux3_ws_sleep: lpi_aux3_ws_sleep { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux3_ws_active: lpi_aux3_ws_active { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux3_sd0 { + lpi_aux3_sd0_sleep: lpi_aux3_sd0_sleep { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux3_sd0_active: lpi_aux3_sd0_active { + mux { + pins = "gpio16"; + function = "func1"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_aux3_sd1 { + lpi_aux3_sd1_sleep: lpi_aux3_sd1_sleep { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_aux3_sd1_active: lpi_aux3_sd1_active { + mux { + pins = "gpio17"; + function = "func1"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tx_swr_clk_sleep: tx_swr_clk_sleep { + mux { + pins = "gpio0"; + function = "func1"; + input-enable; + bias-pull-down; + }; + + config { + pins = "gpio0"; + drive-strength = <10>; + }; + }; + + tx_swr_clk_active: tx_swr_clk_active { + mux { + pins = "gpio0"; + function = "func1"; + }; + + config { + pins = "gpio0"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + }; + + tx_swr_data1_sleep: tx_swr_data1_sleep { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <10>; + input-enable; + bias-bus-hold; + }; + }; + + tx_swr_data1_active: tx_swr_data1_active { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + tx_swr_data2_sleep: tx_swr_data2_sleep { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + tx_swr_data2_active: tx_swr_data2_active { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + rx_swr_clk_sleep: rx_swr_clk_sleep { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_clk_active: rx_swr_clk_active { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + }; + + rx_swr_data_sleep: rx_swr_data_sleep { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_data_active: rx_swr_data_active { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + rx_swr_data1_sleep: rx_swr_data1_sleep { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_data1_active: rx_swr_data1_active { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic23_clk_active: dmic23_clk_active { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic23_clk_sleep: dmic23_clk_sleep { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic23_data_active: dmic23_data_active { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic23_data_sleep: dmic23_data_sleep { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + wsa_mclk_sleep: wsa_mclk_sleep { + mux { + pins = "gpio18"; + function = "func1"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + wsa_mclk_active: wsa_mclk_active { + mux { + pins = "gpio18"; + function = "func1"; + }; + + config { + pins = "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + +}; From c7b1fc7cee460e1df65dd88fcd94c0ddc78d346c Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 24 Mar 2021 14:43:20 +0530 Subject: [PATCH 1152/1809] ARM: dts: msm: Avoid xbl_aop_mem overlay with aop_cmd_db Carveout for xbl_aop_mem overlaps with aop_cmd_db memory. Fix this overlap in SM6150. Change-Id: Id3ae858068768b7f0a309d9ccb8d6d73ff69acb3 --- qcom/sm6150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 3ab4dd3f72a2..1c929aae27fa 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -297,7 +297,7 @@ xbl_aop_mem: xbl_aop_mem@85e00000 { no-map; - reg = <0x0 0x85e00000 0x0 0x140000>; + reg = <0x0 0x85e00000 0x0 0x120000>; }; aop_cmd_db: memory@85f20000 { From b3e71e34af973e902da57587c434ea6b5125cd89 Mon Sep 17 00:00:00 2001 From: Amit Blay Date: Sun, 7 Mar 2021 16:54:11 +0200 Subject: [PATCH 1153/1809] ARM: dts: msm: Enable rename_blk device for LXC guest For LXC guest VM, rename the vda virtual device to system. This is needed for supporting standard kernel command line generated in AVB2.0 vbmeta, which refers to the rootfs as /dev/system. Change-Id: I354e9f3a2173ecea40fb54920f2a255553a40b46 --- qcom/sa8195-vm-lv-lxc.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 75228e2e38af..350ee45b4cb1 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -13,6 +13,14 @@ }; }; +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda"; + rename-dev = "system"; + }; +}; + &usb0 { status = "ok"; }; From e8983a1f81c912ffd759e2856379c0d143094124 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Wed, 17 Mar 2021 14:08:49 +0530 Subject: [PATCH 1154/1809] ARM: dts: msm: Enable uefi_log memory for SA8155 Enable uefi_log reserved memory node to read uefi log buffer. Change-Id: Ie27f11e59c08ed7d21e89c106b018838aeb7ddc2 --- qcom/sa8155.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 7b26ce200df2..62b94a170b07 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -206,6 +206,13 @@ qcom,adsp-remoteheap-vmid = <3 5 6>; }; +&reserved_memory { + uefi_log: uefi_log@0x9241C000 { + reg = <0x0 0x9241C000 0x0 0x10000>; + label = "uefi_log"; + }; +}; + #include "camera/sa8155-camera.dtsi" #include "camera/sa8155-camera-sensor.dtsi" #include "sa8155-audio.dtsi" From 01123904f8b2d86870026b0694eee366f5ed8d7c Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Wed, 24 Mar 2021 22:35:13 +0800 Subject: [PATCH 1155/1809] ARM: dts: msm: Reduce reserved size of modem for sdxnightjar Change the reserved size of modem from 115MB to 110MB, remove "MPSS DIAG BUFFER" region of 5MB. Change-Id: I69da7094e3a0c3dbbbdc0764e184449f48b50999 --- qcom/sdxnightjar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 8f6eb9931d11..13e2ff8235c4 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -49,7 +49,7 @@ mss_mem: mss_region@0x88000000 { no-map; - reg = <0x88000000 0x7300000>; + reg = <0x88000000 0x6e00000>; label = "mss_mem"; }; From 556030b7fa7a53b814f87551a05a1e804447fdac Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Mon, 15 Mar 2021 11:43:43 +0530 Subject: [PATCH 1156/1809] ARM: dts: msm: Add spmi device tree node for sa6155p Add spmi pmic and its dependent device tree node to support SA6155P for automotive platforms. Change-Id: Ic2c63ea8b25fbbe058adbffdb2661bf1396cbcbd --- qcom/pm6155-vm.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 qcom/pm6155-vm.dtsi diff --git a/qcom/pm6155-vm.dtsi b/qcom/pm6155-vm.dtsi new file mode 100644 index 000000000000..5b400ee4bc5b --- /dev/null +++ b/qcom/pm6155-vm.dtsi @@ -0,0 +1,21 @@ +#include +#include +#include + +&spmi_bus { + qcom,pm6155@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm6155_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From edfcbf5d77fda7587fbe3be6a87c643addb6f99c Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Thu, 18 Mar 2021 16:01:57 -0700 Subject: [PATCH 1157/1809] ARM: dts: msm: reduce the fastmap memory Set the geometry to reduce the fastmap memory on IPA AP cb. Change-Id: I45ae12513a69715545313047f3a41dcf16953517 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..c1e320e67ac3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1224,6 +1224,7 @@ qcom,additional-mapping = /* modem tables in IMEM */ <0x14688000 0x14688000 0x3000>; + qcom,iommu-geometry = <0x0 0xA0000000>; qcom,iommu-dma = "fastmap"; qcom,ipa-q6-smem-size = <36864>; }; From a70d9dc703795bec9fde3d5f0d683853b93eeca4 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 9 Oct 2020 10:18:49 +0530 Subject: [PATCH 1158/1809] bindings: clock: Add support for direwolf clock controllers Update the gcc, debugcc, rpmhcc bindings for direwolf device. Change-Id: I74769ebf8835816c427d661600f642e8c8ea6a80 --- bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,rpmh-clk.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 8e9b51d2ba60..844cb4c02cdc 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -14,6 +14,7 @@ Required properties : "qcom,scshrike-debugcc" "qcom,sm6150-debugcc" "qcom,monaco-debugcc" + "qcom,direwolf-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 89ee69d7d28d..a3097a70d4b0 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -38,6 +38,7 @@ Required properties : "qcom,sm6150-gcc" "qcom,sa6155-gcc" "qcom,monaco-gcc" + "qcom,direwolf-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,rpmh-clk.txt b/bindings/clock/qcom,rpmh-clk.txt index 877068e9a435..0cab1fe57d02 100644 --- a/bindings/clock/qcom,rpmh-clk.txt +++ b/bindings/clock/qcom,rpmh-clk.txt @@ -15,6 +15,7 @@ Required properties : "qcom,sm6150-rpmh-clk" "qcom,sdxlemur-rpmh-clk" "qcom,yupik-rpmh-clk" + "qcom,direwolf-rpmh-clk" - #clock-cells : must contain 1 From 1615203f88622be24d4c1d938d6887938b73355f Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 5 Feb 2021 16:32:33 -0800 Subject: [PATCH 1159/1809] ARM: dts: msm: Add fixed regulators for select sdxlemur boards Add fixed regulators that are used in the sdxlemur NTN3 and CPE boards. Multiple regulator enables are tied to the same GPIO as follows: - GPIO 105 connects to both 0.7V and 1V regulator enable (AQR) - GPIO 106 connects to both 1.05V and 1.8V regulator enable (QCA Napa) - GPIO 107 connects to both 0.9 and 1V regulator enable (NTN3) For each of the regulators, the higher voltage has been selected for advertising to consumers. Change-Id: I77ce152345561d8ed6b1a668818c556db3f965af --- qcom/sdxlemur-mtp-cpe.dtsi | 30 ++++++++++++++++++++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 20 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index e23998921bb7..73f9ee8e190b 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -2,7 +2,37 @@ #include "sdxlemur-mtp-audio-overlay.dtsi" &soc { + ntn3_vreg: ntn3_vreg { + compatible = "regulator-fixed"; + regulator-name = "ntn3_vreg"; + gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <4300>; + }; + qca_vreg: qca_vreg { + compatible = "regulator-fixed"; + regulator-name = "qca_vreg"; + gpio = <&tlmm 106 GPIO_ACTIVE_HIGH>; + vin-supply = <&ntn3_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <200000>; + }; + + aqr_vreg: aqr_vreg { + compatible = "regulator-fixed"; + regulator-name = "aqr_vreg"; + gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; + vin-supply = <&qca_vreg>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <2400>; + }; }; &pcie0 { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 0a782562d79a..0ca02fe098bb 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,6 +1,26 @@ #include "sdxlemur-mtp-mbb.dtsi" &soc { + ntn3_vreg: ntn3_vreg { + compatible = "regulator-fixed"; + regulator-name = "ntn3_vreg"; + gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <4300>; + }; + + aqr_vreg: aqr_vreg { + compatible = "regulator-fixed"; + regulator-name = "aqr_vreg"; + gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; + vin-supply = <&ntn3_vreg>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <2400>; + }; }; From 772f34de7bce985065eac304a3cedec12a26cd69 Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Thu, 25 Mar 2021 11:37:22 +0800 Subject: [PATCH 1160/1809] ARM: dts: msm: add gpio cells property for auto sa*155 platform Add gpio cells property to define the number of cells in the gpio specifier. Change-Id: I068a1cee292afd9ef04d57772a9c3c345b5d7713 --- qcom/sa6155-audio.dtsi | 4 ++++ qcom/sa8155-audio.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index a2aedec0d0ec..1da3130998b0 100644 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -186,6 +186,7 @@ &ter_i2s_data1_active>; pinctrl-1 = <&ter_i2s_sck_sleep &ter_i2s_data0_sleep &ter_i2s_data1_sleep>; + #gpio-cells = <0>; dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36896>; @@ -282,6 +283,7 @@ pinctrl-1 = <&quat_tdm_sclk_sleep &quat_tdm_ws_sleep &quat_tdm_data0_sleep &quat_tdm_data1_sleep &quat_tdm_data2_sleep &quat_tdm_data3_sleep>; + #gpio-cells = <0>; dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36912>; @@ -376,6 +378,7 @@ &quin_tdm_data0_active &quin_tdm_data1_active>; pinctrl-1 = <&quin_tdm_sclk_sleep &quin_tdm_ws_sleep &quin_tdm_data0_sleep &quin_tdm_data1_sleep>; + #gpio-cells = <0>; dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36928>; @@ -464,6 +467,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&audio_internal_mclk2_active>; pinctrl-1 = <&audio_internal_mclk2_sleep>; + #gpio-cells = <0>; }; qcom,msm-dai-q6 { diff --git a/qcom/sa8155-audio.dtsi b/qcom/sa8155-audio.dtsi index 2a4d9777df24..e93ab89508e5 100644 --- a/qcom/sa8155-audio.dtsi +++ b/qcom/sa8155-audio.dtsi @@ -105,6 +105,7 @@ &sec_tdm_dout_active>; pinctrl-1 = <&sec_tdm_sleep &sec_tdm_din_sleep &sec_tdm_dout_sleep>; + #gpio-cells = <0>; dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36880>; @@ -191,6 +192,7 @@ &tert_tdm_dout_active>; pinctrl-1 = <&tert_tdm_sleep &tert_tdm_din_sleep &tert_tdm_dout_sleep>; + #gpio-cells = <0>; dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36896>; @@ -285,6 +287,7 @@ &quat_tdm_dout_active>; pinctrl-1 = <&quat_tdm_sleep &quat_tdm_din_sleep &quat_tdm_dout_sleep>; + #gpio-cells = <0>; dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36912>; @@ -379,6 +382,7 @@ &quin_tdm_dout_active>; pinctrl-1 = <&quin_tdm_sleep &quin_tdm_din_sleep &quin_tdm_dout_sleep>; + #gpio-cells = <0>; dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36928>; From 08404332e59e560381ad295a32446e67548fee02 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 24 Mar 2021 14:51:31 +0530 Subject: [PATCH 1161/1809] ARM: dts: msm: Avoid xbl_aop_mem overlay with aop_cmd_db Carveout for xbl_aop_mem overlaps with aop_cmd_db memory. Fix this overlap in SDMSHRIKE. Change-Id: Iacb282e0c899fd5578d599505defc59e7d4fc1d3 --- qcom/sdmshrike.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 5c1b9876759a..5ea623a8b495 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -288,7 +288,7 @@ xbl_aop_mem: xbl_aop_mem@85e00000 { no-map; - reg = <0x0 0x85e00000 0x0 0x140000>; + reg = <0x0 0x85e00000 0x0 0x120000>; }; flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 { From 90cda7a69a1fcb3833fdffbb598bcb4ce9c24f8f Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 25 Mar 2021 12:01:16 +0530 Subject: [PATCH 1162/1809] ARM: dts: msm: Fix GPIO pin name Fix the error in GPIO pin name. Change-Id: Ic3589ee672fbd9f3ebc6bf5536b80e8da166052b --- qcom/sm8150-slpi-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm8150-slpi-pinctrl.dtsi b/qcom/sm8150-slpi-pinctrl.dtsi index b393c12ac079..2dfaa98271d3 100644 --- a/qcom/sm8150-slpi-pinctrl.dtsi +++ b/qcom/sm8150-slpi-pinctrl.dtsi @@ -38,7 +38,7 @@ qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { qupv3_se21_i2c_active: qupv3_se21_i2c_active { mux { - pins = "gpi2", "gpio3"; + pins = "gpio2", "gpio3"; function = "func1"; }; From dab5b5e5b27bf6f15372551feebabc1fcd097a47 Mon Sep 17 00:00:00 2001 From: Yingjie Zhu Date: Fri, 27 Nov 2020 15:01:06 +0800 Subject: [PATCH 1163/1809] ARM: dts: msm: Add Bluetooth device tree for SA6155VM Add Bluetooth device tree to support Bluetooth for SA6155VM. Change-Id: I63771d8ebfc21c0eba92ce15dd9cd5669d342baf --- qcom/sa6155p-vm-la.dtsi | 4 ++++ qcom/sa6155p-vm.dtsi | 42 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/qcom/sa6155p-vm-la.dtsi b/qcom/sa6155p-vm-la.dtsi index 02f6c060618b..83cdcfef7532 100644 --- a/qcom/sa6155p-vm-la.dtsi +++ b/qcom/sa6155p-vm-la.dtsi @@ -37,3 +37,7 @@ &sdhc_2 { status = "ok"; }; + +&qupv3_se7_4uart { + status = "ok"; +}; diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index d8658d39a80d..cdaf1d722a38 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -11,6 +11,10 @@ qcom,msm-name = "SA6155P"; qcom,msm-id = <377 0x0>; + aliases { + hsuart0 = &qupv3_se7_4uart; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -127,6 +131,24 @@ = ; }; + /* PWR_CTR1_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 1 0>; + }; + + /* PWR_CTR2_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 6 0>; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x80000>, @@ -310,6 +332,26 @@ /* 6155 have no Doorbell, only keep ifence */ db-off = <1>; }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 85 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-rfa1-supply = <&pm6155_1_s6>; + qcom,bt-vdd-rfa2-supply = <&pm6155_1_s5>; + qcom,bt-vdd-rfa3-supply = <&pm6155_1_l15>; + + /* */ + qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1904000 1904000 0 0>; + }; }; ®ulator { From 47742e574aa4ed6be53afceaa22c13551f81199e Mon Sep 17 00:00:00 2001 From: Srinivas Ganji Date: Thu, 25 Mar 2021 07:50:16 -0700 Subject: [PATCH 1164/1809] Revert "ARM: dts: qcom: Enable the second UFS instance" This reverts commit 7c4889dd688fff08af26f46f70ff0f822f8b2a12. Change-Id: Ic5139ad1615332ac6d354a65e3fbcbbbec14635f --- qcom/sa8195p-regulator.dtsi | 7 +- qcom/sa8195p.dtsi | 30 -------- qcom/sdmshrike.dtsi | 137 ------------------------------------ 3 files changed, 2 insertions(+), 172 deletions(-) diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi index 2554e103dc92..5d480a9a464b 100644 --- a/qcom/sa8195p-regulator.dtsi +++ b/qcom/sa8195p-regulator.dtsi @@ -336,12 +336,10 @@ L17A: pm8195_1_l17: regulator-pm8195-1-l17 { regulator-name = "pm8195_1_l17"; qcom,set = ; - regulator-min-microvolt = <2504000>; + regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2904000>; + qcom,init-voltage = <1700000>; qcom,init-mode = ; - regulator-system-load = <1>; - regulator-always-on; }; }; @@ -696,7 +694,6 @@ regulator-max-microvolt = <3544000>; qcom,init-voltage = <2500000>; qcom,init-mode = ; - regulator-always-on; }; }; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 9ed8062fb621..10532f45caff 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -59,36 +59,6 @@ status= "ok"; }; -&ufs2phy_mem { - compatible = "qcom,ufs-phy-qmp-v4"; - vdda-phy-supply = <&pm8195_3_l5>; - vdda-pll-supply = <&pm8195_1_l9>; - vdda-phy-max-microamp = <138000>; - vdda-pll-max-microamp = <65100>; - - status = "ok"; -}; - -&ufshc2_mem { - vdd-hba-supply = <&ufs_card_2_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm8195_1_l17>; - vcc-voltage-level = <2894000 2904000>; - vcc-low-voltage-sup; - vccq-supply = <&pm8195_2_l5>; - vccq2-supply = <&pm8195_s4>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <750000>; - vccq2-max-microamp = <750000>; - - qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vccq-parent-supply = <&pm8195_1_s2>; - qcom,vccq-parent-max-microamp = <210000>; - - status= "ok"; -}; - &usb2_phy0 { vdd-supply = <&pm8195_3_l5>; vdda18-supply = <&pm8195_1_l12>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 500293df7983..300784e45dbf 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -35,7 +35,6 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ - ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */ serial0 = &qupv3_se12_2uart; sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ spi22 = &qupv3_se22_spi; @@ -1432,8 +1431,6 @@ interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; - spm-level = <5>; - rpm-level = <1>; #reset-cells = <1>; lanes-per-direction = <2>; @@ -1539,140 +1536,6 @@ status = "disabled"; }; - ufs2phy_mem: ufsphy_mem@1d67000 { - reg = <0x1d67000 0xe00>; /* PHY regs */ - reg-names = "phy_mem"; - #phy-cells = <0>; - - lanes-per-direction = <2>; - - clock-names = "ref_clk_src", - "ref_clk", - "ref_aux_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>; - - resets = <&ufshc2_mem 0>; - status = "disabled"; - }; - - ufshc2_mem: ufshc@1d64000 { - compatible = "qcom,ufshc"; - reg = <0x1d64000 0x3000>, - <0x1d70000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; - interrupts = ; - phys = <&ufs2phy_mem>; - phy-names = "ufsphy"; - spm-level = <5>; - rpm-level = <1>; - #reset-cells = <1>; - - lanes-per-direction = <2>; - dev-ref-clk-freq = <0>; /* 19.2 MHz */ - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_CARD_2_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>, - <&gcc GCC_UFS_CARD_2_AHB_CLK>, - <&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - interconnects = - <&aggre1_noc MASTER_UFS_GEN4 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_UFS_MEM_1_CFG>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - - qcom,ufs-bus-bw,name = "ufshc_mem"; - qcom,ufs-bus-bw,num-cases = <26>; - qcom,ufs-bus-bw,num-paths = <2>; - qcom,ufs-bus-bw,vectors-KBps = - /* - * During HS G3 UFS runs at nominal voltage corner, vote - * higher bandwidth to push other buses in the data path - * to run at nominal to achieve max throughput. - * 4GBps pushes BIMC to run at nominal. - * 200MBps pushes CNOC to run at nominal. - * Vote for half of this bandwidth for HS G3 1-lane. - * For max bandwidth, vote high enough to push the buses - * to run in turbo voltage corner. - */ - <0 0>, <0 0>, /* No vote */ - <922 0>, <1000 0>, /* PWM G1 */ - <1844 0>, <1000 0>, /* PWM G2 */ - <3688 0>, <1000 0>, /* PWM G3 */ - <7376 0>, <1000 0>, /* PWM G4 */ - <1844 0>, <1000 0>, /* PWM G1 L2 */ - <3688 0>, <1000 0>, /* PWM G2 L2 */ - <7376 0>, <1000 0>, /* PWM G3 L2 */ - <14752 0>, <1000 0>, /* PWM G4 L2 */ - <127796 0>, <1000 0>, /* HS G1 RA */ - <255591 0>, <1000 0>, /* HS G2 RA */ - <2097152 0>, <102400 0>, /* HS G3 RA */ - <4194304 0>, <204800 0>, /* HS G4 RA */ - <255591 0>, <1000 0>, /* HS G1 RA L2 */ - <511181 0>, <1000 0>, /* HS G2 RA L2 */ - <4194304 0>, <204800 0>, /* HS G3 RA L2 */ - <8388608 0>, <409600 0>, /* HS G4 RA L2 */ - <149422 0>, <1000 0>, /* HS G1 RB */ - <298189 0>, <1000 0>, /* HS G2 RB */ - <2097152 0>, <102400 0>, /* HS G3 RB */ - <4194304 0>, <204800 0>, /* HS G4 RB */ - <298189 0>, <1000 0>, /* HS G1 RB L2 */ - <596378 0>, <1000 0>, /* HS G2 RB L2 */ - /* As UFS working in HS G3 RB L2 mode, aggregated - * bandwidth (AB) should take care of providing - * optimum throughput requested. However, as tested, - * in order to scale up CNOC clock, instantaneous - * bindwidth (IB) needs to be given a proper value too. - */ - <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ - <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ - <7643136 0>, <307200 0>; /* Max. bandwidth */ - - qcom,bus-vector-names = "MIN", - "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", - "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", - "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", - "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", - "MAX"; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - resets = <&gcc GCC_UFS_CARD_2_BCR>; - reset-names = "rst"; - - secondary-storage; - status = "disabled"; - }; - spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1000>, From ccdf5e08df2282b4c046340095627559e4e02a98 Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Thu, 25 Mar 2021 17:08:54 +0800 Subject: [PATCH 1165/1809] ARM: dts: msm: update QUPs for sa8195 virtual machine Add missing QUPv3 devices and update sa8915 lxc VM. Change-Id: I73fb30df25755e69f2149be0af686c503542c993 --- qcom/sa8195-qupv3.dtsi | 53 +++++++++++++++++++++++++++++ qcom/sa8195-vm-lv-lxc.dtsi | 8 +++++ qcom/sdmshrike-pinctrl.dtsi | 67 +++++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) diff --git a/qcom/sa8195-qupv3.dtsi b/qcom/sa8195-qupv3.dtsi index 6cf8da2377cf..ce4ce38db758 100644 --- a/qcom/sa8195-qupv3.dtsi +++ b/qcom/sa8195-qupv3.dtsi @@ -340,6 +340,43 @@ status = "ok"; }; + qupv3_se4_4uart: qcom,qup_uart@890000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>, + <&qupv3_se4_default_tx>; + pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + interrupts = ; + qcom,wrapper-core = <&qupv3_0>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se10_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_2uart_active>; + pinctrl-1 = <&qupv3_se10_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + /* Debug UART Instance for CDP/MTP platform */ qupv3_se12_2uart: qcom,qup_uart@0xa90000 { compatible = "qcom,msm-geni-console"; @@ -380,6 +417,22 @@ status = "disabled"; }; + qupv3_se16_2uart: qcom,qup_uart@0xa94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_2uart_active>; + pinctrl-1 = <&qupv3_se16_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + /* I2C */ qupv3_se8_i2c: i2c@a80000 { compatible = "qcom,i2c-geni"; diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 75228e2e38af..a8cc7b2e0104 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -22,6 +22,14 @@ status = "ok"; }; +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se4_4uart { + status = "ok"; +}; + &pcie0_msi { status = "ok"; }; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index 56599e3baeed..cbfbf3e9cdd0 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -5013,6 +5013,73 @@ }; }; + qupv3_se4_4uart_pins: qupv3_se4_4uart_pins { + qupv3_se4_default_ctsrtsrx: qupv3_se4_default_ctsrtsrx { + mux { + pins = "gpio51", "gpio52", "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se4_default_tx: qupv3_se4_default_tx { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_ctsrx: qupv3_se4_ctsrx { + mux { + pins = "gpio51", "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio54"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_rts: qupv3_se4_rts { + mux { + pins = "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se4_tx: qupv3_se4_tx { + mux { + pins = "gpio53"; + function = "qup4"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + /* SE 10 pin mappings */ qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { qupv3_se10_2uart_active: qupv3_se10_2uart_active { From 2575ea7332b6ae133867b5ebf648edb20e475a20 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 26 Mar 2021 12:03:12 +0530 Subject: [PATCH 1166/1809] ARM: dts: msm: Add cpuidle states and LPM stats devices for direwolf Add various cpuidle and cluster lpm states. Also add sleep stats devices for master stats, SoC sleep stats and ddr stats. Change-Id: I039ff778252c9fbd132e35f798b45cb0d9782a91 --- qcom/direwolf-pm.dtsi | 185 ++++++++++++++++++++++++++++++++++++++++++ qcom/direwolf.dtsi | 9 ++ 2 files changed, 194 insertions(+) create mode 100644 qcom/direwolf-pm.dtsi diff --git a/qcom/direwolf-pm.dtsi b/qcom/direwolf-pm.dtsi new file mode 100644 index 000000000000..73a3de7dbd79 --- /dev/null +++ b/qcom/direwolf-pm.dtsi @@ -0,0 +1,185 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L3"; + qcom,clstr-tmr-add = <1000>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l3-wfi"; + entry-latency-us = <660>; + exit-latency-us = <600>; + min-residency-us = <1260>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,is-reset; + qcom,min-child-idx = <2>; + }; + + CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "cx-off"; + entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + arm,psci-suspend-param = <0x2340>; + qcom,psci-mode = <0x234>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */ + reg = <3>; + compatible = "arm,idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3638>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + arm,psci-suspend-param = <0xc340>; + qcom,psci-mode = <0xc34>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <61>; + exit-latency-us = <60>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <55>; + exit-latency-us = <66>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; + + ddr-stats@c300000 { + compatible = "qcom,ddr-stats"; + reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + }; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 0aabc3988d91..0babcb1ce004 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -24,6 +24,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -42,6 +43,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -55,6 +57,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -68,6 +71,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -81,6 +85,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -94,6 +99,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -107,6 +113,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -120,6 +127,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -568,3 +576,4 @@ #include "direwolf-pinctrl.dtsi" #include "direwolf-regulators.dtsi" +#include "direwolf-pm.dtsi" From ddcd71f509ae7a6ed3bf5bb9283caa1bb9a8f96b Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Fri, 26 Mar 2021 14:42:21 +0530 Subject: [PATCH 1167/1809] ARM: dts: qcom: remove audio heap allocation for sdxnightjar audio will use system heap instead. Change-Id: Idf7f8d92ed5c6e1928ece5460b039eb9b2a6a5a2 --- qcom/sdx-audio-lpass-elite.dtsi | 2 -- qcom/sdxnightjar-ion.dtsi | 6 ------ qcom/sdxnightjar.dtsi | 6 ------ 3 files changed, 14 deletions(-) diff --git a/qcom/sdx-audio-lpass-elite.dtsi b/qcom/sdx-audio-lpass-elite.dtsi index 598e16ed0b5a..32841765a1e4 100644 --- a/qcom/sdx-audio-lpass-elite.dtsi +++ b/qcom/sdx-audio-lpass-elite.dtsi @@ -7,8 +7,6 @@ qcom,msm-audio-ion { compatible = "qcom,msm-audio-ion"; - qcom,scm-mp-enabled; - memory-region = <&audio_mem>; }; pcm0: qcom,msm-pcm { diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 1a35044d6b30..1f533ccd6081 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -11,12 +11,6 @@ qcom,ion-heap-type = "MSM_SYSTEM"; }; - audio_heap: qcom,ion-heap@8 { /* AUDIO HEAP */ - reg = ; - memory-region = <&audio_mem>; - qcom,ion-heap-type = "DMA"; - }; - qcom,ion-heap@27 { /* QSEECOM HEAP */ reg = ; memory-region = <&qseecom_mem>; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index b1f160c00823..11b22469a0d5 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -68,12 +68,6 @@ size = <0x400000>; }; - audio_mem: audio_region@0 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - size = <0x400000>; - }; }; aliases { }; From f549366d31cf44455f601e90dd9bc5cb78905a8a Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Fri, 26 Mar 2021 19:19:51 +0530 Subject: [PATCH 1168/1809] dt-bindings: clock: Add support for BLAIR clock controllers Update the GCC, GPUCC and DISPCC bindings for BLAIR device. Change-Id: Icd841e4182dad6f0150a809a965cb82c94ddd26c --- bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index a8849c685c66..c1ee76347304 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -17,6 +17,7 @@ Required properties : "qcom,sm6150-dispcc" "qcom,sa6155-dispcc" "qcom,monaco-dispcc" + "qcom,blair-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index a3097a70d4b0..b0919e3137e0 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -39,6 +39,7 @@ Required properties : "qcom,sa6155-gcc" "qcom,monaco-gcc" "qcom,direwolf-gcc" + "qcom,blair-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index bc6a3e2ce15a..03535db55849 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -13,6 +13,7 @@ Required properties : "qcom,sm6150-gpucc", "qcom,sa6155-gpucc". "qcom,monaco-gpucc" + "qcom,blair-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. From 8f5224b1da4354470b0408d0579599040d0b3f40 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 26 Mar 2021 11:00:34 -0700 Subject: [PATCH 1169/1809] dt-bindings: arm: msm: add support for BDF filtering Add DT entry to filter out list of BDFs for enumeration. This list is required for PCIe switches unable to respond to configuration access request to certain supported BDFs. Without filtering, such BDFs are causing system bus hang or enumeration failure of downstream ports of switch. Change-Id: Ic89ad56f290f91f1e50255a4fdaa2f7d0d78b539 --- bindings/pci/pci-msm.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 22f05045e34c..e2f744b3e9cb 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -400,6 +400,11 @@ interconnects: Definition: PCIe PHY initialization sequence +- qcom,filtered-bdfs: + Usage: optional + Value type: + Definition: Skip enumeration for the list of 32-bit BDFs. + ============== Root port node ============== @@ -557,6 +562,7 @@ Example qcom,ep-latency = <20>; qcom,num-parf-testbus-sel = <0xb9>; qcom,switch-latency = <25>; + qcom,filtered-bdfs = <0x02080000>; qcom,eq-pset-req-vec = <0>; qcom,core-preset = <0x55555555> /* short channel */ From e813986e17185d2aa181f3e6f5f1a9e877a51965 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 26 Mar 2021 18:07:50 -0700 Subject: [PATCH 1170/1809] dt-bindings: arm: msm: Add child node entry for NTN3 i2c client In order to access NTN3 switch registers add i2c client properties. By accessing these registers root complex driver can toggle NTN3 GPIOs to tied to downstream endpoint reset. i2c interface is also used to dump NTN3 registers for debugging PCIe link related issues. Change-Id: I38279185c07a2ff7a9736a585f5e84053d459462 --- bindings/pci/pci-msm.txt | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index e2f744b3e9cb..719ef66a1c15 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -585,3 +585,53 @@ Example qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */ qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>; }; + +============== +i2c child node +============== + +- compatible: + Usage: required + Value type: + Definition: Compatible list, contains + - "qcom,pcie0-i2c-ntn3" for NTN3 switch attached to Root port 0 + +- reg: + Usage: required + Value type: + Definition: i2c slave id + +- gpio-config-reg: + Usage: optional + Value type: + Definition: Slave GPIO configuration register address + +- ep-reset-reg: + Usage: optional + Value type: + Definition: Slave endpoint reset register address + +- ep-reset-gpio-mask: + Usage: optional + Value type: + Definition: Slave GPIO number as 32-bit mask + +- dump-regs: + Usage: optional + Value Type: Array of + Definition: List of slave registers to dump by i2c read + +======= +Example +======= + +&i2c_3 { + pcie_i2c_ctrl: pcie_i2c_ctrl { + compatible = "qcom,pcie0-i2c-ntn3"; + reg = <0x77>; + gpio-config-reg = <0x801208>; + ep-reset-reg = <0x801210>; + ep-reset-gpio-mask = <0xf>; + dump-regs = <0x801330 0x801350 0x801370>; + }; +}; From 7c8c87be2c898e9924069c601363204b8db1afa5 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 26 Mar 2021 18:28:23 -0700 Subject: [PATCH 1171/1809] ARM: dts: msm: Filter NTN3 downstream BDF for sdxlemur Add DT entry to filter BDF for enumeration. This is required for PCIe NTN3 switch unable to respond to configuration access request to certain supported BDF. Without filtering, such BDF is causing system bus hang. Change-Id: I97dc4411b5dfcce8f02881275fe36388268e3a13 --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 0ca02fe098bb..632a1adda7cd 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -25,6 +25,8 @@ }; &pcie0 { + qcom,filtered-bdfs = <0x02080000>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, From ca07cdcac12e22c31668912ff09b46536badbb8b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Sun, 28 Mar 2021 14:22:46 -0700 Subject: [PATCH 1172/1809] ARM: dts: msm: Have PCIe RC control NTN3 and its ETH power for sdxlemur When connecting a NTN3 switch to sdxlemur, host needs to control the power to the switch as well as to the ETHs downstream. Add DT entry in PCIe root complex node to toggle the regulators that controls power to NTN3 and its ETHs on sdxlemur. Change-Id: I747b3ba718ad9c4aaed1b7b0ac7aa79edf36fc7f --- qcom/sdxlemur-mtp-cpe.dtsi | 2 ++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 73f9ee8e190b..1114bac99640 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -36,6 +36,8 @@ }; &pcie0 { + vreg-3p3-supply = <&aqr_vreg>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 632a1adda7cd..f3477511f83c 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -27,6 +27,8 @@ &pcie0 { qcom,filtered-bdfs = <0x02080000>; + vreg-3p3-supply = <&aqr_vreg>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, From 833631d980556316c1bc55535378bddc331480e5 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Sun, 28 Mar 2021 14:38:36 -0700 Subject: [PATCH 1173/1809] ARM: dts: msm: Modify BDF to SID mapping for MBB on sdxlemur Switch downstream BDF 0x208 is not used for enumeration. This causes downstream bus number assignments to get changed. Hence update BDF to SID table to reflect the same. Also update CPE SIDs to lower case from upper case. Change-Id: I0b5428021637c5c8255fead663a1c8e45fe1815b --- qcom/sdxlemur-mtp-cpe.dtsi | 4 ++-- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 12 +++++------- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 1114bac99640..165cb7c5594c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -45,8 +45,8 @@ <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, - <0x500 &apps_smmu 0x020C 0x1>, - <0x501 &apps_smmu 0x020E 0x1>; + <0x500 &apps_smmu 0x020c 0x1>, + <0x501 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index f3477511f83c..3972cf326b4a 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -31,13 +31,11 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, - <0x208 &apps_smmu 0x0202 0x1>, - <0x210 &apps_smmu 0x0203 0x1>, - <0x218 &apps_smmu 0x0204 0x1>, - <0x300 &apps_smmu 0x0207 0x1>, - <0x400 &apps_smmu 0x0208 0x1>, - <0x500 &apps_smmu 0x020C 0x1>, - <0x501 &apps_smmu 0x020E 0x1>; + <0x210 &apps_smmu 0x0202 0x1>, + <0x218 &apps_smmu 0x0203 0x1>, + <0x300 &apps_smmu 0x0208 0x1>, + <0x400 &apps_smmu 0x020c 0x1>, + <0x401 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { From 741eda5055c77567d8ccf724253d7a942f6b1849 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 19 Mar 2021 16:29:31 +0800 Subject: [PATCH 1174/1809] ARM: dts: msm: Removed pil-scm-pas for sdxnightjar Remove pil-scm-pas as sdxnightjar has no ICC. Change-Id: I5d87011b7e88d3d8cb77f78b0d29aba3e28cf796 --- qcom/sdxnightjar.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 38817f15fe7e..800ac717709e 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -610,11 +610,6 @@ qcom,rmnet-ipa-ssr; }; - pil_scm_pas { - compatible = "qcom,pil-tz-scm-pas"; - interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>; - }; - blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; From d703024c34238221d23fe803500c408048525cb7 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 1 Mar 2021 13:25:51 +0530 Subject: [PATCH 1175/1809] ARM: dts: msm: Disable NPU DCVS support on SA8195 There are stability issues seen if NPU DCVS support is enabled. Disable it as a temporary fix. Change-Id: I85d7496270015925246fa305cf5c6591c4e1157d --- qcom/sdmshrike.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 8b0d412d2ae0..d396e94a4a00 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -849,6 +849,7 @@ interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&ddr_bw_opp_table>; qcom,active-only; + status = "disabled"; }; npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { @@ -860,6 +861,7 @@ qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&npu_npu_ddr_bw>; qcom,count-unit = <0x10000>; + status = "disabled"; }; cpu_pmu: cpu-pmu { From bf3c425ed68dbc2d4f23f6ca47183dbd50b99dd4 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Fri, 26 Mar 2021 20:49:30 +0530 Subject: [PATCH 1176/1809] ARM: dts: msm: Add support for GCC for BLAIR Enable Global clock controller for BLAIR. While at it, disable other clock nodes and Use dummy rpm clock driver for BLAIR RUMI. Change-Id: I43ac592528cb5f23d21073a4d1835da387a0814f --- qcom/blair-rumi.dtsi | 25 +++++++++++++++++++++++++ qcom/blair.dtsi | 13 +++++++++---- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 903075da46cd..3ac07c6f9a1e 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -26,6 +26,22 @@ 0x10060 0x3c 0x0 0x4>; }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; }; &tsens0 { @@ -124,3 +140,12 @@ &rpm_bus { rpm-standalone; }; + +&rpmcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; + +&gcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 96d87849cfe1..ef1a515f9297 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1,6 +1,6 @@ -#include -#include -#include +#include +#include +#include #include #include #include @@ -1176,7 +1176,7 @@ }; gcc: clock-controller@1400000 { - compatible = "qcom,holi-gcc", "syscon"; + compatible = "qcom,blair-gcc", "syscon"; reg = <0x1400000 0x1f0000>; reg_names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; @@ -1199,6 +1199,7 @@ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; #clock-cells = <1>; #reset-cells = <1>; + status = "disabled"; }; gpucc: clock-controller@5990000 { @@ -1216,6 +1217,7 @@ "gcc_gpu_snoc_dvm_gfx_clk"; #clock-cells = <1>; #reset-cells = <1>; + status = "disabled"; }; cpucc: syscon@faa0018 { @@ -1238,6 +1240,7 @@ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo_clk_src"; #clock-cells = <1>; + status = "disabled"; }; cpufreq_hw: qcom,cpufreq-hw { @@ -1256,6 +1259,7 @@ ; interrupt-names = "dcvsh0_int", "dcvsh1_int"; #freq-domain-cells = <2>; + status = "disabled"; }; qcom,cpufreq-hw-debug@0fd91000 { @@ -1263,6 +1267,7 @@ reg = <0x0fd91000 0x800>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + status = "disabled"; }; ddr_bw_opp_table: ddr-bw-opp-table { From cc9bb4cf73a8d92dc6a7b5dd1572ed0f37c8c731 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 29 Mar 2021 19:16:52 +0530 Subject: [PATCH 1177/1809] ARM: dts: qcom: Add modem TSENS thermal zone mitigations for SHIMA Add modem junction temperature thermal zone mitigation rules based on latest recommendation for SHIMA. Change-Id: I3b3ebd66e606038574706f4c8e9765e935e00350 --- qcom/shima-thermal.dtsi | 174 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 653a24778481..a5b819e44a9c 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -213,6 +213,180 @@ &thermal_zones { /delete-node/ modem-sdr-mmw-usr; /delete-node/ modem-ambient-usr; + /delete-node/ mdmss-1-step; + /delete-node/ mdmss-2-step; + + mdmss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 8>; + trips { + mdmss0_trip0: mdmss0-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip1: mdmss0-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip2: mdmss0-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss0_cdev0 { + trip = <&mdmss0_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss0_cdev1 { + trip = <&mdmss0_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss0_cdev2 { + trip = <&mdmss0_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 9>; + trips { + mdmss1_trip0: mdmss1-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip1: mdmss1-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip2: mdmss1-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss1_cdev0 { + trip = <&mdmss1_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss1_cdev1 { + trip = <&mdmss1_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss1_cdev2 { + trip = <&mdmss1_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 10>; + trips { + mdmss2_trip0: mdmss2-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip1: mdmss2-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip2: mdmss2-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss2_cdev0 { + trip = <&mdmss2_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss2_cdev1 { + trip = <&mdmss2_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss2_cdev2 { + trip = <&mdmss2_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdmss-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 11>; + trips { + mdmss3_trip0: mdmss3-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip1: mdmss3-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip2: mdmss3-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss3_cdev0 { + trip = <&mdmss3_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss3_cdev1 { + trip = <&mdmss3_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss3_cdev2 { + trip = <&mdmss3_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; msm-skin-therm-usr { polling-delay-passive = <0>; From 390b3f3f4b25b724a37654ad7b330d2b8c31467b Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 29 Mar 2021 08:58:25 -0700 Subject: [PATCH 1178/1809] ARM: dts: msm: Add bindings for llcc tcm Add memory region for llcc tightly coupled memory. Change-Id: Ic553f10e26f24fc51e3c1de1c466a4f78f3c0b9b --- bindings/arm/msm/qcom,llcc.txt | 6 ++++++ qcom/sdxlemur.dtsi | 14 ++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index bf052f36b6de..dc9c20cfec7b 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -47,6 +47,12 @@ Properties: Definition: List of clock input name strings sorted in the same order as the clocks property. Definition must have "qdss_clk" + +- memory-region: + Usage: optional + Value type: + Definition: List of memory regions which define the range of addresses used + for tightly coupled memory in the llcc. Example: cache-controller@1100000 { diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 931e72883b24..9b5aae70a9e0 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -76,6 +76,19 @@ reusable; size = <0x400000>; }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; + + llcc_tcm_mem: llcc_tcm_region { + no-map; + reg = <0x15800000 0x800000>; + }; }; cpus { @@ -704,6 +717,7 @@ cap-based-alloc-and-pwr-collapse; clocks = <&aopcc QDSS_CLK>; clock-names = "aopcc_closks"; + memory-region = <&llcc_tcm_mem>; }; smem: qcom,smem { From bfd2d337df67d4ac9ea45db15671dce63b6da862 Mon Sep 17 00:00:00 2001 From: Huicheng Liu Date: Tue, 5 Jan 2021 16:47:22 -0500 Subject: [PATCH 1179/1809] ARM: dts: msm: update quat tdm multilane config on auto VMs Update QUAT TDM multilane mask config for TX/RX - automotive VM platforms. Change-Id: I8ebc93545683ee93a6247b2a9cca70c5d43b03dd --- qcom/sa8155-vm-audio.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi index 712ec64d98d2..0db1f18be5a0 100644 --- a/qcom/sa8155-vm-audio.dtsi +++ b/qcom/sa8155-vm-audio.dtsi @@ -262,7 +262,7 @@ qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; qcom,msm-cpudai-tdm-data-delay = <0>; - qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <3>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <10>; dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36912>; @@ -307,7 +307,7 @@ qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; qcom,msm-cpudai-tdm-data-delay = <0>; - qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <12>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>; dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36913>; From 927ea7aaae27f016b7e07b0a5c397bf5539c3a74 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Mon, 29 Mar 2021 16:53:26 -0700 Subject: [PATCH 1180/1809] ARM: dts: msm: Add child node entry for MBB NTN3 i2c client on sdxlemur In order to access NTN3 switch registers add i2c client properties. By accessing these registers, root complex driver can toggle NTN3 GPIOs tied to downstream endpoint reset. i2c interface is also used to dump NTN3 registers for debugging PCIe link related issues. Change-Id: Ia92127f138c2d21ed51e7803b26bcfbb7f2c127f --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 3972cf326b4a..ee8d7977ed58 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -24,7 +24,20 @@ }; +&i2c_3 { + pcie_i2c_ctrl: pcie_i2c_ctrl { + compatible = "qcom,pcie0-i2c-ntn3"; + reg = <0x77>; + gpio-config-reg = <0x801208>; + ep-reset-reg = <0x801210>; + ep-reset-gpio-mask = <0x9>; + dump-regs = <0x801330 0x801350 0x801370>; + }; +}; + &pcie0 { + pcie-i2c-phandle = <&i2c_3>; + qcom,filtered-bdfs = <0x02080000>; vreg-3p3-supply = <&aqr_vreg>; From b49809f9d8834616c325e6498e9fe6cc62ecdf16 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Mon, 29 Mar 2021 20:34:20 -0700 Subject: [PATCH 1181/1809] ARM: dts: msm: Add child node entry for CPE NTN3 i2c client on sdxlemur In order to access NTN3 switch registers add i2c client properties. By accessing these registers, root complex driver can toggle NTN3 GPIOs tied to downstream endpoint reset. i2c interface is also used to dump NTN3 registers for debugging PCIe link related issues. Change-Id: Ib7e85c463a0072dd2919559ab4d701d5eb42f400 --- qcom/sdxlemur-mtp-cpe.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 165cb7c5594c..e63b48f2a73d 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -35,7 +35,22 @@ }; }; +&i2c_5 { + status = "ok"; + + pcie_i2c_ctrl: pcie_i2c_ctrl { + compatible = "qcom,pcie0-i2c-ntn3"; + reg = <0x77>; + gpio-config-reg = <0x801208>; + ep-reset-reg = <0x801210>; + ep-reset-gpio-mask = <0xf>; + dump-regs = <0x801330 0x801350 0x801370>; + }; +}; + &pcie0 { + pcie-i2c-phandle = <&i2c_5>; + vreg-3p3-supply = <&aqr_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, From c66c1d37732ade73894253d4078bd343cbd2087d Mon Sep 17 00:00:00 2001 From: wadesong Date: Fri, 26 Feb 2021 16:09:30 +0530 Subject: [PATCH 1182/1809] ARM: dts: msm: enable mem_dump for Linux guest Enable mem_dump driver to support WLAN firmware dump download on crash. Change-Id: I4047c38eb952b655b04c7fa17972eb34db89b735 --- qcom/quin-vm-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 502e5d1896db..ac7e931d2929 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -45,6 +45,13 @@ alignment = <0 0x400000>; size = <0 0x1000000>; }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; }; firmware: firmware { @@ -298,4 +305,14 @@ compatible = "qcom,vm-restart"; status = "ok"; }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; }; From 8a6b4cccbfadeb983795dc61b8fdc2bd00b8a008 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 30 Mar 2021 14:21:03 +0800 Subject: [PATCH 1183/1809] ARM: dts: msm: correct modem etm path The Modem ETM should be connected to port 6 of the funnel in1. Change-Id: I324986173d2a7ffb1da72272be149144b40387c6 --- qcom/sdxnightjar-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar-coresight.dtsi b/qcom/sdxnightjar-coresight.dtsi index 1a5475cc1d32..1dddb7791c77 100644 --- a/qcom/sdxnightjar-coresight.dtsi +++ b/qcom/sdxnightjar-coresight.dtsi @@ -319,8 +319,8 @@ in-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; + port@6 { + reg = <6>; funnel_in1_in_modem_etm0: endpoint { remote-endpoint = <&modem_etm0_out_funnel_in1>; From 258fa5a5426cb3a28f7e3683098acfb3a03dfc7e Mon Sep 17 00:00:00 2001 From: Shilun Wan Date: Thu, 25 Mar 2021 18:36:22 +0800 Subject: [PATCH 1184/1809] ARM: dts: msm: Add initial device tree for direwolf virtual machine Add initial device tree to support direwolf virtual machine platform. Change-Id: I7c148e07fd2b0b278bce08acdb1f7c1ffb70c900 --- qcom/Makefile | 3 +- qcom/direwolf-vm-lv.dts | 10 ++ qcom/direwolf-vm-lv.dtsi | 10 ++ qcom/direwolf-vm.dtsi | 222 +++++++++++++++++++++++++++++++++++++++ qcom/pm8540-vm.dtsi | 20 ++++ 5 files changed, 264 insertions(+), 1 deletion(-) create mode 100644 qcom/direwolf-vm-lv.dts create mode 100644 qcom/direwolf-vm-lv.dtsi create mode 100644 qcom/direwolf-vm.dtsi create mode 100644 qcom/pm8540-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 3ff3cd7551c7..de5ea0359e17 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -357,7 +357,8 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8195-vm-la-mt.dtb \ sa8195-vm-lv-mt.dtb \ sa8195-vm-lv-lxc.dtb \ - sa6155p-vm-la.dtb + sa6155p-vm-la.dtb \ + direwolf-vm-lv.dtb ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi-overlay.dtbo \ diff --git a/qcom/direwolf-vm-lv.dts b/qcom/direwolf-vm-lv.dts new file mode 100644 index 000000000000..d2a7069c72c7 --- /dev/null +++ b/qcom/direwolf-vm-lv.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine"; + compatible = "qcom,direwolf"; + qcom,board-id = <0x1000002 0>; +}; diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi new file mode 100644 index 000000000000..9e05ed049c14 --- /dev/null +++ b/qcom/direwolf-vm-lv.dtsi @@ -0,0 +1,10 @@ +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x66500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi new file mode 100644 index 000000000000..6ed8aadb34e2 --- /dev/null +++ b/qcom/direwolf-vm.dtsi @@ -0,0 +1,222 @@ +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine"; + qcom,msm-name = "Direwolf V1"; + qcom,msm-id = <460 0x10000>; +}; + +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x0F000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,direwolf-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <14 494 2>, <138 623 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; +}; + +®ulator { + gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc { + regulator-name = "gcc_usb30_prim_gdsc"; + }; + + gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc { + regulator-name = "gcc_usb30_sec_gdsc"; + }; + + L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 { + regulator-name = "ldoa5"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 { + regulator-name = "ldoa7"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 { + regulator-name = "ldoa13"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + }; + + L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 { + regulator-name = "ldoc1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 { + regulator-name = "ldoc7"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 { + regulator-name = "ldoc2"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + }; +}; + +#include "direwolf-pinctrl.dtsi" +#include "pm8540-vm.dtsi" diff --git a/qcom/pm8540-vm.dtsi b/qcom/pm8540-vm.dtsi new file mode 100644 index 000000000000..a6bcf5460e07 --- /dev/null +++ b/qcom/pm8540-vm.dtsi @@ -0,0 +1,20 @@ +#include + +&spmi_bus { + qcom,pm8540@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + From a90ef723f5dbd74471cbe326cb78233619caa4e2 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 25 Mar 2021 12:30:52 +0530 Subject: [PATCH 1185/1809] ARM: dts: msm: Disable IPA for yupik iot qcs variants Add change to disable IPA for yupik iot qcs varaints. Change-Id: I87098cdae524f33e6534c23d87e499d0efe1a35d --- qcom/yupikp-iot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/yupikp-iot.dtsi b/qcom/yupikp-iot.dtsi index 4c713241a0bc..18eb5c8ee5a3 100644 --- a/qcom/yupikp-iot.dtsi +++ b/qcom/yupikp-iot.dtsi @@ -5,3 +5,13 @@ compatible = "qcom,yupikp-iot"; qcom,msm-id = <498 0x10000>; }; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; From db11e69be9f216ddbc5ce33feb5ae32a941b2f27 Mon Sep 17 00:00:00 2001 From: Xiaowen Wu Date: Tue, 30 Mar 2021 10:15:39 -0700 Subject: [PATCH 1186/1809] ARM: dts: msm: Move display include to end of quin-vm-common Move display include to end of quin-vm-common to avoid probe defer. Change-Id: I37594a79fbc29a68e67f97f505a19095dd3af261 --- qcom/quin-vm-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 502e5d1896db..bad8cdf02438 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -80,8 +80,6 @@ }; }; -#include "display/quin-vm-display.dtsi" - &soc { #address-cells = <1>; #size-cells = <1>; @@ -299,3 +297,5 @@ status = "ok"; }; }; + +#include "display/quin-vm-display.dtsi" From aa54ad1236def079a4fea5f154136ac59e5e416c Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Thu, 25 Mar 2021 17:15:43 +0800 Subject: [PATCH 1187/1809] ARM: dts: msm: enable dual wlan for Quin SA8195 VM LXC To support dual wlan, increase cma size and pass through pcie RC0 and RC2. Change-Id: Id7e16b91650e0d9b4d4d08c7b121c7c47527028d --- qcom/sa8195-vm-lv-cnss-lxc.dtsi | 577 ++++++++++++++++++++++++++++++++ qcom/sa8195-vm-lv-lxc.dtsi | 6 + qcom/sa8195-vm.dtsi | 2 +- qcom/sdmshrike-pinctrl.dtsi | 2 +- 4 files changed, 585 insertions(+), 2 deletions(-) create mode 100644 qcom/sa8195-vm-lv-cnss-lxc.dtsi diff --git a/qcom/sa8195-vm-lv-cnss-lxc.dtsi b/qcom/sa8195-vm-lv-cnss-lxc.dtsi new file mode 100644 index 000000000000..7ed9ddb4651b --- /dev/null +++ b/qcom/sa8195-vm-lv-cnss-lxc.dtsi @@ -0,0 +1,577 @@ +&cnss_pins { + cnss_wlan_en_active2: cnss_wlan_en_active2 { + mux { + pins = "gpio170"; + function = "gpio"; + }; + + config { + pins = "gpio170"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep2: cnss_wlan_en_sleep2 { + mux { + pins = "gpio170"; + function = "gpio"; + }; + + config { + pins = "gpio170"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; +}; + +&cnss_pcie { + status = "disabled"; +}; + +&soc { + /* Support Dual Hastings case*/ + cnss_pcie0: qcom,cnss-qca-converged0 { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,qrtr_node_id = <0x10>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8195_1_s5>; + vdd-wlan-rfa1-supply = <&pm8195_1_s2>; + vdd-wlan-rfa2-supply = <&pm8195_2_s5>; + vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0xb0000000 0x10000>; + + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; + + cnss_pcie2: qcom,cnss-qca-converged2 { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <2>; + qcom,bus-type=<0>; + qcom,qrtr_node_id = <0x20>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xd0000000 0xd0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8195_1_s5>; + vdd-wlan-rfa1-supply = <&pm8195_1_s2>; + vdd-wlan-rfa2-supply = <&pm8195_2_s5>; + vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; + wlan-en-gpio = <&tlmm 170 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active2>; + pinctrl-1 = <&cnss_wlan_en_sleep2>; + + chip_cfg@0 { + reg = <0xd0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xd0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xd0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; +}; + +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "bypass"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; + +&pcie_rc2 { + cnss_pci2: cnss_pci2 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group2>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group2: cnss_pci_iommu_group2 { + qcom,iommu-dma-addr-pool = <0xc0000000 0x10000000>; + qcom,iommu-dma = "bypass"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 970dff14d4bf..fbfc54be8767 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -38,6 +38,10 @@ status = "ok"; }; +&linux_cma { + size = <0x0 0x3c00000>; +}; + &pcie0_msi { status = "ok"; }; @@ -53,3 +57,5 @@ &pcie2 { status = "ok"; }; + +#include "sa8195-vm-lv-cnss-lxc.dtsi" diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 334e1c14d6e9..8cf8b0a09440 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -145,7 +145,7 @@ gpio = <&tlmm 174 0>; }; - qcom,cnss-qca-converged { + cnss_pcie: qcom,cnss-qca-converged { compatible = "qcom,cnss-qca-converged"; qcom,converged-dt; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index cbfbf3e9cdd0..4bb550245cd9 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -3573,7 +3573,7 @@ }; }; - cnss_pins { + cnss_pins: cnss_pins { cnss_wlan_en_active: cnss_wlan_en_active { mux { pins = "gpio169"; From 370b9a556857ec7a33fe2b5c5065e5b62def357c Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Thu, 25 Mar 2021 17:22:44 +0800 Subject: [PATCH 1188/1809] ARM: dts: msm: add 2nd UFS for Quin SA8195 LXC VM enable 2nd UFS pass-through on SA8195 LXC VM. Change-Id: I71cbee302756cbcd2a664daa2f46b60d329cfeaf --- qcom/sa8195-vm-lv-lxc.dtsi | 9 ++ qcom/sa8195-vm-ufs.dtsi | 211 +++++++++++++++++++++++++++++++++++++ qcom/sa8195-vm.dtsi | 4 + 3 files changed, 224 insertions(+) create mode 100644 qcom/sa8195-vm-ufs.dtsi diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index fbfc54be8767..36b87490f86b 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -59,3 +59,12 @@ }; #include "sa8195-vm-lv-cnss-lxc.dtsi" +#include "sa8195-vm-ufs.dtsi" + +&ufs2phy_mem { + status = "ok"; +}; + +&ufshc2_mem { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-ufs.dtsi b/qcom/sa8195-vm-ufs.dtsi new file mode 100644 index 000000000000..56d4e8f17db7 --- /dev/null +++ b/qcom/sa8195-vm-ufs.dtsi @@ -0,0 +1,211 @@ +#include + +®ulator { + L17A: pm8195_1_l17: regulator-pm8195-1-l17 { + regulator-name = "ldoa17"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3544000>; + regulator-always-on; + regulator-allow-set-load; + }; + + L5C: pm8195_2_l5: regulator-pm8195-2-l5 { + regulator-name = "ldoc5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + L10E: pm8195_3_l10: regulator-pm8195-3-l10 { + regulator-name = "ldoe10"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + regulator-always-on; + }; + + S4A: pm8195_1_s4: regulator-pm8195-1-s4 { + regulator-name = "smpa4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&soc { + ufs2_ice: ufs2ice@1d70000 { + compatible = "qcom,ice"; + reg = <0x1d70000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_CARD_2_AHB_CLK>, + <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_card_2_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + + status = "disabled"; + }; + + ufs2phy_mem: ufsphy2_mem@1d67000 { + compatible = "qcom,ufs-phy-qmp-v4"; + reg = <0x1d67000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + ufs-qcom-crypto = <&ufs2_ice>; + + lanes-per-direction = <2>; + + vdda-phy-supply = <&pm8195_3_l5>; + vdda-pll-supply = <&pm8195_1_l9>; + vdda-phy-max-microamp = <138000>; + vdda-pll-max-microamp = <65100>; + + clock-names = "ref_clk_src", + "ref_aux_clk"; + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc2_mem: ufshc2@1d64000 { + compatible = "qcom,ufshc"; + reg = <0x1d64000 0x3000>; + interrupts = ; + phys = <&ufs2phy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs2_ice>; + spm-level = <5>; + rpm-level = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + vdd-hba-supply = <&ufs_card_2_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8195_1_l17>; + vcc-voltage-level = <2894000 2904000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8195_2_l5>; + vccq2-supply = <&pm8195_1_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vccq-parent-supply = <&pm8195_1_s2>; + qcom,vccq-parent-max-microamp = <210000>; + + qcom,disable-lpm; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_CARD_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>, + <&gcc GCC_UFS_CARD_2_AHB_CLK>, + <&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <26>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <163 512 0 0>, <1 798 0 0>, /* No vote */ + <163 512 922 0>, <1 798 1000 0>, /* PWM G1 */ + <163 512 1844 0>, <1 798 1000 0>, /* PWM G2 */ + <163 512 3688 0>, <1 798 1000 0>, /* PWM G3 */ + <163 512 7376 0>, <1 798 1000 0>, /* PWM G4 */ + <163 512 1844 0>, <1 798 1000 0>, /* PWM G1 L2 */ + <163 512 3688 0>, <1 798 1000 0>, /* PWM G2 L2 */ + <163 512 7376 0>, <1 798 1000 0>, /* PWM G3 L2 */ + <163 512 14752 0>, <1 798 1000 0>, /* PWM G4 L2 */ + <163 512 127796 0>, <1 798 1000 0>, /* HS G1 RA */ + <163 512 255591 0>, <1 798 1000 0>, /* HS G2 RA */ + <163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RA */ + <163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RA */ + <163 512 255591 0>, <1 798 1000 0>, /* HS G1 RA L2 */ + <163 512 511181 0>, <1 798 1000 0>, /* HS G2 RA L2 */ + <163 512 4194304 0>, <1 798 204800 0>, /* HS G3 RA L2 */ + <163 512 8388608 0>, <1 798 409600 0>, /* HS G4 RA L2 */ + <163 512 149422 0>, <1 798 1000 0>, /* HS G1 RB */ + <163 512 298189 0>, <1 798 1000 0>, /* HS G2 RB */ + <163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RB */ + <163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RB */ + <163 512 298189 0>, <1 798 1000 0>, /* HS G1 RB L2 */ + <163 512 596378 0>, <1 798 1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <163 512 4194304 0>, <1 798 204800 409600>, /* HS G3 RB L2 */ + <163 512 8388608 0>, <1 798 409600 409600>, /* HS G4 RB L2 */ + <163 512 7643136 0>, <1 798 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <44 44>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs0_dev_reset_assert>; + pinctrl-1 = <&ufs0_dev_reset_deassert>; + + resets = <&gcc GCC_UFS_CARD_2_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 8cf8b0a09440..b4b5d0bea8aa 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -770,6 +770,10 @@ regulator-name = "pcie_3_gdsc"; }; + ufs_card_2_gdsc: ufs_card_2_gdsc { + regulator-name = "ufs_card_2_gdsc"; + }; + L2A: pm8195_1_l2: regulator-pm8195-1-l2 { regulator-name = "ldoa2"; regulator-min-microvolt = <1800000>; From 8dcc77823b472bd453b36d9775e1768ad56ad84c Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 31 Mar 2021 14:38:19 +0800 Subject: [PATCH 1189/1809] ARM: dts: msm: Correct the soc dts info for HHG HSP Pro platform HHG HSP Pro uses P variant, so correct the soc dts for it. Change-Id: I761e81edb5c914c4a1e793d31873d3f85366c89e --- qcom/Makefile | 6 +++--- qcom/lahaina-v2.1-hhg-hsp-pro.dts | 10 ---------- ...ro-overlay.dts => lahainap-hhg-hsp-pro-overlay.dts} | 4 ++-- ...aina-hhg-hsp-pro.dtsi => lahainap-hhg-hsp-pro.dtsi} | 0 qcom/lahainap-v2.1-hhg-hsp-pro.dts | 10 ++++++++++ 5 files changed, 15 insertions(+), 15 deletions(-) delete mode 100644 qcom/lahaina-v2.1-hhg-hsp-pro.dts rename qcom/{lahaina-hhg-hsp-pro-overlay.dts => lahainap-hhg-hsp-pro-overlay.dts} (55%) rename qcom/{lahaina-hhg-hsp-pro.dtsi => lahainap-hhg-hsp-pro.dtsi} (100%) create mode 100644 qcom/lahainap-v2.1-hhg-hsp-pro.dts diff --git a/qcom/Makefile b/qcom/Makefile index 3ff3cd7551c7..4ec82fb9e8c9 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -8,7 +8,7 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \ lahaina-atp-overlay.dtbo \ lahaina-hdk-overlay.dtbo \ lahaina-hhg-overlay.dtbo \ - lahaina-hhg-hsp-pro-overlay.dtbo \ + lahainap-hhg-hsp-pro-overlay.dtbo \ lahaina-qrd-hsp-overlay.dtbo \ lahaina-qrd-module-overlay.dtbo \ lahainap-mtp-overlay.dtbo \ @@ -29,7 +29,7 @@ lahaina-cdp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-atp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-hdk-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-hhg-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb -lahaina-hhg-hsp-pro-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb +lahainap-hhg-hsp-pro-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb lahaina-qrd-hsp-overlay.dtbo-base := lahaina.dtb lahaina-qrd-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb lahaina-qrd-module-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb @@ -79,7 +79,7 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-v2.1-atp.dtb \ lahaina-v2.1-hdk.dtb \ lahaina-v2.1-hhg.dtb \ - lahaina-v2.1-hhg-hsp-pro.dtb \ + lahainap-v2.1-hhg-hsp-pro.dtb \ lahaina-v2.1-qrd.dtb \ lahaina-v2.1-qrd-module.dtb \ lahainap-v2.1-mtp.dtb \ diff --git a/qcom/lahaina-v2.1-hhg-hsp-pro.dts b/qcom/lahaina-v2.1-hhg-hsp-pro.dts deleted file mode 100644 index dce431e5d4ed..000000000000 --- a/qcom/lahaina-v2.1-hhg-hsp-pro.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "lahaina-v2.1.dtsi" -#include "lahaina-hhg-hsp-pro.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Lahaina HHG-HSP-PRO"; - compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; - qcom,board-id = <0x1001f 0x02>; -}; diff --git a/qcom/lahaina-hhg-hsp-pro-overlay.dts b/qcom/lahainap-hhg-hsp-pro-overlay.dts similarity index 55% rename from qcom/lahaina-hhg-hsp-pro-overlay.dts rename to qcom/lahainap-hhg-hsp-pro-overlay.dts index 0fd700376d25..52c065d37e35 100644 --- a/qcom/lahaina-hhg-hsp-pro-overlay.dts +++ b/qcom/lahainap-hhg-hsp-pro-overlay.dts @@ -1,10 +1,10 @@ /dts-v1/; /plugin/; -#include "lahaina-hhg-hsp-pro.dtsi" +#include "lahainap-hhg-hsp-pro.dtsi" / { - model = "Qualcomm Technologies, Inc. Lahaina HHG-HSP-PRO"; + model = "Qualcomm Technologies, Inc. Lahainap HHG-HSP-PRO"; compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; qcom,board-id = <0x1001f 0x02>; }; diff --git a/qcom/lahaina-hhg-hsp-pro.dtsi b/qcom/lahainap-hhg-hsp-pro.dtsi similarity index 100% rename from qcom/lahaina-hhg-hsp-pro.dtsi rename to qcom/lahainap-hhg-hsp-pro.dtsi diff --git a/qcom/lahainap-v2.1-hhg-hsp-pro.dts b/qcom/lahainap-v2.1-hhg-hsp-pro.dts new file mode 100644 index 000000000000..0ce56fd4bab6 --- /dev/null +++ b/qcom/lahainap-v2.1-hhg-hsp-pro.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahainap-v2.1.dtsi" +#include "lahainap-hhg-hsp-pro.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahainap HHG-HSP-PRO"; + compatible = "qcom,lahaina-hdk", "qcom,lahaina", "qcom,hdk"; + qcom,board-id = <0x1001f 0x02>; +}; From 871d2e4802fb8d23a37fd1cf868a5ddbe0e229da Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 31 Mar 2021 14:46:24 +0800 Subject: [PATCH 1190/1809] ARM: dts: msm: Update PCIe0 PHY settings to v1.00 for p v2.1 Update PCIe0 PHY setting to version 1.00 based on hardware recommendation for p v2.1. Change-Id: Ib0dc5da58ca41520d4f23efdd3f71239aef4a0e0 --- qcom/lahainap-v2.1.dtsi | 79 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 67728c60f3b9..4b57547fab01 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -5,3 +5,82 @@ compatible = "qcom,lahainap"; qcom,msm-id = <439 0x20001>, <502 0x20001>; }; + +&pcie0 { + qcom,pcie-phy-ver = <21101>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x10d8 0x07 0x0 + 0x0e3c 0x1d 0x0 + 0x0e40 0x0c 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; +}; From 8bea7d6100b58f49c32e631490054834bb57d9ca Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 31 Mar 2021 14:50:14 +0800 Subject: [PATCH 1191/1809] ARM: dts: msm: Enable L1SS sleep for p-v2.1 PCIe0 phy on v2.1 manages the phy PLL properly hence remove the software workaround to keep the phy PLL always on. Change-Id: I435a5776a75b6613d93f47d46ced65e0080b3a94 --- qcom/lahainap-v2.1.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 4b57547fab01..53307dcb647b 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -7,6 +7,7 @@ }; &pcie0 { + qcom,l1ss-sleep-disable = <0x0>; qcom,pcie-phy-ver = <21101>; qcom,phy-sequence = <0x0240 0x03 0x0 0x0094 0x08 0x0 From 934d36f20760a369feeca53e8323767bb318741f Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Thu, 27 Aug 2020 14:15:24 +0800 Subject: [PATCH 1192/1809] ARM: dts: msm: Add hwrng nodes for sa8155 and sa8195 VM Enables hwrng and adds related configuration for SA8155 and SA8195 VM. Change-Id: Ife6ef9c9989e650bdf041f52abe45afcb2f6c4b0 --- qcom/sa8155-vm.dtsi | 8 ++++++++ qcom/sa8195-vm.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 32bcde2c359c..d0eb054cb32b 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -723,6 +723,14 @@ qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + }; }; ®ulator { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 334e1c14d6e9..847a0d275234 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -735,6 +735,14 @@ qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + }; }; ®ulator { From 1bd678c3cb2caca9270c4dc367489325cca01af6 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 31 Mar 2021 13:18:07 +0530 Subject: [PATCH 1193/1809] ARM: dts: msm: Add support for USB secondary clocks for YUPIK IOT YUPIK IOT requires to use usb secondary gdsc and clocks, thus add support for the same. Change-Id: Ib6bd10974f5158b36ed1fb1492f1beef5e7b59c1 --- qcom/yupik-iot-qrd.dtsi | 12 +++++------- qcom/yupik-iot.dtsi | 4 ++++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/qcom/yupik-iot-qrd.dtsi b/qcom/yupik-iot-qrd.dtsi index 8964f1cca55d..3eaf08aed50a 100644 --- a/qcom/yupik-iot-qrd.dtsi +++ b/qcom/yupik-iot-qrd.dtsi @@ -21,13 +21,7 @@ , , , , , , - , , - , , - , , - , , - , , - , , - , , + , , ; }; @@ -38,3 +32,7 @@ &gcc_pcie_1_gdsc { status = "disabled"; }; + +&gcc_usb30_sec_gdsc { + status = "ok"; +}; diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi index 5667de65803a..f069e51e512b 100644 --- a/qcom/yupik-iot.dtsi +++ b/qcom/yupik-iot.dtsi @@ -24,3 +24,7 @@ &gcc_pcie_1_gdsc { status = "ok"; }; + +&gcc_usb30_sec_gdsc { + status = "ok"; +}; From b8b41f5ddf52e4317884533d02a2568a97b6c14a Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Wed, 30 Dec 2020 12:25:32 +0530 Subject: [PATCH 1194/1809] ARM: dts: msm: STMMAC changes for SA8155 Enable the fastmap for sa8155 for high t-put. Change-Id: Id9e30647b0cf297360736d04a7055a8aa1e65350 --- qcom/sa8155.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 62b94a170b07..16db15f09860 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -130,6 +130,7 @@ ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; iommus = <&apps_smmu 0x3C0 0x0>; + qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; }; From 04d7be3b483c624bd29e43aafa3a6a0be2d1f13f Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Wed, 31 Mar 2021 15:59:25 +0530 Subject: [PATCH 1195/1809] ARM: dts: msm: Add MDM flag for Audio memory regions Adding mdm specific flags in the audio memory regions to distinguish when the hyp-assign calls are made. These differ bnetween the mdm and non-mdm targets. Change-Id: Ie5143ab19442b03608a538d7d5983125e05e0dd2 --- qcom/sdx-audio-lpass.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi index bc1beebeac0c..2369bfe586b0 100644 --- a/qcom/sdx-audio-lpass.dtsi +++ b/qcom/sdx-audio-lpass.dtsi @@ -15,6 +15,7 @@ qcom,msm-audio-ion { compatible = "qcom,msm-audio-ion-cma"; + qcom,scm-mp-enabled; memory-region = <&audio_mem>; }; From ed40237f52a1bc6083d4e9ed994b6d455108f359 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Wed, 31 Mar 2021 17:29:31 +0530 Subject: [PATCH 1196/1809] ARM: dts: msm: set dma mapping mode to atomic set qcom,iommu-dma = "atomic" for all gvm targets to avoid issues with fastmap mappings. Change-Id: I17f71b3bdc2bb1c1d2aa13411999305fc4b5a5d4 --- qcom/sa6155p-vm.dtsi | 2 ++ qcom/sa8155-vm.dtsi | 4 ++++ qcom/sa8195-vm.dtsi | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 55ebcf73df15..e8eeb6962b76 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -436,10 +436,12 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 32bcde2c359c..17a44b250337 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -854,21 +854,25 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_2 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_3 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &pcie_rc0 { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 334e1c14d6e9..3f1fbfac0bf5 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -881,19 +881,23 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_2 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; &qupv3_3 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; + qcom,iommu-dma = "atomic"; }; From 4d9ec4b0b613e1fb0d35f0daf17188bf5fcc8c3e Mon Sep 17 00:00:00 2001 From: Piyush Dhyani Date: Thu, 1 Apr 2021 01:57:54 +0530 Subject: [PATCH 1197/1809] ARM: dts: msm: Add DT entry for wrapper pm support Adding DT entry for target using wrapper PM support. Change-Id: I18be9407533812277c4cb3b95ca280c26e13a485 --- qcom/sdxnightjar.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 38817f15fe7e..4671254ba302 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1009,6 +1009,7 @@ qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; qcom,use-rg10-limitation-mitigation; + qcom,use-wrapper-pm-support; qcom,use-ipa-tethering-bridge; qcom,modem-cfg-emb-pipe-flt; clock-names = "core_clk"; From 6d10f124be74a57bb9c835a2287c1cb929ccb9d9 Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Thu, 18 Mar 2021 15:23:51 +0800 Subject: [PATCH 1198/1809] ARM: dts: msm: add audio gvm dts for auto direwolf platform Add GVM audio device tree file for direwolf platform Change-Id: I544bba6f2741138d1699a410cb27c410e95c1e4b --- bindings/sound/qcom-audio-dev.txt | 119 +++++++ qcom/direwolf-vm-audio.dtsi | 548 ++++++++++++++++++++++++++++++ qcom/direwolf-vm.dtsi | 1 + 3 files changed, 668 insertions(+) create mode 100644 qcom/direwolf-vm-audio.dtsi diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 8819272c0202..c910d433cd58 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -2610,3 +2610,122 @@ Example: "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; }; + +* SA8295 ASoC Machine driver + +Required properties: +- compatible : "qcom,sa8295-asoc-snd-auto" for auto adp codec and + "qcom,sa8295-asoc-snd-auto-custom" for auto custom codec. +- qcom,model : The user-visible name of this sound card. +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order given + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". +Optional properties: +- qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target +- qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target +- qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces +- qcom,msm_audio_ssr_devs: List the snd event framework clients + +Example: + + sound-adp-star { + compatible = "qcom,sa8295-asoc-snd-adp-star"; + qcom,model = "sa8295-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_tx_0>, <&dai_sec_tdm_tx_1>, + <&dai_sec_tdm_tx_2>, <&dai_sec_tdm_tx_3>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_rx_1>, + <&dai_tert_tdm_rx_2>, <&dai_tert_tdm_rx_3>, + <&dai_tert_tdm_rx_4>, <&dai_tert_tdm_tx_0>, + <&dai_tert_tdm_tx_1>, <&dai_tert_tdm_tx_2>, + <&dai_tert_tdm_tx_3>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_tx_1>, <&dai_quat_tdm_tx_2>, + <&dai_quat_tdm_tx_3>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36883", + "msm-dai-q6-tdm.36885", "msm-dai-q6-tdm.36887", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36898", + "msm-dai-q6-tdm.36900", "msm-dai-q6-tdm.36902", + "msm-dai-q6-tdm.36904", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36899", "msm-dai-q6-tdm.36901", + "msm-dai-q6-tdm.36903", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36915", "msm-dai-q6-tdm.36917", + "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; diff --git a/qcom/direwolf-vm-audio.dtsi b/qcom/direwolf-vm-audio.dtsi new file mode 100644 index 000000000000..6cf9114fc14d --- /dev/null +++ b/qcom/direwolf-vm-audio.dtsi @@ -0,0 +1,548 @@ +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + /delete-property/ iommus; + /delete-property/ qcom,iommu-dma-addr-pool; +}; + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <10>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + afe_pcm_rx_1: qcom,msm-dai-q6-be-afe-pcm-rx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <226>; + }; + + afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <242>; + }; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + snd_8295: sound-adp-star { + compatible = "qcom,sa8295-asoc-snd-adp-star"; + qcom,model = "sa8295-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&afe_pcm_rx_1>, <&afe_proxy_tx_1>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.226", "msm-dai-q6-dev.242", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 6ed8aadb34e2..28afac2fd760 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -220,3 +220,4 @@ #include "direwolf-pinctrl.dtsi" #include "pm8540-vm.dtsi" +#include "direwolf-vm-audio.dtsi" From e6b1b14bbe7de3997633a8297eb7604abe33f2bc Mon Sep 17 00:00:00 2001 From: kmeng Date: Fri, 6 Nov 2020 17:33:01 +0800 Subject: [PATCH 1199/1809] ARM: dts: msm: multi-card for Gen3 platform lxc dtbo Add multi-card configuration for LXC overlay DT and include shared display configuration for original overlay DT Different device trees will be selected at compile time based on the flag CONFIG_AUTO_LXC_OVERLAY. Change-Id: If5e05fddd90f63c93188f21129d8020dbec3a223 --- qcom/Makefile | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/qcom/Makefile b/qcom/Makefile index de5ea0359e17..f3699174e011 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -228,16 +228,24 @@ dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) - dtbo-$(CONFIG_ARCH_SA8155) += \ +ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) + dtbo-$(CONFIG_ARCH_SA8155) += \ + sa8155-v2-adp-air-lxc-overlay.dtbo \ + sa8155p-v2-adp-air-lxc-overlay.dtbo +else + dtbo-$(CONFIG_ARCH_SA8155) += \ sa8155-adp-star-overlay.dtbo \ sa8155p-adp-star-overlay.dtbo \ sa8155-v2-adp-air-overlay.dtbo \ sa8155p-v2-adp-air-overlay.dtbo +endif sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb +sa8155-v2-adp-air-lxc-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb +sa8155p-v2-adp-air-lxc-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155p-adp-star.dtb \ @@ -248,7 +256,11 @@ dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) - dtbo-$(CONFIG_ARCH_SA6155) += \ +ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) + dtbo-$(CONFIG_ARCH_SA6155) += \ + sa6155p-v2-adp-air-lxc-overlay.dtbo +else + dtbo-$(CONFIG_ARCH_SA6155) += \ sa6155-adp-star-overlay.dtbo \ sa6155p-adp-star-overlay.dtbo \ sa6155p-adp-star-lpass-overlay.dtbo \ @@ -257,6 +269,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) sa6155p-v2-adp-star-overlay.dtbo \ sa6155p-v2-adp-air-overlay.dtbo \ sa6155p-v2-adp-air-lpass-overlay.dtbo +endif sa6155-adp-star-overlay.dtbo-base := sa6155.dtb sa6155p-adp-star-overlay.dtbo-base := sa6155p.dtb @@ -266,6 +279,7 @@ sa6155-adp-air-overlay.dtbo-base := sa6155.dtb sa6155p-adp-air-overlay.dtbo-base := sa6155p.dtb sa6155p-v2-adp-air-overlay.dtbo-base := sa6155p.dtb sa6155p-v2-adp-air-lpass-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-air-lxc-overlay.dtbo-base := sa6155p.dtb else dtb-$(CONFIG_ARCH_SA6155) += sa6155-adp-star.dtb \ sa6155p-adp-star.dtb \ @@ -278,12 +292,18 @@ dtb-$(CONFIG_ARCH_SA6155) += sa6155-adp-star.dtb \ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) + dtbo-$(CONFIG_ARCH_SA8195) += \ + sa8195p-v2-adp-air-lxc-overlay.dtbo +else dtbo-$(CONFIG_ARCH_SA8195) += \ sa8195p-adp-star-overlay.dtbo \ sa8195p-v2-adp-air-overlay.dtbo +endif sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb +sa8195p-v2-adp-air-lxc-overlay.dtbo-base := sa8195p.dtb else dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \ sa8195p-v2-adp-air.dtb From cb7e84cd6d8242dec94db6ae8661844b69b89b7c Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Wed, 31 Mar 2021 00:22:07 +0530 Subject: [PATCH 1200/1809] ARM: dts: msm: Add cpufreq-hw clock node for MONACO Add cpufreq-hw node for clients to request and scale avalible frequencies for cpu cores for MONACO. Change-Id: I0b01a115dcd7e3007d6a51eb216fdfd66a500e46 --- qcom/monaco-rumi.dtsi | 6 ++++++ qcom/monaco.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 00444217e4c5..06eae741f70b 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -1,3 +1,5 @@ +#include + &soc { timer { clock-frequency = <5000000>; @@ -17,4 +19,8 @@ clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GPLL0>; +}; + #include "monaco-stub-regulator.dtsi" diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4e8849fa427f..47415a453570 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -37,6 +37,7 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; @@ -59,6 +60,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { @@ -77,6 +79,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { @@ -95,6 +98,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; + qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { @@ -724,6 +728,24 @@ #reset-cells = <1>; }; + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw"; + reg = <0xf521000 0x1400>; + reg-names = "freq-domain0"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; + qcom,max-lut-entries = <12>; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@f521000 { + compatible = "qcom,cpufreq-hw-debug"; + reg = <0xf521000 0x1400>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, From 0244f7aff17c0f7f6c0d66b55c312aefa2a95d8f Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Fri, 7 Aug 2020 13:28:22 +0530 Subject: [PATCH 1201/1809] ARM: dts: msm: Add multi queue support Add multi queue support in stmmac driver to enable the Avb data paths. Change-Id: I9a63d299b1116ceceb8e2e86b74536483c3ae7be --- qcom/sa8155.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 16db15f09860..d2f9f4246f21 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -62,6 +62,64 @@ read-only; ranges; }; + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + }; + ethqos_hw: qcom,ethernet@00020000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; @@ -74,13 +132,17 @@ <&gcc GCC_EMAC_PTP_CLK>, <&gcc GCC_EMAC_RGMII_CLK>; clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; interrupts-extended = <&intc 0 689 4>, <&intc 0 699 4>, <&tlmm 124 2>; interrupt-names = "macirq", "eth_lpi", "phy-intr"; snps,tso; - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; gdsc_emac-supply = <&emac_gdsc>; From 424c924b1aaeb65b2c58e2f5d4104d58f2c5d06b Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 1 Apr 2021 12:28:39 +0530 Subject: [PATCH 1202/1809] ARM: dts: msm: Add base device tree for direwolf LA guest Add initial device tree for direwolf la guest. Change-Id: I13d151cde2468559961c1c6bb458a8f41a72ba8d --- qcom/Makefile | 3 ++- qcom/direwolf-vm-la.dts | 10 ++++++++++ qcom/direwolf-vm-la.dtsi | 6 ++++++ qcom/direwolf-vm.dtsi | 12 ++++++++++++ 4 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 qcom/direwolf-vm-la.dts create mode 100644 qcom/direwolf-vm-la.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index de5ea0359e17..f0f8a156f987 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -358,7 +358,8 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8195-vm-lv-mt.dtb \ sa8195-vm-lv-lxc.dtb \ sa6155p-vm-la.dtb \ - direwolf-vm-lv.dtb + direwolf-vm-lv.dtb \ + direwolf-vm-la.dtb ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi-overlay.dtbo \ diff --git a/qcom/direwolf-vm-la.dts b/qcom/direwolf-vm-la.dts new file mode 100644 index 000000000000..f535375cac94 --- /dev/null +++ b/qcom/direwolf-vm-la.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine"; + compatible = "qcom,direwolf"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi new file mode 100644 index 000000000000..10aa218eda14 --- /dev/null +++ b/qcom/direwolf-vm-la.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x66500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 6ed8aadb34e2..d402678a7242 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -5,6 +5,18 @@ model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine"; qcom,msm-name = "Direwolf V1"; qcom,msm-id = <460 0x10000>; + + firmware:firmware { + android { + /delete-property/ boot_devices; + fstab { + vendor { + dev="/dev/block/platform/vdevs/1c160000.virtio_blk/vdc"; + fsmgr_flags = "wait"; + }; + }; + }; + }; }; &soc { From 9872fb03a5ba7428bef26c1985b517de2e74e5fa Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Wed, 24 Mar 2021 11:56:08 +0800 Subject: [PATCH 1203/1809] ARM: dts: msm: Add common CMA region for sdxnightjar Add a 12MB CMA region for common use. Change-Id: Id7b8fbe888d345086cbf18cd48c88659260e2893 --- qcom/sdxnightjar.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 38817f15fe7e..4e4ba8339ff5 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -53,6 +53,15 @@ label = "mss_mem"; }; + common_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0xc00000>; + linux,cma-default; + }; + qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; From 380c1351387bf29768a38b6cf1289e919c4b72fc Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 30 Mar 2021 12:06:12 +0800 Subject: [PATCH 1204/1809] ARM: dts: msm: remove mem_dump region Remove the mem_dump_region cma region and change "memory-region" of mem_dump reference to common cma node on sdxnightjar. Change-Id: I620ff826fb78b555c711471e1dac4f5ed6daadf4 --- qcom/sdxnightjar.dtsi | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 4e4ba8339ff5..b819eb181b32 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -70,13 +70,6 @@ size = <0x400000>; }; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - size = <0x400000>; - }; - }; aliases { }; @@ -440,7 +433,7 @@ mem_dump { compatible = "qcom,mem-dump"; - memory-region = <&dump_mem>; + memory-region = <&common_cma>; c0_context { qcom,dump-size = <0x800>; From 2be7b3d2104c02b2cf683f1a56be55136bc04c67 Mon Sep 17 00:00:00 2001 From: Raymon Sang Date: Tue, 30 Mar 2021 12:06:46 +0800 Subject: [PATCH 1205/1809] ARM: dts: msm: remove wlan section of mem_dump Remove cnss_wlan section in mem_dump on sdxnightjar. Change-Id: I9d18a20aa9dc4d5d83a174378977c9de515d7526 --- qcom/sdxnightjar.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index b819eb181b32..ff431030199e 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -440,11 +440,6 @@ qcom,dump-id = <0x0>; }; - cnss_wlan { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe1>; - }; - etr_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x100>; From 3fd9de4e3e24a9c24ada010b5b42add454a43378 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Wed, 30 Dec 2020 12:27:15 +0530 Subject: [PATCH 1206/1809] ARM: dts: msm: STMMAC changes for SA8195 Enable fastmap for sa8195 for high t-put. Change-Id: I400fd50c232d880fb1b7575b6cebd09a8c1bb77a --- qcom/sa8195p-adp-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 198a39402a3e..382f0d6d7230 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -182,6 +182,7 @@ ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; iommus = <&apps_smmu 0x7C0 0x0>; + qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; }; From 7cde7a3e6968794799de29d5f21a59f5399b7b96 Mon Sep 17 00:00:00 2001 From: Xiaoning Ma Date: Thu, 1 Apr 2021 17:37:39 +0800 Subject: [PATCH 1207/1809] ARM: dts: msm: Enable GPIO function of GPIO171 GPIO171 is used as 2nd BT chip's bt_en on SA8195 VM LXC. Change-Id: If7851d95a19ec703a663a4d48a1e0530554802e5 --- qcom/sa8195-vm-lv-cnss-lxc.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sa8195-vm-lv-cnss-lxc.dtsi b/qcom/sa8195-vm-lv-cnss-lxc.dtsi index 7ed9ddb4651b..f1c1fbf2095a 100644 --- a/qcom/sa8195-vm-lv-cnss-lxc.dtsi +++ b/qcom/sa8195-vm-lv-cnss-lxc.dtsi @@ -575,3 +575,20 @@ }; }; }; + +&soc { + tlmm: pinctrl@3000000 { + bt_en_active: bt_en_active { + mux { + pins = "gpio172", "gpio171"; + function = "gpio"; + }; + + config { + pins = "gpio172", "gpio171"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; From dffb01fea04883d229fe2bc432f02a0bd3d293a5 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Mon, 25 Jan 2021 12:11:23 +0530 Subject: [PATCH 1208/1809] ARM: dts: msm: SA6155 EAVB fix Fix the EAVB class A failure issue. Change-Id: I0502c68665bb56bfe87283cfee9d1dc330381053 --- qcom/sa6155-adp-common.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index 1b00deb39e43..ba24c846e482 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -49,7 +49,7 @@ }; mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; + snps,tx-queues-to-use = <4>; snps,tx-sched-sp; queue0 { snps,dcb-algorithm; @@ -97,8 +97,9 @@ "phy-intr"; snps,tso; + snps,pbl = <32>; rx-fifo-depth = <16384>; - tx-fifo-depth = <32768>; + tx-fifo-depth = <20480>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; snps,reset-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; From a6bd5335545cacc7d21316ddb921803825d87a86 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Mon, 25 Jan 2021 12:11:31 +0530 Subject: [PATCH 1209/1809] ARM: dts: msm: SA8155 EAVB fix Fix the EAVB class A failure issue. Change-Id: Ife972c3b4dec2f571fa3db32bb99135be62ff8f3 --- qcom/sa8155.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index d2f9f4246f21..9aea5b2b4036 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -93,7 +93,7 @@ }; mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; + snps,tx-queues-to-use = <4>; snps,tx-sched-sp; queue0 { snps,dcb-algorithm; @@ -139,8 +139,9 @@ interrupt-names = "macirq", "eth_lpi", "phy-intr"; snps,tso; + snps,pbl = <32>; rx-fifo-depth = <16384>; - tx-fifo-depth = <32768>; + tx-fifo-depth = <20480>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; From e19dd9af219f5ff7dd1f73dd0e8e0b0b1dfdb9e8 Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Fri, 2 Apr 2021 18:44:57 +0530 Subject: [PATCH 1210/1809] ARM: dts: msm: Reduce cma region Remove the qseecom_region cma region and change "memory-region" of qseecom_mem reference to common cma node on sdxnightjar. Change-Id: Ie5dac221d7600938f7dda312ce2ca7c38ea2cf4a --- qcom/sdxnightjar-ion.dtsi | 2 +- qcom/sdxnightjar.dtsi | 10 +--------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/qcom/sdxnightjar-ion.dtsi b/qcom/sdxnightjar-ion.dtsi index 1f533ccd6081..4946dc34ac47 100644 --- a/qcom/sdxnightjar-ion.dtsi +++ b/qcom/sdxnightjar-ion.dtsi @@ -13,7 +13,7 @@ qcom,ion-heap@27 { /* QSEECOM HEAP */ reg = ; - memory-region = <&qseecom_mem>; + memory-region = <&common_cma>; qcom,ion-heap-type = "DMA"; }; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index ff431030199e..11919189aaae 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -62,14 +62,6 @@ linux,cma-default; }; - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x400000>; - }; - }; aliases { }; @@ -583,7 +575,7 @@ compatible = "qcom,qseecom"; reg = <0x87800000 0x200000>; reg-names = "secapp-region"; - memory-region = <&qseecom_mem>; + memory-region = <&common_cma>; qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; From d3d75844ab72c05be57972b0f355cf38cf90657e Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 2 Mar 2021 11:12:52 +0530 Subject: [PATCH 1211/1809] ARM: dts: msm: Add dtsi changes for PCIe1 enablement for yupik Add dtsi changes for PCIe1 enablement in RC mode for yupik. Change-Id: I271d908a3e58f703d0be39b53a65d88bc8bb2638 --- qcom/yupik-iot-idp.dtsi | 18 +++ qcom/yupik-pcie.dtsi | 296 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-pinctrl.dtsi | 68 +++++++++ 3 files changed, 382 insertions(+) diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 55e5d0e3bf91..6f7484cd3458 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -8,3 +8,21 @@ &pcie0_msi { status = "ok"; }; + +&pcie1 { + status = "ok"; + qcom,boot-option = <0x0>; + qcom,ep-gpio = <&tlmm 19 0>; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default + &pcie1_ep_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default + &pcie1_ep_default>; +}; + +&pcie1_msi { + status = "ok"; +}; diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 72baf84b90a6..66476baf7f8b 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -274,4 +274,300 @@ status = "disabled"; }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie1_msi>; + + perst-gpio = <&tlmm 2 0>; + wake-gpio = <&tlmm 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_1_gdsc>; + vreg-1p8-supply = <&L6B>; + vreg-0p9-supply = <&L10C>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 99000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre1_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie_1_pipe_clk>; + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_1_axi_clk", + "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src"; + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1c80>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + qcom,boot-option = <0x1>; + qcom,drv-supported; + qcom,use-19p2mhz-aux-clk; + qcom,no-l0s-supported; + qcom,slv-addr-space-size = <0x20000000>; + qcom,ep-latency = <10>; + + qcom,pcie-phy-ver = <1102>; + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xca 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0xa2 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x75 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x1b 0x0 + 0x04e8 0x04 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xbf 0x0 + 0x0574 0x3f 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x15 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x05b8 0x38 0x0 + 0x063c 0x11 0x0 + 0x0684 0x75 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x08d4 0x04 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x1b 0x0 + 0x08e8 0x04 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xbf 0x0 + 0x0974 0x3f 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x15 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x09b8 0x38 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x77 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0be0 0x0f 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0eb4 0x33 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + status = "disabled"; + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a10040 { + compatible = "qcom,pci-msi"; + status = "disabled"; + msi-controller; + reg = <0x17a10040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index af3ae0e13f8f..9cc831f32f2f 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -1273,6 +1273,74 @@ }; }; + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio79"; + function = "pcie1_clkreqn"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_ep_default: pcie1_ep_default { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <16>; + output-high; + bias-disable; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK0 */ mux { From 41a643440b5a20fa9cf51e35860a2f1d75b2dec4 Mon Sep 17 00:00:00 2001 From: Anjana Hari Date: Mon, 5 Apr 2021 10:14:25 +0530 Subject: [PATCH 1212/1809] ARM: dts: msm: Add shared memory driver support Add shared memory driver support. Change-Id: I36738d87b75c87405b472d5c0ec5f4e62ad23341 --- qcom/sm8150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index d5e05617706b..a4a555204eb4 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1475,6 +1475,14 @@ }; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; From 5cabfa5faf1e40b32180b35df3c8e584317e3d87 Mon Sep 17 00:00:00 2001 From: Hiren Gohel Date: Sun, 1 Nov 2020 23:29:13 +0530 Subject: [PATCH 1213/1809] ARM: dts: msm: Add eMMC card support for monaco Add eMMC card support for monaco. Change-Id: I77b7ea4f7b10a4eccc7e0b7bcd65343cb3362995 --- qcom/monaco-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++++++ qcom/monaco-rumi.dtsi | 16 ++++++++++ qcom/monaco.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index f98e24512fec..44e0c9de0410 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -746,4 +746,55 @@ }; }; }; + /* SDC pin type */ + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + }; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 06eae741f70b..e0c8369a741f 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -24,3 +24,19 @@ }; #include "monaco-stub-regulator.dtsi" +&sdhc_1 { + status = "ok"; + + cap-mmc-highspeed; + max-frequency = <50000000>; + + vdd-supply = <&L25A>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 270000>; + + vdd-io-supply = <&L15A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 250000>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 47415a453570..61d40ae99ba4 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -21,6 +21,7 @@ aliases { serial0 = &qupv3_se6_2uart; hsuart0 = &qupv3_se5_4uart; + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ }; firmware: firmware {}; @@ -1004,6 +1005,69 @@ interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>,<1600 1600>, + /* 25 MB/s */ + <25600 250000>,<50000 133320>, + /* 50 MB/s */ + <51200 250000>,<65000 133320>, + /* 100 MB/s */ + <102400 250000>,<65000 133320>, + /* 200 MB/s */ + <204800 800000>,<200000 300000>, + /* 400 MB/s */ + <204800 800000>,<200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642E 0x0 0x01 0x2c010800 0x80040868>; + + no-sd; + no-sdio; + + bus-width = <8>; + non-removable; + supports-cqe; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; }; #include "monaco-pinctrl.dtsi" From 713f3e6bc2ace82fd8ba50b55d5de507fddaf16b Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 5 Apr 2021 18:20:23 +0530 Subject: [PATCH 1214/1809] dt-bindings: qpnp-lcdb-regulator: Add support for some LCDB DT properties Add support for the following LCDB devicee tree properties: "qcom,high-p2-blank-time-ns" to control the higher clamp threshold for p2 minimum on time. "qcom,low-p2-blank-time-ns" to control the lower clamp threshold for p2 minimum on time. "qcom,mpc-current-thr-ma" to control the mpc threshold for inductor current after start up is done. Change-Id: Ibc095328035bb52899846587e3db711a5c8296f2 --- bindings/regulator/qpnp-lcdb-regulator.txt | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/bindings/regulator/qpnp-lcdb-regulator.txt b/bindings/regulator/qpnp-lcdb-regulator.txt index 0a852ec29392..7fc3df91647e 100644 --- a/bindings/regulator/qpnp-lcdb-regulator.txt +++ b/bindings/regulator/qpnp-lcdb-regulator.txt @@ -61,13 +61,34 @@ First Level Node - LCDB module Usage: optional Value type: Definition: Controls the order of powering up BOOST, LDO AND NCP - blocks. Appilcable for PM7325B. Possible values are: 0, 1, 2, 3, 4. + blocks. Applicable for PM7325B. Possible values are: 0, 1, 2, 3, 4. 0 - Boost, LDO, NCP 1 - Boost, LDO 2 - Boost, NCP 3 - Boost only 4 - Boost, NCP, LDO +- qcom,high-p2-blank-time-ns + Usage: optional + Value type: + Definition: Controls the higher clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + +- qcom,low-p2-blank-time-ns + Usage: optional + Value type: + Definition: Controls the lower clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + +- qcom,mpc-current-thr-ma + Usage: optional + Value type: + Definition: Controls the mpc threshold for inductor current after start up + is done. Applicable for PM7325B. Possible values are 160, 200, 240, + 280, 320, 360, 400, 440. + Touch-to-wake (TTW) properties: TTW supports 2 modes of operation - HW and SW. In the HW mode the enable/disable From 450ef18b74c7b67f56d2cb50bce7dd2d66809405 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 1 Apr 2021 21:33:01 +0530 Subject: [PATCH 1215/1809] ARM: dts: msm: enable disable-alarm-wakeup for rtc Enable disable-alarm-wakeup property for rtc to avoid registering alarm interrupt as wake up capable for auto targets. Change-Id: I5b144adc887d8a3c8cea23cd0f716e749935961b --- qcom/sa6155-pmic.dtsi | 4 ++++ qcom/sa8155-pmic-overlay.dtsi | 1 + qcom/sa8195-pmic.dtsi | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index f5c3cb70b5ff..dee41906a9dc 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -108,3 +108,7 @@ }; }; }; + +&pm6155_1_rtc { + disable-alarm-wakeup; +}; diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi index 10ecbbf260bb..8fec335488de 100644 --- a/qcom/sa8155-pmic-overlay.dtsi +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -9,6 +9,7 @@ pm8150_1_clkdiv: &pm8150_clkdiv { }; pm8150_1_rtc: &pm8150_rtc { + disable-alarm-wakeup; }; pm8150_1_gpios: &pm8150_gpios { diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi index facbca2ecc34..9d970a762df4 100644 --- a/qcom/sa8195-pmic.dtsi +++ b/qcom/sa8195-pmic.dtsi @@ -292,3 +292,7 @@ }; }; }; + +&pm8195_1_rtc { + disable-alarm-wakeup; +}; From 8fdc99ec16ed4dbb196278e3433ac30e8c7fb344 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 31 Mar 2021 08:58:31 +0530 Subject: [PATCH 1216/1809] ARM: dts: msm: fix rtc entries Update the rtc node entries as required by the driver. Change-Id: Ic3dd1ce27a75f88ae60f2241671345878705f070 --- qcom/pm6155.dtsi | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/qcom/pm6155.dtsi b/qcom/pm6155.dtsi index cda605b20b87..1c198e4626fe 100644 --- a/qcom/pm6155.dtsi +++ b/qcom/pm6155.dtsi @@ -61,18 +61,7 @@ pm6155_1_rtc: qcom,pm6155_1_rtc { compatible = "qcom,pm8941-rtc"; - #address-cells = <1>; - #size-cells = <1>; - qcom,qpnp-rtc-write = <0>; - qcom,qpnp-rtc-alarm-pwrup = <0>; - - qcom,pm6155_1_rtc_rw@6000 { - reg = <0x6000 0x100>; - }; - qcom,pm6155_1_rtc_alarm@6100 { - reg = <0x6100 0x100>; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; pm6155_1_gpios: pinctrl@c000 { From e03ab21d38d15a79ecb21b69ca7d17ade2f4bfa6 Mon Sep 17 00:00:00 2001 From: Cong Tang Date: Mon, 5 Apr 2021 11:02:50 -0400 Subject: [PATCH 1217/1809] ARM: dts: msm: Support new TDM interfaces for Automotive Enable additional Senary and Septenary and HSIF0/1/2 TDM interfaces for Automotive. Change-Id: I6c7f43fd9a59abbe9393af0f4321fd67f58fb378 --- qcom/direwolf-vm-audio.dtsi | 704 +++++++++++++++++++++++++++++++++++- qcom/msm-audio-lpass.dtsi | 152 ++++++++ 2 files changed, 854 insertions(+), 2 deletions(-) diff --git a/qcom/direwolf-vm-audio.dtsi b/qcom/direwolf-vm-audio.dtsi index 6cf9114fc14d..cc26d7d642c7 100644 --- a/qcom/direwolf-vm-audio.dtsi +++ b/qcom/direwolf-vm-audio.dtsi @@ -427,6 +427,626 @@ }; }; + tdm_sen_rx: qcom,msm-dai-tdm-sen-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37200>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36944 36946 36948 + 36950 36952 36954 36956 36958>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36944>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_1: qcom,msm-dai-q6-tdm-sen-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36946>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_2: qcom,msm-dai-q6-tdm-sen-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36948>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_3: qcom,msm-dai-q6-tdm-sen-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36950>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_4: qcom,msm-dai-q6-tdm-sen-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36952>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_5: qcom,msm-dai-q6-tdm-sen-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36954>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_6: qcom,msm-dai-q6-tdm-sen-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36956>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_7: qcom,msm-dai-q6-tdm-sen-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36958>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sen_tx: qcom,msm-dai-tdm-sen-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37201>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36945 36947 36949 + 36951 36953 36955 36957 36959>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36945>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_1: qcom,msm-dai-q6-tdm-sen-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36947>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_2: qcom,msm-dai-q6-tdm-sen-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36949>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_3: qcom,msm-dai-q6-tdm-sen-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36951>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_4: qcom,msm-dai-q6-tdm-sen-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36953>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_5: qcom,msm-dai-q6-tdm-sen-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36955>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_6: qcom,msm-dai-q6-tdm-sen-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36957>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_7: qcom,msm-dai-q6-tdm-sen-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36959>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sep_rx: qcom,msm-dai-tdm-sep-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37216>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36960 36962 36964 + 36966 36968 36970 36972 36974>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sep_tdm_rx_0: qcom,msm-dai-q6-tdm-sep-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36960>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_1: qcom,msm-dai-q6-tdm-sep-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36962>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_2: qcom,msm-dai-q6-tdm-sep-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36964>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_3: qcom,msm-dai-q6-tdm-sep-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36966>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_4: qcom,msm-dai-q6-tdm-sep-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36968>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_5: qcom,msm-dai-q6-tdm-sep-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36970>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_6: qcom,msm-dai-q6-tdm-sep-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36972>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_7: qcom,msm-dai-q6-tdm-sep-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36974>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sep_tx: qcom,msm-dai-tdm-sep-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37217>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36961 36963 36965 + 36967 36969 36971 36973 36975>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sep_tdm_tx_0: qcom,msm-dai-q6-tdm-sep-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36961>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_1: qcom,msm-dai-q6-tdm-sep-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36963>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_2: qcom,msm-dai-q6-tdm-sep-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36965>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_3: qcom,msm-dai-q6-tdm-sep-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36967>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_4: qcom,msm-dai-q6-tdm-sep-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36969>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_5: qcom,msm-dai-q6-tdm-sep-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36971>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_6: qcom,msm-dai-q6-tdm-sep-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36973>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_7: qcom,msm-dai-q6-tdm-sep-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36975>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_rx: qcom,msm-dai-tdm-hsif0-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37232>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36976 36978 36980 + 36982 36984 36986 36988 36990>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif0_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif0-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36976>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif0-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36978>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif0-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36980>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif0-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36982>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif0-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36984>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif0-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36986>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif0-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36988>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif0-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36990>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_tx: qcom,msm-dai-tdm-hsif0-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37233>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36977 36979 36981 + 36983 36985 36987 36989 36991>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif0_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif0-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36977>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif0-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36979>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif0-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36981>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif0-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36983>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif0-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36985>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif0-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36987>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif0-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36989>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif0-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36991>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_rx: qcom,msm-dai-tdm-hsif1-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37248>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36992 36994 36996 + 36998 37000 37002 37004 37006>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif1_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif1-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36992>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif1-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36994>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif1-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36996>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif1-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36998>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif1-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37000>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif1-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37002>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif1-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37004>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif1-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37006>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_tx: qcom,msm-dai-tdm-hsif1-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37249>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36993 36995 36997 + 36999 37001 37003 37005 37007>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif1_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif1-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36993>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif1-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36995>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif1-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36997>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif1-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36999>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif1-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37001>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif1-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37003>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif1-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37005>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif1-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37007>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_rx: qcom,msm-dai-tdm-hsif2-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37264>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <37008 37010 37012 + 37014 37016 37018 37020 37022>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif2_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif2-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37008>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif2-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37010>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif2-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37012>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif2-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37014>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif2-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37016>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif2-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37018>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif2-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37020>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif2-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37022>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_tx: qcom,msm-dai-tdm-hsif2-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37265>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <37009 37011 37013 + 37015 37017 37019 37021 37023>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif2_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif2-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37009>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif2-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37011>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif2-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37013>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif2-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37015>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif2-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37017>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif2-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37019>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif2-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37021>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif2-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37023>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + qcom,msm-dai-q6 { compatible = "qcom,msm-dai-q6"; @@ -503,7 +1123,47 @@ <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, - <&dai_quin_tdm_tx_7>; + <&dai_quin_tdm_tx_7>, <&dai_sen_tdm_rx_0>, + <&dai_sen_tdm_rx_1>, <&dai_sen_tdm_rx_2>, + <&dai_sen_tdm_rx_3>, <&dai_sen_tdm_rx_4>, + <&dai_sen_tdm_rx_5>, <&dai_sen_tdm_rx_6>, + <&dai_sen_tdm_rx_7>, <&dai_sen_tdm_tx_0>, + <&dai_sen_tdm_tx_1>, <&dai_sen_tdm_tx_2>, + <&dai_sen_tdm_tx_3>, <&dai_sen_tdm_tx_4>, + <&dai_sen_tdm_tx_5>, <&dai_sen_tdm_tx_6>, + <&dai_sen_tdm_tx_7>, <&dai_sep_tdm_rx_0>, + <&dai_sep_tdm_rx_1>, <&dai_sep_tdm_rx_2>, + <&dai_sep_tdm_rx_3>, <&dai_sep_tdm_rx_4>, + <&dai_sep_tdm_rx_5>, <&dai_sep_tdm_rx_6>, + <&dai_sep_tdm_rx_7>, <&dai_sep_tdm_tx_0>, + <&dai_sep_tdm_tx_1>, <&dai_sep_tdm_tx_2>, + <&dai_sep_tdm_tx_3>, <&dai_sep_tdm_tx_4>, + <&dai_sep_tdm_tx_5>, <&dai_sep_tdm_tx_6>, + <&dai_sep_tdm_tx_7>, <&dai_hsif0_tdm_rx_0>, + <&dai_hsif0_tdm_rx_1>, <&dai_hsif0_tdm_rx_2>, + <&dai_hsif0_tdm_rx_3>, <&dai_hsif0_tdm_rx_4>, + <&dai_hsif0_tdm_rx_5>, <&dai_hsif0_tdm_rx_6>, + <&dai_hsif0_tdm_rx_7>, <&dai_hsif0_tdm_tx_0>, + <&dai_hsif0_tdm_tx_1>, <&dai_hsif0_tdm_tx_2>, + <&dai_hsif0_tdm_tx_3>, <&dai_hsif0_tdm_tx_4>, + <&dai_hsif0_tdm_tx_5>, <&dai_hsif0_tdm_tx_6>, + <&dai_hsif1_tdm_tx_7>, <&dai_hsif1_tdm_rx_0>, + <&dai_hsif1_tdm_rx_1>, <&dai_hsif1_tdm_rx_2>, + <&dai_hsif1_tdm_rx_3>, <&dai_hsif1_tdm_rx_4>, + <&dai_hsif1_tdm_rx_5>, <&dai_hsif1_tdm_rx_6>, + <&dai_hsif1_tdm_rx_7>, <&dai_hsif1_tdm_tx_0>, + <&dai_hsif1_tdm_tx_1>, <&dai_hsif1_tdm_tx_2>, + <&dai_hsif1_tdm_tx_3>, <&dai_hsif1_tdm_tx_4>, + <&dai_hsif1_tdm_tx_5>, <&dai_hsif1_tdm_tx_6>, + <&dai_hsif1_tdm_tx_7>, <&dai_hsif2_tdm_rx_0>, + <&dai_hsif2_tdm_rx_1>, <&dai_hsif2_tdm_rx_2>, + <&dai_hsif2_tdm_rx_3>, <&dai_hsif2_tdm_rx_4>, + <&dai_hsif2_tdm_rx_5>, <&dai_hsif2_tdm_rx_6>, + <&dai_hsif2_tdm_rx_7>, <&dai_hsif2_tdm_tx_0>, + <&dai_hsif2_tdm_tx_1>, <&dai_hsif2_tdm_tx_2>, + <&dai_hsif2_tdm_tx_3>, <&dai_hsif2_tdm_tx_4>, + <&dai_hsif2_tdm_tx_5>, <&dai_hsif2_tdm_tx_6>, + <&dai_hsif2_tdm_tx_7>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", @@ -539,7 +1199,47 @@ "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", - "msm-dai-q6-tdm.36943"; + "msm-dai-q6-tdm.36943", "msm-dai-q6-tdm.36944", + "msm-dai-q6-tdm.36946", "msm-dai-q6-tdm.36948", + "msm-dai-q6-tdm.36950", "msm-dai-q6-tdm.36952", + "msm-dai-q6-tdm.36954", "msm-dai-q6-tdm.36956", + "msm-dai-q6-tdm.36958", "msm-dai-q6-tdm.36945", + "msm-dai-q6-tdm.36947", "msm-dai-q6-tdm.36949", + "msm-dai-q6-tdm.36951", "msm-dai-q6-tdm.36953", + "msm-dai-q6-tdm.36955", "msm-dai-q6-tdm.36957", + "msm-dai-q6-tdm.36959", "msm-dai-q6-tdm.36960", + "msm-dai-q6-tdm.36962", "msm-dai-q6-tdm.36964", + "msm-dai-q6-tdm.36966", "msm-dai-q6-tdm.36968", + "msm-dai-q6-tdm.36970", "msm-dai-q6-tdm.36972", + "msm-dai-q6-tdm.36974", "msm-dai-q6-tdm.36961", + "msm-dai-q6-tdm.36963", "msm-dai-q6-tdm.36965", + "msm-dai-q6-tdm.36967", "msm-dai-q6-tdm.36969", + "msm-dai-q6-tdm.36971", "msm-dai-q6-tdm.36973", + "msm-dai-q6-tdm.36975", "msm-dai-q6-tdm.36976", + "msm-dai-q6-tdm.36978", "msm-dai-q6-tdm.36980", + "msm-dai-q6-tdm.36982", "msm-dai-q6-tdm.36984", + "msm-dai-q6-tdm.36986", "msm-dai-q6-tdm.36988", + "msm-dai-q6-tdm.36990", "msm-dai-q6-tdm.36977", + "msm-dai-q6-tdm.36979", "msm-dai-q6-tdm.36981", + "msm-dai-q6-tdm.36983", "msm-dai-q6-tdm.36985", + "msm-dai-q6-tdm.36987", "msm-dai-q6-tdm.36989", + "msm-dai-q6-tdm.36991", "msm-dai-q6-tdm.36992", + "msm-dai-q6-tdm.36994", "msm-dai-q6-tdm.36996", + "msm-dai-q6-tdm.36998", "msm-dai-q6-tdm.37000", + "msm-dai-q6-tdm.37002", "msm-dai-q6-tdm.37004", + "msm-dai-q6-tdm.37006", "msm-dai-q6-tdm.36993", + "msm-dai-q6-tdm.36995", "msm-dai-q6-tdm.36997", + "msm-dai-q6-tdm.36999", "msm-dai-q6-tdm.37001", + "msm-dai-q6-tdm.37003", "msm-dai-q6-tdm.37005", + "msm-dai-q6-tdm.37007", "msm-dai-q6-tdm.37008", + "msm-dai-q6-tdm.37010", "msm-dai-q6-tdm.37012", + "msm-dai-q6-tdm.37014", "msm-dai-q6-tdm.37016", + "msm-dai-q6-tdm.37018", "msm-dai-q6-tdm.37020", + "msm-dai-q6-tdm.37022", "msm-dai-q6-tdm.37009", + "msm-dai-q6-tdm.37011", "msm-dai-q6-tdm.37013", + "msm-dai-q6-tdm.37015", "msm-dai-q6-tdm.37017", + "msm-dai-q6-tdm.37019", "msm-dai-q6-tdm.37021", + "msm-dai-q6-tdm.37023"; asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; diff --git a/qcom/msm-audio-lpass.dtsi b/qcom/msm-audio-lpass.dtsi index d3de12166ce2..2b4eb0ef2c15 100644 --- a/qcom/msm-audio-lpass.dtsi +++ b/qcom/msm-audio-lpass.dtsi @@ -698,6 +698,158 @@ }; }; + tdm_sep_rx: qcom,msm-dai-tdm-sep-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37216>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36960>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sep_tdm_rx_0: qcom,msm-dai-q6-tdm-sep-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36960>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sep_tx: qcom,msm-dai-tdm-sep-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37217>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36961>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sep_tdm_tx_0: qcom,msm-dai-q6-tdm-sep-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36961>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_rx: qcom,msm-dai-tdm-hsif0-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37232>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36976>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif0_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif0-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36976>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_tx: qcom,msm-dai-tdm-hsif0-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37231>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36977>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif0_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif0-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36977>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_rx: qcom,msm-dai-tdm-hsif1-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37248>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36992>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif1_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif1-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36992>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_tx: qcom,msm-dai-tdm-hsif1-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37249>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36993>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif1_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif1-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36993>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_rx: qcom,msm-dai-tdm-hsif2-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37264>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <37008>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif2_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif2-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37008>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_tx: qcom,msm-dai-tdm-hsif2-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37265>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <37009>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_hsif2_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif2-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37009>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx { compatible = "qcom,msm-dai-q6-spdif"; qcom,msm-dai-q6-dev-id = <20480>; From 98a4ca8732d16ff8b1826a023a9f74e3b8bb6cea Mon Sep 17 00:00:00 2001 From: Shilun Wan Date: Thu, 25 Mar 2021 18:22:29 +0800 Subject: [PATCH 1218/1809] ARM: dts: msm: include direwolf-vm-lv-display.dtsi Including the direwolf-vm-lv-display.dtsi that adds four display sde-kms-hyp nodes for multi cards case. Change-Id: Ifbb516ca015818a63e171829f796299e6ed4567a --- qcom/direwolf-vm-lv.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi index 9e05ed049c14..16ae40ac4d92 100644 --- a/qcom/direwolf-vm-lv.dtsi +++ b/qcom/direwolf-vm-lv.dtsi @@ -8,3 +8,5 @@ label = "pmem_shared_mem"; }; }; + +#include "display/direwolf-vm-lv-display.dtsi" From a95ab40a0fa2508d294159c8f1503031eb5af34e Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Fri, 2 Apr 2021 15:02:52 +0530 Subject: [PATCH 1219/1809] ARM: dts: msm: Add direwolf QUPv3 spi, i2c and console nodes Add QUPv3 spi, i2c and console nodes for direwolf. Change-Id: I84fec5c3a3a39c6762920208a019b5f8b3df6a2c --- qcom/direwolf-pinctrl.dtsi | 1581 +++++++++++++++++++++++++++++++++++- qcom/direwolf-qupv3.dtsi | 996 +++++++++++++++++++++++ 2 files changed, 2576 insertions(+), 1 deletion(-) create mode 100644 qcom/direwolf-qupv3.dtsi diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi index 8b7b9bd9baa8..e3fb955590ac 100644 --- a/qcom/direwolf-pinctrl.dtsi +++ b/qcom/direwolf-pinctrl.dtsi @@ -1 +1,1580 @@ -&tlmm { }; +&tlmm { + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio135", "gpio136"; + function = "qup0"; + }; + + config { + pins = "gpio135", "gpio136"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio135", "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio136"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio135", "gpio136", + "gpio137", "gpio138"; + function = "qup0"; + }; + + config { + pins = "gpio135", "gpio136", + "gpio137", "gpio138"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio135", "gpio136", + "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio136", + "gpio137", "gpio138"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio158", "gpio159"; + function = "qup1"; + }; + + config { + pins = "gpio158", "gpio159"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio158", "gpio159"; + function = "gpio"; + }; + + config { + pins = "gpio158", "gpio159"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio158", "gpio159", + "gpio160", "gpio161"; + function = "qup1"; + }; + + config { + pins = "gpio158", "gpio159", + "gpio160", "gpio161"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio158", "gpio159", + "gpio160", "gpio161"; + function = "gpio"; + }; + + config { + pins = "gpio158", "gpio159", + "gpio160", "gpio161"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio121", "gpio122"; + function = "qup2"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio121", "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio121", "gpio122", + "gpio123", "gpio124"; + function = "qup2"; + }; + + config { + pins = "gpio121", "gpio122", + "gpio123", "gpio124"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio121", "gpio122", + "gpio123", "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122", + "gpio123", "gpio124"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_4uart_pins: qupv3_se2_4uart_pins { + qupv3_se2_default_cts: + qupv3_se2_default_cts { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_default_rtsrx: + qupv3_se2_default_rtsrx { + mux { + pins = "gpio122", "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio122", "gpio124"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_default_tx: + qupv3_se2_default_tx { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_ctsrx: qupv3_se2_ctsrx { + mux { + pins = "gpio121", "gpio124"; + function = "qup2"; + }; + + config { + pins = "gpio121", "gpio124"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_rts: qupv3_se2_rts { + mux { + pins = "gpio122"; + function = "qup2"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_tx: qupv3_se2_tx { + mux { + pins = "gpio123"; + function = "qup2"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio137", "gpio138"; + function = "qup3"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio137", "gpio138", + "gpio135", "gpio136"; + function = "qup3"; + }; + + config { + pins = "gpio137", "gpio138", + "gpio135", "gpio136"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio137", "gpio138", + "gpio135", "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138", + "gpio135", "gpio136"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio171", "gpio172"; + function = "qup4"; + }; + + config { + pins = "gpio171", "gpio172"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio171", "gpio172"; + function = "gpio"; + }; + + config { + pins = "gpio171", "gpio172"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio171", "gpio172", + "gpio173", "gpio174"; + function = "qup4"; + }; + + config { + pins = "gpio171", "gpio172", + "gpio173", "gpio174"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio171", "gpio172", + "gpio173", "gpio174"; + function = "gpio"; + }; + + config { + pins = "gpio171", "gpio172", + "gpio173", "gpio174"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio111", "gpio112"; + function = "qup5"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio111", "gpio112"; + function = "gpio"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio111", "gpio112", + "gpio145", "gpio146"; + function = "qup5"; + }; + + config { + pins = "gpio111", "gpio112", + "gpio145", "gpio146"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio111", "gpio112", + "gpio145", "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio111", "gpio112", + "gpio145", "gpio146"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio154", "gpio155"; + function = "qup6"; + }; + + config { + pins = "gpio154", "gpio155"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio154", "gpio155"; + function = "gpio"; + }; + + config { + pins = "gpio154", "gpio155"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio154", "gpio155", + "gpio156", "gpio157"; + function = "qup6"; + }; + + config { + pins = "gpio154", "gpio155", + "gpio156", "gpio157"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio154", "gpio155", + "gpio156", "gpio157"; + function = "gpio"; + }; + + config { + pins = "gpio154", "gpio155", + "gpio156", "gpio157"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio128", "gpio129"; + function = "qup7"; + }; + + config { + pins = "gpio128", "gpio129"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio128", "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio128", "gpio129"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio128", "gpio129", + "gpio125", "gpio126"; + function = "qup7"; + }; + + config { + pins = "gpio128", "gpio129", + "gpio125", "gpio126"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio128", "gpio129", + "gpio125", "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio128", "gpio129", + "gpio125", "gpio126"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup8"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio43", "gpio44", + "gpio45", "gpio46"; + function = "qup8"; + }; + + config { + pins = "gpio43", "gpio44", + "gpio45", "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio43", "gpio44", + "gpio45", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", + "gpio45", "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio41", "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio41", "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "qup9"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio18", "gpio19"; + function = "qup11"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + function = "qup11"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup12"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup12"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio26", "gpio27"; + function = "qup13"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "qup13"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se13_2uart_pins: qupv3_se13_2uart_pins { + qupv3_se13_2uart_active: qupv3_se13_2uart_active { + mux { + pins = "gpio28", "gpio29"; + function = "qup13"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup14"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup14"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup15"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup15"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se17_2uart_pins: qupv3_se17_2uart_pins { + qupv3_se17_2uart_active: qupv3_se17_2uart_active { + mux { + pins = "gpio63", "gpio64"; + function = "qup17"; + }; + + config { + pins = "gpio63", "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_2uart_sleep: qupv3_se17_2uart_sleep { + mux { + pins = "gpio63", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio63", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio70", "gpio71"; + function = "qup16"; + }; + + config { + pins = "gpio70", "gpio71"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio70", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio70", "gpio71"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio70", "gpio71", + "gpio72", "gpio73"; + function = "qup16"; + }; + + config { + pins = "gpio70", "gpio71", + "gpio72", "gpio73"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio70", "gpio71", + "gpio72", "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio70", "gpio71", + "gpio72", "gpio73"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio61", "gpio62"; + function = "qup17"; + }; + + config { + pins = "gpio61", "gpio62"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio61", "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio61", "gpio62"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio61", "gpio62", + "gpio63", "gpio64"; + function = "qup17"; + }; + + config { + pins = "gpio61", "gpio62", + "gpio63", "gpio64"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio61", "gpio62", + "gpio63", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio61", "gpio62", + "gpio63", "gpio64"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio66", "gpio67"; + function = "qup18"; + }; + + config { + pins = "gpio66", "gpio67"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio66", "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio66", "gpio67"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio66", "gpio67", + "gpio68", "gpio69"; + function = "qup18"; + }; + + config { + pins = "gpio66", "gpio67", + "gpio68", "gpio69"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio66", "gpio67", + "gpio68", "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio66", "gpio67", + "gpio68", "gpio69"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup19"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio55", "gpio56", + "gpio57", "gpio58"; + function = "qup19"; + }; + + config { + pins = "gpio55", "gpio56", + "gpio57", "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio55", "gpio56", + "gpio57", "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", + "gpio57", "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { + qupv3_se20_i2c_active: qupv3_se20_i2c_active { + mux { + pins = "gpio87", "gpio88"; + function = "qup20"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { + mux { + pins = "gpio87", "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se20_spi_pins: qupv3_se20_spi_pins { + qupv3_se20_spi_active: qupv3_se20_spi_active { + mux { + pins = "gpio87", "gpio88", + "gpio89", "gpio90"; + function = "qup20"; + }; + + config { + pins = "gpio87", "gpio88", + "gpio89", "gpio90"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se20_spi_sleep: qupv3_se20_spi_sleep { + mux { + pins = "gpio87", "gpio88", + "gpio89", "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio88", + "gpio89", "gpio90"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { + qupv3_se21_i2c_active: qupv3_se21_i2c_active { + mux { + pins = "gpio81", "gpio82"; + function = "qup21"; + }; + + config { + pins = "gpio81", "gpio82"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { + mux { + pins = "gpio81", "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio82"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se21_spi_pins: qupv3_se21_spi_pins { + qupv3_se21_spi_active: qupv3_se21_spi_active { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "qup21"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se22_i2c_pins: qupv3_se22_i2c_pins { + qupv3_se22_i2c_active: qupv3_se22_i2c_active { + mux { + pins = "gpio85", "gpio85"; + function = "qup22"; + }; + + config { + pins = "gpio85", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep { + mux { + pins = "gpio85", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se22_spi_pins: qupv3_se22_spi_pins { + qupv3_se22_spi_active: qupv3_se22_spi_active { + mux { + pins = "gpio85", "gpio86", + "gpio83", "gpio84"; + function = "qup22"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se22_spi_sleep: qupv3_se22_spi_sleep { + mux { + pins = "gpio85", "gpio86", + "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se23_i2c_pins: qupv3_se23_i2c_pins { + qupv3_se23_i2c_active: qupv3_se23_i2c_active { + mux { + pins = "gpio59", "gpio60"; + function = "qup23"; + }; + + config { + pins = "gpio59", "gpio60"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep { + mux { + pins = "gpio59", "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio59", "gpio60"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se23_spi_pins: qupv3_se23_spi_pins { + qupv3_se23_spi_active: qupv3_se23_spi_active { + mux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + function = "qup23"; + }; + + config { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se23_spi_sleep: qupv3_se23_spi_sleep { + mux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + drive-strength = <6>; + bias-disable; + }; + }; + }; +}; diff --git a/qcom/direwolf-qupv3.dtsi b/qcom/direwolf-qupv3.dtsi new file mode 100644 index 000000000000..a0274605c38f --- /dev/null +++ b/qcom/direwolf-qupv3.dtsi @@ -0,0 +1,996 @@ +#include + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + * Qup1 0: SE 8 + * Qup1 1: SE 9 + * Qup1 2: SE 10 + * Qup1 3: SE 11 + * Qup1 4: SE 12 + * Qup1 5: SE 13 + * Qup1 6: SE 14 + * Qup1 7: SE 15 + * Qup2 0: SE 16 + * Qup2 1: SE 17 + * Qup2 2: SE 18 + * Qup2 3: SE 19 + * Qup2 4: SE 20 + * Qup2 5: SE 21 + * Qup2 6: SE 22 + * Qup2 7: SE 23 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x9c0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x563 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x83 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0xa3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se17_2uart: qcom,qup_uart@884000 { + compatible = "qcom,msm-geni-console"; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_2uart_active>; + pinctrl-1 = <&qupv3_se17_2uart_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se20_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se20_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_spi_active>; + pinctrl-1 = <&qupv3_se20_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se21_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se23_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se23_i2c_active>; + pinctrl-1 = <&qupv3_se23_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se23_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se23_spi_active>; + pinctrl-1 = <&qupv3_se23_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* 4-wire HSUART Instance */ + qupv3_se2_4uart: qcom,qup_uart@988000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x988000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 124 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se2_default_cts>, + <&qupv3_se2_default_rtsrx>, <&qupv3_se2_default_tx>; + pinctrl-1 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>; + pinctrl-2 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@994000 { + compatible = "qcom,spi-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@99c000 { + compatible = "qcom,spi-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* 2-Wire HSUART Instance */ + qupv3_se13_2uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_2uart_active>; + pinctrl-1 = <&qupv3_se13_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; +}; From aed4c6ee45b06a511ef02f45cde8f4b2985ed75f Mon Sep 17 00:00:00 2001 From: Jayadev K Date: Mon, 29 Mar 2021 23:23:35 +0530 Subject: [PATCH 1220/1809] ARM: dts: qcom: Add HS-I2S device tree support on SA8155 Adding documentation and device nodes for HS-I2S interface. Change-Id: I53600f72f4a22aecaabaa69d61a08b37fa219c85 --- bindings/sound/qcom,hsi2s.txt | 187 ++++++++++++++++++++++++++++++++++ qcom/sa8155.dtsi | 101 ++++++++++++++++++ 2 files changed, 288 insertions(+) create mode 100644 bindings/sound/qcom,hsi2s.txt diff --git a/bindings/sound/qcom,hsi2s.txt b/bindings/sound/qcom,hsi2s.txt new file mode 100644 index 000000000000..fcb969f9e61c --- /dev/null +++ b/bindings/sound/qcom,hsi2s.txt @@ -0,0 +1,187 @@ +Qualcomm Technologies, Inc. High Speed I2S Interface + +* HS-I2S generic node + +Required properties: + + - compatible : Should include "qcom,hsi2s" + Should include target specific compatible field + "qcom,sa6155-hsi2s" for SA6155 + "qcom,sa8155-hsi2s" for SA8155 + "qcom,sa8195-hsi2s" for SA8195 + - number-of-interfaces : Denotes the number of HS-I2S interfaces + - reg : Specifies the base physical address and the size of the HS-I2S + register space + - reg-names : "lpa_if" - string to identify the HS-I2S base register + - interrupts : Interrupt number used by this interface + - clocks : Core clocks used by this interface + - clock-names : Clock names for each core clock + - iommus: The phandle and stream IDs for the SMMU used by this root + - qcom,iommu-dma-addr-pool: Specifies the start address and size of iova space + +Optional properties: + + - number-of-rate-detectors : Number of rate detectors to enable + 0 - Doesn't enable rate detectors + 1 - Enables primary rate detector + 2 - Enables both primary and secondary + rate detectors + - rate-detector-interfaces : Specifies the minor number of the interfaces + to have rate detection enabled + +* HS-I2S interface nodes + +Required properties: + + - compatible : Should be "qcom,hsi2s-interface" + - minor-number : Minor number of the character device interface + Should be 0 for HS0 interface + Should be 1 for HS1 interface + Should be 2 for HS2 interface + - clocks : Interface clock used by this interface + - clock-names : Clock name for the interface clock + - pinctrl-names : Pinctrl state names for each pin group configuration + - pinctrl-x : Defines pinctrl state for each pin group + - bit-clock-hz : Default bit clock frequency in hertz + - data-buffer-ms : Default periodic interrupt interval in milliseconds + +Optional properties: + + - bit-depth : Bit depth of the I2S data + Default - 32 + - spkr-channel-count : Number of speaker channels + Default - 2 + - mic-channel-count : Number of mic channels + Default - 2 + - pcm-rate : Number of bit clocks per PCM frame + 0 - ENUM_8 + 1 - ENUM_16 + 2 - ENUM_32 (Default) + 3 - ENUM_64 + 4 - ENUM_128 + 5 - ENUM_256 + - pcm-sync-src : Specifies whether the PCM block uses internal or + external sync + 0 - External (Default) + 1 - Internal + - aux-mode : Specifies the type of sync expected/generated by the + PCM block. + 0 - PCM (Short sync) (Default) + 1 - Aux PCM (Long sync) + - rpcm-width : Number of bits per receive slot + 0 - 8 bits + 1 - 16 bits (Default) + - tpcm-width : Number of bits per transmit slot + 0 - 8 bits + 1 - 16 bits (Default) + - enable-tdm : Specifies whether TDM is enabled by default + 0 - Disable TDM + 1 - Enable TDM (Default) + - tdm-rate : Number of bit clocks per TDM frame + Maximum permissible value is 512 + Default - 32 + - tdm-rpcm-width : Number of bits per receive slot in TDM + Maximum permissible value is 32 + Default - 16 + - tdm-tpcm-width : Number of bits per transmit slot in TDM + Maximum permissible value is 32 + Default - 16 + - tdm-sync-delay : Specifies the data delay relative to sync pulse + 0 - First data appears two cycles after frame pulse + 1 - First data appears one cycle after frame pulse + 2 - First data and frame pulse occur on the same cycle + Default - 2 + - tdm-inv-sync : Specifies whether the frame sync has to be inverted + in long sync(Aux PCM) mode + 0 - Do not invert frame sync (Default) + 1 - Invert frame sync + - pcm-lane-config : Specifies the PCM data lane configuration + 0 - Single lane + D0 - MIC + D1 - SPEAKER + 1 - Multi lane Rx (Default) + D0 - MIC + D1 - MIC + 2 - Multi lane Tx + D0 - SPEAKER + D1 - SPEAKER + +Example: + +hsi2s: qcom,hsi2s { + compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <2>; + reg = <0x1B40000 0x28000>; + reg-names = "lpa_if"; + interrupts = ; + clocks = <&clock_gcc GCC_SDR_CORE_CLK>, + <&clock_gcc GCC_SDR_WR0_MEM_CLK>, + <&clock_gcc GCC_SDR_WR1_MEM_CLK>, + <&clock_gcc GCC_SDR_WR2_MEM_CLK>, + <&clock_gcc GCC_SDR_CSR_HCLK>; + clock-names = "core_clk", "wr0_mem_clk", + "wr1_mem_clk", "wr2_mem_clk", + "csr_hclk"; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x035C 0x1>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active + &hs0_i2s_data1_active>; + pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep + &hs0_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>; + clock-names = "pri_mi2s_clk"; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>; + clock-names = "sec_mi2s_clk"; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 9aea5b2b4036..72f8f1fffd87 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -203,6 +203,107 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <3>; + reg = <0x172C0000 0x28000>, + <0x17080000 0xE000>; + reg-names = "lpa_if", "lpass_tcsr"; + interrupts = ; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x1B5C 0x1>, + <&apps_smmu 0x1B5E 0x0>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active + &hs1_i2s_ws_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep + &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active + &hs2_i2s_ws_active &hs2_i2s_data0_active + &hs2_i2s_data1_active>; + pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep + &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep + &hs2_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr2: qcom,hs2_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active + &hs3_i2s_ws_active &hs3_i2s_data0_active + &hs3_i2s_data1_active>; + pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep + &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep + &hs3_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + }; }; &usb2_phy0 { From 939babb28ebe78c3c6df69e922f4afe8fd80884b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 29 Mar 2021 22:09:29 +0530 Subject: [PATCH 1221/1809] ARM: dts: qcom: Add modem TSENS thermal zone mitigations for HOLI Add modem junction temperature thermal zone mitigation rules based on latest recommendation for HOLI. Change-Id: Ifcb155674e8ca437a21d09f6ac29cabea04c9357 --- qcom/holi-thermal.dtsi | 172 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index c98479d3b71a..3055d38c3777 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -121,6 +121,178 @@ }; &thermal_zones { + mdm-core0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 6>; + trips { + mdmss0_trip0: mdmss0-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip1: mdmss0-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss0_trip2: mdmss0-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss0_cdev0 { + trip = <&mdmss0_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss0_cdev1 { + trip = <&mdmss0_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss0_cdev2 { + trip = <&mdmss0_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-core1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 7>; + trips { + mdmss1_trip0: mdmss1-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip1: mdmss1-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss1_trip2: mdmss1-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss1_cdev0 { + trip = <&mdmss1_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss1_cdev1 { + trip = <&mdmss1_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss1_cdev2 { + trip = <&mdmss1_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-vec-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 8>; + trips { + mdmss2_trip0: mdmss2-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip1: mdmss2-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss2_trip2: mdmss2-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss2_cdev0 { + trip = <&mdmss2_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss2_cdev1 { + trip = <&mdmss2_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss2_cdev2 { + trip = <&mdmss2_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-scl-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 9>; + trips { + mdmss3_trip0: mdmss3-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip1: mdmss3-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + mdmss3_trip2: mdmss3-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + mdmss3_cdev0 { + trip = <&mdmss3_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + mdmss3_cdev1 { + trip = <&mdmss3_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + mdmss3_cdev2 { + trip = <&mdmss3_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + mapss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; From 197f089a1162aba13867a06b974e8244f88fd1f1 Mon Sep 17 00:00:00 2001 From: Kasin Li Date: Mon, 8 Mar 2021 17:37:48 +0800 Subject: [PATCH 1222/1809] ARM: dts: msm: Enable hgsl support on direwolf Doorbell is not enabled currently, support ifence only Change-Id: I2df4ddd847b9623b6146b62aa1554062bd1c4e1e --- qcom/direwolf-vm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 1c8d06446e43..a8b5b4383648 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -174,6 +174,13 @@ ; }; + msm_gpu_hyp: qcom,hgsl { + compatible = "qcom,hgsl"; + + /* TBD, complete doorbell */ + db-off = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,direwolf-pdc"; reg = <0xb220000 0x30000>; From 3cc900996b8da67bd5d64b01a0d79c498727b445 Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 9 Mar 2021 10:53:09 +0530 Subject: [PATCH 1223/1809] ARM: dts: msm: Add the rpmcc support for monaco Change the dummy rpmcc to real for Monaco. Change-Id: Ifa2c4d8c68edae217b8415f3329e8eb88bc45d2d --- qcom/monaco-rumi.dtsi | 10 ---------- qcom/monaco.dtsi | 19 +------------------ 2 files changed, 1 insertion(+), 28 deletions(-) diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 06eae741f70b..aa3e9f57a73b 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -1,5 +1,3 @@ -#include - &soc { timer { clock-frequency = <5000000>; @@ -15,12 +13,4 @@ }; -&gcc { - clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; -}; - -&cpufreq_hw { - clocks = <&bi_tcxo>, <&gcc GPLL0>; -}; - #include "monaco-stub-regulator.dtsi" diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 47415a453570..b753f2c41340 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -677,25 +677,8 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - rpmcc: qcom,rpmcc { - compatible = "qcom,dummycc"; - clock-output-names = "rpmcc_clocks"; + compatible = "qcom,rpmcc-monaco"; #clock-cells = <1>; #reset-cells = <1>; }; From d1dea92b8c6eeb8f9522619982179a252f8dec8b Mon Sep 17 00:00:00 2001 From: Biao Long Date: Tue, 6 Apr 2021 10:10:58 +0800 Subject: [PATCH 1224/1809] dt-bindings: Add opp table for ahb device Support opp table for ahb devices. Change-Id: If9dc6cb6cc62641c6e2ca2bd75395a688667ae58 --- qcom/sdxnightjar.dtsi | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 1238ce10e2af..fe54dae83f99 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -300,16 +300,21 @@ < 1286400 >; }; + ahb_bw_opp_table: ahb-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 19, 8); /* 144 MB/s */ + BW_OPP_ENTRY( 50, 8); /* 381 MB/s */ + BW_OPP_ENTRY( 100, 8); /* 762 MB/s */ + BW_OPP_ENTRY( 133, 8); /* 1014 MB/s */ + }; + ahb_clk: qcom,ahb-clk-src { compatible = "devfreq-simple-dev"; clocks = <&gcc APSS_AHB_CLK_SRC>; clock-names = "devfreq_clk"; governor = "powersave"; - freq-tbl-khz = - < 19200 >, - < 50000 >, - < 100000 >, - < 133330 >; + qcom,bus-width = <8>; + operating-points-v2 = <&ahb_bw_opp_table>; }; cpubw: qcom,cpubw { @@ -339,10 +344,10 @@ cpuahb-cpufreq { target-dev = <&ahb_clk>; cpu-to-dev-map = - < 200000 19200 >, - < 384000 50000 >, - < 787200 100000 >, - < 1286400 133330 >; + < 200000 144 >, + < 384000 381 >, + < 787200 762 >, + < 1286400 1014 >; }; }; From 7ad8de7b948353566004c9757b6ed5fc42b75943 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 2 Apr 2021 15:14:57 +0530 Subject: [PATCH 1225/1809] ARM: dts: qcom: Enable CPU frequency cooling device for YUPIK Add cooling-cell property to enable CPU frequency cooling devices for YUPIK. Change-Id: I5c91c1cbe11552466c08013968f46d568f6b9d42 --- qcom/yupik.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 748d3dfc222d..2d9075c89e2f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -77,6 +77,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -150,6 +151,7 @@ dynamic-power-coefficient = <520>; qcom,freq-domain = <&cpufreq_hw 1 4>; next-level-cache = <&L2_4>; + #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -201,6 +203,7 @@ dynamic-power-coefficient = <552>; qcom,freq-domain = <&cpufreq_hw 2 4>; next-level-cache = <&L2_7>; + #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; From ccf6e0c4f2f38176180ccd884480d8274be51bb3 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Tue, 6 Apr 2021 16:31:43 +0530 Subject: [PATCH 1226/1809] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit 6b84a80dde1ab6801f606e9f81cea291ef462da7. Commit 6b84a80dde1ab6 ("ARM: dts: msm: Use PCIe_MSI for Shima") revert the synopsys MSI controller to GIC interrupt controller. We are facing an issue where wake MSI is enabled after DRV suspend by the time PCIe clocks are off and also there is an interrupt latency with SNPS controller. Change-Id: Iaf47c2c8b9c188183d6ad0e72bb7d05b0b7262b7 --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 679206758308..4f9b6aef51ab 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -204,15 +204,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From d4ac95c1bb65e5812d724c05deab738c2055bba0 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 6 Apr 2021 17:46:09 +0530 Subject: [PATCH 1227/1809] ARM: dts: msm: Enable USB2 functionality for yupik IOT IDP Enable USB2 functionality for 2nd USB port on Yupik IOT IDP platform. And also set default mode to none for USB2 port as there is no provision for dynamic detection of USB modes. Change-Id: Iaf311e6f6842e3f6062659c017d49704bb5a08a4 --- qcom/yupik-iot-idp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 6f7484cd3458..6b2bdff2033c 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -26,3 +26,12 @@ &pcie1_msi { status = "ok"; }; + +&usb1 { + qcom,default-mode-none; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; From fbe8699202b5fcc79871677120c9411688ee0a99 Mon Sep 17 00:00:00 2001 From: Ramachandran Venkataramani Date: Mon, 5 Apr 2021 19:23:58 -0700 Subject: [PATCH 1228/1809] ARM: dts: msm: Add support for USB on Direwolf GVM Add USB device tree nodes for Direwolf GVM. Change-Id: If89a47dd639382f00c8d85bd9d0592d5c3ecfbb1 --- qcom/direwolf-vm-la.dtsi | 8 ++ qcom/direwolf-vm-lv.dtsi | 8 ++ qcom/direwolf-vm-usb.dtsi | 168 ++++++++++++++++++++++++++++++++++++++ qcom/direwolf-vm.dtsi | 2 + qcom/quin-vm-common.dtsi | 1 + 5 files changed, 187 insertions(+) create mode 100644 qcom/direwolf-vm-usb.dtsi diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi index 10aa218eda14..9eca2745a0cb 100644 --- a/qcom/direwolf-vm-la.dtsi +++ b/qcom/direwolf-vm-la.dtsi @@ -4,3 +4,11 @@ label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "okay"; +}; + +&usb2_phy0 { + status = "okay"; +}; diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi index 16ae40ac4d92..788736b4f55a 100644 --- a/qcom/direwolf-vm-lv.dtsi +++ b/qcom/direwolf-vm-lv.dtsi @@ -10,3 +10,11 @@ }; #include "display/direwolf-vm-lv-display.dtsi" + +&usb0 { + status = "okay"; +}; + +&usb2_phy0 { + status = "okay"; +}; diff --git a/qcom/direwolf-vm-usb.dtsi b/qcom/direwolf-vm-usb.dtsi new file mode 100644 index 000000000000..c4251030f0f0 --- /dev/null +++ b/qcom/direwolf-vm-usb.dtsi @@ -0,0 +1,168 @@ +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0820 0x0>; + qcom,iommu-dma = "bypass"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + status = "disabled"; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e5000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x088e5000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L5A0>; + vdda18-supply = <&L7A0>; + vdda33-supply = <&L13A0>; + + qcom,vdd-voltage-level = <0 912000 912000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0860 0x0>; + qcom,iommu-dma = "bypass"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + qcom,default-mode-host; + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xd93c>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@8902000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x08902000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L1C0>; + vdda18-supply = <&L7C0>; + vdda33-supply = <&L2C0>; + + qcom,vdd-voltage-level = <0 912000 912000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 1c8d06446e43..6ad97dfcc8ec 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -1,4 +1,5 @@ #include +#include #include "quin-vm-common.dtsi" / { @@ -233,3 +234,4 @@ #include "direwolf-pinctrl.dtsi" #include "pm8540-vm.dtsi" #include "direwolf-vm-audio.dtsi" +#include "direwolf-vm-usb.dtsi" diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index ea2347e4cd1d..653363f9505b 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -1,4 +1,5 @@ #include +#include / { #address-cells = <2>; From e3545f19bb74795d78de13c5de9e5b8f0242da03 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Tue, 6 Apr 2021 17:58:50 -0700 Subject: [PATCH 1229/1809] ARM: dts: msm: Add SPI to support PCIe SNPS IRQ 1-7 for sdxlemur In order to support more than one Synopsys MSI group, add the SPIs for Synopsys IRQ 1-7 to PCIe interrupt table. Change-Id: I366b87d27a743b537b1b4cb1a44a05ed3785aa05 --- qcom/sdxlemur-pcie.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 9834159a1112..62b45985834f 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -279,7 +279,14 @@ msi-controller; reg = <0xa0000000 0x0>; interrupt-parent = <&intc>; - interrupts = ; + interrupts = , + , + , + , + , + , + , + ; qcom,snps; }; }; From e4c9d897e20bb6dc8b2739205b47211bcff534e4 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Fri, 26 Mar 2021 14:37:44 +0530 Subject: [PATCH 1230/1809] ARM: dts: msm: Add switch control GPIO for WLAN Add SW_CTRL GPIO TLMM 153 in the CNSS node for WLAN device. Change-Id: Ic07c565e85c30796def08d8c3dd3784ae65fafc7 --- bindings/cnss/cnss-wlan.txt | 1 + qcom/lahaina.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 05e7db9fd7f5..deb8508b9a8e 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -94,6 +94,7 @@ Optional properties: enable to resolve PMU power up issues. Provide BT GPIO using this config param. - qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention. + - qcom,sw-ctrl-gpio: Switch control GPIO for device power control - qcom,same-dt-multi-dev: Boolean property to decide whether it supports multiple WLAN devices using the same DT node without sub-nodes. diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 6700bdec8550..10768627ee74 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5386,6 +5386,7 @@ reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; qcom,bt-en-gpio = <&tlmm 65 0>; + qcom,sw-ctrl-gpio = <&tlmm 153 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From adf3725c93fec11933311803204b820477266e88 Mon Sep 17 00:00:00 2001 From: Feng Chen Date: Mon, 29 Mar 2021 19:27:31 +0530 Subject: [PATCH 1231/1809] ARM: dts: msm: STMMAC changes for SA6155 Enable fastmap for sa6155 for high t-put. Change-Id: I32052bd05c7a43fc582bf603a813de200f51a92c --- qcom/sa6155-adp-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index ba24c846e482..ff92a862d999 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -150,6 +150,7 @@ ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; }; From 384c83376610825b12a83e352eda60c38920bad6 Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 6 Apr 2021 20:41:47 +0530 Subject: [PATCH 1232/1809] ARM: dts: msm: Update the venus and vcodec gdsc for monaco Update the register space address for venus and vcodec gdsc for monaco. Change-Id: I59eed10b0b13dcbc3f62511b97dc29baa932801e --- qcom/monaco-gdsc.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi index f527f93bf3b1..dfa39a8cdaa4 100644 --- a/qcom/monaco-gdsc.dtsi +++ b/qcom/monaco-gdsc.dtsi @@ -14,16 +14,16 @@ status = "disabled"; }; - gcc_vcodec0_gdsc: qcom,gdsc@14580a8 { + gcc_vcodec0_gdsc: qcom,gdsc@14580ac { compatible = "qcom,gdsc"; - reg = <0x14580a8 0x4>; + reg = <0x14580ac 0x4>; regulator-name = "gcc_vcodec0_gdsc"; status = "disabled"; }; - gcc_venus_gdsc: qcom,gdsc@1458084 { + gcc_venus_gdsc: qcom,gdsc@1458088 { compatible = "qcom,gdsc"; - reg = <0x1458084 0x4>; + reg = <0x1458088 0x4>; regulator-name = "gcc_venus_gdsc"; status = "disabled"; }; From 2b24a12d99dd7efadd95529d57879a548342460c Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 6 Apr 2021 18:19:32 +0530 Subject: [PATCH 1233/1809] ARM: dts: msm: Add VBUS supply for USB2 port for Yupik IOT IDP Add required support to have VBUS supply enabled for USB2 port for Yupik IOT IDP platform. Change-Id: Ic541d6062ecf59b5f6c0ec9dbd5371b89fca54fc --- qcom/yupik-iot-idp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 6b2bdff2033c..45b0b4e4718f 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -27,7 +27,32 @@ status = "ok"; }; +&pm7325_gpios { + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio8"; + function = "normal"; + output-low; + power-source = <0>; /* 1.8V input supply */ + }; + }; +}; + +&soc { + usb2_vbus_boost_reg: usb2_vbus_boost_reg { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpios = <&pm7325_gpios 8 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; +}; + &usb1 { + vbus_dwc3-supply = <&usb2_vbus_boost_reg>; qcom,default-mode-none; status = "ok"; }; From 3c485089ffadba25a800d427c836c7ab9a870600 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Fri, 2 Apr 2021 16:31:25 +0530 Subject: [PATCH 1234/1809] ARM: dts: msm: Adding new DT entries for ETH bridging Addign new DT entries to check ETH bridging and BW monitor feature supported or not. Change-Id: I86b19134a3b0d16f2e648bff389f859c06a43699 --- bindings/platform/msm/ipa.txt | 5 +++++ qcom/yupik.dtsi | 2 ++ 2 files changed, 7 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 6939190e3d42..0fe273044913 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -137,6 +137,11 @@ memory allocation over a PCIe bridge rings read pointer should be read from the ddr. - qcom,max_num_smmu_cb: Total number of context banks used for the target +- qcom,eth-bridging-not-supported : Boolean context flag to indicate whether ETH bridging + is supported or not in this target. + +- qcom,bw-monitor-supported: Boolean context flag to indicate BW monitor feature support. + IPA pipe sub nodes (A2 static pipes configurations): -label: two labels are supported, a2-to-ipa and ipa-to-a2 which diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 748d3dfc222d..89d94df35bd0 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3745,6 +3745,8 @@ qcom,smmu-fast-map; qcom,use-64-bit-dma-mask; qcom,ipa-endp-delay-wa-v2; + qcom,eth-bridging-not-supported; + qcom,bw-monitor-supported; qcom,lan-rx-napi; qcom,tx-napi; qcom,wan-use-skb-page; From 39532106ba6d87593ca0e0b0d5564fcfc1401cd7 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Wed, 7 Apr 2021 14:18:54 -0700 Subject: [PATCH 1235/1809] ARM: dts: msm: Add qcom_gadget node for sdxlemur Add qcom_gadget node to enable early usb enumeration at boot time on sdxlemur. Change-Id: I6c39f30ff5bb05a4febe82f7081cfa9981e9e5e7 --- bindings/usb/qcom,usb-gadget.txt | 41 ++++++++++++++++++++++++++++ qcom/sdxlemur-usb.dtsi | 47 ++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 bindings/usb/qcom,usb-gadget.txt diff --git a/bindings/usb/qcom,usb-gadget.txt b/bindings/usb/qcom,usb-gadget.txt new file mode 100644 index 000000000000..19cca02e9176 --- /dev/null +++ b/bindings/usb/qcom,usb-gadget.txt @@ -0,0 +1,41 @@ +Qualcomm Technologies, Inc's USB Gadget + +Required properties: +- compatible: Should be "qcom,usb-gadget". +- qcom,vid: VendorId to be used by composite device. + +Required subnode properties: +- qcom,pid: ProductId to be used by composite device. +- qcom,composition: List of configurations where each is separated by '|'. + And each configuration has comma separated list of functions + specified as: .,.... +- qcom,bmAttributes: Config characteritics of composite device. + e.g. remote wakeup capability, self or bus powered. + +Optional properties: +- qcom,default-pid: ProductId to be used by composite device. +- qcom,class: Class of composite device. +- qcom,subclass: SubClass of composite device. +- qcom,protocol: Protocol of composite device. + +Example: + usb_gadget { + compatible = "qcom,usb-gadget"; + qcom,vid = <0x05c6>; + + composition1 { + qcom,pid = <0x9103>; + qcom,composition = "diag.diag,ipc.ipc,gsi.rmnet,gsi.rmnet.v2x,ecm.ecm,gsi.dpl"; + }; + + composition2 { + qcom,pid = <0x9105>; + qcom,composition = "diag.diag,gsi.dpl"; + }; + + composition3 { + qcom,pid = <0x9063>; + qcom,composition = "gsi.rndis|gsi.ecm|gsi.mbim"; + qcom,bmAttributes = <0xa0>; + }; + }; diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 7eba656d4638..a4dac2bfbf67 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -259,3 +259,50 @@ }; }; + +/ { + qcom_gadget { + compatible = "qcom,usb-gadget"; + qcom,vid = <0x05c6>; + + composition1 { + qcom,pid = <0x9057>; + qcom,composition = "gsi.rndis|gsi.ecm"; + }; + + composition2 { + qcom,pid = <0x905b>; + qcom,composition = "gsi.mbim"; + qcom,bmAttributes = <0xa0>; + }; + + composition3 { + qcom,pid = <0x9063>; + qcom,composition = "gsi.rndis|gsi.ecm|gsi.mbim"; + qcom,bmAttributes = <0xa0>; + }; + + composition4 { + qcom,pid = <0x9067>; + qcom,composition = "mass_storage.0,gsi.rmnet|mass_storage.1,gsi.mbim"; + qcom,bmAttributes = <0xa0>; + }; + + composition5 { + qcom,pid = <0x90b1>; + qcom,composition = "gsi.ecm"; + qcom,bmAttributes = <0xa0>; + }; + + composition6 { + qcom,pid = <0x90e2>; + qcom,composition = "gsi.mbim,gsi.gps"; + qcom,bmAttributes = <0xa0>; + }; + + composition7 { + qcom,pid = <0xf000>; + qcom,composition = "mass_storage.0"; + }; + }; +}; From e3325e26c575b9830825d3cc359544227afead65 Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Thu, 8 Apr 2021 13:26:10 +0800 Subject: [PATCH 1236/1809] ARM: dts: msm: add USB0 for SA8195 LXC VM enable usb0 phy for sa8195 lxc virtual machine. Change-Id: Ie30f2b5d98228cd334e565d69d4dab8a8c97f8ff --- qcom/sa8195-vm-lv-lxc.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 36b87490f86b..831afe1de548 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -25,8 +25,7 @@ status = "ok"; }; -&usb1 { - qcom,default-mode-host; +&usb2_phy0 { status = "ok"; }; From 9a86c18126aada3da16626a61fa4b6370703738c Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 8 Apr 2021 10:13:38 +0530 Subject: [PATCH 1237/1809] ARM: dts: msm: bypass S1 dma mappings in Linux guest set qcom,iommu-dma = "bypass" for all gvm targets. Change-Id: I701c197b658ca2be4fae127fb158ca58151b843a --- qcom/sa6155p-vm.dtsi | 4 ++-- qcom/sa8155-vm.dtsi | 8 ++++---- qcom/sa8195-vm.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index e8eeb6962b76..d05b4a78d23d 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -436,12 +436,12 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index c8cd071c445d..f018c755ef3f 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -862,25 +862,25 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_2 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_3 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &pcie_rc0 { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 24fe4aa76894..9b0126ff7ef4 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -893,19 +893,19 @@ &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_1 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_2 { /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; - qcom,iommu-dma = "atomic"; + qcom,iommu-dma = "bypass"; }; &qupv3_3 { From ed74cd3f7843663a33932f7f881937c0b66ab86a Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Wed, 30 Sep 2020 15:09:36 +0800 Subject: [PATCH 1238/1809] ARM: dts: msm: Add spmi device tree node for sa8195 Add spmi pmic and its dependent device tree node to support SA8195 for automotive platforms. Change-Id: I2b76821c2b53d7e11b4e5fa254c4dea24a424342 --- qcom/pm8195-vm.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++++ qcom/sa8195-vm.dtsi | 1 + 2 files changed, 47 insertions(+) create mode 100644 qcom/pm8195-vm.dtsi diff --git a/qcom/pm8195-vm.dtsi b/qcom/pm8195-vm.dtsi new file mode 100644 index 000000000000..47bdb2e15547 --- /dev/null +++ b/qcom/pm8195-vm.dtsi @@ -0,0 +1,46 @@ +#include +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm8195@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8195_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&pm8195_1_gpios { + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 24fe4aa76894..1ed05ea0bf2d 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -864,6 +864,7 @@ #include "sa8195-qupv3.dtsi" #include "sa8195-ssc-qupv3.dtsi" #include "sa8155-vm-audio.dtsi" +#include "pm8195-vm.dtsi" &tlmm { /delete-property/ wakeup-parent; From 345f61b3bdb8e9552be11be98e6f1846cd39365c Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 7 Apr 2021 13:37:20 +0530 Subject: [PATCH 1239/1809] ARM: dts: msm: update gold L3 memlat mapping for yupik target Incorrect value for 1.2GHz in L3 memlat mapping table results in L3 memlat vote from Gold cluster to not go above 768Mhz. Update the table with correct value. Change-Id: Iba6d57e0f04ef4dfb8409334bc784c751b0f6cc2 --- qcom/yupik.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 2d9075c89e2f..dabe7c2b05d4 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2050,7 +2050,7 @@ qcom,core-dev-table = < 940800 556800000 >, - < 12288000 768000000 >, + < 1228800 768000000 >, < 1651200 1190400000 >, < 1900800 1401600000 >, < 2400000 1516800000 >; From 9599e622c3af1bc125ce3d13419203ecee22b929 Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Fri, 9 Apr 2021 16:12:51 +0800 Subject: [PATCH 1240/1809] ARM: dts: msm: change the data delay to 1 for direwolf GVM audio Need set data delay to 1 for removing noise of GVM recording. Change-Id: Id533cabe086365f28a09258613dfdab9b9dc07c8 --- qcom/direwolf-vm-audio.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/direwolf-vm-audio.dtsi b/qcom/direwolf-vm-audio.dtsi index cc26d7d642c7..b19586acd6d7 100644 --- a/qcom/direwolf-vm-audio.dtsi +++ b/qcom/direwolf-vm-audio.dtsi @@ -17,7 +17,7 @@ qcom,msm-cpudai-tdm-sync-src = <1>; qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; - qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36864>; @@ -54,7 +54,7 @@ qcom,msm-cpudai-tdm-sync-src = <1>; qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; - qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { compatible = "qcom,msm-dai-q6-tdm"; qcom,msm-cpudai-tdm-dev-id = <36865>; From 4e54781b4af737dc1edb242da4febb47b9729fb1 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 9 Apr 2021 16:21:53 +0800 Subject: [PATCH 1241/1809] ARM: dts: msm: disable rpm etm There is no rpm subsystem, so disable rpm etm. Change-Id: Ia2080795334991b7d9881ab8583a912cc362c169 --- qcom/sdxnightjar-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar-coresight.dtsi b/qcom/sdxnightjar-coresight.dtsi index 1dddb7791c77..7322798dc7c6 100644 --- a/qcom/sdxnightjar-coresight.dtsi +++ b/qcom/sdxnightjar-coresight.dtsi @@ -132,7 +132,7 @@ coresight-name = "coresight-rpm-etm0"; qcom,inst-id = <4>; - + status = "disabled"; out-ports { port { rpm_etm0_out_funnel_in0: endpoint { From 06e39ff07ca12060585ce0d769875e62ba89f03d Mon Sep 17 00:00:00 2001 From: Ajit Kumar Date: Thu, 8 Apr 2021 09:59:15 +0530 Subject: [PATCH 1242/1809] bindings: Add device-tree bindings for slate_events_bridge driver Add device-tree bindings documentation describing the properties for the slate-events-bridge and slate-events-bridge-rpmsg driver. Change-Id: Ic2530235d30758ceb82f19f1177ab81309e49bf1 --- .../soc/qcom/qcom,slate_events_bridge.txt | 14 +++++++++++++ .../qcom/qcom,slate_events_bridge_rpmsg.txt | 20 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slate_events_bridge.txt create mode 100644 bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.txt diff --git a/bindings/soc/qcom/qcom,slate_events_bridge.txt b/bindings/soc/qcom/qcom,slate_events_bridge.txt new file mode 100644 index 000000000000..8f0fec72f56f --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_events_bridge.txt @@ -0,0 +1,14 @@ +* Slate Events Bridge Driver + +slate_events_bridge driver provides a set of apis for clients +to receive events from slate co processor. The events are +received over Glink. + +Required properties: +- compatible: Must be "qcom,slate-events-bridge" + +Example: + qcom,slate-events-bridge { + compatible = "qcom,slate-events-bridge"; + }; + diff --git a/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.txt b/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.txt new file mode 100644 index 000000000000..3576e98a88dc --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.txt @@ -0,0 +1,20 @@ +* Slate Events Bridge RPMSG Driver + +slate_events_bridge_rpmsg driver provides functionality +to send and receive data over Glink from slate co processor. + +Required properties: +- compatible: Must be "qcom,slate-events-bridge-rpmsg" +- qcom,glink-channels specifies the glink channel name +- qcom,glinkpkt-edge specifies the glink edge to match + +Optional properties: +- intents specifies the size and count of intents to glink + +Example: + qcom,slate-events-bridge-rpmsg { + compatible = "qcom,slate-events-bridge-rpmsg"; + qcom,glink-channels = "slate_events"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 5>; + }; From 3658467cb7bd9f9e439d890daab3889e6f700db2 Mon Sep 17 00:00:00 2001 From: aishpras Date: Thu, 1 Apr 2021 17:53:26 +0530 Subject: [PATCH 1243/1809] ARM: dts: qcom: Add qti-can device tree node Add qti-can device node for sa8195 and sa6155. Change-Id: I1dce510c999e8015104df5b4fa47939723f892c5 --- qcom/sa6155-adp-common.dtsi | 15 +++++++++++++++ qcom/sa8195p-adp-common.dtsi | 19 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index 1b00deb39e43..8550b2ac1915 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -5,6 +5,21 @@ status = "ok"; }; +&qupv3_se6_spi { + status = "ok"; + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <40 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + &soc { qcom,lpass@62400000 { status = "ok"; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 198a39402a3e..f15744799179 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -7,6 +7,25 @@ status = "ok"; }; +&qupv3_se0_spi { +status = "ok"; + +#address-cells = <1>; +#size-cells = <0>; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + &qupv3_se12_2uart { status = "ok"; }; From 445eecaabbebdff58442058adcde2273092ff909 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Apr 2021 16:10:21 +0530 Subject: [PATCH 1244/1809] dt-bindings: leds-qpnp-flash-v2: Add support to control ramp time Add device tree properties "qcom,ramp-up-step" and "qcom,ramp-down-step", to configure the time steps for flash current ramp up and ramp down. Change-Id: I0cfe8c21f55fe864364337bb6c909426be966d6d --- bindings/leds/leds-qpnp-flash-v2.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/leds/leds-qpnp-flash-v2.txt b/bindings/leds/leds-qpnp-flash-v2.txt index bb7e5202391a..e2216afa583c 100644 --- a/bindings/leds/leds-qpnp-flash-v2.txt +++ b/bindings/leds/leds-qpnp-flash-v2.txt @@ -21,6 +21,12 @@ Optional properties: 128, 192. Unit is uS. - qcom,warmup-delay-us : Integer type to specify warm up delay. Valid values are 32, 64, 128, 192. Unit is uS. +- qcom,ramp-up-step : Integer property to specify flash current ramp up time + step. Unit is in nS. Allowed values are: 200, 400, 800, 1600, + 3200, 6400, 12800, 25600. +- qcom,ramp-down-step : Integer property to specify flash current ramp down + time step. Unit is in nS. Allowed values are: 200, 400, 800, 1600, + 3200, 6400, 12800, 25600. - qcom,short-circuit-det : Boolean property which enables short circuit fault detection. - qcom,open-circuit-det : Boolean property which enables open circuit fault detection. - qcom,vph-droop-det : Boolean property which enables VPH droop detection. From a870975352f4ececddabdf76837a04cd9b700599 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 12 Apr 2021 19:02:41 +0530 Subject: [PATCH 1245/1809] bindings: cpufreq-hw: Add support for SDPM CX/MX offset Introduce an optional addresses and sizes for the SDPM memory of the HW bases in each frequency domain, indicated by an "id"(0/1/2). Change-Id: I7762c62176258fe09c94a0b118340b076940955a --- bindings/cpufreq/cpufreq-qcom-hw.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/cpufreq/cpufreq-qcom-hw.txt b/bindings/cpufreq/cpufreq-qcom-hw.txt index 251ea7dcca40..4ece108cbbb0 100644 --- a/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -50,6 +50,12 @@ Properties: should have the "pdmem-domainX" to indicate the corresponding bases. +- qcom,sdpm-cx-mx- + Usage: Optional + Value type: + Definition: Addresses and sizes for the SDPM memory of the HW bases + in each frequency domain, indicated by an "id"(0/1/2). + * Property qcom,freq-domain Devices supporting freq-domain must set their "qcom,freq-domain" property with phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. @@ -181,6 +187,8 @@ DCVS state together. clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>; + qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>; #freq-domain-cells = <1>; }; From c7841aabfbc24448e954cfc773838b7e0a0f7bc8 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 2 Mar 2021 13:11:39 +0530 Subject: [PATCH 1246/1809] ARM: dts: msm: Add SDPM domain indexes for YUPIK Add the MX domain indexes for Gold & Goldp. Change-Id: I2870306bdd8fa26af053286e579018dd8fe3314e --- qcom/yupik.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 2d9075c89e2f..612f8e69cc3f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1162,6 +1162,9 @@ ; interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; + qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>; + qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>; + #freq-domain-cells = <2>; }; From c18bafeda196be9f897ee116f03d2f13375c00cf Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Mon, 12 Apr 2021 11:13:43 -0700 Subject: [PATCH 1247/1809] ARM: dts: msm: Remove CNSS WLAN CMA region for sdxlemur-512M variants Commit 390b3f3f4b25 ("ARM: dts: msm: Add bindings for llcc tcm") added the CNSS WLAN CMA region back for all variants of sdxlemur targets, including 512 MB variants, which is not desired. Remove it, such that it is only included for the 1 GB variants of sdxlemur. Fixes: 390b3f3f4b25 ("ARM: dts: msm: Add bindings for llcc tcm") Change-Id: I9b94e87480e3133eeec057cd5b124eb0da87668d --- qcom/sdxlemur.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 9b5aae70a9e0..916500cb0ad8 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -77,14 +77,6 @@ size = <0x400000>; }; - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x1400000>; - }; - llcc_tcm_mem: llcc_tcm_region { no-map; reg = <0x15800000 0x800000>; From a6916b160d26c9c8127d9116e8eefb87daa1e1db Mon Sep 17 00:00:00 2001 From: pxiao Date: Tue, 13 Apr 2021 10:02:01 +0800 Subject: [PATCH 1248/1809] ARM: dts: qcom: Update fan cooling thermal config for HHG Update venus sensor thermal config threshold to enable fan cooling work as per latest recommendation. Change-Id: I6734ad190b07f2ce5fad2fa2aa77b1db43353a3f --- qcom/lahaina-hhg.dtsi | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 823c48c0e189..d2ba7eb32f1b 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -133,7 +133,7 @@ fan_cpu16_config2: fan-cpu16-config2 { temperature = <95000>; - hysteresis = <0>; + hysteresis = <5000>; type = "passive"; }; }; @@ -172,7 +172,7 @@ fan_cpu17_config2: fan-cpu17-config2 { temperature = <95000>; - hysteresis = <0>; + hysteresis = <5000>; type = "passive"; }; }; @@ -273,6 +273,38 @@ }; }; + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 6>; + trips { + fan_video_config0: fan-video-config0 { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + + fan_video_config1: fan-video-config1 { + temperature = <60000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_video_config0>; + cooling-device = <&fancontroller 1 1>; + }; + + fan_cdev_1 { + trip = <&fan_video_config1>; + cooling-device = <&fancontroller 2 2>; + }; + }; + }; + gpu-skin-avg-step { disable-thermal-zone; }; From 062fe0da9a7335af7e622f7cdc61d32e13e92f2d Mon Sep 17 00:00:00 2001 From: wadesong Date: Mon, 12 Apr 2021 11:25:58 +0800 Subject: [PATCH 1249/1809] ARM: dts: qcom: Remove unused mem reservation for wlan It is confirmed that the following items from device tree will not be required on auto platforms given these items are only used by iHelium while auto platforms do not use the same chipset: 'pil_wlan_fw_mem' 'wlan_msa_mem' Those memory blocks reserved by the above dtsi nodes will be re-allocated to other components. Change-Id: Ib20177c135cf53ed0bfb7a97c03363ea6ac3b330 --- qcom/sa6155.dtsi | 7 +++++++ qcom/sa8155.dtsi | 5 +++++ qcom/sa8195p.dtsi | 7 +++++++ 3 files changed, 19 insertions(+) diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index e092a8907c96..d3b627917396 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -13,6 +13,13 @@ }; }; +&reserved_memory { + /* wlan_msa_mem is only used when iHelium is attached, + * so remove the node for sa6155 + */ + /delete-node/ wlan_msa_mem; +}; + &soc { qfprom: qfprom@780130 { compatible = "qcom,qfprom"; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 72f8f1fffd87..78933e085cd0 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -372,6 +372,11 @@ }; &reserved_memory { + /* pil_wlan_fw_mem is only used when iHelium is attached, + * so remove the node for sa8155 + */ + /delete-node/ pil_wlan_fw_mem; + uefi_log: uefi_log@0x9241C000 { reg = <0x0 0x9241C000 0x0 0x10000>; label = "uefi_log"; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 10532f45caff..392a9323f0b4 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -13,6 +13,13 @@ }; }; +&reserved_memory { + /* pil_wlan_fw_mem is only used when iHelium is attached, + * so remove the node for sa8195p + */ + /delete-node/ pil_wlan_fw_mem; +}; + &soc { qfprom: qfprom@780130 { compatible = "qcom,qfprom"; From 278b616db3ada1ffdd56fba1e45bacd475fd1608 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Thu, 8 Apr 2021 21:32:37 +0530 Subject: [PATCH 1250/1809] bindings: update documentation for custom-bridge-size This change adds documenation for a newly added property for shmbridge driver, qcom,custom-bridge-size. Change-Id: I82287d3e3fd6e595f6388400b1866c696ec88433 --- .../soc/qcom/qcom,tee-shared-memory-bridge.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/bindings/soc/qcom/qcom,tee-shared-memory-bridge.yaml b/bindings/soc/qcom/qcom,tee-shared-memory-bridge.yaml index 0e617b851dca..1ad6dc60ee5a 100644 --- a/bindings/soc/qcom/qcom,tee-shared-memory-bridge.yaml +++ b/bindings/soc/qcom/qcom,tee-shared-memory-bridge.yaml @@ -18,11 +18,24 @@ properties: items: - const: qcom,tee-shared-memory-bridge + qcom,custom-bridge-size : indicates the size of SHM Bridge to be supported in multiples of 4K + required: - compatible +optional: + - qcom,custom-bridge-size + examples: - | qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; }; + + To allocate 1M memory for SHMBridge, we will have entry like this: + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <256>; + }; + From 24218a4bd7fb56a4942fba1b5a027ba785085619 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 9 Oct 2020 10:04:29 +0530 Subject: [PATCH 1251/1809] ARM: dts: msm: Add gcc, rpmhcc and gdsc nodes for direwolf Add gcc, rpmhcc nodes to facilitate clients to request and operate on clocks. Change-Id: I00be9a8fd363ac3c590a64c20d0dbc8abb5f6ca5 --- qcom/direwolf-gdsc.dtsi | 232 +++++++++++++++++++++ qcom/direwolf.dtsi | 432 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 664 insertions(+) create mode 100644 qcom/direwolf-gdsc.dtsi diff --git a/qcom/direwolf-gdsc.dtsi b/qcom/direwolf-gdsc.dtsi new file mode 100644 index 000000000000..4815908f4936 --- /dev/null +++ b/qcom/direwolf-gdsc.dtsi @@ -0,0 +1,232 @@ +&soc { + gcc_apcs_gdsc_vote_ctrl: syscon@152128 { + compatible = "syscon"; + reg = <0x152128 0x4>; + }; + + /* GDSCs in GCC */ + gcc_emac0_gdsc: qcom,gdsc@1aa004 { + compatible = "qcom,gdsc"; + reg = <0x1aa004 0x4>; + qcom,support-hw-trigger; + qcom,retain-regs; + regulator-name = "gcc_emac0_gdsc"; + status = "disabled"; + }; + + gcc_emac1_gdsc: qcom,gdsc@1ba004 { + compatible = "qcom,gdsc"; + reg = <0x1ba004 0x4>; + qcom,support-hw-trigger; + qcom,retain-regs; + regulator-name = "gcc_emac1_gdsc"; + status = "disabled"; + }; + + gcc_pcie_0_tunnel_gdsc: qcom,gdsc@1a4004 { + compatible = "qcom,gdsc"; + reg = <0x1a4004 0x4>; + qcom,gds-timeout = <500>; + qcom,support-hw-trigger; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>; + qcom,retain-regs; + regulator-name = "gcc_pcie_0_tunnel_gdsc"; + status = "disabled"; + }; + + gcc_pcie_1_tunnel_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + reg = <0x18d004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>; + regulator-name = "gcc_pcie_1_tunnel_gdsc"; + status = "disabled"; + }; + + gcc_pcie_2a_gdsc: qcom,gdsc@19d004 { + compatible = "qcom,gdsc"; + reg = <0x19d004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>; + regulator-name = "gcc_pcie_2a_gdsc"; + status = "disabled"; + }; + + gcc_pcie_2b_gdsc: qcom,gdsc@19e004 { + compatible = "qcom,gdsc"; + reg = <0x19e004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>; + regulator-name = "gcc_pcie_2b_gdsc"; + status = "disabled"; + }; + + gcc_pcie_3a_gdsc: qcom,gdsc@1a0004 { + compatible = "qcom,gdsc"; + reg = <0x1a0004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>; + regulator-name = "gcc_pcie_3a_gdsc"; + status = "disabled"; + }; + + gcc_pcie_3b_gdsc: qcom,gdsc@1a2004 { + compatible = "qcom,gdsc"; + reg = <0x1a2004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 5>; + regulator-name = "gcc_pcie_3b_gdsc"; + status = "disabled"; + }; + + gcc_pcie_4_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + qcom,support-hw-trigger; + qcom,gds-timeout = <500>; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 6>; + regulator-name = "gcc_pcie_4_gdsc"; + status = "disabled"; + }; + + gcc_ufs_card_gdsc: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + reg = <0x175004 0x4>; + qcom,retain-regs; + regulator-name = "gcc_ufs_card_gdsc"; + status = "disabled"; + }; + + gcc_ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + qcom,retain-regs; + regulator-name = "gcc_ufs_phy_gdsc"; + status = "disabled"; + }; + + gcc_usb30_mp_gdsc: qcom,gdsc@1ab004 { + compatible = "qcom,gdsc"; + reg = <0x1ab004 0x4>; + qcom,retain-regs; + regulator-name = "gcc_usb30_mp_gdsc"; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + qcom,retain-regs; + regulator-name = "gcc_usb30_prim_gdsc"; + status = "disabled"; + }; + + gcc_usb30_sec_gdsc: qcom,gdsc@110004 { + compatible = "qcom,gdsc"; + reg = <0x110004 0x4>; + qcom,retain-regs; + regulator-name = "gcc_usb30_sec_gdsc"; + status = "disabled"; + }; + + gcc_usb4_1_gdsc: qcom,gdsc@1b8004 { + compatible = "qcom,gdsc"; + reg = <0x1b8004 0x4>; + qcom,support-hw-trigger; + qcom,retain-regs; + regulator-name = "gcc_usb4_1_gdsc"; + status = "disabled"; + }; + + gcc_usb4_gdsc: qcom,gdsc@12a004 { + compatible = "qcom,gdsc"; + reg = <0x12a004 0x4>; + qcom,support-hw-trigger; + qcom,retain-regs; + regulator-name = "gcc_usb4_gdsc"; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c { + compatible = "qcom,gdsc"; + reg = <0x17d06c 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { + compatible = "qcom,gdsc"; + reg = <0x17d05c 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 { + compatible = "qcom,gdsc"; + reg = <0x17d060 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu2_gdsc: qcom,gdsc@17d0a0 { + compatible = "qcom,gdsc"; + reg = <0x17d0a0 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu2_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu3_gdsc: qcom,gdsc@17d0a4 { + compatible = "qcom,gdsc"; + reg = <0x17d0a4 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu3_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 0babcb1ce004..255184fd0d17 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1,6 +1,8 @@ #include #include #include +#include +#include #include / { @@ -385,6 +387,11 @@ system_pm { compatible = "qcom,system-pm"; }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,direwolf-rpmh-clk"; + #clock-cells = <1>; + }; }; pdc: interrupt-controller@b220000 { @@ -522,6 +529,334 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + gcc_usb4_1_phy_dp_gmux_clk_src: gcc_usb4_1_phy_dp_gmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_1_phy_dp_gmux_clk_src"; + #clock-cells = <0>; + }; + + gcc_usb4_1_phy_pipegmux_clk_src: gcc_usb4_1_phy_pipegmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_1_phy_pipegmux_clk_src"; + #clock-cells = <0>; + }; + + gcc_usb4_1_phy_sys_pipegmux_clk_src: gcc_usb4_1_phy_sys_pipegmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_1_phy_sys_pipegmux_clk_src"; + #clock-cells = <0>; + }; + + gcc_usb4_phy_dp_gmux_clk_src: gcc_usb4_phy_dp_gmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_phy_dp_gmux_clk_src"; + #clock-cells = <0>; + }; + + gcc_usb4_phy_pipegmux_clk_src: gcc_usb4_phy_pipegmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_phy_pipegmux_clk_src"; + #clock-cells = <0>; + }; + + gcc_usb4_phy_sys_pipegmux_clk_src: gcc_usb4_phy_sys_pipegmux_clk_src { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "gcc_usb4_phy_sys_pipegmux_clk_src"; + #clock-cells = <0>; + }; + + pcie_2a_pipe_clk: pcie_2a_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_2a_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_2b_pipe_clk: pcie_2b_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_2b_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_3a_pipe_clk: pcie_3a_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_3a_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_3b_pipe_clk: pcie_3b_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_3b_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_4_pipe_clk: pcie_4_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_4_pipe_clk"; + #clock-cells = <0>; + }; + + qusb4phy_1_gcc_usb4_rx0_clk: qusb4phy_1_gcc_usb4_rx0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "qusb4phy_1_gcc_usb4_rx0_clk"; + #clock-cells = <0>; + }; + + qusb4phy_1_gcc_usb4_rx1_clk: qusb4phy_1_gcc_usb4_rx1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "qusb4phy_1_gcc_usb4_rx1_clk"; + #clock-cells = <0>; + }; + + qusb4phy_gcc_usb4_rx0_clk: qusb4phy_gcc_usb4_rx0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "qusb4phy_gcc_usb4_rx0_clk"; + #clock-cells = <0>; + }; + + qusb4phy_gcc_usb4_rx1_clk: qusb4phy_gcc_usb4_rx1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "qusb4phy_gcc_usb4_rx1_clk"; + #clock-cells = <0>; + }; + + rxc0_ref_clk: rxc0_ref_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "rxc0_ref_clk"; + #clock-cells = <0>; + }; + + rxc1_ref_clk: rxc1_ref_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "rxc1_ref_clk"; + #clock-cells = <0>; + }; + + ufs_card_rx_symbol_0_clk: ufs_card_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_card_rx_symbol_1_clk: ufs_card_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_card_tx_symbol_0_clk: ufs_card_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_uni_phy_mp_gcc_usb30_pipe_0_clk: usb3_uni_phy_mp_gcc_usb30_pipe_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_0_clk"; + #clock-cells = <0>; + }; + + usb3_uni_phy_mp_gcc_usb30_pipe_1_clk: usb3_uni_phy_mp_gcc_usb30_pipe_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_1_clk"; + #clock-cells = <0>; + }; + + usb3_uni_phy_sec_gcc_usb30_pipe_clk: usb3_uni_phy_sec_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + + usb4_1_phy_gcc_usb4_pcie_pipe_clk: usb4_1_phy_gcc_usb4_pcie_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb4_1_phy_gcc_usb4_pcie_pipe_clk"; + #clock-cells = <0>; + }; + + usb4_1_phy_gcc_usb4rtr_max_pipe_clk: usb4_1_phy_gcc_usb4rtr_max_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb4_1_phy_gcc_usb4rtr_max_pipe_clk"; + #clock-cells = <0>; + }; + + usb4_phy_gcc_usb4_pcie_pipe_clk: usb4_phy_gcc_usb4_pcie_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb4_phy_gcc_usb4_pcie_pipe_clk"; + #clock-cells = <0>; + }; + + usb4_phy_gcc_usb4rtr_max_pipe_clk: usb4_phy_gcc_usb4rtr_max_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb4_phy_gcc_usb4rtr_max_pipe_clk"; + #clock-cells = <0>; + }; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,direwolf-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc_usb4_1_phy_dp_gmux_clk_src>, + <&gcc_usb4_1_phy_pipegmux_clk_src>, + <&gcc_usb4_1_phy_sys_pipegmux_clk_src>, + <&gcc_usb4_phy_dp_gmux_clk_src>, + <&gcc_usb4_phy_pipegmux_clk_src>, + <&gcc_usb4_phy_sys_pipegmux_clk_src>, + <&pcie_2a_pipe_clk>, + <&pcie_2b_pipe_clk>, + <&pcie_3a_pipe_clk>, + <&pcie_3b_pipe_clk>, + <&pcie_4_pipe_clk>, + <&qusb4phy_1_gcc_usb4_rx0_clk>, + <&qusb4phy_1_gcc_usb4_rx1_clk>, + <&qusb4phy_gcc_usb4_rx0_clk>, + <&qusb4phy_gcc_usb4_rx1_clk>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>, + <&sleep_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>, + <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>, + <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>, + <&usb4_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_phy_gcc_usb4rtr_max_pipe_clk>; + clock-names = "bi_tcxo", + "gcc_usb4_1_phy_dp_gmux_clk_src", + "gcc_usb4_1_phy_pipegmux_clk_src", + "gcc_usb4_1_phy_sys_pipegmux_clk_src", + "gcc_usb4_phy_dp_gmux_clk_src", + "gcc_usb4_phy_pipegmux_clk_src", + "gcc_usb4_phy_sys_pipegmux_clk_src", + "pcie_2a_pipe_clk", + "pcie_2b_pipe_clk", + "pcie_3a_pipe_clk", + "pcie_3b_pipe_clk", + "pcie_4_pipe_clk", + "qusb4phy_1_gcc_usb4_rx0_clk", + "qusb4phy_1_gcc_usb4_rx1_clk", + "qusb4phy_gcc_usb4_rx0_clk", + "qusb4phy_gcc_usb4_rx1_clk", + "rxc0_ref_clk", + "rxc1_ref_clk", + "sleep_clk", + "ufs_card_rx_symbol_0_clk", + "ufs_card_rx_symbol_1_clk", + "ufs_card_tx_symbol_0_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "usb3_uni_phy_mp_gcc_usb30_pipe_0_clk", + "usb3_uni_phy_mp_gcc_usb30_pipe_1_clk", + "usb3_uni_phy_sec_gcc_usb30_pipe_clk", + "usb4_1_phy_gcc_usb4_pcie_pipe_clk", + "usb4_1_phy_gcc_usb4rtr_max_pipe_clk", + "usb4_phy_gcc_usb4_pcie_pipe_clk", + "usb4_phy_gcc_usb4rtr_max_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90ba000 { + compatible = "syscon"; + reg = <0x90ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,direwolf-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,gcc = <&gcc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; @@ -577,3 +912,100 @@ #include "direwolf-pinctrl.dtsi" #include "direwolf-regulators.dtsi" #include "direwolf-pm.dtsi" +#include "direwolf-gdsc.dtsi" + +&gcc_emac0_gdsc { + status = "ok"; +}; + +&gcc_emac1_gdsc { + status = "ok"; +}; + +&gcc_pcie_0_tunnel_gdsc { + status = "ok"; +}; + +&gcc_pcie_1_tunnel_gdsc { + status = "ok"; +}; + +&gcc_pcie_2a_gdsc { + status = "ok"; +}; + +&gcc_pcie_2b_gdsc { + status = "ok"; +}; + +&gcc_pcie_3a_gdsc { + status = "ok"; +}; + +&gcc_pcie_3b_gdsc { + status = "ok"; +}; + +&gcc_pcie_4_gdsc { + status = "ok"; +}; + +&gcc_ufs_card_gdsc { + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + status = "ok"; +}; + +&gcc_usb30_mp_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_usb30_sec_gdsc { + status = "ok"; +}; + +&gcc_usb4_1_gdsc { + status = "ok"; +}; + +&gcc_usb4_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu3_gdsc { + status = "ok"; +}; From 480df512eb80566ea6db62ef9aa39ac2a3e9f023 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 4 Nov 2020 14:13:03 +0530 Subject: [PATCH 1252/1809] ARM: dts: msm: Add cpufreq HW device node for direwolf Add cpufreq HW device node to scale 4 domain-0 & 4 domain-1 cores on direwolf SoCs. Change-Id: If9697bd87eff71fa0cb8a3ae7fa0a04f4a0f4629 --- qcom/direwolf.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 255184fd0d17..8291673f00a5 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -28,6 +28,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -47,6 +48,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -61,6 +63,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_2>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -75,6 +78,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_3>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -89,6 +93,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -103,6 +108,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -117,6 +123,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -131,6 +138,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 1 4>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -857,6 +865,23 @@ #clock-cells = <1>; }; + cpufreq_hw: qcom,cpufreq-hw@18591000 { + compatible = "qcom,cpufreq-hw-epss"; + reg = <0x18591000 0x1000>, <0x18592000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + qcom,lut-row-size = <4>; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@18591000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; From ec0331337f3b19e908359737eb0f2c3e63444f7b Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 4 Nov 2020 11:41:03 +0530 Subject: [PATCH 1253/1809] ARM: dts: msm: Add aopcc for direwolf Add aopcc node to facilitate clients to request and operate on clocks. Change-Id: I61121dd0a69ed2d204045a56a3f1745b43557390 --- qcom/direwolf.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 8291673f00a5..6cb13e465868 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -770,6 +771,13 @@ }; }; + aopcc: qcom,aopclk { + compatible = "qcom,aop-qmp-clk"; + #clock-cells = <1>; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + }; + gcc: clock-controller@100000 { compatible = "qcom,direwolf-gcc", "syscon"; reg = <0x100000 0x1f0000>; From 0403ffe79eef501f68ff7db23778ed5ec3b7f5f7 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Mon, 12 Apr 2021 22:42:34 -0700 Subject: [PATCH 1254/1809] ARM: dts: msm: Add QUPv3 functionality for the Direwolf VMs Add support for peripherals connected over QUP's for the Direwolf VMs. Change-Id: Idedfe4884cc0b83ce1b32f74bff3a07f200a10a3 --- qcom/direwolf-vm.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 33e04271c5c0..5b03442bd334 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -7,6 +7,10 @@ qcom,msm-name = "Direwolf V1"; qcom,msm-id = <460 0x10000>; + aliases { + hsuart0 = &qupv3_se2_4uart; + }; + firmware:firmware { android { /delete-property/ boot_devices; @@ -239,6 +243,26 @@ }; #include "direwolf-pinctrl.dtsi" +#include "direwolf-qupv3.dtsi" #include "pm8540-vm.dtsi" #include "direwolf-vm-audio.dtsi" #include "direwolf-vm-usb.dtsi" + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_2 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_se2_4uart { + status = "ok"; +}; From 2f49472d4792cb0a21e3ec8312774f886b619f16 Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Mon, 22 Feb 2021 14:46:05 -0800 Subject: [PATCH 1255/1809] ARM: dts: msm: add MX entries for PCIe EP on sdxlemur To properly support PCIe Gen4 on sdxlemur, PCIe needs to vote and scale MX rails accordingly. Add the required MX entries to enable PCIe EP driver to do so for sdxlemur. Change-Id: Ibebb2ac470fbe1ed22c9f4bd7e902de5e71c81fc --- qcom/sdxlemur.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..d8a64a575c8b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -925,9 +925,11 @@ gdsc-vdd-supply = <&gcc_pcie_gdsc>; vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; qcom,vreg-1p8-voltage-level = <1200000 1200000 3000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + qcom,vreg-mx-voltage-level = ; clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&gcc GCC_PCIE_CFG_AHB_CLK>, From e38239f0fc1010742d0b18a326dd845509c7b9e0 Mon Sep 17 00:00:00 2001 From: Anjana Hari Date: Fri, 9 Apr 2021 22:41:22 +0530 Subject: [PATCH 1256/1809] ARM: dts: msm: Add shared memory driver support Add shared memory driver support to steppe. Change-Id: Id24db16d19f5f754eaff0f1d21b7b5f9d8045b7c --- qcom/sm6150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 1c929aae27fa..11d351da53f3 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2397,6 +2397,14 @@ }; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; From 61c1f81056bad8908d43edaa6583d27c83b60c22 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 8 Apr 2021 12:57:06 +0530 Subject: [PATCH 1257/1809] ARM: dts: msm: Add support for GPU models properties GPU models properties will allow to configure gpu model name based on the hw fuse configuration. Change-Id: I467d68a0d4a3e5992430c3d90f937291b4039b2f --- bindings/gpu/adreno.txt | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 87789cf8d409..8e0bcc8566ca 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -97,6 +97,7 @@ Optional Properties: - qcom,chipid: If it exists this property is used to replace the chip identification read from the GPU hardware. This is used to override faulty hardware readings. +- qcom,gpu-model: If it exists this property is used for GPU model name. - qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event. - qcom,disable-busy-time-burst: Boolean. Disables the busy time burst to avoid switching @@ -214,10 +215,10 @@ Optional Properties: the threshold set by KGSL_GOVERNOR_CALL_INTERVAL. Enable only if target has NAP state enabled. nvmem-cells: - A phandle to the configuration data such as gpu speed bin, gpu gaming mode - provided by a nvmem device. If unspecified default values shall be used. + A phandle to the configuration data such as gpu speed bin, gpu gaming mode, + gpu model name provided by a nvmem device. If unspecified default values shall be used. nvmem-cell-names: - Should be "speed_bin", "gaming_bin" + Should be "speed_bin", "gaming_bin", "gpu_model" GPU Quirks: - qcom,gpu-quirk-two-pass-use-wfi: @@ -259,6 +260,22 @@ Properties: - qcom,mempool-reserved: Number of pages reserved at init time for a pool. - qcom,mempool-allocate: Allocate memory from the system memory when the reserved pool exhausted. +GPU model configuration: +- qcom,gpu-models: + Container of sets of GPU model names specified by qcom,gpu-models. +Properties: +- compatible: + Must be qcom,gpu-models. + +- qcom,gpu-model: + Defines a GPU model name for specific GPU model ID. + +Properties: +- qcom,gpu-model-id: + Identifier for the specific GPU hardware configuration - must match the value read + from the hardware. +- qcom,gpu-model: + GPU model name for a specific GPU hardware. SOC Hardware revisions: - qcom,soc-hw-revisions: @@ -364,8 +381,8 @@ Example of A330 GPU in MSM8916: vdd-parent-supply = <&VDD_GFX_LEVEL>; vdd-parent-min-corner = ; - nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; - nvmem-cell-names = "speed_bin", "gaming_bin"; + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model"; /* IOMMU Data */ iommu = <&gfx_iommu>; @@ -409,6 +426,17 @@ Example of A330 GPU in MSM8916: }; }; + qcom,gpu-models { + #address-cells = <1>; + #size-cells = <0>; + compatible="qcom,gpu-models"; + + qcom,gpu-model@0 { + qcom,gpu-model-id = <0>; + qcom,gpu-model = "Adreno642Lv1"; + }; + } + /* GPU Mempools */ qcom,gpu-mempools { #address-cells= <1>; From 574998b3696ed178d7cbfd27794ee2854f369fb7 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Fri, 19 Mar 2021 20:15:54 +0530 Subject: [PATCH 1258/1809] ARM: dts: msm: Add USB nodes for Blair Add USB nodes to support USB in peripheral mode on simulation platforms for Blair. Change-Id: I6c0b1815ce75e8a720720024dc187d0fcc33eceb --- qcom/blair-rumi.dtsi | 7 +++++ qcom/blair-usb.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++++ qcom/blair.dtsi | 1 + 3 files changed, 78 insertions(+) create mode 100644 qcom/blair-usb.dtsi diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 3ac07c6f9a1e..6994b5445b9b 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -149,3 +149,10 @@ &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; +&usb0 { + dwc3@4e00000 { + usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi new file mode 100644 index 000000000000..dee02ace8c3a --- /dev/null +++ b/qcom/blair-usb.dtsi @@ -0,0 +1,70 @@ +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = , + , + ; + interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,gsi-disable-io-coherency; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = ; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "super-speed"; + dr_mode = "drd"; + }; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + +}; + diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 16811dffc753..1446933ef5dc 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3382,6 +3382,7 @@ #include "holi-qupv3.dtsi" #include "display/holi-sde.dtsi" #include "holi-audio.dtsi" +#include "blair-usb.dtsi" #include "ipcc-test-holi.dtsi" &gcc_camss_top_gdsc { From 942ef1061cfa3fc29165fc43f80abd06136912f8 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 7 Apr 2021 11:44:22 +0530 Subject: [PATCH 1259/1809] ARM: dts: msm: Adding updated PHY tune parameters for Yupik Adding updated phy tune parameters for Yupik. This will ensure that QRD and MTP both have same phy tuning values. Change-Id: I46fd6ffbe901466ddcad3f726d39d440bc90c75f --- qcom/yupik-qrd.dtsi | 4 ---- qcom/yupik-usb.dtsi | 5 ++++- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 41d2e26b5921..cebfeb233046 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -652,7 +652,3 @@ }; -&usb2_phy0 { - qcom,param-override-seq = <0x0f 0x70 - 0x2c 0x74>; -}; diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 67b822bf441d..f4afd58dcfad 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -103,7 +103,10 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; - qcom,param-override-seq = <0x43 0x70>; /* override_x1 */ + qcom,param-override-seq = + <0xe6 0x6c /* override_x0 */ + 0x8b 0x70 /* override_x1 */ + 0x16 0x74>; /* override_x2 */ }; /* Primary USB port related QMP USB DP Combo PHY */ From 46ceb2a0fb87525973d67ba820cf22848da1b218 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 8 Apr 2021 13:07:17 +0530 Subject: [PATCH 1260/1809] ARM: dts: msm: Add gpu-model property for yupik gpu Add gpu-model property to specify gpu name for yupik. Change-Id: I95787b3cedf98d7b71ba83ae16fd110ea84b5fff --- qcom/yupik-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 67f2eb0010ed..c09538cf0ddc 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -48,6 +48,7 @@ "gpu_cc_hub_cx_int"; qcom,chipid = <0x06030500>; + qcom,gpu-model = "Adreno642Lv1"; qcom,no-nap; qcom,min-access-length = <32>; From d211ea3e3f22df13d665fbe486c1157dd4a45d51 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 24 Mar 2021 16:50:53 -0700 Subject: [PATCH 1261/1809] ARM: dts: msm: Add device tree for sdxlemur eMMC 512 MB variant Add device tree for sdxlemur eMMC 512 MB variant Change-Id: I8b8c09207c9c954fe59241b2bc261e4925c89f84 --- qcom/Makefile | 1 + qcom/sdxlemur-mtp-mbb-emmc-512mb.dts | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 qcom/sdxlemur-mtp-mbb-emmc-512mb.dts diff --git a/qcom/Makefile b/qcom/Makefile index 229cdd699c4f..4aec201f43d9 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -326,6 +326,7 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-mtp-cpe.dtb \ sdxlemur-mtp-mbb-emmc.dtb \ + sdxlemur-mtp-mbb-emmc-512mb.dtb \ sdxlemur-mtp-mbb-ntn3-pcie.dtb \ sdxlemur-mtp-mbb-pcie-ep.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ diff --git a/qcom/sdxlemur-mtp-mbb-emmc-512mb.dts b/qcom/sdxlemur-mtp-mbb-emmc-512mb.dts new file mode 100644 index 000000000000..aac6c513a0fb --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-emmc-512mb.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-emmc.dtsi" +#include "sdxlemur-512mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC 512 MB"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010108 0x202>; +}; From ad5b6295510428499ab914053f58a6778acd1e8a Mon Sep 17 00:00:00 2001 From: Deru Wang Date: Tue, 13 Apr 2021 19:40:20 +0800 Subject: [PATCH 1262/1809] ARM: dts: msm: mv quat/quin slpi pinctrl to SLPI devicetree file Fix the error of "invalid function func1/2/3 in map table" because these functions are defined in pinctrl-slpi.c. Need mv the quat/quin slpi pinctrl to sm6150-slpi-pinctrl.dtsi from sm6150-pinctrl.dtsi. Change-Id: I732136718eaedd2c1015dd74b6c2f6f476674960 --- qcom/sm6150-pinctrl.dtsi | 260 ---------------------------------- qcom/sm6150-slpi-pinctrl.dtsi | 260 ++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+), 260 deletions(-) diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi index fe39f680b9f4..8d39ef444d9f 100644 --- a/qcom/sm6150-pinctrl.dtsi +++ b/qcom/sm6150-pinctrl.dtsi @@ -1343,266 +1343,6 @@ }; }; - quat_tdm_sclk_active: quat_tdm_sclk_active { - mux { - pins = "gpio23"; - function = "func3"; - }; - - config { - pins = "gpio23"; - drive-strength = <6>; - bias-disable; - }; - }; - - quat_tdm_sclk_sleep: quat_tdm_sclk_sleep { - mux { - pins = "gpio23"; - function = "gpio"; - }; - - config { - pins = "gpio23"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quat_tdm_ws_active: quat_tdm_ws_active { - mux { - pins = "gpio24"; - function = "func1"; - }; - - config { - pins = "gpio24"; - drive-strength = <6>; - bias-disable; - }; - }; - - quat_tdm_ws_sleep: quat_tdm_ws_sleep { - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quat_tdm_data3_active: quat_tdm_data3_active { - mux { - pins = "gpio28"; - function = "func2"; - }; - - config { - pins = "gpio28"; - drive-strength = <4>; - bias-disable; - }; - }; - - quat_tdm_data3_sleep: quat_tdm_data3_sleep { - mux { - pins = "gpio28"; - function = "gpio"; - }; - - config { - pins = "gpio28"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quat_tdm_data2_active: quat_tdm_data2_active { - mux { - pins = "gpio27"; - function = "func2"; - }; - - config { - pins = "gpio27"; - drive-strength = <4>; - bias-disable; - }; - }; - - quat_tdm_data2_sleep: quat_tdm_data2_sleep { - mux { - pins = "gpio27"; - function = "gpio"; - }; - - config { - pins = "gpio27"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quat_tdm_data1_active: quat_tdm_data1_active { - mux { - pins = "gpio26"; - function = "func2"; - }; - - config { - pins = "gpio26"; - drive-strength = <4>; - bias-disable; - }; - }; - - quat_tdm_data1_sleep: quat_tdm_data1_sleep { - mux { - pins = "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio26"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quat_tdm_data0_active: quat_tdm_data0_active { - mux { - pins = "gpio25"; - function = "func1"; - }; - - config { - pins = "gpio25"; - drive-strength = <4>; - bias-disable; - }; - }; - - quat_tdm_data0_sleep: quat_tdm_data0_sleep { - mux { - pins = "gpio25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - quin_tdm_sclk_active: quin_tdm_sclk_active { - mux { - pins = "gpio18"; - function = "func3"; - }; - - config { - pins = "gpio18"; - drive-strength = <2>; - bias-disable; - }; - }; - - quin_tdm_sclk_sleep: quin_tdm_sclk_sleep { - mux { - pins = "gpio18"; - function = "gpio"; - }; - - config { - pins = "gpio18"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quin_tdm_data0_active: quin_tdm_data0_active { - mux { - pins = "gpio20"; - function = "func3"; - }; - - config { - pins = "gpio20"; - drive-strength = <2>; - bias-disable; - }; - }; - - quin_tdm_data0_sleep: quin_tdm_data0_sleep { - mux { - pins = "gpio20"; - function = "gpio"; - }; - - config { - pins = "gpio20"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - quin_tdm_ws_active: quin_tdm_ws_active { - mux { - pins = "gpio21"; - function = "func3"; - }; - - config { - pins = "gpio21"; - drive-strength = <2>; - bias-disable; - }; - }; - - quin_tdm_ws_sleep: quin_tdm_ws_sleep { - mux { - pins = "gpio21"; - function = "gpio"; - }; - - config { - pins = "gpio21"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - quin_tdm_data1_active: quin_tdm_data1_active { - mux { - pins = "gpio22"; - function = "func3"; - }; - - config { - pins = "gpio22"; - drive-strength = <8>; - bias-disable; - }; - }; - - quin_tdm_data1_sleep: quin_tdm_data1_sleep { - mux { - pins = "gpio22"; - function = "gpio"; - }; - - config { - pins = "gpio22"; - drive-strength = <2>; - bias-pull-down; - }; - }; - audio_internal_mclk2_active: audio_internal_mclk2_active { mux { pins = "gpio122"; diff --git a/qcom/sm6150-slpi-pinctrl.dtsi b/qcom/sm6150-slpi-pinctrl.dtsi index 58f609ab0c47..32d250433a47 100644 --- a/qcom/sm6150-slpi-pinctrl.dtsi +++ b/qcom/sm6150-slpi-pinctrl.dtsi @@ -239,5 +239,265 @@ }; }; }; + + quat_tdm_sclk_active: quat_tdm_sclk_active { + mux { + pins = "gpio23"; + function = "func3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + quat_tdm_sclk_sleep: quat_tdm_sclk_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_ws_active: quat_tdm_ws_active { + mux { + pins = "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + quat_tdm_ws_sleep: quat_tdm_ws_sleep { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data3_active: quat_tdm_data3_active { + mux { + pins = "gpio28"; + function = "func2"; + }; + + config { + pins = "gpio28"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data3_sleep: quat_tdm_data3_sleep { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data2_active: quat_tdm_data2_active { + mux { + pins = "gpio27"; + function = "func2"; + }; + + config { + pins = "gpio27"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data2_sleep: quat_tdm_data2_sleep { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data1_active: quat_tdm_data1_active { + mux { + pins = "gpio26"; + function = "func2"; + }; + + config { + pins = "gpio26"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data1_sleep: quat_tdm_data1_sleep { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quat_tdm_data0_active: quat_tdm_data0_active { + mux { + pins = "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio25"; + drive-strength = <4>; + bias-disable; + }; + }; + + quat_tdm_data0_sleep: quat_tdm_data0_sleep { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_sclk_active: quin_tdm_sclk_active { + mux { + pins = "gpio18"; + function = "func3"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_sclk_sleep: quin_tdm_sclk_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data0_active: quin_tdm_data0_active { + mux { + pins = "gpio20"; + function = "func3"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_data0_sleep: quin_tdm_data0_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_ws_active: quin_tdm_ws_active { + mux { + pins = "gpio21"; + function = "func3"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_ws_sleep: quin_tdm_ws_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data1_active: quin_tdm_data1_active { + mux { + pins = "gpio22"; + function = "func3"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; + bias-disable; + }; + }; + + quin_tdm_data1_sleep: quin_tdm_data1_sleep { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; }; From 6bd4c018d49ec82f41ecaf46b7427e86b4ea265d Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Fri, 16 Apr 2021 14:34:00 +0530 Subject: [PATCH 1263/1809] ARM: dts: msm: Disable icnss node for blair Disable wlan node for blair. Change-Id: I2966a061e425318c19ce25ad092151bd67367d2c --- qcom/blair.dtsi | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 1446933ef5dc..2618151b2517 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3158,6 +3158,7 @@ }; icnss: qcom,icnss@C800000 { + status = "disabled"; compatible = "qcom,icnss"; reg = <0xC800000 0x800000>, <0xb0000000 0x10000>; @@ -3180,14 +3181,6 @@ qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; qcom,iommu-geometry = <0xa0000000 0x10010000>; - vdd-cx-mx-supply = <&L4A>; - vdd-1.8-xo-supply = <&L7A>; - vdd-1.3-rfa-supply = <&L2E>; - vdd-3.3-ch1-supply = <&L11E>; - vdd-3.3-ch0-supply = <&L10E>; - qcom,vdd-cx-mx-config = <640000 640000>; - qcom,vdd-3.3-ch1-config = <3000000 3312000>; - qcom,vdd-3.3-ch0-config = <3000000 3312000>; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; From e6be55fc047440bd13bfca846579495d38fff504 Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Fri, 5 Mar 2021 13:33:03 -0800 Subject: [PATCH 1264/1809] ARM: dts: msm: Update load factor for PCIe rail on sdxlemur Changes to the devicetree property to reflect the updated load factor for the 1.2V PCIe rail. Change-Id: Id8ce153b810b25f4620daeddddb3c300efab9e8f --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..23e309427507 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -926,7 +926,7 @@ vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; - qcom,vreg-1p8-voltage-level = <1200000 1200000 3000>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; clocks = <&gcc GCC_PCIE_PIPE_CLK>, From 252a6899041f13efe6005a665964c742ac7fa4bb Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Tue, 9 Mar 2021 14:45:17 -0800 Subject: [PATCH 1265/1809] ARM: dts: msm: Add MX property for PCIe on sdxlemur Update the bindings document to include the devicetree property needed to scale the MX voltage to support the PCIe Gen4 controller for sdxlemur. Change-Id: I9b5b9f9cda70456a9c7af06adee498fa713d1f39 --- bindings/pci/msm_ep_pcie.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt index c364f472cc0b..425bddc9533d 100644 --- a/bindings/pci/msm_ep_pcie.txt +++ b/bindings/pci/msm_ep_pcie.txt @@ -33,6 +33,8 @@ Required properties: Optional Properties: - qcom,-voltage-level: specifies voltage levels for supply. Should be specified in pairs (max, min, optimal), units uV. + - qcom,vreg-mx-voltage-level: Support PCIe Gen4 on sdxlemur by scaling MX to + appropriate voltage. - clock-names: list of names of clock inputs. Should be "pcie_pipe_clk", "pcie_aux_clk", "pcie_cfg_ahb_clk", From 0710905907a1059443f9c10c480fe0266c56edaf Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Fri, 19 Mar 2021 18:42:09 +0530 Subject: [PATCH 1266/1809] ARM: dts: msm: Add DISPCC/DEBUGCC clock node for MONACO Add DISPCC clock nodes which is required for clocks client to request, so add support for the same. Add debug clock controller to support measure functionality for all clock controllers. Also add the disp GDSCs required by clients for MONACO. Change-Id: Ibed0e45fef8b88a972c2b154c43f1b38ce62d388 --- qcom/monaco-gdsc.dtsi | 2 +- qcom/monaco.dtsi | 30 ++++++++++++++++++++++++++++-- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi index dfa39a8cdaa4..88829cb6e9fa 100644 --- a/qcom/monaco-gdsc.dtsi +++ b/qcom/monaco-gdsc.dtsi @@ -46,7 +46,7 @@ /* GDSCs in DISPCC */ mdss_core_gdsc: qcom,gdsc@5f03000 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x5f03000 0x4>; regulator-name = "mdss_core_gdsc"; proxy-supply = <&mdss_core_gdsc>; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b753f2c41340..3e9883ccbcad 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -698,8 +698,14 @@ }; dispcc: clock-controller@5f00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,monaco-dispcc", "syscon"; + reg = <0x05f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main", + "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0>, <&sleep_clk>; + vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -711,6 +717,26 @@ #reset-cells = <1>; }; + mccc_debug: syscon@447d200 { + compatible = "syscon"; + }; + + apsscc_debug: syscon@f11101c { + compatible = "syscon"; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,monaco-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc_debug>; + qcom,apsscc = <&apsscc_debug>; + clock-names = "xo_clk_src"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + #clock-cells = <1>; + }; + cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw"; reg = <0xf521000 0x1400>; From 1eb2296a2506657abec7849ea8c789d934dde4da Mon Sep 17 00:00:00 2001 From: Mukesh Savaliya Date: Wed, 7 Apr 2021 05:00:18 -0700 Subject: [PATCH 1267/1809] Revert "ARM: dts: msm: Add LA specific TVM flag in respective SPI node" This reverts commit 7d8ed3e95e374bacefa7ae5b5a8c226ce8f12b2d. The change was added temporarily to fix the LA side issue and unblocking touch feature. This flag qcom, la-vm can be added by client on LA DT file when they use QUPV3 SE node for TVM usecase. Change-Id: Ic650e21597623f1a2b2d9aca8be8616310501010 --- qcom/yupik-qupv3.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index 446d7a5f6d7a..9b80a8e36999 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -667,7 +667,6 @@ dma-names = "tx", "rx"; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; - qcom,la-vm; status = "disabled"; }; From 86e9c9bfd243c8f21ba3b54146c16ae79df7304c Mon Sep 17 00:00:00 2001 From: Santoshkumar Zalake Date: Thu, 4 Feb 2021 13:14:01 -0800 Subject: [PATCH 1268/1809] ARM: dts: msm: enable SiRF GNSS Driver and hsuart1 DTS Entries to enable SiRF GNSS Driver and hsuart1 serial port for sa8155au. Change-Id: Ia7496d4201f1aa9cf53ca96cf71b23c16a68be6c --- qcom/sa8155-adp-common.dtsi | 12 ++++++++++++ qcom/sm8150-pinctrl.dtsi | 34 +++++++++++++++++++++++----------- qcom/sm8150-qupv3.dtsi | 20 +++++++++++++++++++- qcom/sm8150.dtsi | 1 + 4 files changed, 55 insertions(+), 12 deletions(-) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index 9f83b3860f0f..a78104e01c6b 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -72,6 +72,10 @@ status = "ok"; }; +&qupv3_se4_2uart { + status = "ok"; +}; + &qupv3_se12_2uart { status = "ok"; }; @@ -86,6 +90,14 @@ qcom,pil-force-shutdown; }; + ss5_pwr_ctrl0 { + compatible = "gnss_sirf"; + pinctrl-0 = <&ss5_pwr_ctrl_rst_on>; + ssVreset-gpio = <&tlmm 11 1>; + ssVonoff-gpio = <&tlmm 39 1>; + ssVboot-gpio = <&tlmm 40 1>; + }; + qcom,turing@8300000 { status = "ok"; }; diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index 33a90ce5e00e..01b748976c9a 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -723,7 +723,6 @@ bias-disable; }; }; - qupv3_se3_spi_miso_sleep: qupv3_se3_spi_miso_sleep { mux { pins = "gpio144"; @@ -741,13 +740,13 @@ ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins { ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on { mux { - pins = "gpio11", "gpio39"; + pins = "gpio11", "gpio39", "gpio40"; function = "gpio"; }; config { - pins = "gpio11", "gpio39"; - drive-strength = <16>; /* 16 mA */ + pins = "gpio11", "gpio39", "gpio40"; + drive-strength = <2>; /* 2 mA */ bias-pull-up; output-high; }; @@ -755,15 +754,15 @@ ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off { mux { - pins = "gpio11", "gpio39"; + pins = "gpio11", "gpio39", "gpio40"; function = "gpio"; }; config { - pins = "gpio11", "gpio39"; - drive-strength = <16>; /* 16 mA */ - bias-pull-up; - output-high; + pins = "gpio11", "gpio39", "gpio40"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + output-low; }; }; }; @@ -830,6 +829,19 @@ }; qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_default: qupv3_se4_2uart_default { + mux { + pins = "gpio41", "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + qupv3_se4_2uart_active: qupv3_se4_2uart_active { mux { pins = "gpio41", "gpio42"; @@ -838,7 +850,7 @@ config { pins = "gpio41", "gpio42"; - drive-strength = <16>; + drive-strength = <2>; bias-disable; }; }; @@ -851,7 +863,7 @@ config { pins = "gpio41", "gpio42"; - drive-strength = <16>; + drive-strength = <2>; bias-disable; }; }; diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi index e900d34b19e7..74b51b054ad7 100644 --- a/qcom/sm8150-qupv3.dtsi +++ b/qcom/sm8150-qupv3.dtsi @@ -336,10 +336,28 @@ ; iommus = <&apps_smmu 0x603 0x0>; qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; - qcom,iommu-dma = "fastmap"; + qcom,iommu-dma = "bypass"; status = "ok"; }; + /* GNSS UART Instance for CDP/MTP platform */ + qupv3_se4_2uart: qcom,qup_uart@a84000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default","active", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_default>; + pinctrl-1 = <&qupv3_se4_2uart_active>; + pinctrl-2 = <&qupv3_se4_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + /* Debug UART Instance for CDP/MTP platform */ qupv3_se12_2uart: qcom,qup_uart@0xa90000 { compatible = "qcom,msm-geni-console"; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index a4a555204eb4..876f6b77f1af 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -40,6 +40,7 @@ pci-domain1 = &pcie1; /* PCIe1 domain */ serial0 = &qupv3_se12_2uart; hsuart0 = &qupv3_se13_4uart; + hsuart1 = &qupv3_se4_2uart; spi22 = &qupv3_se22_spi; }; From 48cd84787b663ddee86457a42351316d5a8ce21b Mon Sep 17 00:00:00 2001 From: Santoshkumar Zalake Date: Thu, 4 Feb 2021 12:56:48 -0800 Subject: [PATCH 1269/1809] dt-bindings: Add devicetree bindings to devicetree project Add devicetree bindings snapshot to the devicetree project Change-Id: Ie64349677227a47cd3528b2c5d8101bc00d70d76 --- bindings/gnsssirf/gnss_sirf.txt | 47 +++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 bindings/gnsssirf/gnss_sirf.txt diff --git a/bindings/gnsssirf/gnss_sirf.txt b/bindings/gnsssirf/gnss_sirf.txt new file mode 100644 index 000000000000..18e8b251d9c5 --- /dev/null +++ b/bindings/gnsssirf/gnss_sirf.txt @@ -0,0 +1,47 @@ +Binding for SIRF GNSS receiver control driver +GPIO pins are toggled to control GNSS receiver power states either to +wake it from sleep or put receiver into sleep mode + +Required properties: +- compatible: must be "gnss_sirf" +- #gpio-pins: + 0: GPIO 18 + 1: GPIO 87 + +Example: + ss5_pwr_ctrl0 { + compatible = "gnss_sirf"; + pinctrl-0 = <&ss5_pwr_ctrl_rst_on>; + ssVreset-gpio = <&tlmm 87 1>; + ssVonoff-gpio = <&tlmm 18 1>; + }; + + ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins { + ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + + ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + }; From efec5d8cbcc548165c85484f573bf758764aadbd Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Thu, 10 Dec 2020 22:44:04 +0530 Subject: [PATCH 1270/1809] bindings: power: supply: Add documentation for QTI Battery Gauge Add bindings documentation for Qualcomm Technologies, Inc. Battery Gauge which uses periodic samples of the battery voltage and current to determine the battery state-of-charge (SOC) and supports other battery management features. Change-Id: Ic803215a24e333cc8bb5c2dd010289bda7f5ee24 --- bindings/power/supply/qcom/qcom,qbg.yaml | 110 +++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 bindings/power/supply/qcom/qcom,qbg.yaml diff --git a/bindings/power/supply/qcom/qcom,qbg.yaml b/bindings/power/supply/qcom/qcom,qbg.yaml new file mode 100644 index 000000000000..fccb19663159 --- /dev/null +++ b/bindings/power/supply/qcom/qcom,qbg.yaml @@ -0,0 +1,110 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/power/supply/qcom/qcom,qbg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Battery Gauge (QBG) binding + +maintainers: + - Shyam Kumar Thella + +description: | + Qualcomm Technologies, Inc. Battery Gauge (QBG) uses the periodic samples of + battery voltage and current to determine the battery state-of-charge (SOC) + and supports other battery management features. + +properties: + compatible: + const: qcom,qbg + + reg: + description: Base address of QBG MAIN peripheral. + maxItems: 1 + + interrupts: + description: Specifies the interrupts for nvmem devices used by QBG. + maxItems: 1 + + interrupt-names: + description: Specifies the interrupt names for nvmem devices used by QBG. + minItems: 1 + items: + - const: qbg-sdam + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,num-data-sdams: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of SDAMs used for storing QBG FIFO data. + + qcom,sdam-base: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Base address of QBG SDAM peripheral. + + qcom,vbat-cutoff-mv: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + description: The battery voltage threshold (in mV) at which the battery + power cuts off. The SOC is forced to 0 when battery voltage reaches + this value. + default: 3100 + + qcom,ibat-cutoff-ma: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: The battery current threshold (in mA) at which the battery + power cuts off. The SOC is forced to 0 when battery current reaches + this value. + default: 150 + + qcom,vph-min-mv: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: Minimum sustainable system power (in mV). + default: 2700 + + qcom,iterm-ma: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: The battery current (in mA) at which the QBG algorithm + converges the SOC to 100% during charging and can be used to terminate + charging. + default: 100 + + qcom,rconn-mohm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Resistance of the battery connector in mOhms. + +required: + - compatible + - reg + - interrupt-names + - interrupts + - qcom,num-data-sdams + - qcom,sdam-base + +examples: + - | + #include + spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm5100@0 { + #address-cells = <1>; + #size-cells = <0>; + + qbg@4f00 { + compatible = "qcom,qbg"; + reg = <0x4f00>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-names = "qbg-sdam"; + interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>; + qcom,num-data-sdams = <6>; + qcom,sdam-base = <0x7600>; + }; + }; + }; +... From 5a7c16b1823754d6c29ef49005ac0874fc2ee44c Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 15 Apr 2021 11:34:25 -0700 Subject: [PATCH 1271/1809] ARM: dts: msm: Add device tree for sdxlemur ATP variant Add device tree files for sdxlemur ATP variant. Change-Id: I19e2844577d880dcf9c87275db9d88f10c828c61 --- bindings/arm/msm/msm.txt | 1 + qcom/Makefile | 1 + qcom/sdxlemur-atp.dts | 12 ++++++++++++ qcom/sdxlemur-atp.dtsi | 5 +++++ 4 files changed, 19 insertions(+) create mode 100644 qcom/sdxlemur-atp.dts create mode 100644 qcom/sdxlemur-atp.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index e5d16d2541b1..f9c00aca2cb5 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -276,6 +276,7 @@ compatible = "qcom,sdxprairie-rumi" compatible = "qcom,sdxprairie-mtp" compatible = "qcom,sdxprairie-cdp" compatible = "qcom,sdxlemur-rumi" +compatible = "qcom,sdxlemur-atp" compatible = "qcom,sdxlemur-mtp" compatible = "qcom,sdxlemur-cdp" compatible = "qcom,sdxlemur-rcm" diff --git a/qcom/Makefile b/qcom/Makefile index 229cdd699c4f..00a497247381 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -321,6 +321,7 @@ endif endif dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ + sdxlemur-atp.dtb \ sdxlemur-cdp.dtb \ sdxlemur-mtp.dtb \ sdxlemur-mtp-mbb.dtb \ diff --git a/qcom/sdxlemur-atp.dts b/qcom/sdxlemur-atp.dts new file mode 100644 index 000000000000..67062a57aae1 --- /dev/null +++ b/qcom/sdxlemur-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-atp.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR ATP"; + compatible = "qcom,sdxlemur-atp", + "qcom,sdxlemur", "qcom,atp"; + qcom,board-id = <0x010021 0x200>; +}; diff --git a/qcom/sdxlemur-atp.dtsi b/qcom/sdxlemur-atp.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-atp.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + From 7c762769034efbe89004d9b38b2c76583099ca5f Mon Sep 17 00:00:00 2001 From: Ramachandran Venkataramani Date: Thu, 15 Apr 2021 22:47:54 -0700 Subject: [PATCH 1272/1809] ARM: dts: msm: Fix compilation warnings for auto GVM device tree - Remove duplicate includes for gcc and regulator header files. - Move includes for common header files to quin-vm-common. - Add/Fix address and size cells values where missing/incorrect. - Add #interrupt-controller for vgic node. Change-Id: I488c79bfb5c54dee0c4cd219e8937794489051da --- qcom/direwolf-vm.dtsi | 1 - qcom/pm6155-vm.dtsi | 3 +-- qcom/pm8150-vm.dtsi | 2 -- qcom/pm8195-vm.dtsi | 2 -- qcom/quin-vm-common.dtsi | 15 ++++++++++----- qcom/sa6155p-vm-pcie.dtsi | 3 --- qcom/sa6155p-vm-usb.dtsi | 2 -- qcom/sa6155p-vm.dtsi | 4 ---- qcom/sa8155-vm-pcie.dtsi | 4 ---- qcom/sa8155-vm-usb.dtsi | 2 -- qcom/sa8155-vm.dtsi | 4 ---- qcom/sa8195-vm-pcie.dtsi | 9 ++++++--- qcom/sa8195-vm-ufs.dtsi | 2 -- qcom/sa8195-vm-usb.dtsi | 3 +-- qcom/sa8195-vm.dtsi | 5 ----- 15 files changed, 18 insertions(+), 43 deletions(-) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 5b03442bd334..15ea3cf606de 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -1,4 +1,3 @@ -#include #include #include "quin-vm-common.dtsi" diff --git a/qcom/pm6155-vm.dtsi b/qcom/pm6155-vm.dtsi index 5b400ee4bc5b..5a96fb02f46c 100644 --- a/qcom/pm6155-vm.dtsi +++ b/qcom/pm6155-vm.dtsi @@ -1,4 +1,3 @@ -#include #include #include @@ -6,7 +5,7 @@ qcom,pm6155@0 { compatible = "qcom,spmi-pmic"; reg = <0 SPMI_USID>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; pm6155_1_gpios: pinctrl@c000 { diff --git a/qcom/pm8150-vm.dtsi b/qcom/pm8150-vm.dtsi index 2139dee1ebeb..b8c2c6569057 100644 --- a/qcom/pm8150-vm.dtsi +++ b/qcom/pm8150-vm.dtsi @@ -1,7 +1,5 @@ -#include #include #include -#include #include #include diff --git a/qcom/pm8195-vm.dtsi b/qcom/pm8195-vm.dtsi index 47bdb2e15547..0aa5c78fde8e 100644 --- a/qcom/pm8195-vm.dtsi +++ b/qcom/pm8195-vm.dtsi @@ -1,7 +1,5 @@ -#include #include #include -#include #include #include diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 653363f9505b..02f309379006 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -1,5 +1,8 @@ +#include +#include #include #include +#include / { #address-cells = <2>; @@ -97,6 +100,8 @@ intc: vgic@0 { qvm,vdev = "gic"; + #interrupt-cells = <3>; + interrupt-controller; }; dummycc: qcom,dummycc { @@ -108,7 +113,7 @@ gcc: virtio_clock@1c200000 { compatible = "virtio,mmio"; reg = <0x1c200000 0x1000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #clock-cells = <1>; #reset-cells = <1>; }; @@ -116,14 +121,14 @@ scc: virtio_clock@1c300000 { compatible = "virtio,mmio"; reg = <0x1c300000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #clock-cells = <1>; }; regulator: virtio_regulator@1c700000 { compatible = "virtio,mmio"; reg = <0x1c700000 0x1000>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; msm_ion: qcom,ion { @@ -292,8 +297,8 @@ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; qcom,bark-time = <11000>; qcom,pet-time = <9360>; qcom,ipi-ping; diff --git a/qcom/sa6155p-vm-pcie.dtsi b/qcom/sa6155p-vm-pcie.dtsi index 406b50e5a14f..8d703d9f0566 100644 --- a/qcom/sa6155p-vm-pcie.dtsi +++ b/qcom/sa6155p-vm-pcie.dtsi @@ -1,6 +1,3 @@ -#include -#include - &soc { pcie0: qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; diff --git a/qcom/sa6155p-vm-usb.dtsi b/qcom/sa6155p-vm-usb.dtsi index 9fc20ab70033..46c8590566b7 100644 --- a/qcom/sa6155p-vm-usb.dtsi +++ b/qcom/sa6155p-vm-usb.dtsi @@ -1,5 +1,3 @@ -#include -#include #include &soc { diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index d05b4a78d23d..9e59be2a0196 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -1,9 +1,5 @@ #include #include -#include -#include -#include -#include #include "quin-vm-common.dtsi" / { diff --git a/qcom/sa8155-vm-pcie.dtsi b/qcom/sa8155-vm-pcie.dtsi index 9f935edf9c43..79be17ecc8b6 100644 --- a/qcom/sa8155-vm-pcie.dtsi +++ b/qcom/sa8155-vm-pcie.dtsi @@ -1,7 +1,3 @@ -#include -#include - - &soc { pcie0: qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi index 9269e084ff3a..21723136431f 100644 --- a/qcom/sa8155-vm-usb.dtsi +++ b/qcom/sa8155-vm-usb.dtsi @@ -1,5 +1,3 @@ -#include -#include #include &soc { diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index f018c755ef3f..60d50ca07a64 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,9 +1,5 @@ #include #include -#include -#include -#include -#include #include "quin-vm-common.dtsi" / { diff --git a/qcom/sa8195-vm-pcie.dtsi b/qcom/sa8195-vm-pcie.dtsi index 44c9d2b10f62..fda8aeccea73 100644 --- a/qcom/sa8195-vm-pcie.dtsi +++ b/qcom/sa8195-vm-pcie.dtsi @@ -1,6 +1,3 @@ -#include -#include - &soc { pcie0: qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; @@ -221,6 +218,8 @@ status = "disabled"; pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; reg = <0 0 0 0 0>; pci-ids = "17cb:0109"; }; @@ -523,6 +522,8 @@ status = "disabled"; pcie_rc1: pcie_rc1 { + #address-cells = <5>; + #size-cells = <0>; reg = <0 0 0 0 0>; pci-ids = "17cb:0109"; }; @@ -827,6 +828,8 @@ pcie_rc2: pcie_rc2 { reg = <0 0 0 0 0>; pci-ids = "17cb:0109"; + #address-cells = <5>; + #size-cells = <0>; }; }; diff --git a/qcom/sa8195-vm-ufs.dtsi b/qcom/sa8195-vm-ufs.dtsi index 56d4e8f17db7..c6d35366d766 100644 --- a/qcom/sa8195-vm-ufs.dtsi +++ b/qcom/sa8195-vm-ufs.dtsi @@ -1,5 +1,3 @@ -#include - ®ulator { L17A: pm8195_1_l17: regulator-pm8195-1-l17 { regulator-name = "ldoa17"; diff --git a/qcom/sa8195-vm-usb.dtsi b/qcom/sa8195-vm-usb.dtsi index 83dfbfacd778..1231d3481514 100644 --- a/qcom/sa8195-vm-usb.dtsi +++ b/qcom/sa8195-vm-usb.dtsi @@ -1,6 +1,5 @@ -#include #include -#include + &soc { /* Primary USB port related controller */ usb0: ssusb@a600000 { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 59e6cc3f821a..923ef5210371 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -1,10 +1,5 @@ #include #include -#include -#include -#include -#include -#include #include "quin-vm-common.dtsi" / { From 1f891a34fb654865ff41027a9a6fd67a69649b44 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 19 Nov 2020 22:01:53 +0530 Subject: [PATCH 1273/1809] ARM: dts: msm: Remove duplicate dt node for qupv3 from sm8150 Remove duplicate dt node for qupv3 from sm8150 base dtsi file, the relevant support is present in sm8150-qupv3.dtsi file. Change-Id: Iee75e0619bdaafd67d77fe6da29820d5a737fac4 --- qcom/sm8150.dtsi | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index a4a555204eb4..af6f50f02244 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1483,28 +1483,6 @@ qcom,guard-memory; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x00ac0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "ok"; - - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "ok"; - }; - }; - tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; From 0265e253b28acf7f61fd500190511fcda8c8f227 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 19 Apr 2021 14:41:57 -0700 Subject: [PATCH 1274/1809] ARM: dts: msm: Use svs bus voting with USB on sdxlemur USB can operate when system is in SVS mode. Hence use svs bus voting instead of nominal bus voting on sdxlemur. Change-Id: I0bd6421d54de5bc5235d557e131a92ae2840b21d --- qcom/sdxlemur-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 7eba656d4638..0bdfd4c640f4 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -54,6 +54,7 @@ <&system_noc MASTER_USB3 &system_noc SLAVE_IPA_CFG>, <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3>; + qcom,default-bus-vote = <2>; /* use svs bus voting */ dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; From 3acf5c1bb023ed468ab480c51a4c8051f13a9f3a Mon Sep 17 00:00:00 2001 From: nishant raj Date: Thu, 15 Apr 2021 13:35:27 +0530 Subject: [PATCH 1275/1809] ARM: dts: msm: Enable QCPE on direwolf vm Added scm node in firmware to enable QCPE FE. Change-Id: I8edcad31d8098cd15614210d5e8fb666bb42f786 --- qcom/direwolf-vm.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 5b03442bd334..e3f08021f0d0 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -242,6 +242,12 @@ }; }; +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + #include "direwolf-pinctrl.dtsi" #include "direwolf-qupv3.dtsi" #include "pm8540-vm.dtsi" From 3529eb3cb31c8cab01aae7dd1cab72c191aec0c7 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 19 Apr 2021 20:52:07 +0530 Subject: [PATCH 1276/1809] ARM: dts: msm: Add skin, modem and junction thermal config for YUPIK Add queit-therm, modem-lte-sub6-pa, camera and video sensors mitigation config based on latest recommendation for yupik. Change-Id: I7ecbb36e88208c6c30df0c3c0a40a685624d6602 --- qcom/yupik-qrd.dtsi | 70 ++++++++++++++++- qcom/yupik-thermal.dtsi | 162 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 226 insertions(+), 6 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index cebfeb233046..c9db2290ae63 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -272,6 +272,42 @@ thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; trips { + quiet_skin_trip0: quiet-skin-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_batt_trip0: quiet-batt-trip0 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_skin_trip1: quiet-skin-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_batt_trip1: quiet-batt-trip1 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip2: quiet-batt-trip2 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip3: quiet-batt-trip3 { + temperature = <49000>; + hysteresis = <1000>; + type = "passive"; + }; + quiet_apc_trip: quiet-apc-trip { temperature = <50000>; hysteresis = <0>; @@ -329,9 +365,39 @@ cooling-device = <&cdsp_sw 4 4>; }; - modem-pa-cdev { + skin-cdev0 { + trip = <&quiet_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + skin-cdev1 { + trip = <&quiet_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + skin-cdev2 { trip = <&quiet_cx_trip>; - cooling-device = <&modem_pa 3 3>; + cooling-device = <&modem_skin 3 3>; + }; + + batt-cdev0 { + trip = <&quiet_batt_trip0>; + cooling-device = <&battery_charger 4 4>; + }; + + batt-cdev1 { + trip = <&quiet_batt_trip1>; + cooling-device = <&battery_charger 8 8>; + }; + + batt-cdev2 { + trip = <&quiet_batt_trip2>; + cooling-device = <&battery_charger 12 12>; + }; + + batt-cdev3 { + trip = <&quiet_batt_trip3>; + cooling-device = <&battery_charger 16 16>; }; }; }; diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 644d307e781d..579811c898ca 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -259,6 +259,94 @@ }; }; + modem-sub6-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + sub6_pa1_trip0: sub6-pa1-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip1: sub6-pa1-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip2: sub6-pa1-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_fr1_cdev0 { + trip = <&sub6_pa1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + pa_fr1_cdev1 { + trip = <&sub6_pa1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + pa_fr1_cdev2 { + trip = <&sub6_pa1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; + + modem-lte-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + sub6_pa2_trip0: sub6-pa2-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip1: sub6-pa2-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip2: sub6-pa2-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_cdev0 { + trip = <&sub6_pa2_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + pa_cdev1 { + trip = <&sub6_pa2_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + pa_cdev2 { + trip = <&sub6_pa2_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -1277,7 +1365,7 @@ }; cooling-maps { - cdsp-cdev { + cdsp_cdev { trip = <&nspss0_trip>; cooling-device = <&cdsp_sw 4 4>; }; @@ -1289,7 +1377,7 @@ THERMAL_MAX_LIMIT>; }; - modem-pa-cdev { + modem_pa_cdev { trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; }; @@ -1310,7 +1398,7 @@ }; cooling-maps { - cdsp-cdev { + cdsp_cdev { trip = <&nspss1_trip>; cooling-device = <&cdsp_sw 4 4>; }; @@ -1322,13 +1410,46 @@ THERMAL_MAX_LIMIT>; }; - modem-pa-cdev { + modem_pa_cdev { trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; }; }; }; + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 5>; + trips { + video_trip: video-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp_cdev { + trip = <&video_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu_cdev { + trip = <&video_trip>; + /* throttle to 315000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem_pa_cdev { + trip = <&video_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + mdmss-0-step { polling-delay-passive = <0>; polling-delay = <0>; @@ -1501,6 +1622,39 @@ }; }; + camera-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 11>; + trips { + camera_trip: camera-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu_cdev { + trip = <&camera_trip>; + /* throttle to 315000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem_pa_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + mx-pe-step { polling-delay-passive = <0>; polling-delay = <0>; From d40decae68312d586860b3c62307e8ccfabc1a79 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 19 Apr 2021 23:14:13 +0530 Subject: [PATCH 1277/1809] ARM: dts: msm: Update Ibat threshold and BCL thermal config for YUPIK Update ibat level0 threshold to 5A based on latest recommendation. Remove GPU mitigation rules from BCL thermalzone config as GPU driver itself monitors BCL irq on CB and mitigates its frequency. Change-Id: I73f3fbab2e949cee957c09325f6fb4364bdead60 --- qcom/yupik-thermal-overlay-qrd.dtsi | 98 +++++++++++++++++------------ qcom/yupik-thermal-overlay.dtsi | 76 ++++++++++------------ 2 files changed, 90 insertions(+), 84 deletions(-) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 4d302f1cff41..1b35cdcf63e9 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -33,6 +33,14 @@ }; }; + pm8350b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <5000>; + }; + }; + }; + pm8350b-bcl-lvl0 { cooling-maps { vbat_cpu4 { @@ -45,50 +53,55 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { + vbat_cpu6 { trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vbat_cdsp0 { trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; pm8350b-bcl-lvl1 { cooling-maps { - vbat_cpu6 { + vbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vbat_cpu7 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vbat_cdsp1 { trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vbat_modem2 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; pm8350b-bcl-lvl2 { cooling-maps { - vbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vbat_cdsp2 { trip = <&b_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -110,52 +123,57 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { + vph_cpu6 { trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vph_cdsp0 { trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vph_modem0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vph_modem1 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&c_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&c_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vph_cdsp1 { trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vph_modem2 { + trip = <&c_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 6e1e1f9389e4..08629122a0e4 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -33,6 +33,14 @@ }; }; + pm7325b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <5000>; + }; + }; + }; + pm7325b-bcl-lvl0 { cooling-maps { vbat_cpu4 { @@ -45,9 +53,14 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { + vbat_cpu6 { trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vbat_cdsp0 { @@ -69,19 +82,10 @@ pm7325b-bcl-lvl1 { cooling-maps { - vbat_cpu6 { + vbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vbat_cpu7 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vbat_cdsp1 { @@ -89,7 +93,7 @@ cooling-device = <&cdsp_sw 4 4>; }; - vbat_modem0 { + vbat_modem2 { trip = <&b_bcl_lvl1>; cooling-device = <&modem_tj 3 3>; }; @@ -98,12 +102,6 @@ pm7325b-bcl-lvl2 { cooling-maps { - vbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vbat_cdsp2 { trip = <&b_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -125,9 +123,14 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { + vph_cpu6 { trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vph_cdsp0 { @@ -135,12 +138,12 @@ cooling-device = <&cdsp_sw 2 2>; }; - vbat_modem0 { + vph_modem0 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_pa 2 2>; }; - vbat_modem1 { + vph_modem1 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_tj 1 1>; }; @@ -150,19 +153,10 @@ pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&c_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&c_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vph_cdsp1 { @@ -170,7 +164,7 @@ cooling-device = <&cdsp_sw 4 4>; }; - vbat_modem0 { + vph_modem2 { trip = <&c_bcl_lvl1>; cooling-device = <&modem_tj 3 3>; }; @@ -180,12 +174,6 @@ pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT From df7290d8c1a4b648ccabae934f997cdbe954aecd Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Tue, 13 Apr 2021 15:43:18 +0800 Subject: [PATCH 1278/1809] ARM: dts: msm: delete rename-blk on sa8195 LXC VM As avb2.0 is not ready, remove rename-blk node. Change-Id: I734aa23480b7b30cd02e27a95d7911166a677d8f --- qcom/sa8195-vm-lv-lxc.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 831afe1de548..25ad1d85ddbb 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -13,14 +13,6 @@ }; }; -/ { - rename_blk: rename_blk { - compatible = "qcom,blkdev-rename"; - actual-dev = "vda"; - rename-dev = "system"; - }; -}; - &usb0 { status = "ok"; }; From 28c451705049fe91aed1aae7af118ccb694e9e5a Mon Sep 17 00:00:00 2001 From: Srinu Gorle Date: Fri, 5 Feb 2021 10:42:14 +0530 Subject: [PATCH 1279/1809] dt-bindings: Add DT bindings for scuba Add DT binding for video encoders and decoders on scuba. Change-Id: I7e35f1c660c23fd784092b3a9f596b40eb10bf87 --- bindings/media/video/msm-vidc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index abaa26e4c0ce..486c3d089276 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -13,6 +13,7 @@ Required properties: - "qcom,sm8150-vidc" : Invokes driver specific data for SM8150. - "qcom,scshrike-vidc" : Invokes driver specific data for SA8195. - "qcom,sm6150-vidc" : Invokes driver specific data for SA6155. + - "qcom,scuba-vidc" : Invokes driver specific data for SCUBA. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL From 2be548767cf8a35511a4d1679065da245a7b0efb Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Tue, 20 Apr 2021 18:09:56 +0530 Subject: [PATCH 1280/1809] ARM: dts: msm: Correcting watchdog node in blair-rumi.dtsi Correcting watchdog node in blair-rumi.dtsi Change-Id: I28fb0753b0be206435111e1e5d012bcdc6380f90 --- qcom/blair-rumi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 6994b5445b9b..339858337ed2 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -8,7 +8,7 @@ clock-frequency = <500000>; }; - wdog { + wdog: qcom,wdt@f410000 { status = "disabled"; }; From c6c0e850e5411259bc3a29de972b39bc0a6ba2dd Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 20 Apr 2021 17:51:42 +0530 Subject: [PATCH 1281/1809] ARM: dts: msm: Remove SDPM and policy-engine support for YUPIK Remove SDPM and policy-engine support based on latest recommondation for YUPIK. Change-Id: I7bf2d81913d13f448fac22aebfb46097ba93e2ea --- qcom/yupik-thermal.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 579811c898ca..9898b8d44e90 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -70,6 +70,7 @@ <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; csr-id = <1 4>; + status = "disabled"; }; cx_sdpm@0x00634000 { @@ -80,6 +81,7 @@ <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; csr-id = <0 2>; + status = "disabled"; }; mx_pe: mx_rdpm_pe@0x00637000 { @@ -87,6 +89,7 @@ #thermal-sensor-cells = <0>; reg = <0x00637000 0x1000>; interrupts = ; + status = "disabled"; }; cx_pe: cx_rdpm_pe@0x00635000 { @@ -94,6 +97,7 @@ #thermal-sensor-cells = <0>; reg = <0x00635000 0x1000>; interrupts = ; + status = "disabled"; }; }; @@ -1660,6 +1664,7 @@ polling-delay = <0>; thermal-sensors = <&mx_pe>; thermal-governor = "step_wise"; + status = "disabled"; trips { mx_pe_config1: mx-pe-config1 { temperature = <1>; @@ -1723,6 +1728,7 @@ polling-delay = <0>; thermal-sensors = <&cx_pe>; thermal-governor = "step_wise"; + status = "disabled"; trips { cx_pe_config1: cx-pe-config1 { temperature = <1>; From 2e681f66a7c60ea101ddd385b5ee000fae965c9b Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Tue, 20 Apr 2021 11:31:52 -0700 Subject: [PATCH 1282/1809] ARM: dts: msm: Add entry to t_power_on scale and value on sdxlemur PCIe ASPM driver calculates the L1.2 threshold value based on t_common mode and t_power_on by reading from L1SUB capability register. t_power on scale and value are 0 power on default. Pass appropriate value to set the L1.2 threshold above 150us. Change-Id: I9ba7676b0548a6d3484a2aad27619a88f31b25d7 --- qcom/sdxlemur-pcie.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 62b45985834f..cdfb037da0ba 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -109,8 +109,8 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ - qcom,l1-2-th-scale = <2>; /* 1us */ - qcom,l1-2-th-value = <150>; + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From 8469561b3ff1508c43eab10b6217ffdf5827a09a Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 19 Apr 2021 15:49:40 -0700 Subject: [PATCH 1283/1809] ARM: dts: msm: Reduce USB IOVA address size by size of LLCC TCM memory This change reduces USB IOMMU address size by size of LLCC TCM memory (i.e. 128KB). This simplified allowing usage of DDR or LLCC TCM memory selection with USB RMNET IN buffer and need of changing anything with IPA side geometry fastmap mapping. Change-Id: I17335c9ac19b2bf1bf8005d485cc1f441aaf4d95 --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a4dac2bfbf67..d5ddf05c9d41 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -8,7 +8,7 @@ iommus = <&apps_smmu 0x1a0 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x40000000 0x60000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x5ffe0000>; #address-cells = <1>; #size-cells = <1>; ranges; From 4d76e19b3919f5a40116003bbdd4ee7ebced1543 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Mon, 29 Mar 2021 10:36:54 -0700 Subject: [PATCH 1284/1809] ARM: dts: msm: Set R8125B Rx ring size on sdxlemur To address IPA ring index overflow/wraparound limitations, Rx Desc size cannot be a power of 2. Change-Id: I45894e432eaec8dc3abd8625ed8c942df6e64be3 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index df7cb688557d..4aab30d9d047 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -39,7 +39,7 @@ qcom,dir-rx; qcom,rx-filter-ip; - qcom,ring-size = <1024>; + qcom,ring-size = <1023>; /* Cannot be a power of 2 */ qcom,buff-size = <2048>; qcom,mod-count-min = <32>; From 1101640bf90124745d2cd1d571b1faabe318b148 Mon Sep 17 00:00:00 2001 From: Yingjie Zhu Date: Thu, 8 Apr 2021 20:32:42 +0800 Subject: [PATCH 1285/1809] ARM: dts: msm: add bt power node for sa6155 add bt power node for sa6155 Change-Id: I52383b91f46edb954de750abacb676b301de7c73 --- qcom/sa6155-adp-common.dtsi | 1 + qcom/sa6155-cnss.dtsi | 43 +++++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 1 + 3 files changed, 45 insertions(+) create mode 100644 qcom/sa6155-cnss.dtsi diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index a0c21d604d6f..ff23e07f3486 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -1,5 +1,6 @@ #include #include +#include "sa6155-cnss.dtsi" &qupv3_se0_2uart { status = "ok"; diff --git a/qcom/sa6155-cnss.dtsi b/qcom/sa6155-cnss.dtsi new file mode 100644 index 000000000000..76ae6b88e3c6 --- /dev/null +++ b/qcom/sa6155-cnss.dtsi @@ -0,0 +1,43 @@ +&soc { + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 1 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 6 0>; + }; + + bluetooth_ext: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 85 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-rfa1-supply = <&pm6155_1_s6>; + qcom,bt-vdd-rfa2-supply = <&pm6155_1_s5>; + qcom,bt-vdd-rfa3-supply = <&pm6155_1_l15>; + + /* */ + qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1904000 1904000 450000 0>; + }; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 11d351da53f3..78243da492ec 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -37,6 +37,7 @@ sdhc0 = &sdhc_1; sdhc1 = &sdhc_2; spi10 = &qupv3_se10_spi; + hsuart0 = &qupv3_se7_4uart; }; cpus { From de9fcec29d460041bfe93dc8659484bca53fe430 Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Thu, 8 Apr 2021 20:39:21 +0800 Subject: [PATCH 1286/1809] ARM: dts: msm: include sdmshrike-vm-lv-display.dtsi This adds four display sde-kms-hyp nodes for multi cards case. Change-Id: I07e45c04867fa1c8ae371247b56cefdfd9694c09 --- qcom/sa8195-vm-lv-lxc.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 25ad1d85ddbb..50f012dfe677 100644 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -13,6 +13,8 @@ }; }; +#include "display/sdmshrike-vm-lv-display.dtsi" + &usb0 { status = "ok"; }; From 7d5dd223b21700ffaecadbc6bb662fcd919413d7 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 8 Dec 2020 11:00:37 +0530 Subject: [PATCH 1287/1809] dt-bindings: interconnect: add interconnect bindings for direwolf l3 Add interconnect device bindings. These devices can be used to describe L3 based interconnect devices. Change-Id: Ibb88f58032eadf5bb0a8ec397a47e49bd69a7193 --- bindings/interconnect/qcom,epss-l3.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index d3a31ad4e6df..0839062fa26e 100644 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -9,8 +9,9 @@ Required properties : "qcom,lahaina-epss-l3-shared", "qcom,lahaina-epss-l3-cpu", "qcom,shima-epss-l3-cpu", - "qcom,shima-epss-l3-shared"; + "qcom,shima-epss-l3-shared", "qcom,yupik-epss-l3-cpu", + "qcom,direwolf-epss-l3-cpu"; - reg : Address and length of the register set for the device - clock-names: should contain "xo", "alternate" - clocks: list of phandle and clock specifier pairs corresponding to From 61962589a7aa5772383358ab3f2932a61e872e25 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sun, 6 Dec 2020 10:56:44 +0530 Subject: [PATCH 1288/1809] ARM: dts: msm: add SPMI PMIC arbiter and PMIC devices for direwolf Add an SPMI PMIC arbiter device so that it is possible to communicate with PMICs attached to the SPMI bus and also add top level slave devices and their peripherals. Change-Id: If999da320e3212e787af6d22ceed562b808cf690 --- qcom/direwolf-adas.dtsi | 1 + qcom/direwolf-ivi.dtsi | 1 + qcom/direwolf-pmic.dtsi | 115 +++++++++++++ qcom/direwolf.dtsi | 22 +++ qcom/pm8540.dtsi | 364 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 503 insertions(+) create mode 100644 qcom/direwolf-pmic.dtsi create mode 100644 qcom/pm8540.dtsi diff --git a/qcom/direwolf-adas.dtsi b/qcom/direwolf-adas.dtsi index 589458f88196..97fb67c3ab6a 100644 --- a/qcom/direwolf-adas.dtsi +++ b/qcom/direwolf-adas.dtsi @@ -1,4 +1,5 @@ #include "direwolf.dtsi" +#include "direwolf-pmic.dtsi" / { model = "Qualcomm Technologies, Inc. DirewolfAU ADAS SoC"; diff --git a/qcom/direwolf-ivi.dtsi b/qcom/direwolf-ivi.dtsi index 9f12fa8801c1..b03269553b70 100644 --- a/qcom/direwolf-ivi.dtsi +++ b/qcom/direwolf-ivi.dtsi @@ -1,5 +1,6 @@ #include "direwolf.dtsi" #include "direwolf-ivi-regulators.dtsi" +#include "direwolf-pmic.dtsi" / { model = "Qualcomm Technologies, Inc. DirewolfAU IVI SoC"; diff --git a/qcom/direwolf-pmic.dtsi b/qcom/direwolf-pmic.dtsi new file mode 100644 index 000000000000..a41671dade16 --- /dev/null +++ b/qcom/direwolf-pmic.dtsi @@ -0,0 +1,115 @@ +#include "pm8540.dtsi" + +&thermal_zones { + pm8540_1_temp_alarm: pm8540_1_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8540_1_tz>; + wake-capable-sensor; + + trips { + pm8540_1_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8540_1_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8540_2_temp_alarm: pm8540_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8540_2_tz>; + wake-capable-sensor; + + trips { + pm8540_2_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8540_2_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8540_3_temp_alarm: pm8540_3_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8540_3_tz>; + wake-capable-sensor; + + trips { + pm8540_3_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8540_3_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8540_4_temp_alarm: pm8540_4_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8540_4_tz>; + wake-capable-sensor; + + trips { + pm8540_4_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8540_4_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 6cb13e465868..3a255032a8dd 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -890,6 +890,28 @@ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; diff --git a/qcom/pm8540.dtsi b/qcom/pm8540.dtsi new file mode 100644 index 000000000000..d4efec80f2a0 --- /dev/null +++ b/qcom/pm8540.dtsi @@ -0,0 +1,364 @@ +#include +#include +#include +#include +#include +#include + + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8540@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8540_1_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8540_1_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm8540_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8540_1_div_clk1", + "pm8540_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8540_1_rtc: qcom,pm8540_1_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8540_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8540_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100>; + }; + + }; + + qcom,pm8540@1 { + compatible ="qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm8540 */ + qcom,pm8540@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_2_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8540_2_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8540_2_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8540_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8540_2_div_clk1", + "pm8540_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + status = "disabled"; + }; + + pm8540_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* below definitions are for the third instance of pm8540 */ + qcom,pm8540@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_3_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8540_3_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8540_3_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8540_3_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8540_3_div_clk1", + "pm8540_3_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + status = "disabled"; + }; + + pm8540_3_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@9 { + compatible ="qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* below definitions are for the forth instance of pm8540 */ + qcom,pm8540@C { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_4_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xC 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm8540_4_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8540_4_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0xC 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm8540_4_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8540_4_div_clk1", + "pm8540_4_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + status = "disabled"; + }; + + pm8540_4_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@D { + compatible ="qcom,spmi-pmic"; + reg = <13 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From 006c01fe456cd02c0bd4cabc8765944180d1a62e Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Tue, 20 Apr 2021 21:55:49 -0700 Subject: [PATCH 1289/1809] ARM: dts: msm: Enable Virtual SSR for the Direwolf VM Enable virtual SSR notifications for the CDSP0 domain on the Direwolf VM. Change-Id: I83527bad57ead57bc688b089a5a08ec787fe0836 --- qcom/direwolf-vm.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 34d8081d5e42..1bf42e9e0b2c 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -193,6 +193,19 @@ interrupt-parent = <&intc>; interrupt-controller; }; + + subsys_notif_virt: qcom,subsys_notif_virt@2D000000 { + compatible = "qcom,subsys-notif-virt"; + reg = <0x2D000000 0x400>; + reg-names = "vdev_base"; + cdsp0 { + subsys-name = "cdsp0"; + interrupts = ; + interrupt-names = "state-irq"; + type = "virtual"; + offset = <768>; + }; + }; }; ®ulator { From 26ab35860bcb889c0e98b7351b3c8fb32d85839e Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Mon, 19 Apr 2021 15:14:52 +0530 Subject: [PATCH 1290/1809] ARM: dts: msm: Add initial device tree for SCUBA Add initial device tree support for SCUBA target on QRB2210-RB1 platform. Change-Id: Ie0c29614986254f701f7c11bbf2cb737dc23f297 --- qcom/Makefile | 2 + qcom/msm-arm-smmu-qrb2210-rb1.dtsi | 196 +++++ qcom/qrb2210-rb1-idp.dtsi | 41 + qcom/qrb2210-rb1-ion.dtsi | 36 + qcom/qrb2210-rb1-pinctrl.dtsi | 1095 +++++++++++++++++++++++ qcom/qrb2210-rb1-regulator.dtsi | 348 ++++++++ qcom/qrb2210-rb1.dts | 11 + qcom/qrb2210-rb1.dtsi | 1291 ++++++++++++++++++++++++++++ 8 files changed, 3020 insertions(+) create mode 100644 qcom/msm-arm-smmu-qrb2210-rb1.dtsi create mode 100644 qcom/qrb2210-rb1-idp.dtsi create mode 100644 qcom/qrb2210-rb1-ion.dtsi create mode 100644 qcom/qrb2210-rb1-pinctrl.dtsi create mode 100644 qcom/qrb2210-rb1-regulator.dtsi create mode 100644 qcom/qrb2210-rb1.dts create mode 100644 qcom/qrb2210-rb1.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 229cdd699c4f..7103be9c6413 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -227,6 +227,8 @@ else dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb endif +dtb-$(CONFIG_ARCH_SCUBA) += qrb2210-rb1.dtb + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) dtbo-$(CONFIG_ARCH_SA8155) += \ diff --git a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi new file mode 100644 index 000000000000..bb960362ef1a --- /dev/null +++ b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi @@ -0,0 +1,196 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x59a0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x59a0000 0x10000>, + <0x59c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,no-dynamic-asid; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + #size-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* ALL CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x30B>; + + gfx_0_tbu: gfx_0_tbu@0x59c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x59c5000 0x1000>, + <0x59c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + }; + }; + + apps_smmu: apps-smmu@0xc600000 { + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc782000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + + qcom,actlr = + /* For rt TBU +3 deep PF */ + <0x400 0x3ff 0x103>, + /* For nrt TBU +3 deep PF */ + <0x800 0x3ff 0x103>; + + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc785000 0x1000>, + <0xc782200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc789000 0x1000>, + <0xc782208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc78d000 0x1000>, + <0xc782210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&kgsl_smmu 0x7 0x0>; + status = "disabled"; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E0 0x0>; + status = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E1 0x0>; + dma-coherent; + status = "disabled"; + }; +}; diff --git a/qcom/qrb2210-rb1-idp.dtsi b/qcom/qrb2210-rb1-idp.dtsi new file mode 100644 index 000000000000..6a6c301959cb --- /dev/null +++ b/qcom/qrb2210-rb1-idp.dtsi @@ -0,0 +1,41 @@ +#include +#include +#include "qrb2210-rb1-ion.dtsi" + +&soc { + scuba_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm2250_qg { + qcom,battery-data = <&scuba_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; +}; + +&pm2250_charger { + interrupts-extended = <&tlmm 89 0>; + interrupt-names = "usb_id_irq"; + qcom,usb-id-gpio = <&tlmm 89 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_interrupt>; + + qcom,auto-recharge-soc = <98>; + qcom,suspend-input-on-debug-batt; + qcom,battery-data = <&scuba_batterydata>; + io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>, + <&pm2250_vadc ADC5_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "chg_temp"; + qcom,thermal-mitigation = <2000000 1500000 1000000 500000>; +}; diff --git a/qcom/qrb2210-rb1-ion.dtsi b/qcom/qrb2210-rb1-ion.dtsi new file mode 100644 index 000000000000..c19c0bf75298 --- /dev/null +++ b/qcom/qrb2210-rb1-ion.dtsi @@ -0,0 +1,36 @@ +#include +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/qrb2210-rb1-pinctrl.dtsi b/qcom/qrb2210-rb1-pinctrl.dtsi new file mode 100644 index 000000000000..e292ad133313 --- /dev/null +++ b/qcom/qrb2210-rb1-pinctrl.dtsi @@ -0,0 +1,1095 @@ +&soc { + tlmm: pinctrl@500000 { + compatible = "qcom,scuba-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&wakegic>; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup4"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* WSA speaker reset pin1 */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + fsa_usbc_ana_en_n@102 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_ctsrtsrx: + qupv3_se3_default_ctsrtsrx { + mux { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: + qupv3_se3_default_tx { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_ctsrx: qupv3_se3_ctsrx { + mux { + pins = "gpio8", "gpio11"; + function = "qup3"; + }; + + config { + pins = "gpio8", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio9"; + function = "qup3"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio10"; + function = "qup3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio80", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pm8008_interrupt: pm8008_interrupt { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; + input-enable; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active { + /*CSIMUX_OE*/ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend { + /* CSIMUX_OE */ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active { + /*CSIMUX_SEL*/ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend { + /* CSIMUX_SEL */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + gpio_vol_up: gpio_vol_up { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + usb_id_interrupt: usb_id_interrupt { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + bias-pull-up; + input-enable; + }; + }; + }; +}; diff --git a/qcom/qrb2210-rb1-regulator.dtsi b/qcom/qrb2210-rb1-regulator.dtsi new file mode 100644 index 000000000000..a1344d005c24 --- /dev/null +++ b/qcom/qrb2210-rb1-regulator.dtsi @@ -0,0 +1,348 @@ +#include +#include + +&rpm_bus { + /* PM2250 S2 - VDD_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + + VDD_CX_LEVEL: + VDD_GFX_LEVEL: + VDD_MSS_LEVEL: + S2A_LEVEL: pm2250_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + VDD_MSS_FLOOR_LEVEL: + S2A_FLOOR_LEVEL: + pm2250_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + VDD_MSS_LEVEL_AO: + S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* PM2250 L1 - VDD_MX/WCSS_MX supply */ + rpm-regulator-ldoa1 { + status = "okay"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + + VDD_MX_LEVEL: + L1A_LEVEL: pm2250_l1_level: regulator-l1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + L1A_FLOOR_LEVEL: + pm2250_l1_floor_level: regulator-l1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + S3A: pm2250_s3: regulator-s3 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1662500>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + S4A: pm2250_s4: regulator-s4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2350000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa8 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + + VDD_LPI_CX_LEVEL: + L8A_LEVEL: pm2250_l8_level: regulator-l8-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l8_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + + VDD_LPI_MX_LEVEL: + L9A_LEVEL: pm2250_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm2250_l2: regulator-l2 { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1060000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + L3A: pm2250_l3: regulator-l3 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <570000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm2250_l4: regulator-l4 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm2250_l5: regulator-l5 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1312000>; + qcom,init-voltage = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm2250_l6: regulator-l6 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + /* WCSS_CX */ + rpm-regulator-ldoa7 { + status = "okay"; + WCSS_CX: + L7A: pm2250_l7: regulator-l7 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm2250_l10: regulator-l10 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + qcom,init-voltage = <1150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm2250_l11: regulator-l11 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm2250_l12: regulator-l12 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm2250_l13: regulator-l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm2250_l14: regulator-l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm2250_l15: regulator-l15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm2250_l16: regulator-l16 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1500000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm2250_l17: regulator-l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm2250_l18: regulator-l18 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm2250_l19: regulator-l19 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm2250_l20: regulator-l20 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm2250_l21: regulator-l21 { + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2921000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm2250_l22: regulator-l22 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; +}; diff --git a/qcom/qrb2210-rb1.dts b/qcom/qrb2210-rb1.dts new file mode 100644 index 000000000000..44fabbe458f6 --- /dev/null +++ b/qcom/qrb2210-rb1.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +//#include "qrb2210-rb1.dtsi" +//#include +//#include "qrb2210-rb1-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IOT SoC"; + compatible = "qcom,scuba-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi new file mode 100644 index 000000000000..480a441b3dec --- /dev/null +++ b/qcom/qrb2210-rb1.dtsi @@ -0,0 +1,1291 @@ +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Qrb2210 RB1"; + compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp"; + qcom,msm-id = <473 0x0>; + qcom,board-id = <34 0>; + + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + swr0 = &swr0; + swr1 = &swr1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = + "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x100000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_adsp_mem: adsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1c00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@53600000 { + no-map; + reg = <0x0 0x53600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + no-map; + reg = <0x0 0x53610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@53615000 { + no-map; + reg = <0x0 0x53615000 0x0 0x2000>; + }; + + removed_region: removed_region@60000000 { + no-map; + reg = <0x0 0x60000000 0x0 0x3900000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-scuba", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + status="disabled"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + status="disabled"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + status="disabled"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + + status="disabled"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + thermal_zones: thermal-zones { }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + status="disabled"; + feat_conf5: feat_conf5@6018 { + reg = <0x6018 0x4>; + }; + + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; + + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + +dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bee000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x2000>; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,scuba-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + + }; + + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; + }; + + qcom,lpass@ab00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xab00000 0x00100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <1>; + qcom,minidump-id = <5>; + qcom,ssctl-instance-id = <0x14>; + qcom,pas-id = <1>; + qcom,smem-id = <423>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + pil_modem: qcom,mss@6080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x6080000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + qcom,sequential-fw-load; + + /* Inputs from mss */ + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom_scm: qcomscm { + compatible = "qcom,scm"; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + audio_gpr: qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,intents = <0x200 20>; + reg = ; + spf_core { + compatible = "qcom,spf_core"; + reg = ; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = ; + }; + + audio_prm: q6prm { + compatible = "qcom,audio_prm"; + reg = ; + }; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical","slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x360>; + status = "ok"; + }; + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1A0 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + vdd-cx-mx-supply = <&L7A>; + vdd-1.8-xo-supply = <&L13A>; + vdd-1.3-rfa-supply = <&L10A>; + vdd-3.3-ch0-supply = <&L22A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; +}; + +#include "pm2250.dtsi" +#include "pm2250-rpm-regulator.dtsi" +#include "qrb2210-rb1-regulator.dtsi" +#include "qrb2210-rb1-pinctrl.dtsi" +#include "qrb2210-rb1-ion.dtsi" +#include "msm-arm-smmu-qrb2210-rb1.dtsi" + +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + }; + + pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + pm8008_en-supply = <&PM8008_EN>; + + vdd_l1_l2-supply = <&S3A>; + + L1P: qcom,pm8008-l1@4000 { + reg = <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1256000>; + qcom,min-dropout-voltage = <75000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1144000>; + qcom,min-dropout-voltage = <187500>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4500 { + reg = <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4600 { + reg = <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1656000>; + regulator-max-microvolt = <1896000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + }; + }; +}; + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm2250_vadc ADC5_GPIO3_100K_PU>, + <&pm2250_vadc ADC5_GPIO4_100K_PU>, + <&pm2250_vadc ADC5_SBUx>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + s3_die_temp { + reg = ; + }; + }; + }; +}; From 3ff8221511d6fb35396792b06306a4a412d609b3 Mon Sep 17 00:00:00 2001 From: nishant raj Date: Thu, 22 Apr 2021 09:41:20 +0530 Subject: [PATCH 1291/1809] ARM: dts: msm: Indentation issue for qcom,scm on direwolf vm Indentation issue for qcom,scm on direwolf vm Change-Id: Idcd8b186e8d8c6f86872f8e2395817c516cfa4c3 --- qcom/direwolf-vm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 34d8081d5e42..25314c32d5d9 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -243,8 +243,8 @@ &firmware { scm { - compatible = "qcom,scm"; - }; + compatible = "qcom,scm"; + }; }; #include "direwolf-pinctrl.dtsi" From 6a9695b87e7f97d6ecf7c1490fe846d5487a8dfd Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 19 Apr 2021 17:11:34 +0530 Subject: [PATCH 1292/1809] ARM: dts: msm: Fix DDR OPP table entries DDR OPP table entries were missing the opp-supported-hw property. Add the missing property. Change-Id: I46608517649ef5620ab7e5f4f8933989368de169 --- qcom/sm6150.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 78243da492ec..31615b302bf2 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -593,16 +593,16 @@ ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; - BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY_DDR( 200, 4, 0x80); /* 762 MB/s */ + BW_OPP_ENTRY_DDR( 300, 4, 0x80); /* 1144 MB/s */ + BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */ + BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */ + BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */ + BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */ + BW_OPP_ENTRY_DDR(1017, 4, 0x80); /* 3879 MB/s */ + BW_OPP_ENTRY_DDR(1353, 4, 0x80); /* 5161 MB/s */ + BW_OPP_ENTRY_DDR(1555, 4, 0x80); /* 5931 MB/s */ + BW_OPP_ENTRY_DDR(1804, 4, 0x80); /* 6881 MB/s */ }; cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { From 0c6a7dc854324396ec14e64eb3528657f20dc007 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 2 Mar 2021 17:05:28 +0530 Subject: [PATCH 1293/1809] ARM: dts: msm: Add wakeup support for SDIO Add wakeup support for SDIO. Change-Id: I5c894c6c8f08357c3481d78d7569a23d7f01d2f4 --- qcom/sdxnightjar-dualwifi-512mb-mtp.dts | 11 +++++++++++ qcom/sdxnightjar-dualwifi-mtp.dts | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/qcom/sdxnightjar-dualwifi-512mb-mtp.dts b/qcom/sdxnightjar-dualwifi-512mb-mtp.dts index 512e1fc1b7d3..f28145937fda 100644 --- a/qcom/sdxnightjar-dualwifi-512mb-mtp.dts +++ b/qcom/sdxnightjar-dualwifi-512mb-mtp.dts @@ -25,5 +25,16 @@ pinctrl-0 = <&sdc2_on &sdc2_wlan_gpio_active>; pinctrl-1 = <&sdc2_off &sdc2_wlan_gpio_sleep>; + enable-sdio-wakeup; + #address-cells = <0>; + interrupt-parent = <&sdhc_1>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH + 1 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq"; + status = "ok"; }; diff --git a/qcom/sdxnightjar-dualwifi-mtp.dts b/qcom/sdxnightjar-dualwifi-mtp.dts index 2d84dcfb363d..f69d61971e2b 100644 --- a/qcom/sdxnightjar-dualwifi-mtp.dts +++ b/qcom/sdxnightjar-dualwifi-mtp.dts @@ -25,5 +25,16 @@ pinctrl-0 = <&sdc2_on &sdc2_wlan_gpio_active>; pinctrl-1 = <&sdc2_off &sdc2_wlan_gpio_sleep>; + enable-sdio-wakeup; + #address-cells = <0>; + interrupt-parent = <&sdhc_1>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH + 1 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm_pinmux 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq"; + status = "ok"; }; From 362e1f659d75f4ac0ef7501c28e5e9383009268d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sun, 8 Nov 2020 15:28:22 +0530 Subject: [PATCH 1294/1809] ARM: dts: msm: add interconnect devices for direwolf Add interconnect devices for direwolf. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I6cf0545e55eae62c76af0c9b291e8f901062ab2b --- qcom/direwolf.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 3a255032a8dd..561a8a51ce5b 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -5,6 +5,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. Direwolf"; @@ -401,6 +403,10 @@ compatible = "qcom,direwolf-rpmh-clk"; #clock-cells = <1>; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; pdc: interrupt-controller@b220000 { @@ -912,6 +918,100 @@ thermal_zones: thermal-zones { }; + clk_virt: interconnect@0 { + compatible = "qcom,direwolf-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,direwolf-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect@10c0000 { + compatible = "qcom,direwolf-nspa_noc"; + reg = <0x10C0000 0x10000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,direwolf-config_noc"; + reg = <0x1500000 0x2C000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,direwolf-system_noc_main"; + reg = <0x01680000 0x1A400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc:interconnect@16c0000 { + compatible = "qcom,direwolf-aggre1_noc"; + reg = <0x16C0000 0x3AF80>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,direwolf-aggre2_noc"; + reg = <0x1700000 0x3AF80>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,direwolf-mmss_noc"; + reg = <0x1740000 0x1FA80>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,direwolf-lpass_ag_noc"; + reg = <0x3C40000 0xF080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@90e0000 { + compatible = "qcom,direwolf-dc_noc"; + reg = <0x90E0000 0x5080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,direwolf-gem_noc"; + reg = <0x9100000 0xB8400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect@210C0000 { + compatible = "qcom,direwolf-nspb_noc"; + reg = <0x210C0000 0x10000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; From e633522ef78f9fecfbe40c6d092ac333908f7ffd Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 22 Apr 2021 15:26:32 +0530 Subject: [PATCH 1295/1809] ARM: dts: msm: Add ADC thermistors for sdxnightjar Add VADC and ADCTM channels with corresponding thermal zones for ADC thermistors under PMD9650 on sdxnightjar. Change-Id: I1fa2d9ad2a3eaaf0c3c250d671fb297e520095c6 --- qcom/pmd9650.dtsi | 8 ++ qcom/sdxnightjar.dtsi | 167 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+) diff --git a/qcom/pmd9650.dtsi b/qcom/pmd9650.dtsi index 03c2586b80de..4d0bf05aaae7 100644 --- a/qcom/pmd9650.dtsi +++ b/qcom/pmd9650.dtsi @@ -69,6 +69,14 @@ label = "ref_1p25"; qcom,pre-scaling = <1 1>; }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; }; qcom,pmd9650_rtc { diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 1238ce10e2af..b625affa3b88 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -1055,6 +1055,173 @@ #include "sdxnightjar-audio-overlay.dtsi" #include "sdxnightjar-thermal.dtsi" +&pmd9650_gpios { + ambient_therm { + ambient_therm_default: ambient_therm_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; +}; + +&pmd9650_vadc { + case_therm { + reg = ; + label = "case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ambient_therm { + reg = ; + label = "ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&spmi_bus { + qcom,pmd9650@0 { + pmd9650_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pmd9650_vadc ADC5_XO_THERM_100K_PU>, + <&pmd9650_vadc ADC5_AMUX_THM1_100K_PU>, + <&pmd9650_vadc ADC5_AMUX_THM2_100K_PU>, + <&pmd9650_vadc ADC5_AMUX_THM3_100K_PU>, + <&pmd9650_vadc ADC5_GPIO2_100K_PU>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmd9650_adc_tm_iio ADC5_XO_THERM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + case-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + ambient-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmd9650_adc_tm_iio ADC5_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + &i2c_3 { status = "ok"; smb1351_otg_supply: smb1351-charger@55 { From 0549f2f866332442eb92d9df143817aad0b9970f Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 28 Oct 2020 20:01:58 +0530 Subject: [PATCH 1296/1809] ARM: dts: msm: Enable L3 interconnect driver for direwolf Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: I71f7090e0ebbd428ae2e0d7044dc44397d19d68d --- qcom/direwolf.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 561a8a51ce5b..58db8e45f42d 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -1012,6 +1013,15 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + epss_l3_cpu: l3_cpu@18590000 { + reg = <0x18590000 0x3000>; + compatible = "qcom,direwolf-epss-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; From 32808e7ff0b43204e292e1f8c129474a2f2167d7 Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Mon, 22 Mar 2021 15:08:52 +0530 Subject: [PATCH 1297/1809] ARM: dts: qcom: add audio device tree source files Add audio device tree source files for monaco. Add spkr node in pinctrl. dt-bindings: sound: Add Documentation for besbev. Change-Id: I7d544d0a0563228a2f8ae262b6a2fab12d4941ed --- bindings/sound/qcom-audio-dev.txt | 137 ++++++++++ bindings/sound/wcd_codec.txt | 70 ++++++ qcom/monaco-amic-audio-overlay.dtsi | 197 +++++++++++++++ qcom/monaco-audio-overlay.dtsi | 234 +++++++++++++++++ qcom/monaco-audio.dtsi | 168 +++++++++++++ qcom/monaco-lpi.dtsi | 377 ++++++++++++++++++++++++++++ qcom/monaco-pinctrl.dtsi | 31 +++ qcom/monaco-wsa-audio-overlay.dtsi | 227 +++++++++++++++++ qcom/pm5100.dtsi | 4 + 9 files changed, 1445 insertions(+) create mode 100644 qcom/monaco-amic-audio-overlay.dtsi create mode 100644 qcom/monaco-audio-overlay.dtsi create mode 100644 qcom/monaco-audio.dtsi create mode 100644 qcom/monaco-lpi.dtsi create mode 100644 qcom/monaco-wsa-audio-overlay.dtsi diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index c910d433cd58..2b05028368b2 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1935,6 +1935,143 @@ Example: qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; }; +* MONACO ASoC Machine driver + +Required properties: +- compatible : "qcom,monaco-asoc-snd". +- qcom,model : The user-visible name of this sound card. +- qcom,audio-routing : A list of the connections between audio components. +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order given + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". + +Optional properties: +- qcom,msm-mi2s-master: This property is used to inform machine driver + if MSM is the clock master of mi2s. 1 means master and 0 means slave. The + first entry is primary mi2s; the second entry is secondary mi2s, and so on. +- qcom,wsa-max-devs : Maximum number of WSA883x devices present in the target +- qcom,wsa-devs : List of phandles for all possible WSA883x devices supported for the target +- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target +- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target +- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target +- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target +- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. +- qcom,msm_audio_ssr_devs: List the snd event framework clients +- qcom,afe-rxtx-lb: AFE RX to TX loopback. +- qcom,tlmm-gpio: TLMM gpio number for corresponding LPASS gpio +- qcom,va-bolero-codec: Property to specify VA macro supported. +- qcom,rxtx-bolero-codec: Property to specify RX-TX macros supported. +- qcom,wsa-bolero-codec: Property to specify WSA macro supported. + +Example: + monaco_snd: sound { + status = "okay"; + compatible = "qcom,monaco-asoc-snd"; + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec = <&stub_codec>, <&bolero>, + <&besbev_codec>, <&wsa883x_0221>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "besbev_codec", "wsa-codec1"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa883x_0221>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; + }; + * KONA ASoC Machine driver Required properties: diff --git a/bindings/sound/wcd_codec.txt b/bindings/sound/wcd_codec.txt index b23079a85418..63dd92296f1f 100644 --- a/bindings/sound/wcd_codec.txt +++ b/bindings/sound/wcd_codec.txt @@ -95,6 +95,9 @@ Example: rouleur_tx_slave: rouleur-tx-slave { compatible = "qcom,rouleur-slave"; }; + besbev_tx_slave: besbev-tx-slave { + compatible = "qcom,besbev-slave"; + }; }; }; }; @@ -135,6 +138,9 @@ Example: rouleur_rx_slave: rouleur-rx-slave { compatible = "qcom,rouleur-slave"; }; + besbev_rx_slave: besbev-rx-slave { + compatible = "qcom,besbev-slave"; + }; }; }; }; @@ -602,3 +608,67 @@ Example: qcom,cdc-on-demand-supplies = "cdc-pa-vpos"; }; }; + +PM5100 SPMI node + +pm5100_spmi: Child node of SPMI bus required for besbev codec + in order to access SPMI register to reset the peripheral. + +Required properties: + -compatible: "qcom,pm5100-spmi"; + +&spmi_bus { + pm5100_cdc: qcom,pm5100-cdc { + compatible = "qcom,pm5100-spmi"; + }; +}; + +Besbev Codec + +Required properties: + - compatible: "qcom,besbev-codec"; + - qcom,split-codec: Property to check on split codec support. + - qcom,swr_ch_map: mapping of swr tx/rx slave port configuration to port_type and also + corresponding master port type it need to attach. + format: + same port_id configurations have to be grouped, and in ascending order. + - qcom,pmic-spmi-node: Phandle reference to the PMIC SPMI DT node. + - qcom,wcd-reset-reg: Reset register address in PMIC for rouleur codec. + - qcom,besbev-slave: phandle reference of Soundwire Tx/Rx slave device. + - qcom,speaker-present: Property to check besbev is connected RX SWR or TX SWR of bolero codec. + +Optional properties: + + - cdc-mic-bias-supply: phandle of mic bias supply's regulator device tree node. + - qcom,cdc-mic-bias-voltage: mic bias supply's voltage level min and max in mV. + - qcom,cdc-mic-bias-current: mic bias supply's max current in mA. + + - qcom,cdc-mic-bias-lpm-supported: mic bias supply's LPM mode. + + - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec + hardware probe. Supplies in this list will be + stay enabled. + +Example: + +besbev_codec: besbev-codec { + compatible = "qcom,besbev-codec"; + qcom,split-codec = <1>; + qcom,pmic-spmi-node = <&pm2250_cdc>; + qcom,wcd-reset-reg = <0x0000FCDB>; + qcom,foundry-id-reg = <0x0000704D>; + qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, + <3 SPKR_L_VI 0x3 0 PCM_IN>; + + qcom,besbev-slave = <&besbev_rx_slave>; + qcom,speaker-present = <1>; + + cdc-mic-bias-supply = <&L28A>; + qcom,cdc-mic-bias-voltage = <2904000 2904000>; + qcom,cdc-mic-bias-current = <1180> + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-mic-bias"; +}; diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi new file mode 100644 index 000000000000..f896df8e4a15 --- /dev/null +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -0,0 +1,197 @@ +#include +#include +#include +#include + +&bolero { + qcom,num-macros = <3>; + qcom,bolero-version = <6>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,va_mclk_mode_muxsel = <0x0a7a0000>; + clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", + "va_core_clk", "va_npl_clk"; + clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, + <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, + <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; + }; + + tx_macro: tx-macro@0a620000 { + compatible = "qcom,tx-macro"; + reg = <0x0a620000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,is-used-swr-gpio = <0>; + }; + + rx_macro: rx-macro@0a600000 { + compatible = "qcom,rx-macro"; + reg = <0x0a600000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; + qcom,default-clk-id = ; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <2>; + qcom,swrm-hctl-reg = <0x0a6a9098>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a610000 0x0>; + interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <7>; + qcom,disable-div2-clk-switch = <1>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>, + <7 SWRM_RX_PCM_IN 0xF>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + besbev_rx_slave: besbev-rx-slave { + compatible = "qcom,besbev-slave"; + reg = <0x0C 0x01170224>; + }; + }; + }; + + besbev_codec: besbev-codec { + compatible = "qcom,besbev-codec"; + qcom,split-codec = <1>; + qcom,wcd-reset-reg = <0x0000FCDB>; + qcom,foundry-id-reg = <0x000001F2>; + qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, + <2 ADC1 0x1 0 SWRM_RX_PCM_IN>, <2 ADC2 0x2 0 SWRM_RX_PCM_IN>; + + qcom,besbev-slave = <&besbev_rx_slave>; + qcom,speaker-present = <1>; + + cdc-mic-bias-supply = <&L28A>; + qcom,cdc-mic-bias-voltage = <2904000 2904000>; + qcom,cdc-mic-bias-current = <1180>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-mic-bias"; + }; +}; + +&monaco_snd { + qcom,model = "monaco-idp-amic-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,va-bolero-codec = <1>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1","MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS3", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS1", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS1", + "SPKR_IN", "AUX_OUT", + "TX SWR_INPUT", "VA_TX_SWR_CLK", + "RX_SWR_TX_PCM_IN0", "RX_MCLK", + "RX_SWR_TX_PCM_IN1", "RX_MCLK", + "RX_SWR_TX_PCM_IN0", "ADC1_OUTPUT", + "RX_SWR_TX_PCM_IN1", "ADC2_OUTPUT", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "TX_AIF1 CAP", "VA_TX_SWR_CLK", + "TX_AIF2 CAP", "VA_TX_SWR_CLK", + "TX_AIF3 CAP", "VA_TX_SWR_CLK", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + asoc-codec = <&stub_codec>, <&bolero>, + <&besbev_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "besbev_codec"; + qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; +}; + +&soc { + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + clock_audio_va_1: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x307>; + #clock-cells = <1>; + }; + + clock_audio_va_2: va_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x308>; + #clock-cells = <1>; + }; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi new file mode 100644 index 000000000000..b50c44230947 --- /dev/null +++ b/qcom/monaco-audio-overlay.dtsi @@ -0,0 +1,234 @@ +#include +#include +#include +#include + +&bolero { + qcom,num-macros = <3>; + qcom,bolero-version = <6>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,va_mclk_mode_muxsel = <0x0a7a0000>; + clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", + "va_core_clk", "va_npl_clk"; + clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, + <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, + <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; + }; + + tx_macro: tx-macro@0a620000 { + compatible = "qcom,tx-macro"; + reg = <0x0a620000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-dmic-sample-rate = <2400000>; + qcom,is-used-swr-gpio = <0>; + }; + + rx_macro: rx-macro@0a600000 { + compatible = "qcom,rx-macro"; + reg = <0x0a600000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; + qcom,default-clk-id = ; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <2>; + qcom,swrm-hctl-reg = <0x0a6a9098>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a610000 0x0>; + interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <7>; + qcom,disable-div2-clk-switch = <1>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>, + <7 SWRM_RX_PCM_IN 0xF>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + besbev_rx_slave: besbev-rx-slave { + compatible = "qcom,besbev-slave"; + reg = <0x0C 0x01170224>; + }; + }; + }; + + va_macro: va-macro@0a730000 { + compatible = "qcom,va-macro"; + reg = <0x0a730000 0x0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,va-dmic-sample-rate = <600000>; + qcom,va-clk-mux-select = <1>; + qcom,va-island-mode-muxsel = <0x0a7a0000>; + qcom,default-clk-id = ; + qcom,is-used-swr-gpio = <1>; + qcom,va-swr-gpios = <&va_swr_gpios>; + swr0: va_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <3>; + qcom,swrm-hctl-reg = <0x0a7ec100>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a740000 0x0>; + interrupts = + <0 296 IRQ_TYPE_LEVEL_HIGH>, + <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + qcom,swr-wakeup-required = <1>; + qcom,swr-num-ports = <3>; + qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>, + <1 ADC3 0x4>, <1 ADC4 0x8>, + <2 DMIC0 0x1>, <2 DMIC1 0x2>, + <2 DMIC2 0x4>, <2 DMIC3 0x8>, + <3 DMIC4 0x1>, <3 DMIC5 0x2>, + <3 DMIC6 0x4>, <3 DMIC7 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-mstr-irq-wakeup-capable = <1>; + besbev_tx_slave: besbev-tx-slave { + compatible = "qcom,besbev-slave"; + reg = <0x0C 0x01170223>; + }; + }; + }; + + besbev_codec: besbev-codec { + compatible = "qcom,besbev-codec"; + qcom,split-codec = <1>; + qcom,wcd-reset-reg = <0x0000FCDB>; + qcom,foundry-id-reg = <0x000001F2>; + qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, + <3 SPKR_L_VI 0x3 0 SWRM_RX_PCM_IN>; + + qcom,besbev-slave = <&besbev_rx_slave>; + qcom,speaker-present = <1>; + + cdc-mic-bias-supply = <&L28A>; + qcom,cdc-mic-bias-voltage = <2904000 2904000>; + qcom,cdc-mic-bias-current = <1180>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-mic-bias"; + }; +}; + +&monaco_snd { + qcom,model = "monaco-idp-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,va-bolero-codec = <1>; + qcom,audio-routing = + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS3", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS1", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS1", + "SPKR_IN", "AUX_OUT", + "TX SWR_INPUT", "VA_TX_SWR_CLK", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "TX_AIF1 CAP", "VA_TX_SWR_CLK", + "TX_AIF2 CAP", "VA_TX_SWR_CLK", + "TX_AIF3 CAP", "VA_TX_SWR_CLK", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + + asoc-codec = <&stub_codec>, <&bolero>, + <&besbev_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "besbev_codec"; + qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; +}; + +&soc { + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + clock_audio_va_1: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x307>; + #clock-cells = <1>; + }; + + clock_audio_va_2: va_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x308>; + #clock-cells = <1>; + }; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/qcom/monaco-audio.dtsi b/qcom/monaco-audio.dtsi new file mode 100644 index 000000000000..ed9e4d025a35 --- /dev/null +++ b/qcom/monaco-audio.dtsi @@ -0,0 +1,168 @@ +#include +#include "msm-audio-lpass.dtsi" + +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; + + audio_pkt_core_platform: qcom,audio-pkt-core-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; +}; + +#include "monaco-lpi.dtsi" + +&spf_core_platform { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic02_gpios: cdc_dmic02_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic02_clk_active &cdc_dmic02_data_active>; + pinctrl-1 = <&cdc_dmic02_clk_sleep &cdc_dmic02_data_sleep>; + qcom,lpi-gpios; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + qcom,lpi-gpios; + }; + + va_swr_gpios: va_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + qcom,lpi-gpios; + qcom,chip-wakeup-reg = <0x003ca064>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@0a730000 { + swr0: va_swr_master { + }; + }; + + rx_macro: rx-macro@0a600000 { + swr1: rx_swr_master { + }; + }; + }; + + monaco_snd: sound { + compatible = "qcom,monaco-asoc-snd"; + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; + +&msm_audio_ion { + iommus = <&apps_smmu 0x01c1 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&qupv3_se1_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + }; +}; diff --git a/qcom/monaco-lpi.dtsi b/qcom/monaco-lpi.dtsi new file mode 100644 index 000000000000..1ab89ed940ee --- /dev/null +++ b/qcom/monaco-lpi.dtsi @@ -0,0 +1,377 @@ +&spf_core_platform { + lpass_audio_hw_vote: vote_lpass_audio_hw { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; + + lpi_tlmm: lpi_pinctrl@0a7c0000 { + compatible = "qcom,lpi-pinctrl"; + reg = <0x0a7c0000 0x0>; + qcom,slew-reg = <0x0a95a000 0x0>; + qcom,gpios-count = <19>; + gpio-controller; + #gpio-cells = <2>; + qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>, + <0x00002000>, <0x00003000>, + <0x00004000>, <0x00005000>, + <0x00006000>, <0x00007000>, + <0x00008000>, <0x00009000>, + <0x0000A000>, <0x0000B000>, + <0x0000C000>, <0x0000D000>, + <0x0000E000>, <0x0000F000>, + <0x00010000>, <0x00011000>, + <0x00012000>; + qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, + <0x00000004>, <0x00000008>, + <0x0000000A>, <0x0000000C>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000000>, <0x00000000>, + <0x00000014>; + + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + + quat_mi2s_sck { + quat_mi2s_sck_sleep: quat_mi2s_sck_sleep { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sck_active: quat_mi2s_sck_active { + mux { + pins = "gpio0"; + function = "func2"; + }; + + config { + pins = "gpio0"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_ws { + quat_mi2s_ws_sleep: quat_mi2s_ws_sleep { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_ws_active: quat_mi2s_ws_active { + mux { + pins = "gpio1"; + function = "func2"; + }; + + config { + pins = "gpio1"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio2"; + function = "func2"; + }; + + config { + pins = "gpio2"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tx_swr_clk_sleep: tx_swr_clk_sleep { + mux { + pins = "gpio0"; + function = "func1"; + input-enable; + bias-pull-down; + }; + + config { + pins = "gpio0"; + drive-strength = <10>; + }; + }; + + tx_swr_clk_active: tx_swr_clk_active { + mux { + pins = "gpio0"; + function = "func1"; + }; + + config { + pins = "gpio0"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + }; + + tx_swr_data1_sleep: tx_swr_data1_sleep { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <10>; + input-enable; + bias-bus-hold; + }; + }; + + tx_swr_data1_active: tx_swr_data1_active { + mux { + pins = "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio1"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + tx_swr_data2_sleep: tx_swr_data2_sleep { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + tx_swr_data2_active: tx_swr_data2_active { + mux { + pins = "gpio2"; + function = "func1"; + }; + + config { + pins = "gpio2"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + rx_swr_clk_sleep: rx_swr_clk_sleep { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_clk_active: rx_swr_clk_active { + mux { + pins = "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio3"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + }; + + rx_swr_data_sleep: rx_swr_data_sleep { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <10>; + input-enable; + bias-pull-down; + }; + }; + + rx_swr_data_active: rx_swr_data_active { + mux { + pins = "gpio4"; + function = "func1"; + }; + + config { + pins = "gpio4"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio6"; + function = "func1"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic02_clk_active: dmic02_clk_active { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic02_clk_sleep: dmic02_clk_sleep { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic02_data_active: dmic02_data_active { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic02_data_sleep: dmic02_data_sleep { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + }; +}; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index f98e24512fec..9b1af4cace1c 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -745,5 +745,36 @@ }; }; }; + + /* WSA speaker reset pin1 */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; }; }; diff --git a/qcom/monaco-wsa-audio-overlay.dtsi b/qcom/monaco-wsa-audio-overlay.dtsi new file mode 100644 index 000000000000..2d91a04619ab --- /dev/null +++ b/qcom/monaco-wsa-audio-overlay.dtsi @@ -0,0 +1,227 @@ +#include +#include +#include +#include + +&bolero { + qcom,num-macros = <3>; + qcom,bolero-version = <6>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,va_mclk_mode_muxsel = <0x0a7a0000>; + clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", + "va_core_clk", "va_npl_clk"; + clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, + <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, + <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; + }; + + tx_macro: tx-macro@0a620000 { + compatible = "qcom,tx-macro"; + reg = <0x0a620000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-dmic-sample-rate = <2400000>; + qcom,is-used-swr-gpio = <0>; + }; + + rx_macro: rx-macro@0a600000 { + compatible = "qcom,rx-macro"; + reg = <0x0a600000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; + qcom,default-clk-id = ; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <2>; + qcom,swrm-hctl-reg = <0x0a6a9098>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a610000 0x0>; + interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <7>; + qcom,disable-div2-clk-switch = <1>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>, + <7 SWRM_RX_PCM_IN 0xF>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + wsa883x_0221: wsa883x@02170221 { + compatible = "qcom,wsa883x"; + reg = <0x2 0x2170221>; + qcom,spkr-sd-n-node = <&wsa_spkr_en>; + qcom,bolero-handle = <&bolero>; + + cdc-vdd-1p8-supply = <&L19A>; + qcom,cdc-vdd-1p8-voltage = <1800000 1800000>; + qcom,cdc-vdd-1p8-current = <20000>; + qcom,cdc-static-supplies = "cdc-vdd-1p8"; + qcom,wsa-prefix = "SpkrLeft"; + }; + + }; + }; + + va_macro: va-macro@0a730000 { + compatible = "qcom,va-macro"; + reg = <0x0a730000 0x0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,va-dmic-sample-rate = <600000>; + qcom,va-clk-mux-select = <1>; + qcom,va-island-mode-muxsel = <0x0a7a0000>; + qcom,default-clk-id = ; + qcom,is-used-swr-gpio = <1>; + qcom,va-swr-gpios = <&va_swr_gpios>; + swr0: va_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + qcom,swr_master_id = <3>; + qcom,swrm-hctl-reg = <0x0a7ec100>; + qcom,mipi-sdw-block-packing-mode = <1>; + swrm-io-base = <0x0a740000 0x0>; + interrupts = + <0 296 IRQ_TYPE_LEVEL_HIGH>, + <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + qcom,swr-wakeup-required = <1>; + qcom,swr-num-ports = <3>; + qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>, + <1 ADC3 0x4>, <1 ADC4 0x8>, + <2 DMIC0 0x1>, <2 DMIC1 0x2>, + <2 DMIC2 0x4>, <2 DMIC3 0x8>, + <3 DMIC4 0x1>, <3 DMIC5 0x2>, + <3 DMIC6 0x4>, <3 DMIC7 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-mstr-irq-wakeup-capable = <1>; + }; + }; +}; + +&monaco_snd { + qcom,model = "monaco-idp-wsa-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,va-bolero-codec = <1>; + qcom,audio-routing = + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS3", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS1", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS1", + "SpkrLeft IN", "AUX_OUT", + "TX SWR_INPUT", "VA_TX_SWR_CLK", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "TX_AIF1 CAP", "VA_TX_SWR_CLK", + "TX_AIF2 CAP", "VA_TX_SWR_CLK", + "TX_AIF3 CAP", "VA_TX_SWR_CLK", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + + asoc-codec = <&stub_codec>, <&bolero>, + <&wsa883x_0221>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wsa-codec1"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa883x_0221>; + qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; +}; + +&soc { + wsa_spkr_en: wsa_spkr_en_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + clock_audio_va_1: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x307>; + #clock-cells = <1>; + }; + + clock_audio_va_2: va_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x308>; + #clock-cells = <1>; + }; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index a64f48feccfd..ff498fe835f7 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -54,5 +54,9 @@ reg-names = "rtc", "alarm"; interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; }; + + pm5100_cdc: qcom,pm5100-cdc { + compatible = "qcom,pm5100-spmi"; + }; }; }; From bd82334bfe25fe533a199177fd9c16f87f6ea82f Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 19 Apr 2021 17:19:55 +0530 Subject: [PATCH 1298/1809] ARM: dts: msm: update interconnect devices for Monaco Update the interconnect devices for cnoc, snoc, bimc, clk_virt, mmnrt_virt and mmrt_virt to enable the real interconenct devices. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: Idc66b9971f9065d3fb0a990b1a8ebd2b15d108ba --- qcom/monaco.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3e9883ccbcad..83c6ad9cbbe5 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -980,31 +980,60 @@ clk_virt: interconnect { compatible = "qcom,monaco-clk_virt"; #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_QUP_CLK>, + <&rpmcc RPM_SMD_QUP_A_CLK>; }; mmnrt_virt: interconnect@0 { compatible = "qcom,monaco-mmnrt_virt"; #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, + <&rpmcc RPM_SMD_MMNRT_A_CLK>; }; mmrt_virt: interconnect@1 { compatible = "qcom,monaco-mmrt_virt"; #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMRT_CLK>, + <&rpmcc RPM_SMD_MMRT_A_CLK>; }; system_noc: interconnect@1880000 { + reg = <0x01880000 0x5e200>; compatible = "qcom,monaco-system_noc"; #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; }; config_noc: interconnect@1900000 { + reg = <0x01900000 0x1000>; compatible = "qcom,monaco-config_noc"; #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; }; bimc: interconnect@4480000 { + reg = <0x04480000 0x80000>; compatible = "qcom,monaco-bimc"; #interconnect-cells = <1>; + qcom,util-factor = <151>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; }; rpm_bus: qcom,rpm-smd { From 600758bf8eaae8dc37404b16f659ce7d774dd1a7 Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Thu, 22 Apr 2021 16:33:45 -0700 Subject: [PATCH 1299/1809] ARM: dts: msm: bypass IPA eth shared-cb bypass IPA eth shared-cb. Change-Id: Id88736ee596de78daeec963d45d9aea3c6e0a233 --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index af021815a43b..63505538c5bf 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -25,6 +25,10 @@ status = "ok"; }; +&ipa_eth_group1 { + qcom,iommu-dma = "bypass"; +}; + &ipa_hw { qcom,use-ipa-in-mhi-mode; ipa_smmu_ap { From 3d93865409811e15267d881db57ef7b7cb4d22b1 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 22 Apr 2021 20:17:11 -0700 Subject: [PATCH 1300/1809] ARM: dts: msm: Include sdxlemur-mtp dt in sdxlemur-atp Assuming that ATP is similar to MTP in this aspect. Change-Id: I2519dcba24ec60c549a27aea4641a95ecdd2569b --- qcom/sdxlemur-atp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-atp.dtsi b/qcom/sdxlemur-atp.dtsi index cc3a833f430e..e39236090d51 100644 --- a/qcom/sdxlemur-atp.dtsi +++ b/qcom/sdxlemur-atp.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-mtp.dtsi" &soc { From 2d0652d8b6a059fcc3cc537720e0e5cfffbc72e2 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 16 Apr 2021 18:43:48 -0700 Subject: [PATCH 1301/1809] ARM: dts: msm: Add PM7250B to sdxlemur-atp Add support for PM7250B on the ATP board. Change-Id: I5b5551eced2ffa28766b7b560d3d80136be35c52 --- qcom/sdxlemur-atp.dtsi | 228 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 227 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-atp.dtsi b/qcom/sdxlemur-atp.dtsi index e39236090d51..71d059cff54d 100644 --- a/qcom/sdxlemur-atp.dtsi +++ b/qcom/sdxlemur-atp.dtsi @@ -1,6 +1,232 @@ #include "sdxlemur-mtp.dtsi" +#include "pm7250b.dtsi" +#include &soc { - + atp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&atp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&atp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; From 3ed72b74e81ef74292495ba5dfe85faf028d75eb Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 16 Apr 2021 19:04:25 -0700 Subject: [PATCH 1302/1809] ARM: dts: msm: Add extcon node for sdxlemur-atp Enable cable detection using pdphy functionality. Also disable PMX65 VBUS_DET as VBUS detection is through PM7250B. Change-Id: I9301e5f7412c5a443da4254524bcf7bd9e1fd79c --- qcom/sdxlemur-atp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdxlemur-atp.dtsi b/qcom/sdxlemur-atp.dtsi index 71d059cff54d..b14515805db6 100644 --- a/qcom/sdxlemur-atp.dtsi +++ b/qcom/sdxlemur-atp.dtsi @@ -9,6 +9,18 @@ }; }; +&usb { + extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&vbus_detect { + status = "disabled"; +}; + &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; From 2b128eaa856e4993a0a088386f017d26dee0f702 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 23 Apr 2021 10:28:44 -0700 Subject: [PATCH 1303/1809] ARM: dts: msm: Enable CPU cooling device for sdxlemur Enable CPU cooling device to register with thermal framework for sdxlemur. Change-Id: I1be3532bfed77d4a82b1ef5c337220fe3f199783 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 9b5aae70a9e0..e951139d46db 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -101,6 +101,7 @@ reg = <0x0>; enable-method = "psci"; cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>; + #cooling-cells = <2>; }; }; From 89ec72642e751ddf38b62dc3a614dd05f63b9f35 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 23 Apr 2021 10:31:11 -0700 Subject: [PATCH 1304/1809] dt-bindings: thermal: Add new QMI sensors to the supported list Add new QMI sensors to the already supported list of QMI sensors. This will enable the new sensors starting to be available starting sdxlemur. Change-Id: Ibf7b5d9bdb197a5ee59c683ede2ad5cc25ca54f9 --- bindings/thermal/qti-qmi-sensor.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index 319329676034..1c42a19e8cc7 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -71,6 +71,27 @@ Subsystem properties: 38. qfe_wtr_pa2_fr1 39. qfe_wtr_pa3_fr1 40. qfe_wtr0_fr1 + 41. qtm_therm + 42. modem_bcl_warn + 43. sdr0_pa0 + 44. sdr0_pa1 + 45. sdr0_pa2 + 46. sdr0_pa3 + 47. sdr0_pa4 + 48. sdr0_pa5 + 49. sdr0 + 50. sdr1_pa0 + 51. sdr1_pa1 + 52. sdr1_pa2 + 53. sdr1_pa3 + 54. sdr1_pa4 + 55. sdr1_pa5 + 56. sdr1 + 57. mmw0 + 58. mmw1 + 59. mmw2 + 60. mmw3 + 61. mmw_ific0 Example: From 76a2d1338703654a90f3d9d8c2c093cfb5046e15 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 23 Apr 2021 10:40:16 +0530 Subject: [PATCH 1305/1809] bindings: spmi: spmi-pmic-arb: Add description for "qcom,mid" Add a description for the "qcom,mid" property which corresponds to the SPMI master ID of the SPMI PMIC arbiter controller. It is most useful in systems with multiple masters, e.g. when there are multiple SoCs connected to a single SPMI bus. Change-Id: I376e6f569f9bbea44ba3930480a330fb1dd2c2de --- bindings/spmi/qcom,spmi-pmic-arb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/spmi/qcom,spmi-pmic-arb.txt b/bindings/spmi/qcom,spmi-pmic-arb.txt index dd7539564b19..dfcc29023aad 100644 --- a/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -43,6 +43,8 @@ Optional properties: cell 3: the requested peripheral interrupt (0-7) cell 4: interrupt flags indicating level-sense information, as defined in dt-bindings/interrupt-controller/irq.h +- qcom,mid : SPMI master ID of this controller. Supported values + are 0, 1, 2 and 3. Consumer node optional properties: - qcom,pmic-arb : phandle for an spmi-pmic-arb device. This can be used by @@ -63,6 +65,7 @@ Example: qcom,ee = <0>; qcom,channel = <0>; + qcom,mid = <0>; #address-cells = <2>; #size-cells = <0>; From 259ce0cd7a5b6ae001e0d8489f6b101d6bdf392c Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Mon, 19 Apr 2021 16:56:42 +0530 Subject: [PATCH 1306/1809] dt-bindings: batterydata: Add bindings for properties used by QBG Add documentation for batterydata properties used in battery profile for Qualcomm Technologies, Inc. Battery Gauge device. Change-Id: Id6fa8bff4eb2fb26ab70cb90f0e9a2f42d21e4e3 --- bindings/batterydata/batterydata.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/bindings/batterydata/batterydata.txt b/bindings/batterydata/batterydata.txt index 734f7817d464..020789f9e880 100644 --- a/bindings/batterydata/batterydata.txt +++ b/bindings/batterydata/batterydata.txt @@ -39,6 +39,13 @@ Profile data node required properties: of coefficients used in hardware state machines and thus influencing the final output of the state of charge read by software. +- qcom,capacity : Maximum capacity of the battery (in mAH). +- qcom,checksum : Checksum used to determine if loaded battery profile is valid. +- qcom,recharge-soc-delta : Percentage of SOC delta dropped after end of charge + to enable recharge. +- qcom,recharge-vflt-delta : Delta in Vfloat dropped from regular vfloat in + recharge. +- qcom,recharge-iterm-ma : Termination current (in mA) in recharge. Profile data node optional properties: - qcom,chg-rslow-comp-c1 : A constant for rslow compensation in the fuel gauge. @@ -198,6 +205,16 @@ Lookup table required properties: the size of qcom,lut-row-legend if it's a 2-dimensional table. The data should be in a flattened row-major representation. +- qcom,bp-c-table0 : LUT table of the battery used for PON SOC estimation + during battery charge. +- qcom,bp-d-table0 : LUT table of the battery used for PON SOC estimation + during battery discharge. +- qcom,bp-c-table-X : LUT tables of the battery at different temperatures + used for SOC estimation during battery charge. Value + of X starts from 1. +- qcom,bp-d-table-X : LUT tables of the battery at different temperatures + used for SOC estimation during battery charge. Value + of X starts from 1. Lookup table optional properties: - qcom,lut-row-legend : An array that encodes the legend of the lookup table's rows. From 0e7cf5a1e732a79d5828f69953f7552cb7edb8c7 Mon Sep 17 00:00:00 2001 From: Fch Date: Wed, 21 Apr 2021 06:58:34 +0530 Subject: [PATCH 1307/1809] ARM: dts: msm: setting clk is provided by SOC Solving QUIN TDM without CLK Change-Id: Ifec0d86bcba5c5c21b6d296ad001fbcb45a2119f --- qcom/sa6155-audio.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index 1da3130998b0..8e1aa63d8e9f 100644 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -367,9 +367,9 @@ qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 36934 36942>; qcom,msm-cpudai-tdm-clk-rate = <12288000>; - qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; qcom,msm-cpudai-tdm-data-delay = <0>; @@ -417,9 +417,9 @@ qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 36935 36943>; qcom,msm-cpudai-tdm-clk-rate = <12288000>; - qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; qcom,msm-cpudai-tdm-data-out = <0>; qcom,msm-cpudai-tdm-invert-sync = <0>; qcom,msm-cpudai-tdm-data-delay = <0>; From 78f6afc8b31336850c7515289c9d272817237708 Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Mon, 26 Apr 2021 13:56:36 +0530 Subject: [PATCH 1308/1809] ARM: dts: msm: Change the shmbridge default size to 1M sdxnightjar is a low memory target. Change the default bridge size to 1M to avoid OOM issues. Change-Id: Ib7ed8f32569a2422978573ca3f8c5c7dda0853ab --- qcom/sdxnightjar.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index 123e6dd21454..d89076b9ac6d 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -74,6 +74,7 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <256>; }; }; From fee07b543a4f56097d8d77fdf508ee089ac76335 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 12 Apr 2021 19:08:12 +0530 Subject: [PATCH 1309/1809] ARM: dts: msm: Update CPUFREQ-HW nodes for Blair Enable CPU frequency scaling and debug nodes for BLAIR. Change-Id: I68cad665c716283298f08bb4501c7dd646dd8758 --- qcom/blair-rumi.dtsi | 6 ++++++ qcom/blair.dtsi | 17 ++++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 6994b5445b9b..22df7e1574e2 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { timer { clock-frequency = <500000>; @@ -149,6 +150,7 @@ &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; + &usb0 { dwc3@4e00000 { usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; @@ -156,3 +158,7 @@ dr_mode = "peripheral"; }; }; + +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GPLL0>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 2618151b2517..d07cff003c66 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -68,6 +68,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -89,6 +90,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -105,6 +107,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_2>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -121,6 +124,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_3>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -137,6 +141,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -153,6 +158,7 @@ dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -169,6 +175,7 @@ dynamic-power-coefficient = <520>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 2>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -185,6 +192,7 @@ dynamic-power-coefficient = <520>; cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 1 2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -1261,21 +1269,17 @@ cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw-epss"; - reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>, - <0x0fd04504 0x4>, <0x0fd04508 0x4>; - reg-names = "freq-domain0", "freq-domain1", - "pdmem-domain0", "pdmem-domain1"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; qcom,lut-row-size = <4>; qcom,max-lut-entries = <12>; qcom,skip-enable-check; - qcom,perf-lock-support; interrupts = , ; interrupt-names = "dcvsh0_int", "dcvsh1_int"; #freq-domain-cells = <2>; - status = "disabled"; }; qcom,cpufreq-hw-debug@0fd91000 { @@ -1283,7 +1287,6 @@ reg = <0x0fd91000 0x800>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; - status = "disabled"; }; ddr_bw_opp_table: ddr-bw-opp-table { From eb9b7b1b8a378deefdbc74889f34e25c078af370 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Thu, 22 Apr 2021 15:08:46 +0530 Subject: [PATCH 1310/1809] bindings: clock: Add debugcc bindings for BLAIR Add debugcc clock controller bindings to support BLAIR. Change-Id: Ib8fe2baabf741a6d0d500893a10e137c7344b4d3 --- bindings/clock/qcom,debugcc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 844cb4c02cdc..3b898dc10040 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -15,6 +15,7 @@ Required properties : "qcom,sm6150-debugcc" "qcom,monaco-debugcc" "qcom,direwolf-debugcc" + "qcom,blair-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. From 2e55bc6bef9a16f4e30909ad1f03433a63b811e4 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Wed, 7 Apr 2021 18:01:28 +0530 Subject: [PATCH 1311/1809] ARM: dts: msm: Add support for clock controllers for BLAIR Enable GPUCC, DISPCC and DEBUGCC and update RPMCC to use holi-rpmcc instead of dummy for BLAIR RUMI. Change-Id: Ia3aa16e4181aa3e2760eb2981af24c6111d27a32 --- qcom/blair-rumi.dtsi | 30 ------------------------------ qcom/blair.dtsi | 9 +++------ 2 files changed, 3 insertions(+), 36 deletions(-) diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 22df7e1574e2..23e168b9326c 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -1,5 +1,4 @@ #include -#include &soc { timer { clock-frequency = <500000>; @@ -27,22 +26,6 @@ 0x10060 0x3c 0x0 0x4>; }; - - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; }; &tsens0 { @@ -142,15 +125,6 @@ rpm-standalone; }; -&rpmcc { - compatible = "qcom,dummycc"; - clock-output-names = "rpmhcc_clocks"; -}; - -&gcc { - clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; -}; - &usb0 { dwc3@4e00000 { usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; @@ -158,7 +132,3 @@ dr_mode = "peripheral"; }; }; - -&cpufreq_hw { - clocks = <&bi_tcxo>, <&gcc GPLL0>; -}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index d07cff003c66..218dfa212f0e 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1214,7 +1214,7 @@ }; dispcc: clock-controller@5f00000 { - compatible = "qcom,holi-dispcc", "syscon"; + compatible = "qcom,blair-dispcc", "syscon"; reg = <0x5f00000 0x20000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; @@ -1223,11 +1223,10 @@ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; #clock-cells = <1>; #reset-cells = <1>; - status = "disabled"; }; gpucc: clock-controller@5990000 { - compatible = "qcom,holi-gpucc", "syscon"; + compatible = "qcom,blair-gpucc", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; @@ -1241,7 +1240,6 @@ "gcc_gpu_snoc_dvm_gfx_clk"; #clock-cells = <1>; #reset-cells = <1>; - status = "disabled"; }; cpucc: syscon@faa0018 { @@ -1255,7 +1253,7 @@ }; debugcc: clock-controller@0 { - compatible = "qcom,holi-debugcc"; + compatible = "qcom,blair-debugcc"; qcom,gcc = <&gcc>; qcom,dispcc = <&dispcc>; qcom,gpucc = <&gpucc>; @@ -1264,7 +1262,6 @@ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo_clk_src"; #clock-cells = <1>; - status = "disabled"; }; cpufreq_hw: qcom,cpufreq-hw { From 5ecb7c92a48b67b5d6a8f841124d7a1b209d32f4 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 13:38:29 +0530 Subject: [PATCH 1312/1809] ARM: dts: msm: Add devfreq support nodes for Direwolf Add devfreq support device tree noded for Direwolf platform. This includes the devfreq devices, OPP tables, and devfreq hardware monitors to support the different bandwidth and latency requirements. Change-Id: I30ac477957c2e4bec54f3e39db6a880a09bb6f0b --- qcom/direwolf.dtsi | 398 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 398 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 58db8e45f42d..85562b39fe25 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -9,6 +9,15 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + +#define DDR_TYPE_LPDDR4X 7 +#define DDR_TYPE_LPDDR5 8 + / { model = "Qualcomm Technologies, Inc. Direwolf"; compatible = "qcom,direwolf"; @@ -1072,6 +1081,395 @@ mbox-desc-offset = <0x0>; #mbox-cells = <1>; }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */ + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 200, 4, 0x80); /* 762 MB/s */ + BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */ + BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */ + BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */ + BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */ + BW_OPP_ENTRY_DDR( 1017, 4, 0x80); /* 3879 MB/s */ + BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */ + BW_OPP_ENTRY_DDR( 1555, 4, 0x80); /* 5931 MB/s */ + BW_OPP_ENTRY_DDR( 1708, 4, 0x80); /* 6515 MB/s */ + BW_OPP_ENTRY_DDR( 2092, 4, 0x80); /* 7980 MB/s */ + BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */ + BW_OPP_ENTRY_DDR( 2736, 4, 0x80); /* 10437 MB/s */ + BW_OPP_ENTRY_DDR( 3196, 4, 0x80); /* 12191 MB/s */ + }; + + qoslat_opp_table: qoslat-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + + opp-2 { + opp-hz = /bits/ 64 < 2 >; + }; + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x9091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU5>; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat { + compatible = "qcom,devfreq-qoslat"; + governor = "powersave"; + operating-points-v2 = <&qoslat_opp_table>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 403200 403200000 >, + < 499200 499200000 >, + < 691200 614400000 >, + < 806400 710400000 >, + < 998400 806400000 >, + < 1190400 998400000 >, + < 1286400 1094400000 >, + < 1459200 1248000000 >, + < 1728000 1344000000 >, + < 1804800 1440000000 >, + < 1900800 1516800000 >; + }; + + cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl { + qcom,core-dev-table = + < 300000 300000000 >, + < 787200 614400000 >, + < 1209600 806400000 >, + < 1497600 998400000 >, + < 1689600 1248000000 >, + < 1900800 1344000000 >, + < 2188800 1440000000 >, + < 2400000 1516800000 >; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 150, 16) >, + < 691200 MHZ_TO_MBPS( 300, 16) >, + < 1459200 MHZ_TO_MBPS( 466, 16) >, + < 1900800 MHZ_TO_MBPS( 600, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1190400 MHZ_TO_MBPS( 547, 4) >, + < 1459200 MHZ_TO_MBPS( 768, 4) >, + < 1900800 MHZ_TO_MBPS( 1017, 4) >; + }; + + }; + + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 150, 16) >, + < 672000 MHZ_TO_MBPS( 300, 16) >, + < 1017600 MHZ_TO_MBPS( 466, 16) >, + < 1305600 MHZ_TO_MBPS( 600, 16) >, + < 1804800 MHZ_TO_MBPS( 806, 16) >, + < 2188800 MHZ_TO_MBPS( 933, 16) >, + < 2400000 MHZ_TO_MBPS( 1000, 16) >; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 672000 MHZ_TO_MBPS( 451, 4) >, + < 902400 MHZ_TO_MBPS( 547, 4) >, + < 1017600 MHZ_TO_MBPS( 768, 4) >, + < 1305600 MHZ_TO_MBPS(1017, 4) >, + < 1593600 MHZ_TO_MBPS(1353, 4) >, + < 1804800 MHZ_TO_MBPS(1555, 4) >, + < 2188800 MHZ_TO_MBPS(1708, 4) >, + < 2400000 MHZ_TO_MBPS(2133, 4) >; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 1804800 MHZ_TO_MBPS( 200, 4) >, + < 2304000 MHZ_TO_MBPS(1017, 4) >, + < 2400000 MHZ_TO_MBPS(2133, 4) >; + }; + + ddr5-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 1804800 MHZ_TO_MBPS( 200, 4) >, + < 2303000 MHZ_TO_MBPS(1017, 4) >, + < 2400000 MHZ_TO_MBPS(3196, 4) >; + }; + }; + + cpu4_qoslatmon: qcom,cpu4-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu4_cpu_ddr_qoslat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 1 >, + < 3000000 2 >; + }; + }; }; #include "direwolf-pinctrl.dtsi" From 282d9db0e1575af3df29fe90b4ff1921112fe413 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 13:46:06 +0530 Subject: [PATCH 1313/1809] ARM: dts: msm: Add LLCC PMU device nodes on Direwolf Add LLCC PMU device nodes to measure the various performance metrics on Direwolf target. Change-Id: I8cae3762bd1659ee60343259b578ba0df82d2947 --- qcom/direwolf.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 85562b39fe25..d2c3003d9a91 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1082,6 +1082,12 @@ #mbox-cells = <1>; }; + llcc_pmu: llcc-pmu@9095000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x09095000 0x300>; + reg-names = "lagg-base"; + }; + llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ From a4bdea86f1a2386a4d49eba2515a189183bff8e8 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:19:19 +0530 Subject: [PATCH 1314/1809] ARM: dts: msm: Add LLCC device nodes for Direwolf Add device nodes for Last level cache controller for Direwolf target. Change-Id: I7b207f8a63a9f466e5e3f1767b130137704fc73d --- bindings/arm/msm/qcom,llcc.txt | 1 + qcom/direwolf.dtsi | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index dc9c20cfec7b..2705ee9b1b5d 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -15,6 +15,7 @@ Properties: or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" + or "qcom,direwolf-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index d2c3003d9a91..3eb5ba2ff0aa 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1082,6 +1082,16 @@ #mbox-cells = <1>; }; + cache-controller@9200000 { + compatible = "qcom,direwolf-llcc", "qcom,llcc-v2"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + interrupts = ; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; + }; + llcc_pmu: llcc-pmu@9095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x09095000 0x300>; From f3b6f39e849cb2b3f0d0b1604f0e64cd3ebf0a4a Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 10 Mar 2021 13:38:08 +0530 Subject: [PATCH 1315/1809] ARM: dts: msm: Add ION support for Direwolf Add ION support for Direwolf target. Change-Id: Ifd42df124041771aa84f665c085a45765d7208b6 --- qcom/direwolf-ion.dtsi | 14 ++++++++++++++ qcom/direwolf.dtsi | 1 + 2 files changed, 15 insertions(+) create mode 100644 qcom/direwolf-ion.dtsi diff --git a/qcom/direwolf-ion.dtsi b/qcom/direwolf-ion.dtsi new file mode 100644 index 000000000000..fbd71987b0bc --- /dev/null +++ b/qcom/direwolf-ion.dtsi @@ -0,0 +1,14 @@ +#include + +&soc { + msm_ion: qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + }; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 3eb5ba2ff0aa..e7165829baef 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1492,6 +1492,7 @@ #include "direwolf-regulators.dtsi" #include "direwolf-pm.dtsi" #include "direwolf-gdsc.dtsi" +#include "direwolf-ion.dtsi" &gcc_emac0_gdsc { status = "ok"; From efb8949aee5b498afb14c1e739c5fb7c79fe4f15 Mon Sep 17 00:00:00 2001 From: Kuichu Ni Date: Thu, 22 Apr 2021 18:05:28 +0800 Subject: [PATCH 1316/1809] ARM: dts: msm: Enlarge the minidump cma area Enlarge the minidump cma area due to a number of new DTSI nodes (mainly related to CPU cache minidumps) have been added, which require more space. Change-Id: I985d2bc74124e75c65ac98f0c207a76ee868c4b7 --- qcom/sm6150.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 78243da492ec..a195d6fe7f2a 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -445,8 +445,9 @@ dump_mem: mem_dump_region { compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; - size = <0 0x2400000>; + size = <0 0x2800000>; }; /* global autoconfigured region for contiguous allocations */ From 76e239db3f75ccca1e0f07e6e9b97c691be67d68 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 27 Apr 2021 09:54:01 +0530 Subject: [PATCH 1317/1809] Revert "ARM: dts: msm: Disable NPU DCVS support on SA8195" Enable NPU DCVS support. This reverts commit d703024c34238221d23fe803500c408048525cb7. Change-Id: If193f56329cbec08a00edcc59838ba33dba1eefb --- qcom/sdmshrike.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index d94487134df9..f9963d44fc0b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -849,7 +849,6 @@ interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&ddr_bw_opp_table>; qcom,active-only; - status = "disabled"; }; npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { @@ -861,7 +860,6 @@ qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&npu_npu_ddr_bw>; qcom,count-unit = <0x10000>; - status = "disabled"; }; cpu_pmu: cpu-pmu { From 3ddc9e9953ae6b51bde3036f7e4f1077b519100f Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 27 Apr 2021 09:54:37 +0530 Subject: [PATCH 1318/1809] Revert "ARM: dts: msm: Disable NPU DCVS support on SM8150" Enable NPU DCVS support. This reverts commit d641513439dcc428df6d25942ef7f23d8a10cac9. Change-Id: I6f5cecf8aa05ba5582da3a5cbadc0d5e5c98b477 --- qcom/sm8150.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index f0bbf9ed930d..719f983fc39f 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -908,7 +908,6 @@ interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&ddr_bw_opp_table>; qcom,active-only; - status = "disabled"; }; npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { @@ -920,7 +919,6 @@ qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&npu_npu_ddr_bw>; qcom,count-unit = <0x10000>; - status = "disabled"; }; cpu_pmu: cpu-pmu { From 6d27ecf33a99a63ae34ae332a73ed506f7310ccc Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 22 Mar 2021 13:28:47 +0530 Subject: [PATCH 1319/1809] dt-bindings: iio: qcom,spmi-vadc: Add PMIC5 GEN3 ADC bindings PMIC5 GEN3 ADC has support for clients to read voltage and current on supported channels connected to the PMIC. Clients include reading voltage phone power and on board system thermistors for thermal management. ADCs on certain PMICs have support to read battery current. Change-Id: Ief7cbdf77d227ba2cb4ef7919aa66d9962d98e37 --- bindings/iio/adc/qcom,spmi-vadc.txt | 99 +++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 13 deletions(-) diff --git a/bindings/iio/adc/qcom,spmi-vadc.txt b/bindings/iio/adc/qcom,spmi-vadc.txt index 0c01def74f7f..975907257ad6 100644 --- a/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/bindings/iio/adc/qcom,spmi-vadc.txt @@ -11,6 +11,7 @@ VADC node: Usage: required Value type: Definition: Should contain "qcom,spmi-vadc". + Should contain "qcom,spmi-adc5-gen3" for PMIC5 Gen3 ADC driver. Should contain "qcom,spmi-adc7" for PMIC7 ADC driver. Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. @@ -20,6 +21,8 @@ VADC node: Usage: required Value type: Definition: VADC base address in the SPMI PMIC register map. + Debug ADC peripheral base address in the SPMI PMIC + register map. Debug peripheral address is optional. - #address-cells: Usage: required @@ -52,7 +55,8 @@ Channel node properties: See include/dt-bindings/iio/qcom,spmi-vadc.h - label: - Usage: required for "qcom,spmi-adc5", "qcom,spmi-adc7" and "qcom,spmi-adc-rev2" + Usage: required for "qcom,spmi-adc5", "qcom,spmi-adc7", "qcom,spmi-adc5-gen3" + and "qcom,spmi-adc-rev2" Value type: Definition: ADC input of the platform as seen in the schematics. For thermistor inputs connected to generic AMUX or GPIO inputs @@ -70,9 +74,9 @@ Channel node properties: - For compatible property "qcom,spmi-adc5", valid values are 250, 420 and 840. If property is not found, default value of 840 is used. - - For compatible property "qcom,spmi-adc7", valid values are - 85, 340 and 1360. If property is not found, default value of - 1360 is used. + - For compatible property "qcom,spmi-adc7" and "qcom,spmi-adc5-gen3", + valid values are 85, 340 and 1360. If property is not found, default + value of 1360 is used. - For compatible property "qcom,spmi-adc-rev2", valid values are 256, 512 and 1024. If property is not present, default value is 1024. @@ -97,9 +101,10 @@ Channel node properties: channel calibration. If property is not found, channel will be calibrated with 0.625V and 1.25V reference channels, also known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and - "qcom,spmi-adc-rev2", if this property is specified VADC will - use the VDD reference (1.875V) and GND for channel calibration. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7", + "qcom,spmi-adc5-gen3" and "qcom,spmi-adc-rev2", if this property + is specified VADC will use the VDD reference (1.875V) and GND for + channel calibration. If property is not found, channel will be calibrated with 0V and 1.25V reference channels, also known as absolute calibration. @@ -123,8 +128,8 @@ Channel node properties: Certain controller digital versions have valid values of 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms If property is not found, channel will use 15us. - - For compatible property "qcom,spmi-adc7", delay = 15us for - value 0, 100us * (value) for values < 8, 1ms for value 8 + - For compatible property "qcom,spmi-adc7" or "qcom,spmi-adc5-gen3", + delay = 15us for value 0, 100us * (value) for values < 8, 1ms for value 8 and 2ms * (value - 8) otherwise. Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 us. @@ -140,8 +145,9 @@ Channel node properties: - For compatible property "qcom,spmi-vadc", valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 If property is not found, 1 sample will be used. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" - and "qcom,spmi-adc-rev2", valid values are: 1, 2, 4, 8, 16. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7", + "qcom,spmi-adc5-gen3" and "qcom,spmi-adc-rev2", + valid values are: 1, 2, 4, 8, 16. If property is not found, 1 sample will be used. - qcom,scale-fn-type: @@ -149,9 +155,30 @@ Channel node properties: Value type: Definition: The index of the VADC scale function used to convert raw ADC code to physical scaled units for the channel. Defined for compatible - properties "qcom,spmi-adc5" and "qcom,spmi-adc7". + properties "qcom,spmi-adc5", "qcom,spmi-adc5-gen3" and "qcom,spmi-adc7". See include/dt-bindings/iio/qcom,spmi-vadc.h. +- qcom,adc-tm-type: + Usage: optional + Value type: + Definition: Type of ADC_TM usage defined for a given channel. Valid values + are 0-3. Defined for compatible property "qcom,spmi-adc5-gen3". + - Value 0 indicates it will not be used for ADC_TM. + - Value 1 indicates it will be used for thermistors, for detecting + temperature threshold violations and temperature reads. + - Value 2 indicates it will be used for thermistors, for temperature + reads alone. + - Value 3 indicates it will be used for non-thermal clients, for + detecting threshold violations for that channel. + +- qcom,rscale-type: + Usage: optional + Value type: + Definition: Type of reverse scaling function used for ADC_TM channels. Valid only + for the case of non-thermal ADC_TM client. Valid value at present is only + 0 for reverse scaling of default voltage scaling function. Defined for + compatible property "qcom,spmi-adc5-gen3". + NOTE: For compatible property "qcom,spmi-vadc" following channels, also known as @@ -160,7 +187,7 @@ configuration nodes should be defined: VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, VADC_GND_REF and VADC_VDD_VADC. -Example: +Example1: #include #include @@ -192,3 +219,49 @@ Example: io-channels = <&pmic_vadc VADC_LR_MUX10_USB_ID>; io-channel-names = "vadc"; }; + +Example2: + +#include +#include +/* ... */ + + /* VADC node */ + pm5100_adc: adc@8000 { + compatible = "qcom,spmi-adc-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x80 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + #thermal-sensor-cells = <1>; + + pm5100_die_temp { + reg = ; + label = "pm5100_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm5100_xo_therm { + reg = ; + label = "pm5100_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm5100_vph_pwr { + reg = ; + label = "pm5100_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + + /* IIO client node */ + batt { + io-channels = <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>; + io-channel-names = "vph_pwr"; + }; From 0ede632f8c1357634ad98c86e1ebece2c5626c06 Mon Sep 17 00:00:00 2001 From: Kuichu Ni Date: Fri, 23 Apr 2021 15:47:49 +0800 Subject: [PATCH 1320/1809] ARM: dts: qcom: Add wlan node for sa6155 1. Add wlan converged node to support QCA6574/QCA6595/QCA6696 wlan devices. 2. Use the "-config" suffix to replace with "-info" because of the code changes in CNSS2, only reading property settings with "-config" suffix for vregs. Change-Id: Ib743b30f826f6dd5092db42aa0a9857e838880c4 --- qcom/sa6155-cnss.dtsi | 282 +++++++++++++++++++++++++++++++++++++++++ qcom/sa8155-cnss.dtsi | 2 +- qcom/sa8195p-cnss.dtsi | 2 +- 3 files changed, 284 insertions(+), 2 deletions(-) diff --git a/qcom/sa6155-cnss.dtsi b/qcom/sa6155-cnss.dtsi index 76ae6b88e3c6..335a6937ce2b 100644 --- a/qcom/sa6155-cnss.dtsi +++ b/qcom/sa6155-cnss.dtsi @@ -36,8 +36,290 @@ qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; qcom,bt-vdd-rfa3-config = <1904000 1904000 450000 0>; }; + + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-rfa1-supply = <&pm6155_1_s6>; + vdd-wlan-rfa2-supply = <&pm6155_1_s5>; + vdd-wlan-rfa3-supply = <&pm6155_1_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; + wlan-en-gpio = <&tlmm 98 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-config = <0 0 0 10 1>; + + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; }; &qupv3_se7_4uart { status = "ok"; }; + +&pcie_rc0 { + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "no-CFRE", + "non-fatal"; + }; + }; +}; diff --git a/qcom/sa8155-cnss.dtsi b/qcom/sa8155-cnss.dtsi index ee72cce892d3..a21d999a9444 100644 --- a/qcom/sa8155-cnss.dtsi +++ b/qcom/sa8155-cnss.dtsi @@ -84,7 +84,7 @@ supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; - qcom,vdd-wlan-info = <0 0 0 10 1>; + qcom,vdd-wlan-config = <0 0 0 10 1>; qcom,wlan-ramdump-dynamic = <0x200000>; }; diff --git a/qcom/sa8195p-cnss.dtsi b/qcom/sa8195p-cnss.dtsi index 251800fa1cf6..f6d3076f7c5b 100644 --- a/qcom/sa8195p-cnss.dtsi +++ b/qcom/sa8195p-cnss.dtsi @@ -82,7 +82,7 @@ supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; - qcom,vdd-wlan-info = <0 0 0 10 1>; + qcom,vdd-wlan-config = <0 0 0 10 1>; qcom,wlan-ramdump-dynamic = <0x200000>; }; From 2317b5f55b45ccda33400720b02f14dd2a897eec Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 28 Apr 2021 00:11:55 -0400 Subject: [PATCH 1321/1809] ARM: dts: msm: Enable LLCC support in IOSS for sdxlemur Enable LLCC support in IOSS v2 for sdxlemur for ethernet link speeds higher than 5 Gbps. Change-Id: Ibaa0dcd411d0fbc3324bed6a72c878e04e719b45 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 114324fb5276..3d48aeb17081 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -897,6 +897,7 @@ ioss: qcom,ioss { compatible = "qcom,ioss-v2"; + qcom,max-ddr-bandwidth = <5000>; }; pcie_ep: qcom,pcie@40002000 { From 0f10f878e88af23778c212e6326122e66679a769 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 28 Apr 2021 11:39:18 +0530 Subject: [PATCH 1322/1809] ARM: dts: msm: Update clock frequenices for PCIe 2nd instance Clock frequencies for PCIe 2nd instance are not passed correctly due to which frequency for pcie1_phy_rchng_clk is not set to 100MHz. This results in link training fail in Gen3 speed. Hence update clock frequencies passed for PCIe 2nd instance to fix the issue. Change-Id: I3065ebf725ecd8980057588e7bf93cb8ccedf51a --- qcom/yupik-pcie.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 66476baf7f8b..557d9d49725f 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -365,7 +365,8 @@ "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_PHY_BCR>; From 3f9968c71f63f85d2611bd90169762e65d496c1a Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 9 Mar 2021 10:33:21 +0530 Subject: [PATCH 1323/1809] ARM: dts: msm: Add GPUCC clock node and GDSCs for MONACO GPUCC clock nodes is required for clocks client to request, so add support for the same. Also add the GDSCs required by clients for MONACO. Change-Id: I2eb3f35e48a1f7f44c93df64384cee1af871416a --- qcom/monaco-gdsc.dtsi | 4 ++-- qcom/monaco.dtsi | 11 ++++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi index 88829cb6e9fa..d68823eeb79e 100644 --- a/qcom/monaco-gdsc.dtsi +++ b/qcom/monaco-gdsc.dtsi @@ -71,7 +71,7 @@ }; gpu_cx_gdsc: qcom,gdsc@5994064 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x5994064 0x4>; regulator-name = "gpu_cx_gdsc"; hw-ctl-addr = <&gpu_cx_hw_ctrl>; @@ -80,7 +80,7 @@ }; gpu_gx_gdsc: qcom,gdsc@599400c { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x599400c 0x4>; regulator-name = "gpu_gx_gdsc"; sw-reset = <&gpu_gx_sw_reset>; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3e9883ccbcad..4b96b0aa38ca 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -710,9 +710,14 @@ #reset-cells = <1>; }; - gpucc: clock-controller@5994000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + gpucc: clock-controller@5990000 { + compatible = "qcom,monaco-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main"; + vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; }; From baf2148b920744be0b70e053e88c239fa270958e Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Tue, 13 Apr 2021 14:06:30 -0700 Subject: [PATCH 1324/1809] bindings: Use list of PCIe RC ports for WLAN device CNSS driver will retry PCIe RC ports with the same order from the list if it fails to enumerate the device attached to the port. Hence update bindings document for it. Change-Id: Ibfcd6f72072650118b8abfa27c818a1933080171 --- bindings/cnss/cnss-wlan.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index deb8508b9a8e..284ef3b1d350 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -23,7 +23,8 @@ Required properties: - pinctrl-names: Names corresponding to the numbered pinctrl states - pinctrl-: Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt - - qcom,wlan-rc-num: PCIe root complex number which WLAN chip is attached to + - qcom,wlan-rc-num: List of PCIe root complex numbers which WLAN device may + attach to Optional properties: - qcom,notify-modem-status: Boolean property to decide whether modem From cdbafa00331ea2a1ba4a4423565c78ce5311ee7e Mon Sep 17 00:00:00 2001 From: Srinu Gorle Date: Fri, 5 Feb 2021 10:49:24 +0530 Subject: [PATCH 1325/1809] ARM: dts: msm: Add scuba video dtsi in target dtsi Add scuba video dtsi in bengal dtsi to enable the video device. Change-Id: I04d7d1f4b1897a88c4d2489f134192b9d306e187 --- qcom/scuba-vidc.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 qcom/scuba-vidc.dtsi diff --git a/qcom/scuba-vidc.dtsi b/qcom/scuba-vidc.dtsi new file mode 100644 index 000000000000..faa99d78252a --- /dev/null +++ b/qcom/scuba-vidc.dtsi @@ -0,0 +1,88 @@ +&soc { + msm_vidc: qcom,vidc@5a00000 { + compatible = "qcom,msm-vidc", "qcom,scuba-vidc"; + status = "ok"; + reg = <0x5a00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&gcc_venus_gdsc>; + venus-core0-supply = <&gcc_vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; + qcom,allowed-clock-rates = <133330000 240000000>; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_VENUS_CFG>, + <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; + + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 2128000>; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x860 0x00>, + <&apps_smmu 0x880 0x00>; + qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x861 0x04>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x863 0x0>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x804 0xE0>; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; From 6434a084d3c8fb0960cda63f8637c5d5d57161f9 Mon Sep 17 00:00:00 2001 From: Srinu Gorle Date: Fri, 5 Feb 2021 17:04:41 +0530 Subject: [PATCH 1326/1809] ARM: dts: msm: Add bus topology in Scuba Venus PIL Bus topology is required for bus scaling driver to serve the bandwidth requests from various clients. Add the same for scuba venus PIL. Change-Id: Iadce1e9be6d5274d3df8d6ce1443cdac2751175d --- qcom/scuba-iot.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 4e20bf61373f..2fad11ccdd3f 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1004,6 +1004,31 @@ dcc: dcc_v2@1be2000 { qcom,ea-pc = <0x360>; status = "ok"; }; + qcom,venus@5ab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ab0000 0x20000>; + + vdd-supply = <&gcc_venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + + qcom,core-freq = <240000000>; + qcom,ahb-freq = <240000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "pm2250.dtsi" From 4ef38c621bd7d099c99c5a96ecaf9316dbfb8c50 Mon Sep 17 00:00:00 2001 From: Srinu Gorle Date: Fri, 5 Feb 2021 17:01:58 +0530 Subject: [PATCH 1327/1809] ARM: dts: msm: Add video dtsi in scuba target dtsi Add video dtsi in scuba main target dtsi. Change-Id: I671cd3586dcd63b0a2e39c0a771a6177fac93943 --- qcom/scuba-iot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 2fad11ccdd3f..b60a58d63561 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1038,6 +1038,7 @@ dcc: dcc_v2@1be2000 { #include "scuba-ion.dtsi" #include "msm-arm-smmu-scuba.dtsi" #include "scuba-audio.dtsi" +#include "scuba-vidc.dtsi" &qupv3_se1_i2c { #address-cells = <1>; From cdd5fbc8eaea40b7e02fc0733ab4ec90164ebd51 Mon Sep 17 00:00:00 2001 From: Jayadev K Date: Thu, 29 Apr 2021 13:06:51 +0530 Subject: [PATCH 1328/1809] ARM: dts: qcom: Add HS-I2S device tree support on SA8195 1. Add device nodes for HS-I2S interface. 2. Correct gpio function in sleep state. Change-Id: If1c986f64f314c0fb0134dee831236739e4a1d02 --- qcom/sa8195p.dtsi | 101 ++++++++++++++++++++++++++++++++++++ qcom/sdmshrike-pinctrl.dtsi | 2 +- qcom/sm8150-pinctrl.dtsi | 2 +- 3 files changed, 103 insertions(+), 2 deletions(-) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 392a9323f0b4..f948d707cf54 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -29,6 +29,107 @@ read-only; ranges; }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <3>; + reg = <0x172C0000 0x28000>, + <0x17080000 0xE000>; + reg-names = "lpa_if", "lpass_tcsr"; + interrupts = ; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x1B5C 0x1>, + <&apps_smmu 0x1B5E 0x0>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active + &hs1_i2s_ws_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep + &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active + &hs2_i2s_ws_active &hs2_i2s_data0_active + &hs2_i2s_data1_active>; + pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep + &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep + &hs2_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr2: qcom,hs2_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active + &hs3_i2s_ws_active &hs3_i2s_data0_active + &hs3_i2s_data1_active>; + pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep + &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep + &hs3_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + }; }; &scc { diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index 4bb550245cd9..64531df19b7b 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -2996,7 +2996,7 @@ hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { mux { pins = "gpio158"; - function = "sleep"; + function = "gpio"; }; config { diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index 01b748976c9a..ed449a36f0dd 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -4454,7 +4454,7 @@ hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { mux { pins = "gpio158"; - function = "sleep"; + function = "gpio"; }; config { From 189b56c01400ac0b7be464d31c69e125fff36c44 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 13 Apr 2021 22:37:24 +0530 Subject: [PATCH 1329/1809] dt-bindings: qcom: Add boolean flag to enable concurrency mode DT property to control charger concurrency mode. Its supported only on PM5100. Change-Id: I2350aae371e6a711e2ff576d2a31d81f3d7ca398 --- bindings/power/supply/qcom/qpnp-smblite.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/power/supply/qcom/qpnp-smblite.txt b/bindings/power/supply/qcom/qpnp-smblite.txt index 137518e988eb..0b5f59ae63fa 100644 --- a/bindings/power/supply/qcom/qpnp-smblite.txt +++ b/bindings/power/supply/qcom/qpnp-smblite.txt @@ -196,6 +196,12 @@ Charger specific properties: Definition: Specifies the step size of each step of FCC stepper algorithm. If left unspecified, the default value is 100mA. +- qcom,concurrency-mode-enable + Usage: optional + Value type: bool + Definition: Boolean flag to control charger concurrency mode. Its supported + only on PM5100, By default this feature is disabled. + ================================================= Second Level Nodes - SMBLITE Charger Peripherals ================================================= From 68b92868ebdda2402ce29dc856cc775e743c5e56 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 23 Apr 2021 10:34:08 -0700 Subject: [PATCH 1330/1809] ARM: dts: msm: Add thermal configuration for sdxlemur Add thermal configuration to, 1. enable all the modem QMI based sensors 2. add modem junction temperature rule 3. enable all the modem QMI based mitigation devices 4. add CPU junction temperature rule. Change-Id: Ieb6cc3feaf81c74f9248aef47a79260af6d656e0 --- qcom/sdxlemur-thermal-modem.dtsi | 632 +++++++++++++++++++++++++++++++ qcom/sdxlemur-thermal.dtsi | 230 +++++++++++ 2 files changed, 862 insertions(+) create mode 100644 qcom/sdxlemur-thermal-modem.dtsi diff --git a/qcom/sdxlemur-thermal-modem.dtsi b/qcom/sdxlemur-thermal-modem.dtsi new file mode 100644 index 000000000000..1a06dee942bd --- /dev/null +++ b/qcom/sdxlemur-thermal-modem.dtsi @@ -0,0 +1,632 @@ +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_lte_dsc: modem_lte_dsc { + qcom,qmi-dev-name = "modem_lte_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_dsc: modem_nr_dsc { + qcom,qmi-dev-name = "modem_nr_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_dsc: modem_nr_scg_dsc { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + #cooling-cells = <2>; + }; + + sdr0_lte_dsc: sdr0_lte_dsc { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr1_lte_dsc: sdr1_lte_dsc { + qcom,qmi-dev-name = "sdr1_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr0_nr_dsc: sdr0_nr_dsc { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + #cooling-cells = <2>; + }; + + sdr1_nr_dsc: sdr1_nr_dsc { + qcom,qmi-dev-name = "sdr1_nr_dsc"; + #cooling-cells = <2>; + }; + + pa_sdr0_dsc: pa_sdr0_dsc { + qcom,qmi-dev-name = "pa_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_sdr1_dsc: pa_sdr1_dsc { + qcom,qmi-dev-name = "pa_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_fr1_sdr0_dsc: pa_fr1_sdr0_dsc { + qcom,qmi-dev-name = "pa_fr1_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_fr1_sdr1_dsc: pa_fr1_sdr1_dsc { + qcom,qmi-dev-name = "pa_fr1_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_fr1_sdr0_scg_dsc: pa_fr1_sdr0_scg_dsc { + qcom,qmi-dev-name = "pa_fr1_sdr0_scg_dsc"; + #cooling-cells = <2>; + }; + + pa_fr1_sdr1_scg_dsc: pa_fr1_sdr1_scg_dsc { + qcom,qmi-dev-name = "pa_fr1_sdr1_scg_dsc"; + #cooling-cells = <2>; + }; + + mmw0_dsc: mmw0_dsc { + qcom,qmi-dev-name = "mmw0_dsc"; + #cooling-cells = <2>; + }; + + mmw1_dsc: mmw1_dsc { + qcom,qmi-dev-name = "mmw1_dsc"; + #cooling-cells = <2>; + }; + + mmw2_dsc: mmw2_dsc { + qcom,qmi-dev-name = "mmw2_dsc"; + #cooling-cells = <2>; + }; + + mmw3_dsc: mmw3_dsc { + qcom,qmi-dev-name = "mmw3_dsc"; + #cooling-cells = <2>; + }; + + mmw_ul_throttling_dsc: mmw_ul_throttling_dsc { + qcom,qmi-dev-name = "mmw_ul_throttling_dsc"; + #cooling-cells = <2>; + }; + + mmw_ific_dsc: mmw_ific_dsc { + qcom,qmi-dev-name = "mmw_ific_dsc"; + #cooling-cells = <2>; + }; + + qmi_wlan: wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + + wlan_bw: wlan_bw { + qcom,qmi-dev-name = "wlan_bw"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "pa", + "pa_1", + "qtm_therm", + "sys_therm1", + "sys_therm2", + "modem_bcl_warn", + "modem_tsens", + "modem_tsens1", + "sdr0_pa0", + "sdr0_pa1", + "sdr0_pa2", + "sdr0_pa3", + "sdr0_pa4", + "sdr0", + "sdr1_pa0", + "sdr1_pa1", + "sdr1_pa2", + "sdr1_pa3", + "sdr1_pa4", + "sdr1_pa5", + "sdr1", + "mmw0", + "mmw1", + "mmw2", + "mmw3", + "mmw_ific0"; + }; + }; +}; + +&thermal_zones { + modem-lte-sub6-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-lte-sub6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-beamer { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_QTM_THERM)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-wifi { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-ambient { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-bcl-warn { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BCL_WARN)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0-pa0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0-pa3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0-pa4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA4)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA4)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA5)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw-ific0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi index 3aed3255d650..eee39c1d8838 100644 --- a/qcom/sdxlemur-thermal.dtsi +++ b/qcom/sdxlemur-thermal.dtsi @@ -1,3 +1,5 @@ +#include + &soc { tsens0: tsens@c222000 { compatible = "qcom,tsens24xx"; @@ -12,7 +14,235 @@ }; }; +#include "sdxlemur-thermal-modem.dtsi" + &thermal_zones { + cpuss-0-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + trips { + cpu_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + cpu_cdev { + trip = <&cpu_config>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + mdmss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + trips { + mdmss1_config0: mdmss1-config0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss1_config2: mdmss1-config2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_lte_dsc 7 7>; + }; + + nr_scg_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_scg_dsc 2 2>; + }; + + nr_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_dsc 4 4>; + }; + + lte_cdev1 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev1 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev1 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss1_config2>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss1_config2>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 4>; + trips { + mdmss2_config0: mdmss2-config0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss2_config2: mdmss2-config2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_lte_dsc 7 7>; + }; + + nr_scg_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_scg_dsc 2 2>; + }; + + nr_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_dsc 4 4>; + }; + + lte_cdev1 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev1 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev1 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss2_config2>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss2_config2>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 5>; + trips { + mdmss3_config0: mdmss3-config0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss3_config2: mdmss3-config2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_lte_dsc 7 7>; + }; + + nr_scg_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_scg_dsc 2 2>; + }; + + nr_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_dsc 4 4>; + }; + + lte_cdev1 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev1 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev1 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss3_config2>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss3_config2>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; From 2199591416db05e42ef84629df6ada845fdeeccf Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Thu, 29 Apr 2021 17:49:18 -0700 Subject: [PATCH 1331/1809] ARM: dts: msm: update ab/ib votes for IPA on Olympic Make changes to use required bandwdith as the ab value for all the paths. Remove voting imem as it not required. Change-Id: Icd410dc8809b72d85288bbfcc8349dac16e4356e --- qcom/sdxlemur.dtsi | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 432531215cbe..dc6d1b625744 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1197,37 +1197,36 @@ clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; - qcom,interconnect,num-paths = <4>; + qcom,interconnect,num-paths = <3>; qcom,max_num_smmu_cb = <6>; interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>, <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, - <&system_noc MASTER_IPA &system_noc SLAVE_IMEM>, <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; - interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa"; /* No vote */ qcom,no-vote = - <0 0 0 0 0 0 0 0>; + <0 0 0 0 0 0>; /* SVS2 */ qcom,svs2 = - <150000 600000 150000 1804000 75000 300000 0 76800>; + <600000 0 600000 1900000 0 76800>; /* SVS */ qcom,svs = - <625000 1200000 625000 3072000 312500 700000 0 150000>; + <1200000 0 1200000 2800000 0 150000>; /* NOMINAL */ qcom,nominal = - <1250000 2400000 1250000 6220800 625000 1500000 0 400000>; + <2400000 0 2400000 5500000 0 400000>; /* TURBO */ qcom,turbo = - <2000000 3500000 2000000 7219200 1000000 1920000 0 400000>; + <3600000 0 3600000 5500000 0 400000>; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <600 2500 5000>; + qcom,throughput-threshold = <2000 4000 8000>; qcom,scaling-exceptions = <>; ipa_smmu_ap: ipa_smmu_ap { From 1397907fc8040a9f7e47cf5223a699c7ce437ea9 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Fri, 30 Apr 2021 10:43:04 +0530 Subject: [PATCH 1332/1809] ARM: dts: msm: Update CNSS node for BT GPIO config QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: Idd28f3c5f6c6cf6b636fd13b2f7062da9c0ce5ce --- qcom/qcx6490-cnss.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi index 6a3f68c6e68b..5c50c7e7fb45 100644 --- a/qcom/qcx6490-cnss.dtsi +++ b/qcom/qcx6490-cnss.dtsi @@ -5,6 +5,7 @@ reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; wlan-en-gpio = <&tlmm 84 0>; + qcom,bt-en-gpio = <&tlmm 85 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From a8d6cbc9bb4d65dd1fac9fd8acc4d5157b21fca1 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Thu, 25 Mar 2021 20:12:03 +0530 Subject: [PATCH 1333/1809] ARM: dts: msm: Add ACD control register values for Yupik GPU Add the dvm values to enable ACD support for all GPU power levels. Change-Id: Ia840a8c22fc86f62b9ed105e4aecb1fbd175eff2 --- qcom/yupik-gpu.dtsi | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c09538cf0ddc..02ca156dc51f 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -171,7 +171,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <802000000>; + qcom,gpu-freq = <812000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; @@ -181,6 +181,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -195,6 +197,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -209,6 +213,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@3 { @@ -223,6 +229,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@4 { @@ -237,6 +245,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@5 { @@ -251,6 +261,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; @@ -264,7 +276,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <802000000>; + qcom,gpu-freq = <812000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; @@ -274,6 +286,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -288,6 +302,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -302,6 +318,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@3 { @@ -316,6 +334,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@4 { @@ -330,6 +350,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@5 { @@ -344,6 +366,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; @@ -366,6 +390,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -380,6 +406,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -394,6 +422,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; qcom,gpu-pwrlevels-3 { @@ -415,6 +445,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -429,6 +461,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; }; From c2aea4d5a2756810e443dfce527a5b3da3f6ab44 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Fri, 30 Apr 2021 16:07:12 +0530 Subject: [PATCH 1334/1809] ARM: dts: msm: Enable cnss on 6155 guest Enable CNSS and MHI pass through changes on 6155 linux guest. Change-Id: I485961565bc4c2ee1f2f241a8054caeb899eb9cc --- qcom/sa6155p-vm.dtsi | 168 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 9e59be2a0196..11baa0e1aec0 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -145,6 +145,174 @@ gpio = <&pm6155_1_gpios 6 0>; }; + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-rfa1-supply = <&pm6155_1_s6>; + vdd-wlan-rfa2-supply = <&pm6155_1_s5>; + vdd-wlan-rfa3-supply = <&pm6155_1_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + + wlan-en-gpio = <&tlmm 98 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1904000 1904000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x80000>, From 8ebb258b3ec806f44e16b9a7f74eaf53582d136f Mon Sep 17 00:00:00 2001 From: Santoshkumar Zalake Date: Fri, 23 Apr 2021 17:56:38 +0530 Subject: [PATCH 1335/1809] dt-bindings: add bindings for gnss_sirf This change updates documentation about vendor info Change-Id: I10c76d43641146f841bc7b311a708ba6f4d77718 --- bindings/gnsssirf/gnss_sirf.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/gnsssirf/gnss_sirf.txt b/bindings/gnsssirf/gnss_sirf.txt index 18e8b251d9c5..4e7237d624df 100644 --- a/bindings/gnsssirf/gnss_sirf.txt +++ b/bindings/gnsssirf/gnss_sirf.txt @@ -10,7 +10,7 @@ Required properties: Example: ss5_pwr_ctrl0 { - compatible = "gnss_sirf"; + compatible = "qcom,gnss_sirf"; pinctrl-0 = <&ss5_pwr_ctrl_rst_on>; ssVreset-gpio = <&tlmm 87 1>; ssVonoff-gpio = <&tlmm 18 1>; From f86bfc5f48daadc9fafd09be023473289668d3a7 Mon Sep 17 00:00:00 2001 From: Naina Vaskenly Date: Mon, 3 May 2021 11:06:48 +0530 Subject: [PATCH 1336/1809] ARM: dts: msm: bindings: include camera devicetree for sa6155 Added camera devicetree bindings for sa6155 target. Change-Id: Ib3d9da074cdbe194102d45b033e149ac7ea57931 --- bindings/soc/qcom/qcom,cx_ipeak.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 bindings/soc/qcom/qcom,cx_ipeak.txt diff --git a/bindings/soc/qcom/qcom,cx_ipeak.txt b/bindings/soc/qcom/qcom,cx_ipeak.txt new file mode 100644 index 000000000000..42dd78ba50fe --- /dev/null +++ b/bindings/soc/qcom/qcom,cx_ipeak.txt @@ -0,0 +1,22 @@ +* Cx iPeak driver to handle requests from various multimedia clients. + +Cx ipeak HW module is used to limit the current drawn by various subsystem +blocks on Cx power rail. Each client needs to set their bit in tcsr register +if it is going to cross its own threshold. If all clients are going to cross +their thresholds then Cx ipeak hw module will raise an interrupt to cDSP block +to throttle cDSP's fmax. + +Required properties: + +- compatible : name of the component used for driver matching, should be one + "qcom,cx-ipeak-v1", "qcom,cx-ipeak-v2" + +- reg : physical base address and length of the register set(s), SRAM and XPU + of the component. + +Example: + + cx_ipeak_lm: cx_ipeak@1fe5040 { + compatible = "qcom,cx-ipeak-v1"; + reg = <0x01fe5040 0x28>; + }; From 91a9aa59f5b7618c2a39c41fdc8f6e9b764986b4 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Thu, 29 Apr 2021 16:53:11 +0530 Subject: [PATCH 1337/1809] ARM: dts: msm: Add rmtfs_sharedmem support for monaco Add shared memory support to enable rmt_storage service in userspace that allows other processor to access the primary storage device to store its data. Change-Id: I1af329fd8568439d730d3a7fea7587df5567ddb6 --- qcom/monaco.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4187cdcc689a..af7a3dfc9160 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -434,6 +434,15 @@ qcom,rtb-size = <0x100000>; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + qcom,vm-nav-path; + }; + qcom,chd_silver { compatible = "qcom,core-hang-detect"; label = "silver"; From 83ba8f604fb4aa2c8111134b3d5a9981b012961e Mon Sep 17 00:00:00 2001 From: Santoshkumar Zalake Date: Fri, 30 Apr 2021 23:46:53 +0530 Subject: [PATCH 1338/1809] ARM: dts: qcom: Add qcom in SiRF GNSS driver Add qcom as vendor for SiRF GNSS Driver Change-Id: I112cc1bf4177df99f1ae847752f315803bf0a897 --- qcom/sa8155-adp-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index a78104e01c6b..f9d32f4980b8 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -91,7 +91,7 @@ }; ss5_pwr_ctrl0 { - compatible = "gnss_sirf"; + compatible = "qcom,gnss_sirf"; pinctrl-0 = <&ss5_pwr_ctrl_rst_on>; ssVreset-gpio = <&tlmm 11 1>; ssVonoff-gpio = <&tlmm 39 1>; From 9e715d67ce60ea6f82c93b38c3d51a1bce21a182 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 4 May 2021 13:26:59 +0530 Subject: [PATCH 1339/1809] dt-bindings: thermal: Snapshot of lmh cpu VDD driver document from msm-4.19 Add a snapshot of limits cpu voltage cooling device driver document from msm-4.19. This is snapshot as of 'commit <683e0411b258> ("dt-bindings: thermal: Add limits CPU voltage cooling device")'. Change-Id: I2de821ec34d89e0c9d1702ebb322267f4c8ea943 --- bindings/thermal/qti-lmh-cpu-vdd-cdev.txt | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 bindings/thermal/qti-lmh-cpu-vdd-cdev.txt diff --git a/bindings/thermal/qti-lmh-cpu-vdd-cdev.txt b/bindings/thermal/qti-lmh-cpu-vdd-cdev.txt new file mode 100644 index 000000000000..40bf2a14b8be --- /dev/null +++ b/bindings/thermal/qti-lmh-cpu-vdd-cdev.txt @@ -0,0 +1,33 @@ +QTI LMH CPU Voltage cooling devices. + +The LMH CPU voltage cooling device will be used to place voltage restriction +vote on CPU railway during cold thermal condition. This cooling device driver +will register one cooling device per LLM, which can be used by thermal zone to +place voltage restriction vote. + +Properties: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,lmh-cpu-vdd" + +Cooling device node: +- reg: + Usage: Required + Value type: + Definition: where 'a' is the starting register address of the LLM + and 'b' is the size of LLM address space. + +- #cooling-cells: + Usage: required + Value type: + Definition: Must be 2. Needed for of_thermal as cooling device + identifier. Please refer to + for more + details. +Example: + lmh_cpu_vdd0: qcom,lmh-cpu-vdd@18350800 { + compatible = "qcom,lmh-cpu-vdd"; + reg = <0x18350800 0x1000>; + #cooling-cells = <2>; + }; From 77fa0b237e48271c9f3c3434392575149e3ec6c2 Mon Sep 17 00:00:00 2001 From: Jayadev K Date: Tue, 4 May 2021 18:16:49 +0530 Subject: [PATCH 1340/1809] ARM: dts: qcom: Add HS-I2S device tree support on SA6155 Add device nodes for HS-I2S interface on 5.4 kernel. Change-Id: I37525470729caf1c9bafd147a83a39289f25b774 --- qcom/sa6155p.dtsi | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 470c7f12a7d2..cdb73870c1fc 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -40,6 +40,84 @@ read-only; ranges; }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <2>; + reg = <0x1B40000 0x28000>; + reg-names = "lpa_if"; + interrupts = ; + clocks = <&gcc GCC_SDR_CORE_CLK>, + <&gcc GCC_SDR_WR0_MEM_CLK>, + <&gcc GCC_SDR_WR1_MEM_CLK>, + <&gcc GCC_SDR_WR2_MEM_CLK>, + <&gcc GCC_SDR_CSR_HCLK>; + clock-names = "core_clk", "wr0_mem_clk", + "wr1_mem_clk", "wr2_mem_clk", + "csr_hclk"; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x035C 0x1>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active + &hs0_i2s_data1_active>; + pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep + &hs0_i2s_data1_sleep>; + clocks = <&gcc GCC_SDR_PRI_MI2S_CLK>; + clock-names = "pri_mi2s_clk"; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + clocks = <&gcc GCC_SDR_SEC_MI2S_CLK>; + clock-names = "sec_mi2s_clk"; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + }; }; &qusb_phy0 { From 4a78328749ab7c4ed0d1d8cfbf9e8a973b12a00a Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 16 Apr 2021 16:05:15 +0530 Subject: [PATCH 1341/1809] ARM: dts: msm: Update GPU revision for Shima Shima GPU correct revision is 642. Update the compatible string to reflect correct revision. Change-Id: I8ee50be2116a9f203c6f15298e1549d1e19aa0a6 --- bindings/gpu/adreno.txt | 2 +- qcom/shima-gpu.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 8e0bcc8566ca..075ae20dd9d9 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -6,7 +6,7 @@ Required properties: - compatible: Must be "qcom,kgsl-3d0". May also includes "qcom,adreno-gpu-*" for few targets. Must include "qcom,adreno-gpu-a619-holi" for Holi target. - Must include "qcom,adreno-gpu-a660-shima" for Shima target. + Must include "qcom,adreno-gpu-a642" for Shima target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 69e3fbc592f8..0022d07aed6a 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -11,7 +11,7 @@ msm_gpu: qcom,kgsl-3d0@3d00000 { compatible = "qcom,kgsl-3d0", - "qcom,adreno-gpu-a660-shima"; + "qcom,adreno-gpu-a642"; status = "ok"; reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, From 8dc8f761f8590342c50e8c6a520575f76818d2e9 Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Tue, 27 Apr 2021 19:15:42 -0700 Subject: [PATCH 1342/1809] ARM: dts: msm: Update PHY sequence for sdxlemur Add PHY sequence for PCIE4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 to support two additional FLL frequencies. Change-Id: I657e984037f9228be9fec9ff01e02474a386e4f5 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 114324fb5276..45fb37b692c9 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1116,6 +1116,7 @@ 0x1584 0x28 0x0 0x1370 0x2e 0x0 0x155c 0x2e 0x0 + 0x1484 0x08 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; From 8be455bb75c8a1e3f1dada771fa97ddba6dafd53 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Wed, 10 Mar 2021 11:15:26 +0530 Subject: [PATCH 1343/1809] ARM: dts: msm: Add device tree variants for Monaco Add initial dts files for Monaco. Change-Id: I5a44d60cbc31aa6e0f7d930d6f44a902942ead04 --- bindings/arm/msm/msm.txt | 5 +++++ qcom/Makefile | 24 +++++++++++++++++++++-- qcom/monaco-idp-v1-overlay.dts | 9 +++++++++ qcom/monaco-idp-v1.dts | 10 ++++++++++ qcom/monaco-idp-v1.dtsi | 0 qcom/monaco-idp-v2-overlay.dts | 9 +++++++++ qcom/monaco-idp-v2.dts | 10 ++++++++++ qcom/monaco-idp-v2.dtsi | 0 qcom/monaco-idp-v3-overlay.dts | 9 +++++++++ qcom/monaco-idp-v3.dts | 10 ++++++++++ qcom/monaco-idp-v3.dtsi | 0 qcom/monaco-rumi-overlay.dts | 2 -- qcom/monaco-standalone-idp-v1-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v1.dts | 10 ++++++++++ qcom/monaco-standalone-idp-v1.dtsi | 0 qcom/monaco-standalone-idp-v2-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v2.dts | 10 ++++++++++ qcom/monaco-standalone-idp-v2.dtsi | 0 qcom/monaco-standalone-idp-v3-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v3.dts | 10 ++++++++++ qcom/monaco-standalone-idp-v3.dtsi | 0 qcom/monacop-idp-v1.dts | 10 ++++++++++ qcom/monacop.dts | 9 +++++++++ qcom/monacop.dtsi | 7 +++++++ 24 files changed, 167 insertions(+), 4 deletions(-) create mode 100644 qcom/monaco-idp-v1-overlay.dts create mode 100644 qcom/monaco-idp-v1.dts create mode 100644 qcom/monaco-idp-v1.dtsi create mode 100644 qcom/monaco-idp-v2-overlay.dts create mode 100644 qcom/monaco-idp-v2.dts create mode 100644 qcom/monaco-idp-v2.dtsi create mode 100644 qcom/monaco-idp-v3-overlay.dts create mode 100644 qcom/monaco-idp-v3.dts create mode 100644 qcom/monaco-idp-v3.dtsi create mode 100644 qcom/monaco-standalone-idp-v1-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v1.dts create mode 100644 qcom/monaco-standalone-idp-v1.dtsi create mode 100644 qcom/monaco-standalone-idp-v2-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v2.dts create mode 100644 qcom/monaco-standalone-idp-v2.dtsi create mode 100644 qcom/monaco-standalone-idp-v3-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v3.dts create mode 100644 qcom/monaco-standalone-idp-v3.dtsi create mode 100644 qcom/monacop-idp-v1.dts create mode 100644 qcom/monacop.dts create mode 100644 qcom/monacop.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index f9c00aca2cb5..f6441369dc2f 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -107,6 +107,9 @@ SoCs: - MONACO compatible = "qcom,monaco" +- MONACOP + compatible = "qcom,monacop" + - SDXNIGHTJAR compatible = "qcom,sdxnightjar" @@ -291,6 +294,8 @@ compatible = "qcom,holi-atp" compatible = "qcom,blair-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" +compatible = "qcom,monaco" +compatible = "qcom,monacop" compatible = "qcom,sdxnightjar-mtp" compatible = "qcom,sdxnightjar-cdp" compatible = "qcom,sdxnightjar-qrd" diff --git a/qcom/Makefile b/qcom/Makefile index 1c8e445a5ab3..1f151607651e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -220,11 +220,31 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_MONACO) += \ - monaco-rumi-overlay.dtbo + monaco-rumi-overlay.dtbo \ + monaco-standalone-idp-v1-overlay.dtbo \ + monaco-standalone-idp-v2-overlay.dtbo \ + monaco-standalone-idp-v3-overlay.dtbo \ + monaco-idp-v1-verlay.dtbo \ + monaco-idp-v2-overlay.dtbo \ + monaco-idp-v3-overlay.dtbo monaco-rumi-overlay.dtbo-base := monaco.dtb +monaco-standalone-idp-v1-overlay.dtbo-base := monaco.dtb +monaco-standalone-idp-v2-overlay.dtbo-base := monaco.dtb +monaco-standalone-idp-v3-overlay.dtbo-base := monaco.dtb +monaco-idp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb +monaco-idp-v2-overlay.dtbo-base := monaco.dtb +monaco-idp-v3-overlay.dtbo-base := monaco.dtb + else -dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb +dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb \ + monaco-standalone-idp-v1.dtb \ + monaco-standalone-idp-v2.dtb \ + monaco-standalone-idp-v3.dtb \ + monaco-idp-v1.dtb \ + monaco-idp-v2.dtb \ + monaco-idp-v3.dtb \ + monacop-idp-v1.dtb endif dtb-$(CONFIG_ARCH_SCUBA) += qrb2210-rb1.dtb diff --git a/qcom/monaco-idp-v1-overlay.dts b/qcom/monaco-idp-v1-overlay.dts new file mode 100644 index 000000000000..2d46bdbd323a --- /dev/null +++ b/qcom/monaco-idp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V1.0"; + qcom,board-id = <0x010022 0x0>; +}; diff --git a/qcom/monaco-idp-v1.dts b/qcom/monaco-idp-v1.dts new file mode 100644 index 000000000000..cfcca8abfad9 --- /dev/null +++ b/qcom/monaco-idp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V1.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x010022 0x0>; +}; diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-idp-v2-overlay.dts b/qcom/monaco-idp-v2-overlay.dts new file mode 100644 index 000000000000..24f7976eb669 --- /dev/null +++ b/qcom/monaco-idp-v2-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V2.0"; + qcom,board-id = <0x020022 0x0>; +}; diff --git a/qcom/monaco-idp-v2.dts b/qcom/monaco-idp-v2.dts new file mode 100644 index 000000000000..d5255c3f43db --- /dev/null +++ b/qcom/monaco-idp-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V2.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x020022 0x0>; +}; diff --git a/qcom/monaco-idp-v2.dtsi b/qcom/monaco-idp-v2.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-idp-v3-overlay.dts b/qcom/monaco-idp-v3-overlay.dts new file mode 100644 index 000000000000..8dd05c6e9b8b --- /dev/null +++ b/qcom/monaco-idp-v3-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V3.0"; + qcom,board-id = <0x030022 0x0>; +}; diff --git a/qcom/monaco-idp-v3.dts b/qcom/monaco-idp-v3.dts new file mode 100644 index 000000000000..d8ed64279c77 --- /dev/null +++ b/qcom/monaco-idp-v3.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco IDP V3.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x030022 0x0>; +}; diff --git a/qcom/monaco-idp-v3.dtsi b/qcom/monaco-idp-v3.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-rumi-overlay.dts b/qcom/monaco-rumi-overlay.dts index 05c56ab9fafa..0864e5e2b786 100644 --- a/qcom/monaco-rumi-overlay.dts +++ b/qcom/monaco-rumi-overlay.dts @@ -5,7 +5,5 @@ / { model = "Qualcomm Technologies, Inc. Monaco RUMI"; - compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; - qcom,msm-id = <486 0x10000>; qcom,board-id = <15 0>; }; diff --git a/qcom/monaco-standalone-idp-v1-overlay.dts b/qcom/monaco-standalone-idp-v1-overlay.dts new file mode 100644 index 000000000000..22c69bedebc2 --- /dev/null +++ b/qcom/monaco-standalone-idp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V1.0"; + qcom,board-id = <0x010022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v1.dts b/qcom/monaco-standalone-idp-v1.dts new file mode 100644 index 000000000000..f19c036a2aef --- /dev/null +++ b/qcom/monaco-standalone-idp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-standalone-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V1.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x010022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-standalone-idp-v2-overlay.dts b/qcom/monaco-standalone-idp-v2-overlay.dts new file mode 100644 index 000000000000..a3d1a9246a59 --- /dev/null +++ b/qcom/monaco-standalone-idp-v2-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V2.0"; + qcom,board-id = <0x020022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v2.dts b/qcom/monaco-standalone-idp-v2.dts new file mode 100644 index 000000000000..b27dd6a30c1c --- /dev/null +++ b/qcom/monaco-standalone-idp-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-standalone-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V2.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x020022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v2.dtsi b/qcom/monaco-standalone-idp-v2.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-standalone-idp-v3-overlay.dts b/qcom/monaco-standalone-idp-v3-overlay.dts new file mode 100644 index 000000000000..253330f8b56d --- /dev/null +++ b/qcom/monaco-standalone-idp-v3-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V3.0"; + qcom,board-id = <0x030022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v3.dts b/qcom/monaco-standalone-idp-v3.dts new file mode 100644 index 000000000000..c03b6af014d6 --- /dev/null +++ b/qcom/monaco-standalone-idp-v3.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-standalone-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone DP V3.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x030022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v3.dtsi b/qcom/monaco-standalone-idp-v3.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monacop-idp-v1.dts b/qcom/monacop-idp-v1.dts new file mode 100644 index 000000000000..d755480022da --- /dev/null +++ b/qcom/monacop-idp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monacop.dtsi" +#include "monaco-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MonacoP IDP V1.0"; + compatible = "qcom,monaco", "qcom,idp"; + qcom,board-id = <0x010022 0x0>; +}; diff --git a/qcom/monacop.dts b/qcom/monacop.dts new file mode 100644 index 000000000000..1f3281068cc7 --- /dev/null +++ b/qcom/monacop.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "monacop.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MonacoP SoC"; + compatible = "qcom,monacop"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/monacop.dtsi b/qcom/monacop.dtsi new file mode 100644 index 000000000000..ac4efcf7f507 --- /dev/null +++ b/qcom/monacop.dtsi @@ -0,0 +1,7 @@ +#include "monaco.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MonacoP"; + compatible = "qcom,monacop"; + qcom,msm-id = <517 0x10000>; +}; From 05547a8ab21f47638abb0869f3414519fb859433 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 26 Nov 2020 13:44:50 +0530 Subject: [PATCH 1344/1809] ARM: dts: msm: Add LPM device nodes and stats for Monaco Add Low Power Modes, soc sleep stats and rpm master stats device nodes. Change-Id: If49a907ff39b9c39e007530708799a4f0f85cbac --- qcom/monaco-pm.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 5 +++ 2 files changed, 95 insertions(+) create mode 100644 qcom/monaco-pm.dtsi diff --git a/qcom/monaco-pm.dtsi b/qcom/monaco-pm.dtsi new file mode 100644 index 000000000000..3b67d4b32af0 --- /dev/null +++ b/qcom/monaco-pm.dtsi @@ -0,0 +1,90 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l2-wfi"; + entry-latency-us = <38>; + exit-latency-us = <51>; + min-residency-us = <89>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l2-rail-pc"; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,notify-rpm; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + label = "pwr"; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + CORE_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <49>; + exit-latency-us = <42>; + min-residency-us = <91>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + CORE_PC: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + qcom,psci-cpu-mode = <0x3>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpm_sleep_stats: soc-sleep-stats@4690000 { + compatible = "qcom,rpm-sleep-stats"; + reg = <0x04690000 0x400>; + }; + + subsystem-sleep-stats { + compatible = "qcom,subsystem-sleep-stats"; + }; + + rpmh-master-stats { + compatible = "qcom,rpmh-master-stats-v1"; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4187cdcc689a..f34adb3d7534 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -34,6 +34,7 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; + cpu-idle-states = <&CORE_PC>; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -58,6 +59,7 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; + cpu-idle-states = <&CORE_PC>; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -77,6 +79,7 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; + cpu-idle-states = <&CORE_PC>; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -96,6 +99,7 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; + cpu-idle-states = <&CORE_PC>; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -1119,6 +1123,7 @@ #include "monaco-stub-regulator.dtsi" #include "monaco-gdsc.dtsi" #include "monaco-qupv3.dtsi" +#include "monaco-pm.dtsi" &qupv3_se6_2uart { status = "ok"; From 700adaae0345a57603b6b4d7f1f908156b44ba18 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 26 Nov 2020 14:14:02 +0530 Subject: [PATCH 1345/1809] ARM: dts: msm: Add system_pm_rpm node for Monaco Add System_pm_rpm node. Change-Id: Iff0c7996c654770d186351c3530cb0a207eebe9a --- qcom/monaco.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f34adb3d7534..9122227a77af 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1115,6 +1115,10 @@ vote = <43>; }; }; + + system_pm_rpm { + compatible = "qcom,system-pm-rpm"; + }; }; #include "monaco-pinctrl.dtsi" From 1eb9c927e4fcfeec47cbe8193d6f0798c466897f Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 3 Dec 2020 16:56:38 +0530 Subject: [PATCH 1346/1809] ARM: dts: msm: Add wakeup interrupt controller for Monaco Add wakeup interrupt controller node to support wakeup capabale interrupts and add mpm as wakeup parent for TLMM. Change-Id: Icfdf050510d0102e1906a3848557e7dd806425ad --- bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/monaco-pinctrl.dtsi | 1 + qcom/monaco.dtsi | 12 ++++++++++++ 3 files changed, 14 insertions(+) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index b998c94d89f1..2b4beeeb7a37 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -26,6 +26,7 @@ Properties: "qcom,mpm-gic-holi" "qcom,mpm-gic-scuba" "qcom,mpm-gic-sdxnightjar" + "qcom,mpm-gic-monaco" - interrupts: Usage: required diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 6961c9d6e4e4..fc3bff370d59 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -7,6 +7,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&wakegic>; qupv3_se6_2uart_pins: qupv3_se6_2uart_pins { qupv3_se6_2uart_active: qupv3_se6_2uart_active { diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 9122227a77af..90685c5413d1 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1119,6 +1119,18 @@ system_pm_rpm { compatible = "qcom,system-pm-rpm"; }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-monaco", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0xf111008 0x4>; + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; }; #include "monaco-pinctrl.dtsi" From 3235bde13ed6dab8d30f6baa46beb38f1a8b9a5d Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Wed, 5 May 2021 18:18:16 +0530 Subject: [PATCH 1347/1809] ARM: dts: msm: Add vk-device-id property vk-device-id allows user to specify the unique number for specific GPU model. Change-Id: I1cc5f0fc9ef6882eb72a8578891f13ecbbc129c2 --- bindings/gpu/adreno.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 8e0bcc8566ca..ccd8e250e835 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -98,6 +98,7 @@ Optional Properties: the chip identification read from the GPU hardware. This is used to override faulty hardware readings. - qcom,gpu-model: If it exists this property is used for GPU model name. +- qcom,vk-device-id: If it exists this property is used to specify vulkan device ID. - qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event. - qcom,disable-busy-time-burst: Boolean. Disables the busy time burst to avoid switching @@ -277,6 +278,8 @@ Properties: - qcom,gpu-model: GPU model name for a specific GPU hardware. +- qcom,vk-device-id: + Vulkan device id unique for specific GPU hardware model. SOC Hardware revisions: - qcom,soc-hw-revisions: Container of sets of SOC hardware revisions specified by @@ -434,6 +437,7 @@ Example of A330 GPU in MSM8916: qcom,gpu-model@0 { qcom,gpu-model-id = <0>; qcom,gpu-model = "Adreno642Lv1"; + qcom,vk-device-id= <0x06030500>; }; } From 6ff399babfaffea2f656989b9a85abe1dc56bf71 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Wed, 17 Feb 2021 14:32:36 +0530 Subject: [PATCH 1348/1809] ARM: dts: msm: Add initial platform device tree for blair Add initial device tree to support blair platform on MTP, CDP, ATP platforms. Change-Id: I043c2e797610c1f8524cbba950ad719525af0cca --- bindings/arm/msm/msm.txt | 3 +++ qcom/Makefile | 14 ++++++++++++-- qcom/blair-atp-overlay.dts | 11 +++++++++++ qcom/blair-atp.dts | 10 ++++++++++ qcom/blair-atp.dtsi | 2 ++ qcom/blair-cdp-overlay.dts | 11 +++++++++++ qcom/blair-cdp.dts | 10 ++++++++++ qcom/blair-cdp.dtsi | 2 ++ qcom/blair-mtp-overlay.dts | 12 ++++++++++++ qcom/blair-mtp.dts | 11 +++++++++++ qcom/blair-mtp.dtsi | 2 ++ 11 files changed, 86 insertions(+), 2 deletions(-) create mode 100644 qcom/blair-atp-overlay.dts create mode 100644 qcom/blair-atp.dts create mode 100644 qcom/blair-atp.dtsi create mode 100644 qcom/blair-cdp-overlay.dts create mode 100644 qcom/blair-cdp.dts create mode 100644 qcom/blair-cdp.dtsi create mode 100644 qcom/blair-mtp-overlay.dts create mode 100644 qcom/blair-mtp.dts create mode 100644 qcom/blair-mtp.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index f6441369dc2f..e993afb45b1f 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -292,6 +292,9 @@ compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" compatible = "qcom,blair-rumi" +compatible = "qcom,blair-mtp" +compatible = "qcom,blair-cdp" +compatible = "qcom,blair-atp" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" compatible = "qcom,monaco" diff --git a/qcom/Makefile b/qcom/Makefile index 1f151607651e..c82309013266 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -120,11 +120,21 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) -dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo +dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo \ + blair-mtp-overlay.dtbo \ + blair-cdp-overlay.dtbo \ + blair-atp-overlay.dtbo blair-rumi-overlay.dtbo-base := blair.dtb +blair-mtp-overlay.dtbo-base := blair.dtb +blair-cdp-overlay.dtbo-base := blair.dtb +blair-atp-overlay.dtbo-base := blair.dtb + else -dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb +dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ + blair-mtp.dtb \ + blair-cdp.dtb \ + blair-atp.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/blair-atp-overlay.dts b/qcom/blair-atp-overlay.dts new file mode 100644 index 000000000000..3cb5e6589def --- /dev/null +++ b/qcom/blair-atp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair ATP"; + compatible = "qcom,blair-atp", "qcom,blair", "qcom,atp"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/blair-atp.dts b/qcom/blair-atp.dts new file mode 100644 index 000000000000..f9a6a9ab1028 --- /dev/null +++ b/qcom/blair-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair ATP"; + compatible = "qcom,blair-atp", "qcom,blair", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-atp.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/qcom/blair-cdp-overlay.dts b/qcom/blair-cdp-overlay.dts new file mode 100644 index 000000000000..040d921c2875 --- /dev/null +++ b/qcom/blair-cdp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair CDP"; + compatible = "qcom,blair-cdp", "qcom,blair", "qcom,cdp"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/blair-cdp.dts b/qcom/blair-cdp.dts new file mode 100644 index 000000000000..1126b6f080ce --- /dev/null +++ b/qcom/blair-cdp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair CDP"; + compatible = "qcom,blair-cdp", "qcom,blair", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-cdp.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/qcom/blair-mtp-overlay.dts b/qcom/blair-mtp-overlay.dts new file mode 100644 index 000000000000..dc4692d649ac --- /dev/null +++ b/qcom/blair-mtp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair MTP"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <8 0>; +}; + diff --git a/qcom/blair-mtp.dts b/qcom/blair-mtp.dts new file mode 100644 index 000000000000..b02097f25f9d --- /dev/null +++ b/qcom/blair-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair MTP"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,board-id = <8 0>; +}; + diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-mtp.dtsi @@ -0,0 +1,2 @@ +/ { +}; From cf10f0445c017f1930a61ee22602540b1ee30396 Mon Sep 17 00:00:00 2001 From: vagdhan kumar kanukurthi Date: Wed, 28 Apr 2021 18:04:30 +0530 Subject: [PATCH 1349/1809] ARM: dts: msm: Change renamed partition names for Direwolf guest Change virtual partition names according to guest command line on direwolf la guest. Change-Id: I99c8df985f33564d2d721752d4163749f0856b75 --- qcom/direwolf-vm-la.dtsi | 12 ++++++++++++ qcom/direwolf-vm.dtsi | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi index 9eca2745a0cb..3601f010b2b6 100644 --- a/qcom/direwolf-vm-la.dtsi +++ b/qcom/direwolf-vm-la.dtsi @@ -12,3 +12,15 @@ &usb2_phy0 { status = "okay"; }; + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 28ac3c485a95..5f1c1a9c0777 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -15,7 +15,7 @@ /delete-property/ boot_devices; fstab { vendor { - dev="/dev/block/platform/vdevs/1c160000.virtio_blk/vdc"; + dev="/dev/block/platform/vdevs/1c160000.virtio_blk/vendor"; fsmgr_flags = "wait"; }; }; From 56ceff09180d09024e78aaeab58aadb5d691c8b7 Mon Sep 17 00:00:00 2001 From: Paul Zhang Date: Wed, 28 Apr 2021 18:07:35 +0800 Subject: [PATCH 1350/1809] ARM: dts: msm: add cnss node for sa6155p-vm Add cnss node for sa6155p-vm. Change-Id: Iad330d885521857accda79628d37de88d50bcf26 --- qcom/sa6155p-vm-cnss.dtsi | 319 ++++++++++++++++++++++++++++++++++++++ qcom/sa6155p-vm.dtsi | 1 + 2 files changed, 320 insertions(+) create mode 100644 qcom/sa6155p-vm-cnss.dtsi diff --git a/qcom/sa6155p-vm-cnss.dtsi b/qcom/sa6155p-vm-cnss.dtsi new file mode 100644 index 000000000000..5c1b5b4aebf3 --- /dev/null +++ b/qcom/sa6155p-vm-cnss.dtsi @@ -0,0 +1,319 @@ +&soc { + /* PWR_CTR1_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 1 0>; + }; + + /* PWR_CTR2_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 6 0>; + }; + + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + bluetooth_ext: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 85 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-rfa1-supply = <&pm6155_1_s6>; + qcom,bt-vdd-rfa2-supply = <&pm6155_1_s5>; + qcom,bt-vdd-rfa3-supply = <&pm6155_1_l15>; + + /* */ + qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>; + qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; + qcom,bt-vdd-rfa3-config = <1904000 1904000 450000 0>; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-rfa1-supply = <&pm6155_1_s6>; + vdd-wlan-rfa2-supply = <&pm6155_1_s5>; + vdd-wlan-rfa3-supply = <&pm6155_1_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; + + wlan-en-gpio = <&tlmm 98 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-config = <0 0 0 10 1>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; +}; diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 9e59be2a0196..a951814787a2 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -424,6 +424,7 @@ #include "sm6150-qupv3.dtsi" #include "sa8155-vm-audio.dtsi" #include "pm6155-vm.dtsi" +#include "sa6155p-vm-cnss.dtsi" &tlmm { /delete-property/ wakeup-parent; From 466254a86a2f78822c4356dece0f66b4fa14f729 Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Thu, 6 May 2021 18:09:01 +0800 Subject: [PATCH 1351/1809] ARM: dts: msm: Add dcc registers lists for yupik Add DCC registers lists to support DCC register dump. Change-Id: I5fd2c0000314a22a67261ebab0b931d9604675c3 --- qcom/yupik.dtsi | 1544 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1544 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be99710aae59..55dc0da899a5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -808,6 +809,1549 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; + + link_list1 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list3 { + qcom,curr-link-list = <3>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; qcom,msm-imem@146aa000 { From 2ceed302850a4eb8169badac52119d8062132485 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Thu, 6 May 2021 19:15:09 +0530 Subject: [PATCH 1352/1809] ARM: dts: msm: Remove stub regulators from monaco rumi Remove including stub regulators in monaco-rumi.dtsi as it is already included in monaco.dtsi. Change-Id: Iba5c065b3aca718328ed9466191bdcd8bffc65b3 --- qcom/monaco-rumi.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 4e6335d2a9d0..0d2189e70578 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -13,7 +13,6 @@ }; -#include "monaco-stub-regulator.dtsi" &sdhc_1 { status = "ok"; From 22470ff8af7bf21f3569871bdd64883484e0707d Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Thu, 6 May 2021 19:00:00 +0530 Subject: [PATCH 1353/1809] ARM: dts: msm: Remove RPMh macros from monaco-regulators Remove RPMh macros from monaco-regulators.dtsi as it is RPM_SMD based design. Change-Id: I1225c08a7c5ab8e1484ff0853a09d340e3145bf4 --- qcom/monaco-regulators.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi index ff520cff6add..99d06dca19eb 100644 --- a/qcom/monaco-regulators.dtsi +++ b/qcom/monaco-regulators.dtsi @@ -155,11 +155,11 @@ regulator-max-microvolt = ; qcom,init-voltage-level = - ; + ; qcom,proxy-consumer-enable; qcom,proxy-consumer-voltage = - ; + ; qcom,use-voltage-level; }; @@ -174,7 +174,7 @@ regulator-max-microvolt = ; qcom,init-voltage-level = - ; + ; qcom,use-voltage-level; }; From e9071fb9ce1509838fad89409cbbc6038be6eac0 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 5 May 2021 12:30:53 +0530 Subject: [PATCH 1354/1809] ARM: dts: msm: Rename regulators file for holi and blair Rename "holi-regulators.dtsi" to "holi-regulators-pm6350.dtsi" for holi and blair. Change-Id: Ie6eca9882d9b38530fc269d26fd17bf5d818a6d9 --- qcom/blair.dtsi | 2 +- qcom/{holi-regulators.dtsi => holi-regulators-pm6350.dtsi} | 0 qcom/holi.dtsi | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename qcom/{holi-regulators.dtsi => holi-regulators-pm6350.dtsi} (100%) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 2618151b2517..f7091776c66d 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3363,7 +3363,7 @@ #include "blair-pinctrl.dtsi" #include "pm6350-rpm-regulator.dtsi" #include "pm6150l-rpm-regulator.dtsi" -#include "holi-regulators.dtsi" +#include "holi-regulators-pm6350.dtsi" #include "holi-gdsc.dtsi" #include "holi-ion.dtsi" #include "msm-arm-smmu-holi.dtsi" diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators-pm6350.dtsi similarity index 100% rename from qcom/holi-regulators.dtsi rename to qcom/holi-regulators-pm6350.dtsi diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 88cb863d8ac4..7f54e19f394c 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -3386,7 +3386,7 @@ #include "holi-pinctrl.dtsi" #include "pm6350-rpm-regulator.dtsi" #include "pm6150l-rpm-regulator.dtsi" -#include "holi-regulators.dtsi" +#include "holi-regulators-pm6350.dtsi" #include "holi-gdsc.dtsi" #include "holi-ion.dtsi" #include "msm-arm-smmu-holi.dtsi" From 07a057943dc7c1bfc9575fa50e0c97e76c47414a Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Thu, 6 May 2021 20:25:01 -0700 Subject: [PATCH 1355/1809] ARM: dts: msm: Add PCIe clocks and regulators for the Direwolf VM Add the clocks and regulators required for PCIe functionality on the Direwolf VM platform. Change-Id: I0287846fe6de15ab1bc02967d2ed370bf47fadc5 --- qcom/direwolf-vm.dtsi | 77 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 28ac3c485a95..f55a7e5b7464 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -206,6 +206,51 @@ offset = <768>; }; }; + + VDD_CX_LEVEL: + S1A0_LEVEL: pm8540_a0_s1_level: regulator-pm8540_a0-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8540_a0_s1_level"; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + pcie_2a_pipe_clk: pcie_2a_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_2a_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_2b_pipe_clk: pcie_2b_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_2b_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_3a_pipe_clk: pcie_3a_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_3a_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_3b_pipe_clk: pcie_3b_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_3b_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_4_pipe_clk: pcie_4_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_4_pipe_clk"; + #clock-cells = <0>; + }; }; ®ulator { @@ -217,6 +262,32 @@ regulator-name = "gcc_usb30_sec_gdsc"; }; + gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc { + regulator-name = "gcc_pcie_2a_gdsc"; + }; + + gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc { + regulator-name = "gcc_pcie_2b_gdsc"; + }; + + gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc { + regulator-name = "gcc_pcie_3a_gdsc"; + }; + + gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc { + regulator-name = "gcc_pcie_3b_gdsc"; + }; + + gcc_pcie_4_gdsc: gcc_pcie_4_gdsc { + regulator-name = "gcc_pcie_4_gdsc"; + }; + + L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 { + regulator-name = "ldoa3"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 { regulator-name = "ldoa5"; regulator-min-microvolt = <720000>; @@ -229,6 +300,12 @@ regulator-max-microvolt = <1980000>; }; + L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 { + regulator-name = "ldoa11"; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 { regulator-name = "ldoa13"; regulator-min-microvolt = <2970000>; From d5e7f51c74d3ad691f7e349ca1f1160d47157341 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Thu, 6 May 2021 20:52:01 -0700 Subject: [PATCH 1356/1809] ARM: dts: msm: Add GPIO support for the PCIe RCs on the Direwolf platform Add the GPIO definitions for PCIe RCs 2a, 2b, 3a, 3b, and 4, for the Direwolf platform. Change-Id: I9f2467e0f49f36cb27f81544d668e93f518277f7 --- qcom/direwolf-pinctrl.dtsi | 270 +++++++++++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+) diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi index e3fb955590ac..742c12f51810 100644 --- a/qcom/direwolf-pinctrl.dtsi +++ b/qcom/direwolf-pinctrl.dtsi @@ -1577,4 +1577,274 @@ }; }; }; + + pcie0 { + pcie2a_perst_default: pcie2a_perst_default { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2a_clkreq_default: pcie2a_clkreq_default { + mux { + pins = "gpio142"; + function = "pcie2a_clkreq"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2a_wake_default: pcie2a_wake_default { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2a_clkreq_sleep: pcie2a_clkreq_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie2b_perst_default: pcie2b_perst_default { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2b_clkreq_default: pcie2b_clkreq_default { + mux { + pins = "gpio144"; + function = "pcie2b_clkreq"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2b_wake_default: pcie2b_wake_default { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2b_clkreq_sleep: pcie2b_clkreq_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie3a_perst_default: pcie3a_perst_default { + mux { + pins = "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio151"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie3a_clkreq_default: pcie3a_clkreq_default { + mux { + pins = "gpio150"; + function = "pcie3a_clkreq"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_wake_default: pcie3a_wake_default { + mux { + pins = "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_clkreq_sleep: pcie3a_clkreq_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie3 { + pcie3b_perst_default: pcie3b_perst_default { + mux { + pins = "gpio153"; + function = "gpio"; + }; + + config { + pins = "gpio153"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie3b_clkreq_default: pcie3b_clkreq_default { + mux { + pins = "gpio152"; + function = "pcie3b_clkreq"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_wake_default: pcie3b_wake_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_clkreq_sleep: pcie3b_clkreq_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie4 { + pcie4_perst_default: pcie4_perst_default { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie4_clkreq_default: pcie4_clkreq_default { + mux { + pins = "gpio140"; + function = "pcie4_clkreq"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_wake_default: pcie4_wake_default { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_clkreq_sleep: pcie4_clkreq_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; }; From 0d741ad9bcefbe2ec9e72e21169a42f8ce198aeb Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Tue, 20 Apr 2021 14:27:23 +0800 Subject: [PATCH 1357/1809] ARM: dts: msm: add more dts properties for 2nd ufs Add more dts properties for 2nd ufs in 8195 gvm Change-Id: Ic6f08b7992cc1ee1473809b439c1d728d36efc2a --- qcom/sa8195-vm-ufs.dtsi | 76 +++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 33 deletions(-) diff --git a/qcom/sa8195-vm-ufs.dtsi b/qcom/sa8195-vm-ufs.dtsi index c6d35366d766..9525e90c8eba 100644 --- a/qcom/sa8195-vm-ufs.dtsi +++ b/qcom/sa8195-vm-ufs.dtsi @@ -1,10 +1,12 @@ ®ulator { L17A: pm8195_1_l17: regulator-pm8195-1-l17 { regulator-name = "ldoa17"; - regulator-min-microvolt = <1700000>; + regulator-min-microvolt = <2504000>; regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2904000>; + qcom,init-mode = <1>; regulator-always-on; - regulator-allow-set-load; + regulator-allow-set-load = <1>; }; L5C: pm8195_2_l5: regulator-pm8195-2-l5 { @@ -28,6 +30,10 @@ }; &soc { + aliases { + ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */ + }; + ufs2_ice: ufs2ice@1d70000 { compatible = "qcom,ice"; reg = <0x1d70000 0x8000>; @@ -71,6 +77,7 @@ clocks = <&dummycc RPMH_CXO_CLK>, <&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>; + resets = <&ufshc2_mem 0>; status = "disabled"; }; @@ -83,6 +90,7 @@ ufs-qcom-crypto = <&ufs2_ice>; spm-level = <5>; rpm-level = <1>; + #reset-cells = <1>; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ @@ -136,10 +144,10 @@ <0 0>, <0 0>; - qcom,msm-bus,name = "ufshc_mem"; - qcom,msm-bus,num-cases = <26>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = /* * During HS G3 UFS runs at nominal voltage corner, vote * higher bandwidth to push other buses in the data path @@ -150,38 +158,38 @@ * For max bandwidth, vote high enough to push the buses * to run in turbo voltage corner. */ - <163 512 0 0>, <1 798 0 0>, /* No vote */ - <163 512 922 0>, <1 798 1000 0>, /* PWM G1 */ - <163 512 1844 0>, <1 798 1000 0>, /* PWM G2 */ - <163 512 3688 0>, <1 798 1000 0>, /* PWM G3 */ - <163 512 7376 0>, <1 798 1000 0>, /* PWM G4 */ - <163 512 1844 0>, <1 798 1000 0>, /* PWM G1 L2 */ - <163 512 3688 0>, <1 798 1000 0>, /* PWM G2 L2 */ - <163 512 7376 0>, <1 798 1000 0>, /* PWM G3 L2 */ - <163 512 14752 0>, <1 798 1000 0>, /* PWM G4 L2 */ - <163 512 127796 0>, <1 798 1000 0>, /* HS G1 RA */ - <163 512 255591 0>, <1 798 1000 0>, /* HS G2 RA */ - <163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RA */ - <163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RA */ - <163 512 255591 0>, <1 798 1000 0>, /* HS G1 RA L2 */ - <163 512 511181 0>, <1 798 1000 0>, /* HS G2 RA L2 */ - <163 512 4194304 0>, <1 798 204800 0>, /* HS G3 RA L2 */ - <163 512 8388608 0>, <1 798 409600 0>, /* HS G4 RA L2 */ - <163 512 149422 0>, <1 798 1000 0>, /* HS G1 RB */ - <163 512 298189 0>, <1 798 1000 0>, /* HS G2 RB */ - <163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RB */ - <163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RB */ - <163 512 298189 0>, <1 798 1000 0>, /* HS G1 RB L2 */ - <163 512 596378 0>, <1 798 1000 0>, /* HS G2 RB L2 */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ /* As UFS working in HS G3 RB L2 mode, aggregated * bandwidth (AB) should take care of providing * optimum throughput requested. However, as tested, * in order to scale up CNOC clock, instantaneous * bindwidth (IB) needs to be given a proper value too. */ - <163 512 4194304 0>, <1 798 204800 409600>, /* HS G3 RB L2 */ - <163 512 8388608 0>, <1 798 409600 409600>, /* HS G4 RB L2 */ - <163 512 7643136 0>, <1 798 307200 0>; /* Max. bandwidth */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", @@ -201,9 +209,11 @@ pinctrl-0 = <&ufs0_dev_reset_assert>; pinctrl-1 = <&ufs0_dev_reset_deassert>; + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_CARD_2_BCR>; - reset-names = "core_reset"; + reset-names = "rst"; + secondary-storage; status = "disabled"; }; }; From 2b86f483558c17d2d44b72299263b47d3b692a11 Mon Sep 17 00:00:00 2001 From: Pranay Raj Anand Date: Thu, 8 Apr 2021 09:54:39 +0530 Subject: [PATCH 1358/1809] ARM: dts: msm: Enable qsee drivers for monaco Add device node entries on DT include file to enable Qseecom. The nodes added are Qseecom, tzlog and shmbridge. Change-Id: Iae9698fd8beaa82dc994f359e11fd58c1daef1dd --- qcom/monaco.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index bdb2099eea7d..42f171d9d91f 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -219,6 +219,22 @@ size = <0 0x800000>; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -456,6 +472,45 @@ 0x0f1a80b8 0x0f1b80b8>; }; + qcom_qseecom: qseecom@61800000 { + compatible = "qcom,qseecom"; + reg = <0x61800000 0x2100000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + wdog: qcom,wdt@f017000 { compatible = "qcom,msm-watchdog"; reg = <0xf017000 0x1000>; From ed622d9212a1243a125bd7c47b3849654fad4091 Mon Sep 17 00:00:00 2001 From: Pranay Raj Anand Date: Thu, 8 Apr 2021 09:42:06 +0530 Subject: [PATCH 1359/1809] ARM: dts: msm: Enable Qseecom node for monaco Add Qseecom device-tree node to provide secure communication between HLOS and TZ for Monaco target. Change-Id: Ia24cb91d2b994df586f4d332ac67fd26eb293ebd --- qcom/monaco-ion.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi index ce1a9e482129..8119d38c10ba 100644 --- a/qcom/monaco-ion.dtsi +++ b/qcom/monaco-ion.dtsi @@ -14,5 +14,29 @@ reg = ; qcom,ion-heap-type = "SYSTEM_SECURE"; }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; From 7aea0205fb7471916fb48ebc1517e4b778f2862c Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 8 Apr 2021 13:03:04 +0530 Subject: [PATCH 1360/1809] ARM: dts: msm: Add gpu-model property for shima gpu Add gpu-model property to specify gpu name for shima. Change-Id: Id0864e80668d33d1cbfca514df39a2bb552fd69e --- qcom/shima-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 0022d07aed6a..d7f0353e76e9 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -43,6 +43,7 @@ "gpu_cc_hub_cx_int"; qcom,chipid = <0x06060010>; + qcom,gpu-model = "Adreno642v1"; qcom,no-nap; From 17821bd92fefd3e1d71d25a224253ecbb12126f5 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 10 May 2021 14:34:27 +0800 Subject: [PATCH 1361/1809] ARM: dts: msm: disable mss cti Some clock for mss cti is not enabled from kernel side. so disable it. Change-Id: Iaf381620d08bbc6768eb588de9777a7529aa8708 --- qcom/sdxlemur-coresight.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 1a969e3b4942..60efffb4855e 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -1596,6 +1596,7 @@ coresight-name = "coresight-cti-mss_q6_cti"; + status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; }; @@ -1608,6 +1609,7 @@ coresight-name = "coresight-cti-mss_vq6_cti"; + status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; }; From a40c0b9edf25aa980e681f565c17134b8b787c4e Mon Sep 17 00:00:00 2001 From: Ajit Kumar Date: Mon, 10 May 2021 19:36:14 +0530 Subject: [PATCH 1362/1809] ARM: dts: qcom: Add spi node for slatecom Add entry for slatecom spi driver. Change-Id: I6d97e2af870f9bf5c781a240ab6aed809c48617b --- qcom/slate.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 qcom/slate.dtsi diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi new file mode 100644 index 000000000000..d9bca13c4fdd --- /dev/null +++ b/qcom/slate.dtsi @@ -0,0 +1,12 @@ +&soc { + qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ + status = "ok"; + qcom,slate-spi { + compatible = "qcom,slate-spi"; + reg = <0>; + spi-max-frequency = <737000>; + interrupt-parent = <&tlmm>; + qcom,irq-gpio = <&tlmm 95 1>; + }; + }; +}; From ce3b8d797a007647bced379ed92afff0072f1534 Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Mon, 10 May 2021 21:12:38 +0530 Subject: [PATCH 1363/1809] dt-bindings: usb: Document usage of new ANoc and SysNoc clocks Add the documentation for new clocks required by some platforms for accessing ANoc and SysNoc. These clocks are optional. Change-Id: Iee7d175e417db90823c95bd8a3af906551448811 --- bindings/usb/msm-ssusb.txt | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/bindings/usb/msm-ssusb.txt b/bindings/usb/msm-ssusb.txt index c06374302acc..b6304391b6df 100644 --- a/bindings/usb/msm-ssusb.txt +++ b/bindings/usb/msm-ssusb.txt @@ -9,11 +9,12 @@ Required properties : - interrupt-names : Interrupt resource entries are : "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM. Used for SS-USB power events. - - clocks: a list of phandles to the controller clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk" - and "utmi_clk". +- clocks: a list of phandles to the controller clocks. Use as per + Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. Required clocks are "iface_clk", "core_clk", "sleep_clk" and + "utmi_clk". Optional clocks are "xo", "bus_aggr_clk", "noc_aggr_clk", + "cfg_ahb_clk", "noc_aggr_north_clk", "noc_aggr_south_clk" and "noc_sys_clk". - resets: reset specifier pair consists of phandle for the reset provider and reset lines used by this controller. - reset-names: reset signal name strings sorted in the same order as the resets @@ -39,11 +40,6 @@ Optional properties : going through PDC. (use qcom,use-pdc-interrupts property) "dm_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM going through PDC. (use qcom,use-pdc-interrupts property) - - - clocks: a list of phandles to the controller clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. Optional clocks are "bus_aggr_clk", "noc_aggr_clk" and "cfg_ahb_clk". - qcom,charging-disabled: If present then battery charging using USB is disabled. - vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode. From 4d6b01e529e78869ad96408657733b0ee7fb4f92 Mon Sep 17 00:00:00 2001 From: Huixian Ma Date: Mon, 10 May 2021 20:14:20 +0800 Subject: [PATCH 1364/1809] ARM: dts: msm: Add coresight device tree for monaco Add coresight device tree for monaco. Change-Id: I9ea1ba909ac41f7cfbf9272900fc6bfbbcfc873e --- qcom/monaco-coresight.dtsi | 1823 ++++++++++++++++++++++++++++++++++++ 1 file changed, 1823 insertions(+) create mode 100644 qcom/monaco-coresight.dtsi diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi new file mode 100644 index 000000000000..7ec86eb6761d --- /dev/null +++ b/qcom/monaco-coresight.dtsi @@ -0,0 +1,1823 @@ +&soc { + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + apss_tgu: tgu@9900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x09900000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <8>; + tgu-timer-counters = <3>; + interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>; + coresight-name = "coresight-tgu-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + csr: csr@8001000 { + compatible = "qcom,coresight-csr"; + reg = <0x8001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@8a03000 { + compatible = "qcom,coresight-csr"; + reg = <0x8a03000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + + qcom,timestamp-support; + qcom,aodbg-csr-support; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + stm: stm@8002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + + reg = <0x8002000 0x1000>, + <0xe280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + }; + + tpdm_center: tpdm@8b58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8b58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_dl_ct_out_tpda0: endpoint { + remote-endpoint = + <&tpda0_in_tpdm_dl_ct>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@8940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_gpu_out_funnel_gpu: endpoint { + remote-endpoint = + <&funnel_gpu_in_tpdm_gpu>; + }; + }; + }; + }; + + modem_rfxe: modem_rfxe { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-modem-rfxe"; + qcom,dummy-source; + out-ports { + port { + modem_rxfe_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_rxfe>; + }; + }; + }; + }; + + audio_etm0: audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + + qcom,inst-id = <5>; + out-ports { + port { + audio_etm0_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_audio_etm0>; + }; + }; + }; + }; + + snoc: snoc { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-snoc"; + + qcom,dummy-source; + + out-ports { + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@8a26000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass"; + qcom,dummy-source; + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_ddr0: tpdm@8a50000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a50000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + out-ports { + port { + tpdm_ddr0_out_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_in_tpdm_ddr0>; + }; + }; + }; + }; + + tpdm_ddr1: tpdm@8a51000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a51000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-shrm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + out-ports { + port { + tpdm_ddr1_out_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_in_tpdm_ddr1>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@8840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_vsense_out_tpda15: endpoint { + remote-endpoint = + <&tpda15_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@8870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_dcc_out_tpda12: endpoint { + remote-endpoint = + <&tpda12_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_prng: tpdm@884c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x884c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_prng_out_tpda14: endpoint { + remote-endpoint = + <&tpda14_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@89d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x89d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_qm_out_tpda16: endpoint { + remote-endpoint = + <&tpda16_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_west_out_tpda17: endpoint { + remote-endpoint = + <&tpda17_in_tpdm_west>; + }; + }; + }; + }; + + tpdm_pimem: tpdm@8850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_pimem_out_tpda21: endpoint { + remote-endpoint = + <&tpda21_in_tpdm_pimem>; + }; + }; + }; + }; + + tpdm_mapss: tpdm@8a01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_mapss_out_tpda_mapss: endpoint { + remote-endpoint = + <&tpda_mapss_in_tpdm_mapss>; + }; + }; + }; + }; + + tpdm_sdcc_2: tpdm@89b9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x89b9000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-sdcc-2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_sdcc2_out_tpda20: endpoint { + remote-endpoint = + <&tpda20_in_tpdm_sdcc2>; + }; + }; + }; + }; + + tpdm_sdcc_1: tpdm@89b8000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x89b8000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-sdcc-1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_sdcc1_out_tpda19: endpoint { + remote-endpoint = + <&tpda19_in_tpdm_sdcc1>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@800f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x800f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda18: endpoint { + remote-endpoint = + <&tpda18_in_tpdm_spdm>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@899c000 { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + out-ports { + port { + tpdm_wcss_out_funnel_wcss: endpoint { + remote-endpoint = + <&funnel_wcss_in_tpdm_wcss>; + }; + }; + }; + }; + + funnel_wcss: funnel@899e000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-wcss"; + + out-ports { + port { + funnel_wcss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_wcss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + funnel_wcss_in_tpdm_wcss: endpoint { + remote-endpoint = + <&tpdm_wcss_out_funnel_wcss>; + }; + }; + }; + }; + + modem_etm0: modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + + qcom,inst-id = <2>; + + out-ports { + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + }; + + etm0: etm@9040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9040000 0x1000>; + cpu = <&CPU0>; + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + etm0_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm0>; + }; + }; + }; + }; + + etm1: etm@9140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9140000 0x1000>; + cpu = <&CPU1>; + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + etm1_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm1>; + }; + }; + }; + }; + + etm2: etm@9240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9240000 0x1000>; + cpu = <&CPU2>; + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + etm2_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm2>; + }; + }; + }; + }; + + etm3: etm@9340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9340000 0x1000>; + cpu = <&CPU3>; + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + etm3_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm3>; + }; + }; + }; + }; + + tpdm_actpm: tpd@9830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_actpm_out_tpda_actpm: endpoint { + remote-endpoint = + <&tpda_actpm_in_tpdm_actpm>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@98a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x98a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_apss: tpdm@9860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + out-ports { + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + }; + + funnel_apss0: funnel@9800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x9800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_apss0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss0_in_etm0: endpoint { + remote-endpoint = + <&etm0_out_funnel_apss0>; + }; + }; + + port@1 { + reg = <1>; + funnel_apss0_in_etm1: endpoint { + remote-endpoint = + <&etm1_out_funnel_apss0>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss0_in_etm2: endpoint { + remote-endpoint = + <&etm2_out_funnel_apss0>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss0_in_etm3: endpoint { + remote-endpoint = + <&etm3_out_funnel_apss0>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss0_in_tpda_actpm: endpoint { + remote-endpoint = + <&tpda_actpm_out_funnel_apss0>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss0_in_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss0>; + }; + }; + + port@6 { + reg = <6>; + funnel_apss0_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss0>; + }; + }; + }; + }; + + tpda_actpm: tpda@9832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-actpm"; + + qcom,tpda-atid = <77>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_actpm_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_actpm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_actpm_in_tpdm_actpm: endpoint { + remote-endpoint = + <&tpdm_actpm_out_tpda_actpm>; + }; + }; + }; + }; + + tpda_apss: tpda@9862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_apss_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_apss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + + tpda_llm_silver: tpda@98c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x98c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_llm_silver_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_llm_silver>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpda_mapss: tpda@8a04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8a04000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mapss"; + + qcom,tpda-atid = <76>; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_mapss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mapss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_mapss_in_tpdm_mapss: endpoint { + remote-endpoint = + <&tpdm_mapss_out_tpda_mapss>; + }; + }; + + }; + }; + + + funnel_gpu: funnel@8944000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8944000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu"; + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_gpu_out_tpda1: endpoint { + remote-endpoint = + <&tpda1_in_funnel_gpu>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_gpu_in_tpdm_gpu: endpoint { + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu>; + }; + }; + + }; + }; + + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <0 32>, + <1 32>, + <16 32>, + <17 32>; + + qcom,cmb-elem-size = <6 32>, + <7 32>, + <12 32>, + <14 32>, + <15 32>, + <18 32>, + <19 32>, + <20 32>, + <21 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda0_in_tpdm_dl_ct: endpoint { + remote-endpoint = + <&tpdm_dl_ct_out_tpda0>; + }; + }; + + port@1 { + reg = <1>; + tpda1_in_funnel_gpu: endpoint { + remote-endpoint = + <&funnel_gpu_out_tpda1>; + }; + }; + + port@6 { + reg = <6>; + tpda6_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda6>; + }; + }; + + port@7 { + reg = <7>; + tpda7_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda7>; + }; + }; + + port@12 { + reg = <12>; + tpda12_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda12>; + }; + }; + + port@14 { + reg = <14>; + tpda14_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda14>; + }; + }; + + port@15 { + reg = <15>; + tpda15_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda15>; + }; + }; + + port@16 { + reg = <16>; + tpda16_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda16>; + }; + }; + + port@17 { + reg = <17>; + tpda17_in_tpdm_west: endpoint { + remote-endpoint = + <&tpdm_west_out_tpda17>; + }; + }; + + port@18 { + reg = <18>; + tpda18_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda18>; + }; + }; + + port@19 { + reg = <19>; + tpda19_in_tpdm_sdcc1: endpoint { + remote-endpoint = + <&tpdm_sdcc1_out_tpda19>; + }; + }; + + port@20 { + reg = <20>; + tpda20_in_tpdm_sdcc2: endpoint { + remote-endpoint = + <&tpdm_sdcc2_out_tpda20>; + }; + }; + + port@21 { + reg = <21>; + tpda21_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda21>; + }; + }; + }; + }; + + funnel_qatb: funnel@8005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@5 { + reg = <5>; + funnel_qatb_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_funnel_qatb>; + }; + }; + }; + }; + + funnel_in0: funnel@8041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + }; + + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel_in0_in_snoc: endpoint { + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@8042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_in1_in_tpda_mapss: endpoint { + remote-endpoint = + <&tpda_mapss_out_funnel_in1>; + }; + }; + + port@2 { + reg = <2>; + funnel_in1_in_modem_rxfe: endpoint { + remote-endpoint = + <&modem_rxfe_out_funnel_in1>; + }; + }; + + port@3 { + reg = <3>; + funnel_in1_in_funnel_wcss: endpoint { + remote-endpoint = + <&funnel_wcss_out_funnel_in1>; + }; + }; + + port@4 { + reg = <4>; + funnel_in1_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + + port@6 { + reg = <6>; + funnel_in1_in_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_out_funnel_in1>; + }; + }; + + }; + }; + + funnel_lpass: funnel@8a24000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass"; + + out-ports { + port { + funnel_lpass_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_lpass>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + }; + }; + + funnel_ddr: funnel@8a57000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x08a57000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + out-ports { + port@0 { + reg = <0>; + funnel_ddr_out_tpda6: endpoint { + remote-endpoint = + <&tpda6_in_funnel_ddr>; + source = <&tpdm_ddr0>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_out_tpda7: endpoint { + remote-endpoint = + <&tpda7_in_funnel_ddr>; + source = <&tpdm_ddr1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@ { + reg = <0>; + funnel_ddr_in_tpdm_ddr0: endpoint { + remote-endpoint = + <&tpdm_ddr0_out_funnel_ddr>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_in_tpdm_ddr1: endpoint { + remote-endpoint = + <&tpdm_ddr1_out_funnel_ddr>; + }; + }; + + }; + }; + + funnel_merg: funnel@8045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@1 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + }; + }; + + tmc_etf: tmc@8047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + coresight-ctis = <&cti0 &cti6>; + cti-flush-trig-num = <1>; + cti-reset-trig-num = <5>; + + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tmc_etf_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_tmc_etf>; + }; + }; + }; + + in-ports { + port { + tmc_etf_in_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + }; + + replicator_qdss: replicator@8046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x8046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_qdss>; + }; + }; + }; + + out-ports { + port { + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_qdss>; + }; + }; + }; + }; + + tmc_etr: tmc@8048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8048000 0x1000>, + <0x8064000 0x15000>; + reg-names = "tmc-base","bam-base"; + + coresight-name = "coresight-tmc-etr"; + + iommus = <&apps_smmu 0x0180 0>, + <&apps_smmu 0x0160 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + arm,scatter-gather; + + coresight-ctis = <&cti0 &cti6>; + cti-flush-trig-num = <3>; + cti-reset-trig-num = <5>; + + coresight-csr = <&csr>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + in-ports { + port { + tmc_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + }; + }; + + cti_cortex_m3: cti@8b30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b30000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti0: cti@98e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti1: cti@98f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti0: cti@89a4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti0"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti1: cti@89a5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti1"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti2: cti@89a6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a6000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti2"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_lpi: cti@8a21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a21000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass-lpi"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_q6: cti@8a2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a2b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass-q6"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@8833000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8833000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_isdb_gpu: cti@8941000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8941000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-isdb-gpu"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mapss: cti@8a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti0: cti@8b59000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b59000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti1: cti@8b5a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti2: cti@8b5b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti3: cti@8b5c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@8010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1: cti@8011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2: cti@8012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + //qcom,cti-gpio-trigout = <0>; + //pinctrl-names = "cti-trigout-pctrl"; + //pinctrl-0 = <&trigout_a>; + + }; + + cti3: cti@8013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti4: cti@8014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti5: cti@8015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti6: cti@8016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti7: cti@8017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti8: cti@8018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti9: cti@8019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti10: cti@801a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti11: cti@801b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti12: cti@801c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti13: cti@801d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti14: cti@801e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti15: cti@801f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; + From 1391c5485dba68472869f1589ff24a90048bd4a1 Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Sat, 17 Apr 2021 15:53:53 +0530 Subject: [PATCH 1365/1809] ARM: dts: qcom: Upadate base dts file for Monaco Add gpr node and include audio dtsi file in monaco base dtsi. Change-Id: I61197787c53151c8423c6f1a5e8f25ca13a5ff07 --- qcom/monaco-amic-audio-overlay.dtsi | 6 +++++- qcom/monaco-audio-overlay.dtsi | 6 +++++- qcom/monaco-wsa-audio-overlay.dtsi | 4 +++- qcom/monaco.dtsi | 31 +++++++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi index f896df8e4a15..6b588baa925f 100644 --- a/qcom/monaco-amic-audio-overlay.dtsi +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -70,6 +70,7 @@ besbev_codec: besbev-codec { compatible = "qcom,besbev-codec"; qcom,split-codec = <1>; + qcom,pmic-spmi-node = <&pm5100_cdc>; qcom,wcd-reset-reg = <0x0000FCDB>; qcom,foundry-id-reg = <0x000001F2>; qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, @@ -77,6 +78,7 @@ qcom,besbev-slave = <&besbev_rx_slave>; qcom,speaker-present = <1>; + qcom,comp-support = <0>; cdc-mic-bias-supply = <&L28A>; qcom,cdc-mic-bias-voltage = <2904000 2904000>; @@ -135,11 +137,13 @@ "VA DMIC2", "VA MIC BIAS1", "VA DMIC3", "VA MIC BIAS1"; + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; asoc-codec = <&stub_codec>, <&bolero>, <&besbev_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "besbev_codec"; - qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; }; &soc { diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi index b50c44230947..90f4d63a9b6e 100644 --- a/qcom/monaco-audio-overlay.dtsi +++ b/qcom/monaco-audio-overlay.dtsi @@ -114,6 +114,7 @@ besbev_codec: besbev-codec { compatible = "qcom,besbev-codec"; qcom,split-codec = <1>; + qcom,pmic-spmi-node = <&pm5100_cdc>; qcom,wcd-reset-reg = <0x0000FCDB>; qcom,foundry-id-reg = <0x000001F2>; qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, @@ -121,6 +122,7 @@ qcom,besbev-slave = <&besbev_rx_slave>; qcom,speaker-present = <1>; + qcom,comp-support = <0>; cdc-mic-bias-supply = <&L28A>; qcom,cdc-mic-bias-voltage = <2904000 2904000>; @@ -172,11 +174,13 @@ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; asoc-codec = <&stub_codec>, <&bolero>, <&besbev_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "besbev_codec"; - qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; }; &soc { diff --git a/qcom/monaco-wsa-audio-overlay.dtsi b/qcom/monaco-wsa-audio-overlay.dtsi index 2d91a04619ab..e19857c5bdfe 100644 --- a/qcom/monaco-wsa-audio-overlay.dtsi +++ b/qcom/monaco-wsa-audio-overlay.dtsi @@ -156,13 +156,15 @@ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; asoc-codec = <&stub_codec>, <&bolero>, <&wsa883x_0221>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wsa-codec1"; qcom,wsa-max-devs = <1>; qcom,wsa-devs = <&wsa883x_0221>; - qcom,msm_audio_ssr_devs = <&bolero>, <&lpi_tlmm>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; }; &soc { diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 42f171d9d91f..c254e4862da7 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1,3 +1,4 @@ +#include #include #include #include @@ -22,6 +23,8 @@ serial0 = &qupv3_se6_2uart; hsuart0 = &qupv3_se5_4uart; sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + swr0 = &swr0; + swr1 = &swr1; }; firmware: firmware {}; @@ -552,6 +555,10 @@ #size-cells = <1>; read-only; ranges; + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; }; mem_dump { @@ -964,6 +971,28 @@ 0x4400 2>; }; + audio_gpr: qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,intents = <0x200 20>; + reg = ; + spf_core { + compatible = "qcom,spf_core"; + reg = ; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = ; + }; + + audio_prm: q6prm { + compatible = "qcom,audio_prm"; + reg = ; + }; + }; + qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>; @@ -1197,6 +1226,7 @@ }; }; +#include "pm5100.dtsi" #include "monaco-pinctrl.dtsi" #include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" @@ -1204,6 +1234,7 @@ #include "monaco-gdsc.dtsi" #include "monaco-qupv3.dtsi" #include "monaco-pm.dtsi" +#include "monaco-audio.dtsi" &qupv3_se6_2uart { status = "ok"; From ac54379b2bd450a7400b1da3e57510af0beac021 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Fri, 23 Oct 2020 19:02:25 +0530 Subject: [PATCH 1366/1809] ARM: dts: msm: Add the APPS SMMU device for direwolf Add the initial set of devices that describe the APPS SMMU register spaces for the direwolf. Change-Id: I373485bd26eab010614d60fddb289b757cd20358 --- qcom/direwolf.dtsi | 1 + qcom/msm-arm-smmu-direwolf.dtsi | 165 ++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 qcom/msm-arm-smmu-direwolf.dtsi diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index e7165829baef..0d5e78727299 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1493,6 +1493,7 @@ #include "direwolf-pm.dtsi" #include "direwolf-gdsc.dtsi" #include "direwolf-ion.dtsi" +#include "msm-arm-smmu-direwolf.dtsi" &gcc_emac0_gdsc { status = "ok"; diff --git a/qcom/msm-arm-smmu-direwolf.dtsi b/qcom/msm-arm-smmu-direwolf.dtsi new file mode 100644 index 000000000000..0717289dfffb --- /dev/null +++ b/qcom/msm-arm-smmu-direwolf.dtsi @@ -0,0 +1,165 @@ +#include + +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_IMEM_CFG>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x0 0>; + qcom,iommu-dma = "disabled"; + status = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x1 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + status = "disabled"; + }; +}; From 337db00d0c77d2d6c360e0a138712bdd65f40132 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Thu, 15 Apr 2021 15:17:32 +0530 Subject: [PATCH 1367/1809] ARM: dts: msm: Add regulator and PMIC support for holi-pm6125 Add device tree to support holi platform on MTP, CDP, MTP-USBC, CDP-LCD platforms with PM6125 pmic. Change-Id: Ief5917e73e041d52dd2fde2dbd6a124596f3e308 --- qcom/Makefile | 21 +- qcom/holi-cdp-lcd-pm6125-overlay.dts | 20 + qcom/holi-cdp-lcd-pm6125.dts | 13 + qcom/holi-cdp-lcd-pm6125.dtsi | 30 ++ qcom/holi-cdp-pm6125-overlay.dts | 20 + qcom/holi-cdp-pm6125.dts | 13 + qcom/holi-cdp-pm6125.dtsi | 310 +++++++++++ qcom/holi-mtp-pm6125-nopmi-overlay.dts | 1 + qcom/holi-mtp-pm6125-nopmi.dts | 13 + qcom/holi-mtp-pm6125-nopmi.dtsi | 2 + qcom/holi-mtp-pm6125-overlay.dts | 15 + qcom/holi-mtp-pm6125.dts | 15 + qcom/holi-mtp-pm6125.dtsi | 380 +++++++++++++ qcom/holi-mtp-usbc-pm6125-overlay.dts | 52 ++ qcom/holi-mtp-usbc-pm6125.dts | 14 + qcom/holi-mtp-usbc-pm6125.dtsi | 399 ++++++++++++++ qcom/holi-pm6125-overlay.dtsi | 5 + qcom/holi-pm7250b.dtsi | 1 + qcom/holi-pmic-overlay-pm6125.dtsi | 498 +++++++++++++++++ qcom/holi-regulators-pm6125.dtsi | 711 +++++++++++++++++++++++++ qcom/pmr735a-rpm-regulator.dtsi | 168 ++++++ 21 files changed, 2699 insertions(+), 2 deletions(-) create mode 100644 qcom/holi-cdp-lcd-pm6125-overlay.dts create mode 100644 qcom/holi-cdp-lcd-pm6125.dts create mode 100644 qcom/holi-cdp-lcd-pm6125.dtsi create mode 100644 qcom/holi-cdp-pm6125-overlay.dts create mode 100644 qcom/holi-cdp-pm6125.dts create mode 100644 qcom/holi-cdp-pm6125.dtsi create mode 100644 qcom/holi-mtp-pm6125-nopmi-overlay.dts create mode 100644 qcom/holi-mtp-pm6125-nopmi.dts create mode 100644 qcom/holi-mtp-pm6125-nopmi.dtsi create mode 100644 qcom/holi-mtp-pm6125-overlay.dts create mode 100644 qcom/holi-mtp-pm6125.dts create mode 100644 qcom/holi-mtp-pm6125.dtsi create mode 100644 qcom/holi-mtp-usbc-pm6125-overlay.dts create mode 100644 qcom/holi-mtp-usbc-pm6125.dts create mode 100644 qcom/holi-mtp-usbc-pm6125.dtsi create mode 100644 qcom/holi-pm6125-overlay.dtsi create mode 100644 qcom/holi-pm7250b.dtsi create mode 100644 qcom/holi-pmic-overlay-pm6125.dtsi create mode 100644 qcom/holi-regulators-pm6125.dtsi create mode 100644 qcom/pmr735a-rpm-regulator.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index c82309013266..9d5d6f68bb88 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -100,7 +100,12 @@ dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-cdp-lcd-overlay.dtbo \ holi-qrd-overlay.dtbo \ holi-atp-overlay.dtbo \ - holi-mtp-usbc-overlay.dtbo + holi-mtp-usbc-overlay.dtbo \ + holi-mtp-pm6125-overlay.dtbo \ + holi-cdp-pm6125-overlay.dtbo \ + holi-cdp-lcd-pm6125-overlay.dtbo \ + holi-mtp-usbc-pm6125-overlay.dtbo \ + holi-mtp-pm6125-nopmi-overlay.dtbo holi-rumi-overlay.dtbo-base := holi.dtb holi-mtp-overlay.dtbo-base := holi.dtb @@ -109,6 +114,12 @@ holi-cdp-lcd-overlay.dtbo-base := holi.dtb holi-qrd-overlay.dtbo-base := holi.dtb holi-atp-overlay.dtbo-base := holi.dtb holi-mtp-usbc-overlay.dtbo-base := holi.dtb +holi-mtp-pm6125-overlay.dtbo-base := holi.dtb +holi-cdp-pm6125-overlay.dtbo-base := holi.dtb +holi-cdp-lcd-pm6125-overlay.dtbo-base := holi.dtb +holi-mtp-usbc-pm6125-overlay.dtbo-base := holi.dtb +holi-mtp-pm6125-nopmi-overlay.dtbo-base := holi.dtb + else dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-mtp.dtb \ @@ -116,7 +127,13 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-cdp-lcd.dtb \ holi-qrd.dtb \ holi-atp.dtb \ - holi-mtp-usbc.dtb + holi-mtp-usbc.dtb\ + holi-mtp-pm6125.dtb \ + holi-cdp-pm6125.dtb \ + holi-cdp-lcd-pm6125.dtb \ + holi-mtp-usbc-pm6125.dtb \ + holi-mtp-pm6125-nopmi.dtb + endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/holi-cdp-lcd-pm6125-overlay.dts b/qcom/holi-cdp-lcd-pm6125-overlay.dts new file mode 100644 index 000000000000..7aa7634f1373 --- /dev/null +++ b/qcom/holi-cdp-lcd-pm6125-overlay.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-cdp-lcd-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi CDP-LCD PM6125 attached"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <1 1>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; diff --git a/qcom/holi-cdp-lcd-pm6125.dts b/qcom/holi-cdp-lcd-pm6125.dts new file mode 100644 index 000000000000..f0b5b44968b5 --- /dev/null +++ b/qcom/holi-cdp-lcd-pm6125.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-cdp-lcd-pm6125.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Holi CDP-LCD PM6125 attach"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-cdp-lcd-pm6125.dtsi b/qcom/holi-cdp-lcd-pm6125.dtsi new file mode 100644 index 000000000000..c486e4d2d4a8 --- /dev/null +++ b/qcom/holi-cdp-lcd-pm6125.dtsi @@ -0,0 +1,30 @@ +#include "holi-cdp-pm6125.dtsi" + +&qupv3_se8_i2c { + qcom,i2c-touch-active="synaptics,dsx-i2c"; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,reset-gpio = <&tlmm 21 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + }; +}; diff --git a/qcom/holi-cdp-pm6125-overlay.dts b/qcom/holi-cdp-pm6125-overlay.dts new file mode 100644 index 000000000000..ede94a7b8fb1 --- /dev/null +++ b/qcom/holi-cdp-pm6125-overlay.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-cdp-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi CDP PM6125"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <1 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; diff --git a/qcom/holi-cdp-pm6125.dts b/qcom/holi-cdp-pm6125.dts new file mode 100644 index 000000000000..00f582deee36 --- /dev/null +++ b/qcom/holi-cdp-pm6125.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-cdp-pm6125.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Holi CDP PM6125"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi new file mode 100644 index 000000000000..c9395ba292bf --- /dev/null +++ b/qcom/holi-cdp-pm6125.dtsi @@ -0,0 +1,310 @@ +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include + +/* Dummy LDO reference */ +&wcd938x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&wcd937x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L6A>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + }; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/holi-mtp-pm6125-nopmi-overlay.dts b/qcom/holi-mtp-pm6125-nopmi-overlay.dts new file mode 100644 index 000000000000..71fe2b7f1a8a --- /dev/null +++ b/qcom/holi-mtp-pm6125-nopmi-overlay.dts @@ -0,0 +1 @@ +/dts-v1/; diff --git a/qcom/holi-mtp-pm6125-nopmi.dts b/qcom/holi-mtp-pm6125-nopmi.dts new file mode 100644 index 000000000000..ceaba4bf503e --- /dev/null +++ b/qcom/holi-mtp-pm6125-nopmi.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-mtp-pm6125-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP PM6125 NOPMI"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x00 0x0>; +}; + diff --git a/qcom/holi-mtp-pm6125-nopmi.dtsi b/qcom/holi-mtp-pm6125-nopmi.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/holi-mtp-pm6125-nopmi.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/qcom/holi-mtp-pm6125-overlay.dts b/qcom/holi-mtp-pm6125-overlay.dts new file mode 100644 index 000000000000..4bd5809d06ac --- /dev/null +++ b/qcom/holi-mtp-pm6125-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP PM6125"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-mtp-pm6125.dts b/qcom/holi-mtp-pm6125.dts new file mode 100644 index 000000000000..80145038a5ec --- /dev/null +++ b/qcom/holi-mtp-pm6125.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP PM6125"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi new file mode 100644 index 000000000000..d4f26c106212 --- /dev/null +++ b/qcom/holi-mtp-pm6125.dtsi @@ -0,0 +1,380 @@ +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include + +/* Dummy LDO reference */ +&wcd938x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&wcd937x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, + <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1398.dtsi" +}; + +&smb1396 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1396"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1396_div2_cp_master { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/holi-mtp-usbc-pm6125-overlay.dts b/qcom/holi-mtp-usbc-pm6125-overlay.dts new file mode 100644 index 000000000000..2754d2c8ffe6 --- /dev/null +++ b/qcom/holi-mtp-usbc-pm6125-overlay.dts @@ -0,0 +1,52 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-usbc-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP USBC PM6125 audio"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <8 1>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&swr0 { + qcom,is_wcd937x = <0>; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd938x_tx_slave { + status = "ok"; +}; + +&wcd938x_rx_slave { + status = "ok"; +}; + +&wcd938x_codec { + status = "ok"; +}; + +&holi_snd { + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&wsa881x_i2c_e>, + <&wsa881x_i2c_f>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "wsa-codec0", + "wsa-codec1"; +}; diff --git a/qcom/holi-mtp-usbc-pm6125.dts b/qcom/holi-mtp-usbc-pm6125.dts new file mode 100644 index 000000000000..724b2f976df9 --- /dev/null +++ b/qcom/holi-mtp-usbc-pm6125.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-usbc-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP USBC PM6125 audio"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi new file mode 100644 index 000000000000..f689c43b7f8d --- /dev/null +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -0,0 +1,399 @@ +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include + +/* Dummy LDO reference */ +&wcd938x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&wcd937x_codec { + cdc-vdd-mic-bias-supply = <&L2A>; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&holi_snd { + qcom,model = "holi-usbc-snd-card"; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + fsa4480-i2c-handle = <&fsa4480>; +}; + +&qupv3_se10_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + io-channels = <&pm7250b_charger PSY_IIO_TYPEC_ACCESSORY_MODE>; + io-channel-names = "typec_mode"; + qcom,use-power-supply = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, + <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1398.dtsi" +}; + +&smb1396 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1396"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1396_div2_cp_master { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi new file mode 100644 index 000000000000..74c9102a0c75 --- /dev/null +++ b/qcom/holi-pm6125-overlay.dtsi @@ -0,0 +1,5 @@ +/* Dummy LDO referenses */ + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&S6A>; +}; diff --git a/qcom/holi-pm7250b.dtsi b/qcom/holi-pm7250b.dtsi new file mode 100644 index 000000000000..71fe2b7f1a8a --- /dev/null +++ b/qcom/holi-pm7250b.dtsi @@ -0,0 +1 @@ +/dts-v1/; diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi new file mode 100644 index 000000000000..fb8061b053e3 --- /dev/null +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -0,0 +1,498 @@ +#include +#include +#include + +#include "pm7250b.dtsi" +#include "pm6125.dtsi" +#include "pmr735a.dtsi" + +#define PMK8350_SID 6 + +#include "pmk8350.dtsi" + +&pmr735a_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + /* Channel nodes */ + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6125_vadc { + pinctrl-names = "default"; + pinctrl-0 = < + &pa_therm2_default + &msm_therm_default + &rfc_cam_therm_default + &rear_cam_flash_therm_default>; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rfc_cam_therm { + reg = ; + label = "rfc_cam_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rear_cam_flash_therm { + reg = ; + label = "rear_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + pa_therm2 { + pa_therm2_default: pa_therm2_default { + pins = "gpio7"; + bias-high-impedance; + }; + }; + + msm_therm { + msm_therm_default: msm_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + rfc_cam_therm { + rfc_cam_therm_default: rfc_cam_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; + + rear_cam_flash_therm { + rear_cam_flash_therm_default: rear_cam_flash_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC5_GPIO4_100K_PU>, + <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm6125_vadc ADC5_GPIO3_100K_PU>, + <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>; + + /* Channel nodes */ + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rear_cam_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&spmi_bus { + qcom,pm6125@4 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>, + <&pm6125_vadc ADC5_GPIO2_100K_PU>; + + msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rfc_cam_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pmk8350 { + reg = <6 SPMI_USID>; + + pon_pbs@800 { + status = "disabled"; + }; + + pon_hlos@1300 { + status = "disabled"; + }; +}; + +&pmk8350_rtc { + interrupts = <0x6 0x62 0x1 IRQ_TYPE_EDGE_RISING>; +}; + +&pmk8350_vadc { + interrupts = <0x6 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; +}; + +&pmk8350_adc_tm { + interrupts = <0x6 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rfc-cam-pa3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_GPIO3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + }; + + pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + pm8008_en-supply = <&PM8008_EN>; + + vdd_l1_l2-supply = <&S6A>; + vdd_l6-supply = <&S7A>; + + L1P: qcom,pm8008-l1@4000 { + reg = <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,min-dropout-voltage = <56000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <96000>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <168000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <136000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <240000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4400 { + reg = <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1900000>; + qcom,min-dropout-voltage = <48000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4400 { + reg = <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <96000>; + qcom,hpm-min-load = <10000>; + }; + }; + }; +}; diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi new file mode 100644 index 000000000000..5f3956474160 --- /dev/null +++ b/qcom/holi-regulators-pm6125.dtsi @@ -0,0 +1,711 @@ +#include + +&rpm_bus { + /* Delete all pm6350 and pm6150l nodes */ + /delete-node/ rpm-regulator-smpa1; + /delete-node/ rpm-regulator-smpa2; + /delete-node/ rpm-regulator-smpa3; + /delete-node/ rpm-regulator-smpa5; + /delete-node/ rpm-regulator-ldoa1; + /delete-node/ rpm-regulator-ldoa2; + /delete-node/ rpm-regulator-ldoa3; + /delete-node/ rpm-regulator-ldoa4; + /delete-node/ rpm-regulator-ldoa5; + /delete-node/ rpm-regulator-ldoa6; + /delete-node/ rpm-regulator-ldoa7; + /delete-node/ rpm-regulator-ldoa8; + /delete-node/ rpm-regulator-ldoa9; + /delete-node/ rpm-regulator-ldoa10; + /delete-node/ rpm-regulator-ldoa11; + /delete-node/ rpm-regulator-ldoa12; + /delete-node/ rpm-regulator-ldoa13; + /delete-node/ rpm-regulator-ldoa14; + /delete-node/ rpm-regulator-ldoa15; + /delete-node/ rpm-regulator-ldoa16; + /delete-node/ rpm-regulator-ldoa17; + /delete-node/ rpm-regulator-ldoa18; + /delete-node/ rpm-regulator-ldoa19; + /delete-node/ rpm-regulator-ldoa20; + /delete-node/ rpm-regulator-ldoa21; + /delete-node/ rpm-regulator-ldoa22; + /delete-node/ rpm-regulator-bobe; + + /delete-node/ rpm-regulator-smpe1; + /delete-node/ rpm-regulator-smpe8; + /delete-node/ rpm-regulator-ldoe1; + /delete-node/ rpm-regulator-ldoe2; + /delete-node/ rpm-regulator-ldoe3; + /delete-node/ rpm-regulator-ldoe4; + /delete-node/ rpm-regulator-ldoe5; + /delete-node/ rpm-regulator-ldoe7; + + /* Disable PM6350 and PM6150L rpm-regulators */ + rpm-regulator-smpa1 { + status = "disabled"; + }; + + rpm-regulator-smpa2 { + status = "disabled"; + }; + + rpm-regulator-smpa3 { + status = "disabled"; + }; + + rpm-regulator-smpa5 { + status = "disabled"; + }; + + rpm-regulator-ldoa1 { + status = "disabled"; + }; + + rpm-regulator-ldoa2 { + status = "disabled"; + }; + + rpm-regulator-ldoa3 { + status = "disabled"; + }; + + rpm-regulator-ldoa4 { + status = "disabled"; + }; + + rpm-regulator-ldoa5 { + status = "disabled"; + }; + + rpm-regulator-ldoa6 { + status = "disabled"; + }; + + rpm-regulator-ldoa7 { + status = "disabled"; + }; + + rpm-regulator-ldoa8 { + status = "disabled"; + }; + + rpm-regulator-ldoa9 { + status = "disabled"; + }; + + rpm-regulator-ldoa10 { + status = "disabled"; + }; + + rpm-regulator-ldoa11 { + status = "disabled"; + }; + + rpm-regulator-ldoa12 { + status = "disabled"; + }; + + rpm-regulator-ldoa13 { + status = "disabled"; + }; + + rpm-regulator-ldoa14 { + status = "disabled"; + }; + + rpm-regulator-ldoa15 { + status = "disabled"; + }; + + rpm-regulator-ldoa16 { + status = "disabled"; + }; + + rpm-regulator-ldoa17 { + status = "disabled"; + }; + + rpm-regulator-ldoa18 { + status = "disabled"; + }; + + rpm-regulator-ldoa19 { + status = "disabled"; + }; + + rpm-regulator-ldoa20 { + status = "disabled"; + }; + + rpm-regulator-ldoa21 { + status = "disabled"; + }; + + rpm-regulator-ldoa22 { + status = "disabled"; + }; + + rpm-regulator-bobe { + status = "disabled"; + }; + + rpm-regulator-smpe1 { + status = "disabled"; + }; + + rpm-regulator-smpe8 { + status = "disabled"; + }; + + rpm-regulator-ldoe1 { + status = "disabled"; + }; + + rpm-regulator-ldoe2 { + status = "disabled"; + }; + + rpm-regulator-ldoe3 { + status = "disabled"; + }; + + rpm-regulator-ldoe4 { + status = "disabled"; + }; + + rpm-regulator-ldoe5 { + status = "disabled"; + }; + + rpm-regulator-ldoe6 { + status = "disabled"; + }; + + rpm-regulator-ldoe7 { + status = "disabled"; + }; + + rpm-regulator-ldoe8 { + status = "disabled"; + }; + + rpm-regulator-ldoe9 { + status = "disabled"; + }; + + rpm-regulator-ldoe10 { + status = "disabled"; + }; + + rpm-regulator-ldoe11 { + status = "disabled"; + }; +}; + +#include "pm6125-rpm-regulator.dtsi" +#include "pmr735a-rpm-regulator.dtsi" + +&rpm_bus { + rpm-regulator-smpa6 { + status = "okay"; + S6A: pm6125_s6: regulator-s6 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1374000>; + qcom,init-voltage = <1352000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa7 { + status = "okay"; + S7A: pm6125_s7: regulator-s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <2040000>; + status = "okay"; + }; + }; + + /* PM6125 S8 - VDD_GFX supply */ + rpm-regulator-smpa8 { + status = "okay"; + qcom,resource-name = "rwgx"; + qcom,resource-id = <0>; + qcom,always-wait-for-ack; + VDD_GFX_LEVEL: + S8A_LEVEL: pm6125_s8_level: regulator-s8-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s8_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,use-voltage-level; + }; + + VDD_GFX_LEVEL_AO: + S8A_LEVEL_AO: pm6125_s8_level_ao: regulator-s8-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s8_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + /* Dummy node */ + gfx_cdev: gfx-cdev { + }; + + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa1 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + VDD_LPI_CX_LEVEL: + L1A_LEVEL: pm6125_l1_level: regulator-l1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm6125_l2: regulator-l2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + L3A: pm6125_l3: regulator-l3 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1170000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm6125_l4: regulator-l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1232000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm6125_l5: regulator-l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm6125_l6: regulator-l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + L7A: pm6125_l7: regulator-l7 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + L8A: pm6125_l8: regulator-l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + L9A: pm6125_l9: regulator-l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm6125_l10: regulator-l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm6125_l11: regulator-l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm6125_l12: regulator-l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm6125_l13: regulator-l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm6125_l14: regulator-l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm6125_l15: regulator-l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm6125_l16: regulator-l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa17 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + VDD_LPI_MX_LEVEL: + L17A_LEVEL: pm6125_l17_level: regulator-l17-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l17_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm6125_l18: regulator-l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm6125_l19: regulator-l19 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm6125_l20: regulator-l20 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm6125_l21: regulator-l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm6125_l22: regulator-l22 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + L23A: pm6125_l23: regulator-l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + L24A: pm6125_l24: regulator-l24 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2960000>; + status = "okay"; + }; + }; + + /* PMR735A S1E - VDD_MX supply */ + rpm-regulator-smpe1 { + status = "okay"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + proxy-supply = <&VDD_MX_LEVEL>; + VDD_MX_LEVEL: + S1E_LEVEL: pmr735a_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + S1E_FLOOR_LEVEL: + pmr735a_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + S1E_LEVEL_AO: pmr735a_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + /* Dummy node */ + mx_cdev: mx-cdev-lvl { + }; + }; + + + /* PMR735A S2E - VDD_CX supply */ + rpm-regulator-smpe2 { + status = "okay"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S2E_LEVEL: pmr735a_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + S2E_FLOOR_LEVEL: + pmr735a_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + S2E_LEVEL_AO: pmr735a_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + /* Dummy node */ + cx_cdev: cx-cdev-lvl { + }; + }; + + rpm-regulator-ldoe1 { + status = "okay"; + L1E: pmr735a_l1: regulator-l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe2 { + status = "okay"; + L2E: pmr735a_l2: regulator-l2 { + regulator-min-microvolt = <360000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe3 { + status = "okay"; + L3E: pmr735a_l3: regulator-l3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1128000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe4 { + status = "okay"; + L4E: pmr735a_l4: regulator-l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe5 { + status = "okay"; + L5E: pmr735a_l5: regulator-l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <751000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe6 { + status = "okay"; + L6E: pmr735a_l6: regulator-l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + qcom,init-voltage = <504000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoe7 { + status = "okay"; + L7E: pmr735a_l7: regulator-l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3080000>; + status = "okay"; + }; + }; +}; + +&soc { + refgen: refgen-regulator@162F000 { + compatible = "qcom,refgen-kona-regulator"; + reg = <0x162F000 0x84>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; +}; diff --git a/qcom/pmr735a-rpm-regulator.dtsi b/qcom/pmr735a-rpm-regulator.dtsi new file mode 100644 index 000000000000..1cc17f949bbe --- /dev/null +++ b/qcom/pmr735a-rpm-regulator.dtsi @@ -0,0 +1,168 @@ +&rpm_bus { + rpm-regulator-smpe1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpe"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpe2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpe"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpe3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpe"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoe7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoe"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmr735a_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; From de7a20a16e4b00bb6b858e71b1663b16d7c185fb Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 7 May 2021 11:01:39 +0530 Subject: [PATCH 1368/1809] ARM: dts: msm: Add eMMC/SD card regulators for holi-pm6125 This change add support for eMMC/SD card regulators for holi-pm6125 according to the new powergrid. Change-Id: I370de2e0c824039fba232ecd521952c0835dd7a6 --- qcom/holi-cdp-pm6125.dtsi | 8 ++++---- qcom/holi-mtp-pm6125.dtsi | 8 ++++---- qcom/holi-mtp-usbc-pm6125.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index c9395ba292bf..7306779c547a 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -20,11 +20,11 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; - vdd-supply = <&L7E>; + vdd-supply = <&L24A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 570000>; - vdd-io-supply = <&L12A>; + vdd-io-supply = <&L11A>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -38,11 +38,11 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - vdd-supply = <&L9E>; + vdd-supply = <&L22A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; - vdd-io-supply = <&L6E>; + vdd-io-supply = <&L5A>; qcom,vdd-io-voltage-level = <1800000 2960000>; qcom,vdd-io-current-level = <0 22000>; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d4f26c106212..5511797dad36 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -20,11 +20,11 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; - vdd-supply = <&L7E>; + vdd-supply = <&L24A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 570000>; - vdd-io-supply = <&L12A>; + vdd-io-supply = <&L11A>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -38,11 +38,11 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - vdd-supply = <&L9E>; + vdd-supply = <&L22A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; - vdd-io-supply = <&L6E>; + vdd-io-supply = <&L5A>; qcom,vdd-io-voltage-level = <1800000 2960000>; qcom,vdd-io-current-level = <0 22000>; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index f689c43b7f8d..4290d083d7c5 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -20,11 +20,11 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; - vdd-supply = <&L7E>; + vdd-supply = <&L24A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 570000>; - vdd-io-supply = <&L12A>; + vdd-io-supply = <&L11A>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -38,11 +38,11 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - vdd-supply = <&L9E>; + vdd-supply = <&L22A>; qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; - vdd-io-supply = <&L6E>; + vdd-io-supply = <&L5A>; qcom,vdd-io-voltage-level = <1800000 2960000>; qcom,vdd-io-current-level = <0 22000>; From 5aeaa1cd1cee4dd09ec07b1412d7417638f9ce40 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 26 Apr 2021 10:56:47 +0530 Subject: [PATCH 1369/1809] dt-bindings: interconnect: add interconnect bindings for QCS405 Add interconnect device bindings. These devices can be used to describe any RPM and NoC based interconnect devices. Change-Id: I91fcad06d1989dde13bd63bbaff37e928a7d60d2 --- bindings/interconnect/qcom,qcs405.txt | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 bindings/interconnect/qcom,qcs405.txt diff --git a/bindings/interconnect/qcom,qcs405.txt b/bindings/interconnect/qcom,qcs405.txt new file mode 100644 index 000000000000..bb2a5a6d804d --- /dev/null +++ b/bindings/interconnect/qcom,qcs405.txt @@ -0,0 +1,52 @@ +QTI QCS405 Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,qcs405-bimc", + "qcom,qcs405-pcnoc", + "qcom,qcs405-snoc", +- #interconnect-cells : should contain 1 + +reg : specifies the physical base address and size of registers +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus" and "bus_a" + +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + +Examples: + +soc { + ... + system_noc: interconnect@580000 { + reg = <0x580000 0x23080>; + compatible = "qcom,qcs405-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>, + }; + + pc_noc: interconnect@500000{ + reg = <0x500000 0x15080>; + compatible = "qcom,qcs405-pcnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + bimc: interconnect@400000{ + reg = <0x400000 0x80000>; + compatible = "qcom,qcs405-bimc"; + qcom,util-factor = <153>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; +}; From 5f97e4a477777245c61533913c0f0bd107a7d21e Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 11 May 2021 10:28:41 +0530 Subject: [PATCH 1370/1809] dt-bindings: regulator: add cpr, mem-acc, spm regulator bindings Add cpr-regulator, mem-acc-regulator, spm-regulator bindings. Change-Id: If9d35d4f797d5acb2a299c3f897462a50b37f9d4 --- bindings/regulator/cpr-regulator.txt | 961 +++++++++++++++++++++++ bindings/regulator/mem-acc-regulator.txt | 288 +++++++ bindings/regulator/spm-regulator.txt | 61 ++ 3 files changed, 1310 insertions(+) create mode 100644 bindings/regulator/cpr-regulator.txt create mode 100644 bindings/regulator/mem-acc-regulator.txt create mode 100644 bindings/regulator/spm-regulator.txt diff --git a/bindings/regulator/cpr-regulator.txt b/bindings/regulator/cpr-regulator.txt new file mode 100644 index 000000000000..0f5e27a2293b --- /dev/null +++ b/bindings/regulator/cpr-regulator.txt @@ -0,0 +1,961 @@ +QTI CPR (Core Power Reduction) Regulator + +CPR regulator device is for QTI RBCPR (RapidBridge CPR) on + application processor core. It takes voltage corner level + as input and converts it to actual voltage based on the + suggestions from factory production process. When CPR is + enabled for application processer core, it will suggest + scaling the voltage up or down for best performance and + power of the core. The scaling based on factory production + process is called PVS (Process Voltage Scaling) with efuse + bits to indicate what bin (and voltage range) a chip is in. + +Required properties: +- compatible: Must be "qcom,cpr-regulator" +- reg: Register addresses for RBCPR, RBCPR clock + select, PVS and CPR eFuse address +- reg-names: Register names. Must be "rbcpr" and "efuse_addr". + "rbcpr_clk" is optional. +- regulator-name: A string used to describe the regulator +- interrupts: Interrupt line from RBCPR to interrupt controller. +- qcom,cpr-fuse-corners: Number of fuse corners present. Many other properties + are sized based upon this value. +- regulator-min-microvolt: Minimum corner value which should be 1 to + represent the lowest supported corner. +- regulator-max-microvolt: Maximum corner value which should be equal to + qcom,cpr-fuse-corners if consumers request fuse + corners or the length of qcom,cpr-corner-map if + consumers request virtual corners. +- qcom,cpr-voltage-ceiling: Array of ceiling voltages in microvolts for fuse + corners ordered from lowest voltage corner to highest + voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. +- qcom,cpr-voltage-floor: Array of floor voltages in microvolts for fuse + corners ordered from lowest voltage corner to highest + voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. +- vdd-apc-supply: Regulator to supply VDD APC power +- qcom,vdd-apc-step-up-limit: Limit of vdd-apc-supply steps for scaling up. +- qcom,vdd-apc-step-down-limit: Limit of vdd-apc-supply steps for scaling down. +- qcom,cpr-ref-clk: The reference clock in kHz. +- qcom,cpr-timer-delay: The delay in microseconds for the timer interval. +- qcom,cpr-timer-cons-up: Consecutive number of timer interval (qcom,cpr-timer-delay) + occurred before issuing UP interrupt. +- qcom,cpr-timer-cons-down: Consecutive number of timer interval (qcom,cpr-timer-delay) + occurred before issuing DOWN interrupt. +- qcom,cpr-irq-line: Internal interrupt route signal of RBCPR, one of 0, 1 or 2. +- qcom,cpr-step-quotient: Defines the number of CPR quotient (i.e. Ring Oscillator(RO) + count) per vdd-apc-supply output voltage step. A single + integer value may be specified which is to be used for all + RO's. Alternatively, 8 integer values may be specified which + define the step quotients for RO0 to RO7 in order. +- qcom,cpr-up-threshold: The threshold for CPR to issue interrupt when + error_steps is greater than it when stepping up. +- qcom,cpr-down-threshold: The threshold for CPR to issue interrupt when + error_steps is greater than it when stepping down. +- qcom,cpr-idle-clocks: Idle clock cycles RO can be in. +- qcom,cpr-gcnt-time: The time for gate count in microseconds. +- qcom,cpr-apc-volt-step: The voltage in microvolt per CPR step, such as 5000uV. +- qcom,cpr-fuse-row: Array of row number of CPR fuse and method to read that row. It should have + index and value like this: + [0] => the fuse row number + [1] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,cpr-fuse-target-quot: Array of bit positions in the primary CPR fuse row defined + by qcom,cpr-fuse-row for the target quotients of each + fuse corner. Each bit position corresponds to the LSB + of the quotient parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage + corner. This property must be of length defined by + qcom,cpr-fuse-corners. +- qcom,cpr-fuse-ro-sel: Array of bit positions in the primary CPR fuse row defined + by qcom,cpr-fuse-row for the ring oscillator selection for each + fuse corner. Each bit position corresponds to the LSB + of the RO select parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage + corner. This property must be of length defined by + qcom,cpr-fuse-corners. + +Optional properties: +- vdd-mx-supply: Regulator to supply memory power as dependency + of VDD APC. +- qcom,vdd-mx-vmax: The maximum voltage in uV for vdd-mx-supply. This + is required when vdd-mx-supply is present. +- qcom,vdd-mx-vmin-method: The method to determine the minimum voltage for + vdd-mx-supply, which can be one of following + choices compared with VDD APC: + 0 => equal to the voltage(vmin) of VDD APC + 1 => equal to PVS corner ceiling voltage + 2 => equal to slow speed corner ceiling + 3 => equal to qcom,vdd-mx-vmax + 4 => equal to VDD_APC fuse corner mapped vdd-mx voltage + 5 => equal to VDD_APC virtual corner mapped vdd-mx voltage + This is required when vdd-mx-supply is present. +- qcom,vdd-mx-corner-map: Array of integers which defines the mapping from VDD_APC + voltage corners to vdd-mx-supply voltages. + Each element is a voltage to request from vdd-mx for the + corresponding fuse corner or virtual corner. The elements + in the array are ordered from lowest voltage corner + to highest voltage corner. The length of this property + depends on the value of qcom,vdd-mx-vmin-method property. + When qcom,vdd-mx-vmin-method property has a value of 4, the length + of this property must be equal to the value defined by qcom,cpr-fuse-corners. + When qcom,vdd-mx-vmin-method property has a value of 5, the length of + this property must be equal to the number of elements in the qcom,cpr-corner-map + property. +- qcom,pvs-voltage-table: Array of N-tuples in which each tuple specifies the + initial voltage in microvolts of the PVS bin for each + fuse voltage corner. The location or 0-based index + of a tuple in the list corresponds to the PVS bin number. + Each tuple must be of length defined by qcom,cpr-fuse-corners. + A given cpr-regulator device must have either + qcom,pvs-voltage-table specified or + qcom,cpr-fuse-init-voltage (and its associated properties). +- qcom,pvs-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the redundant PVS fuse bits would be + used instead of the original bits and method to read fuse row, reading + register through SCM or directly. The 5 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => the value to indicate redundant selection + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading + When the value of the fuse bits specified by first 3 elements equals to + the value in 4th element, redundant PVS fuse bits should be selected. + Otherwise, the original PVS bits should be selected. If the 5th + element is 0, read the fuse row from register directly. Otherwise, + read it through SCM. + This property is required if qcom,pvs-voltage-table is present. +- qcom,pvs-fuse: Array of 4 elements to indicate the bits for PVS fuse and read method. + The array should have index and value like this: + [0] => the PVS fuse row number + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading + This property is required if qcom,pvs-voltage-table is present. +- qcom,pvs-fuse-redun: Array of 4 elements to indicate the bits for redundant PVS fuse. + The array should have index and value like this: + [0] => the redundant PVS fuse row number + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading + This property is required if qcom,pvs-voltage-table is present. +- qcom,cpr-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the redundant CPR fuse bits would be + used instead of the original bits and method to read fuse row, using SCM + to read or read register directly. The 5 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => the value to indicate redundant selection + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading + When the value of the fuse bits specified by first 3 elements equals to + the value in 4th element, redundant CPR fuse bits should be selected. + Otherwise, the original CPR bits should be selected. If the 5th element + is 0, read the fuse row from register directly. Otherwise, read it through + SCM. +- qcom,cpr-fuse-redun-row: Array of row number of redundant CPR fuse and method to read that + row. It should have index and value like this: + [0] => the redundant fuse row number + [1] => the value to indicate reading the fuse row directly or using SCM + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-target-quot: Array of bit positions in the redundant CPR fuse row defined + by qcom,cpr-fuse-redun-row for the target quotients of each + fuse corner. Each bit position corresponds to the LSB + of the quotient parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage corner. + This property must be of length defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-ro-sel: Array of bit positions in the redundant CPR fuse row defined + by qcom,cpr-fuse-redun-row for the ring oscillator select of each + fuse corner. Each bit position corresponds to the LSB of the RO + select parameter. The elements in the array are ordered from + lowest voltage corner to highest voltage corner. + This property must be of length defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-bp-cpr-disable: Redundant bit position of the bit to indicate if CPR should be disable +- qcom,cpr-fuse-redun-bp-scheme: Redundant bit position of the bit to indicate if it's a global/local scheme + This property is required if cpr-fuse-redun-bp-cpr-disable + is present, and vise versa. +- qcom,cpr-fuse-bp-cpr-disable: Bit position of the bit to indicate if CPR should be disabled +- qcom,cpr-fuse-bp-scheme: Bit position of the bit to indicate if it's a global/local scheme +- qcom,cpr-fuse-revision: Array of 4 integer elements which define the location of the bits for + the CPR fusing revision fuse parameter. The 4 elements are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => the number of bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The fusing revision value is used to determine which specific adjustments + are required on some chips. +- qcom,cpr-fuse-target-quot-size: Array of target quotient parameter bit sizes in the primary + or redundant CPR fuse row for each fuse corner. The elements in the + array are ordered from lowest voltage corner to highest voltage corner. + If this property is not present, then all target quotient fuse values + are assumed to be the default length of 12 bits. +- qcom,cpr-fuse-target-quot-scale: Array of doubles which defines the scaling coefficients to decode + the target quotients of each fuse corner. The first element in each + double represents the offset to add to the scaled quotient. The second + element represents the multiplier to scale the quotient by. For example, + given a tuple , quot_decoded = A + (B * quot_raw). + The doubles in the array are ordered from lowest voltage corner to highest + voltage corner. This property must contain a number of doubles equal to + the value of qcom,cpr-fuse-corners. If this property is not present, + then all target quotient parameters are assumed to have an offset of 0 + and a multiplier of 1 (i.e. no decoding needed). +- qcom,cpr-enable: Present: CPR enabled by default. + Not Present: CPR disable by default. +- qcom,cpr-fuse-cond-min-volt-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the conditional minimum apc voltage needs + to be applied and the fuse reading method. + The 5 elements with index[0..4] are: + [0] => the fuse row number; + [1] => LSB bit position of the bits; + [2] => number of the bits; + [3] => the expected data to read; + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading; + When the value of the fuse bits specified by first 3 elements is not equal to + the value in 4th element, then set the apc voltage for all parts running + at each voltage corner to be not lower than the voltage defined + using "qcom,cpr-cond-min-voltage". +- qcom,cpr-cond-min-voltage: Minimum voltage in microvolts allowed for cpr-regulator output if the fuse bits + defined in qcom,cpr-fuse-cond-min-volt-sel have not been programmed with the + expected data. This is required if cpr-fuse-cond-min-volt-sel is present. +- qcom,cpr-fuse-uplift-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to enable or disable the pvs voltage uplift workaround, + and the fuse reading method. + The 5 elements with index[0..4] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => number of the bits; + [3]: => the value to indicate if the apc pvs voltage uplift workaround will + be enabled; + [4]: => fuse reading method, 0 for direct reading or 1 for SCM reading. + When the value of the fuse bits specified by first 3 elements equals to the + value in 4th element, the pvs voltage uplift workaround will be enabled. +- qcom,speed-bin-fuse-sel: Array of 4 elements to indicate where to read the speed bin of the processor, + and the fuse reading method. + The 4 elements with index[0..3] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => number of the bits; + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-voltage: Uplift in microvolts used for increasing pvs init voltage. If this property is present, + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-max-volt: Maximum voltage in microvolts used for pvs voltage uplift workaround to limit + the maximum pvs voltage. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-quotient: Array of target quotient increments to add to the fused quotients of each + fuse corner as part of the PVS voltage uplift workaround. + The elements in the array are ordered from lowest voltage + corner to highest voltage corner. This property must be of + length defined by qcom,cpr-fuse-corners. This is required + if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-speed-bin: The speed bin value corresponding to one type of processor which needs to apply the + pvs voltage uplift workaround. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-fuse-version-map: Array of integer tuples which each match to a given combination of CPR + fuse parameter values. Each tuple consists of N + 3 elements. Where + N is the number of fuse corners defined by the qcom,cpr-fuse-corners + property. The elements in one tuple are: + [0]: => the speed bin of the CPU + [1]: => the PVS version of the CPU + [2]: => the CPR fuse revision + [3 - N+2]: => the ring oscillator select value of each fuse corner + ordered from lowest to highest + Any element in a tuple may use the value 0xffffffff as a wildcard + which will match against any fuse parameter value. The first tuple + that matches against the fuse values read from hardware will be used. + This property is used by several properties to provide an index into + their lists. +- qcom,cpr-allowed: Integer values that specifies whether the closed loop CPR is allowed or + not for a particular fuse revision. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-allowed must contain the same number + of integers as that of the number of tuples in qcom,cpr-fuse-version-map. + If the integer value has a value 0 for a particular fuse revision, then it + is treated as if the closed loop operation is disabled in the fuse. If the + integer value has a value 1 for a particular fuse revision, then the closed + loop operation is enabled for that fuse revision. If nothing is specified + for a particular fuse revision, then the closed loop operation is enabled + for that fuse revision by default. +- qcom,cpr-quotient-adjustment: Array of integer tuples of target quotient adjustments to add to the fused + quotients of each fuse corner. The elements in a tuple are ordered from + lowest voltage corner to highest voltage corner. Each tuple must be of + length defined by qcom,cpr-fuse-corners. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-quotient-adjustment must contain the + same number of tuples as qcom,cpr-fuse-version-map. These tuples are then + mapped one-to-one in the order specified. E.g. if the second + qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient + adjustments defined in the second qcom,cpr-quotient-adjustment tuple will + be applied. If the qcom,cpr-fuse-version-map property is not specified, + then qcom,cpr-quotient-adjustment must contain a single tuple which is then + applied unconditionally. If this property is specified, then the quotient + adjustment values are added to the target quotient values read from fuses + before writing them into the CPR GCNT target control registers. + This property can be used to add or subtract static voltage margin from the + regulator managed by the CPR controller. +- qcom,cpr-init-voltage-adjustment: Array of integer tuples of initial voltage adjustments in microvolts to + add to the fused initial voltage values of each fuse corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length defined by qcom,cpr-fuse-corners. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-init-voltage-adjustment must contain the same number of tuples as + qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then the initial voltage adjustments defined in the + second qcom,cpr-init-voltage-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-init-voltage-adjustment must contain a single tuple which is then + applied unconditionally. This property can be used to add or subtract + static initial voltage margin from the regulator managed by the CPR + controller. +- qcom,cpr-quot-offset-adjustment: Array of integer tuples of target quotient offset adjustments to add + to the fused quotient offsets of each fuse corner. The elements in a tuple + are ordered from lowest voltage corner to highest voltage corner. Each tuple + must be of length defined by qcom,cpr-fuse-corners. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-quot-offset-adjustment must contain the + same number of tuples as qcom,cpr-fuse-version-map. These tuples are then + mapped one-to-one in the order specified. E.g. if the second + qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient + offset adjustments defined in the second qcom,cpr-quot-offset-adjustment tuple + will be applied. If the qcom,cpr-fuse-version-map property is not specified, + then qcom,cpr-quot-offset-adjustment must contain a single tuple which is then + applied unconditionally. If this property is specified, then the quotient + offset adjustment values are added to the target quotient offset values read + from fuses. + This property can be used to add or subtract static quotient offset margin from + the regulator managed by the CPR controller. +- qcom,cpr-clamp-timer-interval: The number of 64 reference clock cycle blocks to delay for whenever + the clamp signal, sensor mask registers or sensor bypass registers + change. The CPR controller loop is disabled during this delay. + Supported values are 0 to 255. If this property is not specified, + then a value of 0 is assumed. Note that if this property has a + value greater than 0, then software cannot accurately determine the + error_steps value that corresponds to a given CPR measurement + unless processor power collapsing is disabled. If this property + has a value of 0, then the CPR controller loop is not disabled and + re-enabled while idle if the clamp signal changes. Instead, it + will remain idle until software issues an ACK or NACK command. + This ensures that software can read the error_steps value which + resulted in the CPR up or down interrupt. Setting this property to + a value greater than 0 is useful for resetting the CPR sensors of a + processor that uses BHS type voltage switches in order to avoid + anomalous CPR up interrupts when exiting from power collapse. +- vdd-apc-optional-prim-supply: Present: Regulator of highest priority to supply VDD APC power + Not Present: No such regulator. +- vdd-apc-optional-sec-supply: Present: Regulator of second highest priority to supply VDD APC power. + Not Present: No such regulator. +- qcom,cpr-speed-bin-max-corners: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version to + the maximum virtual voltage corner corresponding to each fuse corner. The value N + corresponds to the number of fuse corners specified by qcom,cpr-fuse-corners. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as + a wildcard to match any PVS version values. + [2 - N+1]: => the max virtual voltage corner value corresponding to each fuse corner + for this speed bin, ordered from lowest voltage corner to highest + voltage corner. + No CPR target quotient scaling is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified, then quotient scaling is enabled for the highest voltage corner. If this property is + not specified, then no quotient scaling can take place. +- qcom,cpr-corner-map: Array of elements of fuse corner value for each virtual corner. + The location or 1-based index of an element in the list corresponds to + the virtual corner value. For example, the first element in the list is the fuse corner + value that virtual corner 1 maps to. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,cpr-corner-frequency-map: Array of tuples in which a tuple describes a corner to application processor frequency + mapping. + The 2 elements in one tuple are: + [0]: => a virtual voltage corner. + [1]: => the application processor frequency in Hz corresponding to the virtual corner. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,pvs-version-fuse-sel: Array of 4 elements to indicate where to read the pvs version of the processor, + and the fuse reading method. + The 4 elements with index[0..3] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => the number of bits; + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading. +- qcom,cpr-voltage-ceiling-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version + to the ceiling voltage to apply for each virtual voltage corner. The value N + corresponds to the number of virtual corners as specified by the number of elements + in the qcom,cpr-corner-map property. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as a + wildcard to match any PVS version values. + [2 - N+1]: => the ceiling voltage value in microvolts corresponding to each virtual + corner for this speed bin, ordered from lowest voltage corner to + highest voltage corner. + No ceiling override is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified and the speed bin + PVS version matches, then the per-virtual-corner ceiling + voltages will be used in place of the per-fuse-corner ceiling voltages defined in the + qcom,cpr-voltage-ceiling property. If this property is not specified, then the + per-fuse-corner ceiling voltages will always be used. +- qcom,cpr-voltage-floor-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version + to the floor voltage to apply for each virtual voltage corner. The value N + corresponds to the number of virtual corners as specified by the number of elements + in the qcom,cpr-corner-map property. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as a + wildcard to match any PVS version values. + [2 - N+1]: => the floor voltage value in microvolts corresponding to each virtual + corner for this speed bin, ordered from lowest voltage corner to + highest voltage corner. + No floor override is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified and the speed bin + PVS version matches, then the per-virtual-corner floor + voltages will be used in place of the per-fuse-corner floor voltages defined in the + qcom,cpr-voltage-floor property. If this property is not specified, then the + per-fuse-corner floor voltages will always be used. +- qcom,cpr-floor-to-ceiling-max-range: Array of integer tuples of floor-to-ceiling max range values in microvolts + to be subtracted from the ceiling voltage values of each virtual corner. + Supported values are those greater than or equal 0, or (-1). The value 0 for a corner + implies that the floor value for that corner has to equal to its ceiling value. + The value (-1) for a corner implies that no modification to the default floor voltage + is required. The elements in a tuple are ordered from lowest voltage corner to highest + voltage corner. Each tuple must be of the length equal to the number of virtual corners + as specified by the number of elements in the qcom,cpr-corner-map property. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-dynamic-floor-override-adjustment must contain the same number of + tuples as qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then voltage adjustments defined in the second + qcom,cpr-dynamic-floor-override-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-dynamic-floor-override-adjustment must contain a single tuple which + is then applied unconditionally. +- qcom,cpr-virtual-corner-init-voltage-adjustment: Array of integer tuples of voltage adjustments in microvolts to be + added to the initial voltage values of each virtual corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length equal to the number of virtual corners as + specified by the number of elements in the qcom,cpr-corner-map property. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-virtual-corner-init-voltage-adjustment must contain the same number of + tuples as qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then voltage adjustments defined in the second + qcom,cpr-virtual-corner-init-voltage-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-virtual-corner-init-voltage-adjustment must contain a single tuple which + is then applied unconditionally. +- qcom,cpr-virtual-corner-quotient-adjustment: Array of integer tuples of quotient offsets to be added to + the scaled target quotient of each virtual corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length equal to the number of virtual corners as + specified by the number of elements in the qcom,cpr-corner-map property. + If the qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-virtual-corner-quotient-adjustment must contain the same number of tuples as + qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then quotient adjustments defined in the second + qcom,cpr-virtual-corner-quotient-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-virtual-corner-quotient-adjustment must contain a single tuple which is then + applied unconditionally. +- qcom,cpr-cpus: Array of CPU phandles which correspond to the cores that this cpr-regulator + device must monitor when adjusting the voltage and/or target quotient based + upon the number of online cores or make sure that one of them must be online + when performing de-aging measurements. This property must be specified in order to + utilize the qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment or + qcom,cpr-online-cpu-virtual-corner-quotient-adjustment or qcom,cpr-aging-sensor-id properties. +- qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment: Array of tuples where each tuple specifies + the voltage adjustment for each corner. These adjustments apply to the + initial voltage of each corner. The size of each tuple must be equal + to qcom,cpr-fuse-corners if consumers request fuse corners or the length of + qcom,cpr-corner-map if consumers request virtual corners. In each tuple, the + value corresponds to the voltage adjustment when running at that corner at + init, from lowest to highest. The tuples must be organized into 1 group if + qcom,cpr-fuse-version-map is not specified or the same number of groups as + the number of tuples in qcom,cpr-fuse-version-map. The i-th group of tuples + corresponds to the voltage adjustments for i-th fuse version map tuple. In + each group, there are 1 plus length of qcom,cpr-cpus tuples, each tuple + corresponds to the number of cores online, from 0 to the number of elements + in qcom,cpr-cpus. +- qcom,cpr-online-cpu-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a + given virtual corner may be reduced to the per number of cores online, + per-virtual corner ceiling voltage value. This property takes precedence + over qcom,cpr-scaled-init-voltage-as-ceiling if both are specified. +- qcom,cpr-online-cpu-virtual-corner-quotient-adjustment: Array of tuples where each tuple specifies + the quotient adjustment for each corner. These adjustments will be applied + to each corner at run time. The size of each tuple must be equal to + qcom,cpr-fuse-corners if consumers request fuse corners or the length of + qcom,cpr-corner-map if consumers request virtual corners. In each tuple, + the value corresponds to the quotient adjustment when running at that corner, + from lowest to highest. The tuples must be organized into 1 group if + qcom,cpr-fuse-version-map is not specified or the same number of groups + as the number of tuples in qcom,cpr-fuse-version-map. The i-th group of + tuples corresponds to the quotient adjustments for i-th fuse version map + tuple. In each group, there are 1 plus length of qcom,cpr-cpus tuples, + each tuple corresponds to the number of cores online, from 0 to the + number of elements in qcom,cpr-cpus. +- qcom,cpr-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given virtual + corner may be reduced to the per-fuse-corner initial voltage fuse value. +- qcom,cpr-scaled-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given + virtual corner may be reduced to the interpolated, per-virtual-corner initial + voltage value. Note that if both qcom,cpr-init-voltage-as-ceiling and + qcom,cpr-scaled-init-voltage-as-ceiling are specified, then + qcom,cpr-scaled-init-voltage-as-ceiling will take precedence since the interpolated + voltages are necessarily less than or equal to the fused initial voltage values. +- qcom,cpr-voltage-scaling-factor-max: Array of values which define the maximum allowed scaling factor to apply + when calculating per-corner initial voltage values for each fuse corner. The + array must be of length equal to the value of the qcom,cpr-fuse-corners property. + Each element in the array maps to the fuse corners in increasing order. + The elements have units of uV/MHz. Each element corresponds to 'max_factor' in + the following equation: + init_voltage_min(f) = fuse_init_voltage(f) - (fuse_f_max - f) * max_factor + If this property is not specified, then the initial voltage for each virtual + corner will be set to the initial voltage of the associated fuse corner. +- qcom,cpr-quot-adjust-scaling-factor-max: Array of values which define the maximum allowed scaling factor to + apply when calculating per-virtual-corner target quotients for each fuse + corner. Two data formats are allowed for this property. The primary one + requires that the array be of length equal to the value of the + qcom,cpr-fuse-corners property. When using this format, each element in the + array maps to the fuse corners in increasing order. The second depreciated + format allows for only a single element to be specified which defines the + maximum scaling factor for the highest fuse corner. In this case, a value of + 0 is assumed for the lower fuse corners. The elements of this property have + units of QUOT/GHz. Each element corresponds to 'max_factor' in the following + equation: + quot_min(f) = fuse_quot(f) - (fuse_f_max - f) * max_factor / 1000 + where f and fuse_f_max have units of MHz. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,cpr-fuse-init-voltage: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get an initial voltage for a fuse corner. The fuse values + are encoded as voltage steps higher or lower than the voltages defined in + qcom,cpr-voltage-ceiling. Each step corresponds to the voltage defined by + the qcom,cpr-init-voltage-step property. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The quadruples are ordered from the lowest voltage fuse corner to the + highest voltage fuse corner. + A given cpr-regulator device must have either qcom,cpr-fuse-init-voltage + specified or qcom,pvs-voltage-table (and its associated properties). +- qcom,cpr-fuse-redun-init-voltage: Array of quadruples in which each quadruple specifies a fuse location + to read in order to get the redundant initial voltage for a fuse corner. + This property is the same as qcom,cpr-fuse-init-voltage except that it is + only utilized if a chip is configured to use the redundant set of fuse + values. This property is required if qcom,cpr-fuse-redun-sel and + qcom,cpr-fuse-init-voltage are specified. +- qcom,cpr-init-voltage-ref: Array of reference voltages in microvolts used when decoding the initial + voltage fuse values. The elements in the array are ordered from lowest + voltage corner to highest voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-init-voltage is present. +- qcom,cpr-init-voltage-step: The voltage step size in microvolts of the CPR initial voltage fuses described by the + qcom,cpr-fuse-init-voltage property. + This property is required if qcom,cpr-fuse-init-voltage is present. +- mem-acc-supply: Regulator to vote for the memory accelerator configuration. + Not Present: memory accelerator configuration not supported. +- qcom,mem-acc-corner-map: Array of integer which defines the mapping from mem-acc corner value for each + virtual corner. Each element is a mem-acc state for the corresponding virtual corner. + The elements in the array are ordered from lowest voltage corner to highest voltage corner. +- qcom,fuse-remap-source: Array of quadruples in which each quadruple specifies a fuse location to + remap. The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => the number of bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The fuse bits for all quadruples are packed together in the order specified + into 64-bit virtual fuse rows beginning at the row number defined in the + qcom,fuse-remap-base-row property. The remapped rows may be used by any + other properties. + Example: + qcom,fuse-remap-base-row = <1000>; + qcom,fuse-remap-source = + <13 57 2 0>, + <14 30 3 0>, + <20 1 7 0>, + <40 47 120 0>; + + This results in the following bit remapping: + + Row Bits Remap Row Remap Bits + 13 57..58 --> 1000 0..1 + 14 30..32 --> 1000 2..4 + 20 1..7 --> 1000 5..11 + 40 47..63 --> 1000 12..28 + 41 0..34 --> 1000 29..63 + 41 35..63 --> 1001 0..28 + 42 0..34 --> 1001 29..63 + 42 35..38 --> 1002 0..3 + + A tuple like this could then be used to reference some of the + concatenated bits from rows 13, 14, and 20: + + qcom,cpr-fuse-init-voltage = <1000 0 6 0>; +- qcom,fuse-remap-base-row: Integer which defines the virtual row number to use as a base when remapping + fuse bits. The remap base row number can be any value as long as it is + greater than all of the real row numbers addressed in other properties of + the cpr-regulator device node. This property is required if + qcom,fuse-remap-source is specified. +- qcom,cpr-quot-min-diff: Integer which defines the minimum target-quotient difference between + the highest and (highest - 1) fuse corner to keep CPR enabled. If this + property is not specified a default value of 50 is used. +- qcom,cpr-fuse-quot-offset: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get the quotient offset for a fuse corner. The fuse values + are encoded as the difference between quotients of that fuse corner and its + adjacent lower fuse corner divided by an unpacking multiplier value defined + under qcom,cpr-fuse-quot-offset-scale property. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The quadruples are ordered from the lowest fuse corner to the highest + fuse corner. + Quotient offset read from the fuse locations above can be overridden with + the property qcom,cpr-quot-adjust-scaling-factor-max. +- qcom,cpr-fuse-quot-offset-scale: Array of integer values which defines the multipliers to decode the quotient offsets + of each fuse corner. The elements in the array are ordered from the lowest voltage fuse corner + to the highest voltage fuse corner. If this property is not present, then all target quotient + parameters are assumed to have a multiplier of 1 (i.e. no decoding needed). +- qcom,cpr-redun-fuse-quot-offset: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get the redundant quotient offset for a fuse corner. This + property is the same as qcom,cpr-fuse-quot-offset except that it is only + utilized if a chip is configured to use the redundant set of fuse values. +- qcom,cpr-fuse-min-quot-diff: Array of values which define the minimum difference allowed between the adjusted + quotients of the fuse corners. The length of the array should be equal to the value + of the qcom,cpr-fuse-corners property. Where each element in the array maps to the + fuse corners in increasing order. +- qcom,cpr-min-quot-diff-adjustment: Array of integer tuples of target quotient offsets to be added to + the adjusted target quotients of each fuse corner. When the quotient difference + between two adjacent fuse corners is insufficient, the quotient for the higher fuse corner is + replaced with that of the lower fuse corner plus the adjustment value. + The elements in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length defined by qcom,cpr-fuse-corners. + If the qcom,cpr-fuse-version-map property is specified, then qcom,cpr-min-quot-diff-adjustment + must contain the same number of tuples as qcom,cpr-fuse-version-map. These tuples are then mapped + one-to-one in the order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then the quotient adjustments defined in the + second qcom,cpr-min-quot-diff-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-min-quot-diff-adjustment must contain a single tuple which is then + applied unconditionally. The qcom,cpr-min-quot-diff-adjustment property must be specified + if the qcom,cpr-fuse-min-quot-diff property is specified. +- qcom,cpr-skip-voltage-change-during-suspend: Boolean property which indicates that the CPR voltage + should not be adjusted based upon the number of online cores while + entering or exiting system suspend. +- rpm-apc-supply: Regulator to notify RPM of the APC operating + corner +- qcom,rpm-apc-corner-map: Array of integers which define the mapping of + the RPM corner to the corresponding APC virtual + corner. This property must be defined if + 'rpm-apc-supply' is present. +- qcom,vsens-corner-map: Array of integers which define the mapping of the VSENS corner to the + corresponding APC fuse corner. The qcom,vsens-corner-map and + vdd-vsense-corner-supply properties must both be specified for a given + cpr-regulator device or neither must be specified. +- vdd-vsens-corner-supply: Regulator to specify the current operating fuse corner to the Voltage Sensor. +- vdd-vsens-voltage-supply: Regulator to specify the corner floor/ceiling voltages to the Voltage Sensor. +- qcom,cpr-aging-sensor-id: Array of CPR sensor IDs to be used in the CPR de-aging algorithm. The number + of values should be equal to number of sensors selected for age calibration. + If this property is not specified, then the de-aging procedure is not enabled. +- qcom,cpr-de-aging-allowed: Integer values that specify whether the CPR de-aging procedure is allowed or + not for a particular fuse revision. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-de-aging-allowed must contain the same number + of elements as there are tuples in qcom,cpr-fuse-version-map. If qcom,cpr-fuse-version-map + is not specified, then qcom,cpr-de-aging-allowed must contain a single value that + is used unconditionally. An element value of 1 means that the CPR de-aging procedure + can be performed for parts with the corresponding fuse revision. An element value of 0 + means that CPR de-aging cannot be performed. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ref-corner: The vdd-apc-supply reference virtual voltage corner to be set during the CPR de-aging + measurements. This corner value is needed to set appropriate voltage on + the dependent voltage rails such as vdd-mx and mem-acc. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ref-voltage: The vdd-apc-supply reference voltage in microvolts to be set during the + CPR de-aging measurements. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-max-aging-margin: The maximum allowed aging voltage margin in microvolts. This is used to limit + the calculated aging voltage margin. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-non-collapsible-sensors: Array of CPR sensor IDs which are in non-collapsible domain. The sensor IDs not + specified in the array should be bypassed for the de-aging procedure. The number of + elements should be less than or equal to 32. The values of the array elements should + be greater than or equal to 0 and less than or equal to 31. + This property is required for power-domains with bypass mux present in HW. + This property can be required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ro-scaling-factor: The aging ring oscillator (RO) scaling factor with units of QUOT/V. + This value is used for calculating a voltage margin from RO measurements. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-ro-scaling-factor: Array of scaling factors with units of QUOT/V for each ring oscillator ordered + from the lowest to the highest RO. These values are used to calculate + the aging voltage margin adjustment for all of the ROs. Since CPR2 supports + exactly 8 ROs, the array must contain 8 elements corresponding to RO0 through RO7 in order. + If a given RO is unused for a fuse corner, then its scaling factor may be specified as 0. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-derate: Array of scaling factors which define the amount of derating to apply to the reference + aging voltage margin adjustment for each of the fuse corners. Each element has units + of uV/mV. This property must be of length defined by qcom,cpr-fuse-corners. + The elements are ordered from the lowest to the highest fuse corner. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-fuse-aging-init-quot-diff: Array of quadruples in which each quadruple specifies a fuse location to read in + order to get an initial quotient difference. The difference between quot min and quot max + is fused as the initial quotient difference. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The number of quadruples should be equal to the number of values specified in + the qcom,cpr-aging-sensor-id property. This property is required if + the qcom,cpr-aging-sensor-id property has been specified. +Example: + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xfc4b8000 0x1000>; + reg-names = "rbcpr", "efuse_addr"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + qcom,cpr-fuse-corners = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <12>; + + qcom,pvs-fuse = <22 6 5 1>; + qcom,pvs-fuse-redun-sel = <22 24 3 2 1>; + qcom,pvs-fuse-redun = <22 27 5 1>; + + qcom,pvs-voltage-table = + <1050000 1150000 1350000>, + <1050000 1150000 1340000>, + <1050000 1150000 1330000>, + <1050000 1150000 1320000>, + <1050000 1150000 1310000>, + <1050000 1150000 1300000>, + <1050000 1150000 1290000>, + <1050000 1150000 1280000>, + <1050000 1150000 1270000>, + <1050000 1140000 1260000>, + <1050000 1130000 1250000>, + <1050000 1120000 1240000>, + <1050000 1110000 1230000>, + <1050000 1100000 1220000>, + <1050000 1090000 1210000>, + <1050000 1080000 1200000>, + <1050000 1070000 1190000>, + <1050000 1060000 1180000>, + <1050000 1050000 1170000>, + <1050000 1050000 1160000>, + <1050000 1050000 1150000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>; + qcom,cpr-voltage-ceiling = <1050000 1150000 1280000>; + qcom,cpr-voltage-floor = <1050000 1050000 1100000>; + vdd-apc-supply = <&pm8226_s2>; + vdd-apc-optional-prim-supply = <&ncp6335d>; + vdd-apc-optional-sec-supply = <&fan53555>; + vdd-mx-supply = <&pm8226_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,cpr-clamp-timer-interval = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,vsens-corner-map = <1 2 2>; + vdd-vsens-corner-supply = <&vsens_apc0_corner>; + vdd-vsens-voltage-supply = <&vsens_apc0_voltage>; + + rpm-apc-supply = <&rpm_apc_vreg>; + qcom,rpm-apc-corner-map = <4 4 5 5 7 7 7 7 7 7 7 7>; + + qcom,cpr-fuse-row = <138 1>; + qcom,cpr-fuse-bp-cpr-disable = <36>; + qcom,cpr-fuse-bp-scheme = <37>; + qcom,cpr-fuse-target-quot = <24 12 0>; + qcom,cpr-fuse-target-quot-size = <12 12 12>; + qcom,cpr-fuse-ro-sel = <54 38 41>; + qcom,cpr-fuse-revision = <140 26 2 0>; + qcom,cpr-fuse-redun-sel = <138 57 1 1 1>; + qcom,cpr-fuse-redun-row = <139 1>; + qcom,cpr-fuse-redun-target-quot = <24 12 0>; + qcom,cpr-fuse-redun-ro-sel = <46 36 39>; + qcom,cpr-fuse-cond-min-volt-sel = <54 42 6 7 1>; + qcom,cpr-cond-min-voltage = <1140000>; + qcom,cpr-fuse-uplift-sel = <22 53 1 0 0>; + qcom,cpr-uplift-voltage = <50000>; + qcom,cpr-uplift-quotient = <0 0 120>; + qcom,cpr-uplift-max-volt = <1350000>; + qcom,cpr-uplift-speed-bin = <1>; + qcom,speed-bin-fuse-sel = <22 0 3 0>; + qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 300000000>, + <2 384000000>, + <3 600000000>, + <4 787200000>, + <5 998400000>, + <6 1094400000>, + <7 1190400000>, + <8 1305600000>, + <9 1344000000>, + <10 1401600000>, + <11 1497600000>, + <12 1593600000>; + qcom,pvs-version-fuse-sel = <22 4 2 0>; + qcom,cpr-speed-bin-max-corners = + <0 1 2 4 7>, + <1 1 2 4 12>, + <2 1 2 4 10>, + <5 1 2 4 14>; + qcom,cpr-fuse-target-quot-scale = + <0 1>, + <0 1>, + <0 1>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 650 650>; + qcom,cpr-fuse-quot-offset = + <138 53 5 0>, + <138 53 5 0>, + <138 48 5 0>, + <138 58 5 0>; + qcom,cpr-fuse-redun-quot-offset = + <200 53 5 0>, + <200 53 5 0>, + <200 48 5 0>, + <200 58 5 0>; + qcom,cpr-fuse-init-voltage = + <27 36 6 0>, + <27 18 6 0>, + <27 0 6 0>; + qcom,cpr-fuse-redun-init-voltage = + <140 36 6 0>, + <140 18 6 0>, + <140 0 6 0>; + qcom,cpr-init-voltage-ref = <1050000 1150000 1280000>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-voltage-ceiling-override = + <1 1 1050000 1050000 1150000 1150000 1280000 + 1280000 1280000 1280000 1280000 1280000 + 1280000 1280000>; + qcom,cpr-voltage-floor-override = + <1 1 1050000 1050000 1050000 1050000 1060000 + 1070000 1080000 1090000 1100000 1100000 + 1100000 1100000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + + qcom,cpr-fuse-version-map = + <0xffffffff 0xffffffff 2 4 4 4>, + <0xffffffff 0xffffffff 2 6 6 6>, + <0xffffffff 0xffffffff 3 4 4 4>; + qcom,cpr-quotient-adjustment = + <0 0 (-210)>, + <0 0 (-60)>, + <0 0 (-94)>; + qcom,cpr-quot-offset-adjustment = + <0 0 (-5)>; + qcom,cpr-init-voltage-adjustment = + <0 0 (-100000)>, + <0 0 (-100000)>, + <0 0 (-45000)>; + qcom,cpr-fuse-min-quot-diff = <0 0 40>; + qcom,cpr-min-quot-diff-adjustment = + <0 0 0>, + <0 0 72>, + <0 0 104>; + qcom,cpr-floor-to-ceiling-max-range = + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) 50000 50000 50000 50000 50000>; + qcom,cpr-virtual-corner-init-voltage-adjustment = + <0 0 0 (-10000) 0 0 0 0 0 0 0 0>, + <0 0 0 0 0 0 0 0 0 0 0 (-20000)>, + <0 0 0 0 0 0 0 0 0 0 0 (-30000)>; + qcom,cpr-virtual-corner-quotient-adjustment = + <0 0 0 100 0 0 0 0 0 0 0 0>, + <0 0 0 0 0 0 0 0 0 0 0 (-300)>, + <0 0 0 (-60) 0 0 0 0 0 0 0 0>; + qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment = + /* 1st fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 2nd fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 3rd fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */ + qcom,cpr-online-cpu-virtual-corner-quotient-adjustment = + /* 1st fuse version tuple matched */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */ + <0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 2nd fuse version tuple matched */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */ + <0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 3rd fuse version tuple matched */ + <0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 0 CPUs online */ + <0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 1 CPUs online */ + <0 0 0 (-11) (-11) (-11) (-11) (-11) (-21) 0 (-21) (-21)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */ + qcom,cpr-allowed = + <0>, + <1>, + <1>; + + qcom,fuse-remap-base-row = <1000>; + qcom,fuse-remap-source = + <140 7 3 0>, + <138 45 5 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + + qcom,cpr-aging-sensor-id = <17, 18>; + qcom,cpr-aging-ref-corner = <4>; + qcom,cpr-aging-ref-voltage = <1050000>; + qcom,cpr-max-aging-margin = <15000>; + qcom,cpr-de-aging-allowed = + <0>, + <0>, + <1>; + qcom,cpr-non-collapsible-sensors= <7 12 17 22>; + qcom,cpr-aging-ro-scaling-factor = <3500>; + qcom,cpr-ro-scaling-factor = <0 2500 2500 2500 0 0 0 0>; + qcom,cpr-aging-derate = <1000 1000 1250>; + qcom,cpr-fuse-aging-init-quot-diff = + <101 0 8 0>, + <101 8 8 0>; + }; diff --git a/bindings/regulator/mem-acc-regulator.txt b/bindings/regulator/mem-acc-regulator.txt new file mode 100644 index 000000000000..a681f4854b3a --- /dev/null +++ b/bindings/regulator/mem-acc-regulator.txt @@ -0,0 +1,288 @@ +Qualcomm Technologies, Inc. Memory Accelerator + +Memory accelerator configures the power-mode (corner) for the +accelerator. + +Required properties: +- compatible: Must be "qcom,mem-acc-regulator" +- regulator-name: A string used to describe the regulator +- regulator-min-microvolt: Minimum corner value as min constraint, which + should be 1 for SVS corner +- regulator-max-microvolt: Maximum corner value as max constraint, which + should be 4 for SUPER_TURBO or 3 for TURBO + +Optional properties: +- reg: Register addresses for acc-sel-l1, acc-sel-l2 control, acc-en, + MEM ACC eFuse address, acc-l1-custom , acc-l2-custom, + mem-acc-type1, mem-acc-type2, mem-acc-type3, mem-acc-type4, + mem-acc-type5 and mem-acc-type6. +- reg-names: Register names. Must be "acc-sel-l1", + "acc-sel-l2", "acc-en", "efuse_addr", + "acc-l1-custom", "acc-l2-custom", "mem-acc-type1", + "mem-acc-type2", "mem-acc-type3", "mem-acc-type4", + "mem-acc-type5", "mem-acc-type6". + A given mem-acc-regulator driver must have "acc-sel-l1" or + "acc-sel-l2" or "mem-acc-type*" reg-names property and + related register address property. +- qcom,corner-acc-map Array which maps the APC (application processor) + corner value to the accelerator corner. The number of elements + in this property defines the number of accelerator corners. + Either qcom,corner-acc-map property or qcom,cornerX-reg-config + properties should be specified. +- qcom,acc-en-bit-pos Array which specifies bit positions in the + 'acc-en' register. Setting these bits forces the + the acclerator to use the corner value specified + in the 'acc-sel-l1' and 'acc-sel-l2' register. +- qcom,acc-sel-l1-bit-size Integer which specifies the number of bits in + the 'acc-sel-l1' register which define each L1 + select parameter. If this property is not + specified, then a default value of 2 is assumed. +- qcom,acc-sel-l1-bit-pos Array which specifies bit positions in the + 'acc-sel-l1' register. Each element in this array + is the LSB of an N-bit value where 'N' is + defined by the qcom,acc-sel-l1-bit-size + property. This N-bit value specifies the corner + value used by the accelerator for the L1 cache. +- qcom,acc-sel-l2-bit-size Integer which specifies the number of bits in + the 'acc-sel-l2' register which define each L2 + select parameter. If this property is not + specified, then a default value of 2 is assumed. +- qcom,acc-sel-l2-bit-pos Array which specifies bit positions in the + 'acc-sel-l2' register. Each element in this array + is the LSB of an N-bit value where 'N' is + defined by the qcom,acc-sel-l2-bit-size + property. This N-bit value specifies the corner + value used by the accelerator for the L2 cache. +- qcom,l1-acc-custom-data: Array which maps APC corner values to L1 ACC custom data values. + The corresponding custom data is written into the custom register + while switching between APC corners. The custom register address + is specified by "acc-11-custom" reg-property. The length of the array + should be equal to number of APC corners. +- qcom,l2-acc-custom-data: Array which maps APC corner values to L2 ACC custom data values. + The corresponding custom data is written into the custom register + while switching between APC corners. The custom register address + is specified by "acc-l2-custom" reg-property. The length of the array + should be equal to number of APC corners. +- qcom,override-acc-fuse-sel: Array of 4 elements which specify the way to read the override fuse. + The override fuse value is used by the qcom,override-fuse-version-map + to identify the correct set of override properties. + The 4 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,override-fuse-version-map: Array of integers which each match to a override fuse value. + Any element in a tuple may use the value 0xffffffff as a wildcard. + The index of the first value (in the array) which matches the override fuse + is used to select the right tuples from the other override properties. +- qcom,override-corner-acc-map: Array of tuples which overrides the existing acc-corner map + (specified by qcom,corner-acc-map) with corner values selected + from this property. "qcom,override-corner-acc-map" must contain the + same number of tuples as "qcom,override-fuse-version-map". These tuples + are then mapped one-to-one in the order specified. If the + "qcom,override-fuse-version-map" property is not specified, then + "qcom,override-corner-acc-map" must contain a single tuple which is then + applied unconditionally. +- qcom,override-l1-acc-custom-data: Array of tuples of which overrides the existing l1-acc-custom data + (specified by qcom,l1-acc-custom-data), with values specified in this property. + The corresponding custom data is written into the custom register while + switching between APC corners. The custom register address is specified by + "acc-11-custom" reg-property. This property can only be specified if the + "qcom,l1-acc-custom-data" is already defined. If the + "qcom,override-fuse-version-map" property is specified, then + qcom,override-l1-acc-custom-data must contain the same number of tuples + as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-l1-acc-custom-data" must contain a single + tuple which is then applied unconditionally. +- qcom,override-l2-acc-custom-data: Array of tuples of which overrides the existing l1-acc-custom data + (specified by qcom,l2-acc-custom-data), with values specified in this property. + The corresponding custom data is written into the custom register while + switching between APC corners. The custom register address is specified by + "acc-12-custom" reg-property. This property can only be specified if the + "qcom,l2-acc-custom-data" is already defined. If the + "qcom,override-fuse-version-map" property is specified, then + "qcom,override-l2-acc-custom-data" must contain the same number of tuples + as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-l2-acc-custom-data" must contain a single + tuple which is then applied unconditionally. +- qcom,mem-acc-type1: Array which specifies the value to be written to the mem acc type1 register for each fuse + corner, from the lowest fuse corner to the highest fuse corner. The length of the array + must be equal to the number of APC fuse corners. This property must be present if reg names + specifies mem-acc-type1. +- qcom,mem-acc-type2: Same as qcom,mem-acc-type1 except for mem acc type2 register. +- qcom,mem-acc-type3: Same as qcom,mem-acc-type1 except for mem acc type3 register. +- qcom,mem-acc-type4: Same as qcom,mem-acc-type1 except for mem acc type4 register. +- qcom,mem-acc-type5: Same as qcom,mem-acc-type1 except for mem acc type5 register. +- qcom,mem-acc-type6: Same as qcom,mem-acc-type1 except for mem acc type6 register. +- qcom,acc-reg-addr-list: Array of register addresses which need to be programmed during any corner switch. + This property can be used when multi register configuration is needed during a corner switch. +- qcom,acc-init-reg-config: Array of tuples specify the multi register configuration sequence need to be programmed + one time during device boot. + The format of each tuple as below: + + Where register-address-index is used as an index in to qcom,acc-reg-addr-list property + to get the required register address and the value is programmed in to the corresponding + mapped register address. This property is required if qcom,acc-corner-addr-val-map + property specified. +- qcom,cornerX-reg-config: Array of tuples specify the multi register configuration sequence need to be programmed + when switching from acc corner X to any other corner. The possible values for X are {1, N}, + where N is the value defined in qcom,num-acc-corners. + The format of each tuple as below: + + Where register-address-index is used as an index in to qcom,acc-reg-addr-list property + to get the required register address and the value is programmed in to the corresponding + mapped register address. Same index can be used multiple times when the register is + required to configure multiple times with different values in the sequence. + The number of register configuration sequences should be equal to N, where N is the + value specified in qcom,num-acc-corners property. Also, the number of tuples in each + register configuration sequence should be same and must be equal to the maximum required + register configurations in any sequence. The invalid register configuration can be + specified as <(-1) (-1)>. This property can only be specified when qcom,acc-corner-addr-val-map + property already defined. Either this property or qcom,corner-acc-map should be specified. +- qcom,num-acc-corners: The number of acc corners supported. This property is required if qcom,cornerX-reg-config + property specified. +- qcom,boot-acc-corner: The acc corner used during device boot. This property is required if qcom,cornerX-reg-config + property specified. +- qcom,override-cornerX-reg-config: A grouping of register configuration sequence lists. Each list is same as + the qcom,cornerX-reg-config property. The possible values for X are {1, N} where N is + the value defined in qcom,num-acc-corners. This property is used to specify the different + register configuration sequence lists and select one list among them based on the selected + index in qcom,override-fuse-version-map property. The selected list overrides the existing + register configuration sequence list specified in "qcom,cornerX-reg-config". If the + "qcom,override-fuse-version-map" property is specified, then + "qcom,override-cornerX-reg-config" must contain the same number of register + configuration sequence lists as the number of tuples in "qcom,override-fuse-version-map". + These register configuration sequence lists are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-cornerX-reg-config" must contain a single + register configuration sequence list which is then applied unconditionally. + This property can only be specified if qcom,cornerX-reg-config property is already defined. +- qcom,override-acc-range-fuse-list: Array of tuples define the selection parameters used for selecting the override + mem-acc configuration. The fused values for these selection parameters are used by the + qcom,override-fuse-range-map to identify the correct set of override properties. + Each tuple contains 4 elements as defined below: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,override-fuse-range-map: Array of tuples where each tuple specifies the allowed range for all the selection parameters + defined in qcom,override-acc-range-fuse-list. The fused values of these selection parameters + are compared against their allowed range in each tuple starting from 0th tuple and use the + first matched tuple index to select the right tuples from the other override properties. + Either qcom,override-fuse-range-map or qcom,override-fuse-version-map is used to select + the override configuration. The qcom,override-fuse-range-map is used if both the + properties are specified. + +mem_acc_vreg_corner: regulator@fd4aa044 { + compatible = "qcom,mem-acc-regulator"; + reg = <0xfd4aa048 0x1>, <0xfd4aa044 0x1>, <0xfd4af000 0x1>, + <0x58000 0x1000>, <0x01942124 0x4>, <0xf900d084 1>, + <0xf900d088 1>, <0xf900d08c 1>, <0xf900d090 1>; + reg-names = "acc-en", "acc-sel-l1" , "acc-sel-l2", + "efuse_addr", "acc-l2-custom", "mem-acc-type1", + "mem-acc-type2", "mem-acc-type3", "mem-acc-type4"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-en-bit-pos = <0>; + qcom,acc-sel-l1-bit-pos = <0>; + qcom,acc-sel-l2-bit-pos = <0>; + qcom,acc-sel-l1-bit-size = <2>; + qcom,acc-sel-l2-bit-size = <2>; + qcom,corner-acc-map = <0 1 3>; + qcom,l2-acc-custom-data = <0x0 0x3000 0x3000>; + + qcom,override-acc-fuse-sel = <0 52 2 0>; + qcom,override-fuse-version-map = <0>, + <2>, + <(-1)>; + qcom,override-acc-range-fuse-list = + <37 40 3 0>, + <36 30 8 0>; + qcom,override-fuse-range-map = + <0 0>, < 0 0>, <49 63>, + <1 1>, < 0 0>, <50 63>, + <0 1>, < 95 255>, < 0 63>; + qcom,override-corner-acc-map = <0 0 1>, + <0 1 2>, + <0 1 1>; + qcom,override-l2-acc-custom-data = <0x0 0x0 0x3000>, + <0x0 0x3000 0x3000>, + <0x0 0x0 0x0>; + qcom,mem-acc-type1 = <0x02 0x02 0x00>; + qcom,mem-acc-type2 = <0x02 0x02 0x00>; + qcom,mem-acc-type3 = <0x02 0x02 0x00>; + qcom,mem-acc-type4 = <0x02 0x02 0x00>; + + qcom,acc-reg-addr-list = <0x01942130 0x01942124 0x01942120>; + qcom,acc-init-reg-config = <1 0x55> <2 0x02>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>; /* 1 -> 3 */ + + qcom,corner2-reg-config = + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>; /* 2 -> 3 */ + + qcom,corner3-reg-config = + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */ + + qcom,override-corner1-reg-config = + /* 1st fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 1 -> 3 */ + + /* 2nd fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 1 -> 3 */ + + /* 3rd fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 3 0x22>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, < 3 0x144>; /* 1 -> 3 */ + + qcom,override-corner2-reg-config = + /* 1st fuse version tuple matched */ + < 1 0x144>, < 1 0x11>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 2 -> 3 */ + + /* 2nd fuse version tuple matched */ + < 1 0x144>, < 2 0x133>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, < 1 0x33>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x133>, < 2 0x0>, < 3 0x155>, /* 2 -> 3 */ + + /* 3rd fuse version tuple matched */ + < 1 0x144>, < 1 0x11>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x22>, < 3 0x155>; /* 2 -> 3 */ + + + qcom,override-corner3-reg-config = + /* 1st fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */ + + /* 2nd fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */ + + /* 3rd fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, < 3 0x11>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */ +}; diff --git a/bindings/regulator/spm-regulator.txt b/bindings/regulator/spm-regulator.txt new file mode 100644 index 000000000000..c3241577a429 --- /dev/null +++ b/bindings/regulator/spm-regulator.txt @@ -0,0 +1,61 @@ +Qualcomm Technologies Inc. SPM Regulators + +spm-regulator is a regulator device which supports PMIC processor supply +regulators via the SPM module. + +Required properties: +- compatible: Must be "qcom,spm-regulator" +- reg: Specifies the SPMI address and size for this regulator device +- regulator-name: A string used as a descriptive name for the regulator + +Required structure: +- A qcom,spm-regulator node must be a child of an SPMI node that has specified + the spmi-slave-container property + +Optional properties: +- qcom,mode: A string which specifies the mode to use for the regulator. + Supported values are "pwm" and "auto". PWM mode is more + robust, but draws more current than auto mode. If this + property is not specified, then the regulator will remain + in whatever mode hardware or bootloaders set it to. +- qcom,cpu-num: Specifies which CPU this regulator powers. This property is + not need when the SPM regulator is shared between all CPUs. +- qcom,bypass-spm: Boolean flag which indicates that voltage control should not + be managed by an SPM. Instead, the voltage should be + controlled via SPMI. +- qcom,max-voltage-step: Maximum single voltage step size in microvolts. +- qcom,recal-mask: Bit mask of the APSS clusters to recalibrate after each + voltage change. Bit 0 corresponds to the first cluster, + bit 1 corresponds to the second cluster, and so on. + +Optional structure: +- A child node may be specified within a qcom,spm-regulator node which defines + an additional regulator which controls the AVS minimum and maximum + voltage limits. +- The AVS child node must contain these properties defined in regulator.txt: + regulator-name, regulator-min-microvolt, regulator-max-microvolt. + +All properties specified within the core regulator framework can also be used. +These bindings can be found in regulator.txt. + +Example: + qcom,spmi@fc4c0000 { + + qcom,pm8226@1 { + spmi-slave-container; + + spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8226_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + + avs-limit-regulator { + regulator-name = "8226_s2_avs_limit"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + } + }; + }; + }; From 09b92aaeb819ede762266cb32c9be09d9c09e3b3 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 11 May 2021 14:06:14 +0530 Subject: [PATCH 1371/1809] ARM: dts: msm: Disable two_pass_use_wfi quirk for yupik GPU Disable two_pass_mode_wfi quirk for yupik GPU. Change-Id: Ia7fd2cca9e50a390b76c79f57fed51ed4ad17d54 --- qcom/yupik-gpu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c09538cf0ddc..e08835fbbb80 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -53,7 +53,6 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; - qcom,gpu-quirk-two-pass-use-wfi; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; From 604aa1a50064bf3634a60a3944150a011cd5c4d5 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Mon, 10 May 2021 22:33:33 +0530 Subject: [PATCH 1372/1809] dt-bindings: pinctrl: qcom-pmic-gpio: add PM5100 bindings Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible string for PM5100 PMIC. Change-Id: I0c4d85ced43cdf667d502c6697187ed2a4412439 --- bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index a8784580baa9..ef2ce5bf6a38 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -36,6 +36,7 @@ PMIC's from Qualcomm. "qcom,pmd9650-gpio" "qcom,pm7325-gpio" "qcom,pm7325b-gpio" + "qcom,pm5100-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -126,6 +127,7 @@ to specify in a pin configuration subnode: gpio1-gpio12 for pmd9650 gpio1-gpio10 for pm7325 gpio1-gpio8 for pm7325b + gpio1-gpio16 for pm5100 - function: Usage: required From c4a2c4d56ab51f47582a057d7a68987963fa540b Mon Sep 17 00:00:00 2001 From: Huixian Ma Date: Mon, 10 May 2021 19:25:08 +0800 Subject: [PATCH 1373/1809] ARM: dts: msm: include coresight device tree file for monaco Include the coresight device tree file in monaco.dtsi. Change-Id: Iabe19c2c51d99a1a4e987a79a9d85267d2c215e6 --- qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 42f171d9d91f..a7fb57055612 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1198,6 +1198,7 @@ }; #include "monaco-pinctrl.dtsi" +#include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" #include "monaco-stub-regulator.dtsi" From 92f06da9c3930b0e5d7405326a4e2be6ba3b30f2 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Tue, 11 May 2021 09:26:30 +0530 Subject: [PATCH 1374/1809] ARM: dts: msm: Signal aop change for PIL for BLAIR Add aop signalling property for adsp,cdsp and modem PIL nodes for Blair platform. Change-Id: I532f700d7da1ee5ba5f0da6a6375b149cbb5d266 --- qcom/blair.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 649dcf00d3b2..4ef0dd0b6c34 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2877,7 +2877,7 @@ }; }; - qcom,lpass@a400000 { + pil_lpass: qcom,lpass@a400000 { compatible = "qcom,pil-tz-generic"; reg = <0xa400000 0x00100>; @@ -2901,6 +2901,7 @@ memory-region = <&pil_adsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; + qcom,signal-aop; /* Inputs from lpass */ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, @@ -2920,7 +2921,7 @@ qcom,smem-state-names = "qcom,force-stop"; }; - qcom,turing@b000000 { + pil_turing: qcom,turing@b000000 { compatible = "qcom,pil-tz-generic"; reg = <0xb000000 0x100000>; @@ -2942,6 +2943,7 @@ memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; + qcom,signal-aop; /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, @@ -2983,7 +2985,7 @@ qcom,minidump-id = <3>; qcom,aux-minidump-ids = <4>; qcom,complete-ramdump; - + qcom,signal-aop; /* Inputs from mss */ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, From 41e32ca034f0dfa8ecae068441e1a04746099bd3 Mon Sep 17 00:00:00 2001 From: donghe Date: Fri, 30 Apr 2021 17:34:03 +0530 Subject: [PATCH 1375/1809] ARM: dts: msm: include camera devicetree for sa6155 Added camera devicetree for sa6155 target. Change-Id: Ic7518a178af9b24b493ec85a7e6eaaac83f206fa --- qcom/sa6155-pmic.dtsi | 27 +++++++++++++++++++++++++++ qcom/sa6155p.dtsi | 2 ++ qcom/sm6150.dtsi | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index dee41906a9dc..657911c25b6f 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -39,6 +39,33 @@ /delete-node/ rpmh-regulator-bobc1; }; +&cam_csiphy0 { + mipi-csi-vdd-supply = <&pm6155_1_l11>; + regulator-names = "gdscr", "mipi-csi-vdd"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1232000>; + rgltr-max-voltage = <0 1232000>; + rgltr-load-current = <0 21800>; +}; + +&cam_csiphy1 { + mipi-csi-vdd-supply = <&pm6155_1_l11>; + regulator-names = "gdscr", "mipi-csi-vdd"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1232000>; + rgltr-max-voltage = <0 1232000>; + rgltr-load-current = <0 21800>; +}; + +&cam_csiphy2 { + mipi-csi-vdd-supply = <&pm6155_1_l11>; + regulator-names = "gdscr", "mipi-csi-vdd"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1232000>; + rgltr-max-voltage = <0 1232000>; + rgltr-load-current = <0 21800>; +}; + &soc { qcom,lpass@62400000 { vdd_cx-supply = <&VDD_CX_LEVEL>; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index cdb73870c1fc..50bc8ca55ca6 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -1,5 +1,7 @@ #include "sm6150.dtsi" #include "sa6155-pmic.dtsi" +#include "camera/sa6155p-camera.dtsi" +#include "camera/sa6155p-camera-sensor.dtsi" #include "display/sa6155-display.dtsi" / { diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 9691fa618cc1..b24123c1660f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2440,6 +2440,11 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; + + cx_ipeak_lm: cx_ipeak@01fed000 { + compatible = "qcom,cx-ipeak-v1"; + reg = <0x1fed000 0x28>; + }; }; &firmware { @@ -2564,3 +2569,4 @@ #include "sm6150-vidc.dtsi" #include "sm6150-ion.dtsi" #include "sm6150-thermal.dtsi" +#include "camera/sm6150-camera.dtsi" From c739cbfa40f5653539aff1bb3d1992bd5768d266 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Tue, 11 May 2021 16:36:21 +0530 Subject: [PATCH 1376/1809] ARM: dts: msm: Add icnss regulator for holi-pm6125 Add icnss regulators for holi-pm6125. Change-Id: I257a8d46e42fbe67c418f86bd1783d9796f43c96 --- qcom/holi-pm6125-overlay.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 74c9102a0c75..13169520db90 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -3,3 +3,16 @@ &mdss_dsi_phy0 { vdda-0p9-supply = <&S6A>; }; + +&soc { + icnss: qcom,icnss@C800000 { + vdd-cx-mx-supply = <&L2E>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L2A>; + vdd-3.3-ch1-supply = <&L21A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + }; +}; From 808b14362bcc435c4a5067c1031f71aec2fdc312 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Tue, 20 Apr 2021 17:10:31 +0530 Subject: [PATCH 1377/1809] ARM: dts: msm: include display nodes for pm6125 platform of Holi target This change includes display platform specific nodes in the corresponding platform DT files for Holi target. Change-Id: I08ac12aace683e2a1970d7535e8424759f130610 --- qcom/holi-cdp-pm6125.dtsi | 1 + qcom/holi-mtp-pm6125.dtsi | 1 + qcom/holi-mtp-usbc-pm6125.dtsi | 1 + qcom/holi-pm6125-overlay.dtsi | 7 +++++-- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index c9395ba292bf..f0d87d4c7ee2 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "display/holi-sde-display-cdp-pm6125.dtsi" #include /* Dummy LDO reference */ diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d4f26c106212..f260d8d0a7a5 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "display/holi-sde-display-mtp-pm6125.dtsi" #include /* Dummy LDO reference */ diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index f689c43b7f8d..ab7b473d8565 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "display/holi-sde-display-mtp-pm6125.dtsi" #include /* Dummy LDO reference */ diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 74c9102a0c75..abffd58d3890 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -1,5 +1,8 @@ -/* Dummy LDO referenses */ &mdss_dsi_phy0 { - vdda-0p9-supply = <&S6A>; + vdda-0p9-supply = <&S1E_LEVEL>; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4A>; }; From 3164eaaacb420e9f9b01995426b18d25e640475e Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Wed, 5 May 2021 16:51:43 +0530 Subject: [PATCH 1378/1809] ARM: dts: msm: include touch nodes for rm69299 panel on Holi target This change includes touch node of rm69299 amoled panel for Holi target. Change-Id: I81ce70741fdd9d4aa07111b53d64eafe54a9283f --- qcom/holi-cdp-lcd-pm6125.dtsi | 6 +++--- qcom/holi-cdp-pm6125.dtsi | 39 +++++++++++++++++++++++++++++++--- qcom/holi-mtp-pm6125.dtsi | 37 ++++++++++++++++++++++++++++++-- qcom/holi-mtp-usbc-pm6125.dtsi | 37 ++++++++++++++++++++++++++++++-- 4 files changed, 109 insertions(+), 10 deletions(-) diff --git a/qcom/holi-cdp-lcd-pm6125.dtsi b/qcom/holi-cdp-lcd-pm6125.dtsi index c486e4d2d4a8..dda626b9d06c 100644 --- a/qcom/holi-cdp-lcd-pm6125.dtsi +++ b/qcom/holi-cdp-lcd-pm6125.dtsi @@ -8,10 +8,10 @@ reg = <0x22>; interrupt-parent = <&tlmm>; interrupts = <39 0x2008>; - vdd-supply = <&L11A>; - avdd-supply = <&L6A>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", - "pmx_ts_release"; + "pmx_ts_release"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index f0d87d4c7ee2..890aeb09a861 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -204,6 +204,36 @@ qcom,cl-feedback-on; }; +&tlmm { + touch_avdd_default: touch_avdd_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd { + compatible = "regulator-fixed"; + regulator-name = "touch_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 53 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&touch_avdd_default>; + }; +}; + &qupv3_se8_i2c { status = "okay"; qcom,i2c-touch-active="synaptics,tcm-i2c"; @@ -218,8 +248,8 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - vdd-supply = <&L11A>; - avdd-supply = <&L6A>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; synaptics,pwr-reg-name = "avdd"; synaptics,bus-reg-name = "vdd"; synaptics,irq-gpio = <&tlmm 22 0x2008>; @@ -232,6 +262,9 @@ synaptics,ubl-i2c-addr = <0x20>; synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; focaltech@38 { @@ -244,7 +277,7 @@ focaltech,max-touch-number = <5>; focaltech,display-coords = <0 0 1080 2340>; - vdd-supply = <&L6A>; + vdd-supply = <&touch_avdd>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index f260d8d0a7a5..3d2b5ee3c29f 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -129,6 +129,36 @@ }; }; +&tlmm { + touch_avdd_default: touch_avdd_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd { + compatible = "regulator-fixed"; + regulator-name = "touch_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 53 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&touch_avdd_default>; + }; +}; + &qupv3_se8_i2c { status = "okay"; qcom,i2c-touch-active="synaptics,tcm-i2c"; @@ -143,8 +173,8 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - vdd-supply = <&L11A>; - avdd-supply = <&L6A>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; synaptics,pwr-reg-name = "avdd"; synaptics,bus-reg-name = "vdd"; synaptics,irq-gpio = <&tlmm 22 0x2008>; @@ -157,6 +187,9 @@ synaptics,ubl-i2c-addr = <0x20>; synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; }; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index ab7b473d8565..0d6bc2019dca 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -148,6 +148,36 @@ }; }; +&tlmm { + touch_avdd_default: touch_avdd_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd { + compatible = "regulator-fixed"; + regulator-name = "touch_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 53 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&touch_avdd_default>; + }; +}; + &qupv3_se8_i2c { status = "okay"; qcom,i2c-touch-active="synaptics,tcm-i2c"; @@ -162,8 +192,8 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - vdd-supply = <&L11A>; - avdd-supply = <&L6A>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; synaptics,pwr-reg-name = "avdd"; synaptics,bus-reg-name = "vdd"; synaptics,irq-gpio = <&tlmm 22 0x2008>; @@ -176,6 +206,9 @@ synaptics,ubl-i2c-addr = <0x20>; synaptics,extend_report; synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; }; }; From e9e24617b1ff7abfa588d642a0a7fd0aaa25863a Mon Sep 17 00:00:00 2001 From: Piyush Dhyani Date: Tue, 20 Apr 2021 04:02:35 +0530 Subject: [PATCH 1379/1809] ARM: dts: msm: Add entry to configure modem tput ep Add Entry to support modem tput ep configuration. Change-Id: I6f525703a5b73ea255c52fc05ad9a835a12de5c6 --- bindings/platform/msm/ipa.txt | 3 +++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 0fe273044913..a39d3d334f1e 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -197,6 +197,9 @@ IPA SMMU sub nodes - qcom,additional-mapping: specifies any addtional mapping needed for this context bank. The format is +- qcom,use-tput-estmation-pipe: Indicates if configuring modem throughput + estmation pipe or not. + IPA SMP2P sub nodes -compatible: "qcom,smp2p-map-ipa-1-out" - represents the out smp2p from diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 354ea08b3172..68e625c2e099 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1181,6 +1181,7 @@ qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; qcom,use-ipa-tethering-bridge; + qcom,use-tput-estmation-pipe; qcom,mhi-event-ring-id-limits = <9 15>; /* start and end */ qcom,modem-cfg-emb-pipe-flt; qcom,use-xbl-boot; From b251a7a37404e68fb632a384a7bb4faacf1858b0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 19 Oct 2020 14:08:17 +0530 Subject: [PATCH 1380/1809] ARM: dts: msm: Add UFS support for direwolf Add UFS host controller and UFS PHY (attached to embedded UFS card) for direwolf platform. Change-Id: I0f2858f6bef5a275d362cec3909a13a70cdfd14b --- qcom/direwolf-adp-common.dtsi | 28 +++++++ qcom/direwolf.dtsi | 137 +++++++++++++++++++++++++++++++++- 2 files changed, 164 insertions(+), 1 deletion(-) diff --git a/qcom/direwolf-adp-common.dtsi b/qcom/direwolf-adp-common.dtsi index 23df450781cf..393f11c54700 100644 --- a/qcom/direwolf-adp-common.dtsi +++ b/qcom/direwolf-adp-common.dtsi @@ -1,3 +1,31 @@ &soc { }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + + vdda-phy-supply = <&L8G0>; + vdda-pll-supply = <&L3G0>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L17C0>; + vcc-voltage-level = <2504000 2504000>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L6C0>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L6C0>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 0d5e78727299..98ff935a1075 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -28,7 +28,9 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; - aliases { }; + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + }; cpus { #address-cells = <2>; @@ -906,6 +908,139 @@ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + rpm-level = <3>; + spm-level = <5>; + + status = "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, From 514e0cad5d4045b0890d50f2b71216e8f3fdaebc Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Tue, 4 May 2021 20:17:52 +0530 Subject: [PATCH 1381/1809] ARM: dts: msm: Include camera sensor dtsi for holi pro Include camera sensor dtsi for holi pro camera on MTP, CDP platforms. External Impact: No CRs-Fixed: 2938922 Change-Id: If3ae8e8272aec66b96bcdbe835fb6af8ed0bfa5a --- qcom/holi-cdp-pm6125.dtsi | 3 +++ qcom/holi-mtp-pm6125.dtsi | 3 +++ qcom/holi-mtp-usbc-pm6125.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index c9395ba292bf..402a86c8ef26 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include +#include "camera/holi-camera-pm6125-overlay.dtsi" /* Dummy LDO reference */ &wcd938x_codec { @@ -253,6 +254,8 @@ }; }; +#include "camera/holi-camera-sensor-pm6125-cdp.dtsi" + &pm7250b_charger { dpdm-supply = <&qusb_phy0>; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d4f26c106212..84cf81e9b222 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include +#include "camera/holi-camera-pm6125-overlay.dtsi" /* Dummy LDO reference */ &wcd938x_codec { @@ -323,6 +324,8 @@ status = "ok"; }; +#include "camera/holi-camera-sensor-pm6125-mtp.dtsi" + &pm7250b_charger { dpdm-supply = <&qusb_phy0>; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index f689c43b7f8d..2c9e2a57e810 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include +#include "camera/holi-camera-pm6125-overlay.dtsi" /* Dummy LDO reference */ &wcd938x_codec { @@ -288,6 +289,8 @@ qcom,use-cp-iin-sns; }; +#include "camera/holi-camera-sensor-usbc-pm6125-mtp.dtsi" + &pm7250b_charger { dpdm-supply = <&qusb_phy0>; From 92d2d6418403615d932bc01bef88b1d8b92f3fce Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 12 May 2021 12:10:05 +0530 Subject: [PATCH 1382/1809] ARM: dts: msm: Enable Secure buffer for monaco . Enable secure buffer for monaco. . Set KGSL PF + 15. Change-Id: I2ce7dac2c811f3e28a3519b3f205fbaa05494c4d --- qcom/monaco.dtsi | 4 ++++ qcom/msm-arm-smmu-monaco.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index c254e4862da7..ae4b42190f3f 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1224,6 +1224,10 @@ interrupt-parent = <&intc>; #interrupt-cells = <2>; }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; }; #include "pm5100.dtsi" diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index c9e6c47f03df..62381dae063b 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -37,7 +37,7 @@ qcom,actlr = /* ALL CBs of GFX: +15 deep PF */ - <0x0 0x3ff 0x30B>; + <0x0 0x3ff 0x32B>; gfx_0_tbu: gfx_0_tbu@0x59dd000 { compatible = "qcom,qsmmuv500-tbu"; From 9fca5fc2bb432867e802a2cce2e6d3fcf55c0cee Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 12 May 2021 15:29:46 +0800 Subject: [PATCH 1383/1809] ARM: dts: msm: Add initial platform device tree for blair QRD Add initial device tree to support blair platform on QRD platforms. Change-Id: I6ee35c90f92f3d809a0475dcdab56305813ad405 --- bindings/arm/msm/msm.txt | 1 + qcom/Makefile | 8 +++++--- qcom/blair-qrd-overlay.dts | 12 ++++++++++++ qcom/blair-qrd.dts | 11 +++++++++++ qcom/blair-qrd.dtsi | 2 ++ 5 files changed, 31 insertions(+), 3 deletions(-) create mode 100644 qcom/blair-qrd-overlay.dts create mode 100644 qcom/blair-qrd.dts create mode 100644 qcom/blair-qrd.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index e993afb45b1f..14dff6f58505 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -295,6 +295,7 @@ compatible = "qcom,blair-rumi" compatible = "qcom,blair-mtp" compatible = "qcom,blair-cdp" compatible = "qcom,blair-atp" +compatible = "qcom,blair-qrd" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" compatible = "qcom,monaco" diff --git a/qcom/Makefile b/qcom/Makefile index c82309013266..78774253c9b2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -123,18 +123,20 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo \ blair-mtp-overlay.dtbo \ blair-cdp-overlay.dtbo \ - blair-atp-overlay.dtbo + blair-atp-overlay.dtbo \ + blair-qrd-overlay.dtbo blair-rumi-overlay.dtbo-base := blair.dtb blair-mtp-overlay.dtbo-base := blair.dtb blair-cdp-overlay.dtbo-base := blair.dtb blair-atp-overlay.dtbo-base := blair.dtb - +blair-qrd-overlay.dtbo-base := blair.dtb else dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ blair-mtp.dtb \ blair-cdp.dtb \ - blair-atp.dtb + blair-atp.dtb \ + blair-qrd.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/blair-qrd-overlay.dts b/qcom/blair-qrd-overlay.dts new file mode 100644 index 000000000000..02e5c787ddae --- /dev/null +++ b/qcom/blair-qrd-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair QRD"; + compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/blair-qrd.dts b/qcom/blair-qrd.dts new file mode 100644 index 000000000000..b0bc35a9f0bb --- /dev/null +++ b/qcom/blair-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair QRD"; + compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-qrd.dtsi @@ -0,0 +1,2 @@ +/ { +}; From ae4b1d19aae976cd1d0c01659f48a2f547630a8f Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Thu, 6 May 2021 15:25:38 +0530 Subject: [PATCH 1384/1809] ARM: dts: msm: Add correct LDO reference for NFC LDO voting Modified code to add correct LDO reference for NFC LDO voting to align with PM6125. Change-Id: I98b211f73ac080fec777f740c52bee1774487d99 --- qcom/holi-cdp-pm6125.dtsi | 2 +- qcom/holi-mtp-pm6125.dtsi | 2 +- qcom/holi-mtp-usbc-pm6125.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index c9395ba292bf..2648126ab288 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -89,7 +89,7 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; - qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-supply = <&L9A>; qcom,sn-vdd-1p8-voltage = <1800000 1800000>; qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d4f26c106212..75cc3e0a412c 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -89,7 +89,7 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; - qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-supply = <&L9A>; qcom,sn-vdd-1p8-voltage = <1800000 1800000>; qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index f689c43b7f8d..99d15d9ebc7c 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -89,7 +89,7 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; - qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-supply = <&L9A>; qcom,sn-vdd-1p8-voltage = <1800000 1800000>; qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; From 10b5a85ff4f8d508ed3f08a291453db05b7f3e74 Mon Sep 17 00:00:00 2001 From: Munnuru Srikanth Date: Wed, 12 May 2021 11:02:15 +0530 Subject: [PATCH 1385/1809] ARM: dts: msm: Add mproc node for slate Add glink slatecom dtsi node. Change-Id: Ib60df24d8ee93d5c565ef672fc832a1871378b76 --- qcom/slate.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index d9bca13c4fdd..978c0a221d6f 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -9,4 +9,9 @@ qcom,irq-gpio = <&tlmm 95 1>; }; }; + + qcom,glink-slatecom-xprt-slate { + compatible = "qcom,glink-slatecom-xprt"; + label = "slate"; + }; }; From feac5944b2ce660b649d7b0087f0e87b04317908 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 11 May 2021 19:23:02 +0530 Subject: [PATCH 1386/1809] ARM: dts: msm: Update silver core mitigation for YUPIK Update silver core mitigation in yupik to ensure minimum operating performance. Change-Id: If08c6f462a5344739d0f572f266d2306e7080510 --- qcom/yupik-thermal-overlay-qrd.dtsi | 15 --------------- qcom/yupik-thermal-overlay.dtsi | 15 --------------- 2 files changed, 30 deletions(-) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 1b35cdcf63e9..a6f3e0b09b45 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -201,21 +201,6 @@ THERMAL_MAX_LIMIT>; }; - pm7325_cpu1 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm7325_cpu2 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm7325_cpu3 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm7325_cpu4 { trip = <&pm7325_trip0>; cooling-device = <&cpu4_isolate 1 1>; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 08629122a0e4..03a8f6dbdd25 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -201,21 +201,6 @@ THERMAL_MAX_LIMIT>; }; - pm7325_cpu1 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm7325_cpu2 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm7325_cpu3 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm7325_cpu4 { trip = <&pm7325_trip0>; cooling-device = <&cpu4_isolate 1 1>; From f994d4ec89b4ff471d7bdadd1e67b27ab9ccfcca Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 12 May 2021 17:46:37 +0530 Subject: [PATCH 1387/1809] ARM: dts: msm: Add modem mmw_skin mitigation config for HOLI Add modem mmw_pa sensor based thermal config with mmw_skin aas mitigation devices and update pa_therm skin sensor thresholds based on latest recommondation. Change-Id: Ia725ec716056ba1a4f1ac2d4e7582a590ddab194 --- qcom/holi-qrd.dtsi | 2 +- qcom/holi-thermal-modem.dtsi | 183 ++++++++++++++++++++++++++++++++++- 2 files changed, 181 insertions(+), 4 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index ede97e819b69..7e7dea95bc4f 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -487,7 +487,7 @@ }; modem_trip2: modem-trip2 { - temperature = <56000>; + temperature = <54000>; hysteresis = <4000>; type = "passive"; }; diff --git a/qcom/holi-thermal-modem.dtsi b/qcom/holi-thermal-modem.dtsi index c0a9ba602c1d..2cd31c0a383b 100644 --- a/qcom/holi-thermal-modem.dtsi +++ b/qcom/holi-thermal-modem.dtsi @@ -133,15 +133,147 @@ "beamer_w_therm", "qfe_ret_pa0_fr1", "qfe_wtr_pa0_fr1", - "qfe_wtr_pa1_fr1", - "qfe_wtr_pa2_fr1", - "qfe_wtr_pa3_fr1", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", "qfe_wtr0_fr1"; }; }; }; &thermal_zones { + modem-mmw-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + mmw_pa1_trip0: mmw-pa1-trip0 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip1: mmw-pa1-trip1 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip2: mmw-pa1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin0_cdev0 { + trip = <&mmw_pa1_trip0>; + cooling-device = <&modem_mmw_skin0 1 1>; + }; + + mmw_skin0_cdev1 { + trip = <&mmw_pa1_trip1>; + cooling-device = <&modem_mmw_skin0 2 2>; + }; + + mmw_skin0_cdev2 { + trip = <&mmw_pa1_trip2>; + cooling-device = <&modem_mmw_skin0 3 3>; + }; + }; + }; + + modem-mmw-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + mmw_pa2_trip0: mmw-pa2-trip0 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip1: mmw-pa2-trip1 { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip2: mmw-pa2-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin1_cdev0 { + trip = <&mmw_pa2_trip0>; + cooling-device = <&modem_mmw_skin1 1 1>; + }; + + mmw_skin1_cdev1 { + trip = <&mmw_pa2_trip1>; + cooling-device = <&modem_mmw_skin1 2 2>; + }; + + mmw_skin1_cdev2 { + trip = <&mmw_pa2_trip2>; + cooling-device = <&modem_mmw_skin1 3 3>; + }; + }; + }; + + modem-mmw-pa3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + mmw_pa3_trip0: mmw-pa3-trip0 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip1: mmw-pa3-trip1 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip2: mmw-pa3-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin2_cdev0 { + trip = <&mmw_pa3_trip0>; + cooling-device = <&modem_mmw_skin2 1 1>; + }; + + mmw_skin2_cdev1 { + trip = <&mmw_pa3_trip1>; + cooling-device = <&modem_mmw_skin2 2 2>; + }; + + mmw_skin2_cdev2 { + trip = <&mmw_pa3_trip2>; + cooling-device = <&modem_mmw_skin2 3 3>; + }; + }; + }; + modem-lte-sub6-pa1 { polling-delay-passive = <0>; polling-delay = <0>; @@ -396,4 +528,49 @@ }; }; }; + + modem-mmw-pa1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw-pa2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw-pa3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; From d4fe9282ddaf8d47559220769e378ce95eec79b8 Mon Sep 17 00:00:00 2001 From: Dundi Raviteja Date: Mon, 3 May 2021 14:57:46 +0530 Subject: [PATCH 1388/1809] ARM: dts: msm: Move icnss driver to soc node icnss driver should present in soc node, so moving icnss driver to soc node. Change-Id: I57129363c732b069bc0c39ca8ab58cbd1c166df4 CRs-Fixed: 2937253 --- qcom/scuba-iot.dtsi | 73 ++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index b60a58d63561..0c3a88a00323 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1029,6 +1029,42 @@ dcc: dcc_v2@1be2000 { qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1A0 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + vdd-cx-mx-supply = <&L7A>; + vdd-1.8-xo-supply = <&L13A>; + vdd-1.3-rfa-supply = <&L10A>; + vdd-3.3-ch0-supply = <&L22A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; }; #include "pm2250.dtsi" @@ -1202,43 +1238,6 @@ dcc: dcc_v2@1be2000 { qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; - - - icnss: qcom,icnss@C800000 { - compatible = "qcom,icnss"; - reg = <0xC800000 0x800000>, - <0xb0000000 0x10000>; - reg-names = "membase", "smmu_iova_ipa"; - iommus = <&apps_smmu 0x1A0 0x1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - qcom,iommu-dma = "fastmap"; - qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; - qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; - qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; - vdd-cx-mx-supply = <&L7A>; - vdd-1.8-xo-supply = <&L13A>; - vdd-1.3-rfa-supply = <&L10A>; - vdd-3.3-ch0-supply = <&L22A>; - qcom,vdd-cx-mx-config = <640000 640000>; - qcom,vdd-3.3-ch0-config = <3000000 3312000>; - qcom,smp2p_map_wlan_1_in { - interrupts-extended = <&smp2p_wlan_1_in 0 0>, - <&smp2p_wlan_1_in 1 0>; - interrupt-names = "qcom,smp2p-force-fatal-error", - "qcom,smp2p-early-crash-ind"; - }; - }; }; &pm2250_gpios { From 20e88cedd3306a132192872f0412c392260a16ce Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Fri, 23 Apr 2021 21:59:36 +0530 Subject: [PATCH 1389/1809] ARM: dts: msm: Add GPU properties for Blair Add chip id and update GPU power levels for blair GPU. Change-Id: I14a4995dcd178df1ff91257a1b93e809dd6ed5e2 --- qcom/blair.dtsi | 276 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 276 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 649dcf00d3b2..966ef3be14f5 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3438,4 +3438,280 @@ status = "ok"; }; +&msm_gpu { + qcom,chipid = <0x06010901>; + + /delete-node/qcom,gpu-pwrlevel-bins; + + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz (round up to zero + * decimal places) + 2. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <0>; + qcom,ca-target-pwrlevel = <5>; + qcom,initial-pwrlevel = <6>; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <9>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <5>; + qcom,bus-min-ddr7 = <4>; + qcom,bus-max-ddr7 = <7>; + + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <390000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7= <5>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <266000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <4>; + }; + + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <190>; + qcom,ca-target-pwrlevel = <5>; + qcom,initial-pwrlevel = <6>; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <9>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <5>; + qcom,bus-min-ddr7 = <4>; + qcom,bus-max-ddr7 = <7>; + + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <390000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7= <5>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <266000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <4>; + }; + + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <177>; + qcom,ca-target-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <5>; + qcom,bus-min-ddr7 = <4>; + qcom,bus-max-ddr7 = <7>; + + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <390000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7= <5>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <266000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <4>; + }; + }; + }; +}; + #include "msm-rdbg.dtsi" From 9ce554010e6e654f52e0f5e36b136a36bc9e56f1 Mon Sep 17 00:00:00 2001 From: Chaitanya Pratapa Date: Wed, 12 May 2021 15:49:23 -0700 Subject: [PATCH 1390/1809] ARM: dts: msm: add wdi scaling exceptions For WLAN LAN-LAN use cases, there won't be any other peripheral vote and IPA vote will not scale correctly. Make changes to add scaling exceptions to vote correctly for WLAN standalone cases. Also increase number of buffers on LAN_CONS pipe to 224 to reduce backpressure towards WLAN. Change-Id: Ia2dd50642228ec825d9d18a910e9a7b132ca23f8 --- qcom/lahaina.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 10768627ee74..c940fa425421 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4653,6 +4653,7 @@ qcom,use-64-bit-dma-mask; qcom,ipa-endp-delay-wa; qcom,lan-rx-napi; + qcom,lan-rx-ring-size = <224>; qcom,tx-napi; qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; @@ -4695,7 +4696,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,throughput-threshold = <600 2500 5000>; - qcom,scaling-exceptions = <>; + qcom,scaling-exceptions = "wdi", "100", "600", "1200"; /* smp2p information */ qcom,smp2p_map_ipa_1_out { From dc237cf8878993b94d357f3fd59db05862f13798 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Wed, 12 May 2021 17:10:51 +0530 Subject: [PATCH 1391/1809] ARM: dts: qcom: update mapping table for dcvvs nodes in blair target Update mapping table for memlat and compute dcvs nodes used for L3 and DDR frequency scaling for blair target. Change-Id: Ieba82318e7b7a4938285fcba3272f2afc7140715 --- qcom/blair.dtsi | 59 ++++++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 4ef0dd0b6c34..c5d6368b1169 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1434,27 +1434,27 @@ cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { qcom,core-dev-table = - < 710400 300000000 >, - < 940800 518400000 >, - < 1190400 748800000 >, - < 1478400 921600000 >, - < 1574400 1305600000 >, - < 1804800 1459000000 >; + < 691200 300000000 >, + < 940800 556800000 >, + < 1113600 768000000 >, + < 1516800 921600000 >, + < 1651200 1382400000 >, + < 1804800 1497600000 >; }; cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { qcom,core-dev-table = - < 1017600 518400000 >, - < 1248000 748800000 >, - < 1536000 921600000 >, + < 940800 556800000 >, + < 1228800 768000000 >, + < 1516800 921600000 >, < 1651200 1171200000 >, - < 1804800 1305600000 >, - < 2035200 1459000000 >; + < 1900800 1382400000 >, + < 2054400 1497600000 >; }; - cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + cpu_memlat_cpugrp: qcom,cpu-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; @@ -1510,10 +1510,10 @@ qcom,target-dev = <&cpu0_cpu_ddr_lat>; qcom,cachemiss-ev = <0x2A>; qcom,core-dev-table = - < 710400 MHZ_TO_MBPS( 300, 4) >, + < 691200 MHZ_TO_MBPS( 300, 4) >, < 940800 MHZ_TO_MBPS( 451, 4) >, - < 1190400 MHZ_TO_MBPS( 547, 4) >, - < 1478400 MHZ_TO_MBPS( 768, 4) >, + < 1113600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, < 1804800 MHZ_TO_MBPS( 1017, 4) >; }; @@ -1521,16 +1521,11 @@ compatible = "qcom,arm-compute-mon"; qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; qcom,core-dev-table = - < 710400 MHZ_TO_MBPS( 300, 4) >, - < 1190400 MHZ_TO_MBPS( 451, 4) >, - < 1478400 MHZ_TO_MBPS( 547, 4) >, + < 691200 MHZ_TO_MBPS( 300, 4) >, + < 1113600 MHZ_TO_MBPS( 451, 4) >, + < 1516800 MHZ_TO_MBPS( 547, 4) >, < 1804800 MHZ_TO_MBPS( 768, 4) >; }; - }; - - cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { - compatible = "qcom,arm-memlat-cpugrp"; - qcom,cpulist = <&CPU6 &CPU7>; cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; @@ -1558,11 +1553,11 @@ qcom,target-dev = <&cpu6_cpu_ddr_lat>; qcom,cachemiss-ev = <0x2A>; qcom,core-dev-table = - < 1017600 MHZ_TO_MBPS( 547, 4) >, - < 1248000 MHZ_TO_MBPS(1017, 4) >, - < 1536000 MHZ_TO_MBPS(1555, 4) >, - < 1804800 MHZ_TO_MBPS(1804, 4) >, - < 2035200 MHZ_TO_MBPS(2092, 4) >; + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS(1017, 4) >, + < 1516800 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1804, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; }; cpu6_computemon: qcom,cpu6-computemon { @@ -1571,10 +1566,10 @@ qcom,core-dev-table = < 1248800 MHZ_TO_MBPS( 547, 4) >, < 1401600 MHZ_TO_MBPS( 768, 4) >, - < 1536000 MHZ_TO_MBPS(1017, 4) >, + < 1516800 MHZ_TO_MBPS(1017, 4) >, < 1651200 MHZ_TO_MBPS(1555, 4) >, - < 1804800 MHZ_TO_MBPS(1804, 4) >, - < 2035200 MHZ_TO_MBPS(2092, 4) >; + < 1900800 MHZ_TO_MBPS(1804, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; }; }; From 06b49539333e00ae80cbfa5828b3c89c30988333 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 26 Apr 2021 23:16:03 +0530 Subject: [PATCH 1392/1809] ARM: dts: msm: add MHI register space info for PCIe on SM8150 Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SM8150. Change-Id: Ic16e20be3224ba2cdff337e72d9907b6bbbb2d1e --- qcom/sm8150-pcie.dtsi | 12 ++++++++---- qcom/sm8150-v2.dtsi | 6 ++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/qcom/sm8150-pcie.dtsi b/qcom/sm8150-pcie.dtsi index 367c832e495b..204f8a90c28a 100644 --- a/qcom/sm8150-pcie.dtsi +++ b/qcom/sm8150-pcie.dtsi @@ -12,10 +12,12 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c06000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -282,10 +284,12 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0e000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 89f7cf5c1bfc..cf27fe93f154 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -50,7 +50,8 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c03000 0x1000>; qcom,pcie-phy-ver = <2110>; @@ -160,7 +161,8 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0b000 0x1000>; qcom,pcie-phy-ver = <2109>; From a3df1c9115b513f13d3e5d52ca145a2dee4a2d14 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 26 Apr 2021 23:36:20 +0530 Subject: [PATCH 1393/1809] ARM: dts: msm: add MHI register space info for PCIe on SA8195 Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SA8195. Change-Id: I2633a8be063dd10fe5128ae51d532cd5969f3bc3 --- qcom/sa8195p-pcie.dtsi | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi index c48ae1e75bc7..6b6e6575c891 100644 --- a/qcom/sa8195p-pcie.dtsi +++ b/qcom/sa8195p-pcie.dtsi @@ -12,10 +12,12 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c03000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -282,10 +284,12 @@ <0x68100000 0x100000>, <0x68200000 0x100000>, <0x68300000 0x3d00000>, - <0x01fec004 0x4>; + <0x01fec004 0x4>, + <0x01c13000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars", "tcsr"; + "iatu", "conf", "io", "bars", "tcsr", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -590,10 +594,12 @@ <0x70100000 0x100000>, <0x70200000 0x100000>, <0x70300000 0x3d00000>, - <0x01fec004 0x4>; + <0x01fec004 0x4>, + <0x01c1b000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars", "tcsr"; + "iatu", "conf", "io", "bars", "tcsr", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -897,10 +903,12 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0b000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; From f37837e5474db91fe5a2a1f105be80b9ddba4813 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 26 Apr 2021 23:47:11 +0530 Subject: [PATCH 1394/1809] ARM: dts: msm: add MHI register space info for PCIe on SA6155 Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SA6155. Change-Id: I17e6211165963e0ebdd170f2201cd7424e037fd1 --- qcom/sa6155-pcie.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sa6155-pcie.dtsi b/qcom/sa6155-pcie.dtsi index 67b8b1a46562..42b9a8cc20a1 100644 --- a/qcom/sa6155-pcie.dtsi +++ b/qcom/sa6155-pcie.dtsi @@ -12,10 +12,12 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0b000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; From e46071c4832686063dbe58b806578924ac3e1df8 Mon Sep 17 00:00:00 2001 From: Aniket Arandive Date: Mon, 3 May 2021 12:13:58 +0530 Subject: [PATCH 1395/1809] ARM: dts: msm: Update the QMP UNIPHY init sequence for SM8150 Update the phy register value for the secondary usb controller on SM8150. Change-Id: I5288b0fdf1fd4a88b6fd90f94ba156aeb6255c39 --- qcom/sm8150-usb.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 347a8db118aa..798b5175c1c4 100644 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -272,7 +272,7 @@ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0 USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0 @@ -286,7 +286,7 @@ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0 USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 @@ -301,9 +301,10 @@ USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0 USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0 - USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0 USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0 USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0 USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 From 262c9020bf4222f0f6dbbbbbcbeb2c352afaff50 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Tue, 6 Apr 2021 10:24:29 +0530 Subject: [PATCH 1396/1809] ARM: dts: msm: Add support for QUPv3 dtsi Here er are adding the main dtsi file and enabling the UART node. Change-Id: I22a7c92785b1fb14eefe1cc84155b454c1ff874a --- qcom/direwolf.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 98ff935a1075..3d065368f299 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -30,6 +30,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + serial0 = &qupv3_se17_2uart; + hsuart0 = &qupv3_se2_4uart; }; cpus { @@ -1629,6 +1631,7 @@ #include "direwolf-gdsc.dtsi" #include "direwolf-ion.dtsi" #include "msm-arm-smmu-direwolf.dtsi" +#include "direwolf-qupv3.dtsi" &gcc_emac0_gdsc { status = "ok"; @@ -1725,3 +1728,7 @@ &hlos1_vote_turing_mmu_tbu3_gdsc { status = "ok"; }; + +&qupv3_se17_2uart { + status = "ok"; +}; From bc930a5963a09b1e224c9c28197edf9d3c6d34ae Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Thu, 29 Apr 2021 17:11:52 +0530 Subject: [PATCH 1397/1809] ARM: dts: msm: Add primary and secondary USB nodes on Direwolf Add primary and secondary USB nodes on Direwolf. Limit the max speed to high-Speed for initial bringup. Change-Id: I819bb76c6bf46934ab1a01c0a5e47390676890c7 --- qcom/direwolf-usb.dtsi | 188 +++++++++++++++++++++++++++++++++++++++++ qcom/direwolf.dtsi | 1 + 2 files changed, 189 insertions(+) create mode 100644 qcom/direwolf-usb.dtsi diff --git a/qcom/direwolf-usb.dtsi b/qcom/direwolf-usb.dtsi new file mode 100644 index 000000000000..4d1050e9ccfb --- /dev/null +++ b/qcom/direwolf-usb.dtsi @@ -0,0 +1,188 @@ +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0820 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "noc_aggr_clk", + "noc_aggr_north_clk", "noc_aggr_south_clk", + "noc_sys_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e5000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e5000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L5A0>; + vdda18-supply = <&L7A0>; + vdda33-supply = <&L13A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = + <0xe6 0x6c /* override_x0 */ + 0x0b 0x70 /* override_x1 */ + 0x17 0x74>; /* override x2 */ + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0860 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "noc_aggr_clk", + "noc_aggr_north_clk", "noc_aggr_south_clk", + "noc_sys_clk"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,default-mode-host; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xd93c>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@8902000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x8902000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L1C0>; + vdda18-supply = <&L7C0>; + vdda33-supply = <&L2C0>; + qcom,vdd-voltage-level = <0 912000 912000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = + <0xe6 0x6c /* override_x0 */ + 0x0b 0x70 /* override_x1 */ + 0x17 0x74>; /* override x2 */ + }; + +}; + diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 3d065368f299..3f91d001c6bf 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1632,6 +1632,7 @@ #include "direwolf-ion.dtsi" #include "msm-arm-smmu-direwolf.dtsi" #include "direwolf-qupv3.dtsi" +#include "direwolf-usb.dtsi" &gcc_emac0_gdsc { status = "ok"; From ac3719b7101728e9f1287a2c62c29cbb726c3e09 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 6 May 2021 18:02:47 +0530 Subject: [PATCH 1398/1809] ARM: dts: msm: Add UFS regulators for holi-pm6125 This change add support for UFS regulators for holi-pm6125 according to the new powergrid. Change-Id: Iaf1e06170f11aee011690d33a970fdf743781840 --- qcom/holi-cdp-pm6125.dtsi | 10 +++++----- qcom/holi-mtp-pm6125.dtsi | 10 +++++----- qcom/holi-mtp-usbc-pm6125.dtsi | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 7306779c547a..1836b91ac629 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -52,8 +52,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <62900>; vdda-pll-max-microamp = <18300>; @@ -64,15 +64,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 5511797dad36..aa73515cac68 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -52,8 +52,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <62900>; vdda-pll-max-microamp = <18300>; @@ -64,15 +64,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 4290d083d7c5..276260da9ece 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -52,8 +52,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <62900>; vdda-pll-max-microamp = <18300>; @@ -64,15 +64,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; From 50c4771b86787eb4e495d8cae4cab19bdfdec38c Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Fri, 7 May 2021 22:54:18 +0530 Subject: [PATCH 1399/1809] ARM: dts: msm: Add high speed PHY node on blair Add high speed PHY node and the corresponding resources to support USB high speed on blair. Also add support for eud spoof. Change-Id: I8d58d433731e346206b1dbe83fe06f872e50519b --- qcom/blair-usb.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index dee02ace8c3a..c4b51bce7d5e 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -42,12 +42,14 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,gsi-disable-io-coherency; + extcon = <&eud>; dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xcd00>; interrupt-parent = <&intc>; interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; @@ -62,6 +64,30 @@ }; }; + /* Primary USB port related QUSB2 PHY */ + qusb_phy0: qusb@162b000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x162B000 0x114>, + <0x0162A000 0x1000>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L7A>; + vdda18-supply = <&L10A>; + vdda33-supply = <&L7E>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = + <0xe6 0x6c /* override_x0 */ + 0x0b 0x70 /* override_x1 */ + 0x17 0x74>; /* override x2 */ + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; From 1ea4667cead3a2a249fc7e31fc270f645fbfaf73 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 6 May 2021 11:06:51 +0530 Subject: [PATCH 1400/1809] ARM: dts: msm: Add initial PMIC and regulator support for blair Add initial PM6125, PMR735A and regulator support for blair. Change-Id: Ib49bad6b01f72f2b80b75d0cfb16cfede5c36a21 --- qcom/blair-atp-overlay.dts | 2 +- qcom/blair-atp.dtsi | 190 ++++++++++++++++++++++++++++++++++++- qcom/blair-cdp-overlay.dts | 2 +- qcom/blair-cdp.dtsi | 1 + qcom/blair-mtp-overlay.dts | 2 +- qcom/blair-mtp.dtsi | 1 + qcom/blair-rumi.dtsi | 2 +- qcom/blair.dtsi | 42 +++++++- 8 files changed, 233 insertions(+), 9 deletions(-) diff --git a/qcom/blair-atp-overlay.dts b/qcom/blair-atp-overlay.dts index 3cb5e6589def..c96b78ec4330 100644 --- a/qcom/blair-atp-overlay.dts +++ b/qcom/blair-atp-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "blair.dtsi" #include "blair-atp.dtsi" / { diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 336d7a250678..31a7cfb8f289 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -1,2 +1,190 @@ -/ { +&rpm_bus { + /* Delete all PM6125 and PMR735a rpm-regulators */ + /delete-node/ rpm-regulator-smpa6; + /delete-node/ rpm-regulator-smpa7; + /delete-node/ rpm-regulator-smpa8; + /delete-node/ rpm-regulator-ldoa1; + /delete-node/ rpm-regulator-ldoa2; + /delete-node/ rpm-regulator-ldoa3; + /delete-node/ rpm-regulator-ldoa4; + /delete-node/ rpm-regulator-ldoa5; + /delete-node/ rpm-regulator-ldoa6; + /delete-node/ rpm-regulator-ldoa7; + /delete-node/ rpm-regulator-ldoa8; + /delete-node/ rpm-regulator-ldoa9; + /delete-node/ rpm-regulator-ldoa10; + /delete-node/ rpm-regulator-ldoa11; + /delete-node/ rpm-regulator-ldoa12; + /delete-node/ rpm-regulator-ldoa13; + /delete-node/ rpm-regulator-ldoa14; + /delete-node/ rpm-regulator-ldoa15; + /delete-node/ rpm-regulator-ldoa16; + /delete-node/ rpm-regulator-ldoa17; + /delete-node/ rpm-regulator-ldoa18; + /delete-node/ rpm-regulator-ldoa19; + /delete-node/ rpm-regulator-ldoa20; + /delete-node/ rpm-regulator-ldoa21; + /delete-node/ rpm-regulator-ldoa22; + /delete-node/ rpm-regulator-ldoa23; + /delete-node/ rpm-regulator-ldoa24; + + /delete-node/ rpm-regulator-smpe1; + /delete-node/ rpm-regulator-smpe2; + /delete-node/ rpm-regulator-ldoe1; + /delete-node/ rpm-regulator-ldoe2; + /delete-node/ rpm-regulator-ldoe3; + /delete-node/ rpm-regulator-ldoe4; + /delete-node/ rpm-regulator-ldoe5; + /delete-node/ rpm-regulator-ldoe7; + + /* Disable all PM6125 and PMR735a rpm-regulators */ + rpm-regulator-smpa6 { + status = "disabled"; + }; + + rpm-regulator-smpa7 { + status = "disabled"; + }; + + rpm-regulator-smpa8 { + status = "disabled"; + }; + + rpm-regulator-ldoa1 { + status = "disabled"; + }; + + rpm-regulator-ldoa2 { + status = "disabled"; + }; + + rpm-regulator-ldoa3 { + status = "disabled"; + }; + + rpm-regulator-ldoa4 { + status = "disabled"; + }; + + rpm-regulator-ldoa5 { + status = "disabled"; + }; + + rpm-regulator-ldoa6 { + status = "disabled"; + }; + + rpm-regulator-ldoa7 { + status = "disabled"; + }; + + rpm-regulator-ldoa8 { + status = "disabled"; + }; + + rpm-regulator-ldoa9 { + status = "disabled"; + }; + + rpm-regulator-ldoa10 { + status = "disabled"; + }; + + rpm-regulator-ldoa11 { + status = "disabled"; + }; + + rpm-regulator-ldoa12 { + status = "disabled"; + }; + + rpm-regulator-ldoa13 { + status = "disabled"; + }; + + rpm-regulator-ldoa14 { + status = "disabled"; + }; + + rpm-regulator-ldoa15 { + status = "disabled"; + }; + + rpm-regulator-ldoa16 { + status = "disabled"; + }; + + rpm-regulator-ldoa17 { + status = "disabled"; + }; + + rpm-regulator-ldoa18 { + status = "disabled"; + }; + + rpm-regulator-ldoa19 { + status = "disabled"; + }; + + rpm-regulator-ldoa20 { + status = "disabled"; + }; + + rpm-regulator-ldoa21 { + status = "disabled"; + }; + + rpm-regulator-ldoa22 { + status = "disabled"; + }; + + rpm-regulator-ldoa23 { + status = "disabled"; + }; + + rpm-regulator-ldoa24 { + status = "disabled"; + }; + + rpm-regulator-smpe1 { + status = "disabled"; + }; + + rpm-regulator-smpe2 { + status = "disabled"; + }; + + rpm-regulator-ldoe1 { + status = "disabled"; + }; + + rpm-regulator-ldoe2 { + status = "disabled"; + }; + + rpm-regulator-ldoe3 { + status = "disabled"; + }; + + rpm-regulator-ldoe4 { + status = "disabled"; + }; + + rpm-regulator-ldoe5 { + status = "disabled"; + }; + + rpm-regulator-ldoe6 { + status = "disabled"; + }; + + rpm-regulator-ldoe7 { + status = "disabled"; + }; }; + +#include "pm6350-rpm-regulator.dtsi" +#include "pm6150l-rpm-regulator.dtsi" +#include "holi-regulators-pm6350.dtsi" + +#include "holi-atp.dtsi" diff --git a/qcom/blair-cdp-overlay.dts b/qcom/blair-cdp-overlay.dts index 040d921c2875..e4b36a584b26 100644 --- a/qcom/blair-cdp-overlay.dts +++ b/qcom/blair-cdp-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "blair.dtsi" #include "blair-cdp.dtsi" / { diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 336d7a250678..1485ffe26a9e 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,2 +1,3 @@ +#include "holi-cdp-pm6125.dtsi" / { }; diff --git a/qcom/blair-mtp-overlay.dts b/qcom/blair-mtp-overlay.dts index dc4692d649ac..7f1464083f57 100644 --- a/qcom/blair-mtp-overlay.dts +++ b/qcom/blair-mtp-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "blair.dtsi" #include "blair-mtp.dtsi" / { diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 336d7a250678..5b6c4bff59a4 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -1,2 +1,3 @@ +#include "holi-mtp-pm6125.dtsi" / { }; diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi index 186aa810a6b4..8297cdbaae5b 100644 --- a/qcom/blair-rumi.dtsi +++ b/qcom/blair-rumi.dtsi @@ -65,7 +65,7 @@ cap-sd-highspeed; - vdd-supply = <&L9E>; + /* vdd-supply = <&L9E>; */ qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 4ef0dd0b6c34..954f2e84a93e 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -482,7 +482,7 @@ qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; qcom,bt-vdd-io-supply = <&L11A>; /* IO */ qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ - qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ + /* qcom,bt-vdd-pa-supply = <&L10E>; */ /* CH0 */ qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ qcom,bt-vdd-io-config = <1700000 1900000 1 0>; @@ -3363,9 +3363,9 @@ #include "holi-gpu.dtsi" #include "blair-pinctrl.dtsi" -#include "pm6350-rpm-regulator.dtsi" -#include "pm6150l-rpm-regulator.dtsi" -#include "holi-regulators-pm6350.dtsi" +#include "pm6125-rpm-regulator.dtsi" +#include "pmr735a-rpm-regulator.dtsi" +#include "holi-regulators-pm6125.dtsi" #include "holi-gdsc.dtsi" #include "holi-ion.dtsi" #include "msm-arm-smmu-holi.dtsi" @@ -3380,6 +3380,40 @@ #include "blair-usb.dtsi" #include "ipcc-test-holi.dtsi" +&L2A { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1170000>; +}; + +&L3A { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; +}; + +&L7A { + regulator-min-microvolt = <720000>; +}; + +&L2E { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; +}; + +&L3E { + regulator-min-microvolt = <1000000>; +}; + +&L7E { + regulator-max-microvolt = <3544000>; +}; + +/* Dummy LDO handle*/ +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2A>; +}; + &gcc_camss_top_gdsc { status = "ok"; }; From cf0a7a15d1181833eb27bb91a4f50c5f8d851f1f Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 13 May 2021 16:57:38 +0530 Subject: [PATCH 1401/1809] ARM: dts: msm: Update thermal zone entries for holi-pm6125 Update rear camera thermal zone name and pa_therm0 channel number for holi-pm6125. Change-Id: I952988de7f4ebcb1ba938b2ce3dde6a951ab7364 --- qcom/holi-pmic-overlay-pm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index fb8061b053e3..34bf7d3a19ff 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -291,7 +291,7 @@ }; }; - rfc-cam-pa3-usr { + rear-cam-therm-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -346,7 +346,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; wake-capable-sensor; trips { active-config0 { From 051d17356f0687b93f9e59edd24a37848490393d Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 12 Apr 2021 19:35:28 +0530 Subject: [PATCH 1402/1809] ARM: dts: msm: Add device tree support for PM7250B Add device tree support for IDP with PM7250B for Yupik platform. Change-Id: I3fb9b5e9825997fa66d43c3ce45530e914148891 --- qcom/Makefile | 3 +++ qcom/yupik-idp-pm7250b-overlay.dts | 12 ++++++++++++ qcom/yupik-idp-pm7250b.dts | 11 +++++++++++ qcom/yupik-idp-pm7250b.dtsi | 6 ++++++ 4 files changed, 32 insertions(+) create mode 100644 qcom/yupik-idp-pm7250b-overlay.dts create mode 100644 qcom/yupik-idp-pm7250b.dts create mode 100644 qcom/yupik-idp-pm7250b.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 9d5d6f68bb88..942dc88ff26b 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -189,6 +189,7 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-qrd-overlay.dtbo \ yupik-idps-digital-mics-overlay.dtbo \ yupik-idps-amoled-overlay.dtbo \ + yupik-idp-pm7250b-overlay.dtbo \ yupikp-idp-overlay.dtbo \ yupikp-atp-overlay.dtbo \ yupikp-qrd-overlay.dtbo \ @@ -210,6 +211,7 @@ yupik-atp-overlay.dtbo-base := yupik.dtb yupik-qrd-overlay.dtbo-base := yupik.dtb yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb yupik-idps-amoled-overlay.dtbo-base := yupik.dtb +yupik-idp-pm7250b-overlay.dtbo-base := yupik.dtb yupikp-idp-overlay.dtbo-base := yupikp.dtb yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb @@ -230,6 +232,7 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-qrd.dtb \ yupik-idps-digital-mics.dtb \ yupik-idps-amoled.dtb \ + yupik-idp-pm7250b.dtb \ yupikp-idp.dtb \ yupikp-atp.dtb \ yupikp-qrd.dtb \ diff --git a/qcom/yupik-idp-pm7250b-overlay.dts b/qcom/yupik-idp-pm7250b-overlay.dts new file mode 100644 index 000000000000..b2c533d7738a --- /dev/null +++ b/qcom/yupik-idp-pm7250b-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "yupik-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,msm-id = <475 0x10000>, <515 0x10000>; + /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ + qcom,board-id = <34 0xFF>; +}; diff --git a/qcom/yupik-idp-pm7250b.dts b/qcom/yupik-idp-pm7250b.dts new file mode 100644 index 000000000000..45ac21a01659 --- /dev/null +++ b/qcom/yupik-idp-pm7250b.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "yupik.dtsi" +#include "yupik-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ + qcom,board-id = <34 0xFF>; +}; diff --git a/qcom/yupik-idp-pm7250b.dtsi b/qcom/yupik-idp-pm7250b.dtsi new file mode 100644 index 000000000000..87a11c1f1ebd --- /dev/null +++ b/qcom/yupik-idp-pm7250b.dtsi @@ -0,0 +1,6 @@ +#include "yupik-idp.dtsi" + +/ { + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2e>; + qcom,pmic-id-size = <9>; +}; From d3c57a4bbd7a415eecc3b61936dcbbc801d7098b Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 15 Apr 2021 11:15:27 +0530 Subject: [PATCH 1403/1809] ARM: dts: msm: Add support for yupik IDP with PM7250B Add device tree support for yupik IDP variant with PM7250B replacing PM7325B. Change-Id: I5445934bd05b8ef14a99c84b1d56ffafa848ef29 --- qcom/pm7250b.dtsi | 4 +- qcom/yupik-idp-pm7250b.dtsi | 310 +++++++++++++++++++++++- qcom/yupik-pm7250b-thermal-overlay.dtsi | 226 +++++++++++++++++ 3 files changed, 537 insertions(+), 3 deletions(-) create mode 100644 qcom/yupik-pm7250b-thermal-overlay.dtsi diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index d6febd590a60..33407576b4ac 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -9,7 +9,7 @@ interrupt-controller; #interrupt-cells = <4>; - qcom,pm7250b@2 { + pm7250b_2: qcom,pm7250b@2 { compatible = "qcom,spmi-pmic"; reg = <2 SPMI_USID>; #address-cells = <1>; @@ -408,7 +408,7 @@ }; }; - qcom,pm7250b@3 { + pm7250b_3: qcom,pm7250b@3 { compatible = "qcom,spmi-pmic"; reg = <3 SPMI_USID>; #address-cells = <1>; diff --git a/qcom/yupik-idp-pm7250b.dtsi b/qcom/yupik-idp-pm7250b.dtsi index 87a11c1f1ebd..9ac085eb5f88 100644 --- a/qcom/yupik-idp-pm7250b.dtsi +++ b/qcom/yupik-idp-pm7250b.dtsi @@ -1,6 +1,314 @@ -#include "yupik-idp.dtsi" +#include +#include +#include +#include "yupik-pmic-overlay.dtsi" +#include "pm7250b.dtsi" +#include "yupik-audio-overlay.dtsi" +#include "yupik-pm7250b-thermal-overlay.dtsi" / { qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2e>; qcom,pmic-id-size = <9>; }; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 41 0x00>; + qcom,sn-ven = <&tlmm 38 0x00>; + qcom,sn-firm = <&tlmm 40 0x00>; + qcom,sn-clkreq = <&tlmm 39 0x00>; + qcom,sn-vdd-1p8-supply = <&L18B>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <41 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97500>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2952000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&pm7250b_2 { + /* Slave ID - 8 */ + reg = <8 SPMI_USID>; +}; + +&pm7250b_3 { + /* Slave ID - 9 */ + reg = <9 SPMI_USID>; +}; + +&pm7250b_vadc { + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; + + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + /* Channel nodes */ + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_tz { + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +}; + +&pm7250b_bcl { + interrupts = <0x8 0x1d 0x0 IRQ_TYPE_NONE>, + <0x8 0x1d 0x1 IRQ_TYPE_NONE>, + <0x8 0x1d 0x2 IRQ_TYPE_NONE>; +}; + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; +}; + +&pm7250b_charger { + status = "disabled"; +}; + +&pm7250b_qg { + status = "disabled"; +}; + +&pm7250b_pdphy { + status = "disabled"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350c_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8350c_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8350c_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8350c_flash { + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; +}; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2952000 2952000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + status = "ok"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&qupv3_se13_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active="novatek,NVT-ts"; + + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + + interrupt-parent = <&tlmm>; + interrupts = <81 0x2008>; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + novatek,reset-gpio = <&tlmm 105 0x00>; + novatek,irq-gpio = <&tlmm 81 0x2008>; + + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "pvm"; + novatek,trusted-touch-spi-irq = <601>; + novatek,trusted-touch-io-bases = <0xf134000 0xf135000 0xf169000 0xf151000 0xa94000 0x00a10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +#include "camera/yupik-camera-sensor-idp.dtsi" diff --git a/qcom/yupik-pm7250b-thermal-overlay.dtsi b/qcom/yupik-pm7250b-thermal-overlay.dtsi new file mode 100644 index 000000000000..057d99d8fbcd --- /dev/null +++ b/qcom/yupik-pm7250b-thermal-overlay.dtsi @@ -0,0 +1,226 @@ +#include + +&mdss_mdp { + #cooling-cells = <2>; +}; + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vbat_modem0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vbat_modem0 { + trip = <&c_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325_tz { + cooling-maps { + pm7325_gpu { + trip = <&pm7325_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm7325_cpu1 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm7325_cpu2 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm7325_cpu3 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm7325_cpu4 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm7325_cpu5 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm7325_cpu6 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm7325_cpu7 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_gpu { + trip = <&pm8350c_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + pmr735a_pa { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_pa_fr1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw0 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw2 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw3 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; From 9f8315d2dde9bac7aef22c733033a000ba0db9da Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 13 May 2021 17:36:50 +0530 Subject: [PATCH 1404/1809] ARM: dts: msm: replace usb regulator values for BLAIR ATP platform Replacing the usb regulator values by those of holi for blair ATP platform as it uses the same PMIC as holi. Change-Id: Ibb7d931592dc667726a67e47461f031ad9fc76cf --- qcom/blair-atp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 31a7cfb8f289..ef636c2782e5 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -188,3 +188,15 @@ #include "holi-regulators-pm6350.dtsi" #include "holi-atp.dtsi" + +&qusb_phy0 { + vdd-supply = <&L18A>; + vdda18-supply = <&L2A>; + vdda33-supply = <&L3A>; + refgen-supply = <&L22A>; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&L16A>; + core-supply = <&L22A>; +}; From 86a557dbcf113874670d5ffce4d7b97354b73771 Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Wed, 12 May 2021 17:06:21 +0530 Subject: [PATCH 1405/1809] ARM: dts: qcom: Remove PMIC dt inclusion Remove PMIC dt inclusion in monaco dtsi. Remove pmic spmi node. Remove i2c node. Change-Id: Iedbbc0dddf52927b7d7d4f777928ddb4f8f15f23 --- qcom/monaco-amic-audio-overlay.dtsi | 1 - qcom/monaco-audio-overlay.dtsi | 1 - qcom/monaco-audio.dtsi | 9 --------- qcom/monaco.dtsi | 1 - 4 files changed, 12 deletions(-) diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi index 6b588baa925f..4c3868c669a7 100644 --- a/qcom/monaco-amic-audio-overlay.dtsi +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -70,7 +70,6 @@ besbev_codec: besbev-codec { compatible = "qcom,besbev-codec"; qcom,split-codec = <1>; - qcom,pmic-spmi-node = <&pm5100_cdc>; qcom,wcd-reset-reg = <0x0000FCDB>; qcom,foundry-id-reg = <0x000001F2>; qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi index 90f4d63a9b6e..8f7783f0e0bf 100644 --- a/qcom/monaco-audio-overlay.dtsi +++ b/qcom/monaco-audio-overlay.dtsi @@ -114,7 +114,6 @@ besbev_codec: besbev-codec { compatible = "qcom,besbev-codec"; qcom,split-codec = <1>; - qcom,pmic-spmi-node = <&pm5100_cdc>; qcom,wcd-reset-reg = <0x0000FCDB>; qcom,foundry-id-reg = <0x000001F2>; qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, diff --git a/qcom/monaco-audio.dtsi b/qcom/monaco-audio.dtsi index ed9e4d025a35..04698ce6d97d 100644 --- a/qcom/monaco-audio.dtsi +++ b/qcom/monaco-audio.dtsi @@ -150,7 +150,6 @@ "msm-dai-cdc-dma-dev.45116", "msm-dai-cdc-dma-dev.45118", "msm-dai-q6-dev.24577"; - fsa4480-i2c-handle = <&fsa4480>; }; }; @@ -158,11 +157,3 @@ iommus = <&apps_smmu 0x01c1 0x0>; qcom,smmu-sid-mask = /bits/ 64 <0xf>; }; - -&qupv3_se1_i2c { - status = "ok"; - fsa4480: fsa4480@42 { - compatible = "qcom,fsa4480-i2c"; - reg = <0x42>; - }; -}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3615caf7bc94..93697a91f5fc 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1226,7 +1226,6 @@ }; }; -#include "pm5100.dtsi" #include "monaco-pinctrl.dtsi" #include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" From 62ac268338424a79e60c150c5831d34b1f9691ea Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Thu, 13 May 2021 19:36:01 +0530 Subject: [PATCH 1406/1809] ARM: dts: msm: Update GPU revision for Yupik Yupik GPU correct revision is 642L. Update the compatible string to reflect correct revision. Change-Id: I2555fe27ea5f738301ce07443dc9482c5412e077 --- bindings/gpu/adreno.txt | 1 + qcom/yupik-gpu.dtsi | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 075ae20dd9d9..3f95e92b9df6 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -7,6 +7,7 @@ Required properties: May also includes "qcom,adreno-gpu-*" for few targets. Must include "qcom,adreno-gpu-a619-holi" for Holi target. Must include "qcom,adreno-gpu-a642" for Shima target. + Must include "qcom,adreno-gpu-a642l" for Yupik target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c09538cf0ddc..b2b4c38eca6d 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -16,7 +16,8 @@ }; msm_gpu: qcom,kgsl-3d0@3d00000 { - compatible = "qcom,kgsl-3d0"; + compatible = "qcom,kgsl-3d0", + "qcom,adreno-gpu-a642l"; status = "ok"; reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, From 90c6e537322726a2431c199ea3264c4c6034df0d Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Wed, 5 May 2021 14:40:48 +0530 Subject: [PATCH 1407/1809] ARM: dts: msm: Add USB regulators for holi-pm6125 This change adds proper USB regulators for holi-pm6125 according to the new powergrid. Change-Id: I9a9c12e7e5023e6eb262de4bfeb81f7deca01628 --- qcom/holi-pmic-overlay-pm6125.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index fb8061b053e3..4e78684f2e87 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -496,3 +496,15 @@ }; }; }; + +&qusb_phy0 { + vdd-supply = <&L7A>; + vdda18-supply = <&L10A>; + vdda33-supply = <&L7E>; + refgen-supply = <&L4A>; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&L18A>; + core-supply = <&L4A>; +}; From 84a95d00e00bbbd42e8022377eb1c5739a31fa73 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Fri, 7 May 2021 18:20:16 +0800 Subject: [PATCH 1408/1809] ARM: dts: msm: Fix compilation warnings for sa8155, sa8195 and sa6155 Fix compilation warnings for sa8155, sa8195 and sa6155. Change-Id: I6463b9106e2c40104720052b073455164e641df1 --- qcom/msm-arm-smmu-sdmshrike.dtsi | 56 ++++++++++++++++---------------- qcom/msm-arm-smmu-sm6150.dtsi | 20 ++++++------ qcom/msm-arm-smmu-sm8150-v2.dtsi | 28 ++++++++-------- qcom/msm-arm-smmu-sm8150.dtsi | 46 +++++++++++++------------- qcom/sa6155-adp-common.dtsi | 2 +- qcom/sa6155.dtsi | 2 +- qcom/sa6155p.dtsi | 4 +-- qcom/sa8155-adp-common.dtsi | 2 +- qcom/sa8155.dtsi | 10 +++--- qcom/sa8195-qupv3.dtsi | 18 +++++----- qcom/sa8195p-adp-common.dtsi | 4 +-- qcom/sa8195p.dtsi | 6 ++-- qcom/sdmshrike.dtsi | 32 +++++++++--------- qcom/sm6150-gpu.dtsi | 4 +-- qcom/sm6150-slpi-pinctrl.dtsi | 4 +-- qcom/sm6150.dtsi | 14 ++++---- qcom/sm8150-gpu.dtsi | 8 ++--- qcom/sm8150-pinctrl.dtsi | 2 +- qcom/sm8150-qupv3.dtsi | 16 ++++----- qcom/sm8150-slpi-pinctrl.dtsi | 4 +-- qcom/sm8150.dtsi | 10 +++--- 21 files changed, 146 insertions(+), 146 deletions(-) diff --git a/qcom/msm-arm-smmu-sdmshrike.dtsi b/qcom/msm-arm-smmu-sdmshrike.dtsi index 28a31ba15cd7..8788e684d9e6 100644 --- a/qcom/msm-arm-smmu-sdmshrike.dtsi +++ b/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -1,9 +1,9 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02CA0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02CA0000 0x10000>, + reg = <0x2ca0000 0x10000>, <0x2CC2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; @@ -35,40 +35,40 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC5000 0x1000>, - <0x2CC2200 0x8>; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC9000 0x1000>, - <0x2CC2208 0x8>; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; - gfx_2_tbu: gfx_2_tbu@0x2CCD000 { + gfx_2_tbu: gfx_2_tbu@2ccd000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CCD000 0x1000>, - <0x2CC2210 0x8>; + reg = <0x2ccd000 0x1000>, + <0x2cc2210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; }; - gfx_3_tbu: gfx_3_tbu@0x2CD1000 { + gfx_3_tbu: gfx_3_tbu@2cd1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CD1000 0x1000>, - <0x2CC2218 0x8>; + reg = <0x2cd1000 0x1000>, + <0x2cc2218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xC00 0x400>; }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -213,7 +213,7 @@ interconnects = <&system_noc MASTER_GEM_NOC_SNOC &config_noc SLAVE_IMEM_CFG>; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -226,7 +226,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -239,9 +239,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1518D000 0x1000>, + reg = <0x1518d000 0x1000>, <0x15182210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; @@ -252,7 +252,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -265,7 +265,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -276,7 +276,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -287,9 +287,9 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519D000 { + adsp_tbu: adsp_tbu@1519d000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1519D000 0x1000>, + reg = <0x1519d000 0x1000>, <0x15182230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; @@ -300,9 +300,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_pcie: anoc_pcie@151A1000 { + anoc_pcie: anoc_pcie@151a1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A1000 0x1000>, + reg = <0x151a1000 0x1000>, <0x15182238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; @@ -315,9 +315,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151A5000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A5000 0x1000>, + reg = <0x151a5000 0x1000>, <0x15182240 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; diff --git a/qcom/msm-arm-smmu-sm6150.dtsi b/qcom/msm-arm-smmu-sm6150.dtsi index ebf2aaeeaf3d..1fdde83c4c48 100644 --- a/qcom/msm-arm-smmu-sm6150.dtsi +++ b/qcom/msm-arm-smmu-sm6150.dtsi @@ -1,7 +1,7 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x50a0000 { + kgsl_smmu: kgsl-smmu@50a0000 { compatible = "qcom,qsmmu-v500"; reg = <0x50a0000 0x10000>, <0x50c2000 0x20>; @@ -35,7 +35,7 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x50c5000 { + gfx_0_tbu: gfx_0_tbu@50c5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x50c5000 0x1000>, <0x50c2200 0x8>; @@ -43,7 +43,7 @@ qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x50c9000 { + gfx_1_tbu: gfx_1_tbu@50c9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x50c9000 0x1000>, <0x50c2208 0x8>; @@ -52,7 +52,7 @@ }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x80000>, <0x150c2000 0x20>; @@ -135,7 +135,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x150c5000 { + anoc_1_tbu: anoc_1_tbu@150c5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150c5000 0x1000>, <0x150c2200 0x8>; @@ -148,7 +148,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x150c9000 { + anoc_2_tbu: anoc_2_tbu@150c9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150c9000 0x1000>, <0x150c2208 0x8>; @@ -161,7 +161,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@150cd000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150cd000 0x1000>, <0x150c2210 0x8>; @@ -174,7 +174,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@150d1000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d1000 0x1000>, <0x150c2218 0x8>; @@ -187,7 +187,7 @@ &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; }; - compute_dsp_tbu: compute_dsp_tbu@0x150d5000 { + compute_dsp_tbu: compute_dsp_tbu@150d5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d5000 0x1000>, <0x150c2220 0x8>; @@ -199,7 +199,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - adsp_tbu: adsp_tbu@0x150d9000 { + adsp_tbu: adsp_tbu@150d9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d9000 0x1000>, <0x150c2228 0x8>; diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi index b694e0b014e8..9daee328b3f4 100644 --- a/qcom/msm-arm-smmu-sm8150-v2.dtsi +++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -1,9 +1,9 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02ca0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02ca0000 0x10000>, + reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; @@ -34,7 +34,7 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2cc5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x2cc5000 0x1000>, <0x2cc2200 0x8>; @@ -42,7 +42,7 @@ qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2cc9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x2cc9000 0x1000>, <0x2cc2208 0x8>; @@ -51,7 +51,7 @@ }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -150,7 +150,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -163,7 +163,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -176,7 +176,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x1518d000 0x1000>, <0x15182210 0x8>; @@ -189,7 +189,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -202,7 +202,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -214,7 +214,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -226,7 +226,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519d000 { + adsp_tbu: adsp_tbu@1519d000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x1519d000 0x1000>, <0x15182230 0x8>; @@ -239,7 +239,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 { + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151a1000 0x1000>, <0x15182238 0x8>; @@ -255,7 +255,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151a5000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151a5000 0x1000>, <0x15182240 0x8>; diff --git a/qcom/msm-arm-smmu-sm8150.dtsi b/qcom/msm-arm-smmu-sm8150.dtsi index f279e5a55d46..71ae985d344c 100644 --- a/qcom/msm-arm-smmu-sm8150.dtsi +++ b/qcom/msm-arm-smmu-sm8150.dtsi @@ -1,10 +1,10 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02CA0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02CA0000 0x10000>, - <0x2CC2000 0x20>; + reg = <0x2ca0000 0x10000>, + <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,dynamic; @@ -35,24 +35,24 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC5000 0x1000>, - <0x2CC2200 0x8>; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC9000 0x1000>, - <0x2CC2208 0x8>; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -152,7 +152,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -165,7 +165,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -179,9 +179,9 @@ }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518D000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1518D000 0x1000>, + reg = <0x1518d000 0x1000>, <0x15182210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; @@ -192,7 +192,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -205,7 +205,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -218,7 +218,7 @@ &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -229,9 +229,9 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519D000 { + adsp_tbu: adsp_tbu@1519D000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1519D000 0x1000>, + reg = <0x1519d000 0x1000>, <0x15182230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; @@ -242,9 +242,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 { + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151A1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A1000 0x1000>, + reg = <0x151a1000 0x1000>, <0x15182238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; @@ -258,9 +258,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@151A5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A5000 0x1000>, + reg = <0x151a5000 0x1000>, <0x15182240 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index ff23e07f3486..5a65e70dae2b 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -92,7 +92,7 @@ }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; emac-core-version = <0x20030001>; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index d3b627917396..018ff859c0ef 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -203,7 +203,7 @@ }; &reserved_memory { - uefi_log: uefi_log@0x9241C000 { + uefi_log: uefi_log@9241C000 { reg = <0x0 0x9241C000 0x0 0x10000>; label = "uefi_log"; }; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index cdb73870c1fc..ec2fa6bae6dd 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -41,10 +41,10 @@ ranges; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@1b40000 { compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; number-of-interfaces = <2>; - reg = <0x1B40000 0x28000>; + reg = <0x1b40000 0x28000>; reg-names = "lpa_if"; interrupts = ; clocks = <&gcc GCC_SDR_CORE_CLK>, diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index f9d32f4980b8..5161e34ca504 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -106,7 +106,7 @@ status = "ok"; }; - qcom,spss@1880000 { + qcom,spss@188101c { status = "ok"; }; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 78933e085cd0..f47e907fc63e 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -120,7 +120,7 @@ }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; reg = <0x20000 0x10000>, @@ -204,11 +204,11 @@ mbox-names = "aop"; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@172c0000 { compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; + reg = <0x172c0000 0x28000>, + <0x17080000 0xe000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = ; number-of-rate-detectors = <2>; @@ -377,7 +377,7 @@ */ /delete-node/ pil_wlan_fw_mem; - uefi_log: uefi_log@0x9241C000 { + uefi_log: uefi_log@9241C000 { reg = <0x0 0x9241C000 0x0 0x10000>; label = "uefi_log"; }; diff --git a/qcom/sa8195-qupv3.dtsi b/qcom/sa8195-qupv3.dtsi index ce4ce38db758..02672c886918 100644 --- a/qcom/sa8195-qupv3.dtsi +++ b/qcom/sa8195-qupv3.dtsi @@ -378,7 +378,7 @@ }; /* Debug UART Instance for CDP/MTP platform */ - qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + qupv3_se12_2uart: qcom,qup_uart@a90000 { compatible = "qcom,msm-geni-console"; reg = <0xa90000 0x4000>; reg-names = "se_phys"; @@ -395,7 +395,7 @@ }; /* 4-wire UART */ - qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + qupv3_se13_4uart: qcom,qup_uart@c8c000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xc8c000 0x4000>; reg-names = "se_phys"; @@ -417,7 +417,7 @@ status = "disabled"; }; - qupv3_se16_2uart: qcom,qup_uart@0xa94000 { + qupv3_se16_2uart: qcom,qup_uart@a94000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xa94000 0x4000>; reg-names = "se_phys"; @@ -646,7 +646,7 @@ status = "disabled"; }; - qupv3_se14_i2c: i2c@0xc90000 { + qupv3_se14_i2c: i2c@c90000 { compatible = "qcom,i2c-geni"; reg = <0xc90000 0x4000>; interrupts = ; @@ -663,7 +663,7 @@ status = "disabled"; }; - qupv3_se15_i2c: i2c@0xc94000 { + qupv3_se15_i2c: i2c@c94000 { compatible = "qcom,i2c-geni"; reg = <0xc94000 0x4000>; interrupts = ; @@ -680,7 +680,7 @@ status = "disabled"; }; - qupv3_se16_i2c: i2c@0xa94000 { + qupv3_se16_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = ; @@ -697,7 +697,7 @@ status = "disabled"; }; - qupv3_se17_i2c: i2c@0xc80000 { + qupv3_se17_i2c: i2c@c80000 { compatible = "qcom,i2c-geni"; reg = <0xc80000 0x4000>; interrupts = ; @@ -714,7 +714,7 @@ status = "disabled"; }; - qupv3_se18_i2c: i2c@0xc84000 { + qupv3_se18_i2c: i2c@c84000 { compatible = "qcom,i2c-geni"; reg = <0xc84000 0x4000>; interrupts = ; @@ -731,7 +731,7 @@ status = "disabled"; }; - qupv3_se19_i2c: i2c@0xc88000 { + qupv3_se19_i2c: i2c@c88000 { compatible = "qcom,i2c-geni"; reg = <0xc88000 0x4000>; interrupts = ; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 2812da0bfcb4..1dab6e7db843 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -62,7 +62,7 @@ status = "ok"; status = "ok"; }; - qcom,spss@1880000 { + qcom,spss@188101c { status = "ok"; }; @@ -128,7 +128,7 @@ status = "ok"; }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; emac-core-version = <0x20010001>; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index f948d707cf54..af53e61269e0 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -30,11 +30,11 @@ ranges; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@172c0000 { compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; + reg = <0x172c0000 0x28000>, + <0x17080000 0xe000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = ; number-of-rate-detectors = <2>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f9963d44fc0b..39abaf3c7b80 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -321,52 +321,52 @@ reg = <0x0 0x8bc00000 0x0 0x180000>; }; - pil_npu_mem: pil_npu_region@0x8bd80000 { + pil_npu_mem: pil_npu_region@8bd80000 { no-map; reg = <0x0 0x8bd80000 0x0 0x80000>; }; - pil_adsp_mem: pil_adsp_region@0x8be00000 { + pil_adsp_mem: pil_adsp_region@8be00000 { no-map; reg = <0x0 0x8be00000 0x0 0x1a00000>; }; - pil_modem_mem: modem_region@0x8d800000 { + pil_modem_mem: modem_region@8d800000 { no-map; reg = <0x0 0x8d800000 0x0 0x9600000>; }; - pil_video_mem: pil_video_region@0x96e00000 { + pil_video_mem: pil_video_region@96e00000 { no-map; reg = <0x0 0x96e00000 0x0 0x500000>; }; - pil_slpi_mem: pil_slpi_region@0x97300000 { + pil_slpi_mem: pil_slpi_region@97300000 { no-map; reg = <0x0 0x97300000 0x0 0x1400000>; }; - pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { + pil_ipa_fw_mem: pil_ipa_fw_region@98700000 { no-map; reg = <0x0 0x98700000 0x0 0x10000>; }; - pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { + pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 { no-map; reg = <0x0 0x98710000 0x0 0x5000>; }; - pil_gpu_mem: pil_gpu_region@0x98715000 { + pil_gpu_mem: pil_gpu_region@98715000 { no-map; reg = <0x0 0x98715000 0x0 0x2000>; }; - pil_spss_mem: pil_spss_region@0x98800000 { + pil_spss_mem: pil_spss_region@98800000 { no-map; reg = <0x0 0x98800000 0x0 0x100000>; }; - pil_cdsp_mem: cdsp_regions@0x98900000 { + pil_cdsp_mem: cdsp_regions@98900000 { no-map; reg = <0x0 0x98900000 0x0 0x1400000>; }; @@ -380,12 +380,12 @@ }; - cont_splash_memory: cont_splash_region@0x9c000000 { + cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "cont_splash_region"; }; - disp_rdump_memory: disp_rdump_region@0x9c000000 { + disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "disp_rdump_region"; }; @@ -445,7 +445,7 @@ size = <0 0x2400000>; }; - uefi_log: uefi_log@0x8bc00000 { + uefi_log: uefi_log@8bc00000 { reg = <0x0 0x8bc00000 0x0 0x10000>; label = "uefi_log"; }; @@ -543,7 +543,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -551,7 +551,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 7 0x4>, <0 6 0x4>; @@ -2334,7 +2334,7 @@ memory-region = <&pil_npu_mem>; }; - qcom,spss@1880000 { + qcom,spss@188101c { compatible = "qcom,pil-tz-generic"; reg = <0x188101c 0x4>, <0x1881024 0x4>, diff --git a/qcom/sm6150-gpu.dtsi b/qcom/sm6150-gpu.dtsi index b878a008e0d8..f888e6fa49e1 100644 --- a/qcom/sm6150-gpu.dtsi +++ b/qcom/sm6150-gpu.dtsi @@ -604,10 +604,10 @@ }; }; - kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 { + kgsl_msm_iommu: qcom,kgsl-iommu@50a0000 { compatible = "qcom,kgsl-smmu-v2"; - reg = <0x050a0000 0x10000>; + reg = <0x50a0000 0x10000>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; diff --git a/qcom/sm6150-slpi-pinctrl.dtsi b/qcom/sm6150-slpi-pinctrl.dtsi index 32d250433a47..45b9d0510149 100644 --- a/qcom/sm6150-slpi-pinctrl.dtsi +++ b/qcom/sm6150-slpi-pinctrl.dtsi @@ -1,8 +1,8 @@ &soc { - slpi_tlmm: slpi_pinctrl@62B40000 { + slpi_tlmm: slpi_pinctrl@62b40000 { compatible = "qcom,slpi-pinctrl"; - reg = <0x62B40000 0x20000>; + reg = <0x62b40000 0x20000>; qcom,num-pins = <32>; clock-names = "ssc-clk"; clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 9691fa618cc1..c51c34a39596 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -352,17 +352,17 @@ reg = <0x0 0x95900000 0x0 0x1e00000>; }; - pil_ipa_fw_mem: ips_fw_region@0x97700000 { + pil_ipa_fw_mem: ips_fw_region@97700000 { no-map; reg = <0x0 0x97700000 0x0 0x10000>; }; - pil_ipa_gsi_mem: ipa_gsi_region@0x97710000 { + pil_ipa_gsi_mem: ipa_gsi_region@97710000 { no-map; reg = <0x0 0x97710000 0x0 0x5000>; }; - pil_gpu_mem: gpu_region@0x97715000 { + pil_gpu_mem: gpu_region@97715000 { no-map; reg = <0x0 0x97715000 0x0 0x2000>; }; @@ -375,7 +375,7 @@ size = <0x0 0x1400000>; }; - cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { + cdsp_sec_mem: cdsp_sec_regions@9f800000 { no-map; reg = <0x0 0x9f800000 0x0 0x1e00000>; }; @@ -497,7 +497,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -505,7 +505,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 6 0x4>; @@ -932,7 +932,7 @@ &mc_virt SLAVE_EBI1>; }; - qcom,mpm2-sleep-counter@0xc221000 { + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; clock-frequency = <32768>; diff --git a/qcom/sm8150-gpu.dtsi b/qcom/sm8150-gpu.dtsi index 6538058362f5..f8523ca53eb9 100644 --- a/qcom/sm8150-gpu.dtsi +++ b/qcom/sm8150-gpu.dtsi @@ -9,7 +9,7 @@ memory-region = <&pil_gpu_mem>; }; - msm_gpu: qcom,kgsl-3d0@2C00000 { + msm_gpu: qcom,kgsl-3d0@2c00000 { label = "kgsl-3d0"; compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; status = "ok"; @@ -219,10 +219,10 @@ }; - kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 { + kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 { compatible = "qcom,kgsl-smmu-v2"; - reg = <0x02CA0000 0x10000>; + reg = <0x2ca0000 0x10000>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -239,7 +239,7 @@ }; }; - gmu: qcom,gmu@0x2C6A000 { + gmu: qcom,gmu@2c6a000 { compatible = "qcom,gpu-gmu"; reg = <0x2c6a000 0x30000>, diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index ed449a36f0dd..c8eea6ee4ca2 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -1,5 +1,5 @@ &soc { - tlmm: pinctrl@03000000 { + tlmm: pinctrl@3100000 { compatible = "qcom,sm8150-pinctrl"; reg = <0x03100000 0x300000>, <0x03500000 0x300000>, diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi index 74b51b054ad7..c902b9b75aec 100644 --- a/qcom/sm8150-qupv3.dtsi +++ b/qcom/sm8150-qupv3.dtsi @@ -359,7 +359,7 @@ }; /* Debug UART Instance for CDP/MTP platform */ - qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + qupv3_se12_2uart: qcom,qup_uart@a90000 { compatible = "qcom,msm-geni-console"; reg = <0xa90000 0x4000>; reg-names = "se_phys"; @@ -376,7 +376,7 @@ }; /* 4-wire UART */ - qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + qupv3_se13_4uart: qcom,qup_uart@c8c000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xc8c000 0x4000>; reg-names = "se_phys"; @@ -611,7 +611,7 @@ status = "disabled"; }; - qupv3_se14_i2c: i2c@0xc90000 { + qupv3_se14_i2c: i2c@c90000 { compatible = "qcom,i2c-geni"; reg = <0xc90000 0x4000>; interrupts = ; @@ -628,7 +628,7 @@ status = "disabled"; }; - qupv3_se15_i2c: i2c@0xc94000 { + qupv3_se15_i2c: i2c@c94000 { compatible = "qcom,i2c-geni"; reg = <0xc94000 0x4000>; interrupts = ; @@ -645,7 +645,7 @@ status = "disabled"; }; - qupv3_se16_i2c: i2c@0xa94000 { + qupv3_se16_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = ; @@ -662,7 +662,7 @@ status = "disabled"; }; - qupv3_se17_i2c: i2c@0xc80000 { + qupv3_se17_i2c: i2c@c80000 { compatible = "qcom,i2c-geni"; reg = <0xc80000 0x4000>; interrupts = ; @@ -679,7 +679,7 @@ status = "disabled"; }; - qupv3_se18_i2c: i2c@0xc84000 { + qupv3_se18_i2c: i2c@c84000 { compatible = "qcom,i2c-geni"; reg = <0xc84000 0x4000>; interrupts = ; @@ -696,7 +696,7 @@ status = "disabled"; }; - qupv3_se19_i2c: i2c@0xc88000 { + qupv3_se19_i2c: i2c@c88000 { compatible = "qcom,i2c-geni"; reg = <0xc88000 0x4000>; interrupts = ; diff --git a/qcom/sm8150-slpi-pinctrl.dtsi b/qcom/sm8150-slpi-pinctrl.dtsi index 2dfaa98271d3..6ddc10b4dc0c 100644 --- a/qcom/sm8150-slpi-pinctrl.dtsi +++ b/qcom/sm8150-slpi-pinctrl.dtsi @@ -1,7 +1,7 @@ &soc { - slpi_tlmm: slpi_pinctrl@02B40000 { + slpi_tlmm: slpi_pinctrl@2b40000 { compatible = "qcom,slpi-pinctrl"; - reg = <0x2B40000 0x20000>; + reg = <0x2b40000 0x20000>; clock-names = "ssc-clk"; clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; qcom,num-pins = <14>; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 719f983fc39f..10fb995559ec 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -525,7 +525,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -533,7 +533,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 6 0x4>; @@ -1105,7 +1105,7 @@ status = "disabled"; }; - cpucc: syscon@182a0018 { + cpucc: syscon@182a0000 { compatible = "syscon"; reg = <0x182a0000 0x4>; }; @@ -1240,7 +1240,7 @@ thermal_zones: thermal-zones { }; - osm_l3: interconnect@0x18321000 { + osm_l3: interconnect@18321000 { reg = <0x18321000 0x1400>; compatible = "qcom,sm8150-osm-l3"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; @@ -2228,7 +2228,7 @@ mbox-names = "slpi-pil"; }; - qcom,spss@1880000 { + qcom,spss@188101c { compatible = "qcom,pil-tz-generic"; reg = <0x188101c 0x4>, <0x1881024 0x4>, From 6620ffb5e41c8a71d2cbaa77381a110734efda6c Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:48:49 +0530 Subject: [PATCH 1409/1809] dt-bindings: interconnect: add interconnect bindings Add interconnect device bindings. These devices can be used to describe any RPM and NoC based interconnect devices. Change-Id: I0b43484a4763a1e31b0df039233d4b7ae10a934f --- bindings/interconnect/qcom,qrb2210-rb1.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 bindings/interconnect/qcom,qrb2210-rb1.txt diff --git a/bindings/interconnect/qcom,qrb2210-rb1.txt b/bindings/interconnect/qcom,qrb2210-rb1.txt new file mode 100644 index 000000000000..2ffb5a2cb5f0 --- /dev/null +++ b/bindings/interconnect/qcom,qrb2210-rb1.txt @@ -0,0 +1,46 @@ +QTI SCUBA Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,scuba-bimc", + "qcom,scuba-system_noc", + "qcom,scuba-config_noc", + "qcom,scuba-clk_virt", + "qcom,scuba-mmnrt_virt", + "qcom,scuba-mmrt_virt", +- #interconnect-cells : should contain 1 + +reg : specifies the physical base address and size of registers +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus" and "bus_a" + +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + +Examples: + +soc { + ... + system_noc: interconnect@1880000 { + reg = <0x1880000 0x60200>; + compatible = "qcom,scuba-system_noc"; + qcom,util-factor = <142>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x1900000 0x8200>; + compatible = "qcom,scuba-config_noc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; +}; From 39cbf4c516570a478afe6a84954d390232ba680f Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Sun, 9 May 2021 11:35:34 +0530 Subject: [PATCH 1410/1809] bindings: clock: Add support for SCUBA clock controllers Update the GCC, GPUCC, DISPCC, RPMCC and DEBUGCC controllers bindings for SCUBA. Change-Id: I4c2f325c0c677e2f0fa457d809dbbaf21be60d3f --- bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 1 + bindings/clock/qcom,rpmcc.txt | 1 + 5 files changed, 5 insertions(+) diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 3b898dc10040..2b46f69dacf9 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,monaco-debugcc" "qcom,direwolf-debugcc" "qcom,blair-debugcc" + "qcom,scuba-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index c1ee76347304..4cf54ffff090 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -18,6 +18,7 @@ Required properties : "qcom,sa6155-dispcc" "qcom,monaco-dispcc" "qcom,blair-dispcc" + "qcom,scuba-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index b0919e3137e0..9f64f68d09a0 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -40,6 +40,7 @@ Required properties : "qcom,monaco-gcc" "qcom,direwolf-gcc" "qcom,blair-gcc" + "qcom,scuba-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 03535db55849..5428d95f6bf8 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -14,6 +14,7 @@ Required properties : "qcom,sa6155-gpucc". "qcom,monaco-gpucc" "qcom,blair-gpucc" + "qcom,scuba-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index 4799e44a087e..b85e846a53b2 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -21,6 +21,7 @@ Required properties : "qcom,rpmcc-holi", "qcom,rpmcc" "qcom,rpmcc-sdxnightjar", "qcom,rpmcc" "qcom,rpmcc-monaco", "qcom,rpmcc" + "qcom,rpmcc-scuba", "qcom,rpmcc" - #clock-cells : shall contain 1 From 5a8b0d19a541fc6fb5b404bc01dcb8af41f2b26a Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Mon, 10 May 2021 14:59:03 +0530 Subject: [PATCH 1411/1809] ARM: dts: msm: Adding missing dump entries in blair Adding missing l2_caches and l1_i/dtlb entries and correcting dump size in l2_tlb nodes in blair mem-dump node. Change-Id: If3070227d19b719b82e511101bd98f3dcebf6d85 --- qcom/blair.dtsi | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 4ef0dd0b6c34..56ee7908ee56 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -766,33 +766,63 @@ qcom,dump-id = <0x87>; }; + l1_itlb102 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb103 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb102 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb103 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x47>; + }; + + l2_cache102 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache103 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc7>; + }; + l2_tlb0 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x120>; }; l2_tlb1 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x121>; }; l2_tlb2 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x122>; }; l2_tlb3 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x123>; }; l2_tlb100 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x124>; }; l2_tlb101 { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5b00>; qcom,dump-id = <0x125>; }; From 2879256a5fb028ba63a3ee8b0a44040aa22740a9 Mon Sep 17 00:00:00 2001 From: Shumin Qiu Date: Tue, 20 Apr 2021 19:54:51 +0800 Subject: [PATCH 1412/1809] ARM: dts: msm: Add dtsi security nodes for direwolf gvm Add qseecom node and shmbridge node. Change-Id: I7065876d5f9ecf133bf804838a8b783b25e2fa02 --- qcom/direwolf-vm.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 3760385d1972..ee8eb40d0532 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -178,6 +178,23 @@ ; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@c1800000 { + compatible = "qcom,qseecom"; + reg = <0xc1800000 0x3900000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + msm_gpu_hyp: qcom,hgsl { compatible = "qcom,hgsl"; From 4bed0b5cc083ac450282f10f34c7bcb38c43c8c1 Mon Sep 17 00:00:00 2001 From: Yingjie Zhu Date: Fri, 14 May 2021 16:09:47 +0800 Subject: [PATCH 1413/1809] ARM: dts: msm: adjust S4C voltage To adjust QCA6390, increase S4C output voltage to 1.37v. Change-Id: Iff7443063e1f8e0e06a9f6936ed95c4d692015d4 --- qcom/sa8155-vm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 60d50ca07a64..bc1abaccb37b 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -212,7 +212,7 @@ wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; @@ -715,7 +715,7 @@ /* */ qcom,bt-vdd-aon-config = <1055000 1055000 0 0>; - qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>; + qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>; qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>; qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>; }; From a3e413264e5ff18498407d3ce379853766414813 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 13 May 2021 15:30:06 +0530 Subject: [PATCH 1414/1809] ARM: dts: msm: Add UFS support for blair platforms This change add UFS support for blair platforms. Change-Id: Ie0a2aacf320e840e2fa178cfb75ef51b227ffe77 --- qcom/blair-atp.dtsi | 4 ++++ qcom/blair-cdp.dtsi | 4 ++++ qcom/blair-mtp.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 31a7cfb8f289..727f08b8c005 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -183,6 +183,10 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; +}; + #include "pm6350-rpm-regulator.dtsi" #include "pm6150l-rpm-regulator.dtsi" #include "holi-regulators-pm6350.dtsi" diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 1485ffe26a9e..0cec1c66625e 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,3 +1,7 @@ #include "holi-cdp-pm6125.dtsi" / { }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; +}; diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 5b6c4bff59a4..e76628a3375e 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -1,3 +1,7 @@ #include "holi-mtp-pm6125.dtsi" / { }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; +}; From b76dde329836b233095aea73668fe4af6e123147 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 11 May 2021 16:05:03 +0530 Subject: [PATCH 1415/1809] ARM: dts: msm: Add Superspeed PHY node on blair Add Superspeed PHY node and the corresponding resources to support USB superspeed on blair. Change-Id: I63614815acd8848d05ae16e1db415226ec435077 --- qcom/blair-usb.dtsi | 201 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 198 insertions(+), 3 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index c4b51bce7d5e..e5d935f4bcf9 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { /* Primary USB port related controller */ @@ -7,13 +8,16 @@ reg = <0x4e00000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xe0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = , , - ; + ; interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -42,14 +46,13 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,gsi-disable-io-coherency; - extcon = <&eud>; dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xcd00>; interrupt-parent = <&intc>; interrupts = ; - usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; @@ -88,9 +91,201 @@ 0x17 0x74>; /* override x2 */ }; + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@1630000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x1630000 0x3000>; + reg-names = "qmp_phy_base"; + vdd-supply = <&L18A>; + qcom,vdd-voltage-level = <0 880000 880000>; + core-supply = <&L4A>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x0af 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; }; From 1ec72c6a0d0644bed96434759f5eb0d8d0e04f8e Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Thu, 22 Apr 2021 22:00:56 +0530 Subject: [PATCH 1416/1809] ARM: dts: qcom: add audio device tree source files Add audio device tree source files for A + S. Add gpio for A + S. Change-Id: I666b45cc261f5a641c3c6f6ddb1626e5bdff8c35 --- qcom/monaco-lpi.dtsi | 150 ++++++++++++++++++++++ qcom/monaco-slate-amic-audio-overlay.dtsi | 3 + qcom/monaco-slate-audio-overlay.dtsi | 3 + qcom/monaco-slate-audio.dtsi | 22 ++++ qcom/monaco-slate-wsa-audio-overlay.dtsi | 3 + 5 files changed, 181 insertions(+) create mode 100644 qcom/monaco-slate-amic-audio-overlay.dtsi create mode 100644 qcom/monaco-slate-audio-overlay.dtsi create mode 100644 qcom/monaco-slate-audio.dtsi create mode 100644 qcom/monaco-slate-wsa-audio-overlay.dtsi diff --git a/qcom/monaco-lpi.dtsi b/qcom/monaco-lpi.dtsi index 1ab89ed940ee..2d3a5134c2b0 100644 --- a/qcom/monaco-lpi.dtsi +++ b/qcom/monaco-lpi.dtsi @@ -126,6 +126,36 @@ }; }; + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio3"; + function = "func2"; + }; + + config { + pins = "gpio3"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + tx_swr_clk_sleep: tx_swr_clk_sleep { mux { pins = "gpio0"; @@ -373,5 +403,125 @@ input-enable; }; }; + + lpi_i2s1_sck { + lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sck_active: lpi_i2s1_sck_active { + mux { + pins = "gpio6"; + function = "func2"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_ws { + lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_ws_active: lpi_i2s1_ws_active { + mux { + pins = "gpio7"; + function = "func2"; + }; + + config { + pins = "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd0 { + lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd0_active: lpi_i2s1_sd0_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + lpi_i2s1_sd1 { + lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + lpi_i2s1_sd1_active: lpi_i2s1_sd1_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; }; }; diff --git a/qcom/monaco-slate-amic-audio-overlay.dtsi b/qcom/monaco-slate-amic-audio-overlay.dtsi new file mode 100644 index 000000000000..84e2805e50af --- /dev/null +++ b/qcom/monaco-slate-amic-audio-overlay.dtsi @@ -0,0 +1,3 @@ +&monaco_snd { + qcom,model = "monaco-idp-slate_amic-snd-card"; +}; diff --git a/qcom/monaco-slate-audio-overlay.dtsi b/qcom/monaco-slate-audio-overlay.dtsi new file mode 100644 index 000000000000..113be86490d1 --- /dev/null +++ b/qcom/monaco-slate-audio-overlay.dtsi @@ -0,0 +1,3 @@ +&monaco_snd { + qcom,model = "monaco-idp-slate-snd-card"; +}; diff --git a/qcom/monaco-slate-audio.dtsi b/qcom/monaco-slate-audio.dtsi new file mode 100644 index 000000000000..4b1549f1781c --- /dev/null +++ b/qcom/monaco-slate-audio.dtsi @@ -0,0 +1,22 @@ +#include +#include "msm-audio-lpass.dtsi" + +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; +}; + +#include "monaco-lpi.dtsi" + +&spf_core_platform { + monaco_snd: sound { + compatible = "qcom,monaco-asoc-snd"; + qcom,mi2s-audio-intf = <1>; + }; +}; + +&msm_audio_ion { + iommus = <&apps_smmu 0x01c1 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; diff --git a/qcom/monaco-slate-wsa-audio-overlay.dtsi b/qcom/monaco-slate-wsa-audio-overlay.dtsi new file mode 100644 index 000000000000..f184ffaa1f71 --- /dev/null +++ b/qcom/monaco-slate-wsa-audio-overlay.dtsi @@ -0,0 +1,3 @@ +&monaco_snd { + qcom,model = "monaco-idp-slate_wsa-snd-card"; +}; From 4a5dc080d708586f5bf1ffa16e3c443f587bd84b Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 17:36:53 +0530 Subject: [PATCH 1417/1809] ARM: dts: msm: Add clock controller nodes for SCUBA Add GCC/GPUCC/DISPCC/DEBUGCC/RPMCC/GDSC clock controller nodes for SCUBA and also add CPUFREQ HW node to scale the cpu frequency. Change-Id: Icb621342412e03d299d18f8cf05ba1f681c859b1 --- qcom/qrb2210-rb1-gdsc.dtsi | 111 ++++++++++++++++++++++++++++ qcom/qrb2210-rb1-idp.dtsi | 2 + qcom/qrb2210-rb1.dtsi | 143 +++++++++++++++++++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 qcom/qrb2210-rb1-gdsc.dtsi diff --git a/qcom/qrb2210-rb1-gdsc.dtsi b/qcom/qrb2210-rb1-gdsc.dtsi new file mode 100644 index 000000000000..34a178aaf977 --- /dev/null +++ b/qcom/qrb2210-rb1-gdsc.dtsi @@ -0,0 +1,111 @@ +&soc { + /* GDSCs in GCC */ + gcc_camss_top_gdsc: qcom,gdsc@1458004 { + compatible = "qcom,gdsc"; + reg = <0x1458004 0x4>; + regulator-name = "gcc_camss_top_gdsc"; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@141a004 { + compatible = "qcom,gdsc"; + reg = <0x141a004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@1458098 { + compatible = "qcom,gdsc"; + reg = <0x1458098 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@145807c { + compatible = "qcom,gdsc"; + reg = <0x145807c 0x4>; + regulator-name = "gcc_venus_gdsc"; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { + compatible = "qcom,gdsc"; + reg = <0x147d074 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { + compatible = "qcom,gdsc"; + reg = <0x147d078 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 { + compatible = "qcom,gdsc"; + reg = <0x147d060 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c { + compatible = "qcom,gdsc"; + reg = <0x147d07c 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in DISPCC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "qcom,gdsc"; + reg = <0x5f03000 0x4>; + regulator-name = "mdss_core_gdsc"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + /* GDSCs in GPUCC */ + gpu_cx_hw_ctrl: syscon@5991540 { + compatible = "syscon"; + reg = <0x5991540 0x4>; + }; + + gpu_gx_sw_reset: syscon@5991008 { + compatible = "syscon"; + reg = <0x5991008 0x4>; + }; + + gpu_gx_domain_addr: syscon@5991508 { + compatible = "syscon"; + reg = <0x5991508 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@599106c { + compatible = "qcom,gdsc"; + reg = <0x599106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599100c { + compatible = "qcom,gdsc"; + reg = <0x599100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + sw-reset = <&gpu_gx_sw_reset>; + domain-addr = <&gpu_gx_domain_addr>; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff --git a/qcom/qrb2210-rb1-idp.dtsi b/qcom/qrb2210-rb1-idp.dtsi index 6a6c301959cb..5f0cc45e0530 100644 --- a/qcom/qrb2210-rb1-idp.dtsi +++ b/qcom/qrb2210-rb1-idp.dtsi @@ -1,3 +1,5 @@ +#include +#include #include #include #include "qrb2210-rb1-ion.dtsi" diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 480a441b3dec..87850bf65bcb 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -3,6 +3,10 @@ #include #include #include +#include +#include +#include +#include / { model = "Qualcomm Technologies, Inc. Qrb2210 RB1"; @@ -41,6 +45,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -63,6 +68,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; @@ -81,6 +87,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; @@ -99,6 +106,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; @@ -611,6 +619,93 @@ dcc: dcc_v2@1be2000 { }; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-scuba"; + #clock-cells = <1>; + }; + + gcc: qcom,gcc@1400000 { + compatible = "qcom,scuba-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: qcom,dispcc@5f00000 { + compatible = "qcom,scuba-dispcc", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "cfg_ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: qcom,gpucc@5990000 { + compatible = "qcom,scuba-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + /*qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;*/ + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mccc_debug: syscon@447d200 { + compatible = "syscon"; + reg = <0x447d200 0x100>; + }; + + cpucc_debug: syscon@f11101c { + compatible = "syscon"; + reg = <0xf11101c 0x4>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,scuba-debugcc"; + status = "disabled"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc_debug>; + qcom,cpucc = <&cpucc_debug>; + clock-names = "xo_clk_src"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw"; + reg = <0xf521000 0x1400>; + reg-names = "freq-domain0"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; + qcom,max-lut-entries = <12>; + #freq-domain-cells = <2>; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, @@ -1050,6 +1145,8 @@ dcc: dcc_v2@1be2000 { #include "qrb2210-rb1-pinctrl.dtsi" #include "qrb2210-rb1-ion.dtsi" #include "msm-arm-smmu-qrb2210-rb1.dtsi" +#include "qrb2210-rb1-qupv3.dtsi" +#include "qrb2210-rb1-gdsc.dtsi" &qupv3_se1_i2c { #address-cells = <1>; @@ -1160,6 +1257,52 @@ dcc: dcc_v2@1be2000 { }; }; +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; + &pm2250_vadc { #address-cells = <1>; #size-cells = <0>; From a7ebddfcb22254301db764e5b3081a62152829f1 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Thu, 22 Apr 2021 23:25:35 +0530 Subject: [PATCH 1418/1809] ARM: dts: msm: Include display nodes for yupik idp with PM7250B Include display nodes for yupik idp variant with PM7250B replacing PM7325B and add panel property to enable touch for this platform. Change-Id: I73d6e91b18e0b7e2f53f76315731fb91719056ad --- qcom/yupik-idp-pm7250b.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik-idp-pm7250b.dtsi b/qcom/yupik-idp-pm7250b.dtsi index 9ac085eb5f88..50169462583e 100644 --- a/qcom/yupik-idp-pm7250b.dtsi +++ b/qcom/yupik-idp-pm7250b.dtsi @@ -5,6 +5,7 @@ #include "pm7250b.dtsi" #include "yupik-audio-overlay.dtsi" #include "yupik-pm7250b-thermal-overlay.dtsi" +#include "display/yupik-sde-display-idp-pm7250b.dtsi" / { qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2e>; @@ -220,6 +221,10 @@ status = "ok"; }; +&pm8350c_pwm_2 { + status = "ok"; +}; + &pm8350c_switch0 { qcom,led-mask = <9>; /* Channels 1 & 4 */ qcom,symmetry-en; @@ -303,6 +308,10 @@ novatek,reset-gpio = <&tlmm 105 0x00>; novatek,irq-gpio = <&tlmm 81 0x2008>; + panel = <&dsi_nt36672e_fhd_plus_60_video + &dsi_nt36672e_fhd_plus_120_video + &dsi_nt36672e_fhd_plus_144_video>; + novatek,trusted-touch-mode = "vm_mode"; novatek,touch-environment = "pvm"; novatek,trusted-touch-spi-irq = <601>; From 2fe1bca7ea6bc9427ca0048441f1cafa01a021e7 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 4 Nov 2020 17:40:28 +0530 Subject: [PATCH 1419/1809] ARM: dts: msm: Add USB dtsi nodes for monaco Add USB dtsi nodes for monaco for USB functionality to work. Change-Id: I35aa0c455d410e8e24d0f811c94f5e47aa1dcec4 --- qcom/monaco-rumi.dtsi | 29 +++++++++ qcom/monaco-usb.dtsi | 136 ++++++++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 1 + 3 files changed, 166 insertions(+) create mode 100644 qcom/monaco-usb.dtsi diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 0d2189e70578..2ca7828f5719 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -11,6 +11,35 @@ status = "disabled"; }; + usb_emu_phy_0: usb_emu_phy@0x04f20000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x04e0e000 0x9500>; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1e0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x4 0x3c + 0x0 0x4 + 0x9 0x14>; + }; +}; + +&usb0 { + dpdm-supply = <&usb_nop_phy>; + dwc3@4e00000 { + usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; + +&usb2_phy0 { + status = "disabled"; }; &sdhc_1 { diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi new file mode 100644 index 000000000000..c49aaddce945 --- /dev/null +++ b/qcom/monaco-usb.dtsi @@ -0,0 +1,136 @@ +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: hsusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x120 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts = , + ; + interrupt-names = "pwr_event_irq", "hs_phy_irq"; + + clocks = <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB2_PRIM_CLKREF_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>; + qcom,usb-charger; + + qcom,core-clk-rate = <60000000>; + qcom,default-bus-vote = <2>; /* use svs bus voting */ + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + qcom,interconnect-values-svs = /* SVS Votes */ + <30000 70000>, + <0 2400>, + <0 40000>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <10488>; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@1613000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x1613000 0x120>, + <0x01612000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L12A>; + vdda18-supply = <&L14A>; + vdda33-supply = <&L25A>; + qcom,vdd-voltage-level = <0 904000 904000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = + <0x63 0x6c /* override_x0 */ + 0xC8 0x70 /* override_x1 */ + 0x17 0x74>; /* override x2 */ + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 93697a91f5fc..8a75aa2adcd9 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1235,6 +1235,7 @@ #include "monaco-qupv3.dtsi" #include "monaco-pm.dtsi" #include "monaco-audio.dtsi" +#include "monaco-usb.dtsi" &qupv3_se6_2uart { status = "ok"; From 327a03e9f9e0aee9a12ed046ed22fb989fbe58ae Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 7 May 2021 15:09:54 +0530 Subject: [PATCH 1420/1809] ARM: dts: msm: Update clock handles for PCIE nodes GCC_PCIE_REF_CLK_EN is not applicable to PCIe 2nd instance and hence update it correctly. Also update missing clock handle for PCIe 1st instance. Change-Id: I8303e80c0dda09a51dca4a99fa57923a874d8c8f --- qcom/yupik-pcie.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 557d9d49725f..83133d79f313 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -79,10 +79,11 @@ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, <&pcie_0_pipe_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", @@ -92,6 +93,7 @@ "pcie_ddrss_sf_tbu_clk", "pcie_aggre_noc_0_axi_clk", "pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_pipe_clk_ext_src"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>, @@ -347,7 +349,7 @@ <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, From e00d5a7a75839e6b777a44c0d3a45111d79d73c3 Mon Sep 17 00:00:00 2001 From: Kuichu Ni Date: Thu, 13 May 2021 18:34:08 +0800 Subject: [PATCH 1421/1809] ARM: dts: qcom: Fix three issues in WLAN converged node 1. Rename vdd-wlan-aon-supply to vdd-wlan-vl-supply to avoid be deleted by other platform. Change rfa1/rfa2/rfa3 to vm/sXX/vh as well for sa81x5, sa6155 and lxc-vm platform. This issue was introducted from commit e9d3bea38, and the regulator of "vdd-wlan-aon" will be revmoved from vreg_list in cnss_disable_redundant_vreg(). 2. Set unvote flag to 0 to keep fixed voltage for AUTO platform. This issue was introduced from the commit 65413acfe6, and some LDOs were unvoted after receiving FW ready. This is unexpected behavior for the AUTO platform, so that set the need_unvote to 0. 3. Add "address-cells" and "size-cells" property in pcie_rc0 for sa81x5 and sa6155 platform. Change-Id: I365c773a48ac436ac4d09518c242fdd587b64064 --- qcom/sa6155-cnss.dtsi | 14 +++--- qcom/sa8155-cnss.dtsi | 35 +++++++-------- qcom/sa8195-vm-lv-cnss-lxc.dtsi | 76 ++++++++++++++++----------------- qcom/sa8195p-cnss.dtsi | 34 ++++++++------- 4 files changed, 82 insertions(+), 77 deletions(-) diff --git a/qcom/sa6155-cnss.dtsi b/qcom/sa6155-cnss.dtsi index 335a6937ce2b..714260e59740 100644 --- a/qcom/sa6155-cnss.dtsi +++ b/qcom/sa6155-cnss.dtsi @@ -87,9 +87,9 @@ supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 0>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -195,9 +195,9 @@ supported-ids = <0x1102>; wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1350000 1350000 0 0 0>; + qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-rfa3-config = <1904000 1904000 0 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -307,6 +307,8 @@ }; &pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; cnss_pci: cnss_pci { reg = <0 0 0 0 0>; qcom,iommu-group = <&cnss_pci_iommu_group>; diff --git a/qcom/sa8155-cnss.dtsi b/qcom/sa8155-cnss.dtsi index a21d999a9444..8ab651c9faff 100644 --- a/qcom/sa8155-cnss.dtsi +++ b/qcom/sa8155-cnss.dtsi @@ -65,10 +65,10 @@ vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; vdd-wlan-supply = <&vreg_wlan>; - vdd-wlan-aon-supply = <&pm8150_1_s6>; - vdd-wlan-rfa1-supply = <&pm8150_2_s4>; - vdd-wlan-rfa2-supply = <&pm8150_2_s5>; - vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + vdd-wlan-vl-supply = <&pm8150_1_s6>; + vdd-wlan-vm-supply = <&pm8150_2_s4>; + vdd-wlan-s5c-supply = <&pm8150_2_s5>; + vdd-wlan-vh-supply = <&pm8150_2_l15>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; @@ -94,13 +94,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; - + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1055000 1055000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; mhi,timeout = <10000>; @@ -205,12 +204,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1055000 1055000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -321,6 +320,8 @@ }; &pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; cnss_pci: cnss_pci { reg = <0 0 0 0 0>; qcom,iommu-group = <&cnss_pci_iommu_group>; diff --git a/qcom/sa8195-vm-lv-cnss-lxc.dtsi b/qcom/sa8195-vm-lv-cnss-lxc.dtsi index f1c1fbf2095a..72a2a2cb1c2c 100644 --- a/qcom/sa8195-vm-lv-cnss-lxc.dtsi +++ b/qcom/sa8195-vm-lv-cnss-lxc.dtsi @@ -50,14 +50,14 @@ vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; vdd-wlan-supply = <&vreg_wlan>; - vdd-wlan-aon-supply = <&pm8195_1_s5>; - vdd-wlan-rfa1-supply = <&pm8195_1_s2>; - vdd-wlan-rfa2-supply = <&pm8195_2_s5>; - vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + vdd-wlan-vl-supply = <&pm8195_1_s5>; + vdd-wlan-vm-supply = <&pm8195_1_s2>; + vdd-wlan-s5c-supply = <&pm8195_2_s5>; + vdd-wlan-vh-supply = <&pm8195_2_l7>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; - qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; - qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; wlan-en-gpio = <&tlmm 169 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; @@ -70,7 +70,7 @@ supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; - qcom,vdd-wlan-info = <0 0 0 10>; + qcom,vdd-wlan-config = <0 0 0 10 1>; qcom,wlan-ramdump-dynamic = <0x200000>; }; @@ -80,12 +80,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1000000 1000000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -191,12 +191,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1000000 1000000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x300000>; mhi,max-channels = <30>; @@ -315,14 +315,14 @@ vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; vdd-wlan-supply = <&vreg_wlan>; - vdd-wlan-aon-supply = <&pm8195_1_s5>; - vdd-wlan-rfa1-supply = <&pm8195_1_s2>; - vdd-wlan-rfa2-supply = <&pm8195_2_s5>; - vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + vdd-wlan-vl-supply = <&pm8195_1_s5>; + vdd-wlan-vm-supply = <&pm8195_1_s2>; + vdd-wlan-s5c-supply = <&pm8195_2_s5>; + vdd-wlan-vh-supply = <&pm8195_2_l7>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; - qcom,vdd-wlan-ctrl1-config = <0 0 0 0>; - qcom,vdd-wlan-ctrl2-config = <0 0 0 0>; + qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; + qcom,vdd-wlan-ctrl2-config = <0 0 0 0 0>; wlan-en-gpio = <&tlmm 170 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active2>; @@ -334,7 +334,7 @@ supported-ids = <0x003e>; wlan_vregs = "vdd-wlan"; - qcom,vdd-wlan-info = <0 0 0 10>; + qcom,vdd-wlan-info = <0 0 0 10 1>; qcom,wlan-ramdump-dynamic = <0x200000>; }; @@ -344,12 +344,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1000000 1000000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -433,12 +433,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1055000 1055000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x300000>; mhi,max-channels = <30>; diff --git a/qcom/sa8195p-cnss.dtsi b/qcom/sa8195p-cnss.dtsi index f6d3076f7c5b..c4a4e6021c7c 100644 --- a/qcom/sa8195p-cnss.dtsi +++ b/qcom/sa8195p-cnss.dtsi @@ -63,10 +63,10 @@ vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; vdd-wlan-supply = <&vreg_wlan>; - vdd-wlan-aon-supply = <&pm8195_1_s5>; - vdd-wlan-rfa1-supply = <&pm8195_1_s2>; - vdd-wlan-rfa2-supply = <&pm8195_2_s5>; - vdd-wlan-rfa3-supply = <&pm8195_2_l7>; + vdd-wlan-vl-supply = <&pm8195_1_s5>; + vdd-wlan-vm-supply = <&pm8195_1_s2>; + vdd-wlan-s5c-supply = <&pm8195_2_s5>; + vdd-wlan-vh-supply = <&pm8195_2_l7>; wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; qcom,vdd-wlan-ctrl1-config = <0 0 0 0 0>; @@ -92,12 +92,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1101>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1000000 1000000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; mhi,timeout = <10000>; @@ -202,12 +202,12 @@ reg-names = "smmu_iova_ipa"; supported-ids = <0x1102>; - wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", - "vdd-wlan-rfa2", "vdd-wlan-rfa3"; - qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>; - qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>; - qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>; - qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>; + wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", + "vdd-wlan-s5c", "vdd-wlan-vh"; + qcom,vdd-wlan-vl-config = <1000000 1000000 0 0 0>; + qcom,vdd-wlan-vm-config = <1370000 1370000 0 0 0>; + qcom,vdd-wlan-s5c-config = <2040000 2040000 0 0 0>; + qcom,vdd-wlan-vh-config = <1900000 1900000 450000 0 0>; qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; @@ -317,6 +317,8 @@ }; &pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; cnss_pci: cnss_pci { reg = <0 0 0 0 0>; qcom,iommu-group = <&cnss_pci_iommu_group>; From 87c8a2379a531d8ca481eff26181ef2e4b8f0c15 Mon Sep 17 00:00:00 2001 From: Akshaya Bhat Date: Mon, 15 Mar 2021 07:49:06 +0530 Subject: [PATCH 1422/1809] ARM: dts: msm: Add initial device tree for SA2150P Add initial device tree for SA2150P target. Change-Id: I107ed97c75f15c91e94a470182d4ec749abce7a8 --- bindings/arm/msm/msm.txt | 4 + bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/Makefile | 2 + qcom/qcs405-cpu.dtsi | 114 ++++++++ qcom/qcs405-pinctrl.dtsi | 28 ++ qcom/qcs405.dtsi | 286 +++++++++++++++++++++ qcom/sa2150p-ccard-emmc.dts | 10 + qcom/sa2150p-ccard.dtsi | 1 + 8 files changed, 446 insertions(+) create mode 100644 qcom/qcs405-cpu.dtsi create mode 100644 qcom/qcs405-pinctrl.dtsi create mode 100644 qcom/qcs405.dtsi create mode 100644 qcom/sa2150p-ccard-emmc.dts create mode 100644 qcom/sa2150p-ccard.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index e993afb45b1f..f92135ac9964 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -163,6 +163,9 @@ Generic board variants: - HDK device: compatible = "qcom,hdk" +- SA2150P + compatible = "qcom,sa2150p" + Boards (SoC type + board variant): @@ -272,6 +275,7 @@ compatible = "qcom,sa6155-adp-air" compatible = "qcom,sa6155p-adp-air" compatible = "qcom,qcs405-rumi" compatible = "qcom,qcs405-iot" +compatible = "qcom,sa2150p-ccard" compatible = "qcom,qcs403-iot" compatible = "qcom,sa8150-adp-star" compatible = "qcom,adp-star" diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index 2b4beeeb7a37..dcce6028e872 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -27,6 +27,7 @@ Properties: "qcom,mpm-gic-scuba" "qcom,mpm-gic-sdxnightjar" "qcom,mpm-gic-monaco" + "qcom,mpm-gic-qcs405" - interrupts: Usage: required diff --git a/qcom/Makefile b/qcom/Makefile index 9d5d6f68bb88..dd35dd16b986 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -357,6 +357,8 @@ else dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \ sa8195p-v2-adp-air.dtb endif + +dtb-$(CONFIG_ARCH_SA2150P) += sa2150p-ccard-emmc.dtb endif ifeq ($(CONFIG_ARCH_LAHAINA), y) diff --git a/qcom/qcs405-cpu.dtsi b/qcom/qcs405-cpu.dtsi new file mode 100644 index 000000000000..07c83a54cb13 --- /dev/null +++ b/qcom/qcs405-cpu.dtsi @@ -0,0 +1,114 @@ +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + /* A53 L2 dump not supported */ + qcom,dump-size = <0x0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + }; + +}; diff --git a/qcom/qcs405-pinctrl.dtsi b/qcom/qcs405-pinctrl.dtsi new file mode 100644 index 000000000000..80d8fef22aca --- /dev/null +++ b/qcom/qcs405-pinctrl.dtsi @@ -0,0 +1,28 @@ +&soc { + tlmm: pinctrl@1000000 { + compatible = "qcom,qcs404-pinctrl"; + reg = <0x01000000 0x200000>, + <0x01300000 0x200000>, + <0x07b00000 0x200000>; + reg-names = "south", "north", "east"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 120>; + gpio-controller; + #gpio-cells = <2>; + + blsp1_uart2_default: blsp1-uart2-default { + rx { + pins = "gpio18"; + function = "blsp_uart_rx_a2"; + }; + + tx { + pins = "gpio17"; + function = "blsp_uart_tx_a2"; + }; + }; + + }; +}; diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi new file mode 100644 index 000000000000..10ff3f6bab3b --- /dev/null +++ b/qcom/qcs405.dtsi @@ -0,0 +1,286 @@ +#include +#include +#include +#include +#include + + +/ { + model = "Qualcomm Technologies, Inc. QCS405"; + compatible = "qcom,qcs405"; + qcom,msm-id = <352 0x0>, <452 0x0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &blsp1_uart2_console; + }; + + chosen { + }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + reserved_mem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_region0: removed_region@85900000 { + no-map; + reg = <0x0 0x85900000 0x0 0x600000>; + }; + + smem_region: smem@85f00000 { + no-map; + reg = <0x0 0x85f00000 0x0 0x200000>; + }; + + removed_region1: removed_region@86100000 { + no-map; + reg = <0x0 0x86100000 0x0 0x300000>; + }; + + wlan_fw_mem: wlan_fw_mem@86400000 { + no-map; + reg = <0x0 0x86400000 0x0 0x1000000>; + }; + + adsp_fw_mem: adsp_fw_mem@87400000 { + no-map; + reg = <0x0 0x87400000 0x0 0x1400000>; + }; + + cdsp_fw_mem: cdsp_fw_mem@88800000 { + no-map; + reg = <0x0 0x88800000 0x0 0x800000>; + }; + + wlan_msa_mem: wlan_msa_region@88E00000 { + no-map; + reg = <0x0 0x89000000 0x0 0x100000>; + }; + + secure_mem: secure_region { + status = "disabled"; + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x7000000>; + }; + + mdf_mem: mdf_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x400000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + linux,cma-default; + }; + }; + + soc: soc { }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-qcs405", "qcom,mpm"; + interrupts = ; + reg = <0x601b8 0x1000>, + <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + blsp1_uart2_console: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = <0 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; + status = "okay"; + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 0x4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + }; +}; + +#include "qcs405-pinctrl.dtsi" +#include "qcs405-cpu.dtsi" diff --git a/qcom/sa2150p-ccard-emmc.dts b/qcom/sa2150p-ccard-emmc.dts new file mode 100644 index 000000000000..96df6db65fc8 --- /dev/null +++ b/qcom/sa2150p-ccard-emmc.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa2150p-ccard.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA2150P CCARD EMMC"; + compatible = "qcom,sa2150p-ccard", "qcom,qcs405", "qcom,sa2150p", + "qcom,ccard"; + qcom,board-id = <25 0>, <25 0x100>; +}; diff --git a/qcom/sa2150p-ccard.dtsi b/qcom/sa2150p-ccard.dtsi new file mode 100644 index 000000000000..d6cbcc922f26 --- /dev/null +++ b/qcom/sa2150p-ccard.dtsi @@ -0,0 +1 @@ +#include "qcs405.dtsi" From 0d80ad0f74f0f0fbfa6d00b7d1f37b54f6f8c674 Mon Sep 17 00:00:00 2001 From: Xiaoning Ma Date: Fri, 26 Feb 2021 16:48:25 +0800 Subject: [PATCH 1423/1809] ARM: dts: msm: enable bluetooth for direwolf vm Add bluetooth node and related resources. Change-Id: Ib199668f780b92f03e2db59f8471b2a48d88dfeb --- qcom/direwolf-cnss.dtsi | 50 ++++++++++++++++++++++++++++++++++++++ qcom/direwolf-pinctrl.dtsi | 39 +++++++++++++++++++++++++++++ qcom/direwolf-vm.dtsi | 19 ++++++++++++--- 3 files changed, 104 insertions(+), 4 deletions(-) create mode 100644 qcom/direwolf-cnss.dtsi diff --git a/qcom/direwolf-cnss.dtsi b/qcom/direwolf-cnss.dtsi new file mode 100644 index 000000000000..a18956ca1b21 --- /dev/null +++ b/qcom/direwolf-cnss.dtsi @@ -0,0 +1,50 @@ + +&soc { + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 128 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 129 0>; + }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qcom,bt-reset-gpio = <&tlmm 126 0>; + /* PWR_CTR1_VDD_PA */ + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pm8540_e0_s4>; + qcom,bt-vdd-rfa1-supply = <&pm8540_g0_l6>; + qcom,bt-vdd-rfa2-supply = <&pm8540_a0_l15>; + + /* */ + qcom,bt-vdd-aon-config = <1055000 1055000 0 0>; + /* No vol setting for bypass LDOs */ + qcom,bt-vdd-rfa1-config = <0 0 0 0>; + qcom,bt-vdd-rfa2-config = <0 0 0 0>; + }; +}; + +&qupv3_se2_4uart { + status = "ok"; +}; + diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi index 742c12f51810..f4edf88c5890 100644 --- a/qcom/direwolf-pinctrl.dtsi +++ b/qcom/direwolf-pinctrl.dtsi @@ -1847,4 +1847,43 @@ }; }; }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + conn_power_1p8_active: conn_power_1p8_active { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + conn_power_pa_active: conn_power_pa_active { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index ee8eb40d0532..25f982d519fc 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -305,12 +305,22 @@ regulator-max-microvolt = <1260000>; }; + S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 { + regulator-name = "smpe4"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2040000>; + }; + L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 { regulator-name = "ldoa5"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <950000>; }; + L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 { + regulator-name = "ldog6"; + }; + L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 { regulator-name = "ldoa7"; regulator-min-microvolt = <1620000>; @@ -346,6 +356,10 @@ regulator-min-microvolt = <2970000>; regulator-max-microvolt = <3544000>; }; + + L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 { + regulator-name = "ldoa15"; + }; }; &firmware { @@ -359,6 +373,7 @@ #include "pm8540-vm.dtsi" #include "direwolf-vm-audio.dtsi" #include "direwolf-vm-usb.dtsi" +#include "direwolf-cnss.dtsi" &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; @@ -374,7 +389,3 @@ /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; }; - -&qupv3_se2_4uart { - status = "ok"; -}; From 840bb02b81a3bc19d3e3c6454e74b4ca6e5a7194 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:21:30 +0530 Subject: [PATCH 1424/1809] ARM: dts: msm: Add dt nodes for spi, i2c, uart for scuba add dtsi nodes for spi, i2c, uart for scuba. Change-Id: If8e200b7b2bc0630eb827685e559c53e9a5a9ebf --- qcom/qrb2210-rb1-qupv3.dtsi | 263 ++++++++++++++++++++++++++++++++++++ qcom/qrb2210-rb1.dtsi | 4 +- 2 files changed, 265 insertions(+), 2 deletions(-) create mode 100644 qcom/qrb2210-rb1-qupv3.dtsi diff --git a/qcom/qrb2210-rb1-qupv3.dtsi b/qcom/qrb2210-rb1-qupv3.dtsi new file mode 100644 index 000000000000..42d875459550 --- /dev/null +++ b/qcom/qrb2210-rb1-qupv3.dtsi @@ -0,0 +1,263 @@ +#include + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4ac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se4_2uart: qcom,qup_uart@4a90000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4a90000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@4a8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a8c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-3 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@4a94000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; +}; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 87850bf65bcb..9fb48b4af2dc 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -29,8 +29,8 @@ }; aliases { - swr0 = &swr0; - swr1 = &swr1; + serial0 = &qupv3_se4_2uart; + hsuart0 = &qupv3_se3_4uart; }; cpus { From 76e91b4aa6e5725c4b5b45218c4fbd42c7b80264 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:28:04 +0530 Subject: [PATCH 1425/1809] ARM: dts: msm: Add eMMC, SD card support for SCUBA Add eMMC, SD card support for scuba-iot. Change-Id: If37e9e04aae54753484520f3b4dbbb0fa55b832d --- qcom/qrb2210-rb1-idp.dtsi | 36 ++++++ qcom/qrb2210-rb1-pinctrl.dtsi | 228 +++++++++++++++------------------- qcom/qrb2210-rb1.dtsi | 152 +++++++++++++++++++++++ 3 files changed, 285 insertions(+), 131 deletions(-) diff --git a/qcom/qrb2210-rb1-idp.dtsi b/qcom/qrb2210-rb1-idp.dtsi index 5f0cc45e0530..18399c7871d2 100644 --- a/qcom/qrb2210-rb1-idp.dtsi +++ b/qcom/qrb2210-rb1-idp.dtsi @@ -12,6 +12,42 @@ }; }; +&sdhc_1 { + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L21A>; + qcom,vdd-voltage-level = <2960000 3300000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L4A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + &pm2250_qg { qcom,battery-data = <&scuba_batterydata>; qcom,qg-iterm-ma = <150>; diff --git a/qcom/qrb2210-rb1-pinctrl.dtsi b/qcom/qrb2210-rb1-pinctrl.dtsi index e292ad133313..901f47d21ad1 100644 --- a/qcom/qrb2210-rb1-pinctrl.dtsi +++ b/qcom/qrb2210-rb1-pinctrl.dtsi @@ -37,139 +37,105 @@ }; }; /* SDC pin type */ - sdc1_clk_on: sdc1_clk_on { - config { + sdc1_on: sdc1_on { + clk { pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc1_clk_off: sdc1_clk_off { - config { - pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_cmd_on: sdc1_cmd_on { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc1_cmd_off: sdc1_cmd_off { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_data_on: sdc1_data_on { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc1_data_off: sdc1_data_off { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_rclk_on: sdc1_rclk_on { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc1_rclk_off: sdc1_rclk_off { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cd_on: cd_on { - mux { - pins = "gpio88"; - function = "gpio"; - }; - - config { - pins = "gpio88"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - sdc2_cd_off: cd_off { - mux { - pins = "gpio88"; - function = "gpio"; - }; - - config { - pins = "gpio88"; - drive-strength = <2>; bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio88"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio88"; + bias-disable; + drive-strength = <2>; }; }; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 9fb48b4af2dc..89dee2890d18 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -31,6 +31,8 @@ aliases { serial0 = &qupv3_se4_2uart; hsuart0 = &qupv3_se3_4uart; + sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ }; cpus { @@ -487,6 +489,156 @@ thermal_zones: thermal-zones { }; + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <78 512 0 0>, <1 606 0 0>, + /* 400 KB/s*/ + <78 512 1046 1600>, + <1 606 1600 1600>, + /* 20 MB/s */ + <78 512 20480 80000>, + <1 606 80000 80000>, + /* 25 MB/s */ + <78 512 25600 250000>, + <1 606 50000 133320>, + /* 50 MB/s */ + <78 512 51200 250000>, + <1 606 65000 133320>, + /* 100 MB/s */ + <78 512 102400 250000>, + <1 606 65000 133320>, + /* 200 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* 400 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* Max. bandwidth */ + <78 512 1338562 4096000>, + <1 606 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + max-frequency = <192000000>; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "core", "iface"; + + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 3200>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 250000>, + <1 608 80000 133320>, + /* 25 MB/s */ + <81 512 65360 250000>, + <1 608 100000 133320>, + /* 50 MB/s */ + <81 512 130718 250000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 250000>, + <1 608 150000 133320>, + /* 200 MB/s */ + <81 512 261438 800000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + + bus-width = <4>; + + iommus = <&apps_smmu 0xA0 0x0>; + qcom,iommu-dma = "bypass"; + + no-mmc; + no-sdio; + max-frequency = <202000000>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; From 8006e6d1e255dea55843a3e00e26070c999dc860 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:36:08 +0530 Subject: [PATCH 1426/1809] ARM: dts: msm: Update kgsl smmu clock for scuba Update clock and vdd for KGSL smmu for scuba. Change-Id: Id0f9dd5661963070b10e9ed008b5143215dff493 --- qcom/msm-arm-smmu-qrb2210-rb1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi index bb960362ef1a..9bd8921aef7a 100644 --- a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi +++ b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi @@ -12,6 +12,15 @@ qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; ranges; interrupts = , @@ -148,6 +157,7 @@ qcom,stream-id-range = <0x400 0x400>; interrupts = ; qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; @@ -163,6 +173,7 @@ qcom,stream-id-range = <0x800 0x400>; interrupts = ; qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; From 33629e60bf24903edb186b7a251ca8fe692623f2 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:40:36 +0530 Subject: [PATCH 1427/1809] ARM: dts: msm: Update SMMU Interconnect for scuba iot Update SMMU Interconnect for scuba iot. Change-Id: I72b30a9225bc39abd66316ce3ea9866e4f417607 --- qcom/msm-arm-smmu-qrb2210-rb1.dtsi | 41 +++++++++++++++-------------- qcom/qrb2210-rb1.dtsi | 42 ++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 20 deletions(-) diff --git a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi index 9bd8921aef7a..39747390a54a 100644 --- a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi +++ b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi @@ -124,10 +124,10 @@ , , ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; + + interconnects = <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; qcom,actlr = /* For rt TBU +3 deep PF */ @@ -142,10 +142,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; interrupts = ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_IMEM_CFG>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; @@ -155,14 +156,14 @@ <0xc782208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - + interrupts = ; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 + &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { @@ -171,14 +172,14 @@ <0xc782210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - + interrupts = ; + interconnects = <&mmnrt_virt MASTER_CAMNOC_SF + &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; }; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 89dee2890d18..8538e991b26d 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1289,6 +1289,44 @@ dcc: dcc_v2@1be2000 { "qcom,smp2p-early-crash-ind"; }; }; + + clk_virt: interconnect { + compatible = "qcom,scuba-clk_virt"; + #interconnect-cells = <1>; + }; + + mmnrt_virt: interconnect@0 { + compatible = "qcom,scuba-mmnrt_virt"; + #interconnect-cells = <1>; + }; + + mmrt_virt: interconnect@1 { + compatible = "qcom,scuba-mmrt_virt"; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1880000 { + reg = <0x01880000 0x60200>; + compatible = "qcom,scuba-system_noc"; + #interconnect-cells = <1>; + }; + + config_noc: interconnect@1900000 { + reg = <0x01900000 0x8200>; + compatible = "qcom,scuba-config_noc"; + #interconnect-cells = <1>; + }; + + bimc: interconnect@4480000 { + reg = <0x04480000 0x80000>; + compatible = "qcom,scuba-bimc"; + #interconnect-cells = <1>; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + }; #include "pm2250.dtsi" @@ -1584,3 +1622,7 @@ dcc: dcc_v2@1be2000 { }; }; }; + +&qupv3_se4_2uart { + status = "ok"; +}; From b915ad2e054788b93c9a747ddf5f3fef496d9a5a Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:43:23 +0530 Subject: [PATCH 1428/1809] ARM: dts: msm: add stub interconnect devices for Scuba Add stub interconnect devices for cnoc, snoc, bimc, qup_virt, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I4d7b831a26a2652a81b47bfeba230c0090955188 --- qcom/qrb2210-rb1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 8538e991b26d..8a29cb7466e9 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1,4 +1,6 @@ #include +#include +#include #include #include #include From 438d6a394c5b6361f9eaf1313a2bf44ac6d98b45 Mon Sep 17 00:00:00 2001 From: Yuxin Feng Date: Tue, 20 Apr 2021 11:38:30 +0530 Subject: [PATCH 1429/1809] ARM: dts: msm: Add USB nodes for Scuba Add required USB nodes for scuba USB functionality to work. Change-Id: I07217f337f211be2cc76d5389d71efe0a36ce661 --- qcom/qrb2210-rb1-usb.dtsi | 299 ++++++++++++++++++++++++++++++++++++++ qcom/qrb2210-rb1.dtsi | 1 + 2 files changed, 300 insertions(+) create mode 100644 qcom/qrb2210-rb1-usb.dtsi diff --git a/qcom/qrb2210-rb1-usb.dtsi b/qcom/qrb2210-rb1-usb.dtsi new file mode 100644 index 000000000000..a1e96689f6d8 --- /dev/null +++ b/qcom/qrb2210-rb1-usb.dtsi @@ -0,0 +1,299 @@ +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0120 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = , + , + ; + interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,gsi-disable-io-coherency; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_qmp_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@1613000 { + compatible = "qcom,qusb2phy"; + reg = <0x01613000 0x180>, + <0x003cb250 0x4>, + <0x01b40258 0x4>, + <0x01612000 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "eud_enable_reg"; + + vdd-supply = <&pm2250_l12>; + vdda18-supply = <&pm2250_l13>; + vdda33-supply = <&pm2250_l21>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@1615000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x01615000 0x1000>, + <0x03cb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm2250_l12>; + core-supply = <&pm2250_l13>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_USB_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1cf 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; +}; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 8a29cb7466e9..8046d16978dd 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1339,6 +1339,7 @@ dcc: dcc_v2@1be2000 { #include "msm-arm-smmu-qrb2210-rb1.dtsi" #include "qrb2210-rb1-qupv3.dtsi" #include "qrb2210-rb1-gdsc.dtsi" +#include "qrb2210-rb1-usb.dtsi" &qupv3_se1_i2c { #address-cells = <1>; From 899b907f8696da047c43e875901378255c783141 Mon Sep 17 00:00:00 2001 From: Yuxin Feng Date: Sun, 25 Apr 2021 07:12:37 +0530 Subject: [PATCH 1430/1809] ARM: dts: msm: Enable usb host for scuba Add extcon for usb qusb_phy0 and usb0 Change-Id: I114edc610532740748db76c980cce754a45205e7 --- qcom/pm8008.dtsi | 127 ++++++++++++++++++++++++++++++++++++ qcom/qrb2210-rb1-idp.dtsi | 8 +++ qcom/qrb2210-rb1-usb.dtsi | 9 +++ qcom/qrb2210-rb1.dtsi | 133 ++++++++++---------------------------- 4 files changed, 177 insertions(+), 100 deletions(-) create mode 100644 qcom/pm8008.dtsi diff --git a/qcom/pm8008.dtsi b/qcom/pm8008.dtsi new file mode 100644 index 000000000000..07c8824e2c70 --- /dev/null +++ b/qcom/pm8008.dtsi @@ -0,0 +1,127 @@ +#include + +pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + interrupt-names = "pm8008"; + qcom,periph-map = <0x09 0x24 0xc0 0xc1>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + interrupts = <0x09 4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ocp"; + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + + pm8008_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x200>; + interrupts = <0xc0 0 IRQ_TYPE_EDGE_RISING>, + <0xc1 0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pm8008_gpio1", "pm8008_gpio2"; + gpio-controller; + #gpio-cells = <2>; + + pm8008_gpio1_active: pm8008_gpio1_active { + pins = "gpio1"; + function = "func1"; + power-source = <1>; + output-enable; + input-disable; + bias-disable; + }; + }; +}; + +pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_gpio1_active>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + pm8008_en-supply = <&PM8008_EN>; + qcom,enable-ocp-broadcast; + + L1P: qcom,pm8008-l1@4000 { + reg = <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4400 { + reg = <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4400 { + reg = <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + }; +}; diff --git a/qcom/qrb2210-rb1-idp.dtsi b/qcom/qrb2210-rb1-idp.dtsi index 18399c7871d2..546342256767 100644 --- a/qcom/qrb2210-rb1-idp.dtsi +++ b/qcom/qrb2210-rb1-idp.dtsi @@ -77,3 +77,11 @@ "chg_temp"; qcom,thermal-mitigation = <2000000 1500000 1000000 500000>; }; + +&qusb_phy0 { + extcon = <&pm2250_charger>; +}; + +&usb0 { + extcon = <&qusb_phy0>, <&eud>; +}; diff --git a/qcom/qrb2210-rb1-usb.dtsi b/qcom/qrb2210-rb1-usb.dtsi index a1e96689f6d8..0b8d35cc49ed 100644 --- a/qcom/qrb2210-rb1-usb.dtsi +++ b/qcom/qrb2210-rb1-usb.dtsi @@ -53,6 +53,15 @@ <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xcd00>; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 8046d16978dd..619bb26bb176 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -660,6 +660,23 @@ }; + eud: qcom,msm-eud@1610000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1610000 0x2000>, + <0x1612000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + qcom,eud-clock-vote-req; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + wdog: qcom,wdt@f017000 { compatible = "qcom,msm-watchdog"; reg = <0xf017000 0x1000>; @@ -672,7 +689,7 @@ qcom,wakeup-enable; }; -dcc: dcc_v2@1be2000 { + dcc: dcc_v2@1be2000 { compatible = "qcom,dcc-v2"; reg = <0x1be2000 0x1000>, <0x1bee000 0x2000>; @@ -688,6 +705,11 @@ dcc: dcc_v2@1be2000 { rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; @@ -1346,108 +1368,19 @@ dcc: dcc_v2@1be2000 { #size-cells = <0>; status = "ok"; - pm8008_8: qcom,pm8008@8 { - compatible = "qcom,i2c-pmic"; - reg = <0x8>; - #address-cells = <1>; - #size-cells = <0>; + #include "pm8008.dtsi" +}; - pinctrl-names = "default"; - pinctrl-0 = <&pm8008_active>; +&pm8008_8 { + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; - pm8008_chip: qcom,pm8008-chip@900 { - compatible = "qcom,pm8008-chip"; - reg = <0x900>; + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active &pm8008_interrupt>; +}; - PM8008_EN: qcom,pm8008-chip-en { - regulator-name = "pm8008-chip-en"; - }; - }; - - qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100>; - }; - }; - - pm8008_9: qcom,pm8008@9 { - compatible = "qcom,i2c-pmic"; - reg = <0x9>; - #address-cells = <1>; - #size-cells = <0>; - - pm8008_regulators: qcom,pm8008-regulator { - compatible = "qcom,pm8008-regulator"; - #address-cells = <1>; - #size-cells = <0>; - pm8008_en-supply = <&PM8008_EN>; - - vdd_l1_l2-supply = <&S3A>; - - L1P: qcom,pm8008-l1@4000 { - reg = <0x4000>; - regulator-name = "pm8008_l1"; - regulator-min-microvolt = <528000>; - regulator-max-microvolt = <1256000>; - qcom,min-dropout-voltage = <75000>; - qcom,hpm-min-load = <10000>; - }; - - L2P: qcom,pm8008-l2@4100 { - reg = <0x4100>; - regulator-name = "pm8008_l2"; - regulator-min-microvolt = <528000>; - regulator-max-microvolt = <1144000>; - qcom,min-dropout-voltage = <187500>; - qcom,hpm-min-load = <10000>; - }; - - L3P: qcom,pm8008-l3@4200 { - reg = <0x4200>; - regulator-name = "pm8008_l3"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2896000>; - qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; - }; - - L4P: qcom,pm8008-l4@4300 { - reg = <0x4300>; - regulator-name = "pm8008_l4"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2896000>; - qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; - }; - - L5P: qcom,pm8008-l5@4400 { - reg = <0x4400>; - regulator-name = "pm8008_l5"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2896000>; - qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; - }; - - L6P: qcom,pm8008-l6@4500 { - reg = <0x4500>; - regulator-name = "pm8008_l6"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2896000>; - qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; - }; - - L7P: qcom,pm8008-l7@4600 { - reg = <0x4600>; - regulator-name = "pm8008_l7"; - regulator-min-microvolt = <1656000>; - regulator-max-microvolt = <1896000>; - qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; - }; - }; - }; +&pm8008_regulators { + vdd_l1_l2-supply = <&S3A>; }; &gcc_camss_top_gdsc { From 8ec3985338abbc6bd26c9e30cd0ab3d132eedf44 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Tue, 11 May 2021 17:58:44 +0530 Subject: [PATCH 1431/1809] ARM: dts: msm: Include PM5100 PMIC for Monaco Add Mando PMIC device tree configuration for Monaco target. Change-Id: If65c209e2f1763acf8bfcfde82f0934b79fa2ce9 --- qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 93697a91f5fc..3615caf7bc94 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1226,6 +1226,7 @@ }; }; +#include "pm5100.dtsi" #include "monaco-pinctrl.dtsi" #include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" From 9170e081adc8c4d053c9faba82f919e6666aeb50 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 18 May 2021 11:59:52 +0530 Subject: [PATCH 1432/1809] bindings: clock: Add support for DIREWOLF Display clock controllers Update the DISPCC controller bindings for DIREWOLF. Change-Id: I3c4b8661fab10264d691ec9d05583f8771925dbc --- bindings/clock/qcom,dispcc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index 4cf54ffff090..ce33a8d494f5 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -19,6 +19,8 @@ Required properties : "qcom,monaco-dispcc" "qcom,blair-dispcc" "qcom,scuba-dispcc" + "qcom,direwolf-dispcc0" + "qcom,direwolf-dispcc1" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. From 18e75d054758eaca14d7b3724520aebae37347c0 Mon Sep 17 00:00:00 2001 From: Dundi Raviteja Date: Sun, 22 Nov 2020 22:43:53 +0530 Subject: [PATCH 1433/1809] ARM: dts: msm: Add icnss driver for monaco Add icnss driver for monaco platform. Change-Id: Ifa825897b959d3f3173c1d648ff5344d2c4e28ff CRs-Fixed: 2947959 --- qcom/monaco.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 93697a91f5fc..353d0b6d5f19 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -737,6 +737,46 @@ qcom,smem-state-names = "qcom,force-stop"; }; + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1A0 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,vdd-cx-mx-config = <0 0>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + + qcom,smp2p-modem { + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From 670b216f880012679ffc673f1fef1f7cedd6041b Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Tue, 4 May 2021 15:22:46 +0530 Subject: [PATCH 1434/1809] ARM: dts: msm: Add QBG battery profile for Alium 3600 mAh battery Add the battery profile for 3600mAh Alium battery which will be used by QBG on pm5100. Change-Id: I9178f87b45a19e20fe69b32314312ec20e265231 --- ...-profile-alium-860-89032-0000-3600mAh.dtsi | 550 ++++++++++++++++++ 1 file changed, 550 insertions(+) create mode 100644 qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi diff --git a/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi b/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi new file mode 100644 index 000000000000..00590e50e249 --- /dev/null +++ b/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi @@ -0,0 +1,550 @@ +qcom,qbg-battery-profile-alium-860-89032-0000-3600mAh { + qcom,battery-type = "ALIUM_860_89032_0000_3600MAH"; + qcom,batt-id-kohm = <107>; + qcom,capacity = <3588>; + qcom,max-voltage-uv = <4350000>; + qcom,fastchg-current-ma = <3600>; + qcom,checksum = <4563678>; /*@5, 0.005V, 10% */ + qcom,soh-range = <0 100>; + qcom,battery-impedance = <12580000 25160000>; /* Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell */ + qcom,battery-capacity = <3408 2691>; /* Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell */ + qcom,recharge-soc-delta =<5>; /* SOC delta (in percent) dropped from EOC SOC to enable recharge */ + qcom,recharge-vflt-delta =<50>; /* vfloat delta (in mV) dropped from regular vfloat in recharge */ + qcom,recharge-iterm-ma = <300>; /* termination current (in mA) in recharge */ + + qcom,bp-c-table-0 { + qcom,temperature = <25>; + qcom,soc = < 0 19 39 58 78>, + < 97 136 214 312 449>, + < 605 722 1093 1640 2617>, + < 3886 5019 5683 6210 6621>, + < 7031 7343 7519 7871 8027>, + < 8554 9101 9628 10000>; + qcom,ocv = <30000 30863 31659 32364 32956>, + <33410 34016 34824 35559 36295>, + <36867 37001 37083 37388 37894>, + <38164 38590 38975 39497 39791>, + <40073 40586 40837 41110 41228>, + <41772 42360 42953 43365>; + }; + + qcom,bp-c-table-1 { + qcom,temperature = <(-20)>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>, + <43705 53789 44184 43942 44013 43604 41068 42903>, + <43661 53585 44179 43946 44012 43945 41181 42931>, + <43664 54350 44180 43614 44015 43949 41137 42589>, + <43748 11251 44267 43587 44014 43943 41746 42623>, + <43723 10728 44270 43639 44009 43961 41976 42526>, + <43554 12062 44268 43629 44010 43957 41534 42717>, + <43644 8826 44271 43523 43933 43920 44406 42687>, + <43922 8449 44185 43570 43907 43976 41611 41327>, + <43883 9254 44179 43730 43919 43808 44367 41425>, + <43255 14867 44167 43672 44001 44025 45053 41445>, + <43128 15244 44168 43672 44029 44024 45048 41451>, + <44783 15158 44173 43774 44013 43988 44048 41467>, + <44226 14421 44161 43540 44013 43793 41113 41326>, + <41107 15967 44173 43625 43776 43793 41789 41295>, + <42372 15526 44884 43584 43856 43898 41322 41282>, + <47409 15831 44867 43908 43900 43066 47981 41317>, + <48281 12906 44874 44012 43875 43131 48704 41247>, + <45800 13155 44916 43995 43899 43076 48598 41287>, + <45943 12500 44865 43789 43856 43091 45767 42694>, + <45533 12745 44884 43866 43224 43448 45801 42993>, + <46597 13859 44193 43189 43133 43499 45732 42112>, + <47093 14086 44221 43184 43128 43496 48592 42215>, + <46101 2729 44165 43176 43029 43392 48814 42199>, + <46577 2616 44188 43179 43085 43392 47122 42001>, + <35776 2202 44260 43180 43334 43496 42250 42316>, + <35111 3788 44259 43191 44671 43496 42897 48054>, + <36662 3128 44267 43146 44800 43421 41436 47272>, + <36282 748 44268 43594 44960 41594 44901 47858>; + }; + + qcom,bp-c-table-2 { + qcom,temperature = <(-10)>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>, + <43705 53789 44184 43942 44013 43604 41068 42903>, + <43661 53585 44179 43946 44012 43945 41181 42931>, + <43664 54350 44180 43614 44015 43949 41137 42589>, + <43748 11251 44267 43587 44014 43943 41746 42623>, + <43723 10728 44270 43639 44009 43961 41976 42526>, + <43554 12062 44268 43629 44010 43957 41534 42717>, + <43644 8826 44271 43523 43933 43920 44406 42687>, + <43922 8449 44185 43570 43907 43976 41611 41327>, + <43883 9254 44179 43730 43919 43808 44367 41425>, + <43255 14867 44167 43672 44001 44025 45053 41445>, + <43128 15244 44168 43672 44029 44024 45048 41451>, + <44783 15158 44173 43774 44013 43988 44048 41467>, + <44226 14421 44161 43540 44013 43793 41113 41326>, + <41107 15967 44173 43625 43776 43793 41789 41295>, + <42372 15526 44884 43584 43856 43898 41322 41282>, + <47409 15831 44867 43908 43900 43066 47981 41317>, + <48281 12906 44874 44012 43875 43131 48704 41247>, + <45800 13155 44916 43995 43899 43076 48598 41287>, + <45943 12500 44865 43789 43856 43091 45767 42694>, + <45533 12745 44884 43866 43224 43448 45801 42993>, + <46597 13859 44193 43189 43133 43499 45732 42112>, + <47093 14086 44221 43184 43128 43496 48592 42215>, + <46101 2729 44165 43176 43029 43392 48814 42199>, + <46577 2616 44188 43179 43085 43392 47122 42001>, + <35776 2202 44260 43180 43334 43496 42250 42316>, + <35111 3788 44259 43191 44671 43496 42897 48054>, + <36662 3128 44267 43146 44800 43421 41436 47272>, + <36282 748 44268 43594 44960 41594 44901 47858>; + }; + + qcom,bp-c-table-3 { + qcom,temperature = <0>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>, + <43705 53789 44184 43942 44013 43604 41068 42903>, + <43661 53585 44179 43946 44012 43945 41181 42931>, + <43664 54350 44180 43614 44015 43949 41137 42589>, + <43748 11251 44267 43587 44014 43943 41746 42623>, + <43723 10728 44270 43639 44009 43961 41976 42526>, + <43554 12062 44268 43629 44010 43957 41534 42717>, + <43644 8826 44271 43523 43933 43920 44406 42687>, + <43922 8449 44185 43570 43907 43976 41611 41327>, + <43883 9254 44179 43730 43919 43808 44367 41425>, + <43255 14867 44167 43672 44001 44025 45053 41445>, + <43128 15244 44168 43672 44029 44024 45048 41451>, + <44783 15158 44173 43774 44013 43988 44048 41467>, + <44226 14421 44161 43540 44013 43793 41113 41326>, + <41107 15967 44173 43625 43776 43793 41789 41295>, + <42372 15526 44884 43584 43856 43898 41322 41282>, + <47409 15831 44867 43908 43900 43066 47981 41317>, + <48281 12906 44874 44012 43875 43131 48704 41247>, + <45800 13155 44916 43995 43899 43076 48598 41287>, + <45943 12500 44865 43789 43856 43091 45767 42694>, + <45533 12745 44884 43866 43224 43448 45801 42993>, + <46597 13859 44193 43189 43133 43499 45732 42112>, + <47093 14086 44221 43184 43128 43496 48592 42215>, + <46101 2729 44165 43176 43029 43392 48814 42199>, + <46577 2616 44188 43179 43085 43392 47122 42001>, + <35776 2202 44260 43180 43334 43496 42250 42316>, + <35111 3788 44259 43191 44671 43496 42897 48054>, + <36662 3128 44267 43146 44800 43421 41436 47272>, + <36282 748 44268 43594 44960 41594 44901 47858>; + }; + + qcom,bp-c-table-4 { + qcom,temperature = <10>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 45033 43737 43603 43866 41563 41506>, + <43705 53766 44949 43738 43615 43178 41536 41690>, + <43661 53577 44945 43718 43611 43194 41551 41715>, + <43664 54292 44957 43715 43591 43147 41544 41705>, + <43748 11150 44953 43724 43587 43160 41547 41607>, + <43723 10326 44933 43721 43599 43246 41545 41661>, + <43554 12232 44930 43764 43636 43202 41536 44378>, + <43644 8751 44982 43774 43641 43036 41903 44295>, + <43922 8649 44987 43750 43619 43445 41931 44506>, + <43883 9454 44972 43751 43542 43300 41165 44527>, + <43255 15062 44630 43675 43626 43382 41676 44476>, + <43128 14925 44628 43679 43624 44718 41718 44452>, + <44783 15341 44627 43769 43549 43379 41249 44470>, + <44226 14371 44627 43637 43736 44651 37910 44528>, + <41107 15906 44613 43608 43735 44644 60857 44534>, + <42372 16330 44671 43960 43543 44544 57836 44350>, + <47409 15371 44642 43907 43608 44553 57110 44399>, + <48281 12899 44650 43963 43583 44742 57671 44522>, + <45800 12525 44571 43615 43579 44729 36578 44455>, + <45943 12714 44546 43958 43523 43379 36745 44437>, + <45533 13989 44546 44029 43592 43367 33164 44314>, + <46597 14183 44546 44013 43587 43369 36861 44292>, + <47093 13706 44550 43911 43595 43295 45396 44349>, + <46101 2616 44574 44008 43586 43268 45463 44309>, + <46577 2653 44562 44016 43607 43290 46905 44379>, + <35776 2120 44573 44021 44000 43285 45839 41703>, + <35111 4019 44651 44023 43872 43336 48949 41545>, + <36662 3523 44564 43604 43218 44073 42138 41879>, + <36282 937 44666 43576 43065 43488 41623 41555>; + }; + + qcom,bp-c-table-5 { + qcom,temperature = <25>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 43332 43718 43763 43378 46676 44985>, + <43705 53797 43329 43712 43763 44712 46710 44963>, + <43661 53505 43341 43725 43762 44672 46649 44629>, + <43664 54470 43342 43726 43773 44792 46721 44636>, + <43748 10774 43339 43720 43773 44755 45338 44614>, + <43723 10280 43380 43722 43772 44597 45443 44617>, + <43554 11850 43378 43761 43775 44623 45199 44665>, + <43644 8866 43367 43774 43769 45042 46057 44573>, + <43922 8269 43368 43770 43770 44818 46020 44554>, + <43883 10093 43283 43769 43746 44874 46300 44581>, + <43255 15017 43289 43749 43755 44267 35516 44753>, + <43128 14883 43288 43668 43748 44088 48866 44766>, + <44783 14961 43291 43763 43757 44915 36601 44589>, + <44226 14502 43268 43733 43770 44193 64491 44571>, + <41107 16044 43276 43565 43766 44884 63795 44561>, + <42372 16318 43312 43571 43720 44857 63606 44643>, + <47409 15380 43301 43577 43582 45042 33472 44609>, + <48281 12949 43298 43570 43545 44804 61244 44962>, + <45800 12515 43307 43558 43724 44812 58642 44599>, + <45943 12741 43472 43562 43722 44959 35952 44579>, + <45533 13859 43474 43533 43735 45034 39071 44647>, + <46597 13344 43472 43561 43728 44966 35574 44546>, + <47093 13615 43478 43743 43741 44634 45953 44594>, + <46101 2620 43473 43576 43740 44978 35216 44575>, + <46577 2982 43473 43568 43740 44935 35895 44567>, + <35776 2438 43475 43531 43560 44929 36356 44645>, + <35111 4050 43474 43532 43547 44954 35561 44975>, + <36662 3427 43473 43582 43603 45036 45867 44945>, + <36282 975 43472 43723 43960 44931 42369 44980>; + }; + + qcom,bp-c-table-6 { + qcom,temperature = <40>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 43505 43765 43675 44739 58612 44734>, + <43705 53966 43507 43767 43672 44606 58146 44709>, + <43661 53746 43517 43761 43672 44650 61420 44704>, + <43664 55133 43519 43763 43672 44615 60222 44716>, + <43748 10886 43513 43773 43673 44976 38086 44715>, + <43723 11080 43515 43775 43673 45039 37222 43351>, + <43554 11924 43495 43771 43673 44862 37542 43358>, + <43644 11736 43490 43751 43673 44202 40166 43341>, + <43922 8444 43497 43744 43674 44258 38461 43382>, + <43883 10129 43413 43756 43674 44094 38631 43384>, + <43255 9512 43414 43755 43648 44120 60617 43368>, + <43128 14976 43409 43666 43662 44472 40898 43289>, + <44783 15069 43408 43758 43678 44051 60003 43364>, + <44226 15113 43411 43750 43750 44093 59439 43332>, + <41107 14650 43420 43774 43770 44224 65165 43346>, + <42372 15936 43397 43763 43748 44800 38880 43357>, + <47409 15366 43394 43713 43721 44903 39733 44726>, + <48281 12945 43406 43721 43557 44205 40872 44688>, + <45800 12433 43402 43761 43714 44270 60945 44713>, + <45943 12572 43446 43774 43753 44908 40456 43385>, + <45533 13949 43440 43727 43723 44854 40753 44715>, + <46597 13367 43440 43749 43771 44922 35253 43377>, + <47093 13773 43441 43748 43750 44923 34973 43389>, + <46101 2603 43440 43764 43769 44811 34575 43334>, + <46577 2981 43443 43722 43775 44852 33813 43354>, + <35776 2543 43452 43720 43767 44850 33075 43346>, + <35111 3848 43455 43715 43730 44802 33637 44721>, + <36662 3422 43454 43765 43530 44914 34945 44700>, + <36282 808 43449 43712 43765 44073 36789 43345>; + }; + + qcom,bp-c-table-7 { + qcom,temperature = <50>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 43415 43760 43651 44707 65307 43336>, + <43705 53993 43409 43762 43648 44776 63897 43381>, + <43661 53693 43408 43772 43649 44759 64131 43377>, + <43664 55092 43410 43769 43654 44560 58990 43378>, + <43748 54635 43421 43771 43654 44637 58265 43390>, + <43723 11226 43420 43749 43655 44953 61196 43387>, + <43554 10599 43417 43745 43653 44810 38392 43361>, + <43644 11680 43397 43759 43674 44167 36864 43370>, + <43922 9049 43398 43755 43674 44072 38762 43293>, + <43883 9841 43395 43668 43652 44132 60565 43268>, + <43255 9603 43405 43666 43651 44505 64189 43317>, + <43128 9539 43404 43654 43701 44304 38320 43299>, + <44783 14995 43404 43676 43678 44532 37230 43267>, + <44226 15345 43404 43671 43745 44471 59557 43373>, + <41107 14817 43401 43754 43749 44115 57646 43366>, + <42372 15972 43447 43745 43759 44219 61314 43360>, + <47409 15366 43452 43774 43764 44823 32791 43328>, + <48281 13038 43451 43772 43733 44214 39831 44718>, + <45800 12516 43428 43756 43760 44284 37974 43367>, + <45943 12665 43425 43759 43668 44209 38319 43270>, + <45533 14270 43427 43748 43769 44874 38717 43360>, + <46597 13355 43427 43744 43753 44871 37475 43294>, + <47093 13725 43427 43745 43755 44864 36926 43294>, + <46101 2768 43437 43770 43744 44870 36983 43370>, + <46577 2994 43436 43770 43750 44874 37629 43368>, + <35776 2559 43438 43774 43775 44905 40470 43364>, + <35111 3858 43435 43773 43739 44822 33978 43329>, + <36662 687 43093 43748 43582 44877 36384 44712>, + <36282 813 43088 43768 43723 44316 35572 43367>; + }; + + qcom,bp-d-table-0 { + qcom,temperature = <25>; + qcom,soc = < 0 19 39 58 78>, + < 97 136 214 312 449>, + < 605 722 1093 1640 2617>, + < 3886 5019 5683 6210 6621>, + < 7031 7343 7519 7871 8027>, + < 8554 9101 9628 10000>; + qcom,ocv = <28020 29554 30909 31906 32434>, + <32777 33252 34082 34943 35817>, + <36507 36768 36886 37109 37543>, + <37954 38397 38781 39283 39670>, + <39927 40519 40770 40989 41101>, + <41666 42257 42876 43360>; + }; + + qcom,bp-d-table-1 { + qcom,temperature = <(-20)>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 55845 41409 21845 21845 43694 43705 21845>, + <43705 57283 41409 21845 21845 43695 43649 21845>, + <43661 53814 41409 21845 21845 43692 43774 21845>, + <43664 53319 41409 21845 21845 43692 43553 21845>, + <43748 54810 41423 21845 21845 43693 43641 21845>, + <43723 54402 41459 21845 21845 43692 43908 21845>, + <43554 10764 41360 386 63661 43692 43862 21845>, + <43644 11815 41045 55488 35741 43693 43379 30577>, + <43922 11521 40982 63723 47555 43692 44886 2459>, + <43883 8395 40961 40248 41338 43693 41911 56339>, + <43255 9955 41091 36084 44402 43682 42515 62276>, + <43128 10223 41131 35399 44101 43683 42773 64460>, + <44783 9704 41823 46673 41699 43683 42089 59385>, + <44226 14850 41143 48413 44295 43683 41448 60636>, + <41107 14470 41122 47597 44870 43683 41937 38251>, + <42372 14606 41812 42195 44615 43680 41542 37878>, + <47409 15985 41854 41448 44604 43680 41607 40513>, + <48281 16148 41794 41828 44585 43681 41726 38979>, + <45800 15381 41806 41905 44594 43686 41969 39793>, + <45943 15731 41798 41478 44633 43686 41207 39887>, + <45533 13236 41801 41648 44856 43687 41125 39843>, + <46597 12457 41803 44366 44825 43684 41587 39528>, + <47093 12368 41847 44357 44282 43684 41945 39914>, + <46101 13694 41835 41903 42479 43707 48631 37286>, + <46577 2623 41749 41916 47842 43707 45706 38580>, + <35776 2973 41829 41705 42094 43684 44421 36912>, + <35111 2462 41744 42345 41789 43705 41209 38706>, + <36662 3291 41803 47453 41798 43680 44262 61324>, + <36282 824 41130 49041 41026 43690 43690 57741>; + }; + + qcom,bp-d-table-2 { + qcom,temperature = <(-10)>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 50529 41780 21845 21845 43695 43710 21845>, + <43705 56941 41780 21845 21845 43686 43649 21845>, + <43661 53781 41780 21845 21845 43707 43726 21845>, + <43664 53705 41786 21845 21845 43705 43639 21845>, + <43748 55191 41926 21845 21845 43705 43783 21845>, + <43723 54284 41887 26259 21845 43706 43084 21845>, + <43554 10827 41570 57991 33374 43683 44899 13506>, + <43644 11872 41693 34887 41483 43693 41148 58785>, + <43922 8945 41723 45501 44208 43683 42555 59581>, + <43883 8511 41617 48394 44812 43683 42113 38905>, + <43255 10081 41616 48662 45012 43683 47757 37739>, + <43128 9325 41620 47175 45045 43683 47861 40400>, + <44783 14980 41610 47875 44222 43680 42894 40088>, + <44226 15283 41655 42088 44658 43680 41019 39731>, + <41107 14547 41612 40973 43366 43681 41203 33074>, + <42372 14666 41636 44169 43504 43685 41934 36413>, + <47409 15952 41614 44693 43437 43711 41572 35331>, + <48281 15535 41661 43367 43452 43703 40975 46479>, + <45800 15822 41647 43281 43387 43661 42933 46164>, + <45943 12863 41660 43314 44773 43673 42509 46146>, + <45533 13183 41609 43470 44759 43714 41320 46141>, + <46597 12703 41656 44685 44644 43848 46238 46364>, + <47093 14042 41634 44693 44831 43198 35723 35713>, + <46101 2988 44380 43499 47654 43534 47325 32959>, + <46577 3026 44383 43403 47882 43724 42882 32895>, + <35776 2975 41639 43307 41368 43771 44987 36726>, + <35111 3791 41637 41594 44489 43612 47500 33289>, + <36662 3194 44373 44431 44116 43624 43080 33297>, + <36282 806 44381 43232 41661 43649 43690 33325>; + }; + + qcom,bp-d-table-3 { + qcom,temperature = <0>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 50372 44353 21845 21845 43695 43710 21845>, + <43705 57283 44353 21845 21845 43706 43651 21845>, + <43661 54080 44352 21845 21845 43710 43767 21845>, + <43664 54960 44390 21845 21845 43705 43833 21845>, + <43748 55060 44326 20286 21845 43706 43351 21845>, + <43723 54697 44523 8575 21845 43687 44153 21845>, + <43554 11163 44149 45557 41969 43683 40987 59942>, + <43644 12268 44132 48903 44256 43683 41247 40065>, + <43922 8812 44055 47152 44840 43683 42691 39684>, + <43883 9907 44055 42216 44970 43680 42793 33116>, + <43255 9257 44086 41051 44639 43686 42381 36297>, + <43128 9715 44088 41774 44651 43687 42165 36436>, + <44783 14980 44069 41632 44713 43685 41084 34994>, + <44226 15283 44072 44620 43468 43699 41436 45364>, + <41107 14462 44078 43247 43096 43761 41254 48684>, + <42372 14663 44241 44008 43855 43946 41385 47752>, + <47409 16281 44235 43946 43899 43992 41413 41992>, + <48281 15459 44275 43985 43177 43085 48564 42109>, + <45800 13044 44278 43898 43217 43307 45390 42432>, + <45943 13097 44233 43841 43056 43487 45412 42281>, + <45533 12396 44287 43863 43054 43412 47092 42489>, + <46597 13455 44268 43144 41636 43507 46025 48762>, + <47093 13798 44267 43246 41974 43510 48267 48266>, + <46101 13662 44267 43124 44571 43041 42674 47342>, + <46577 2789 44264 43076 43384 43200 41381 48070>, + <35776 2249 44256 43229 43274 43134 47578 48041>, + <35111 3588 44256 43228 43437 43013 47562 47678>, + <36662 3472 44265 43198 43011 43114 47227 47750>, + <36282 980 44181 43897 43040 43100 47147 42319>; + }; + + qcom,bp-d-table-4 { + qcom,temperature = <10>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 51163 44874 51317 21845 43695 43708 21845>, + <43705 55613 44874 64906 21845 43698 43636 21845>, + <43661 53829 44874 57837 21845 43679 43162 21845>, + <43664 54785 44874 60052 56852 43762 43376 29256>, + <43748 54323 44912 40533 38120 43555 44277 11699>, + <43723 54611 44911 35962 35922 43634 41066 62404>, + <43554 11097 44833 41332 41454 43823 48856 35640>, + <43644 12252 45045 43397 44689 43875 48244 47349>, + <43922 8820 45050 43053 43496 43850 48900 42268>, + <43883 9961 45035 43182 43056 43167 48201 42964>, + <43255 9333 44954 43886 43063 43045 48146 42504>, + <43128 9578 44955 43805 43041 43011 48180 42750>, + <44783 14999 44936 44013 43879 43149 47866 41069>, + <44226 15256 44939 43960 43990 43433 48721 41832>, + <41107 14462 44986 43549 43913 43510 47298 41530>, + <42372 16045 44973 43540 43590 44761 45578 41651>, + <47409 16231 44639 43630 43606 44546 48572 44353>, + <48281 15843 44638 43643 43966 44595 45772 44379>, + <45800 12823 44608 43607 44029 44757 46718 41724>, + <45943 13124 44608 43958 43795 44746 46866 41596>, + <45533 12766 44623 43926 43210 44698 46792 41787>, + <46597 13469 44656 43800 43394 43368 47963 41080>, + <47093 13805 44669 43879 43500 43321 42473 41376>, + <46101 2737 44662 43970 43868 43458 47973 41931>, + <46577 2594 44663 44024 43779 43471 47119 41903>, + <35776 2079 44656 44013 43987 43460 47382 41598>, + <35111 3666 44618 43936 44031 43298 47241 41518>, + <36662 3521 44662 43605 44015 43385 48696 41682>, + <36282 990 44665 43913 44000 44710 45581 41527>; + }; + + qcom,bp-d-table-5 { + qcom,temperature = <25>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 51166 44775 47124 21845 43693 43709 21845>, + <43705 55768 44775 42052 21845 43629 44600 21845>, + <43661 53783 44775 41259 21845 43987 41550 21845>, + <43664 54792 44775 41501 61566 43196 42926 50758>, + <43748 54296 44769 44058 42233 43056 48033 45433>, + <43723 10915 44689 44659 41117 43444 48945 48852>, + <43554 11086 44717 43849 45025 44716 46210 41271>, + <43644 12168 43343 43548 43241 44764 35739 44523>, + <43922 8917 43382 43569 44012 44547 35662 44210>, + <43883 8515 43365 43554 43593 44988 35035 44838>, + <43255 9265 43372 43741 43644 45034 46786 45047>, + <43128 9482 43374 43566 43602 45013 46325 44832>, + <44783 15036 43371 43767 43558 45011 48146 44634>, + <44226 14943 43287 43774 43732 44830 48165 44644>, + <41107 14349 43282 43772 43738 44804 45963 44562>, + <42372 16104 43271 43737 43582 44926 36856 44609>, + <47409 16215 43316 43774 43564 44894 48867 44547>, + <48281 15831 43325 43762 43580 44861 48983 44569>, + <45800 13273 43320 43572 43912 45050 47025 44833>, + <45943 12380 43322 43549 43835 44981 45972 44217>, + <45533 12637 43303 43534 43950 44554 48740 45022>, + <46597 13549 43308 43538 43604 44773 48921 45008>, + <47093 13800 43311 43542 43602 44779 49021 45008>, + <46101 2743 43311 43552 43628 44746 47348 44985>, + <46577 2599 43311 43733 43551 44739 47972 44638>, + <35776 2152 43310 43730 43575 44582 48877 44666>, + <35111 4027 43310 43772 43529 44971 42101 44568>, + <36662 3542 43308 43769 43568 45054 42333 44546>, + <36282 970 43309 43761 43553 45012 47510 44568>; + }; + + qcom,bp-d-table-6 { + qcom,temperature = <40>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 51194 43317 43723 21845 43904 43699 21845>, + <43705 55597 43317 43433 21845 43858 44606 21845>, + <43661 53857 43317 44608 21845 43009 41891 21845>, + <43664 54971 43317 44840 43003 43402 42967 48409>, + <43748 55122 43325 44623 41934 43470 47118 48114>, + <43723 54745 43308 43277 44139 43275 45814 42567>, + <43554 11017 43466 43944 43384 44707 35608 41661>, + <43644 12196 43515 43725 43983 44640 35080 45034>, + <43922 8933 43495 43764 43549 45017 35968 44591>, + <43883 8451 43501 43750 43562 44206 35810 44702>, + <43255 9457 43502 43745 43576 44228 46407 44779>, + <43128 9716 43497 43768 43647 44266 46648 44576>, + <44783 9572 43496 43753 43773 44229 36065 43345>, + <44226 14901 43498 43752 43775 44067 33852 43359>, + <41107 14564 43415 43754 43746 44071 39629 43337>, + <42372 16023 43423 43754 43735 44087 35414 44730>, + <47409 15530 43393 43752 43762 44272 35657 43337>, + <48281 15656 43404 43747 43764 44882 35074 43334>, + <45800 13269 43400 43721 43618 44855 46400 44762>, + <45943 12730 43402 43717 43614 44840 45218 44545>, + <45533 14004 43445 43764 43573 44629 45722 44777>, + <46597 13474 43446 43725 43533 44665 45641 44793>, + <47093 13389 43441 43715 43522 44645 45991 44796>, + <46101 13640 43443 43768 43735 44980 48200 44709>, + <46577 2762 43442 43750 43738 44948 48336 43345>, + <35776 2098 43452 43750 43722 44838 45237 43340>, + <35111 3676 43454 43746 43760 44803 45373 43379>, + <36662 3569 43454 43747 43774 44828 46449 43384>, + <36282 900 43454 43744 43768 44830 35264 43385>; + }; + + qcom,bp-d-table-7 { + qcom,temperature = <50>; + qcom,nrows = <29>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 51120 43482 43723 21845 43917 43696 21845>, + <43705 55378 43482 43228 21845 43244 44765 21845>, + <43661 56668 43482 43346 24109 43423 41585 21159>, + <43664 53659 43482 44743 41335 43294 42982 48852>, + <43748 55195 43456 43333 41722 43382 47309 42416>, + <43723 54370 43511 43098 44877 43356 45742 41469>, + <43554 11136 43496 43641 43414 44726 35620 44432>, + <43644 11793 43410 43766 43926 44646 36626 44613>, + <43922 11605 43423 43775 43532 44855 33761 44773>, + <43883 8703 43419 43758 43743 44170 35271 44717>, + <43255 9378 43396 43668 43561 44090 46107 44705>, + <43128 9610 43399 43747 43635 44034 46844 44742>, + <44783 9529 43399 43666 43775 44116 36331 43385>, + <44226 15093 43393 43676 43762 44430 39369 43384>, + <41107 14501 43395 43674 43745 44433 39567 43287>, + <42372 16024 43403 43672 43743 44489 46412 43337>, + <47409 16209 43442 43676 43770 44142 36065 43282>, + <48281 15829 43448 43667 43774 44283 36585 43286>, + <45800 13278 43431 43744 43535 44800 46795 44727>, + <45943 12724 43425 43774 43631 44998 45964 44768>, + <45533 14071 43424 43748 43565 44993 45928 44718>, + <46597 14205 43426 43768 43552 44982 45526 44707>, + <47093 13363 43436 43768 43552 44961 45429 44707>, + <46101 13675 43438 43752 43724 45001 45164 43384>, + <46577 2810 43438 43754 43767 45009 45137 43374>, + <35776 2093 43432 43755 43771 44814 35455 43292>, + <35111 3651 43435 43752 43745 44851 36039 43269>, + <36662 3552 43093 43667 43751 44276 35743 43279>, + <36282 954 43092 43674 43771 44148 48769 43318>; + }; +}; From ff000e9666d3a776ba907970ba62367d2d742f0c Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Tue, 11 May 2021 17:59:31 +0530 Subject: [PATCH 1435/1809] ARM: dts: msm: Add VOLUME UP Key configuration for Monaco VOL_UP key on Monaco is connected to pm5100 GPIO9. Add the pinctrl and gpio-key configuration for the same. Change-Id: I817d7cb7c368c8cc330454cb77a6ec14707f9720 --- qcom/monaco-pmic.dtsi | 34 ++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 1 + 2 files changed, 35 insertions(+) create mode 100644 qcom/monaco-pmic.dtsi diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi new file mode 100644 index 000000000000..6b56202bbbec --- /dev/null +++ b/qcom/monaco-pmic.dtsi @@ -0,0 +1,34 @@ +#include +#include + +&pm5100_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm5100_gpios 9 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3615caf7bc94..63db97a22b24 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1227,6 +1227,7 @@ }; #include "pm5100.dtsi" +#include "monaco-pmic.dtsi" #include "monaco-pinctrl.dtsi" #include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" From 34048665f834e09a044aad787bb4a8ae2691a558 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Tue, 18 May 2021 12:15:25 +0530 Subject: [PATCH 1436/1809] ARM: dts: msm: Add stubs pm8010 and Speaker boost regulators Add stub regulators for pm8010 regulators and Audio speaker boost regulator for Monaco. Change-Id: I1f6f7322285c5e79e1e870619fa0ab9be28d1eaa --- qcom/monaco-stub-regulator.dtsi | 72 +++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/qcom/monaco-stub-regulator.dtsi b/qcom/monaco-stub-regulator.dtsi index b0eb6737362b..9a5433cc2814 100644 --- a/qcom/monaco-stub-regulator.dtsi +++ b/qcom/monaco-stub-regulator.dtsi @@ -333,4 +333,76 @@ regulator-min-microvolt = <2650000>; regulator-max-microvolt = <3544000>; }; + + L1C: + pm8010_l1: regulator-pm8010-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + L2C: + pm8010_l2: regulator-pm8010-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + L3C: + pm8010_l3: regulator-pm8010-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + L4C: + pm8010_l4: regulator-pm8010-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + L5C: + pm8010_l5: regulator-pm8010-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + L6C: + pm8010_l6: regulator-pm8010-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + L7C: + pm8010_l7: regulator-pm8010-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + SPKR_BOOST: + pm5100_boost: regulator-pm5100-boost { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_boost"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; }; From 7e7bd628a9bfbec1f8a404613e813f8100610e95 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 14 May 2021 13:11:02 +0800 Subject: [PATCH 1437/1809] ARM: dts: msm: Add initial board files for QRD Holi-pm6125 Add initial device tree support with necessary PMIC configuration for QRD Holi platform with PM6125. Change-Id: I5a2fd75d5eb8b469d3da1986756cf85cf3823d0a --- qcom/Makefile | 7 +- qcom/holi-qrd-pm6125-overlay.dts | 15 ++ qcom/holi-qrd-pm6125.dts | 14 ++ qcom/holi-qrd-pm6125.dtsi | 317 +++++++++++++++++++++++++++++++ 4 files changed, 351 insertions(+), 2 deletions(-) create mode 100644 qcom/holi-qrd-pm6125-overlay.dts create mode 100644 qcom/holi-qrd-pm6125.dts create mode 100644 qcom/holi-qrd-pm6125.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 9d5d6f68bb88..d24ef004dd10 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -105,7 +105,8 @@ dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-cdp-pm6125-overlay.dtbo \ holi-cdp-lcd-pm6125-overlay.dtbo \ holi-mtp-usbc-pm6125-overlay.dtbo \ - holi-mtp-pm6125-nopmi-overlay.dtbo + holi-mtp-pm6125-nopmi-overlay.dtbo \ + holi-qrd-pm6125-overlay.dtbo holi-rumi-overlay.dtbo-base := holi.dtb holi-mtp-overlay.dtbo-base := holi.dtb @@ -119,6 +120,7 @@ holi-cdp-pm6125-overlay.dtbo-base := holi.dtb holi-cdp-lcd-pm6125-overlay.dtbo-base := holi.dtb holi-mtp-usbc-pm6125-overlay.dtbo-base := holi.dtb holi-mtp-pm6125-nopmi-overlay.dtbo-base := holi.dtb +holi-qrd-pm6125-overlay.dtbo-base := holi.dtb else dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ @@ -132,7 +134,8 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-cdp-pm6125.dtb \ holi-cdp-lcd-pm6125.dtb \ holi-mtp-usbc-pm6125.dtb \ - holi-mtp-pm6125-nopmi.dtb + holi-mtp-pm6125-nopmi.dtb \ + holi-qrd-pm6125.dtb endif diff --git a/qcom/holi-qrd-pm6125-overlay.dts b/qcom/holi-qrd-pm6125-overlay.dts new file mode 100644 index 000000000000..afdb8ec9f9f0 --- /dev/null +++ b/qcom/holi-qrd-pm6125-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi QRD PM6125"; + compatible = "qcom,holi-qrd", "qcom,holi", "qcom,qrd"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <0xb 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-qrd-pm6125.dts b/qcom/holi-qrd-pm6125.dts new file mode 100644 index 000000000000..35a00d66eb1c --- /dev/null +++ b/qcom/holi-qrd-pm6125.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi QRD PM6125"; + compatible = "qcom,holi-qrd", "qcom,holi", "qcom,qrd"; + qcom,board-id = <0xb 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi new file mode 100644 index 000000000000..4a89749a9f4c --- /dev/null +++ b/qcom/holi-qrd-pm6125.dtsi @@ -0,0 +1,317 @@ +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 5000000 4500000 + 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 500000>; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; From 0d919a3c69f97a8d2b7778bb0f0725fe6fcfbd92 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Tue, 11 May 2021 16:49:22 +0530 Subject: [PATCH 1438/1809] ARM: dts: msm: Update bluetooth regulator for holi-pm6125 This change update bluetooth node based on pm6125. Change-Id: Icade314db0db8c0be58522dad8ee9542579d3f22 --- qcom/holi-pm6125-overlay.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 13169520db90..1a2de489172d 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -15,4 +15,12 @@ qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; }; + + bluetooth: bt_wcn3990 { + qcom,bt-vdd-io-supply = <&L9A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ + }; + }; From 460475c8b7117d3b732b029b445fdafbd81c3457 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Mon, 17 May 2021 17:31:53 +0530 Subject: [PATCH 1439/1809] ARM: dts: msm: Add regulator and supplies for holi-pm6125 Add proper regulator and supplies for holi MTP, CDP, MTP-USBC, platforms with PM6125 pmic. Change-Id: Icb451fe9158999d925f43e3a53da2286d2ec5a69 --- qcom/holi-cdp-pm6125.dtsi | 22 +++++++++++++++++++--- qcom/holi-mtp-pm6125.dtsi | 22 +++++++++++++++++++--- qcom/holi-mtp-usbc-pm6125.dtsi | 22 +++++++++++++++++++--- 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 5af8a4b33637..4fc0b91015d2 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -4,15 +4,31 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include -/* Dummy LDO reference */ &wcd938x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; &wcd937x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ &sdhc_1 { status = "ok"; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 616822dc67d2..8d1dd1455c5f 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -4,15 +4,31 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include -/* Dummy LDO reference */ &wcd938x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; &wcd937x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ &sdhc_1 { status = "ok"; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index e7dc9968edcd..58712f528ce9 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -4,15 +4,31 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include -/* Dummy LDO reference */ &wcd938x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; &wcd937x_codec { - cdc-vdd-mic-bias-supply = <&L2A>; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; }; +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ &sdhc_1 { status = "ok"; From 7a42f649b9cd65032472815c8fcf28443a9feec5 Mon Sep 17 00:00:00 2001 From: Hiren Gohel Date: Sun, 9 May 2021 20:24:40 +0530 Subject: [PATCH 1440/1809] ARM: dts: msm: Add eMMC platform support for Monaco variants Add eMMC platform changes for Monaco variants, And also add clk-scaling, H/w reset, Pinctrl, & speed modes. Change-Id: I77d6552634ee31fdbada7f4e74a77b05d6e111dd --- qcom/monaco-idp-v1.dtsi | 18 ++++++ qcom/monaco-pinctrl.dtsi | 92 +++++++++++++++--------------- qcom/monaco-rumi.dtsi | 4 ++ qcom/monaco-standalone-idp-v1.dtsi | 18 ++++++ qcom/monaco.dtsi | 14 +++++ 5 files changed, 100 insertions(+), 46 deletions(-) diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index e69de29bb2d1..1147544aa013 100644 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -0,0 +1,18 @@ + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L25A>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 270000>; + + vdd-io-supply = <&L15A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 250000>; +}; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index fc3bff370d59..a5ad5c9e3b73 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -777,56 +777,56 @@ }; }; }; - }; - /* SDC pin type */ - sdc1_on: sdc1_on { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; + + /* SDC pin type */ + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; }; - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; - rclk { - pins = "sdc1_rclk"; - bias-pull-down; + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; }; }; - - sdc1_off: sdc1_off { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - }; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 0d2189e70578..839ffe865bc0 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -19,6 +19,10 @@ cap-mmc-highspeed; max-frequency = <50000000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + vdd-supply = <&L25A>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 270000>; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index e69de29bb2d1..1147544aa013 100644 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -0,0 +1,18 @@ + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L25A>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 270000>; + + vdd-io-supply = <&L15A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 250000>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 93697a91f5fc..87f4fb5e6894 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1194,6 +1194,14 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000F642E 0x0 0x01 0x2c010800 0x80040868>; + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; no-sdio; @@ -1201,6 +1209,12 @@ non-removable; supports-cqe; + cap-mmc-hw-reset; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { From 66aa6c35388d92ff1636d516dd7191fd67011bb7 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Tue, 18 May 2021 15:07:16 +0530 Subject: [PATCH 1441/1809] ARM: dts: msm: Enable icnss node for blair Enable icnss node and update regulator config for blair. Change-Id: I101921c66deab6378967bba258779303e6ce0d25 --- qcom/blair-atp.dtsi | 11 +++++++ qcom/blair.dtsi | 74 +++++++++++++++++++++++++-------------------- 2 files changed, 53 insertions(+), 32 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index b80c113288fc..ac1861e90d29 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -204,3 +204,14 @@ vdd-supply = <&L16A>; core-supply = <&L22A>; }; + +&icnss { + vdd-cx-mx-supply = <&L4A>; + vdd-1.8-xo-supply = <&L7A>; + vdd-1.3-rfa-supply = <&L2E>; + vdd-3.3-ch1-supply = <&L11E>; + vdd-3.3-ch0-supply = <&L10E>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 6c695ba7dbd6..012d7884aaf0 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3184,38 +3184,6 @@ status = "ok"; }; - icnss: qcom,icnss@C800000 { - status = "disabled"; - compatible = "qcom,icnss"; - reg = <0xC800000 0x800000>, - <0xb0000000 0x10000>; - reg-names = "membase", "smmu_iova_ipa"; - iommus = <&apps_smmu 0x80 0x1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - qcom,iommu-dma = "fastmap"; - qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; - qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; - qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; - qcom,iommu-geometry = <0xa0000000 0x10010000>; - qcom,smp2p_map_wlan_1_in { - interrupts-extended = <&smp2p_wlan_1_in 0 0>, - <&smp2p_wlan_1_in 1 0>; - interrupt-names = "qcom,smp2p-force-fatal-error", - "qcom,smp2p-early-crash-ind"; - }; - }; - qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; @@ -3775,4 +3743,46 @@ }; }; +&soc { + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + vdd-cx-mx-supply = <&L2E>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L2A>; + vdd-3.3-ch1-supply = <&L21A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + +}; + #include "msm-rdbg.dtsi" From fde362e28b35daaf579c04e6aebd5052c297b9a3 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 19 May 2021 16:17:25 +0530 Subject: [PATCH 1442/1809] ARM: dts: qcom: Add flash pinctrl gpio for holi Pro Configure the sensor strobe, torch, hwen, tx gpios for camera. CRs-Fixed: 2938922 Change-Id: I5409878ada998eff886ec05e6a726e62a72896c5 --- qcom/holi-pinctrl.dtsi | 116 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/qcom/holi-pinctrl.dtsi b/qcom/holi-pinctrl.dtsi index 7ef2bf71ba05..07fd5d75b622 100644 --- a/qcom/holi-pinctrl.dtsi +++ b/qcom/holi-pinctrl.dtsi @@ -1094,6 +1094,122 @@ }; }; + cam_flash_strobe_active: cam_flash_strobe_active { + /* STROBE */ + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_strobe_suspend: cam_flash_strobe_suspend { + /* STROBE */ + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_torch_active: cam_flash_torch_active { + /* TORCH */ + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_torch_suspend: cam_flash_torch_suspend { + /* TORCH */ + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_hwen_active: cam_flash_hwen_active { + /* HWEN */ + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_hwen_suspend: cam_flash_hwen_suspend { + /* HWEN */ + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_tx_active: cam_flash_tx_active { + /* TX */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_tx_suspend: cam_flash_tx_suspend { + /* TX */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + pm8008_active: pm8008_active { mux { pins = "gpio58"; From ed19b4fcd5dcafa2bd9b1e23e764169a0c97dbaf Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 11 May 2021 21:58:33 +0530 Subject: [PATCH 1443/1809] ARM: dts: qcom: enable tsens and thermal zone mitigations for monaco Enable different thermal zones for tsens, different cooling devices like regulator cooling devices, lmh vdd cooling devices, qmi cooling devices etc. for monaco. Change-Id: I292c7d34d103c0cfe708eb63903cf21d90b26c51 --- qcom/monaco-regulators.dtsi | 15 ++ qcom/monaco-rumi.dtsi | 4 + qcom/monaco-stub-regulator.dtsi | 18 ++ qcom/monaco-thermal.dtsi | 419 ++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 8 + 5 files changed, 464 insertions(+) create mode 100644 qcom/monaco-thermal.dtsi diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi index 99d06dca19eb..026c4df19edd 100644 --- a/qcom/monaco-regulators.dtsi +++ b/qcom/monaco-regulators.dtsi @@ -51,6 +51,14 @@ ; qcom,use-voltage-level; }; + + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; }; rpm-regulator-smpa3 { @@ -178,6 +186,13 @@ qcom,use-voltage-level; }; + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MXA_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; }; rpm-regulator-ldoa7 { diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 2ca7828f5719..69376a48fb12 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -58,3 +58,7 @@ qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <0 250000>; }; + +&tsens0 { + status = "disabled"; +}; diff --git a/qcom/monaco-stub-regulator.dtsi b/qcom/monaco-stub-regulator.dtsi index 9a5433cc2814..45958a35747a 100644 --- a/qcom/monaco-stub-regulator.dtsi +++ b/qcom/monaco-stub-regulator.dtsi @@ -23,6 +23,15 @@ regulator-max-microvolt = ; }; + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_CX_LEVEL_AO>; + regulator-levels = ; + #cooling-cells = <2>; + status = "disabled"; + }; + S3A: pm5100_s3: regulator-pm5100-s3 { compatible = "qcom,stub-regulator"; @@ -83,6 +92,15 @@ regulator-max-microvolt = ; }; + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MXA_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + status = "disabled"; + }; + VDD_LPI_CX_LEVEL: L4A_LEVEL: pm5100_l4_level: regulator-pm5100-l4-level { diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi new file mode 100644 index 000000000000..a16a2b1bd4dd --- /dev/null +++ b/qcom/monaco-thermal.dtsi @@ -0,0 +1,419 @@ +#include + +&cpufreq_hw { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@f550800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0xf550800 0x1000>, + <0xf521000 0x1000>; + qcom,no-cooling-device-register; + }; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; +}; + +&soc { + tsens0:tsens@4410000 { + compatible = "qcom,tsens26xx"; + reg = <0x04410000 0x20>, + <0x04411000 0x140>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts-extended = <&intc 0 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 190 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 89 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tsens-upper-lower", + "tsens-critical", + "tsens-0C"; + tsens-reinit-wa; + 0C-sensor-num = <16>; + #thermal-sensor-cells = <1>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_tj: modem_tj { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_wlan: modem_wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = ; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 { + compatible = "qcom,lmh-cpu-vdd"; + reg = <0xf550800 0x1000>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + gpu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 6>; + trips { + gpu_step_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + gpu_cx_mon: gpu-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + + }; + + cooling-maps { + gpu-cx-cdev1 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + trips { + cpu0_2_config: cpu-0-2-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + + cpu2_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + trips { + cpu1_3_config: cpu-1-3-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + cpu3_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + mdm-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 4>; + trips { + mdm0_cx_mon: mdm0-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm0-cx-cdev1 { + trip = <&mdm0_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 5>; + trips { + mdm1_cx_mon: mdm1-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm1-cx-cdev1 { + trip = <&mdm1_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mapss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 7>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + zeroc-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 16>; + thermal-governor = "step_wise"; + trips { + zeroc_0_trip: active-config0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + lmh_cpu_cdev { + trip = <&zeroc_0_trip>; + cooling-device = <&lmh_cpu_vdd 1 1>; + }; + + cx_vdd_cdev { + trip = <&zeroc_0_trip>; + cooling-device = <&cx_cdev 1 1>; + }; + + mx_vdd_cdev { + trip = <&zeroc_0_trip>; + cooling-device = <&mx_cdev 1 1>; + }; + + adsp_vdd_cdev { + trip = <&zeroc_0_trip>; + cooling-device = <&adsp_vdd 1 1>; + }; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 204fe4039a33..8dd1188cc510 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -43,6 +43,8 @@ i-cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; @@ -68,6 +70,7 @@ i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; @@ -88,6 +91,7 @@ i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; @@ -108,6 +112,7 @@ i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; @@ -1249,6 +1254,8 @@ }; }; + thermal_zones: thermal-zones { }; + system_pm_rpm { compatible = "qcom,system-pm-rpm"; }; @@ -1282,6 +1289,7 @@ #include "monaco-pm.dtsi" #include "monaco-audio.dtsi" #include "monaco-usb.dtsi" +#include "monaco-thermal.dtsi" &qupv3_se6_2uart { status = "ok"; From 727c93f982300c1d0a62adb13fd0e8fb317d06e4 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Thu, 22 Apr 2021 12:11:18 +0530 Subject: [PATCH 1444/1809] ARM: dts: msm: Add support for BT in blair platform This patch adds support for BT Soc in blair platform. Change-Id: I3f998379e39db9d387b534b0755cdcec81729556 --- qcom/blair-atp.dtsi | 7 +++++++ qcom/blair.dtsi | 27 +++++++++++++-------------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index ac1861e90d29..5d917c914b60 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -215,3 +215,10 @@ qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; }; + +&bluetooth { + qcom,bt-vdd-io-supply = <&L11A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 012d7884aaf0..9eeaf76c9a38 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -477,20 +477,6 @@ }; }; - bluetooth: bt_wcn3990 { - compatible = "qcom,wcn3990"; - qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; - qcom,bt-vdd-io-supply = <&L11A>; /* IO */ - qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ - /* qcom,bt-vdd-pa-supply = <&L10E>; */ /* CH0 */ - qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ - - qcom,bt-vdd-io-config = <1700000 1900000 1 0>; - qcom,bt-vdd-core-config = <1304000 1304000 1 0>; - qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; - qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; - }; - intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -3783,6 +3769,19 @@ }; }; + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L9A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; }; #include "msm-rdbg.dtsi" From 4844a371a3e120adb00787b256c3380176bd0874 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 4 May 2021 14:25:28 +0530 Subject: [PATCH 1445/1809] ARM: dts: qcom: keep all step wise rules before userspace rules for YUPIK The multiple thermal zone trip violations are handled in same order as in thermal zone configuration in devicetree for a sensor. The userspace thermal zone handling might be slower because of multiple factors like uevent broadcast, low priority userspace process etc. It leads to a case where high priority stepwise thermal zone mitigation will be waiting for userspace thermal zone handling to complete. Keep userspace thermal zone as last thermal zone for each sensor so that step wise rules will be handled first. Change-Id: I1d2c124e7ef0111a914f8656d19df512f0272970 --- qcom/yupik-thermal.dtsi | 1080 +++++++++++++++++++-------------------- 1 file changed, 540 insertions(+), 540 deletions(-) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 9898b8d44e90..93a742f62c48 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -351,546 +351,6 @@ }; }; - aoss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 0>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-0-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 1>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-0-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-0-2-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 3>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-0-3-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 4>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 5>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 6>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 7>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 8>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-2-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 9>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-3-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 10>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-4-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 11>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-5-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 12>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-6-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 13>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu-1-7-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 14>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 0>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpuss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 1>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpuss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - nspss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 3>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - nspss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 4>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 5>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - ddr-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 6>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdmss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 7>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdmss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 8>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdmss-2-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 9>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdmss-3-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 10>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens1 11>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - cpu-0-0-step { polling-delay-passive = <0>; polling-delay = <0>; @@ -1782,4 +1242,544 @@ }; }; }; + + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 7>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 8>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 9>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 10>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 12>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 13>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 14>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nspss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nspss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 7>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 8>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 9>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 10>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; }; From 81791937d73c8cdfd4e7025bea59dab72acc387b Mon Sep 17 00:00:00 2001 From: Huixian Ma Date: Thu, 20 May 2021 08:57:02 +0800 Subject: [PATCH 1446/1809] ARM: dts: msm: Add alloc-ranges in mem_dump_region node Add alloc ranges in mem_dump_region node. Change-Id: I6d5885356e6ae36fc6debe55c671d657f7d28a5b --- qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index ea8308d7599f..11114a79d3d4 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -218,6 +218,7 @@ dump_mem: mem_dump_region { compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; size = <0 0x800000>; }; From 8a45b49c969b48fa4b8877bf960638b6e9384f7e Mon Sep 17 00:00:00 2001 From: Arun Prakash Date: Tue, 11 May 2021 17:12:18 +0530 Subject: [PATCH 1447/1809] ARM: dts: msm: Add Mproc driver support for direwolf Add glink,smp2p,smem & hw mutex support for direwolf. Change-Id: If3423803ec93bc38efd5387f170bdc2670db7e1e --- qcom/direwolf-smp2p.dtsi | 76 ++++++++++++++++++++++ qcom/direwolf.dtsi | 135 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 211 insertions(+) create mode 100644 qcom/direwolf-smp2p.dtsi diff --git a/qcom/direwolf-smp2p.dtsi b/qcom/direwolf-smp2p.dtsi new file mode 100644 index 000000000000..0d66d29df832 --- /dev/null +++ b/qcom/direwolf-smp2p.dtsi @@ -0,0 +1,76 @@ +#include +#include + +&soc { + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; + }; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 3f91d001c6bf..583e6809fdd7 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1623,6 +1623,140 @@ < 3000000 2 >; }; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + label = "spss"; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + qcom,compute-cx-limit-en; + qcom,compute-priority-mode = <2>; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + }; }; #include "direwolf-pinctrl.dtsi" @@ -1633,6 +1767,7 @@ #include "msm-arm-smmu-direwolf.dtsi" #include "direwolf-qupv3.dtsi" #include "direwolf-usb.dtsi" +#include "direwolf-smp2p.dtsi" &gcc_emac0_gdsc { status = "ok"; From 86a09d8fcaaeb358f589d41115da2dfb505fec6a Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 5 May 2021 15:22:59 +0530 Subject: [PATCH 1448/1809] ARM: dts: msm: Add ADC support for PM5100 Add ADC5 Gen3 device with ADC channel nodes for PM5100. Also add ADC channels and thermal zones for ADC thermistors on monaco. Change-Id: I9f92730608d34157ed57e53ba44bb5bcd97512ff --- qcom/monaco-pmic.dtsi | 95 ++++++++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 2 + qcom/pm5100.dtsi | 96 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi index 6b56202bbbec..4f160924154f 100644 --- a/qcom/monaco-pmic.dtsi +++ b/qcom/monaco-pmic.dtsi @@ -32,3 +32,98 @@ }; }; }; + +&pm5100_adc { + pm5100_xo_therm { + qcom,adc-tm-type = <1>; + }; + + pm5100_pa_therm_0 { + reg = ; + label = "pm5100_pa_therm_0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm5100_quiet_therm { + reg = ; + label = "pm5100_quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm5100_msm_therm { + reg = ; + label = "pm5100_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 204fe4039a33..a34b6e59b0d3 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -895,6 +895,8 @@ cell-index = <0>; }; + thermal_zones: thermal-zones {}; + slim_aud: slim@a5c0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index ff498fe835f7..5fbe48b0fca5 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -1,6 +1,8 @@ #include #include #include +#include +#include &spmi_bus { #address-cells = <2>; @@ -39,6 +41,100 @@ #thermal-sensor-cells = <0>; }; + pm5100_adc: vadc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>, <0x8300>; + reg-names = "adc5-gen3-base", "adc5-gen3-debug-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + + pm5100_ref_gnd { + reg = ; + label = "pm5100_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm5100_vref_1p25 { + reg = ; + label = "pm5100_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm5100_die_temp { + reg = ; + label = "pm5100_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm5100_xo_therm { + reg = ; + label = "pm5100_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <700>; + qcom,pre-scaling = <1 1>; + }; + + pm5100_usb_in_i_uv { + reg = ; + label = "pm5100_usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + qcom,scale-fn-type = ; + }; + + pm5100_chg_temp { + reg = ; + label = "pm5100_chg_temp"; + qcom,pre-scaling = <1 1>; + qcom,scale-fn-type = ; + }; + + pm5100_usb_in_v { + reg = ; + label = "pm5100_usb_in_v"; + qcom,pre-scaling = <1 16>; + }; + + pm5100_boost_out_v { + reg = ; + label = "pm5100_boost_out_v"; + qcom,pre-scaling = <1 6>; + }; + + pm5100_bat_therm { + reg = ; + label = "pm5100_bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,scale-fn-type = ; + }; + + pm5100_bat_id { + reg = ; + label = "pm5100_bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,scale-fn-type = ; + }; + + pm5100_vph_pwr { + reg = ; + label = "pm5100_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm5100_vbat_sns { + reg = ; + label = "pm5100_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + }; + pm5100_gpios: pinctrl@8800 { compatible = "qcom,pm5100-gpio"; reg = <0x8800>; From 9343c6741da005ed490d71e93f82309460952bc0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sun, 25 Apr 2021 00:43:45 +0530 Subject: [PATCH 1449/1809] dt-bindings: clock: Add support for QCS404 clock controllers Update the GCC and DEBUGCC bindings for QCS404 device. Change-Id: I3f327b4befb56282a767c1dd6e1e8b1d1d4b773e --- bindings/clock/qcom,cmn-blk-pll.txt | 26 ++++++++++++++++++++++++++ bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + 3 files changed, 28 insertions(+) create mode 100644 bindings/clock/qcom,cmn-blk-pll.txt diff --git a/bindings/clock/qcom,cmn-blk-pll.txt b/bindings/clock/qcom,cmn-blk-pll.txt new file mode 100644 index 000000000000..ae6ae72bad04 --- /dev/null +++ b/bindings/clock/qcom,cmn-blk-pll.txt @@ -0,0 +1,26 @@ +Qualcomm Technologies, Inc. Common Block PLL Controller Binding +--------------------------------------------------------------- + +Required properties : +- compatible : shall contain only the following: + "qcom,cmn_blk_pll" + +- reg : shall contain base register location and size. +- reg-names : "cmn_blk". +- clock-names : Shall contain "misc_reset", "ahb_clk", "aon_clk". +- clocks : phandle + clock reference to misc_reset, ahb and aon clock. +- #clock-cells : shall contain 1. + +Example : + clock_cmn_blk_pll@2f780 { + compatible = "qcom,cmn_blk_pll"; + reg = <0x2f780 0x4>; + reg-names = "cmn_blk"; + clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>, + <&clock_gcc GCC_BIAS_PLL_AHB_CLK>, + <&clock_gcc GCC_BIAS_PLL_AON_CLK>; + clock-names = "misc_reset_clk", "ahb_clk", "aon_clk"; + resets = <&clock_gcc GCC_BIAS_PLL_BCR>; + reset-names = "cmn_blk_pll_reset"; + #clock-cells = <1>; + }; diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 2b46f69dacf9..baa2b6a2f7fb 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -17,6 +17,7 @@ Required properties : "qcom,direwolf-debugcc" "qcom,blair-debugcc" "qcom,scuba-debugcc" + "qcom,qcs404-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 9f64f68d09a0..0db8e2851742 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -41,6 +41,7 @@ Required properties : "qcom,direwolf-gcc" "qcom,blair-gcc" "qcom,scuba-gcc" + "qcom,qcs404-gcc-mdss" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. From e29b559132862b78dcae240cedd91cca0bc5a101 Mon Sep 17 00:00:00 2001 From: Arun Prakash Date: Fri, 23 Apr 2021 11:37:18 +0530 Subject: [PATCH 1450/1809] ARM: dts: msm: Add mproc related node support for qcs405 Add glink and its dependent device tree node support for auto acs405 target. Change-Id: I71435198014502d6e5599cb3aae4414c56af726f --- qcom/qcs405.dtsi | 177 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index 10ff3f6bab3b..e09e9755db17 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -280,6 +280,183 @@ reg = <0x6d0 0xc>; }; }; + + tcsr_mutex_block: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@b011008 { + compatible = "syscon"; + reg = <0xb011008 0x4>; + }; + + apcs_glb: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x10>; + + #mbox-cells = <1>; + }; + + smp2p_sleepstate: qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x6000>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "qcs405-pinctrl.dtsi" From ebb069cb718671d5690b07a08998ed01a182ca2f Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Fri, 30 Apr 2021 03:02:45 +0530 Subject: [PATCH 1451/1809] ARM: dts: msm: Enable audio only for 1GB variants Due to memory constraints in 512MB variants, enabling audio only on 1GB variants. Change-Id: I1f545a5cb7958c9f7b33e34a097e322d190ae1bf --- qcom/sdxlemur-cdp.dts | 2 ++ qcom/sdxlemur-cdp.dtsi | 1 - qcom/sdxlemur-mtp-cpe.dts | 2 ++ qcom/sdxlemur-mtp-cpe.dtsi | 1 - qcom/sdxlemur-mtp-mbb-emmc.dts | 2 ++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 2 ++ qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 1 - qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 1 - qcom/sdxlemur-mtp-mbb.dts | 2 ++ qcom/sdxlemur-mtp-mbb.dtsi | 1 - qcom/sdxlemur-mtp.dts | 2 ++ qcom/sdxlemur-mtp.dtsi | 1 - qcom/sdxlemur-rcm-rc.dts | 2 ++ qcom/sdxlemur-rumi.dts | 2 ++ qcom/sdxlemur-v2-cdp.dts | 2 ++ qcom/sdxlemur-v2-mtp-cpe.dts | 2 ++ qcom/sdxlemur-v2-mtp-mbb-emmc.dts | 2 ++ qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts | 2 ++ qcom/sdxlemur-v2-mtp-mbb.dts | 2 ++ qcom/sdxlemur-v2-mtp.dts | 2 ++ qcom/sdxlemur-v2-rcm-rc.dts | 2 ++ qcom/sdxlemur.dtsi | 1 - 22 files changed, 30 insertions(+), 7 deletions(-) diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 32b5a27c0977..6eb58b96920e 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-cdp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 4f802df82626..2d64f22dc8a6 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -1,6 +1,5 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "sdxlemur-cnss.dtsi" -#include "sdxlemur-cdp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 1c89cc28e220..b5417a3ea95c 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-1024mb-cpe.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index e63b48f2a73d..ead27a18b95a 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,5 +1,4 @@ #include "sdxlemur-mtp.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { ntn3_vreg: ntn3_vreg { diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts index 8b5774a69767..123bbb8ec8ff 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-emmc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" / { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts index 0f207e33241f..1c391ad94074 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 63505538c5bf..20bd6389e01c 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,5 +1,4 @@ #include "sdxlemur-mtp.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 4aab30d9d047..c945092880d4 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,5 +1,4 @@ #include "sdxlemur-mtp.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { ioss_aqc_eth0_rx: aqc_rx@eth0 { diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index 239e0bc30e0a..2068bdaee56f 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" / { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0249a0ff28d..4127b6f32dc4 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -4,7 +4,6 @@ #include #include #include "sdxlemur-cnss.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur-mtp.dts b/qcom/sdxlemur-mtp.dts index 0483238314ac..20da9bce7905 100644 --- a/qcom/sdxlemur-mtp.dts +++ b/qcom/sdxlemur-mtp.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP"; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 586d9c3fe0dd..7213eb337afb 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -1,5 +1,4 @@ #include "sdxlemur-pmic-overlay.dtsi" -#include "sdxlemur-mtp-audio-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index cbd8d5c1ee12..0852b7990d0c 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-rc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-cdp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" / { diff --git a/qcom/sdxlemur-rumi.dts b/qcom/sdxlemur-rumi.dts index d0b471e1379f..523d85983874 100644 --- a/qcom/sdxlemur-rumi.dts +++ b/qcom/sdxlemur-rumi.dts @@ -3,6 +3,8 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rumi.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RUMI"; diff --git a/qcom/sdxlemur-v2-cdp.dts b/qcom/sdxlemur-v2-cdp.dts index a40de23838ce..56d5029dbfc3 100644 --- a/qcom/sdxlemur-v2-cdp.dts +++ b/qcom/sdxlemur-v2-cdp.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-cdp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP V2"; diff --git a/qcom/sdxlemur-v2-mtp-cpe.dts b/qcom/sdxlemur-v2-mtp-cpe.dts index cfa97dea9bbf..f8670b646394 100644 --- a/qcom/sdxlemur-v2-mtp-cpe.dts +++ b/qcom/sdxlemur-v2-mtp-cpe.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-1024mb-cpe.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE V2"; diff --git a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts index 9076ddf8c3d3..9c559e9e1743 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-mbb-emmc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC V2"; diff --git a/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts index 37fd541cd0b2..65630ea06a58 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE V2"; diff --git a/qcom/sdxlemur-v2-mtp-mbb.dts b/qcom/sdxlemur-v2-mtp-mbb.dts index 3814ef3e3d07..de0389ed4adc 100644 --- a/qcom/sdxlemur-v2-mtp-mbb.dts +++ b/qcom/sdxlemur-v2-mtp-mbb.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-mbb.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB V2"; diff --git a/qcom/sdxlemur-v2-mtp.dts b/qcom/sdxlemur-v2-mtp.dts index 40cb9249df97..21a9acca41ee 100644 --- a/qcom/sdxlemur-v2-mtp.dts +++ b/qcom/sdxlemur-v2-mtp.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-mtp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP V2"; diff --git a/qcom/sdxlemur-v2-rcm-rc.dts b/qcom/sdxlemur-v2-rcm-rc.dts index 385329444730..8bac601d1b38 100644 --- a/qcom/sdxlemur-v2-rcm-rc.dts +++ b/qcom/sdxlemur-v2-rcm-rc.dts @@ -3,6 +3,8 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-rcm-rc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-audio.dtsi" +#include "sdxlemur-cdp-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex V2"; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 68e625c2e099..36b1a9dfc324 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1437,5 +1437,4 @@ #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" #include "sdxlemur-blsp.dtsi" -#include "sdxlemur-audio.dtsi" #include "sdxlemur-thermal.dtsi" From ff108da52dca7c7a159bb967e29147826e5f24cd Mon Sep 17 00:00:00 2001 From: Sachin Kumar Garg Date: Thu, 20 May 2021 10:16:27 +0530 Subject: [PATCH 1452/1809] dt-bindings: Add DT bindings for monaco Add DT binding for video encoders and decoders on monaco. Change-Id: I0c782cb76a15c56188f2825f5ed9f9039b0ffd0c --- bindings/media/video/msm-vidc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 486c3d089276..354e1f376c54 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -14,6 +14,7 @@ Required properties: - "qcom,scshrike-vidc" : Invokes driver specific data for SA8195. - "qcom,sm6150-vidc" : Invokes driver specific data for SA6155. - "qcom,scuba-vidc" : Invokes driver specific data for SCUBA. + - "qcom,monaco-vidc" : Invokes driver specific data for MONACO. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL From 2d190d91a3e49a78feab230b825e6cd40afb571e Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Thu, 20 May 2021 14:30:13 -0700 Subject: [PATCH 1453/1809] ARM: dts: msm: Do not timeout waiting for M0 After a reboot device will keep polling for an M0 from the host for 60 seconds. Set the devicetree property to allow it to poll till an M0 is received from the host without timing out. Change-Id: I480ba2231b2f8598a18127e5b571ce13f9c9ce86 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 68e625c2e099..f02bacccb217 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1139,6 +1139,7 @@ interrupt-names = "mhi-device-inta"; qcom,mhi-ifc-id = <0x030817cb>; qcom,mhi-interrupt; + qcom,no-m0-timeout; status = "disabled"; }; From c3915e57ccdfb6c67f05892f037b3802d1ed5dd3 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Fri, 21 May 2021 10:58:59 +0530 Subject: [PATCH 1454/1809] ARM: dts: msm: Add thermal zones for pm5100 temp alarm Add thermal zones supported by temp alram on pm5100 PMIC. Change-Id: Iddc2b6ccb5d816d583ba7f01c7bae7f84aa9bc33 --- qcom/pm5100.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 5fbe48b0fca5..07e2a16337d5 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -38,6 +38,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; }; @@ -156,3 +158,33 @@ }; }; }; + +&thermal_zones { + pm5100_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_tz>; + wake-capable-sensor; + + trips { + pm5100_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm5100_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From 9028aac3392ce18b1d2a5130448b06a3a189ff53 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 20 May 2021 23:31:22 +0530 Subject: [PATCH 1455/1809] dt-bindings: thermal: Add support for ibat CCM hardware to bcl driver There are few pmics those support ibat continuous current monitoring (CCM) comparator hardware for bcl ibat level 1 monitor. Add support to set threshold for ibat CCM comparator hardware for bcl driver. Change-Id: I44ec898ececf107629a0d7fa5e538e66d697108c --- bindings/thermal/qcom-bcl-pmic5.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/thermal/qcom-bcl-pmic5.txt b/bindings/thermal/qcom-bcl-pmic5.txt index 814f161bd6ee..be9e2e0dcde5 100644 --- a/bindings/thermal/qcom-bcl-pmic5.txt +++ b/bindings/thermal/qcom-bcl-pmic5.txt @@ -35,6 +35,11 @@ Optional Parameters: Value type: Definition: When this flag is defined, the BCL driver will account for no bit shift in the threshold registers. +- qcom,ibat-ccm-hw-support: + Value type: + Definition: Enable this flag when BCL Peripheral supports continuous + current monitoring(CCM) hardware for battery current + monitor. Example: bcl@4200 { @@ -45,4 +50,5 @@ Example: interrupt-names = "bcl-lvl0", "bcl-lvl1"; qcom,pmic7-threshold; + qcom,ibat-ccm-hw-support; }; From 2d2bbf901518f329f2fe9b90427bdc76e5deae15 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 21 May 2021 12:00:48 +0530 Subject: [PATCH 1456/1809] ARM: dts: msm: Update base address for monaco Update base address as 0x50000000 instead of 0x9000000 to support IPA to reduce memory usage on 32-bit architecture. Change-Id: I00a49348b54a15cb1125293d3ea47e9a50f9fd2e --- qcom/monaco-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi index c49aaddce945..f98148c2fab6 100644 --- a/qcom/monaco-usb.dtsi +++ b/qcom/monaco-usb.dtsi @@ -10,7 +10,7 @@ iommus = <&apps_smmu 0x120 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; From 2aef344cc3fa02e4b6176bf40da5da8bc70e3848 Mon Sep 17 00:00:00 2001 From: Anil Veshala Date: Tue, 18 May 2021 21:45:09 +0530 Subject: [PATCH 1457/1809] ARM: dts: msm: updated monaco qupv3 dtsi qupv3_se7_spi_b node is duplicated hence it is not required, so removed the node. Change-Id: I7283faf491678ae532c3f8daaf438ed8a035452b --- qcom/monaco-qupv3.dtsi | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 432c2acc8b84..329d2a11425f 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -432,30 +432,6 @@ status = "disabled"; }; - qupv3_se7_spi_b: spi@4a9c000 { - compatible = "qcom,spi-geni"; - reg = <0x4a9c000 0x4000>; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "se_phys"; - interrupts = ; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, - <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se7_spi_active_L0_b - &qupv3_se7_spi_active_L1_b &qupv3_se7_spi_active_L2_b - &qupv3_se7_spi_active_L3_b>; - pinctrl-1 = <&qupv3_se7_spi_sleep_b>; - dmas = <&gpi_dma0 0 7 1 64 0>, - <&gpi_dma0 1 7 1 64 0>; - dma-names = "tx", "rx"; - spi-max-frequency = <75000000>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - /* HS UART Instance */ qupv3_se5_4uart: qcom,qup_uart@4a94000 { compatible = "qcom,msm-geni-serial-hs"; From aa76d43b210c057150568ac6a6978f9de984133f Mon Sep 17 00:00:00 2001 From: Huixian Ma Date: Tue, 11 May 2021 19:01:21 +0800 Subject: [PATCH 1458/1809] ARM: dts: msm: Add jtag_mm nodes for monaco Enable jtag_mm nodes to support cpu etm save/restore feature. Change-Id: I840df2bd17547432123dac84b10b8b7bf32b324c --- qcom/monaco.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index a7419ddaa742..bdc3980efef1 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1122,6 +1122,50 @@ }; }; + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + clk_virt: interconnect { compatible = "qcom,monaco-clk_virt"; #interconnect-cells = <1>; From 613cbf4a41574d4b0b17cc9d652b1d56c519278f Mon Sep 17 00:00:00 2001 From: Zhiqiang Liu Date: Thu, 20 May 2021 17:46:59 +0800 Subject: [PATCH 1459/1809] ARM: dts: msm: add lxc overlay supoort on v1 board Add lxc overlay support on some v1 boards to fix kernel boot failed issue of LXC image. Change-Id: Ia11dd0de44741b504571db50f8ec1ca1f0dd0fde --- qcom/Makefile | 12 ++++++++++++ qcom/sa6155p-adp-air-lxc-overlay.dts | 12 ++++++++++++ qcom/sa6155p-adp-star-lxc-overlay.dts | 12 ++++++++++++ qcom/sa6155p-v2-adp-star-lxc-overlay.dts | 12 ++++++++++++ qcom/sa8155-adp-star-lxc-overlay.dts | 12 ++++++++++++ qcom/sa8155p-adp-star-lxc-overlay.dts | 12 ++++++++++++ qcom/sa8195p-adp-star-lxc-overlay.dts | 13 +++++++++++++ 7 files changed, 85 insertions(+) create mode 100644 qcom/sa6155p-adp-air-lxc-overlay.dts create mode 100644 qcom/sa6155p-adp-star-lxc-overlay.dts create mode 100644 qcom/sa6155p-v2-adp-star-lxc-overlay.dts create mode 100644 qcom/sa8155-adp-star-lxc-overlay.dts create mode 100644 qcom/sa8155p-adp-star-lxc-overlay.dts create mode 100644 qcom/sa8195p-adp-star-lxc-overlay.dts diff --git a/qcom/Makefile b/qcom/Makefile index 51ff557384fa..090447f54f6d 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -284,6 +284,8 @@ dtb-$(CONFIG_ARCH_SCUBA) += qrb2210-rb1.dtb ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) dtbo-$(CONFIG_ARCH_SA8155) += \ + sa8155-adp-star-lxc-overlay.dtbo \ + sa8155p-adp-star-lxc-overlay.dtbo \ sa8155-v2-adp-air-lxc-overlay.dtbo \ sa8155p-v2-adp-air-lxc-overlay.dtbo else @@ -298,6 +300,8 @@ sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb +sa8155-adp-star-lxc-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb +sa8155p-adp-star-lxc-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-lxc-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-lxc-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else @@ -312,6 +316,9 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) dtbo-$(CONFIG_ARCH_SA6155) += \ + sa6155p-adp-star-lxc-overlay.dtbo \ + sa6155p-v2-adp-star-lxc-overlay.dtbo \ + sa6155p-adp-air-lxc-overlay.dtbo \ sa6155p-v2-adp-air-lxc-overlay.dtbo else dtbo-$(CONFIG_ARCH_SA6155) += \ @@ -333,6 +340,9 @@ sa6155-adp-air-overlay.dtbo-base := sa6155.dtb sa6155p-adp-air-overlay.dtbo-base := sa6155p.dtb sa6155p-v2-adp-air-overlay.dtbo-base := sa6155p.dtb sa6155p-v2-adp-air-lpass-overlay.dtbo-base := sa6155p.dtb +sa6155p-adp-star-lxc-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-star-lxc-overlay.dtbo-base := sa6155p.dtb +sa6155p-adp-air-lxc-overlay.dtbo-base := sa6155p.dtb sa6155p-v2-adp-air-lxc-overlay.dtbo-base := sa6155p.dtb else dtb-$(CONFIG_ARCH_SA6155) += sa6155-adp-star.dtb \ @@ -348,6 +358,7 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y) dtbo-$(CONFIG_ARCH_SA8195) += \ + sa8195p-adp-star-lxc-overlay.dtbo \ sa8195p-v2-adp-air-lxc-overlay.dtbo else dtbo-$(CONFIG_ARCH_SA8195) += \ @@ -357,6 +368,7 @@ endif sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb +sa8195p-adp-star-lxc-overlay.dtbo-base := sa8195p.dtb sa8195p-v2-adp-air-lxc-overlay.dtbo-base := sa8195p.dtb else dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \ diff --git a/qcom/sa6155p-adp-air-lxc-overlay.dts b/qcom/sa6155p-adp-air-lxc-overlay.dts new file mode 100644 index 000000000000..33b43234cbb8 --- /dev/null +++ b/qcom/sa6155p-adp-air-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-air.dtsi" +#include "display/sa6155p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/qcom/sa6155p-adp-star-lxc-overlay.dts b/qcom/sa6155p-adp-star-lxc-overlay.dts new file mode 100644 index 000000000000..21206996184c --- /dev/null +++ b/qcom/sa6155p-adp-star-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" +#include "display/sa6155p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa6155p-v2-adp-star-lxc-overlay.dts b/qcom/sa6155p-v2-adp-star-lxc-overlay.dts new file mode 100644 index 000000000000..7d4774e4737e --- /dev/null +++ b/qcom/sa6155p-v2-adp-star-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa6155-adp-star.dtsi" +#include "display/sa6155p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x020019 0>; +}; diff --git a/qcom/sa8155-adp-star-lxc-overlay.dts b/qcom/sa8155-adp-star-lxc-overlay.dts new file mode 100644 index 000000000000..b98910e9197d --- /dev/null +++ b/qcom/sa8155-adp-star-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-star.dtsi" +#include "display/sa8155-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155-adp-star", "qcom,sa8155", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8155p-adp-star-lxc-overlay.dts b/qcom/sa8155p-adp-star-lxc-overlay.dts new file mode 100644 index 000000000000..7cb054ee0325 --- /dev/null +++ b/qcom/sa8155p-adp-star-lxc-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-star.dtsi" +#include "display/sa8155-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155p-adp-star", "qcom,sa8155p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8195p-adp-star-lxc-overlay.dts b/qcom/sa8195p-adp-star-lxc-overlay.dts new file mode 100644 index 000000000000..a5a325aabf2d --- /dev/null +++ b/qcom/sa8195p-adp-star-lxc-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-adp-star.dtsi" +#include "display/sa8195p-v2-adp-air-display-lxc-shd.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,msm-id = <405 0x20000>; + qcom,board-id = <0x010019 0>; +}; From bb8d007df8c7ae782130db939a5c5f6ec56ee66d Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Wed, 19 May 2021 09:35:57 +0530 Subject: [PATCH 1460/1809] ARM: dts: msm: Correct syntax error and reorder dts variants for monaco Correct dts file name in makefile and inherit default variant in other variants of monaco. Change-Id: Ib0f90fb287e909cc0f59e7fe533db9c10bb88dae --- qcom/Makefile | 2 +- qcom/monaco-idp-v1-common.dtsi | 0 qcom/monaco-idp-v1.dtsi | 2 +- qcom/monaco-idp-v2.dtsi | 1 + qcom/monaco-idp-v3.dtsi | 1 + qcom/monaco-standalone-idp-v1.dtsi | 2 +- qcom/monaco-standalone-idp-v2.dtsi | 1 + qcom/monaco-standalone-idp-v3.dtsi | 1 + 8 files changed, 7 insertions(+), 3 deletions(-) create mode 100644 qcom/monaco-idp-v1-common.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 51ff557384fa..bb183d157656 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -256,7 +256,7 @@ dtbo-$(CONFIG_ARCH_MONACO) += \ monaco-standalone-idp-v1-overlay.dtbo \ monaco-standalone-idp-v2-overlay.dtbo \ monaco-standalone-idp-v3-overlay.dtbo \ - monaco-idp-v1-verlay.dtbo \ + monaco-idp-v1-overlay.dtbo \ monaco-idp-v2-overlay.dtbo \ monaco-idp-v3-overlay.dtbo diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index 1147544aa013..13fa035a9467 100644 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -1,4 +1,4 @@ - +#include "monaco-idp-v1-common.dtsi" &sdhc_1 { status = "ok"; diff --git a/qcom/monaco-idp-v2.dtsi b/qcom/monaco-idp-v2.dtsi index e69de29bb2d1..6fea5bc4f643 100644 --- a/qcom/monaco-idp-v2.dtsi +++ b/qcom/monaco-idp-v2.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-idp-v3.dtsi b/qcom/monaco-idp-v3.dtsi index e69de29bb2d1..6fea5bc4f643 100644 --- a/qcom/monaco-idp-v3.dtsi +++ b/qcom/monaco-idp-v3.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index 1147544aa013..13fa035a9467 100644 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -1,4 +1,4 @@ - +#include "monaco-idp-v1-common.dtsi" &sdhc_1 { status = "ok"; diff --git a/qcom/monaco-standalone-idp-v2.dtsi b/qcom/monaco-standalone-idp-v2.dtsi index e69de29bb2d1..d8a5c8c6f1a8 100644 --- a/qcom/monaco-standalone-idp-v2.dtsi +++ b/qcom/monaco-standalone-idp-v2.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v3.dtsi b/qcom/monaco-standalone-idp-v3.dtsi index e69de29bb2d1..d8a5c8c6f1a8 100644 --- a/qcom/monaco-standalone-idp-v3.dtsi +++ b/qcom/monaco-standalone-idp-v3.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" From 2075d459fbe5b855c0ea6bbcf22497ef4beef761 Mon Sep 17 00:00:00 2001 From: Sachin Kumar Garg Date: Wed, 7 Apr 2021 12:06:41 +0530 Subject: [PATCH 1461/1809] ARM: dts: msm: Add monaco video dtsi in target dtsi Add monaco video dtsi to enable the video device. Change-Id: I7f6f9583b12bbd379dbaa5de06da47804d5519a0 --- qcom/monaco-vidc.dtsi | 110 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 qcom/monaco-vidc.dtsi diff --git a/qcom/monaco-vidc.dtsi b/qcom/monaco-vidc.dtsi new file mode 100644 index 000000000000..4ccb68b2550e --- /dev/null +++ b/qcom/monaco-vidc.dtsi @@ -0,0 +1,110 @@ +#include +#include + +&soc { + msm_vidc: qcom,vidc@5a00000 { + compatible = "qcom,msm-vidc", "qcom,monaco-vidc"; + status = "ok"; + reg = <0x5a00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&gcc_venus_gdsc>; + venus-core0-supply = <&gcc_vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; + qcom,allowed-clock-rates = <133330000 240000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,mode = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,mode = "vidc-ar50-ddr"; + qcom,bus-range-kbps = <1000 2128000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,mode = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x860 0x00>, + <&apps_smmu 0x880 0x00>; + qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x861 0x04>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x863 0x0>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x804 0xE0>; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; + From 3d0f0f29128d1a18a782e8853e26fc0870a5821e Mon Sep 17 00:00:00 2001 From: Sachin Kumar Garg Date: Wed, 7 Apr 2021 12:46:26 +0530 Subject: [PATCH 1462/1809] ARM: dts: msm: Interconnect bus handling in video Added changes for interconnect bus handling in video. Change-Id: I8bc3a7da1ca63249794c9fddd9400fb007c9b2b9 --- qcom/monaco-vidc.dtsi | 40 +++++++++------------------------------- 1 file changed, 9 insertions(+), 31 deletions(-) diff --git a/qcom/monaco-vidc.dtsi b/qcom/monaco-vidc.dtsi index 4ccb68b2550e..ad8820459520 100644 --- a/qcom/monaco-vidc.dtsi +++ b/qcom/monaco-vidc.dtsi @@ -1,6 +1,3 @@ -#include -#include - &soc { msm_vidc: qcom,vidc@5a00000 { compatible = "qcom,msm-vidc", "qcom,monaco-vidc"; @@ -26,34 +23,16 @@ qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; qcom,allowed-clock-rates = <133330000 240000000>; - /* Buses */ - bus_cnoc { - compatible = "qcom,msm-vidc,bus"; - label = "cnoc"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,mode = "performance"; - qcom,bus-range-kbps = <1000 1000>; - }; - - venus_bus_ddr { - compatible = "qcom,msm-vidc,bus"; - label = "venus-ddr"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,mode = "vidc-ar50-ddr"; - qcom,bus-range-kbps = <1000 2128000>; - }; - - arm9_bus_ddr { - compatible = "qcom,msm-vidc,bus"; - label = "venus-arm9-ddr"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,mode = "performance"; - qcom,bus-range-kbps = <1000 1000>; - }; + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_VENUS_CFG>, + <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 2128000>; /* MMUs */ non_secure_cb { compatible = "qcom,msm-vidc,context-bank"; @@ -107,4 +86,3 @@ }; }; }; - From 64110f8ec6e51e1b46c53113c8e38c8f2e768a11 Mon Sep 17 00:00:00 2001 From: Sachin Kumar Garg Date: Wed, 7 Apr 2021 14:24:35 +0530 Subject: [PATCH 1463/1809] ARM: dts: msm: Add bus topology in Monaco Venus PIL Bus topology is required for bus scaling driver to serve the bandwidth requests from various clients. Add the same for monaco venus pil. Change-Id: I584cf20a13a15944d631e8e29d5ba6914cceca14 --- qcom/monaco.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 46d2e30cbd5a..62e2bd381424 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1291,6 +1291,32 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; }; + + qcom,venus@5ab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ab0000 0x20000>; + + vdd-supply = <&gcc_venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + + qcom,core-freq = <240000000>; + qcom,ahb-freq = <240000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "pm5100.dtsi" From 06942d0e408d0d84faae3b3d8d6147fd626a01a2 Mon Sep 17 00:00:00 2001 From: Sachin Kumar Garg Date: Wed, 7 Apr 2021 14:31:39 +0530 Subject: [PATCH 1464/1809] ARM: dts: msm: Add video dtsi in monaco target dtsi Add video dtsi in monaco main target dtsi Change-Id: I2d48659208a60e31b6430d525f2a62868625bf17 --- qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 62e2bd381424..13d637068794 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1332,6 +1332,7 @@ #include "monaco-audio.dtsi" #include "monaco-usb.dtsi" #include "monaco-thermal.dtsi" +#include "monaco-vidc.dtsi" &qupv3_se6_2uart { status = "ok"; From 228d279f936d8719616d29141cf657b21ca1ee7c Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Sun, 16 May 2021 11:07:20 +0530 Subject: [PATCH 1465/1809] dt-bindings: qpnp-smblite: Update smblite charger compatible string Add compatible string to support smblite charger driver for PM5100. Change-Id: Icb46f6402b86aed85d9b4ab6d8d53b10de7a892a --- bindings/power/supply/qcom/qpnp-smblite.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/power/supply/qcom/qpnp-smblite.txt b/bindings/power/supply/qcom/qpnp-smblite.txt index 0b5f59ae63fa..2f2c0f598185 100644 --- a/bindings/power/supply/qcom/qpnp-smblite.txt +++ b/bindings/power/supply/qcom/qpnp-smblite.txt @@ -17,7 +17,8 @@ Charger specific properties: - compatible Usage: required Value type: - Definition: "qcom,qpnp-smblite". + Definition: "qcom,qpnp-smblite" for SMBLITE on PM2250. + "qcom,qpnp-pm5100-smblite" for SMBLITE on PM5100. - qcom,pmic-revid Usage: required From a37908abee4221a30c97fcc5b5189f51a59d69ab Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 24 May 2021 00:39:41 +0530 Subject: [PATCH 1466/1809] ARM: dts: msm: change min voltage of touch_avdd fixed regulator The fixed regulator requires the min and max voltage to be the same. Change-Id: I2e3cb3894d485bfc34ce0b7a0c2f672a0f636e34 --- qcom/holi-cdp-pm6125.dtsi | 2 +- qcom/holi-mtp-pm6125.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index b092498fc61a..01db5d23d46f 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -224,7 +224,7 @@ touch_avdd: touch_avdd { compatible = "regulator-fixed"; regulator-name = "touch_avdd"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <233>; gpio = <&tlmm 53 0>; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 24c98800ddab..371ed154cda1 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -149,7 +149,7 @@ touch_avdd: touch_avdd { compatible = "regulator-fixed"; regulator-name = "touch_avdd"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <233>; gpio = <&tlmm 53 0>; From 1413468f1b17c4950371c76ded6b8ead81f48fda Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Mon, 17 May 2021 13:47:58 +0530 Subject: [PATCH 1467/1809] dt-bindings: arm: ddr_stats: Add QMP mailbox as optional property This change adds QMP mailbox as optional property to ddr_stats driver. Change-Id: Iddd0f3d6115ca53e05d2cdb47cddb8df346de15c --- bindings/arm/msm/ddr_stats.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/arm/msm/ddr_stats.txt b/bindings/arm/msm/ddr_stats.txt index 8ee497154d42..8b9eb14f6ab1 100644 --- a/bindings/arm/msm/ddr_stats.txt +++ b/bindings/arm/msm/ddr_stats.txt @@ -23,10 +23,16 @@ PROPERTIES Value type: Definition: Provides labels for the reg property. +- mboxes: + Usage: optional + Value type: Value type: + Definition: List of QMP mailbox phandle and channel identifier tuples. + EXAMPLE: qcom,ddr-stats@c300000 { compatible = "qcom,ddr-stats"; reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; reg-names = "phys_addr_base", "offset_addr"; + mboxes = <&qmp_aop 0>; }; From 5ffdb775c2b895466ab12574d801591e333a777a Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Fri, 21 May 2021 11:49:22 +0530 Subject: [PATCH 1468/1809] ARM: dts: msm: Update ddr_stats to support mbox for lahaina This change adds support to get various subsystems vote for ddr using QMP mailbox. Change-Id: I02216752a4e56e81d28dd071578f0c746a82a552 --- qcom/lahaina-pm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-pm.dtsi b/qcom/lahaina-pm.dtsi index 5028b6e124e4..7ed8f6961ada 100644 --- a/qcom/lahaina-pm.dtsi +++ b/qcom/lahaina-pm.dtsi @@ -139,6 +139,7 @@ compatible = "qcom,ddr-stats"; reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; reg-names = "phys_addr_base", "offset_addr"; + mboxes = <&qmp_aop 0>; }; sys-pm-vx@c320000 { From 9f8917aad1ec58367c19eaee1d5af5704cb6fdfa Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Fri, 7 May 2021 14:55:45 +0530 Subject: [PATCH 1469/1809] ARM: dts: msm: Update ddr stats to support mbox for yupik This change adds support to get various subsystems vote for ddr using QMP mailbox. Change-Id: I34f3a2f0089d262b94fee75f030239460cbffadf --- qcom/yupik-pm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi index e3d1ff43d709..cae63dcb43b0 100644 --- a/qcom/yupik-pm.dtsi +++ b/qcom/yupik-pm.dtsi @@ -181,5 +181,6 @@ compatible = "qcom,ddr-stats"; reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; reg-names = "phys_addr_base", "offset_addr"; + mboxes = <&qmp_aop 0>; }; }; From 52d6dedad43b4180ddf07a08009bc0a075825bb2 Mon Sep 17 00:00:00 2001 From: Munnuru Srikanth Date: Wed, 12 May 2021 16:43:48 +0530 Subject: [PATCH 1470/1809] ARM: dts: msm: sensors glink channels added sensors glink channels and their intent size. Change-Id: I66a5efaa52bc878f2732765fe58fe9cbb8d05042 --- qcom/monaco.dtsi | 114 +++++++++++++++++++++++++++++++++++++++++++++++ qcom/slate.dtsi | 114 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 228 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 13d637068794..4f39930c43e9 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1085,6 +1085,120 @@ qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; + + qcom,glinkpkt-slate-ssc-hal { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_hal"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_hal"; + }; + + qcom,glinkpkt-slate-sso-hal { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "sso_hal"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_sso_hal"; + }; + + qcom,glinkpkt-slate-cam-hal { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "cam_hal"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_cam_hal"; + }; + + qcom,glinkpkt-slate-ssc-usta { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_usta"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_usta"; + }; + + qcom,glinkpkt-slate-ssc-test-0 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_0"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_0"; + }; + + qcom,glinkpkt-slate-ssc-test-1 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_1"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_1"; + }; + + qcom,glinkpkt-slate-ssc-test-2 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_2"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_2"; + }; + + qcom,glinkpkt-slate-ssc-test-3 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_3"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_3"; + }; + + qcom,glinkpkt-slate-ssc-test-4 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_4"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_4"; + }; + + qcom,glinkpkt-slate-ssc-test-5 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_5"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_5"; + }; + + qcom,glinkpkt-slate-ssc-test-6 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_6"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_6"; + }; + + qcom,glinkpkt-slate-ssc-test-7 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_7"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_7"; + }; + + qcom,glinkpkt-slate-ssc-test-8 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_8"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_8"; + }; + + qcom,glinkpkt-slate-ssc-test-9 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_9"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_9"; + }; + + qcom,glinkpkt-slate-ssc-test-10 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_10"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_10"; + }; + + qcom,glinkpkt-slate-ssc-test-11 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_11"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_11"; + }; + + qcom,glinkpkt-slate-ssc-test-12 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_12"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_12"; + }; + + qcom,glinkpkt-slate-ssc-test-13 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_13"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_13"; + }; + + qcom,glinkpkt-slate-ssc-test-14 { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ssc_test_14"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_14"; + }; }; qcom,smp2p-modem { diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index 978c0a221d6f..a6f170802464 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -13,5 +13,119 @@ qcom,glink-slatecom-xprt-slate { compatible = "qcom,glink-slatecom-xprt"; label = "slate"; + + qcom,glinkpkt-slate-ssc-hal { + qcom,glink-channels = "ssc_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-sso-hal { + qcom,glink-channels = "sso_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-cam-hal { + qcom,glink-channels = "cam_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-usta { + qcom,glink-channels = "ssc_usta"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-0 { + qcom,glink-channels = "ssc_test_0"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-1 { + qcom,glink-channels = "ssc_test_1"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-2 { + qcom,glink-channels = "ssc_test_2"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-3 { + qcom,glink-channels = "ssc_test_3"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-4 { + qcom,glink-channels = "ssc_test_4"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-5 { + qcom,glink-channels = "ssc_test_5"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-6 { + qcom,glink-channels = "ssc_test_6"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-7 { + qcom,glink-channels = "ssc_test_7"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-8 { + qcom,glink-channels = "ssc_test_8"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-9 { + qcom,glink-channels = "ssc_test_9"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-10 { + qcom,glink-channels = "ssc_test_10"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-11 { + qcom,glink-channels = "ssc_test_11"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-12 { + qcom,glink-channels = "ssc_test_12"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-13 { + qcom,glink-channels = "ssc_test_13"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-14 { + qcom,glink-channels = "ssc_test_14"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; }; }; From a1da9d0f8baba62156a277864377c03e20e626a4 Mon Sep 17 00:00:00 2001 From: Shumin Qiu Date: Mon, 24 May 2021 16:58:58 +0800 Subject: [PATCH 1471/1809] ARM: dts: msm: Add ion secure heap and secure buffer for quin-vm Add ion secure heap node and secure buffer node. Change-Id: I346dd9b517d2e9f83504041a0cd2f7ea6ecdf346 --- qcom/quin-vm-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 02f309379006..ca5b86e6f822 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -82,6 +82,10 @@ }; }; + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + vdevs { compatible = "simple-bus"; virtio_input_keyboard@1c150000 { @@ -152,6 +156,11 @@ memory-region = <&qseecom_ta_mem>; qcom,ion-heap-type = "DMA"; }; + + qcom,ion-heap@9 { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; }; hab: qcom,hab { From b75ba0930a3a1dfbd6c14cf50d7284db8ee82896 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 24 May 2021 20:41:40 +0530 Subject: [PATCH 1472/1809] ARM: dts: msm: Remove qcom,gpu-qdss-stm property for Shima GPU qcom,gpu-qdss-stm property is not required to be enabled. Remove it to avoid enabling extra clocks and infrastructure to support this setting. Change-Id: I91745d77c23835645b0b0aab14cf20585d96b44b --- qcom/shima-gpu.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index d7f0353e76e9..f570325660b7 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -51,8 +51,6 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; - qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ - qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; @@ -577,12 +575,10 @@ <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, - <&aopcc QDSS_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu_clk", "cxo_clk", "axi_clk", - "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote", - "apb_pclk"; + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; From cc24cf19990b27723d94eae10df9dd4f88c4818b Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 24 May 2021 23:48:52 +0530 Subject: [PATCH 1473/1809] dt-bindings: Add snapshot of CX Ipeak cooling device devicetree binding Add snapshot of CX Ipeak devicetree binding to the devicetree project. This snapshot is taken as of 'commit <829fee7bd3d86> ("driver: thermal: Update CX Ipeak driver to support CX Ipeak v1.1 hardware")' of the msm-4.14 kernel project. Change-Id: Ib661ebdfe21207f8e119819a870cbb0f459e290c --- bindings/thermal/qcom,cx-ipeak-cdev.txt | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 bindings/thermal/qcom,cx-ipeak-cdev.txt diff --git a/bindings/thermal/qcom,cx-ipeak-cdev.txt b/bindings/thermal/qcom,cx-ipeak-cdev.txt new file mode 100644 index 000000000000..562cc6e5f5d3 --- /dev/null +++ b/bindings/thermal/qcom,cx-ipeak-cdev.txt @@ -0,0 +1,53 @@ +Qualcomm Technologies, Inc. CX Peak current cooling device + +The CX IPEAK cooling device, will be used to set thermal client vote to +CX IPEAK LM hardware. When all pre-defined clients on CX rail including +thermal client set their vote, CXIP LM hardware throttles pre-defined +client on the same rail. + +Required Parameters: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,cxip-lm-cooling-device" + +- reg: + Usage: required + Value type: + Definition: Must contain 2 variables where 'a' is the starting + register address of the CX IPEAK LM hardware and 'b' is the + size of the peripheral address space. + +- qcom,thermal-client-offset: + Usage: Optional + Value type: + Definition: This property is required for CX IP LM v1.1 and above + hardware. Must contain offset from CX IPEAK LM reg + base for thermal client voting. If this property is not defined, + then CX IPEAK cooling device will use legacy CXIP LM hardware + offset registers. + +- qcom,bypass-client-list: + Usage: Optional + Value type: + Definition: This property is required for CX IP LM v1.1 and above + hardware. Must contain array of offsets from CX IPEAK LM reg + base for clients those are not participating voting to CXIP LM + hardware. This property makes sense only when thermal-client + is defined. + +- #cooling-cells: + Usage: required + Value type: + Definition: Must be 2. This is required by of-thermal and refer the doc + for more details. + +Example: + + cxip_cdev: cxip-cdev@1fed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x1fed000 0x24>; + qcom,thermal-client-offset = <0x8000>; + qcom,bypass-client-list = <0x2004 0x3004>; + #cooling-cells = <2>; + }; From f2e0cfb51f0ff91119c4d7ea5c080bf53f9344a0 Mon Sep 17 00:00:00 2001 From: Akshaya Bhat Date: Mon, 3 May 2021 15:51:50 +0530 Subject: [PATCH 1474/1809] ARM: dts: msm: Add WDT node for SA2150P Add WDT node with compatible qcom,msm-watchdog, to enable watchdog driver on SA2150P. Change-Id: Icf55d6731dc1ac60f0703e151fbfcaae63383f22 --- qcom/qcs405.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index e09e9755db17..bda882360a27 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -457,6 +457,19 @@ #interrupt-cells = <2>; }; }; + + wdog: qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9744>; + qcom,ipi-ping; + qcom,wakeup-enable; + status = "okay"; + }; }; #include "qcs405-pinctrl.dtsi" From a6846345e49c92ea6b511e469b8f278af6b8e818 Mon Sep 17 00:00:00 2001 From: ziqic Date: Thu, 20 May 2021 16:37:29 +0800 Subject: [PATCH 1475/1809] ARM: dts: msm: Disable modem region reserved on sa8155 DRAM diet requires to remove reserved modem memory. Change-Id: I0b4af51b648a7df6b8ba5e26d75f35d4fdb8e562 --- qcom/sa8155-adp-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index f9d32f4980b8..f0cf75c45429 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -84,6 +84,11 @@ status = "disabled"; }; +&pil_modem_mem { + status = "disabled"; +}; + + &soc { qcom,lpass@17300000 { status = "ok"; From 7c138aad2c9fdcada7f9d415997ee83b8a25b65c Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 22 Apr 2021 17:02:48 +0530 Subject: [PATCH 1476/1809] ARM: dts: qcom: update sdhc properties Enable Change detect for sdhci for 6155/8155/8195 linux guest. Change-Id: Ia5fbad43ddaf3d8ff13cb2fabfbbfce5a9d6f3bb --- qcom/sa6155p-vm.dtsi | 7 +++---- qcom/sa8155-vm.dtsi | 5 ++--- qcom/sa8195-vm.dtsi | 4 ++-- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index 31462826ead9..a0c2424d23c2 100644 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -421,7 +421,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,sm6150-pdc"; reg = <0xb220000 0x30000>; - qcom,pdc-ranges = <6 486 1>, <8 488 4>; + qcom,pdc-ranges = <6 486 1>, <8 488 4>, <94 609 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; @@ -475,8 +475,7 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - broken-cd; - + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; status = "disabled"; qos0 { @@ -595,7 +594,7 @@ #include "sa6155p-vm-cnss.dtsi" &tlmm { - /delete-property/ wakeup-parent; + qcom,gpio-irq-map = <99 94>; }; &qupv3_0 { diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index bc1abaccb37b..15b3a4d213e6 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,6 +1,7 @@ #include #include #include "quin-vm-common.dtsi" +#include "pm8150-vm.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; @@ -578,8 +579,7 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - broken-cd; - qcom,nonhotplug; + cd-gpios = <&pm8150_gpios 4 GPIO_ACTIVE_LOW>; status = "disabled"; qos0 { @@ -827,7 +827,6 @@ #include "sa8155-vm-pcie.dtsi" #include "sm8150-qupv3.dtsi" #include "sm8150-ssc-qupv3.dtsi" -#include "pm8150-vm.dtsi" #include "sa8155-vm-audio.dtsi" &tlmm { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 923ef5210371..f64476c55cba 100644 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -1,6 +1,7 @@ #include #include #include "quin-vm-common.dtsi" +#include "pm8195-vm.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine"; @@ -600,7 +601,7 @@ pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - broken-cd; + cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; status = "disabled"; qos0 { @@ -859,7 +860,6 @@ #include "sa8195-qupv3.dtsi" #include "sa8195-ssc-qupv3.dtsi" #include "sa8155-vm-audio.dtsi" -#include "pm8195-vm.dtsi" &tlmm { /delete-property/ wakeup-parent; From 21a9f243f2811b9fd15839041c99106dd42d2515 Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Tue, 25 May 2021 14:37:48 +0530 Subject: [PATCH 1477/1809] ARM: dts: msm: Add MSM PCIe bus driver device nodes for direwolf Add MSM PCIe bus driver device nodes for PCIe in devicetree for direwolf to enable communication between direwolf and external peripherals connected via PCIe. Change-Id: I03a448372d4291bef90bf2d6863becf11ccf60d2 --- qcom/direwolf-pcie.dtsi | 1110 +++++++++++++++++++++++++++++++++++++++ qcom/direwolf.dtsi | 6 + 2 files changed, 1116 insertions(+) create mode 100644 qcom/direwolf-pcie.dtsi diff --git a/qcom/direwolf-pcie.dtsi b/qcom/direwolf-pcie.dtsi new file mode 100644 index 000000000000..df3953088a61 --- /dev/null +++ b/qcom/direwolf-pcie.dtsi @@ -0,0 +1,1110 @@ +#include + +&soc { + pcie0: qcom,pcie@0x1c20000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c20000 0x3000>, + <0x01c24000 0x2000>, + <0x3c000000 0xf1d>, + <0x3c000f20 0xa8>, + <0x3c001000 0x1000>, + <0x3c100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x3c200000 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x3c300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 143 0>; + wake-gpio = <&tlmm 145 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_perst_default + &pcie2a_clkreq_default + &pcie2a_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_2a_gdsc>; + vreg-1p8-supply = <&L3A0>; + vreg-0p9-supply = <&L11A0>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 99000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_2A &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_2A_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_PCIE_2A_PIPE_CLK_SRC>, + <&pcie_2a_pipe_clk>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_0_pipediv2_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_2A_BCR>, + <&gcc GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_phy_nocsr_com_phy_reset"; + + + dma-coherent; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <1106>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0044 0x14 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0ee4 0x02 0x0 + 0x16e4 0x04 0x0 + 0x0e84 0xd5 0x0 + 0x1684 0xd5 0x0 + 0x0e90 0x3f 0x0 + 0x1690 0x3f 0x0 + 0x0e3c 0x11 0x0 + 0x163c 0x11 0x0 + 0x0e40 0xc 0x0 + 0x1640 0xc 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0x7f 0x0 + 0x1168 0x34 0x0 + 0x116c 0xd8 0x0 + 0x195c 0x7f 0x0 + 0x1960 0xff 0x0 + 0x1964 0x7f 0x0 + 0x1968 0x34 0x0 + 0x196c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1970 0xdc 0x0 + 0x1974 0xdc 0x0 + 0x1978 0x5c 0x0 + 0x197c 0x34 0x0 + 0x1980 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1990 0x34 0x0 + 0x10d8 0x0f 0x0 + 0x18d8 0x0f 0x0 + 0x10dc 0x00 0x0 + 0x18dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x184c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1850 0x08 0x0 + 0x1044 0xf0 0x0 + 0x1844 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x19a4 0x38 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x88 0x0 + 0x0398 0x0b 0x0 + 0x03e4 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie1: qcom,pcie@0x01c18000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c18000 0x3000>, + <0x01c1e000 0x2000>, + <0x38000000 0xf1d>, + <0x38000f20 0xa8>, + <0x38001000 0x1000>, + <0x38100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x38200000 0x38200000 0x0 0x100000>, + <0x02000000 0x0 0x38300000 0x38300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 147 0>; + wake-gpio = <&tlmm 146 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2b_perst_default + &pcie2b_clkreq_default + &pcie2b_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_2b_gdsc>; + vreg-1p8-supply = <&L3A0>; + vreg-0p9-supply = <&L11A0>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 99000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_2B &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_2B_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2B_AUX_CLK>, + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_PCIE_2B_PIPE_CLK_SRC>, + <&pcie_2b_pipe_clk>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_1_pipediv2_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_2B_BCR>, + <&gcc GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_phy_nocsr_com_phy_reset"; + + + dma-coherent; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <1106>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0044 0x14 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0ee4 0x02 0x0 + 0x16e4 0x04 0x0 + 0x0e84 0xd5 0x0 + 0x1684 0xd5 0x0 + 0x0e90 0x3f 0x0 + 0x1690 0x3f 0x0 + 0x0e3c 0x11 0x0 + 0x163c 0x11 0x0 + 0x0e40 0xc 0x0 + 0x1640 0xc 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0x7f 0x0 + 0x1168 0x34 0x0 + 0x116c 0xd8 0x0 + 0x195c 0x7f 0x0 + 0x1960 0xff 0x0 + 0x1964 0x7f 0x0 + 0x1968 0x34 0x0 + 0x196c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1970 0xdc 0x0 + 0x1974 0xdc 0x0 + 0x1978 0x5c 0x0 + 0x197c 0x34 0x0 + 0x1980 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1990 0x34 0x0 + 0x10d8 0x0f 0x0 + 0x18d8 0x0f 0x0 + 0x10dc 0x00 0x0 + 0x18dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x184c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1850 0x08 0x0 + 0x1044 0xf0 0x0 + 0x1844 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x19a4 0x38 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x88 0x0 + 0x0398 0x0b 0x0 + 0x03e4 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie2: qcom,pcie@0x1c10000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c10000 0x3000>, + <0x01c14000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <2>; + linux,pci-domain = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x34200000 0x34200000 0x0 0x100000>, + <0x02000000 0x0 0x34300000 0x34300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 151 0>; + wake-gpio = <&tlmm 56 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_perst_default + &pcie3a_clkreq_default + &pcie3a_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_3a_gdsc>; + vreg-1p8-supply = <&L3A0>; + vreg-0p9-supply = <&L11A0>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 99000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_3A &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK_SRC>, + <&pcie_3a_pipe_clk>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; + + clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", + "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk", + "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk", + "pcie_2_ldo", "pcie_2_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_2_pipediv2_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_2_core_reset", + "pcie_phy_nocsr_com_phy_reset"; + + + dma-coherent; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <1106>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xca 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0xa2 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0ee4 0x02 0x0 + 0x16e4 0x04 0x0 + 0x1684 0xd5 0x0 + 0x0e84 0xd5 0x0 + 0x1690 0x3f 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0x7f 0x0 + 0x1168 0x34 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x195c 0x7f 0x0 + 0x1960 0xff 0x0 + 0x1964 0x7f 0x0 + 0x1968 0x34 0x0 + 0x196c 0xd8 0x0 + 0x1970 0xdc 0x0 + 0x1974 0xdc 0x0 + 0x1978 0x5c 0x0 + 0x197c 0x34 0x0 + 0x1980 0xa6 0x0 + 0x10cc 0xf0 0x0 + 0x18cc 0xf0 0x0 + 0x10d8 0x0f 0x0 + 0x18d8 0x0f 0x0 + 0x10dc 0x00 0x0 + 0x18dc 0x00 0x0 + 0x11a4 0x38 0x0 + 0x19a4 0x38 0x0 + 0x0e3c 0x1d 0x0 + 0x163c 0x1d 0x0 + 0x0e40 0x0c 0x0 + 0x1640 0x0c 0x0 + 0x1190 0x34 0x0 + 0x1990 0x34 0x0 + 0x104c 0x08 0x0 + 0x184c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1850 0x08 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie2_rp: pcie2_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie3: qcom,pcie@0x01c08000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x32000000 0xf1d>, + <0x32000f20 0xa8>, + <0x32001000 0x1000>, + <0x32100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <3>; + linux,pci-domain = <3>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x32200000 0x32200000 0x0 0x100000>, + <0x02000000 0x0 0x32300000 0x32300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie3>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 153 0>; + wake-gpio = <&tlmm 130 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3b_perst_default + &pcie3b_clkreq_default + &pcie3b_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_3b_gdsc>; + vreg-1p8-supply = <&L3A0>; + vreg-0p9-supply = <&L11A0>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 99000>; + qcom,vreg-cx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_3B &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK_SRC>, + <&pcie_3b_pipe_clk>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; + + clock-names = "pcie_3_pipe_clk", "pcie_3_ref_clk_src", + "pcie_3_aux_clk", "pcie_3_cfg_ahb_clk", + "pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk", + "pcie_3_ldo", "pcie_3_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_3_pipediv2_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_3B_BCR>, + <&gcc GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_3_core_reset", + "pcie_phy_nocsr_com_phy_reset"; + + dma-coherent; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <1106>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0044 0x14 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0ee4 0x02 0x0 + 0x16e4 0x04 0x0 + 0x0e84 0xd5 0x0 + 0x1684 0xd5 0x0 + 0x0e90 0x3f 0x0 + 0x1690 0x3f 0x0 + 0x0e3c 0x11 0x0 + 0x163c 0x11 0x0 + 0x0e40 0xc 0x0 + 0x1640 0xc 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0x7f 0x0 + 0x1168 0x34 0x0 + 0x116c 0xd8 0x0 + 0x195c 0x7f 0x0 + 0x1960 0xff 0x0 + 0x1964 0x7f 0x0 + 0x1968 0x34 0x0 + 0x196c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1970 0xdc 0x0 + 0x1974 0xdc 0x0 + 0x1978 0x5c 0x0 + 0x197c 0x34 0x0 + 0x1980 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1990 0x34 0x0 + 0x10d8 0x0f 0x0 + 0x18d8 0x0f 0x0 + 0x10dc 0x00 0x0 + 0x18dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x184c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1850 0x08 0x0 + 0x1044 0xf0 0x0 + 0x1844 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x19a4 0x38 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x88 0x0 + 0x0398 0x0b 0x0 + 0x03e4 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie3_rp: pcie3_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie4: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x30000000 0xf1d>, + <0x30000f20 0xa8>, + <0x30001000 0x1000>, + <0x30100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <4>; + linux,pci-domain = <4>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x30200000 0x30200000 0x0 0x100000>, + <0x02000000 0x0 0x30300000 0x30300000 0x0 0x1d00000>; + + interrupt-parent = <&pcie4>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + + interrupt-map = <0 0 0 0 &intc GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie4_msi>; + qcom,target-link-speed = <0x3>; + qcom,core-preset = <0x77777777>; + + perst-gpio = <&tlmm 141 0>; + wake-gpio = <&tlmm 139 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie4_perst_default + &pcie4_clkreq_default + &pcie4_wake_default>; + pinctrl-1 = <&pcie4_perst_default + &pcie4_clkreq_sleep + &pcie4_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_4_gdsc>; + vreg-1p8-supply = <&L3A0>; + vreg-0p9-supply = <&L11A0>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>; + qcom,vreg-0p9-voltage-level = <880000 880000 97200>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&aggre2_noc MASTER_PCIE_4 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_4_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_CLKREF_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK_SRC>, + <&pcie_4_pipe_clk>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_CNOC_PCIE4_QX_CLK>, + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; + + clock-names = "pcie_4_pipe_clk", "pcie_4_ref_clk_src", + "pcie_4_aux_clk", "pcie_4_cfg_ahb_clk", + "pcie_4_mstr_axi_clk", "pcie_4_slv_axi_clk", + "pcie_4_ldo", "pcie_4_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_aggre_noc_south_sf_axi_clk", "pcie_cnoc_4_qx", + "pcie_4_pipediv2_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_4_core_reset", + "pcie_phy_nocsr_com_phy_reset"; + + dma-coherent; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <70>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + + qcom,pcie-phy-ver = <10102>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x10d8 0x07 0x0 + 0x0e3c 0x1d 0x0 + 0x0e40 0x0c 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie4_rp: pcie4_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie4_msi: qcom,pcie4_msi@17a10040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a10040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 583e6809fdd7..9af97bae3a92 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -32,6 +32,11 @@ ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se17_2uart; hsuart0 = &qupv3_se2_4uart; + pci-domain0 = &pcie0; /* PCIe0 domain */ + pci-domain1 = &pcie1; /* PCIe1 domain */ + pci-domain2 = &pcie2; /* PCIe2 domain */ + pci-domain3 = &pcie3; /* PCIe3 domain */ + pci-domain4 = &pcie4; /* PCIe4 domain */ }; cpus { @@ -1768,6 +1773,7 @@ #include "direwolf-qupv3.dtsi" #include "direwolf-usb.dtsi" #include "direwolf-smp2p.dtsi" +#include "direwolf-pcie.dtsi" &gcc_emac0_gdsc { status = "ok"; From 1d1d4c48eda3452b37e38173a7c8d8beb02dd29a Mon Sep 17 00:00:00 2001 From: Rutvik Patel Date: Sun, 16 May 2021 23:51:36 +0530 Subject: [PATCH 1478/1809] ARM: dts: qcom: add audio dts source file for Monaco Rename slate audio dts file. Add audio dts file for monaco. Include audio dts file in base dts. Change-Id: I28084ae822e77b8d83ba78cf65aa3e8523e24eac --- bindings/sound/qcom-audio-dev.txt | 1 + qcom/monaco-amic-audio-overlay.dtsi | 112 +++++++++++++++++++++ qcom/monaco-audio-overlay.dtsi | 144 ++++++++++++++++++++++++++- qcom/monaco-audio.dtsi | 139 +------------------------- qcom/monaco-lpi.dtsi | 8 +- qcom/monaco-slate-audio.dtsi | 22 ----- qcom/monaco-wsa-audio-overlay.dtsi | 147 +++++++++++++++++++++++++++- 7 files changed, 405 insertions(+), 168 deletions(-) delete mode 100644 qcom/monaco-slate-audio.dtsi diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 2b05028368b2..12eb1432c914 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1976,6 +1976,7 @@ Optional properties: - qcom,va-bolero-codec: Property to specify VA macro supported. - qcom,rxtx-bolero-codec: Property to specify RX-TX macros supported. - qcom,wsa-bolero-codec: Property to specify WSA macro supported. +- qcom,visense-enable: Property to specify VISense need to enable or not. Example: monaco_snd: sound { diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi index 4c3868c669a7..5fb1ce51e85f 100644 --- a/qcom/monaco-amic-audio-overlay.dtsi +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -3,6 +3,108 @@ #include #include +&spf_core_platform { + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + qcom,lpi-gpios; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@0a730000 { + swr0: va_swr_master { + }; + }; + + rx_macro: rx-macro@0a600000 { + swr1: rx_swr_master { + }; + }; + }; + + monaco_snd: sound { + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + }; +}; + &bolero { qcom,num-macros = <3>; qcom,bolero-version = <6>; @@ -83,10 +185,15 @@ qcom,cdc-mic-bias-voltage = <2904000 2904000>; qcom,cdc-mic-bias-current = <1180>; + cdc-vdd-spkr-supply = <&SPKR_BOOST>; + qcom,cdc-vdd-spkr-voltage = <4100000 5600000>; + qcom,cdc-vdd-spkr-current = <700000>; + qcom,cdc-micbias1-mv = <1800>; qcom,cdc-micbias2-mv = <1800>; qcom,cdc-static-supplies = "cdc-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-spkr"; }; }; @@ -95,6 +202,7 @@ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; qcom,va-bolero-codec = <1>; + qcom,visense-enable = <0>; qcom,audio-routing = "AMIC1", "Analog Mic1", "Analog Mic1","MIC BIAS1", @@ -146,6 +254,10 @@ }; &soc { + audio_pkt_core_platform: qcom,audio-pkt-core-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; + clock_audio_rx_1: rx_core_clk { compatible = "qcom,audio-ref-clk"; qcom,codec-ext-clk-src = ; diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi index 8f7783f0e0bf..14da90fa6147 100644 --- a/qcom/monaco-audio-overlay.dtsi +++ b/qcom/monaco-audio-overlay.dtsi @@ -3,6 +3,137 @@ #include #include +&spf_core_platform { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + qcom,lpi-gpios; + }; + + va_swr_gpios: va_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + qcom,lpi-gpios; + qcom,chip-wakeup-reg = <0x003ca064>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@0a730000 { + swr0: va_swr_master { + }; + }; + + rx_macro: rx-macro@0a600000 { + swr1: rx_swr_master { + }; + }; + }; + + monaco_snd: sound { + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + }; +}; + &bolero { qcom,num-macros = <3>; qcom,bolero-version = <6>; @@ -127,10 +258,15 @@ qcom,cdc-mic-bias-voltage = <2904000 2904000>; qcom,cdc-mic-bias-current = <1180>; + cdc-vdd-spkr-supply = <&SPKR_BOOST>; + qcom,cdc-vdd-spkr-voltage = <4100000 5600000>; + qcom,cdc-vdd-spkr-current = <700000>; + qcom,cdc-micbias1-mv = <1800>; qcom,cdc-micbias2-mv = <1800>; qcom,cdc-static-supplies = "cdc-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-spkr"; }; }; @@ -170,8 +306,8 @@ "VA DMIC2", "VA MIC BIAS1", "VA DMIC3", "VA MIC BIAS1"; - qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; - qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; @@ -183,6 +319,10 @@ }; &soc { + audio_pkt_core_platform: qcom,audio-pkt-core-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; + clock_audio_rx_1: rx_core_clk { compatible = "qcom,audio-ref-clk"; qcom,codec-ext-clk-src = ; diff --git a/qcom/monaco-audio.dtsi b/qcom/monaco-audio.dtsi index 04698ce6d97d..4b1549f1781c 100644 --- a/qcom/monaco-audio.dtsi +++ b/qcom/monaco-audio.dtsi @@ -5,151 +5,14 @@ spf_core_platform: spf_core_platform { compatible = "qcom,spf-core-platform"; }; - - audio_pkt_core_platform: qcom,audio-pkt-core-platform { - compatible = "qcom,audio-pkt-core-platform"; - }; }; #include "monaco-lpi.dtsi" &spf_core_platform { - cdc_dmic01_gpios: cdc_dmic01_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; - pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; - qcom,lpi-gpios; - }; - - cdc_dmic02_gpios: cdc_dmic02_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic02_clk_active &cdc_dmic02_data_active>; - pinctrl-1 = <&cdc_dmic02_clk_sleep &cdc_dmic02_data_sleep>; - qcom,lpi-gpios; - }; - - rx_swr_gpios: rx_swr_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; - pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; - qcom,lpi-gpios; - }; - - va_swr_gpios: va_swr_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active - &tx_swr_data2_active>; - pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep - &tx_swr_data2_sleep>; - qcom,lpi-gpios; - qcom,chip-wakeup-reg = <0x003ca064>; - qcom,chip-wakeup-maskbit = <0>; - qcom,chip-wakeup-default-val = <0x1>; - }; - - bolero: bolero-cdc { - compatible = "qcom,bolero-codec"; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - }; - - va_macro: va-macro@0a730000 { - swr0: va_swr_master { - }; - }; - - rx_macro: rx-macro@0a600000 { - swr1: rx_swr_master { - }; - }; - }; - monaco_snd: sound { compatible = "qcom,monaco-asoc-snd"; - qcom,mi2s-audio-intf = <0>; - qcom,auxpcm-audio-intf = <0>; - qcom,tdm-audio-intf = <0>; - qcom,wcn-btfm = <0>; - qcom,afe-rxtx-lb = <0>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&proxy_rx>, <&proxy_tx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&va_cdc_dma_2_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, - <&afe_loopback_tx>; - asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", - "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", - "msm-dai-q6-dev.16401", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45093", - "msm-dai-cdc-dma-dev.45104", - "msm-dai-cdc-dma-dev.45105", - "msm-dai-cdc-dma-dev.45106", - "msm-dai-cdc-dma-dev.45107", - "msm-dai-cdc-dma-dev.45108", - "msm-dai-cdc-dma-dev.45109", - "msm-dai-cdc-dma-dev.45110", - "msm-dai-cdc-dma-dev.45111", - "msm-dai-cdc-dma-dev.45112", - "msm-dai-cdc-dma-dev.45113", - "msm-dai-cdc-dma-dev.45114", - "msm-dai-cdc-dma-dev.45115", - "msm-dai-cdc-dma-dev.45116", - "msm-dai-cdc-dma-dev.45118", - "msm-dai-q6-dev.24577"; + qcom,mi2s-audio-intf = <1>; }; }; diff --git a/qcom/monaco-lpi.dtsi b/qcom/monaco-lpi.dtsi index 2d3a5134c2b0..f7d9894e5389 100644 --- a/qcom/monaco-lpi.dtsi +++ b/qcom/monaco-lpi.dtsi @@ -350,7 +350,7 @@ }; }; - cdc_dmic02_clk_active: dmic02_clk_active { + cdc_dmic23_clk_active: dmic23_clk_active { mux { pins = "gpio8"; function = "func1"; @@ -363,7 +363,7 @@ }; }; - cdc_dmic02_clk_sleep: dmic02_clk_sleep { + cdc_dmic23_clk_sleep: dmic23_clk_sleep { mux { pins = "gpio8"; function = "func1"; @@ -377,7 +377,7 @@ }; }; - cdc_dmic02_data_active: dmic02_data_active { + cdc_dmic23_data_active: dmic23_data_active { mux { pins = "gpio9"; function = "func1"; @@ -390,7 +390,7 @@ }; }; - cdc_dmic02_data_sleep: dmic02_data_sleep { + cdc_dmic23_data_sleep: dmic23_data_sleep { mux { pins = "gpio9"; function = "func1"; diff --git a/qcom/monaco-slate-audio.dtsi b/qcom/monaco-slate-audio.dtsi deleted file mode 100644 index 4b1549f1781c..000000000000 --- a/qcom/monaco-slate-audio.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -#include -#include "msm-audio-lpass.dtsi" - -&soc { - spf_core_platform: spf_core_platform { - compatible = "qcom,spf-core-platform"; - }; -}; - -#include "monaco-lpi.dtsi" - -&spf_core_platform { - monaco_snd: sound { - compatible = "qcom,monaco-asoc-snd"; - qcom,mi2s-audio-intf = <1>; - }; -}; - -&msm_audio_ion { - iommus = <&apps_smmu 0x01c1 0x0>; - qcom,smmu-sid-mask = /bits/ 64 <0xf>; -}; diff --git a/qcom/monaco-wsa-audio-overlay.dtsi b/qcom/monaco-wsa-audio-overlay.dtsi index e19857c5bdfe..c65ee53d6c02 100644 --- a/qcom/monaco-wsa-audio-overlay.dtsi +++ b/qcom/monaco-wsa-audio-overlay.dtsi @@ -3,6 +3,145 @@ #include #include +&spf_core_platform { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + qcom,lpi-gpios; + }; + + va_swr_gpios: va_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + qcom,lpi-gpios; + qcom,chip-wakeup-reg = <0x003ca064>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; + }; + + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_audio_hw_vote"; + clocks = <&lpass_audio_hw_vote 0>; + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + + va_macro: va-macro@0a730000 { + swr0: va_swr_master { + }; + }; + + rx_macro: rx-macro@0a600000 { + swr1: rx_swr_master { + }; + }; + }; + + monaco_snd: sound { + qcom,mi2s-audio-intf = <0>; + qcom,auxpcm-audio-intf = <0>; + qcom,tdm-audio-intf = <0>; + qcom,wcn-btfm = <0>; + qcom,afe-rxtx-lb = <0>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&va_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16401", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-cdc-dma-dev.45093", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118", + "msm-dai-q6-dev.24577"; + }; +}; + &bolero { qcom,num-macros = <3>; qcom,bolero-version = <6>; @@ -153,8 +292,8 @@ "VA DMIC2", "VA MIC BIAS1", "VA DMIC3", "VA MIC BIAS1"; - qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; - qcom,cdc-dmic02-gpios = <&cdc_dmic02_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; @@ -168,6 +307,10 @@ }; &soc { + audio_pkt_core_platform: qcom,audio-pkt-core-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; + wsa_spkr_en: wsa_spkr_en_pinctrl { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; From 8c9d47b214b35e42c39a9607edc4bb16b4af5457 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Wed, 19 May 2021 14:31:06 +0530 Subject: [PATCH 1479/1809] ARM: dts: msm: Add GPU support for monaco IoT Add devicetree node for A702 GPU and its properties. Change-Id: If1d446493e5dc6a1bcda553e023427ba7593d3d6 --- qcom/monaco-gpu.dtsi | 196 +++++++++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 1 + 2 files changed, 197 insertions(+) create mode 100644 qcom/monaco-gpu.dtsi diff --git a/qcom/monaco-gpu.dtsi b/qcom/monaco-gpu.dtsi new file mode 100644 index 000000000000..7f42a35dae74 --- /dev/null +++ b/qcom/monaco-gpu.dtsi @@ -0,0 +1,196 @@ +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a702_zap"; + memory-region = <&pil_gpu_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@5900000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0"; + status = "ok"; + + reg = <0x5900000 0x90000>, + <0x5961000 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; + + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + qcom,chipid = <0x07000201>; + + qcom,initial-pwrlevel = <4>; + qcom,idle-timeout = <80>; + qcom,gpu-bimc-interface-clk-freq = <768000000>; + + qcom,ubwc-mode = <2>; + qcom,min-access-length = <64>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0xe1c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&rpmcc RPM_SMD_BIMC_GPU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "iface_clk", "mem_iface_clk", "gmu_clk", + "smmu_vote", "bimc_gpu_clk"; + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <3>; + + interconnect-names = "gpu_icc_path"; + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + , /* index=11 */ + ; /* index=12 */ + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1010000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <12>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <470000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <3>; + qcom,bus-max-ddr7 = <4>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x59a0000 0x10000>; + + vddcx-supply = <&gpu_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0 1>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2 0>; + qcom,iommu-dma = "disabled"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 52493d28cfda..1ac73a2e798e 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1377,6 +1377,7 @@ #include "monaco-usb.dtsi" #include "monaco-thermal.dtsi" #include "monaco-vidc.dtsi" +#include "monaco-gpu.dtsi" &qupv3_se6_2uart { status = "ok"; From 314f31fe75f73e372fad8543a4e64536f48c898f Mon Sep 17 00:00:00 2001 From: Mousumi Jana Date: Fri, 21 May 2021 13:37:44 +0530 Subject: [PATCH 1480/1809] ARM: dts: qcom: add slate VA interface Configure dynamic addition of VA dai-link based on dt property. Change-Id: I63e53c2b7340798f7b0679336d225d1950ee33d6 --- bindings/sound/qcom-audio-dev.txt | 2 ++ qcom/monaco-amic-audio-overlay.dtsi | 1 + qcom/monaco-audio-overlay.dtsi | 1 + qcom/monaco-audio.dtsi | 1 + qcom/monaco-wsa-audio-overlay.dtsi | 1 + qcom/scuba-audio.dtsi | 1 + 6 files changed, 7 insertions(+) diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 12eb1432c914..5c4fd50ae840 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1968,6 +1968,7 @@ Optional properties: - qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target - qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target - qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target +- qcom,cc-va-intf-enable : Property to specify if VA interface is used for the target - qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target - qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. - qcom,msm_audio_ssr_devs: List the snd event framework clients @@ -1983,6 +1984,7 @@ Example: status = "okay"; compatible = "qcom,monaco-asoc-snd"; qcom,mi2s-audio-intf = <0>; + qcom,cc-va-intf-enable = <0>; qcom,auxpcm-audio-intf = <0>; qcom,tdm-audio-intf = <0>; qcom,wcn-btfm = <0>; diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi index 5fb1ce51e85f..93032e9f63d4 100644 --- a/qcom/monaco-amic-audio-overlay.dtsi +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -33,6 +33,7 @@ monaco_snd: sound { qcom,mi2s-audio-intf = <0>; + qcom,cc-va-intf-enable = <0>; qcom,auxpcm-audio-intf = <0>; qcom,tdm-audio-intf = <0>; qcom,wcn-btfm = <0>; diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi index 14da90fa6147..6f685216c9f0 100644 --- a/qcom/monaco-audio-overlay.dtsi +++ b/qcom/monaco-audio-overlay.dtsi @@ -62,6 +62,7 @@ monaco_snd: sound { qcom,mi2s-audio-intf = <0>; + qcom,cc-va-intf-enable = <0>; qcom,auxpcm-audio-intf = <0>; qcom,tdm-audio-intf = <0>; qcom,wcn-btfm = <0>; diff --git a/qcom/monaco-audio.dtsi b/qcom/monaco-audio.dtsi index 4b1549f1781c..6bb558b89934 100644 --- a/qcom/monaco-audio.dtsi +++ b/qcom/monaco-audio.dtsi @@ -13,6 +13,7 @@ monaco_snd: sound { compatible = "qcom,monaco-asoc-snd"; qcom,mi2s-audio-intf = <1>; + qcom,cc-va-intf-enable = <1>; }; }; diff --git a/qcom/monaco-wsa-audio-overlay.dtsi b/qcom/monaco-wsa-audio-overlay.dtsi index c65ee53d6c02..d14d6a5fea3e 100644 --- a/qcom/monaco-wsa-audio-overlay.dtsi +++ b/qcom/monaco-wsa-audio-overlay.dtsi @@ -62,6 +62,7 @@ monaco_snd: sound { qcom,mi2s-audio-intf = <0>; + qcom,cc-va-intf-enable = <0>; qcom,auxpcm-audio-intf = <0>; qcom,tdm-audio-intf = <0>; qcom,wcn-btfm = <0>; diff --git a/qcom/scuba-audio.dtsi b/qcom/scuba-audio.dtsi index 56907c9efea1..bd1b4870f5e7 100644 --- a/qcom/scuba-audio.dtsi +++ b/qcom/scuba-audio.dtsi @@ -83,6 +83,7 @@ scuba_snd: sound { compatible = "qcom,bengal-asoc-snd"; qcom,mi2s-audio-intf = <0>; + qcom,cc-va-intf-enable = <0>; qcom,auxpcm-audio-intf = <0>; qcom,tdm-audio-intf = <0>; qcom,wcn-btfm = <0>; From 1041eac2f4f4fcf9adedbd874b533a0d9f76d7eb Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 25 May 2021 21:52:18 +0530 Subject: [PATCH 1481/1809] ARM: dts: qcom: Enable cx ipeak cooling device configuration for holi Enable cx ipeak cooling device configuration for holi target and disable device status by default. Change-Id: I2eaa347b06c40c974e24f1fc083f62d5b6324340 --- qcom/holi-thermal.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index 3055d38c3777..958f6b7d74b7 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -62,6 +62,16 @@ }; }; }; + + cxip_cdev: cxip-cdev@3ed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x3ed000 0xe008>; + qcom,thermal-client-offset = <0x8000>; + /* 4th and 5th offsets to bypass VICTIM1 */ + qcom,bypass-client-list = <0x2004 0x4004 0x6004 0xc004 0xc008 0xe004>; + #cooling-cells = <2>; + status = "disabled"; + }; }; &rpm_bus { @@ -1083,6 +1093,12 @@ type = "passive"; }; + q6_hvx_cxip: q6-hvx-cxip-trip { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + q6_hvx_cx_mon: q6-hvx-cx-mon { temperature = <100000>; hysteresis = <5000>; @@ -1097,6 +1113,11 @@ THERMAL_NO_LIMIT>; }; + q6-hvx-cxip-cdev { + trip = <&q6_hvx_cxip>; + cooling-device = <&cxip_cdev 1 1>; + }; + q6-hvx-cx-cdev0 { trip = <&q6_hvx_cx_mon>; /* throttle to 565000000Hz */ From 196a00f6fae7df3f41c8b485a8674b717f18e542 Mon Sep 17 00:00:00 2001 From: Manoj Vishwanathan Date: Mon, 24 May 2021 16:47:31 -0700 Subject: [PATCH 1482/1809] dt-bindings: Add dt bindings for silent boot mode Add device tree binding documentation support for silent mode. Change-Id: Id9d9b60cd0122a819cacb09403170e230554dc02 --- bindings/arm/msm/qcom,silent-boot.txt | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/arm/msm/qcom,silent-boot.txt diff --git a/bindings/arm/msm/qcom,silent-boot.txt b/bindings/arm/msm/qcom,silent-boot.txt new file mode 100644 index 000000000000..993ea6c63250 --- /dev/null +++ b/bindings/arm/msm/qcom,silent-boot.txt @@ -0,0 +1,42 @@ +Power management Silent mode is a boot up mode with display and +audio disabled. This mode allows the platform to boot up the kernel +without enabling the UI, thereby masking the overall system boot latency. +Predominant usage could be seen in automotive applications where +boot latency is critical. +Top 2 use cases could be: +- One possible occasion for booting silently is when the driver approaches the + vehicle and based on the trigger by proximity sensor the vehicle does a remote + start before driver comes in the car. + +- Another might be if the system needs to run in the middle of + the night to perform updates. + +Add " pm_silentmode_kernel_state" viewable/editable via sysfs. + +Kernel driver to monitor external GPIO input to indicate boot into +kernel silent mode or not. This driver sets up the GPIO and links it +up with an IRQ that is rising/falling edge triggered. +On the GPIO rising edge, the IRQ thread is used to clear the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. +On the GPIO falling edge, the IRQ thread is used to set the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. + +The Device tree entry for silent mode can be used to register a GPIO +to the driver framework and use it to communicate to the Vehicle +interface processor. + +Required properties: + +- compatible: "qcom,silent-mode" +- qcom,silent-boot-gpio: GPIO needed HW interface from VIP to SoC +- interrupts: Assign interrupt that is dual edge triggered +- interrupt-names: Name of the interrupt under /proc/interrupt + +Example: + + qcom,silent-mode { + compatible = "qcom,silent-mode"; + qcom,silent-boot-gpio = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + interrupts = < 0xc5 0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "silent_pm8150_1_gpio6"; + }; From f0213a4e15aaff0fecd43a6e66aa260e61b57808 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 26 May 2021 00:04:10 +0530 Subject: [PATCH 1483/1809] ARM: dts: qcom: Remove duplicate thermal zone phandle for monaco Thermal zone phandle is defined in two places. Remove duplicate thermal zone phandle for monaco. Change-Id: I44bcffc083ecf74b7472693c42ed9c9e367adccb --- qcom/monaco.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f9abfe7a58b3..23d4d3b68729 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1428,8 +1428,6 @@ }; }; - thermal_zones: thermal-zones { }; - system_pm_rpm { compatible = "qcom,system-pm-rpm"; }; From ee8592bd8c270622f24f4ce59994947e375d0bb1 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 11 May 2021 21:59:05 +0530 Subject: [PATCH 1484/1809] ARM: dts: qcom: enable pmic alarm sensor and BCL thermal zones for monaco Enable pm5100 pmic alarm thermal zone and BCL thermal zones for monaco. Change-Id: I4585c758c57b0a8b3d34e5d790251194eb8c476c --- qcom/monaco-idp-v1-common.dtsi | 1 + qcom/monaco-thermal-overlay.dtsi | 101 ++++++++++++++++++++++ qcom/pm5100.dtsi | 138 +++++++++++++++++++++++++++++++ 3 files changed, 240 insertions(+) create mode 100644 qcom/monaco-thermal-overlay.dtsi diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi index e69de29bb2d1..0643de7d8f46 100644 --- a/qcom/monaco-idp-v1-common.dtsi +++ b/qcom/monaco-idp-v1-common.dtsi @@ -0,0 +1 @@ +#include "monaco-thermal-overlay.dtsi" diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi new file mode 100644 index 000000000000..13c385a73423 --- /dev/null +++ b/qcom/monaco-thermal-overlay.dtsi @@ -0,0 +1,101 @@ +#include + +&thermal_zones { + pm5100-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm5100_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + trip1_cpu2 { + trip = <&pm5100_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm5100_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + pm5100-bcl-lvl0 { + cooling-maps { + cpu0_cdev { + trip = <&bcl_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + + cpu2_cdev { + trip = <&bcl_lvl0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + cpu3_cdev { + trip = <&bcl_lvl0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + pm5100-bcl-lvl1 { + cooling-maps { + cpu0_cdev { + trip = <&bcl_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + cpu1_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + modem_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem1_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&modem_tj 1 1>; + }; + }; + }; + + pm5100-bcl-lvl2 { + cooling-maps { + modem_cdev { + trip = <&bcl_lvl2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu0 { + trip = <&socd_trip>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + soc_cpu2 { + trip = <&socd_trip>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + soc_cpu3 { + trip = <&socd_trip>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; +}; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 5fbe48b0fca5..9417b82f743c 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -154,5 +154,143 @@ pm5100_cdc: qcom,pm5100-cdc { compatible = "qcom,pm5100-spmi"; }; + + pm5100_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x0 0x47 0x0 IRQ_TYPE_NONE>, + <0x0 0x47 0x1 IRQ_TYPE_NONE>, + <0x0 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + qcom,ibat-ccm-hw-support; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&thermal_zones { + pm5100-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_tz>; + + trips { + pm5100_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm5100_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pm5100_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm5100-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <1100>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm5100-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <1500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm5100-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_bcl 5>; + + trips { + bcl_lvl0: bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm5100-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_bcl 6>; + + trips { + bcl_lvl1: bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm5100-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm5100_bcl 7>; + + trips { + bcl_lvl2: bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_soc>; + + trips { + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; }; }; From e6a51215e99a9904204cb1683dbe6fd0027528f6 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 25 May 2021 12:06:10 -0700 Subject: [PATCH 1485/1809] ARM: dts: msm: Set qcom,rmnet_in_use_tcm_mem with RMNET composition To select LLCC TCM based memory with USB RMNET IN data buffers, set qcom,rmnet_in_use_tcm_mem property with USB RMNET composition. Change-Id: I0e728dfe6af35679ab18e151eede9b9205e7160c --- qcom/sdxlemur-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d63d20923ae4..1b9631e0101c 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -287,6 +287,7 @@ qcom,pid = <0x9067>; qcom,composition = "mass_storage.0,gsi.rmnet|mass_storage.1,gsi.mbim"; qcom,bmAttributes = <0xa0>; + qcom,rmnet_in_use_tcm_mem; }; composition5 { From d787badd624ef2c1bd9be12325c596385bd0eecc Mon Sep 17 00:00:00 2001 From: Wu Gao Date: Tue, 25 May 2021 20:03:39 -0700 Subject: [PATCH 1486/1809] ARM: dts: msm: Add cnss dtsi to cpe Adds cnss dtsi to cpe as requirement. Change-Id: Ia6edbcc800ae1f21e72d58f74b1ac8cdd8491921 --- qcom/sdxlemur-mtp-cpe.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index ead27a18b95a..4065f115e2a0 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -47,7 +47,9 @@ }; }; + &pcie0 { + qcom,boot-option = <0x1>; pcie-i2c-phandle = <&i2c_5>; vreg-3p3-supply = <&aqr_vreg>; @@ -79,6 +81,14 @@ /* BDF 2.2.0 */ pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 { reg = <0x1000 0x0 0x0 0x0 0x0>; + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + }; }; /* BDF 2.3.0 */ @@ -87,3 +97,5 @@ }; }; }; + +#include "sdxlemur-cnss.dtsi" From 0f0d11561292cbf29585341e12eeb26a663db9b8 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 19 May 2021 22:16:37 +0530 Subject: [PATCH 1487/1809] ARM: dts: msm: Fix incorrect regulator label references With overlay support observing regulator labels references from previous definations in "holi-regulators-pm6350.dtsi" are not getting overridden from "holi-regulator-pm6125.dtsi" causing disable clients to refer to disable nodes. Fix this by using alternative label name for clients using this regulators. While at it disable both device and resource node for holi-pm6125 regulators. Also only disable nodes which are present on holi and not present for holi-pm6125. Change-Id: Ibfd931e91eee9380fb14026a2569ef592c96a9c6 --- qcom/blair-atp.dtsi | 228 ++++++++++++++++++++ qcom/blair.dtsi | 24 +-- qcom/holi-pm6125-overlay.dtsi | 76 +++++-- qcom/holi-regulators-pm6125.dtsi | 356 +++++++++++++++++++++++-------- qcom/holi.dtsi | 4 +- 5 files changed, 567 insertions(+), 121 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 5d917c914b60..fba76421c662 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -40,146 +40,286 @@ /* Disable all PM6125 and PMR735a rpm-regulators */ rpm-regulator-smpa6 { status = "disabled"; + regulator-s6 { + status = "disabled"; + }; }; rpm-regulator-smpa7 { status = "disabled"; + regulator-s7 { + status = "disabled"; + }; }; rpm-regulator-smpa8 { status = "disabled"; + regulator-s8 { + status = "disabled"; + }; + + S3A_LEVEL { + status = "disabled"; + }; + + S3A_LEVEL_ao { + status = "disabled"; + }; }; rpm-regulator-ldoa1 { status = "disabled"; + regulator-l1 { + status = "disabled"; + }; + + regulator-l1-level { + status = "disabled"; + }; }; rpm-regulator-ldoa2 { status = "disabled"; + regulator-l2 { + status = "disabled"; + }; }; rpm-regulator-ldoa3 { status = "disabled"; + regulator-l3 { + status = "disabled"; + }; }; rpm-regulator-ldoa4 { status = "disabled"; + regulator-l4 { + status = "disabled"; + }; }; rpm-regulator-ldoa5 { status = "disabled"; + regulator-l5 { + status = "disabled"; + }; }; rpm-regulator-ldoa6 { status = "disabled"; + regulator-l6 { + status = "disabled"; + }; }; rpm-regulator-ldoa7 { status = "disabled"; + regulator-l7 { + status = "disabled"; + }; }; rpm-regulator-ldoa8 { status = "disabled"; + regulator-l8 { + status = "disabled"; + }; }; rpm-regulator-ldoa9 { status = "disabled"; + regulator-l9 { + status = "disabled"; + }; }; rpm-regulator-ldoa10 { status = "disabled"; + regulator-l10 { + status = "disabled"; + }; }; rpm-regulator-ldoa11 { status = "disabled"; + regulator-l11 { + status = "disabled"; + }; }; rpm-regulator-ldoa12 { status = "disabled"; + regulator-l12 { + status = "disabled"; + }; }; rpm-regulator-ldoa13 { status = "disabled"; + regulator-l13 { + status = "disabled"; + }; }; rpm-regulator-ldoa14 { status = "disabled"; + regulator-l14 { + status = "disabled"; + }; }; rpm-regulator-ldoa15 { status = "disabled"; + regulator-l15 { + status = "disabled"; + }; }; rpm-regulator-ldoa16 { status = "disabled"; + regulator-l16 { + status = "disabled"; + }; }; rpm-regulator-ldoa17 { status = "disabled"; + regulator-l17 { + status = "disabled"; + }; }; rpm-regulator-ldoa18 { status = "disabled"; + regulator-l18 { + status = "disabled"; + }; }; rpm-regulator-ldoa19 { status = "disabled"; + regulator-l19 { + status = "disabled"; + }; }; rpm-regulator-ldoa20 { status = "disabled"; + regulator-l20 { + status = "disabled"; + }; }; rpm-regulator-ldoa21 { status = "disabled"; + regulator-l21 { + status = "disabled"; + }; }; rpm-regulator-ldoa22 { status = "disabled"; + regulator-l22 { + status = "disabled"; + }; }; rpm-regulator-ldoa23 { status = "disabled"; + regulator-l23 { + status = "disabled"; + }; }; rpm-regulator-ldoa24 { status = "disabled"; + regulator-l24 { + status = "disabled"; + }; }; rpm-regulator-smpe1 { status = "disabled"; + regulator-s1 { + status = "disabled"; + }; + + mx_cdev { + status = "disabled"; + }; }; rpm-regulator-smpe2 { status = "disabled"; + regulator-s2 { + status = "disabled"; + }; + + regulator-s2-level { + status = "disabled"; + }; + + regulator-s2-floor-level { + status = "disabled"; + }; + + regulator-s2-level-ao { + status = "disabled"; + }; + + cx_cdev { + status = "disabled"; + }; }; rpm-regulator-ldoe1 { status = "disabled"; + regulator-l1 { + status = "disabled"; + }; }; rpm-regulator-ldoe2 { status = "disabled"; + regulator-l2 { + status = "disabled"; + }; }; rpm-regulator-ldoe3 { status = "disabled"; + regulator-l3 { + status = "disabled"; + }; }; rpm-regulator-ldoe4 { status = "disabled"; + regulator-l4 { + status = "disabled"; + }; }; rpm-regulator-ldoe5 { status = "disabled"; + regulator-l5 { + status = "disabled"; + }; }; rpm-regulator-ldoe6 { status = "disabled"; + regulator-l6 { + status = "disabled"; + }; }; rpm-regulator-ldoe7 { status = "disabled"; + regulator-l7 { + status = "disabled"; + }; }; }; @@ -191,6 +331,50 @@ #include "pm6150l-rpm-regulator.dtsi" #include "holi-regulators-pm6350.dtsi" +/* Enable explicitly disabled regulator resources nodes */ +&rpm_bus { + /* Enable gfx_cdev for PM6350 */ + rpm-regulator-smpa3 { + regulator-s3-level { + status = "okay"; + }; + + regulator-s3-level-ao { + status = "okay"; + }; + + gfx-cdev { + status = "okay"; + }; + }; + + /* Enable mx_cdev for PM6350 */ + rpm-regulator-smpa5 { + regulator-s5-level { + status = "okay"; + }; + + regulator-s5-floor-level { + status = "okay"; + }; + + regulator-s5-level-ao { + status = "okay"; + }; + + mx-cdev-lvl { + status = "okay"; + }; + }; + + /* Enable mx_cdev for PM6150A */ + rpm-regulator-smpe1 { + cx-cdev-lvl { + status = "okay"; + }; + }; +}; + #include "holi-atp.dtsi" &qusb_phy0 { @@ -222,3 +406,47 @@ qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ }; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&S5A_LEVEL>; +}; + +&dispcc { + vdd_cx-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&gpucc { + vdd_cx-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ + vdd_mx-supply = <&S5A_LEVEL>; /* VDD_MX_LEVEL */ + vdd_gx-supply = <&S3A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&gpu_cx_gdsc { + parent-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&gpu_gx_gdsc { + parent-supply = <&S3A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&gcc { + vdd_cx-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ + vdd_mx-supply = <&S5A_LEVEL>; /* VDD_MX_LEVEL */ +}; + +&msm_gpu { + vdd-parent-supply = <&S3A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&pil_turing { + vdd_cx-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&pil_modem { + vdd_cx-supply = <&S1E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&pil_lpass { + vdd_lpi_cx-supply = <&L1A_LEVEL>; + vdd_lpi_mx-supply = <&L17A_LEVEL>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 9eeaf76c9a38..ffdba4b621cb 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1219,8 +1219,8 @@ compatible = "qcom,blair-gcc", "syscon"; reg = <0x1400000 0x1f0000>; reg_names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_cx-supply = <&S2E_LEVEL>; + vdd_mx-supply = <&S1E_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; @@ -1233,7 +1233,7 @@ compatible = "qcom,blair-dispcc", "syscon"; reg = <0x5f00000 0x20000>; reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S2E_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; @@ -1245,9 +1245,9 @@ compatible = "qcom,blair-gpucc", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_gx-supply = <&VDD_GFX_LEVEL>; + vdd_cx-supply = <&S2E_LEVEL>; + vdd_mx-supply = <&S1E_LEVEL>; + vdd_gx-supply = <&S8A_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; @@ -2896,9 +2896,9 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; - vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + vdd_lpi_cx-supply = <&L1A_LEVEL>; qcom,vdd_lpi_cx-uV-uA = ; - vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + vdd_lpi_mx-supply = <&L17A_LEVEL>; qcom,vdd_lpi_mx-uV-uA = ; qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; @@ -2936,7 +2936,7 @@ compatible = "qcom,pil-tz-generic"; reg = <0xb000000 0x100000>; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S2E_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,proxy-reg-names = "vdd_cx"; @@ -2982,7 +2982,7 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S2E_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,proxy-reg-names = "vdd_cx"; @@ -3436,12 +3436,12 @@ }; &gpu_cx_gdsc { - parent-supply = <&VDD_CX_LEVEL>; + parent-supply = <&S2E_LEVEL>; status = "ok"; }; &gpu_gx_gdsc { - parent-supply = <&VDD_GFX_LEVEL>; + parent-supply = <&S8A_LEVEL>; status = "ok"; }; diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index db2a9d9c1186..4d9a2a267dfc 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -1,4 +1,3 @@ - &mdss_dsi_phy0 { vdda-0p9-supply = <&S1E_LEVEL>; }; @@ -7,23 +6,60 @@ vdda-1p2-supply = <&L4A>; }; -&soc { - icnss: qcom,icnss@C800000 { - vdd-cx-mx-supply = <&L2E>; - vdd-1.8-xo-supply = <&L16A>; - vdd-1.3-rfa-supply = <&L2A>; - vdd-3.3-ch1-supply = <&L21A>; - vdd-3.3-ch0-supply = <&L23A>; - qcom,vdd-cx-mx-config = <640000 640000>; - qcom,vdd-3.3-ch1-config = <3000000 3312000>; - qcom,vdd-3.3-ch0-config = <3000000 3312000>; - }; - - bluetooth: bt_wcn3990 { - qcom,bt-vdd-io-supply = <&L9A>; /* IO */ - qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ - qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ - qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ - }; - +&icnss { + vdd-cx-mx-supply = <&L2E>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L2A>; + vdd-3.3-ch1-supply = <&L21A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; +}; + +&bluetooth { + qcom,bt-vdd-io-supply = <&L9A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ +}; + +&dispcc { + vdd_cx-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&gpucc { + vdd_cx-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ + vdd_mx-supply = <&S1E_LEVEL>; /* VDD_MX_LEVEL */ + vdd_gx-supply = <&S8A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&gpu_cx_gdsc { + parent-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&gpu_gx_gdsc { + parent-supply = <&S8A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&gcc { + vdd_cx-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ + vdd_mx-supply = <&S1E_LEVEL>; /* VDD_MX_LEVEL */ +}; + +&msm_gpu { + vdd-parent-supply = <&S8A_LEVEL>; /* VDD_GFX_LEVEL */ +}; + +&pil_turing { + vdd_cx-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&pil_modem { + vdd_cx-supply = <&S2E_LEVEL>; /* VDD_CX_LEVEL */ +}; + +&pil_lpass { + vdd_lpi_cx-supply = <&L1A_LEVEL>; + vdd_lpi_mx-supply = <&L17A_LEVEL>; }; diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index 5f3956474160..defdc3ef7781 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -39,165 +39,333 @@ /delete-node/ rpm-regulator-ldoe5; /delete-node/ rpm-regulator-ldoe7; - /* Disable PM6350 and PM6150L rpm-regulators */ + /* + * Disable PM6350 and PM6150L rpm-regulators which are not been used + * for holi-pm6125. + */ rpm-regulator-smpa1 { status = "disabled"; + + regulator-s1 { + status = "disabled"; + }; }; rpm-regulator-smpa2 { status = "disabled"; + + regulator-s2 { + status = "disabled"; + }; }; + /* Disable gfx_cdev for PM6350 */ rpm-regulator-smpa3 { status = "disabled"; + + regulator-s3 { + status = "disabled"; + }; + + regulator-s3-level { + status = "disabled"; + }; + + regulator-s3-level-ao { + status = "disabled"; + }; + + gfx-cdev { + status = "disabled"; + }; }; + /* Disable mx_cdev for PM6150A */ rpm-regulator-smpa5 { status = "disabled"; - }; - rpm-regulator-ldoa1 { - status = "disabled"; - }; + regulator-s5 { + status = "disabled"; + }; - rpm-regulator-ldoa2 { - status = "disabled"; - }; + regulator-s5-level { + status = "disabled"; + }; - rpm-regulator-ldoa3 { - status = "disabled"; - }; + regulator-s5-floor-level { + status = "disabled"; + }; - rpm-regulator-ldoa4 { - status = "disabled"; - }; + regulator-s5-level-ao { + status = "disabled"; + }; - rpm-regulator-ldoa5 { - status = "disabled"; - }; - - rpm-regulator-ldoa6 { - status = "disabled"; - }; - - rpm-regulator-ldoa7 { - status = "disabled"; - }; - - rpm-regulator-ldoa8 { - status = "disabled"; - }; - - rpm-regulator-ldoa9 { - status = "disabled"; - }; - - rpm-regulator-ldoa10 { - status = "disabled"; - }; - - rpm-regulator-ldoa11 { - status = "disabled"; - }; - - rpm-regulator-ldoa12 { - status = "disabled"; - }; - - rpm-regulator-ldoa13 { - status = "disabled"; - }; - - rpm-regulator-ldoa14 { - status = "disabled"; - }; - - rpm-regulator-ldoa15 { - status = "disabled"; - }; - - rpm-regulator-ldoa16 { - status = "disabled"; - }; - - rpm-regulator-ldoa17 { - status = "disabled"; - }; - - rpm-regulator-ldoa18 { - status = "disabled"; - }; - - rpm-regulator-ldoa19 { - status = "disabled"; - }; - - rpm-regulator-ldoa20 { - status = "disabled"; - }; - - rpm-regulator-ldoa21 { - status = "disabled"; - }; - - rpm-regulator-ldoa22 { - status = "disabled"; + mx-cdev-lvl { + status = "disabled"; + }; }; rpm-regulator-bobe { status = "disabled"; + + regulator-pm6150a-bob { + status = "disabled"; + }; + + regulator-pm6150a-bob-ao { + status = "disabled"; + }; }; + rpm-regulator-ldoa1 { + status = "disabled"; + regulator-l1 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + status = "disabled"; + regulator-l2 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + status = "disabled"; + regulator-l3 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + status = "disabled"; + regulator-l4 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + status = "disabled"; + regulator-l5 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + status = "disabled"; + regulator-l6 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + status = "disabled"; + regulator-l7 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + status = "disabled"; + regulator-l8 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + status = "disabled"; + regulator-l9 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + status = "disabled"; + regulator-l10 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + status = "disabled"; + regulator-l11 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + status = "disabled"; + regulator-l12 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + status = "disabled"; + regulator-l13 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + status = "disabled"; + regulator-l14 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + status = "disabled"; + regulator-l15 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + status = "disabled"; + regulator-l16 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + status = "disabled"; + regulator-l17 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + status = "disabled"; + regulator-l18 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + status = "disabled"; + regulator-l19 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + status = "disabled"; + regulator-l20 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + status = "disabled"; + regulator-l21 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + status = "disabled"; + regulator-l22 { + status = "disabled"; + }; + }; + + /* Disable cx_cdev for PM6150A */ rpm-regulator-smpe1 { status = "disabled"; + + regulator-s1 { + status = "disabled"; + }; + + cx-cdev-lvl { + status = "disabled"; + }; }; rpm-regulator-smpe8 { status = "disabled"; + regulator-s8 { + status = "disabled"; + }; }; rpm-regulator-ldoe1 { status = "disabled"; + regulator-l1 { + status = "disabled"; + }; }; rpm-regulator-ldoe2 { status = "disabled"; + regulator-l2 { + status = "disabled"; + }; }; rpm-regulator-ldoe3 { status = "disabled"; + regulator-l3 { + status = "disabled"; + }; }; rpm-regulator-ldoe4 { status = "disabled"; + regulator-l4 { + status = "disabled"; + }; }; rpm-regulator-ldoe5 { status = "disabled"; + regulator-l5 { + status = "disabled"; + }; }; rpm-regulator-ldoe6 { status = "disabled"; + regulator-l6 { + status = "disabled"; + }; }; rpm-regulator-ldoe7 { status = "disabled"; + regulator-l7 { + status = "disabled"; + }; }; rpm-regulator-ldoe8 { status = "disabled"; + regulator-l8 { + status = "disabled"; + }; }; rpm-regulator-ldoe9 { status = "disabled"; + regulator-l9 { + status = "disabled"; + }; }; rpm-regulator-ldoe10 { status = "disabled"; + regulator-l10 { + status = "disabled"; + }; }; rpm-regulator-ldoe11 { status = "disabled"; + regulator-l11 { + status = "disabled"; + }; }; }; @@ -259,6 +427,7 @@ /* Dummy node */ gfx_cdev: gfx-cdev { + status = "disabled"; }; }; @@ -343,10 +512,13 @@ rpm-regulator-ldoa8 { status = "okay"; + proxy-supply = <&pm6125_l8>; L8A: pm6125_l8: regulator-l8 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1304000>; qcom,init-voltage = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <857000>; status = "okay"; }; }; @@ -393,10 +565,13 @@ rpm-regulator-ldoa13 { status = "okay"; + proxy-supply = <&pm6125_l13>; L13A: pm6125_l13: regulator-l13 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1980000>; qcom,init-voltage = <1650000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <62000>; status = "okay"; }; }; @@ -524,7 +699,7 @@ status = "okay"; qcom,resource-name = "rwmx"; qcom,resource-id = <0>; - proxy-supply = <&VDD_MX_LEVEL>; + proxy-supply = <&pmr735a_s1_level>; VDD_MX_LEVEL: S1E_LEVEL: pmr735a_s1_level: regulator-s1-level { compatible = "qcom,rpm-smd-regulator"; @@ -571,6 +746,7 @@ /* Dummy node */ mx_cdev: mx-cdev-lvl { + status = "disabled"; }; }; @@ -580,11 +756,11 @@ status = "okay"; qcom,resource-name = "rwcx"; qcom,resource-id = <0>; - proxy-supply = <&VDD_CX_LEVEL>; + proxy-supply = <&pmr735a_s2_level>; VDD_CX_LEVEL: S2E_LEVEL: pmr735a_s2_level: regulator-s2-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmr735a_s1_level"; + regulator-name = "pmr735a_s2_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -627,15 +803,19 @@ /* Dummy node */ cx_cdev: cx-cdev-lvl { + status = "disabled"; }; }; rpm-regulator-ldoe1 { status = "okay"; + proxy-supply = <&pmr735a_l1>; L1E: pmr735a_l1: regulator-l1 { regulator-min-microvolt = <570000>; regulator-max-microvolt = <650000>; qcom,init-voltage = <600000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <62000>; status = "okay"; }; }; @@ -707,5 +887,7 @@ reg = <0x162F000 0x84>; regulator-name = "refgen"; regulator-enable-ramp-delay = <5>; + proxy-supply = <&refgen>; + qcom,proxy-consumer-enable; }; }; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 7f54e19f394c..8dfe89b0f2b4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2893,7 +2893,7 @@ }; }; - qcom,lpass@a400000 { + pil_lpass: qcom,lpass@a400000 { compatible = "qcom,pil-tz-generic"; reg = <0xa400000 0x00100>; @@ -2936,7 +2936,7 @@ qcom,smem-state-names = "qcom,force-stop"; }; - qcom,turing@b000000 { + pil_turing: qcom,turing@b000000 { compatible = "qcom,pil-tz-generic"; reg = <0xb000000 0x100000>; From 8a54595cc31da544fb93ca4954f5e8ae2d05beae Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 21 May 2021 12:42:16 -0700 Subject: [PATCH 1488/1809] ARM: dts: msm: Disable EP initiated BW scaling on switch for sdxlemur Some EPs are capable of initiating Gen switching request. This capability is only required for direct attach. When these EPs are connected to downstream ports of switch, disable this feature by not creating BW scaling MHI event ring. Change-Id: Ifdcd90329201f6a180cd8ddece671c7746e5c635 --- qcom/sdxlemur-mtp-cpe.dtsi | 25 +++++++++++++++++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 4065f115e2a0..5fb9b8f8c7b4 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -99,3 +99,28 @@ }; #include "sdxlemur-cnss.dtsi" + +&wlan { + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; +}; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index ee8d7977ed58..42ae590813bb 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -75,3 +75,28 @@ }; }; }; + +&wlan { + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; +}; From ae49117a9e7369e5ad5b0418720a833079426067 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Sun, 23 May 2021 10:57:23 +0530 Subject: [PATCH 1489/1809] ARM: dts: msm: Update the LDO2/3A min-max voltages Update the LDO2A and LDO3A min-max voltages for holi-pm6125, While at it also add S5A regulator as per HW recommendation. Change-Id: I1b4f6868335d7d4f8657319047eb38c694b32c7f --- qcom/blair.dtsi | 12 ------------ qcom/holi-regulators-pm6125.dtsi | 22 ++++++++++++++++------ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index ffdba4b621cb..33db45e9db8a 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3359,18 +3359,6 @@ #include "blair-usb.dtsi" #include "ipcc-test-holi.dtsi" -&L2A { - regulator-min-microvolt = <1170000>; - regulator-max-microvolt = <1304000>; - qcom,init-voltage = <1170000>; -}; - -&L3A { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - qcom,init-voltage = <1100000>; -}; - &L7A { regulator-min-microvolt = <720000>; }; diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index defdc3ef7781..3e5fc3cec7bc 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -373,6 +373,16 @@ #include "pmr735a-rpm-regulator.dtsi" &rpm_bus { + rpm-regulator-smpa5 { + status = "okay"; + S5A: pm6125_s5: regulator-s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + qcom,init-voltage = <952000>; + status = "okay"; + }; + }; + rpm-regulator-smpa6 { status = "okay"; S6A: pm6125_s6: regulator-s6 { @@ -453,9 +463,9 @@ rpm-regulator-ldoa2 { status = "okay"; L2A: pm6125_l2: regulator-l2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - qcom,init-voltage = <1100000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1170000>; status = "okay"; }; }; @@ -463,9 +473,9 @@ rpm-regulator-ldoa3 { status = "okay"; L3A: pm6125_l3: regulator-l3 { - regulator-min-microvolt = <1170000>; - regulator-max-microvolt = <1304000>; - qcom,init-voltage = <1170000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; status = "okay"; }; }; From 7f2278ce4f664ee19ea7bebd0dcda2d6bbf8f3a6 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 24 May 2021 22:58:30 +0530 Subject: [PATCH 1490/1809] ARM: dts: msm: Remove generic labels for regulators Remove generic (VDD_XX) labels for holi-pm6350 and holi-pm6125 regulators. Change-Id: I9bb4755f428d7848efe8aa7d43ca05a96fe07ae0 --- qcom/blair.dtsi | 1 + qcom/holi-gpu.dtsi | 2 +- qcom/holi-regulators-pm6125.dtsi | 10 ---------- qcom/holi-regulators-pm6350.dtsi | 20 +++++--------------- qcom/holi.dtsi | 24 ++++++++++++------------ 5 files changed, 19 insertions(+), 38 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 33db45e9db8a..60b42bf4bb09 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3443,6 +3443,7 @@ &msm_gpu { qcom,chipid = <0x06010901>; + vdd-parent-supply = <&S8A_LEVEL>; /delete-node/qcom,gpu-pwrlevel-bins; diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index d18c1771c956..a032c4b483a8 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -32,7 +32,7 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; - vdd-parent-supply = <&VDD_GFX_LEVEL>; + vdd-parent-supply = <&S3A_LEVEL>; vdd-parent-min-corner = ; qcom,chipid = <0x06010900>; diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index 3e5fc3cec7bc..69afd4ccc6f4 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -409,7 +409,6 @@ qcom,resource-name = "rwgx"; qcom,resource-id = <0>; qcom,always-wait-for-ack; - VDD_GFX_LEVEL: S8A_LEVEL: pm6125_s8_level: regulator-s8-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6125_s8_level"; @@ -423,7 +422,6 @@ qcom,use-voltage-level; }; - VDD_GFX_LEVEL_AO: S8A_LEVEL_AO: pm6125_s8_level_ao: regulator-s8-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6125_s8_level_ao"; @@ -447,7 +445,6 @@ status = "okay"; qcom,resource-name = "rwlc"; qcom,resource-id = <0>; - VDD_LPI_CX_LEVEL: L1A_LEVEL: pm6125_l1_level: regulator-l1-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6125_l1_level"; @@ -621,7 +618,6 @@ status = "okay"; qcom,resource-name = "rwlm"; qcom,resource-id = <0>; - VDD_LPI_MX_LEVEL: L17A_LEVEL: pm6125_l17_level: regulator-l17-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6125_l17_level"; @@ -710,7 +706,6 @@ qcom,resource-name = "rwmx"; qcom,resource-id = <0>; proxy-supply = <&pmr735a_s1_level>; - VDD_MX_LEVEL: S1E_LEVEL: pmr735a_s1_level: regulator-s1-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmr735a_s1_level"; @@ -728,7 +723,6 @@ qcom,use-voltage-level; }; - VDD_MX_FLOOR_LEVEL: S1E_FLOOR_LEVEL: pmr735a_s1_floor_level: regulator-s1-floor-level { compatible = "qcom,rpm-smd-regulator"; @@ -742,7 +736,6 @@ qcom,always-send-voltage; }; - VDD_MX_LEVEL_AO: S1E_LEVEL_AO: pmr735a_s1_level_ao: regulator-s1-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmr735a_s1_level_ao"; @@ -767,7 +760,6 @@ qcom,resource-name = "rwcx"; qcom,resource-id = <0>; proxy-supply = <&pmr735a_s2_level>; - VDD_CX_LEVEL: S2E_LEVEL: pmr735a_s2_level: regulator-s2-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmr735a_s2_level"; @@ -785,7 +777,6 @@ qcom,use-voltage-level; }; - VDD_CX_FLOOR_LEVEL: S2E_FLOOR_LEVEL: pmr735a_s2_floor_level: regulator-s2-floor-level { compatible = "qcom,rpm-smd-regulator"; @@ -799,7 +790,6 @@ qcom,always-send-voltage; }; - VDD_CX_LEVEL_AO: S2E_LEVEL_AO: pmr735a_s2_level_ao: regulator-s2-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pmr735a_s2_level_ao"; diff --git a/qcom/holi-regulators-pm6350.dtsi b/qcom/holi-regulators-pm6350.dtsi index 6de77ac0f4ba..179cd8900a8f 100644 --- a/qcom/holi-regulators-pm6350.dtsi +++ b/qcom/holi-regulators-pm6350.dtsi @@ -27,7 +27,6 @@ qcom,resource-name = "rwgx"; qcom,resource-id = <0>; qcom,always-wait-for-ack; - VDD_GFX_LEVEL: S3A_LEVEL: pm6350_s3_level: regulator-s3-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_s3_level"; @@ -41,7 +40,6 @@ qcom,use-voltage-level; }; - VDD_GFX_LEVEL_AO: S3A_LEVEL_AO: pm6350_s3_level_ao: regulator-s3-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_s3_level_ao"; @@ -55,7 +53,7 @@ gfx_cdev: gfx-cdev { compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&VDD_GFX_LEVEL_AO>; + regulator-cdev-supply = <&S3A_LEVEL_AO>; regulator-levels = ; #cooling-cells = <2>; @@ -67,8 +65,7 @@ status = "okay"; qcom,resource-name = "rwmx"; qcom,resource-id = <0>; - proxy-supply = <&VDD_MX_LEVEL>; - VDD_MX_LEVEL: + proxy-supply = <&S5A_LEVEL>; S5A_LEVEL: pm6350_s5_level: regulator-s5-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_s5_level"; @@ -86,7 +83,6 @@ qcom,use-voltage-level; }; - VDD_MX_FLOOR_LEVEL: S5A_FLOOR_LEVEL: pm6350_s5_floor_level: regulator-s5-floor-level { compatible = "qcom,rpm-smd-regulator"; @@ -100,7 +96,6 @@ qcom,always-send-voltage; }; - VDD_MX_LEVEL_AO: S5A_LEVEL_AO: pm6350_s5_level_ao: regulator-s5-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_s5_level_ao"; @@ -114,7 +109,7 @@ mx_cdev: mx-cdev-lvl { compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-cdev-supply = <&S5A_LEVEL>; regulator-levels = ; #cooling-cells = <2>; @@ -126,7 +121,6 @@ status = "okay"; qcom,resource-name = "rwlc"; qcom,resource-id = <0>; - VDD_LPI_CX_LEVEL: L1A_LEVEL: pm6350_l1_level: regulator-l1-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_l1_level"; @@ -297,7 +291,6 @@ status = "okay"; qcom,resource-name = "rwlm"; qcom,resource-id = <0>; - VDD_LPI_MX_LEVEL: L17A_LEVEL: pm6350_l17_level: regulator-l17-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6350_l17_level"; @@ -390,8 +383,7 @@ status = "okay"; qcom,resource-name = "rwcx"; qcom,resource-id = <0>; - proxy-supply = <&VDD_CX_LEVEL>; - VDD_CX_LEVEL: + proxy-supply = <&S1E_LEVEL>; S1E_LEVEL: pm6150a_s1_level: regulator-s1-level { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6150a_s1_level"; @@ -409,7 +401,6 @@ qcom,use-voltage-level; }; - VDD_CX_FLOOR_LEVEL: S1E_FLOOR_LEVEL: pm6150a_s1_floor_level: regulator-s1-floor-level { compatible = "qcom,rpm-smd-regulator"; @@ -423,7 +414,6 @@ qcom,always-send-voltage; }; - VDD_CX_LEVEL_AO: S1E_LEVEL_AO: pm6150a_s1_level_ao: regulator-s1-level-ao { compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm6150a_s1_level_ao"; @@ -437,7 +427,7 @@ cx_cdev: cx-cdev-lvl { compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>; + regulator-cdev-supply = <&S1E_FLOOR_LEVEL>; regulator-levels = ; #cooling-cells = <2>; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 8dfe89b0f2b4..5e70324b441b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1224,8 +1224,8 @@ compatible = "qcom,holi-gcc", "syscon"; reg = <0x1400000 0x1f0000>; reg_names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_cx-supply = <&S1E_LEVEL>; + vdd_mx-supply = <&S5A_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; @@ -1238,7 +1238,7 @@ compatible = "qcom,holi-dispcc", "syscon"; reg = <0x5f00000 0x20000>; reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S1E_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; @@ -1250,9 +1250,9 @@ compatible = "qcom,holi-gpucc", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_gx-supply = <&VDD_GFX_LEVEL>; + vdd_cx-supply = <&S1E_LEVEL>; + vdd_mx-supply = <&S5A_LEVEL>; + vdd_gx-supply = <&S3A_LEVEL>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; @@ -2901,9 +2901,9 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; - vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + vdd_lpi_cx-supply = <&L1A_LEVEL>; qcom,vdd_lpi_cx-uV-uA = ; - vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + vdd_lpi_mx-supply = <&L17A_LEVEL>; qcom,vdd_lpi_mx-uV-uA = ; qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; @@ -2940,7 +2940,7 @@ compatible = "qcom,pil-tz-generic"; reg = <0xb000000 0x100000>; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S1E_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,proxy-reg-names = "vdd_cx"; @@ -2985,7 +2985,7 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx-supply = <&S1E_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,proxy-reg-names = "vdd_cx"; @@ -3445,12 +3445,12 @@ }; &gpu_cx_gdsc { - parent-supply = <&VDD_CX_LEVEL>; + parent-supply = <&S1E_LEVEL>; status = "ok"; }; &gpu_gx_gdsc { - parent-supply = <&VDD_GFX_LEVEL>; + parent-supply = <&S3A_LEVEL>; status = "ok"; }; From a79eeb5225f1121bab2688d7adc3a74202c1c808 Mon Sep 17 00:00:00 2001 From: sasevs Date: Thu, 20 May 2021 10:26:01 +0530 Subject: [PATCH 1491/1809] ARM: dts: qcom: add ipc and codec cdev nodes Add audio-cc-ipc and cc-codec cdev nodes in slate.dtsi. Change-Id: I5d8a18108689ee899142002a5cd211648d72e46d --- .../soc/qcom/qcom,glink-slatecom-xprt.txt | 49 +++++++++++++++++++ qcom/slate.dtsi | 22 +++++++++ 2 files changed, 71 insertions(+) diff --git a/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt index b4ae09def9b2..769317af654b 100644 --- a/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt +++ b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt @@ -22,3 +22,52 @@ The following example reprsents a glink_slatecom node. compatible = "qcom,glink-slatecom-xprt"; label = "slate"; }; + += AUDIO_CC_IPC_NODE +Each subnode of the glink_slatecom_xprt is a device node exposed to user space +by the audio-cc-ipc driver for sending ipc packets between the ipc clients. +Maximum nodes supported is 2. +- Each node defined should contain following property + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,audio_cc_ipc" + +- qcom,glink-channels: + Usage: required + Value type: + +- reg: + Usage: required + Value type: + +- cdev_name: + Usage: required + Value type: + += CC_CODEC_NODE +Audio_cc_ipc nodes can have a cc_codec child node. This node will act as an +interface for proxy codec, to manage the communication to its counter part +through ipc. +- Each node defined should contain following property + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,cc-codec" + += EXAMPLE +The following example represents the audio-cc-ipc node having a codec child node + + audio_ipc1: qcom,audio_cc_ipc1 { + compatible = "qcom,audio_cc_ipc"; + qcom,glink-channels = "custom_cc_apps"; + qcom,intents = <0x2000 2>; + reg = ; + cdev_name = "nongpr_channel"; + + cc_codec: qcom,cc-codec { + compatible = "qcom, cc-codec"; + }; + }; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index a6f170802464..435f05a8083f 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -1,3 +1,5 @@ +#include "dt-bindings/sound/qcom,gpr.h" + &soc { qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ status = "ok"; @@ -127,5 +129,25 @@ qcom,intents = <0x2710 2 0x3E8 2>; }; + + audio_ipc: qcom,audio_cc_ipc { + compatible = "qcom,audio_cc_ipc"; + qcom,glink-channels = "gpr_cc_apps"; + qcom,intents = <0x2000 2>; + reg = ; + cdev_name = "gpr_channel"; + }; + + audio_ipc1: qcom,audio_cc_ipc1 { + compatible = "qcom,audio_cc_ipc"; + qcom,glink-channels = "custom_cc_apps"; + qcom,intents = <0x2000 2>; + reg = ; + cdev_name = "nongpr_channel"; + + cc_codec: qcom,cc-codec { + compatible = "qcom,cc-codec"; + }; + }; }; }; From 4a05ff7b96469f87bab096bc7026c92c6c79a6d0 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 25 May 2021 18:24:23 +0530 Subject: [PATCH 1492/1809] ARM: dts: msm: Update ADC support for PM6125 Correct interrupt name for PM6125 ADC_TM to match the name expected in the driver. Remove VCOIN channel from VADC as it is not used. Change-Id: I1b96fae160b82bf3378b0c72960ecb6fb76c4043 --- qcom/pm6125.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index bc79c4423abf..7df8eb71874b 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -76,12 +76,6 @@ qcom,pre-scaling = <1 3>; }; - vcoin { - reg = ; - label = "vcoin"; - qcom,pre-scaling = <1 3>; - }; - xo_therm { reg = ; label = "xo_therm"; @@ -95,7 +89,7 @@ compatible = "qcom,adc-tm5"; reg = <0x3500>; interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; From 2f75fe14949f59615086f7b6ddd5d0c8f82c9791 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 24 May 2021 10:52:46 +0530 Subject: [PATCH 1493/1809] ARM: dts: qcom: Add flash pinctrl gpio for blair Configure the flash strobe, torch, hwen, tx gpios for camera. CRs-Fixed: 2954621 Change-Id: I8c486e57bc6cdfb25f76d9ade0edb72d177956fb --- qcom/blair-pinctrl.dtsi | 116 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/qcom/blair-pinctrl.dtsi b/qcom/blair-pinctrl.dtsi index 9cb472d3e943..1302fa7d9dec 100644 --- a/qcom/blair-pinctrl.dtsi +++ b/qcom/blair-pinctrl.dtsi @@ -1094,6 +1094,122 @@ }; }; + cam_flash_strobe_active: cam_flash_strobe_active { + /* STROBE */ + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_strobe_suspend: cam_flash_strobe_suspend { + /* STROBE */ + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_torch_active: cam_flash_torch_active { + /* TORCH */ + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_torch_suspend: cam_flash_torch_suspend { + /* TORCH */ + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_hwen_active: cam_flash_hwen_active { + /* HWEN */ + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_hwen_suspend: cam_flash_hwen_suspend { + /* HWEN */ + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_tx_active: cam_flash_tx_active { + /* TX */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_tx_suspend: cam_flash_tx_suspend { + /* TX */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + pm8008_active: pm8008_active { mux { pins = "gpio58"; From 2850dd4e1e5e0c7de1ea7e145953548ee8ef4824 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 26 May 2021 13:08:07 +0530 Subject: [PATCH 1494/1809] ARM: dts: msm: Add smb1394 support for holi-pm6125 Add support for smb1394 for holi-pm6125 mtp and mtp-usbc platform, while at it remove smb1398 nodes for the same. Change-Id: Ie0bce0b289739d1a206eeb6585dac8fca160f63a --- qcom/holi-mtp-pm6125.dtsi | 24 ++++++++++++------------ qcom/holi-mtp-usbc-pm6125.dtsi | 24 ++++++++++++------------ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 3136db197142..9a75570cb649 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -237,13 +237,13 @@ <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, - <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, - <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, - <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, - <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, - <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -300,7 +300,7 @@ <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", @@ -341,20 +341,20 @@ &qupv3_se10_i2c { status = "ok"; - #include "smb1398.dtsi" + #include "smb1394.dtsi" }; -&smb1396 { +&smb1394 { interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1396"; + interrupt-names = "smb1394"; pinctrl-names = "default"; qcom,enable-toggle-stat; pinctrl-0 = <&smb_stat_default>; status = "ok"; }; -&smb1396_div2_cp_master { +&smb1394_div2_cp_primary { io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 7513687694f9..f06872848cf7 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -256,13 +256,13 @@ <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, - <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, - <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, - <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, - <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, - <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -319,7 +319,7 @@ <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", @@ -374,20 +374,20 @@ &qupv3_se10_i2c { status = "ok"; - #include "smb1398.dtsi" + #include "smb1394.dtsi" }; -&smb1396 { +&smb1394 { interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1396"; + interrupt-names = "smb1394"; pinctrl-names = "default"; qcom,enable-toggle-stat; pinctrl-0 = <&smb_stat_default>; status = "ok"; }; -&smb1396_div2_cp_master { +&smb1394_div2_cp_primary { io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, From 23799839ef79dd8b49dd4e869588b1c9cc95996a Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Tue, 20 Apr 2021 23:43:30 +0530 Subject: [PATCH 1495/1809] ARM: dts: msm: Add rpm-smd node for qcs405 Add rpm-smd devic node for APSS communication with RPM. Change-Id: I62497058ed67b97d94dc868250f305097260f64d --- qcom/qcs405.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index e09e9755db17..59cd68007e02 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -238,6 +238,13 @@ status = "okay"; }; + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + qcom,msm-imem@8600000 { compatible = "qcom,msm-imem"; reg = <0x08600000 0x1000>; /* Address and size of IMEM */ From 84d1f84b90bbb90f8fcd6d66597d49adef2c6e8c Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 23 Apr 2021 20:20:39 +0530 Subject: [PATCH 1496/1809] ARM: dts: msm: add RPM managed regulator devices for QCS405 Also add RPM managed regulator devices for QCS405 so that the client requests made for these regulators are aggregated by the RPM processor along with the requests from other processors. Change-Id: Ie9d22bd3b2b080b691f21cecedd337aacf3d3702 --- qcom/pms405-rpm-regulator.dtsi | 305 +++++++++++++++++++++++++++++++++ qcom/qcs405-regulator.dtsi | 251 +++++++++++++++++++++++++++ qcom/qcs405.dtsi | 2 + qcom/sa2150p-ccard.dtsi | 30 ++++ 4 files changed, 588 insertions(+) create mode 100644 qcom/pms405-rpm-regulator.dtsi create mode 100644 qcom/qcs405-regulator.dtsi diff --git a/qcom/pms405-rpm-regulator.dtsi b/qcom/pms405-rpm-regulator.dtsi new file mode 100644 index 000000000000..690da0c443d5 --- /dev/null +++ b/qcom/pms405-rpm-regulator.dtsi @@ -0,0 +1,305 @@ +&rpm_bus { + /* VDD_MX/CX supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/qcs405-regulator.dtsi b/qcom/qcs405-regulator.dtsi new file mode 100644 index 000000000000..a23614f903ef --- /dev/null +++ b/qcom/qcs405-regulator.dtsi @@ -0,0 +1,251 @@ +#include + +&rpm_bus { + /* PMS405 S1 - VDD_MX/CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + pms405_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pms405_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pms405_s1_floor_level>; + regulator-levels = ; + #cooling-cells = <2>; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pms405_s1_level>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PMS405 S2 - VDD_LPI_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + pms405_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pms405_s4: regulator-s4 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1920000>; + qcom,init-voltage = <1728000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pms405_l1: regulator-l1 { + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1240000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pms405_l2: regulator-l2 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1280000>; + qcom,init-voltage = <1048000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pms405_l3: regulator-l3 { + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1160000>; + qcom,init-voltage = <976000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pms405_l4: regulator-l4 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1144000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pms405_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pms405_l5_ao: regulator-l5-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l5_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pms405_l6: regulator-l6 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pms405_l7: regulator-l7 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <1616000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pms405_l8: regulator-l8 { + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1136000>; + status = "okay"; + }; + }; + + /* PMS405 L9 - VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + pms405_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_l9_floor_level: regulator-l9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pms405_l10: regulator-l10 { + regulator-min-microvolt = <2936000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <2936000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pms405_l11: regulator-l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pms405_l12: regulator-l12 { + regulator-min-microvolt = <2968000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2968000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pms405_l13: regulator-l13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; +}; diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index 59cd68007e02..d0902e5ef031 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -468,3 +468,5 @@ #include "qcs405-pinctrl.dtsi" #include "qcs405-cpu.dtsi" +#include "pms405-rpm-regulator.dtsi" +#include "qcs405-regulator.dtsi" diff --git a/qcom/sa2150p-ccard.dtsi b/qcom/sa2150p-ccard.dtsi index d6cbcc922f26..078a12e29fa6 100644 --- a/qcom/sa2150p-ccard.dtsi +++ b/qcom/sa2150p-ccard.dtsi @@ -1 +1,31 @@ #include "qcs405.dtsi" + +&rpm_bus { + rpm-regulator-ldoa1 { + status = "disabled"; + pms405_l1: regulator-l1 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + status = "disabled"; + pms405_l2: regulator-l2 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + status = "disabled"; + pms405_l7: regulator-l7 { + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + status = "disabled"; + pms405_l10: regulator-l10 { + status = "disabled"; + }; + }; +}; From f0a396fdb70bcabe3fff2e30900f6d35d3e2b4c5 Mon Sep 17 00:00:00 2001 From: Om Parkash Date: Wed, 26 May 2021 19:21:25 +0530 Subject: [PATCH 1497/1809] ARM: dts: msm: Add pin controls for camera GPIOs Add pin controls for camera and camera sensor GPIOs. Change-Id: If5eeed86b16735a227159553a78bda867f775295 --- qcom/monaco-pinctrl.dtsi | 170 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index a5ad5c9e3b73..3df0cea442f1 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -778,6 +778,176 @@ }; }; + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio38", "gpio37"; + function = "cci_i2c"; + }; + + config { + pins = "gpio38", "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA*/ + pins = "gpio38", "gpio37"; + function = "cci_i2c"; + }; + + config { + pins = "gpio38", "gpio37"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio40", "gpio39"; + function = "cci_i2c"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA*/ + pins = "gpio40", "gpio39"; + function = "cci_i2c"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + /* SDC pin type */ sdc1_on: sdc1_on { clk { From 7b4626af0998de37d267334e1d6c8cab2e41b2c5 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 26 May 2021 19:36:54 +0530 Subject: [PATCH 1498/1809] dt-bindings: kgsl: Add compatible property in qcom,gpu-model We can define compatible property for qcom,gpu-model nodes. Change-Id: Idd680b536a95d6124c06541253b0cb6b082d790e --- bindings/gpu/adreno.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index e8005917058f..2294c967609e 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -272,6 +272,8 @@ Properties: Defines a GPU model name for specific GPU model ID. Properties: +- compatible: + May also include "qcom,adreno-gpu-*" for few targets. - qcom,gpu-model-id: Identifier for the specific GPU hardware configuration - must match the value read from the hardware. @@ -435,10 +437,17 @@ Example of A330 GPU in MSM8916: compatible="qcom,gpu-models"; qcom,gpu-model@0 { + compatible="qcom,adreno-gpu-a642l"; qcom,gpu-model-id = <0>; qcom,gpu-model = "Adreno642Lv1"; qcom,vk-device-id= <0x06030500>; }; + qcom,gpu-model@1 { + compatible="qcom,adreno-gpu-a645"; + qcom,gpu-model-id = <190>; + qcom,gpu-model = "Adreno645"; + qcom,vk-device-id= <0x06030500>; + }; } /* GPU Mempools */ From f7c1abfff81db961e35db82c6dc1a765b120be4d Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 26 May 2021 19:52:17 +0530 Subject: [PATCH 1499/1809] ARM: dts: qcom: Add thermal overlay devicetree support for holi-pm6125 Add thermal overlay devicetree configurations like pmic alarm sensor thermal zone mitigation and BCL thermal zone mitigation for holi-pm6125. Change-Id: I20fe0880938bde6a62a45a6f11b3b64ae8e847fb --- qcom/holi-cdp-pm6125.dtsi | 1 + qcom/holi-mtp-pm6125.dtsi | 1 + qcom/holi-mtp-usbc-pm6125.dtsi | 1 + qcom/holi-qrd-pm6125.dtsi | 232 ++++++++++++++++++++++++++ qcom/holi-regulators-pm6125.dtsi | 24 ++- qcom/holi-thermal-overlay-pm6125.dtsi | 134 +++++++++++++++ qcom/pm6125.dtsi | 29 ++++ 7 files changed, 416 insertions(+), 6 deletions(-) create mode 100644 qcom/holi-thermal-overlay-pm6125.dtsi diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index fe98db9c97e5..795bd32bf7f6 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-cdp-pm6125.dtsi" #include #include "camera/holi-camera-pm6125-overlay.dtsi" diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 3136db197142..78bc6615c31b 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" #include #include "camera/holi-camera-pm6125-overlay.dtsi" diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 7513687694f9..dc9f8d83d832 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" #include #include "camera/holi-camera-pm6125-overlay.dtsi" diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 4a89749a9f4c..a8614cb12b42 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -1,6 +1,7 @@ #include #include #include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" #include &sdhc_1 { @@ -315,3 +316,234 @@ qcom,parallel-output-mode = <2>; /* VBAT */ status = "ok"; }; + +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + trips { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip2: battery-trip2 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + + modem-skin-cdev0 { + trip = <&modem_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&modem_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&cx_trip>; + cooling-device = <&modem_skin 3 3>; + }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <54000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; +}; diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index 69afd4ccc6f4..519b66a0b9d6 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -433,9 +433,13 @@ qcom,use-voltage-level; }; - /* Dummy node */ gfx_cdev: gfx-cdev { - status = "disabled"; + status = "okay"; + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&S8A_LEVEL_AO>; + regulator-levels = ; + #cooling-cells = <2>; }; }; @@ -747,9 +751,13 @@ qcom,use-voltage-level; }; - /* Dummy node */ mx_cdev: mx-cdev-lvl { - status = "disabled"; + status = "okay"; + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&S1E_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; }; }; @@ -801,9 +809,13 @@ qcom,use-voltage-level; }; - /* Dummy node */ cx_cdev: cx-cdev-lvl { - status = "disabled"; + status = "okay"; + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&S2E_FLOOR_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; }; }; diff --git a/qcom/holi-thermal-overlay-pm6125.dtsi b/qcom/holi-thermal-overlay-pm6125.dtsi new file mode 100644 index 000000000000..7dd3277d4899 --- /dev/null +++ b/qcom/holi-thermal-overlay-pm6125.dtsi @@ -0,0 +1,134 @@ +#include + +&mdss_mdp { + #cooling-cells = <2>; +}; + +&pm7250b_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b_tz { + cooling-maps { + battery_cdev0 { + trip = <&pm7250b_trip0>; + cooling-device = + <&pm7250b_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + battery_cdev1 { + trip = <&pm7250b_trip1>; + cooling-device = + <&pm7250b_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6125_tz { + cooling-maps { + trip0_cpu6 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu4 { + trip = <&pm6125_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm6125_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm6125_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm6125_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + trip0_modem_tj { + trip = <&pmr735a_trip0>; + cooling-device = + <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip0_modem_pa { + trip = <&pmr735a_trip0>; + cooling-device = + <&modem_pa THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + lbat0_cpu6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat0_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + lbat1_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat1_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + lbat2_cpu6 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat2_cpu7 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; +}; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index bc79c4423abf..43c123c9f0dc 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -151,3 +151,32 @@ }; }; }; + +&thermal_zones { + pm6125_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_tz>; + + trips { + pm6125_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6125_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pm6125_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From 372f47f75f4971872e8d81505bb298f33cc056eb Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 26 May 2021 20:58:43 +0530 Subject: [PATCH 1500/1809] ARM: dts: msm: Enable modem pa sensor config only for YUPIK QRD Enable modem pa sensors config rules only for yupik QRD and remove for other platforms as per recommendation. Change-Id: Icfb54a900b17fd9f6bfc1c7eb59dfa34bbdeba2b --- qcom/yupik-qrd.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++ qcom/yupik-thermal.dtsi | 88 ----------------------------------------- 2 files changed, 88 insertions(+), 88 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index c9db2290ae63..55329158acf7 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -265,6 +265,94 @@ }; }; + modem-sub6-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + sub6_pa1_trip0: sub6-pa1-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip1: sub6-pa1-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip2: sub6-pa1-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_fr1_cdev0 { + trip = <&sub6_pa1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + pa_fr1_cdev1 { + trip = <&sub6_pa1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + pa_fr1_cdev2 { + trip = <&sub6_pa1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; + + modem-lte-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + sub6_pa2_trip0: sub6-pa2-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip1: sub6-pa2-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip2: sub6-pa2-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_cdev0 { + trip = <&sub6_pa2_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + pa_cdev1 { + trip = <&sub6_pa2_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + pa_cdev2 { + trip = <&sub6_pa2_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + quiet-therm-step { polling-delay-passive = <2000>; polling-delay = <0>; diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 93a742f62c48..a9d549cfe7b1 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -263,94 +263,6 @@ }; }; - modem-sub6-pa1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_PA)>; - trips { - sub6_pa1_trip0: sub6-pa1-trip0 { - temperature = <43000>; - hysteresis = <4000>; - type = "passive"; - }; - - sub6_pa1_trip1: sub6-pa1-trip1 { - temperature = <45000>; - hysteresis = <4000>; - type = "passive"; - }; - - sub6_pa1_trip2: sub6-pa1-trip2 { - temperature = <55000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - pa_fr1_cdev0 { - trip = <&sub6_pa1_trip0>; - cooling-device = <&modem_pa_fr1 1 1>; - }; - - pa_fr1_cdev1 { - trip = <&sub6_pa1_trip1>; - cooling-device = <&modem_pa_fr1 2 2>; - }; - - pa_fr1_cdev2 { - trip = <&sub6_pa1_trip2>; - cooling-device = <&modem_pa_fr1 3 3>; - }; - }; - }; - - modem-lte-pa2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_PA_1)>; - trips { - sub6_pa2_trip0: sub6-pa2-trip0 { - temperature = <42000>; - hysteresis = <4000>; - type = "passive"; - }; - - sub6_pa2_trip1: sub6-pa2-trip1 { - temperature = <44000>; - hysteresis = <4000>; - type = "passive"; - }; - - sub6_pa2_trip2: sub6-pa2-trip2 { - temperature = <55000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - pa_cdev0 { - trip = <&sub6_pa2_trip0>; - cooling-device = <&modem_pa 1 1>; - }; - - pa_cdev1 { - trip = <&sub6_pa2_trip1>; - cooling-device = <&modem_pa 2 2>; - }; - - pa_cdev2 { - trip = <&sub6_pa2_trip2>; - cooling-device = <&modem_pa 3 3>; - }; - }; - }; - cpu-0-0-step { polling-delay-passive = <0>; polling-delay = <0>; From 50af2132d648e56711e77446f12519e4ae21f042 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Mon, 24 May 2021 11:06:10 +0800 Subject: [PATCH 1501/1809] ARM: dts: msm: Set allowable min volt of L9B to 1.2V for Yupik The L9B Regulator is used by UFS's VCCQ. To follow UFS JEDEC, UFS driver has to vote for 1.14v-1.26v. But the actual measured value of VCCQ would be less than 1.14v due to HW IR drop. So we limit L9B's min volt to 1.2V from regulator layer to avoid this UFS VCCQ Spec violation issue. Change-Id: I2aec6e2cbcfd341265fd33fbd50e3e740d39498b --- qcom/yupik-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index 90a20f083879..ea18346f0255 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -217,7 +217,7 @@ pm7325_l9: regulator-pm7325-l9 { regulator-name = "pm7325_l9"; qcom,set = ; - regulator-min-microvolt = <1080000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; From bf88b90686fbac8b9f309a24186b779bc2b52887 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 24 May 2021 18:00:37 +0530 Subject: [PATCH 1502/1809] ARM: dts: msm: use dummy regulator for 3V eLDO supply of touch on Holi The 3V eLDO controlled by gpio#53 is always ON, to avoid any conflict with the ALS sensor that is also using the same GPIO. Make use of a dummy regulator for the touch 3V supply. Change-Id: Ie40ab4c27a9f10222ce4fbc77f51e65acefeff8b --- qcom/holi-cdp-pm6125.dtsi | 36 ++++++++++------------------------ qcom/holi-mtp-pm6125.dtsi | 36 ++++++++++------------------------ qcom/holi-mtp-usbc-pm6125.dtsi | 36 ++++++++++------------------------ 3 files changed, 30 insertions(+), 78 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 4e49a2f06448..8a5a91161551 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -221,33 +221,17 @@ qcom,cl-feedback-on; }; -&tlmm { - touch_avdd_default: touch_avdd_default { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -}; - &soc { - touch_avdd: touch_avdd { - compatible = "regulator-fixed"; - regulator-name = "touch_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 53 0>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&touch_avdd_default>; + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; }; }; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 9238fc933bd2..9da75ca360ff 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -146,33 +146,17 @@ }; }; -&tlmm { - touch_avdd_default: touch_avdd_default { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -}; - &soc { - touch_avdd: touch_avdd { - compatible = "regulator-fixed"; - regulator-name = "touch_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 53 0>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&touch_avdd_default>; + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; }; }; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 7513687694f9..3848a900313c 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -165,33 +165,17 @@ }; }; -&tlmm { - touch_avdd_default: touch_avdd_default { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -}; - &soc { - touch_avdd: touch_avdd { - compatible = "regulator-fixed"; - regulator-name = "touch_avdd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 53 0>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&touch_avdd_default>; + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; }; }; From c8e6b4fd3562c0a6ed588f096eb3cc1b0906e748 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 19 May 2021 21:53:27 +0530 Subject: [PATCH 1503/1809] ARM: dts: msm: include display nodes for Blair target This change includes display DT nodes to enable display support on Blair target. Change-Id: Idff6e010b93c87a127abb1bf8db1e3d5a3b49e09 --- qcom/blair-cdp.dtsi | 5 +++++ qcom/blair-mtp.dtsi | 1 + qcom/blair.dtsi | 7 +------ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 0cec1c66625e..6a838a4152e8 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,7 +1,12 @@ #include "holi-cdp-pm6125.dtsi" +#include "display/blair-sde-display-cdp.dtsi" / { }; &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; }; + +&pm6125_pwm { + status = "ok"; +}; diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index e76628a3375e..9f9f94eb4e00 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -1,4 +1,5 @@ #include "holi-mtp-pm6125.dtsi" +#include "display/blair-sde-display-mtp.dtsi" / { }; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 60b42bf4bb09..6d3b9158511b 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3354,7 +3354,7 @@ #include "camera/holi-camera.dtsi" #include "holi-thermal.dtsi" #include "holi-qupv3.dtsi" -#include "display/holi-sde.dtsi" +#include "display/blair-sde.dtsi" #include "holi-audio.dtsi" #include "blair-usb.dtsi" #include "ipcc-test-holi.dtsi" @@ -3376,11 +3376,6 @@ regulator-max-microvolt = <3544000>; }; -/* Dummy LDO handle*/ -&mdss_dsi_phy0 { - vdda-0p9-supply = <&L2A>; -}; - &gcc_camss_top_gdsc { status = "ok"; }; From 4e26e8311aa38bbbbd80fdafe147cffa5a4d7f4b Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 19 May 2021 22:22:15 +0530 Subject: [PATCH 1504/1809] ARM: dts: msm: add touch support of lcd panel for Blair target This change adds touch support of nt36672e lcd panel for CDP platform of the Blair target. Change-Id: I15d5f8e95c4fb113dc13a47e54738bb54c5a437d --- qcom/blair-cdp.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 6a838a4152e8..266eafca1927 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -10,3 +10,32 @@ &pm6125_pwm { status = "ok"; }; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + novatek,reset-gpio = <&tlmm 21 0x00>; + novatek,irq-gpio = <&tlmm 22 0x2008>; + + panel = <&dsi_nt36672e_fhd_plus_60_video + &dsi_nt36672e_fhd_plus_120_video + &dsi_nt36672e_fhd_plus_144_video>; + }; +}; From 625fd669968b8f667b8b6824e0d3d56c535e89a0 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Sun, 23 May 2021 23:35:18 +0530 Subject: [PATCH 1505/1809] ARM: dts: msm: Fix ldoa3 regulator for monaco Enable ldoa3 regulator on monaco. Add compatible string for regulator resources of ldoa3. Change-Id: I13de85d117c2d8f49cec4a5823215d588ca6f7d1 --- qcom/monaco-regulators.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi index 026c4df19edd..d44e369c5705 100644 --- a/qcom/monaco-regulators.dtsi +++ b/qcom/monaco-regulators.dtsi @@ -148,22 +148,23 @@ }; rpm-regulator-ldoa3 { + status = "okay"; qcom,resource-name = "rwmx"; qcom,resource-id = <0>; proxy-supply = <&VDD_MXA_LEVEL>; + VDD_MX_LEVEL: VDD_MXA_LEVEL: VDD_EBI_LEVEL: L3A_LEVEL: pm5100_l3_level: regulator-pm5100-l3-level { + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l3_level"; qcom,set = <3>; regulator-min-microvolt = ; regulator-max-microvolt = ; - qcom,init-voltage-level = - ; qcom,proxy-consumer-enable; qcom,proxy-consumer-voltage = ; + qcom,set = <1>; regulator-min-microvolt = ; regulator-max-microvolt = ; - qcom,init-voltage-level = - ; qcom,use-voltage-level; }; From f388b08da35d18e60cff233bf378bc093d154c3e Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Wed, 26 May 2021 13:56:35 +0530 Subject: [PATCH 1506/1809] ARM: dts: msm: Fix regulator naming for pm8010 On monaco RPM uses "ldom" as the reasource name for PM8010. Update the same in PM8010's regulator configuration. Change-Id: Ic0f70d5bf16017d99cbee62d0e05fd15b131cf17 --- qcom/monaco-regulators.dtsi | 14 +++++++------- qcom/pm8010-rpm-regulator.dtsi | 28 ++++++++++++++-------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi index d44e369c5705..4615fd1c0b16 100644 --- a/qcom/monaco-regulators.dtsi +++ b/qcom/monaco-regulators.dtsi @@ -454,7 +454,7 @@ }; }; - rpm-regulator-ldoc1 { + rpm-regulator-ldom1 { status = "okay"; L1C: pm8010_l1: regulator-l1 { regulator-min-microvolt = <1200000>; @@ -464,7 +464,7 @@ }; }; - rpm-regulator-ldoc2 { + rpm-regulator-ldom2 { status = "okay"; L2C: pm8010_l2: regulator-l2 { regulator-min-microvolt = <1200000>; @@ -474,7 +474,7 @@ }; }; - rpm-regulator-ldoc3 { + rpm-regulator-ldom3 { status = "okay"; L3C: pm8010_l3: regulator-l3 { regulator-min-microvolt = <1800000>; @@ -484,7 +484,7 @@ }; }; - rpm-regulator-ldoc4 { + rpm-regulator-ldom4 { status = "okay"; L4C: pm8010_l4: regulator-l4 { regulator-min-microvolt = <1800000>; @@ -494,7 +494,7 @@ }; }; - rpm-regulator-ldoc5 { + rpm-regulator-ldom5 { status = "okay"; L5C: pm8010_l5: regulator-l5 { regulator-min-microvolt = <2800000>; @@ -504,7 +504,7 @@ }; }; - rpm-regulator-ldoc6 { + rpm-regulator-ldom6 { status = "okay"; L6C: pm8010_l6: regulator-l6 { regulator-min-microvolt = <2800000>; @@ -514,7 +514,7 @@ }; }; - rpm-regulator-ldoc7 { + rpm-regulator-ldom7 { status = "okay"; L7C: pm8010_l7: regulator-l7 { regulator-min-microvolt = <3000000>; diff --git a/qcom/pm8010-rpm-regulator.dtsi b/qcom/pm8010-rpm-regulator.dtsi index 24b8f5b90e33..996a138bc760 100644 --- a/qcom/pm8010-rpm-regulator.dtsi +++ b/qcom/pm8010-rpm-regulator.dtsi @@ -1,7 +1,7 @@ &rpm_bus { - rpm-regulator-ldoc1 { + rpm-regulator-ldom1 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <1>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -16,9 +16,9 @@ }; }; - rpm-regulator-ldoc2 { + rpm-regulator-ldom2 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <2>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -33,9 +33,9 @@ }; }; - rpm-regulator-ldoc3 { + rpm-regulator-ldom3 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <3>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -50,9 +50,9 @@ }; }; - rpm-regulator-ldoc4 { + rpm-regulator-ldom4 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <4>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -67,9 +67,9 @@ }; }; - rpm-regulator-ldoc5 { + rpm-regulator-ldom5 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <5>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -84,9 +84,9 @@ }; }; - rpm-regulator-ldoc6 { + rpm-regulator-ldom6 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <6>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; @@ -101,9 +101,9 @@ }; }; - rpm-regulator-ldoc7 { + rpm-regulator-ldom7 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoc"; + qcom,resource-name = "ldom"; qcom,resource-id = <7>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; From 95a5d72cee099fa45c139f66013f7ce96463fc80 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Tue, 25 May 2021 12:24:06 +0530 Subject: [PATCH 1507/1809] ARM: dts: msm: Remove unused static supplies for holi-pm6125 Remove unused static supplies for holi MTP, CDP, MTP-USBC, platforms with PM6125 pmic. Change-Id: Ia5aa80d102c5b4649553810d12dc0ddea9c77443 --- qcom/holi-cdp-pm6125.dtsi | 22 ++++++++++++++++------ qcom/holi-mtp-pm6125.dtsi | 22 ++++++++++++++++------ qcom/holi-mtp-usbc-pm6125.dtsi | 22 ++++++++++++++++------ 3 files changed, 48 insertions(+), 18 deletions(-) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 4e49a2f06448..0d81b604e052 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -7,19 +7,29 @@ #include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wcd937x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wsa881x_i2c_e { diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 9238fc933bd2..47fd159bd53d 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -7,19 +7,29 @@ #include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wcd937x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wsa881x_i2c_e { diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 7513687694f9..3f45b33c1e22 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -7,19 +7,29 @@ #include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wcd937x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wsa881x_i2c_e { From 8982f65ddf55303663fe07fcd382238a66dcddec Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 27 May 2021 13:43:05 +0530 Subject: [PATCH 1508/1809] ARM: dts: qcom: enable gpu mitigation for TSENS and BCL for monaco Enable gpu thermal zone mitigation for TSENS and BCL thermal zones for monaco. Change-Id: Iadb08edc362390c512a63ea6bc666eadcdfc02f8 --- qcom/monaco-thermal-overlay.dtsi | 18 ++++++++++++++++++ qcom/monaco-thermal.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi index 13c385a73423..a778e5a46524 100644 --- a/qcom/monaco-thermal-overlay.dtsi +++ b/qcom/monaco-thermal-overlay.dtsi @@ -40,6 +40,12 @@ trip = <&bcl_lvl0>; cooling-device = <&cpu3_isolate 1 1>; }; + + gpu_cdev { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; }; }; @@ -57,6 +63,12 @@ cooling-device = <&cpu1_isolate 1 1>; }; + gpu_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + modem_cdev { trip = <&bcl_lvl1>; cooling-device = <&modem_pa 2 2>; @@ -96,6 +108,12 @@ trip = <&socd_trip>; cooling-device = <&cpu3_isolate 1 1>; }; + + gpu_cdev { + trip = <&socd_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; }; }; }; diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi index a16a2b1bd4dd..708b9da9400b 100644 --- a/qcom/monaco-thermal.dtsi +++ b/qcom/monaco-thermal.dtsi @@ -120,6 +120,18 @@ }; cooling-maps { + gpu-cdev { + trip = <&gpu_step_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + gpu-cx-cdev0 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + gpu-cx-cdev1 { trip = <&gpu_cx_mon>; cooling-device = <&modem_tj 3 3>; @@ -193,6 +205,12 @@ }; cooling-maps { + mdm0-cx-cdev0 { + trip = <&mdm0_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + mdm0-cx-cdev1 { trip = <&mdm0_cx_mon>; cooling-device = <&modem_tj 3 3>; @@ -214,6 +232,12 @@ }; cooling-maps { + mdm1-cx-cdev0 { + trip = <&mdm1_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + mdm1-cx-cdev1 { trip = <&mdm1_cx_mon>; cooling-device = <&modem_tj 3 3>; From 84cc94906c79b1555a59bc66f227c26982592fec Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Thu, 27 May 2021 14:29:52 +0530 Subject: [PATCH 1509/1809] ARM: dts: msm: Add aop_send_message device node interface for SA8155 Add aop_send_message debugfs interface for clients to send data to the AOP. Change-Id: If6009095849650c0f189e652564363bc1062fdb0 --- qcom/sa8155.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index f47e907fc63e..ecf6b1586772 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -304,6 +304,12 @@ pcm-lane-config = <1>; }; }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; &usb2_phy0 { From 2ae21b046f0f879ee9437c570a8ddda312113f06 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Thu, 27 May 2021 14:33:10 +0530 Subject: [PATCH 1510/1809] ARM: dts: msm: Add aop_send_message device node interface for SA6155 Add aop_send_message debugfs interface for clients to send data to the AOP. Change-Id: Iabda57871d389e2e509d5ad526996baf95761a2d --- qcom/sa6155.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 018ff859c0ef..9a1a185407a3 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -29,6 +29,12 @@ read-only; ranges; }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; &qusb_phy0 { From 40e3c555b0e73dc01286ed2c0cb5a5a305c2ec22 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Wed, 19 May 2021 22:51:49 +0530 Subject: [PATCH 1511/1809] ARM: dts: msm: add display support for monaco IDP Add display nodes and pinctrl details. Also update platform details. Change-Id: Ic4cb86758231c893d3c1a1cead2d1118103e143a --- qcom/monaco-idp-v1-common.dtsi | 11 +++++++++++ qcom/monaco-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ qcom/monaco.dtsi | 17 +++++++++++++++++ qcom/pm5100.dtsi | 30 ++++++++++++++++++++++++++++++ 4 files changed, 86 insertions(+) diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi index 0643de7d8f46..cbe2cd281f6d 100644 --- a/qcom/monaco-idp-v1-common.dtsi +++ b/qcom/monaco-idp-v1-common.dtsi @@ -1 +1,12 @@ #include "monaco-thermal-overlay.dtsi" + +&dsi_rm69090_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,platform-reset-gpio = <&pm5100_gpios 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-en-gpio = <&pm5100_gpios 1 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69090_amoled_cmd>; +}; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 3df0cea442f1..1c0e53ae90e2 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -999,4 +999,32 @@ }; }; }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio73"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio73"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index a2f6ab99959d..a96abaf5f279 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -259,6 +259,21 @@ size = <0 0x5c00000>; }; + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; @@ -1490,6 +1505,8 @@ #include "monaco-thermal.dtsi" #include "monaco-vidc.dtsi" #include "monaco-gpu.dtsi" +#include "display/monaco-sde.dtsi" +#include "display/monaco-sde-display.dtsi" &qupv3_se6_2uart { status = "ok"; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 5bd792e332a7..940bb47d4863 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -326,3 +326,33 @@ }; }; }; + +&pm5100_gpios { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; From c2fd643c61e7b8904db54f142ab09896d6468d63 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Fri, 21 May 2021 05:57:22 +0530 Subject: [PATCH 1512/1809] ARM: dts: msm: Enable IPA node for monaco target Changes to enable the IPA node for monaco target. Change-Id: I7597e73404b4e404da866a8464f92d230ee08eef --- qcom/monaco.dtsi | 125 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index a2f6ab99959d..6deb7306a3ec 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1219,6 +1219,18 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { @@ -1473,6 +1485,119 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + ipa_hw: qcom,ipa@0x5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x34000>, + <0x5804000 0x28000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-endp-delay-wa; + qcom,use-ipa-pm; + qcom,arm-smmu; + qcom,ipa-fltrt-not-hashable; + qcom,skip-ieob-mask-wa; + qcom,msm-bus,name = "ipa"; + qcom,max_num_smmu_cb = <3>; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core_clk"; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <80000 2720000 80000 560000 80000 120000>; + + /* SVS */ + qcom,svs = + <80000 5414000 80000 920000 80000 180000>; + + /* NOMINAL */ + qcom,nominal = + <206000 7200000 206000 1560000 206000 380000>; + + /* TURBO */ + qcom,turbo = + <206000 8500000 206000 1880000 206000 520000>; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x0140 0x0>; + qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-geometry = <0 0xB0000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x141 0x0>; + /* ipa-uc ram */ + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x0142 0x0>; + qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>; + qcom,iommu-dma = "atomic"; + }; + }; }; #include "pm5100.dtsi" From a03043965894e2104eac26645ee21a03ee4fea35 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Thu, 27 May 2021 14:36:09 +0530 Subject: [PATCH 1513/1809] ARM: dts: msm: Add aop_send_message device node interface for sdmshrike Add aop_send_message debugfs interface for clients to send data to the AOP. Change-Id: I61c7e8c110be379dc5748c59fd67a807e3c999ab --- qcom/sdmshrike.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 39abaf3c7b80..f53441284481 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -2418,6 +2418,12 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; #include "sdmshrike-pinctrl.dtsi" From 74815b9c7f80072357e14e18269908ca14a53230 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 27 May 2021 16:47:42 +0530 Subject: [PATCH 1514/1809] ARM: dts: msm: Update UFS phy regulator peak current for blair This updates the UFS phy regulator peak current for blair . Change-Id: I9ea54491ea6b724250c1886ab894105554c34f83 --- qcom/blair-atp.dtsi | 1 + qcom/blair-cdp.dtsi | 1 + qcom/blair-mtp.dtsi | 1 + qcom/blair-qrd.dtsi | 5 +++++ 4 files changed, 8 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index fba76421c662..f4363bcfac46 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -325,6 +325,7 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-max-microamp = <85700>; }; #include "pm6350-rpm-regulator.dtsi" diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 0cec1c66625e..ec95234df985 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -4,4 +4,5 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-max-microamp = <85700>; }; diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index e76628a3375e..d668b0ee60bc 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -4,4 +4,5 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-max-microamp = <85700>; }; diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 336d7a250678..4ff0a8cc3551 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -1,2 +1,7 @@ / { }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-max-microamp = <85700>; +}; From 74d4e9bffb922c8454f2ca4d64c054e074ec7502 Mon Sep 17 00:00:00 2001 From: Akshaya Bhat Date: Tue, 4 May 2021 19:42:20 +0530 Subject: [PATCH 1515/1809] ARM: dts: msm: Add initial ION heaps for SA2150P Add varoius ION heaps for SM2150P SoC, these heaps are populated by using kernel msm-4.14 commit "fb94d5" as a reference. Change-Id: Ibc9c7ce41dd6bf88e84b2e80c18ffde640fb8172 --- qcom/qcs405-ion.dtsi | 33 +++++++++++++++++++++++++++++++++ qcom/qcs405.dtsi | 1 + 2 files changed, 34 insertions(+) create mode 100644 qcom/qcs405-ion.dtsi diff --git a/qcom/qcs405-ion.dtsi b/qcom/qcs405-ion.dtsi new file mode 100644 index 000000000000..2a9a16f1545e --- /dev/null +++ b/qcom/qcs405-ion.dtsi @@ -0,0 +1,33 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + status = "disabled"; + reg = ; + memory-region = <&secure_mem>; + qcom,ion-heap-type = "SECURE_DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index bc26ca331359..5a35aaedf45b 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -483,3 +483,4 @@ #include "qcs405-cpu.dtsi" #include "pms405-rpm-regulator.dtsi" #include "qcs405-regulator.dtsi" +#include "qcs405-ion.dtsi" From 3280ba1c7d92f40e30780927c438c433ccc6a6a0 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 27 May 2021 19:10:51 +0530 Subject: [PATCH 1516/1809] ARM: dts: msm: Update dpdm_supply for USB for Monaco Updated required dpdm_supply for Monaco to enable support for avoiding race between APSD and USB low power mode. Change-Id: I091cb97c14c69b890e792526b57249eb5e2e30ab --- qcom/monaco-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi index f98148c2fab6..e2cf280a8d1f 100644 --- a/qcom/monaco-usb.dtsi +++ b/qcom/monaco-usb.dtsi @@ -33,6 +33,7 @@ reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>; + dpdm-supply = <&usb2_phy0>; qcom,usb-charger; qcom,core-clk-rate = <60000000>; From d9bea11763ca78b06f8145cb74b90ab67615bb7b Mon Sep 17 00:00:00 2001 From: Ramachandran Venkataramani Date: Thu, 1 Apr 2021 23:10:40 -0700 Subject: [PATCH 1517/1809] ARM: dts: msm: Enable multiport USB for SA8195 LA GVM Enable USB2 for SA8195 LA GVM and modify some USB properties for SA8195 VM USB. Change-Id: I1da82fc9c3a1da5a274719e487224df7719d975e --- qcom/sa8195-vm-la.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 3dc4a02705a0..570a64a6aeb4 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -36,6 +36,26 @@ status = "ok"; }; +&usb2 { + status = "ok"; +}; + +&usb2_phy2 { + status = "ok"; +}; + +&usb_qmp_phy0 { + status = "ok"; +}; + +&usb2_phy3 { + status = "ok"; +}; + +&usb_qmp_phy1 { + status = "ok"; +}; + &qupv3_se13_4uart { status = "ok"; }; From da8aaabbbb87206bb5d9ab042c892a995e470baa Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Fri, 28 May 2021 09:59:51 +0530 Subject: [PATCH 1518/1809] ARM: dts: msm: Add support for Blair QRD platform Add support for blair qrd platform by Including holi-qrd-pm6125.dtsi in blair-qrd.dts, while at it fix overlay for same. Change-Id: Ieca50da7435d825f818ef48ba31d12712eab5b7b --- qcom/blair-qrd-overlay.dts | 2 +- qcom/blair-qrd.dtsi | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/qcom/blair-qrd-overlay.dts b/qcom/blair-qrd-overlay.dts index 02e5c787ddae..04955e482053 100644 --- a/qcom/blair-qrd-overlay.dts +++ b/qcom/blair-qrd-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "blair.dtsi" #include "blair-qrd.dtsi" / { diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 4ff0a8cc3551..0014141744c7 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -1,5 +1,4 @@ -/ { -}; +#include "holi-qrd-pm6125.dtsi" &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; From 7301e4bb4ca9f5902ff591d2bf730431f9dc2205 Mon Sep 17 00:00:00 2001 From: Santosh Dronamraju Date: Thu, 20 May 2021 15:45:43 +0530 Subject: [PATCH 1519/1809] ARM: dts: msm: updated qseecom mem node Update qseecom node to support cma heaps allocating from a carveout. Change-Id: I163fd409f86726043fbbe6f717ee29b06b0938b5 --- qcom/sdmshrike.dtsi | 7 ++----- qcom/sm6150.dtsi | 6 ++---- qcom/sm8150.dtsi | 6 ++---- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 39abaf3c7b80..eee2df7d2220 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -373,13 +373,10 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; - cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "cont_splash_region"; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 5c298a741bd8..6193d531ac3c 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -369,10 +369,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions@9f800000 { diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 10fb995559ec..fea29cf401e3 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -371,10 +371,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions { From a281748567a662aa17f8a1ab64f454636e0ad1af Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Thu, 27 May 2021 18:08:59 +0800 Subject: [PATCH 1520/1809] ARM: dts: msm: Add apss dl cti0 for shima Add app dl cti0 to device tree for DCC LLCC timeout on shima. Change-Id: I8f8bd5626a848c015631849b1790e18582109c22 --- qcom/shima-coresight.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 471a736d4b05..23f47fd675cd 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -3598,6 +3598,18 @@ clock-names = "apb_pclk"; }; + cti0_apss_dl: cti@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7862000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_dl_cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + snoc: snoc { compatible = "qcom,coresight-dummy"; coresight-name = "coresight-snoc"; From 6925fe659d28098e2914220cfc90c0cc941d2614 Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Fri, 28 May 2021 15:18:36 +0800 Subject: [PATCH 1521/1809] ARM: dts: msm: Add apss dl cti0 for yupik Add app dl cti0 to device tree for DCC LLCC timeout on yupik. Change-Id: I526cba88c14458eb32a345fe707edd6e3e3f5266 --- qcom/yupik-coresight.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 9d0b985226b8..d2bf1745c734 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -3324,5 +3324,17 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; }; + + cti0_apss_dl: cti@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7862000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_dl_cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; }; From 4b7c2540ec1d377a688c8fafbfb6445ee60b8c7e Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Fri, 28 May 2021 15:36:27 +0530 Subject: [PATCH 1522/1809] ARM: dts: msm: Include pm5100 and pm8010 regulators for monaco Include pm5100 and pm8010 regulators for monaco. Change-Id: I2d7e1ccdb0102a4380d27b90c693d02c1cdb4219 --- qcom/monaco.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index a96abaf5f279..eb33e39b4978 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1491,12 +1491,14 @@ }; #include "pm5100.dtsi" +#include "pm5100-rpm-regulator.dtsi" +#include "pm8010-rpm-regulator.dtsi" +#include "monaco-regulators.dtsi" #include "monaco-pmic.dtsi" #include "monaco-pinctrl.dtsi" #include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" #include "monaco-ion.dtsi" -#include "monaco-stub-regulator.dtsi" #include "monaco-gdsc.dtsi" #include "monaco-qupv3.dtsi" #include "monaco-pm.dtsi" From 5d83ceaf49d5df0461060652afd11dd2a9c662de Mon Sep 17 00:00:00 2001 From: xsang Date: Mon, 17 May 2021 15:42:20 +0800 Subject: [PATCH 1523/1809] ARM: dts: msm: Add audio definition for QRD Holi-pm6125 add audio node on qrd holi pm6125. Change-Id: I7607da407f1f438bda2a27b6f2042489f5c12f68 --- qcom/holi-qrd-pm6125.dtsi | 94 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index a8614cb12b42..f663af22cfd8 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -1,9 +1,27 @@ +#include "holi-audio-overlay.dtsi" #include #include #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include +&wcd938x_codec { + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; +}; + +&wcd937x_codec { + status = "ok"; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; +}; + &sdhc_1 { status = "ok"; @@ -69,6 +87,82 @@ status = "ok"; }; +&wsa881x_analog_reset_gpio { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; + +&wsa881x_i2c_e { + status = "ok"; + cdc-vdd-1p8-supply = <&L9A>; + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x0e>; + clock-names = "wsa_mclk"; + clocks = <&wsa881x_analog_clk 0>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; + qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; +}; + +&holi_snd { + qcom,model = "holi-qrd-snd-card"; + qcom,sku-model = "holi-qrdsku1-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS3", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrMono WSA_IN", "AUX", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd937x_codec>, <&wsa881x_i2c_e>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd937x_codec", "wsa-codec0"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + &soc { gpio_keys { compatible = "gpio-keys"; From 25bb2b93b215684e90ba9fac6d8f06d2a66a3327 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Fri, 28 May 2021 23:34:31 +0530 Subject: [PATCH 1524/1809] ARM: dts: msm: Enable DP and NON DP in rename block Enable DP and NON DP partition sets to support both configurations. Change-Id: I79bc932a27c60a1b8c2b5e00eac2b507923f12fd --- qcom/sa6155p-vm-la.dtsi | 5 ++++- qcom/sa8155-vm-la.dtsi | 5 ++++- qcom/sa8195-vm-la.dtsi | 7 +++++-- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/qcom/sa6155p-vm-la.dtsi b/qcom/sa6155p-vm-la.dtsi index 83cdcfef7532..029d89be10f5 100644 --- a/qcom/sa6155p-vm-la.dtsi +++ b/qcom/sa6155p-vm-la.dtsi @@ -10,10 +10,13 @@ compatible = "qcom,blkdev-rename"; actual-dev = "vda", "vdb", "vdc", "vdd", "vde", "vdf", - "vdg", "vdh"; + "vdg", "vdh", "vdj"; rename-dev = "system", "userdata", "vendor", "persist", "modem", "bluetooth", "misc", "vbmeta"; + rename-dev-ab = "super", "userdata", "vbmeta_system_a", + "persist", "modem_a", "bluetooth_a", + "misc", "vbmeta_a", "metadata"; }; }; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 9a6a06b89c6e..6a817cfe0a15 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -20,10 +20,13 @@ compatible = "qcom,blkdev-rename"; actual-dev = "vda", "vdb", "vdc", "vdd", "vde", "vdf", - "vdg", "vdh"; + "vdg", "vdh", "vdj"; rename-dev = "system", "userdata", "vendor", "persist", "modem", "bluetooth", "misc", "vbmeta"; + rename-dev-ab = "super", "userdata", "vbmeta_system_a", + "persist", "modem_a", "bluetooth_a", + "misc", "vbmeta_a", "metadata"; }; }; &usb0 { diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 3dc4a02705a0..bedbf190a11c 100644 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -17,14 +17,17 @@ }; / { - rename_blk: rename_blk { + rename_blk: rename_blk { compatible = "qcom,blkdev-rename"; actual-dev = "vda", "vdb", "vdc", "vdd", "vde", "vdf", - "vdg", "vdh"; + "vdg", "vdh", "vdj"; rename-dev = "system", "userdata", "vendor", "persist", "modem", "bluetooth", "misc", "vbmeta"; + rename-dev-ab = "super", "userdata", "vbmeta_system_a", + "persist", "modem_a", "bluetooth_a", + "misc", "vbmeta_a", "metadata"; }; }; From 2bbf796be1e3d8038ad869f6a9dcfb2682b159dc Mon Sep 17 00:00:00 2001 From: Om Parkash Date: Wed, 26 May 2021 21:56:32 +0530 Subject: [PATCH 1525/1809] ARM: dts: msm: Include camera DTSi files for monaco Include camera & camera sensor DTSi files for monaco. Change-Id: I6ae442b0843aa15f207c9b16a21c98bf170b890c --- qcom/monaco.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index dc8b90611424..18e484458924 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1635,6 +1635,8 @@ #include "monaco-gpu.dtsi" #include "display/monaco-sde.dtsi" #include "display/monaco-sde-display.dtsi" +#include "camera/monaco-camera.dtsi" +#include "camera/monaco-camera-sensor-idp.dtsi" &qupv3_se6_2uart { status = "ok"; From dac7b7c5583e00b50457ab15c4a6ba1c0cc7a8b8 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Sat, 29 May 2021 21:47:00 +0530 Subject: [PATCH 1526/1809] ARM: dts: msm: Update min-access length for monaco IoT Monaco using MAL32 by default. Change-Id: I697b5ce43a3b7044d452333f78429ceda74d1c8f --- qcom/monaco-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco-gpu.dtsi b/qcom/monaco-gpu.dtsi index 7f42a35dae74..36df3d35ef40 100644 --- a/qcom/monaco-gpu.dtsi +++ b/qcom/monaco-gpu.dtsi @@ -27,7 +27,7 @@ qcom,gpu-bimc-interface-clk-freq = <768000000>; qcom,ubwc-mode = <2>; - qcom,min-access-length = <64>; + qcom,min-access-length = <32>; /* base addr, size */ qcom,gpu-qdss-stm = <0xe1c0000 0x40000>; From 5beba6a9ccf12610dfad815eb33009b29ce7b7c0 Mon Sep 17 00:00:00 2001 From: Sayantan Majumder Date: Fri, 26 Mar 2021 11:17:49 +0530 Subject: [PATCH 1527/1809] ARM: dts: msm: Add video support for KODIAC-IOT target Adding separate compatibility string for video to support for KODIAC IOT(QCM6490.LA.1.0) target. Change-Id: Ic8bd9584286aa512912def98e7cab49e3d0719d0 --- bindings/media/video/msm-vidc.txt | 2 +- qcom/yupik-iot.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 354e1f376c54..603d035bc852 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -15,7 +15,7 @@ Required properties: - "qcom,sm6150-vidc" : Invokes driver specific data for SA6155. - "qcom,scuba-vidc" : Invokes driver specific data for SCUBA. - "qcom,monaco-vidc" : Invokes driver specific data for MONACO. - + - "qcom,qcm6490-vidc" : Invokes driver specific data for YUPIK-IOT. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL - reg : offset and length of the register set for the device. diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi index f069e51e512b..bbe7eca0a22d 100644 --- a/qcom/yupik-iot.dtsi +++ b/qcom/yupik-iot.dtsi @@ -6,6 +6,13 @@ qcom,msm-id = <497 0x10000>; }; +&soc { + msm_vidc: qcom,vidc { + compatible = "qcom,msm-vidc", "qcom,qcm6490-vidc"; + status = "ok"; + }; +}; + &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, From 59b27b0e47e10cf24a50f2b3b36fd25880fd5856 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Sun, 25 Apr 2021 09:28:36 +0530 Subject: [PATCH 1528/1809] ARM: dts: msm: Enable BT for Scuba Add bluetooth node and enable se3 UART. Change-Id: Ib9be0b0a0a3e7f984e66c7fe4e7f82cdc78469ea --- qcom/qrb2210-rb1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 619bb26bb176..694184ad0a69 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -337,6 +337,20 @@ #interrupt-cells = <2>; }; + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */ + qcom,bt-vdd-io-supply = <&L15A>; /* IO */ + qcom,bt-vdd-core-supply = <&L10A>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L22A>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L13A>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, @@ -1562,3 +1576,7 @@ &qupv3_se4_2uart { status = "ok"; }; + +&qupv3_se3_4uart { + status = "ok"; +}; From 8c659779b29a520a8f582e331a2840a3002c2652 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 23 Apr 2021 21:31:09 +0530 Subject: [PATCH 1529/1809] ARM: dts: msm: Add BCL configuration for yupik IDP with PM7250B Add BCL configuration to monitor battery current, level violation and state of charge depletion configuration for yupik IDP variant with PM7250B. Change-Id: I7c578a15fa56458ba3b0a82c412417db764d9b30 --- qcom/pm7250b.dtsi | 10 +- qcom/yupik-pm7250b-thermal-overlay.dtsi | 131 +++++++++++++++++------- 2 files changed, 98 insertions(+), 43 deletions(-) diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 33407576b4ac..32d662ff76df 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -424,7 +424,7 @@ }; &thermal_zones { - pm7250b_tz { + pm7250b_temp_alarm: pm7250b_tz { polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; @@ -440,13 +440,13 @@ pm7250b_trip1: trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; - trip2 { + pm7250b_trip2: trip2 { temperature = <145000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; @@ -535,7 +535,7 @@ trips { socd_trip:socd-trip { temperature = <90>; - hysteresis = <1>; + hysteresis = <0>; type = "passive"; }; }; diff --git a/qcom/yupik-pm7250b-thermal-overlay.dtsi b/qcom/yupik-pm7250b-thermal-overlay.dtsi index 057d99d8fbcd..b8096d2db3e9 100644 --- a/qcom/yupik-pm7250b-thermal-overlay.dtsi +++ b/qcom/yupik-pm7250b-thermal-overlay.dtsi @@ -33,6 +33,75 @@ }; }; + pm7250b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_cpu6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + vbat_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vbat_modem2 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + pm8350c-bcl-lvl0 { disable-thermal-zone; cooling-maps { @@ -46,9 +115,14 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { + vph_cpu6 { trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vph_cdsp0 { @@ -56,12 +130,12 @@ cooling-device = <&cdsp_sw 2 2>; }; - vbat_modem0 { + vph_modem0 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_pa 2 2>; }; - vbat_modem1 { + vph_modem1 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_tj 1 1>; }; @@ -71,19 +145,10 @@ pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&c_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&c_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vph_cdsp1 { @@ -91,7 +156,7 @@ cooling-device = <&cdsp_sw 4 4>; }; - vbat_modem0 { + vph_modem2 { trip = <&c_bcl_lvl1>; cooling-device = <&modem_tj 3 3>; }; @@ -101,12 +166,6 @@ pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -115,6 +174,17 @@ }; }; + pm7250b_tz { + cooling-maps { + battery_cdev { + trip = <&pm7250b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + pm7325_tz { cooling-maps { pm7325_gpu { @@ -123,21 +193,6 @@ THERMAL_MAX_LIMIT>; }; - pm7325_cpu1 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm7325_cpu2 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm7325_cpu3 { - trip = <&pm7325_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm7325_cpu4 { trip = <&pm7325_trip0>; cooling-device = <&cpu4_isolate 1 1>; From 56f3d47cd27a9ce615e025dc2959986808c6305f Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Thu, 6 May 2021 14:42:11 +0530 Subject: [PATCH 1530/1809] ARM: dts: msm: Enable modem subsystem Enable modem subsystem for icnss2. Change-Id: I80a6bffb706d9669dfa80646182a6838d0a4cb1e --- qcom/qrb2210-rb1-coresight.dtsi | 1497 +++++++++++++++++++++++++++++++ qcom/qrb2210-rb1.dtsi | 59 +- 2 files changed, 1551 insertions(+), 5 deletions(-) create mode 100644 qcom/qrb2210-rb1-coresight.dtsi diff --git a/qcom/qrb2210-rb1-coresight.dtsi b/qcom/qrb2210-rb1-coresight.dtsi new file mode 100644 index 000000000000..bbcb275babfd --- /dev/null +++ b/qcom/qrb2210-rb1-coresight.dtsi @@ -0,0 +1,1497 @@ +&soc { + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + apss_tgu: tgu@9900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x09900000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <8>; + tgu-timer-counters = <8>; + interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>; + coresight-name = "coresight-tgu-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + csr: csr@8001000 { + compatible = "qcom,coresight-csr"; + reg = <0x8001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@8a03000 { + compatible = "qcom,coresight-csr"; + reg = <0x8a03000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + + qcom,timestamp-support; + qcom,aodbg-csr-support; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + stm: stm@8002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + + reg = <0x8002000 0x1000>, + <0xe280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + tpdm_center: tpdm@8b58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8b58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dl_ct_out_tpda0: endpoint { + remote-endpoint = + <&tpda0_in_tpdm_dl_ct>; + }; + }; + }; + + tpdm_gpu: tpdm@8940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_gpu_out_funnel_gpu: endpoint { + remote-endpoint = + <&funnel_gpu_in_tpdm_gpu>; + }; + }; + }; + + modem_rfxe: modem_rfxe { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-modem-rfxe"; + qcom,dummy-source; + + port { + modem_rxfe_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_rxfe>; + }; + }; + }; + + audio_etm0: audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_audio_etm0>; + }; + }; + }; + + tpdm_lpass_lpi: tpdm@8a26000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + port { + tpdm_lpass_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpdm_lpass>; + }; + }; + }; + + tpdm_vsense: tpdm@8840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_vsense_out_tpda7: endpoint { + remote-endpoint = + <&tpda7_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@8870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dcc_out_tpda8: endpoint { + remote-endpoint = + <&tpda8_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@884c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x884c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_prng_out_tpda10: endpoint { + remote-endpoint = + <&tpda10_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@89d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x89d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_qm_out_tpda12: endpoint { + remote-endpoint = + <&tpda12_in_tpdm_qm>; + }; + }; + }; + + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_west_out_tpda13: endpoint { + remote-endpoint = + <&tpda13_in_tpdm_west>; + }; + }; + }; + + tpdm_pimem: tpdm@8850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_pimem_out_tpda15: endpoint { + remote-endpoint = + <&tpda15_in_tpdm_pimem>; + }; + }; + }; + + tpdm_mapss: tpdm@8a01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_mapss_out_tpda_mapss: endpoint { + remote-endpoint = + <&tpda_mapss_in_tpdm_mapss>; + }; + }; + }; + + tpdm_wcss: tpdm@899c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_silver_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpdm_wcss_silver>; + }; + }; + }; + + modem_etm0: modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + etm0: etm@9040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9040000 0x1000>; + cpu = <&CPU0>; + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm0_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm0>; + }; + }; + }; + + etm1: etm@9140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9140000 0x1000>; + cpu = <&CPU1>; + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm1_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm1>; + }; + }; + }; + + etm2: etm@9240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9240000 0x1000>; + cpu = <&CPU2>; + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm2_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm2>; + }; + }; + }; + + etm3: etm@9340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9340000 0x1000>; + cpu = <&CPU3>; + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm3_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm3>; + }; + }; + }; + + tpdm_actpm: tpd@9830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_actpm_out_tpda_actpm: endpoint { + remote-endpoint = + <&tpda_actpm_in_tpdm_actpm>; + }; + }; + }; + + tpdm_llm_silver: tpdm@98a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x98a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + tpdm_apss: tpdm@9860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + funnel_apss0: funnel@9800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x9800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss0>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss0_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss0>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss0_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss0>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss0_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss0>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss0_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss0>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss0_in_tpda_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpda_actpm_out_funnel_apss0>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss0_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss0>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss0_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss0>; + }; + }; + + }; + }; + + tpda_actpm: tpda@9832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-actpm"; + + qcom,tpda-atid = <77>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_actpm_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_actpm>; + }; + }; + + port@1 { + reg = <0>; + tpda_actpm_in_tpdm_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_actpm_out_tpda_actpm>; + }; + }; + }; + }; + + tpda_apss: tpda@9862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + + tpda_llm_silver: tpda@98c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x98c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpda_mapss: tpda@8a04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8a04000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mapss"; + + qcom,tpda-atid = <76>; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mapss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mapss>; + }; + }; + + port@1 { + reg = <0>; + tpda_mapss_in_tpdm_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mapss_out_tpda_mapss>; + }; + }; + }; + }; + + funnel_gpu: funnel@8944000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8944000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu"; + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_gpu_out_tpda1: endpoint { + remote-endpoint = + <&tpda1_in_funnel_gpu>; + }; + }; + + port@1 { + reg = <0>; + funnel_gpu_in_tpdm_gpu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu>; + }; + }; + + }; + }; + + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <0 32>, + <1 32>, + <5 32>, + <12 32>, + <13 32>, + <15 32>; + qcom,cmb-elem-size = <7 32>, + <8 32>, + <10 32>, + <15 64>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda0_in_tpdm_dl_ct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_ct_out_tpda0>; + }; + }; + + port@2 { + reg = <1>; + tpda1_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda1>; + }; + }; + + port@3 { + reg = <7>; + tpda7_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda7>; + }; + }; + + port@4 { + reg = <8>; + tpda8_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda8>; + }; + }; + + port@5 { + reg = <10>; + tpda10_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda10>; + }; + }; + + port@6 { + reg = <12>; + tpda12_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda12>; + }; + }; + + port@7 { + reg = <13>; + tpda13_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda13>; + }; + }; + + port@8 { + reg = <15>; + tpda15_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda15>; + }; + }; + + }; + }; + + funnel_qatb: funnel@8005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <5>; + funnel_qatb_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <5>; + funnel_qatb_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_qatb>; + }; + }; + }; + }; + + funnel_in0: funnel@8041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@8042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + + port@1 { + reg = <1>; + funnel_in1_in_tpda_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mapss_out_funnel_in1>; + }; + }; + + port@2 { + reg = <2>; + funnel_in1_in_modem_rxfe: endpoint { + slave-mode; + remote-endpoint = + <&modem_rxfe_out_funnel_in1>; + }; + }; + + port@3 { + reg = <3>; + funnel_in1_in_tpdm_wcss_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_silver_out_funnel_in1>; + }; + }; + + port@4 { + reg = <4>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + + port@5 { + reg = <6>; + funnel_in1_in_funnel_apss0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss0_out_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@8045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + }; + }; + + tmc_etf: tmc@8047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tmc_etf_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + + }; + }; + + replicator_qdss: replicator@8046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x8046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_qdss>; + }; + }; + + port@1 { + reg = <0>; + replicator_qdss_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator_qdss>; + }; + }; + + }; + }; + + tmc_etr: tmc@8048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8048000 0x1000>, + <0x8064000 0x15000>; + reg-names = "tmc-base","bam-base"; + + coresight-name = "coresight-tmc-etr"; + + iommus = <&apps_smmu 0x0180 0>, + <&apps_smmu 0x0160 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + arm,scatter-gather; + + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tmc_etr_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + + }; + }; + + cti_cortex_m3: cti@8b30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b30000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti0: cti@98e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti1: cti@98f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti0: cti@89a4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti0"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti1: cti@89a5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti1"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti2: cti@89a6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89a6000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss-cti2"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_lpi: cti@8a21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a21000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass-lpi"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_q6: cti@8a2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a2b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass-q6"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@8833000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8833000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_isdb_gpu: cti@8941000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8941000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-isdb-gpu"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mapss: cti@8a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti0: cti@8b59000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b59000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti1: cti@8b5a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti2: cti@8b5b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti3: cti@8b5c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8b5c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@8010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1: cti@8011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2: cti@8012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@8013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti4: cti@8014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti5: cti@8015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti6: cti@8016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti7: cti@8017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti8: cti@8018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti9: cti@8019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti10: cti@801a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti11: cti@801b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti12: cti@801c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti13: cti@801d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti14: cti@801e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti15: cti@801f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 694184ad0a69..e7bcfc68dc5e 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -289,6 +289,14 @@ size = <0x0 0x1000000>; }; + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; @@ -500,7 +508,7 @@ reg = <0x0 0x280000>; reg-names = "rmtfs"; qcom,client-id = <0x00000001>; - qcom,guard-memory; + qcom,vm-nav-path; }; thermal_zones: thermal-zones { }; @@ -835,8 +843,11 @@ reg = <0x1400000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1061,6 +1072,14 @@ qcom,smem-state-names = "qcom,force-stop"; }; + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + pil_modem: qcom,mss@6080000 { compatible = "qcom,pil-tz-generic"; reg = <0x6080000 0x100>; @@ -1318,8 +1337,8 @@ vdd-1.8-xo-supply = <&L13A>; vdd-1.3-rfa-supply = <&L10A>; vdd-3.3-ch0-supply = <&L22A>; - qcom,vdd-cx-mx-config = <640000 640000>; - qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,vdd-cx-mx-config = <640000 640000 0 0 1>; + qcom,vdd-3.3-ch0-config = <3000000 3312000 0 0 0>; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; @@ -1344,7 +1363,7 @@ }; system_noc: interconnect@1880000 { - reg = <0x01880000 0x60200>; + reg = <0x01880000 0x5e080>; compatible = "qcom,scuba-system_noc"; #interconnect-cells = <1>; }; @@ -1361,6 +1380,35 @@ #interconnect-cells = <1>; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + qcom-secure-buffer { compatible = "qcom,secure-buffer"; }; @@ -1376,6 +1424,7 @@ #include "qrb2210-rb1-qupv3.dtsi" #include "qrb2210-rb1-gdsc.dtsi" #include "qrb2210-rb1-usb.dtsi" +#include "qrb2210-rb1-coresight.dtsi" &qupv3_se1_i2c { #address-cells = <1>; From 30b7ce9288625899e45c45dbc41043c69684c937 Mon Sep 17 00:00:00 2001 From: Akshaya Bhat Date: Mon, 24 May 2021 19:15:09 +0530 Subject: [PATCH 1531/1809] ARM: dts: msm: add msm poweroff node on qcs405 Added msm poweroff node for all reset functionalities on SA2150P target. Change-Id: I30873323734381c13f1caf5aeb5635f74f5cc9d4 --- qcom/qcs405.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index 5a35aaedf45b..1057ba6ce0f0 100644 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -224,6 +224,13 @@ }; }; + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; From 4089b68ce13c06a0c9c5c98efdbfd67eea4fe0f5 Mon Sep 17 00:00:00 2001 From: Devender Kaushik Date: Tue, 1 Jun 2021 21:19:30 +0530 Subject: [PATCH 1532/1809] ARM: dts: msm: add remote debugger support Add remote debugger device configuration. The Remote Debugger driver allows a debugger running on a host PC to communicate with a remote stub running on peripheral subsystems. Change-Id: Ib0f7ee199881601c2611661fb442ff0e68e9ef57 --- qcom/monaco.dtsi | 12 ++++++++++++ qcom/msm-rdbg-monaco.dtsi | 15 +++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 qcom/msm-rdbg-monaco.dtsi diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 18e484458924..e8d1b6027b1c 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1267,6 +1267,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; jtag_mm0: jtagmm@9040000 { @@ -1637,6 +1648,7 @@ #include "display/monaco-sde-display.dtsi" #include "camera/monaco-camera.dtsi" #include "camera/monaco-camera-sensor-idp.dtsi" +#include "msm-rdbg-monaco.dtsi" &qupv3_se6_2uart { status = "ok"; diff --git a/qcom/msm-rdbg-monaco.dtsi b/qcom/msm-rdbg-monaco.dtsi new file mode 100644 index 000000000000..758dda2c8700 --- /dev/null +++ b/qcom/msm-rdbg-monaco.dtsi @@ -0,0 +1,15 @@ +&soc { + /* smp2p information */ + qcom,smp2p_interrupt_rdbg_2_out { + compatible = "qcom,smp2p-interrupt-rdbg-2-out"; + qcom,smem-states = <&smp2p_rdbg2_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + + qcom,smp2p_interrupt_rdbg_2_in { + compatible = "qcom,smp2p-interrupt-rdbg-2-in"; + interrupts-extended = <&smp2p_rdbg2_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; + +}; From 90fbdd101eb431bc1a8376c64e6f4cd8d9f56b90 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 27 May 2021 19:48:03 -0700 Subject: [PATCH 1533/1809] ARM: dts: msm: add PM7250B and SMB1394 to sdxlemur-mtp-mbb-emmc boards sdxlemur-mtp-mbb-emmc boards use PM7250B and SMB1394 similar to sdxlemur-mtp-mbb boards. However, sdxlemur-mtp-mbb-emmc.dtsi has sdxlemur-pmic-overlay.dtsi which only adds PMK8350 and PMX65. Add pm7250b.dtsi and smb1394.dtsi to sdxlemur-mtp-mbb-emmc.dtsi so that sdxlemur-mtp-mbb-emmc boards can now use USB VBUS detection from PM7250B charger peripheral instead of VBUS_DET peripheral from PMX65. Change-Id: I72a63eb3f6b3f2b8c779e40593da9b7499a69478 --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 317 +++++++++++++++++++++++++++++++- 1 file changed, 316 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index d1848edd40a0..ea6d71dc8fb3 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -1,7 +1,13 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "pm7250b.dtsi" +#include +#include &soc { - + mbb_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; &sdhc_1 { @@ -34,3 +40,312 @@ status = "ok"; }; + +&spmi_debug_bus { + qcom,pm7250b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mbb_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mbb_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&i2c_3 { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&usb { + extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&vbus_detect { + status = "disabled"; +}; From 4daf391637f9258aaeca01afe456cafa7e9bc54f Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Wed, 19 May 2021 13:18:23 +0530 Subject: [PATCH 1534/1809] ARM: dts: msm: Add initial MTP-USBC platform device tree for Blair Add initial device tree to support blair on MTP audio over USB type-C platform. Change-Id: I5435edf16c1299d813b85144cadc198dc2dcc311 --- qcom/Makefile | 7 +++++-- qcom/blair-mtp-usbc-overlay.dts | 13 +++++++++++++ qcom/blair-mtp-usbc.dts | 10 ++++++++++ qcom/blair-mtp-usbc.dtsi | 2 ++ 4 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 qcom/blair-mtp-usbc-overlay.dts create mode 100644 qcom/blair-mtp-usbc.dts create mode 100644 qcom/blair-mtp-usbc.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 9bf6676f0f1e..97125f2b02c0 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -144,19 +144,22 @@ dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo \ blair-mtp-overlay.dtbo \ blair-cdp-overlay.dtbo \ blair-atp-overlay.dtbo \ - blair-qrd-overlay.dtbo + blair-qrd-overlay.dtbo \ + blair-mtp-usbc-overlay.dtbo blair-rumi-overlay.dtbo-base := blair.dtb blair-mtp-overlay.dtbo-base := blair.dtb blair-cdp-overlay.dtbo-base := blair.dtb blair-atp-overlay.dtbo-base := blair.dtb blair-qrd-overlay.dtbo-base := blair.dtb +blair-mtp-usbc-overlay.dtbo-base := blair.dtb else dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ blair-mtp.dtb \ blair-cdp.dtb \ blair-atp.dtb \ - blair-qrd.dtb + blair-qrd.dtb \ + blair-mtp-usbc.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/blair-mtp-usbc-overlay.dts b/qcom/blair-mtp-usbc-overlay.dts new file mode 100644 index 000000000000..f5161de1eb9b --- /dev/null +++ b/qcom/blair-mtp-usbc-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "blair-mtp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair MTP USBC audio"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <8 1>; +}; + + diff --git a/qcom/blair-mtp-usbc.dts b/qcom/blair-mtp-usbc.dts new file mode 100644 index 000000000000..c68cd7fefd93 --- /dev/null +++ b/qcom/blair-mtp-usbc.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-mtp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. BLAIR MTP USBC audio"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,board-id = <8 1>; +}; diff --git a/qcom/blair-mtp-usbc.dtsi b/qcom/blair-mtp-usbc.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-mtp-usbc.dtsi @@ -0,0 +1,2 @@ +/ { +}; From dc01e295ac2e8b36f5b56074ece2c29767f8e6c0 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Thu, 27 May 2021 16:54:38 +0530 Subject: [PATCH 1535/1809] ARM: dts: msm: Add DT support for nopmi on Blair target Add support for nopmi version of Blair platform. Change-Id: Ib2b5440d4108e42eb1f1dfccb6e6bbee8a358768 --- qcom/Makefile | 10 ++++++++-- qcom/blair-mtp-nopmi-overlay.dts | 12 ++++++++++++ qcom/blair-mtp-nopmi.dts | 11 +++++++++++ qcom/blair-mtp-nopmi.dtsi | 2 ++ qcom/blair-qrd-nopmi-overlay.dts | 12 ++++++++++++ qcom/blair-qrd-nopmi.dts | 11 +++++++++++ qcom/blair-qrd-nopmi.dtsi | 2 ++ 7 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 qcom/blair-mtp-nopmi-overlay.dts create mode 100644 qcom/blair-mtp-nopmi.dts create mode 100644 qcom/blair-mtp-nopmi.dtsi create mode 100644 qcom/blair-qrd-nopmi-overlay.dts create mode 100644 qcom/blair-qrd-nopmi.dts create mode 100644 qcom/blair-qrd-nopmi.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 97125f2b02c0..d2843e1e640f 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -145,7 +145,9 @@ dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo \ blair-cdp-overlay.dtbo \ blair-atp-overlay.dtbo \ blair-qrd-overlay.dtbo \ - blair-mtp-usbc-overlay.dtbo + blair-mtp-usbc-overlay.dtbo \ + blair-mtp-nopmi-overlay.dtbo \ + blair-qrd-nopmi-overlay.dtbo blair-rumi-overlay.dtbo-base := blair.dtb blair-mtp-overlay.dtbo-base := blair.dtb @@ -153,13 +155,17 @@ blair-cdp-overlay.dtbo-base := blair.dtb blair-atp-overlay.dtbo-base := blair.dtb blair-qrd-overlay.dtbo-base := blair.dtb blair-mtp-usbc-overlay.dtbo-base := blair.dtb +blair-mtp-nopmi-overlay.dtbo-base := blair.dtb +blair-qrd-nopmi-overlay.dtbo-base := blair.dtb else dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ blair-mtp.dtb \ blair-cdp.dtb \ blair-atp.dtb \ blair-qrd.dtb \ - blair-mtp-usbc.dtb + blair-mtp-usbc.dtb \ + blair-mtp-nopmi.dtb \ + blair-qrd-nopmi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/blair-mtp-nopmi-overlay.dts b/qcom/blair-mtp-nopmi-overlay.dts new file mode 100644 index 000000000000..45f5b62a29a8 --- /dev/null +++ b/qcom/blair-mtp-nopmi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "blair-mtp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair MTP NOPMI"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <8 0>; +}; + diff --git a/qcom/blair-mtp-nopmi.dts b/qcom/blair-mtp-nopmi.dts new file mode 100644 index 000000000000..aa80d9f34851 --- /dev/null +++ b/qcom/blair-mtp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-mtp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair MTP NOPMI"; + compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; + qcom,board-id = <8 0>; +}; + diff --git a/qcom/blair-mtp-nopmi.dtsi b/qcom/blair-mtp-nopmi.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-mtp-nopmi.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/qcom/blair-qrd-nopmi-overlay.dts b/qcom/blair-qrd-nopmi-overlay.dts new file mode 100644 index 000000000000..744a11f3e773 --- /dev/null +++ b/qcom/blair-qrd-nopmi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "blair-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair QRD NOPMI"; + compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/blair-qrd-nopmi.dts b/qcom/blair-qrd-nopmi.dts new file mode 100644 index 000000000000..f09f4f93d5de --- /dev/null +++ b/qcom/blair-qrd-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "blair.dtsi" +#include "blair-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair QRD NOPMI"; + compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/blair-qrd-nopmi.dtsi b/qcom/blair-qrd-nopmi.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/blair-qrd-nopmi.dtsi @@ -0,0 +1,2 @@ +/ { +}; From 64961993dc1f811e6001403f241458663803c901 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 31 May 2021 12:09:58 +0530 Subject: [PATCH 1536/1809] ARM: dts: msm: Update board-id for PM7250B Add board-id support for IDP with PM7250B for Yupik platform. Change-Id: I166e6e2b3a3888ab358f7d49920b4d4967161e95 --- qcom/yupik-idp-pm7250b-overlay.dts | 3 +-- qcom/yupik-idp-pm7250b.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-idp-pm7250b-overlay.dts b/qcom/yupik-idp-pm7250b-overlay.dts index b2c533d7738a..7bae225d5cf2 100644 --- a/qcom/yupik-idp-pm7250b-overlay.dts +++ b/qcom/yupik-idp-pm7250b-overlay.dts @@ -7,6 +7,5 @@ model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; qcom,msm-id = <475 0x10000>, <515 0x10000>; - /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ - qcom,board-id = <34 0xFF>; + qcom,board-id = <34 0>; }; diff --git a/qcom/yupik-idp-pm7250b.dts b/qcom/yupik-idp-pm7250b.dts index 45ac21a01659..d487d08acc80 100644 --- a/qcom/yupik-idp-pm7250b.dts +++ b/qcom/yupik-idp-pm7250b.dts @@ -6,6 +6,5 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ - qcom,board-id = <34 0xFF>; + qcom,board-id = <34 0>; }; From 1024b62435611052d2c563dfded768ad9cbe4910 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 21 May 2021 13:19:26 +0800 Subject: [PATCH 1537/1809] ARM: dts: msm: include display nodes for pm6125 platform of Holi qrd target Included display platform dtsi nodes for qrd platform. Change-Id: I727692996a88a0a7d939892824ec3c06d7f8748f --- qcom/holi-qrd-pm6125.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index f663af22cfd8..92f333ba00fe 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-qrd-pm6125.dtsi" #include &wcd938x_codec { From 4a0a9bf7d06360cc71597d2c2ef31577d9d70c57 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 7 Jun 2021 13:17:27 +0530 Subject: [PATCH 1538/1809] ARM: dts: msm: add cpulist to compute mon governor in blair target Add cpulist to compute mon governor nodes to monitor specified cpulist instead of super set cpulist of complete memlat group. Change-Id: I27f905ecd01a1e7800322802a5ae75dce5f7f58c --- qcom/blair.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 6d3b9158511b..b2437923577e 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1535,6 +1535,7 @@ cpu0_computemon: qcom,cpu0-computemon { compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; qcom,core-dev-table = < 691200 MHZ_TO_MBPS( 300, 4) >, @@ -1578,6 +1579,7 @@ cpu6_computemon: qcom,cpu6-computemon { compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU6 &CPU7>; qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; qcom,core-dev-table = < 1248800 MHZ_TO_MBPS( 547, 4) >, From 26d4b36f632f9820a259132bdd52673105466bb8 Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Thu, 3 Jun 2021 14:13:08 +0530 Subject: [PATCH 1539/1809] ARM: dts: msm: Add I2C NFC device node for holi pro QRD variant Device node changes required on holi pro describing the GPIO configuration for Nfc controller chip. Modified corresponding Nfc device node for QRD platform. Change-Id: I136c8a39bfe577c44503d79656ee08c8e51b23ab --- qcom/holi-qrd-pm6125.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 92f333ba00fe..03a022f1203f 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -88,6 +88,29 @@ status = "ok"; }; +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &wsa881x_analog_reset_gpio { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; From e288930ec668af39de90908bb9238493e9f8b4a0 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Mon, 7 Jun 2021 17:02:47 +0530 Subject: [PATCH 1540/1809] ARM: dts: msm: Updating platform dtb(s) for blair targetr Change to update platform (mtp, cdp and qrd) dtbs to avoid conflicts with other target platforms for blair target. Change-Id: Ic9555c52804ad4e5837df9c879b1a0f3cfd93fdd --- qcom/blair-cdp.dtsi | 366 +++++++++++++++++++++++- qcom/blair-mtp.dtsi | 431 +++++++++++++++++++++++++++- qcom/blair-qrd.dtsi | 675 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 1457 insertions(+), 15 deletions(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 5fd4a5cf3890..5daf868128c5 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,22 +1,309 @@ -#include "holi-cdp-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-cdp-pm6125.dtsi" +#include #include "display/blair-sde-display-cdp.dtsi" -/ { -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-max-microamp = <85700>; -}; &pm6125_pwm { status = "ok"; }; +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L11A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L4A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + &qupv3_se8_i2c { #address-cells = <1>; #size-cells = <0>; + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; - status = "ok"; + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + }; novatek@62 { compatible = "novatek,NVT-ts"; @@ -26,7 +313,7 @@ interrupts = <22 0x2008>; pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; + "pmx_ts_release"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; @@ -40,3 +327,62 @@ &dsi_nt36672e_fhd_plus_144_video>; }; }; + +#include "camera/blair-camera-sensor-cdp.dtsi" + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + + diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index a6d49cabf0d7..57cfbb5efe4b 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -1,9 +1,432 @@ -#include "holi-mtp-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-mtp-pm6125.dtsi" +#include #include "display/blair-sde-display-mtp.dtsi" -/ { + + + +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-max-microamp = <85700>; + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; }; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L11A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L4A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +#include "camera/blair-camera-sensor-mtp.dtsi" + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + + diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 0014141744c7..7d88d673165d 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -1,6 +1,679 @@ -#include "holi-qrd-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "display/holi-sde-display-qrd-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include + +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + status = "ok"; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&wsa881x_analog_reset_gpio { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; + +&wsa881x_i2c_e { + status = "ok"; + cdc-vdd-1p8-supply = <&L9A>; + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x0e>; + clock-names = "wsa_mclk"; + clocks = <&wsa881x_analog_clk 0>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; + qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; +}; + +&holi_snd { + qcom,model = "holi-qrd-snd-card"; + qcom,sku-model = "holi-qrdsku1-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS3", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrMono WSA_IN", "AUX", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd937x_codec>, <&wsa881x_i2c_e>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd937x_codec", "wsa-codec0"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 5000000 4500000 + 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 500000>; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + trips { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip2: battery-trip2 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + + modem-skin-cdev0 { + trip = <&modem_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&modem_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&cx_trip>; + cooling-device = <&modem_skin 3 3>; + }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <54000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; }; From b62bff1524a030a3600a8ec45354d654acb4b1e3 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 18 May 2020 13:22:18 +0530 Subject: [PATCH 1541/1809] dt-bindings: Add victims_table bindings for cx_ipeak driver Victim table support for client to register and throttle freq based on the cx-ipeak interrupt notifier callbacks to clients. Change-Id: I9717056e638ed70f5bf848f99f07a0b2c6919938 --- bindings/soc/qcom/qcom,cx_ipeak.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/bindings/soc/qcom/qcom,cx_ipeak.txt b/bindings/soc/qcom/qcom,cx_ipeak.txt index 42dd78ba50fe..79e99d348914 100644 --- a/bindings/soc/qcom/qcom,cx_ipeak.txt +++ b/bindings/soc/qcom/qcom,cx_ipeak.txt @@ -6,17 +6,37 @@ if it is going to cross its own threshold. If all clients are going to cross their thresholds then Cx ipeak hw module will raise an interrupt to cDSP block to throttle cDSP's fmax. +There are SOC like SCUBA where Cx ipeak HW module raised interrupt will +throttle frequency of other victim clients. + Required properties: +- #size-cells : Must be 1 + - compatible : name of the component used for driver matching, should be one "qcom,cx-ipeak-v1", "qcom,cx-ipeak-v2" - reg : physical base address and length of the register set(s), SRAM and XPU of the component. +Optional properties: + +- interrupts : Danger and Safe interrupts details having interrupt number and + type of interrupt. + +- interrupt-names : Identifier names for Danger and Safe interrupts. + +- victims_table : Victim clients details having client ID, victim ID and + limit frequency to be applied in case of danger interrupt. + Example: cx_ipeak_lm: cx_ipeak@1fe5040 { + #size-cells = <1>; compatible = "qcom,cx-ipeak-v1"; reg = <0x01fe5040 0x28>; + interrupts = <0 415 IRQ_TYPE_EDGE_RISING>, + <0 416 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "cx_ipeak_danger", "cx_ipeak_safe"; + victims_table = <1 0 844800000>; }; From ea130acc092e2c4575898218d8ac2717c0bc40d8 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 8 Jun 2021 20:16:44 +0530 Subject: [PATCH 1542/1809] ARM: dts: qcom: enable cx ipeak common driver for holi-pm6125 Enable common driver to limit Cx ipeak based on voting from various clients in multimedia. Change-Id: I8e89c8acd40716936943d6e100e4cee05b9a68f6 --- qcom/holi-cdp-pm6125.dtsi | 7 +++++++ qcom/holi-mtp-pm6125.dtsi | 7 +++++++ qcom/holi-mtp-usbc-pm6125.dtsi | 7 +++++++ qcom/holi-qrd-pm6125.dtsi | 7 +++++++ 4 files changed, 28 insertions(+) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index e85d061a45f3..fc52a355f145 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -148,6 +148,13 @@ linux,can-disable; }; }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; }; &pm7250b_charger { diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 5138898ec886..d6a0c69ba746 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -155,6 +155,13 @@ #include "qg-batterydata-atl466271_3300mAh.dtsi" #include "qg-batterydata-atl436186020H_3780mAh.dtsi" }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; }; &soc { diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 04eb38e0137e..1dc219f16ba2 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -174,6 +174,13 @@ #include "qg-batterydata-atl466271_3300mAh.dtsi" #include "qg-batterydata-atl436186020H_3780mAh.dtsi" }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; }; &soc { diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 03a022f1203f..2fa5a875f24c 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -211,6 +211,13 @@ #include "qg-batterydata-atl436186020H_3780mAh.dtsi" #include "qg-batterydata-atl466271_3300mAh.dtsi" }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; }; &pm7250b_charger { From a4d06336ca3b8d2bf628f5ad567823982ecf3c80 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 8 Jun 2021 20:48:34 +0530 Subject: [PATCH 1543/1809] ARM: dts: msm: Enable cpufreq cooling device for BLAIR Add cooling-cells proprty to enable cpufreq cooling device for BLAIR. Change-Id: Ic1f7d703eaef8049026e1cbb3267e7d53d65ed00 --- qcom/blair.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b2437923577e..58f833e86eca 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -69,6 +69,7 @@ cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 6>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -176,6 +177,7 @@ cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 2>; + #cooling-cells = <2>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; From 2dd8c8ebad05b2398ceb971212d96d8fbe22fe40 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 27 May 2021 18:26:54 +0800 Subject: [PATCH 1544/1809] ARM: dts: msm: increase dump entries size in blair Increse I1_i/dcache dump entries size in blair. Change-Id: I90ea8c100050e83b296e7c0e425eda7499bfbd8e --- qcom/blair.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b2437923577e..108b9e577d19 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -673,32 +673,32 @@ }; l1_icache0 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x60>; }; l1_icache1 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x61>; }; l1_icache2 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x62>; }; l1_icache3 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x63>; }; l1_icache100 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x64>; }; l1_icache101 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x65>; }; @@ -713,32 +713,32 @@ }; l1_dcache0 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x80>; }; l1_dcache1 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x81>; }; l1_dcache2 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x82>; }; l1_dcache3 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x83>; }; l1_dcache100 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x84>; }; l1_dcache101 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x85>; }; From ede814a82325285a20a41ed056ed55c1a72ee758 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 1 Jun 2021 16:03:02 +0800 Subject: [PATCH 1545/1809] ARM: dts: msm: correct dump entry size Correct dump entry size for gold core on blair. Change-Id: I5da214817c55b76865e6dcd31a9937e1cf73286b --- qcom/blair.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 108b9e577d19..3bdb5006aabc 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -663,12 +663,12 @@ }; c102_scandump: c102_scandump { - qcom,dump-size = <0x25900>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x136>; }; c103_scandump: c103_scandump { - qcom,dump-size = <0x25900>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x137>; }; @@ -703,12 +703,12 @@ }; l1_icache102 { - qcom,dump-size = <0x21000>; + qcom,dump-size = <0x15100>; qcom,dump-id = <0x66>; }; l1_icache103 { - qcom,dump-size = <0x21000>; + qcom,dump-size = <0x15100>; qcom,dump-id = <0x67>; }; @@ -743,12 +743,12 @@ }; l1_dcache102 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x86>; }; l1_dcache103 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x87>; }; @@ -813,12 +813,12 @@ }; l2_tlb102 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x6100>; qcom,dump-id = <0x126>; }; l2_tlb103 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x6100>; qcom,dump-id = <0x127>; }; From cd5e7ce128022e467f080c67647b17bea5a7d4d8 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 28 May 2021 14:26:37 +0530 Subject: [PATCH 1546/1809] ARM: dts: msm: Update DLL values as per HSR for blair Update DLL values as per HSR for blair. Also remove unnecessary property. Change-Id: I4fca5867bcb4dda3d7c7b7c729b3b457c6978d48 --- qcom/blair.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b2437923577e..b42a415ece5f 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2790,7 +2790,7 @@ 100000000 200000000 400000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -2805,7 +2805,6 @@ no-sd; no-sdio; - max-frequency = <192000000>; qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2864,7 +2863,7 @@ 100000000 200000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; bus-width = <4>; @@ -2873,7 +2872,6 @@ no-mmc; no-sdio; - max-frequency = <202000000>; qcom,devfreq,freq-table = <50000000 202000000>; From 752aa460c644bbbdbb918799df2bde1a43680410 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 28 May 2021 10:59:54 +0800 Subject: [PATCH 1547/1809] ARM: dts: msm: Add touch for QRD Holi-pm6125 And new touch node for QRD Holi-pm6125 device. Change-Id: I5814485668823e2972cbfcb8ccb2d60e6b6620de --- qcom/holi-qrd-pm6125.dtsi | 62 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 03a022f1203f..f1514b122d80 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -665,3 +665,65 @@ }; }; }; + +&tlmm { + touch_avdd_default: touch_avdd_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd { + compatible = "regulator-fixed"; + regulator-name = "touch_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 53 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&touch_avdd_default>; + }; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vcc_i2c-supply = <&L9A>; + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; +}; From 2f287027249b72ff8a283a75e0a5467a92eb05dc Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 28 May 2021 10:45:46 +0800 Subject: [PATCH 1548/1809] ARM: dts: msm: use dummy regulator for new QRD Holi The 3V eLDO controlled by gpio#53 is always ON, to avoid any conflict with the ALS sensor that is also using the same GPIO. Make use of a dummy regulator for the touch 3V supply. Change-Id: I12f9a0ffb5f2717949569d0c15a2a943bf45be69 --- qcom/holi-qrd-pm6125.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index f1514b122d80..3fe6a35823c6 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -683,16 +683,16 @@ }; &soc { - touch_avdd: touch_avdd { - compatible = "regulator-fixed"; - regulator-name = "touch_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 53 0>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&touch_avdd_default>; + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; }; }; From b7cfe1d499d5d26eca29f373e97e6423785fef0f Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Sat, 5 Jun 2021 16:05:33 +0530 Subject: [PATCH 1549/1809] ARM: dts: msm: Removing signal-aop from pils on Blair Removing signal-aop property from adscp,cdsp and modem nodes on Blair as they were causing errors. Change-Id: I1b750361fd3cae746a2e61bdf030c9d74eef8115 --- qcom/blair.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b2437923577e..5c7d13d0c2c2 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2914,7 +2914,6 @@ memory-region = <&pil_adsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; - qcom,signal-aop; /* Inputs from lpass */ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, @@ -2956,7 +2955,6 @@ memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; - qcom,signal-aop; /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, @@ -2998,7 +2996,6 @@ qcom,minidump-id = <3>; qcom,aux-minidump-ids = <4>; qcom,complete-ramdump; - qcom,signal-aop; /* Inputs from mss */ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, From 762cecdfb840a5c26348e37630e1a39ab38862ab Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Fri, 7 May 2021 10:06:46 -0700 Subject: [PATCH 1550/1809] ARM: dts: msm: Update the memory map for 1 GB variants of sdxlemur Update the memory map for all 1 GB variants of sdxlemur to version 2 by introducing a carveout for audio usecases. Change-Id: I7a387bbcbb1e6d290625549a56315142bf7fefb3 --- qcom/sdxlemur-1024mb.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdxlemur-1024mb.dtsi b/qcom/sdxlemur-1024mb.dtsi index 86fae265cfbd..e7985b5815af 100644 --- a/qcom/sdxlemur-1024mb.dtsi +++ b/qcom/sdxlemur-1024mb.dtsi @@ -7,3 +7,9 @@ &access_control_mem { reg = <0x8fd80000 0x80000>; }; + +&reserved_memory { + audio_heap_mem: audio_mem_region@8c000000 { + reg = <0x8c000000 0x400000>; + }; +}; From 13bb7b25dfcd665ad895be5123dedf9233a8bb12 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Fri, 7 May 2021 18:08:55 -0700 Subject: [PATCH 1551/1809] ARM: dts: msm: Add an audio ION device node for the audio carveout heap Add an audio ION device node for the audio carveout heap on sdxlemur to ensure that the carveout region is hyp assigned at boot. Change-Id: I32809f50c2767a65303bc6de7e91ad8a310ba84e --- qcom/sdx-audio-lpass.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi index 2369bfe586b0..0cf809dc3c8f 100644 --- a/qcom/sdx-audio-lpass.dtsi +++ b/qcom/sdx-audio-lpass.dtsi @@ -19,6 +19,12 @@ memory-region = <&audio_mem>; }; + qcom,msm-audio-ion-co { + compatible = "qcom,msm-audio-ion-cma"; + qcom,scm-mp-enabled; + memory-region = <&audio_heap_mem>; + }; + pcm0: qcom,msm-pcm { compatible = "qcom,msm-pcm-dsp"; qcom,msm-pcm-dsp-id = <0>; From 40fb3c8793fb83c19d2dd6eaee32cae2ed2b31c7 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Wed, 28 Apr 2021 13:43:04 -0700 Subject: [PATCH 1552/1809] ARM: dts: msm: Add a carveout heap for audio usecases on sdxlemur Define a carveout heap for audio usecases on 1 GB variants of sdxlemur. Change-Id: I71e1904b68b85a16da7f9d95ca60363dffaf51a7 --- qcom/sdxlemur-audio.dtsi | 5 +++++ qcom/sdxlemur-ion.dtsi | 10 ++++++++++ 2 files changed, 15 insertions(+) diff --git a/qcom/sdxlemur-audio.dtsi b/qcom/sdxlemur-audio.dtsi index 4f3cae1c280c..189ec72a5c12 100644 --- a/qcom/sdxlemur-audio.dtsi +++ b/qcom/sdxlemur-audio.dtsi @@ -38,3 +38,8 @@ "msm-dai-q6-auxpcm.2"; }; }; + +&audio_co_heap { + status = "okay"; + memory-region = <&audio_heap_mem>; +}; diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index dbf4220881a9..8fb6e0abb786 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -17,6 +17,16 @@ qcom,ion-heap-type = "DMA"; }; + audio_co_heap: qcom,ion-heap@17 { /* AUDIO CARVEOUT HEAP */ + reg = ; + qcom,ion-heap-type = "MSM_CARVEOUT"; + /* + * memory-region must be specified when enabled here or + * when the node is overridden to be enabled elsewhere. + */ + status = "disabled"; + }; + qcom,ion-heap@27 { /* QSEECOM HEAP */ reg = ; memory-region = <&qseecom_mem>; From 4fc73ce5c56ceed3ef49fc5ebaecc349e9328b02 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Fri, 7 May 2021 10:09:46 -0700 Subject: [PATCH 1553/1809] ARM: dts: msm: Remove the audio ION CMA heap for sdxlemur Remove the audio ION CMA heap, along with its associated memory region, and the audio device node, as they are no longer in use. Change-Id: Ifa5730b8fd6a3f2ceeea82bee8aec153f82d60e1 --- qcom/sdx-audio-lpass.dtsi | 6 ------ qcom/sdxlemur-ion.dtsi | 6 ------ qcom/sdxlemur.dtsi | 8 -------- 3 files changed, 20 deletions(-) diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi index 0cf809dc3c8f..fdbf5d95c4e0 100644 --- a/qcom/sdx-audio-lpass.dtsi +++ b/qcom/sdx-audio-lpass.dtsi @@ -14,12 +14,6 @@ }; qcom,msm-audio-ion { - compatible = "qcom,msm-audio-ion-cma"; - qcom,scm-mp-enabled; - memory-region = <&audio_mem>; - }; - - qcom,msm-audio-ion-co { compatible = "qcom,msm-audio-ion-cma"; qcom,scm-mp-enabled; memory-region = <&audio_heap_mem>; diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi index 8fb6e0abb786..ae1ce3979e3f 100644 --- a/qcom/sdxlemur-ion.dtsi +++ b/qcom/sdxlemur-ion.dtsi @@ -11,12 +11,6 @@ qcom,ion-heap-type = "MSM_SYSTEM"; }; - qcom,ion-heap@8 { /* AUDIO HEAP */ - reg = ; - memory-region = <&audio_mem>; - qcom,ion-heap-type = "DMA"; - }; - audio_co_heap: qcom,ion-heap@17 { /* AUDIO CARVEOUT HEAP */ reg = ; qcom,ion-heap-type = "MSM_CARVEOUT"; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index b111a051ee4d..a130619ee521 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -69,14 +69,6 @@ size = <0x400000>; }; - - audio_mem: audio_region@0 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - size = <0x400000>; - }; - llcc_tcm_mem: llcc_tcm_region { no-map; reg = <0x15800000 0x800000>; From 108e18e7fd045339acea5d35777755f6cefff7ff Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Thu, 10 Jun 2021 15:13:49 +0800 Subject: [PATCH 1554/1809] ARM: dts: msm: Add UFS regulators for qrd blair This change add support for UFS regulators for qrd blair. Change-Id: I9e0856e59c326dee56c090e0b99b8b6f0eee0bf5 --- qcom/blair-qrd.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 7d88d673165d..9aff69b88fcd 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -74,8 +74,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <85700>; vdda-pll-max-microamp = <18300>; @@ -86,15 +86,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; From 186af4cedd2102b7028ce4a2ff39954d9e76c92b Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Thu, 10 Jun 2021 15:55:49 +0800 Subject: [PATCH 1555/1809] ARM: dts: msm: Add touch for QRD Blair Add new tree node for touchscreen to support Blair platform. Change-Id: Iacb042bc1897f61d0c6e3cec8941f4bed8437976 --- qcom/blair-qrd.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 7d88d673165d..5bac1086d3c2 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -677,3 +677,49 @@ }; }; }; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vcc_i2c-supply = <&L9A>; + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; +}; From 33e3509c7c954ef1c49f7c0f29bcc2eebd939275 Mon Sep 17 00:00:00 2001 From: Faiz Kuchay Date: Sun, 6 Jun 2021 12:38:01 +0530 Subject: [PATCH 1556/1809] ARM: dts: msm: Set proper wsa reset gpio Set proper wsa881x analog reset gpio for blair cdp. Change-Id: I3665d523f95fb82641d1abf270457c9d39174632 --- qcom/blair-cdp-overlay.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/blair-cdp-overlay.dts b/qcom/blair-cdp-overlay.dts index e4b36a584b26..c46e6e97fc86 100644 --- a/qcom/blair-cdp-overlay.dts +++ b/qcom/blair-cdp-overlay.dts @@ -9,3 +9,8 @@ qcom,msm-id = <507 0x10000>; qcom,board-id = <1 0>; }; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; From dcb016769fa1bea22eca3f9164f34e69c39eec08 Mon Sep 17 00:00:00 2001 From: xsang Date: Thu, 10 Jun 2021 17:07:44 +0800 Subject: [PATCH 1557/1809] ARM: dts: msm: change vdd supply for WSA Change vdd supply to L9A. Change-Id: I7160af184d97ea341e3ecd21eb310a0ca2190834 --- qcom/blair-qrd.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 5bac1086d3c2..9a0a68891cc3 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -21,9 +21,6 @@ &wcd937x_codec { status = "ok"; - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", @@ -36,6 +33,15 @@ cdc-vdd-mic-bias-supply = <>; }; +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + + &sdhc_1 { status = "ok"; From 5d1dd23f5e1b06746f09ce95271b1a137cc3d71b Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Tue, 8 Jun 2021 15:57:33 -0700 Subject: [PATCH 1558/1809] ARM: dts: msm: Disable TBU halting for pcie tbu on sdxlemur Due to pcie ordering rules, halting a tbu which accepts pcie traffic can cause a deadlock. Change-Id: I3d99b04160ac28034943007764b7fa5398af875b --- qcom/msm-arm-smmu-sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/msm-arm-smmu-sdxlemur.dtsi b/qcom/msm-arm-smmu-sdxlemur.dtsi index 3a9d9a4535b8..87325e336ac2 100644 --- a/qcom/msm-arm-smmu-sdxlemur.dtsi +++ b/qcom/msm-arm-smmu-sdxlemur.dtsi @@ -60,6 +60,7 @@ interconnects = <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IMEM_CFG>; qcom,active-only; + qcom,opt-out-tbu-halting; }; ipa_tbu: ipa_tbu@15049000 { From f81b8dc22a8f7806f2e46c3a9ed5fc1182bebad0 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 28 May 2021 14:26:37 +0530 Subject: [PATCH 1559/1809] ARM: dts: msm: Update DLL values as per HSR for blair Update DLL values as per HSR for blair. Also remove unnecessary property. Change-Id: I4fca5867bcb4dda3d7c7b7c729b3b457c6978d48 --- qcom/blair.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 6d3b9158511b..a58e6ebdfdf8 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2788,7 +2788,7 @@ 100000000 200000000 400000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -2803,7 +2803,6 @@ no-sd; no-sdio; - max-frequency = <192000000>; qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; @@ -2862,7 +2861,7 @@ 100000000 200000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; bus-width = <4>; @@ -2871,7 +2870,6 @@ no-mmc; no-sdio; - max-frequency = <202000000>; qcom,devfreq,freq-table = <50000000 202000000>; From 87442bf2eca01e4480f0e8f918f135e003a820e0 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Sat, 5 Jun 2021 16:05:33 +0530 Subject: [PATCH 1560/1809] ARM: dts: msm: Removing signal-aop from pils on Blair Removing signal-aop property from adscp,cdsp and modem nodes on Blair as they were causing errors. Change-Id: I1b750361fd3cae746a2e61bdf030c9d74eef8115 --- qcom/blair.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index a58e6ebdfdf8..f1a6b272fe95 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2910,7 +2910,6 @@ memory-region = <&pil_adsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; - qcom,signal-aop; /* Inputs from lpass */ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, @@ -2952,7 +2951,6 @@ memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; qcom,minidump-as-elf32; - qcom,signal-aop; /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, @@ -2994,7 +2992,6 @@ qcom,minidump-id = <3>; qcom,aux-minidump-ids = <4>; qcom,complete-ramdump; - qcom,signal-aop; /* Inputs from mss */ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, From bdd79a35128c9713b54b0286e710d9a6482ef9a1 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Sat, 5 Jun 2021 12:07:50 +0530 Subject: [PATCH 1561/1809] ARM: dts: msm: Add support for usb nodes on blair Set usb mode as otg and also add support for dpdm supply, usb charger. Remove the core id as there is only 1 core being used. Change-Id: I9b3dac927bfa0eca09fb1fc783f53c029ca94fb3 --- qcom/blair-usb.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index e5d935f4bcf9..7c707b10f214 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -33,6 +33,8 @@ reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + qcom,usb-charger; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; @@ -56,14 +58,13 @@ tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; + snps,is-utmi-l1-suspend; snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - usb-core-id = <0>; maximum-speed = "super-speed"; - dr_mode = "drd"; + dr_mode = "otg"; }; }; From 21ace7e157353b5b912c5b75762d93bb906a9ec8 Mon Sep 17 00:00:00 2001 From: Faiz Kuchay Date: Sun, 6 Jun 2021 12:38:01 +0530 Subject: [PATCH 1562/1809] ARM: dts: msm: Set proper wsa reset gpio Set proper wsa881x analog reset gpio for blair cdp. Change-Id: I3665d523f95fb82641d1abf270457c9d39174632 --- qcom/blair-cdp-overlay.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/blair-cdp-overlay.dts b/qcom/blair-cdp-overlay.dts index e4b36a584b26..c46e6e97fc86 100644 --- a/qcom/blair-cdp-overlay.dts +++ b/qcom/blair-cdp-overlay.dts @@ -9,3 +9,8 @@ qcom,msm-id = <507 0x10000>; qcom,board-id = <1 0>; }; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; From 5ee9f358700a8241f86cb4c285f2c71e5e78f7b4 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Mon, 7 Jun 2021 17:02:47 +0530 Subject: [PATCH 1563/1809] ARM: dts: msm: Updating platform dtb(s) for blair targetr Change to update platform (mtp, cdp and qrd) dtbs to avoid conflicts with other target platforms for blair target. Change-Id: Ic9555c52804ad4e5837df9c879b1a0f3cfd93fdd --- qcom/blair-cdp.dtsi | 366 +++++++++++++++++++++++- qcom/blair-mtp.dtsi | 431 +++++++++++++++++++++++++++- qcom/blair-qrd.dtsi | 675 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 1457 insertions(+), 15 deletions(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 5fd4a5cf3890..5daf868128c5 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,22 +1,309 @@ -#include "holi-cdp-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-cdp-pm6125.dtsi" +#include #include "display/blair-sde-display-cdp.dtsi" -/ { -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-max-microamp = <85700>; -}; &pm6125_pwm { status = "ok"; }; +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L11A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L4A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + &qupv3_se8_i2c { #address-cells = <1>; #size-cells = <0>; + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; - status = "ok"; + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + }; novatek@62 { compatible = "novatek,NVT-ts"; @@ -26,7 +313,7 @@ interrupts = <22 0x2008>; pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; + "pmx_ts_release"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; @@ -40,3 +327,62 @@ &dsi_nt36672e_fhd_plus_144_video>; }; }; + +#include "camera/blair-camera-sensor-cdp.dtsi" + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + + diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index a6d49cabf0d7..57cfbb5efe4b 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -1,9 +1,432 @@ -#include "holi-mtp-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-mtp-pm6125.dtsi" +#include #include "display/blair-sde-display-mtp.dtsi" -/ { + + + +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-max-microamp = <85700>; + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; }; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L11A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L4A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +#include "camera/blair-camera-sensor-mtp.dtsi" + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + + diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 0014141744c7..7d88d673165d 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -1,6 +1,679 @@ -#include "holi-qrd-pm6125.dtsi" +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay-pm6125.dtsi" +#include "display/holi-sde-display-qrd-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include + +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&wcd937x_codec { + status = "ok"; + /delete-property/ cdc-vdd-mic-bias-supply; + /delete-property/ qcom,cdc-vdd-mic-bias-voltage; + /delete-property/ qcom,cdc-vdd-mic-bias-current; + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&wsa881x_analog_reset_gpio { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; + +&wsa881x_i2c_e { + status = "ok"; + cdc-vdd-1p8-supply = <&L9A>; + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x0e>; + clock-names = "wsa_mclk"; + clocks = <&wsa881x_analog_clk 0>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; + qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; +}; + +&holi_snd { + qcom,model = "holi-qrd-snd-card"; + qcom,sku-model = "holi-qrdsku1-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + qcom,wcn-btfm = <1>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS3", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrMono WSA_IN", "AUX", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd937x_codec>, <&wsa881x_i2c_e>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd937x_codec", "wsa-codec0"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 5000000 4500000 + 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 500000>; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + trips { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip2: battery-trip2 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + + modem-skin-cdev0 { + trip = <&modem_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&modem_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&cx_trip>; + cooling-device = <&modem_skin 3 3>; + }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <54000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; }; From 734d1ea7decdff340728c133a5188e8ba44d4340 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Mon, 7 Jun 2021 15:58:26 +0530 Subject: [PATCH 1564/1809] ARM: dts: msm: Add camera device tree inclusions for Blair camera Include camera device tree nodes to enable camera functionality on Blair target. CRs-Fixed: 2944976 Change-Id: Ibf7273f6f94f32e652bd201425f60a562fb65fe0 --- qcom/blair.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index f1a6b272fe95..72c48603b0a4 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3346,7 +3346,7 @@ #include "holi-coresight.dtsi" #include "holi-pm.dtsi" #include "holi-vidc.dtsi" -#include "camera/holi-camera.dtsi" +#include "camera/blair-camera.dtsi" #include "holi-thermal.dtsi" #include "holi-qupv3.dtsi" #include "display/blair-sde.dtsi" From cb30e695824654f027a12c36a8f305c954ff88fc Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 8 Jun 2021 20:48:34 +0530 Subject: [PATCH 1565/1809] ARM: dts: msm: Enable cpufreq cooling device for BLAIR Add cooling-cells proprty to enable cpufreq cooling device for BLAIR. Change-Id: Ic1f7d703eaef8049026e1cbb3267e7d53d65ed00 --- qcom/blair.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 72c48603b0a4..a31a28892221 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -69,6 +69,7 @@ cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 6>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -176,6 +177,7 @@ cpu-release-addr = <0x0 0x50000000>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 2>; + #cooling-cells = <2>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; From 2c6d070584a1d47712caedd5292be0aff05dea40 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 27 May 2021 18:26:54 +0800 Subject: [PATCH 1566/1809] ARM: dts: msm: increase dump entries size in blair Increse I1_i/dcache dump entries size in blair. Change-Id: I90ea8c100050e83b296e7c0e425eda7499bfbd8e --- qcom/blair.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index a31a28892221..f5f3ba12193f 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -675,32 +675,32 @@ }; l1_icache0 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x60>; }; l1_icache1 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x61>; }; l1_icache2 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x62>; }; l1_icache3 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x63>; }; l1_icache100 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x64>; }; l1_icache101 { - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x10900>; qcom,dump-id = <0x65>; }; @@ -715,32 +715,32 @@ }; l1_dcache0 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x80>; }; l1_dcache1 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x81>; }; l1_dcache2 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x82>; }; l1_dcache3 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x83>; }; l1_dcache100 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x84>; }; l1_dcache101 { - qcom,dump-size = <0x9000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x85>; }; From a08c12624704de215c5aa37737329d00d2782b85 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 1 Jun 2021 16:03:02 +0800 Subject: [PATCH 1567/1809] ARM: dts: msm: correct dump entry size Correct dump entry size for gold core on blair. Change-Id: I5da214817c55b76865e6dcd31a9937e1cf73286b --- qcom/blair.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index f5f3ba12193f..9aecadb2f753 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -665,12 +665,12 @@ }; c102_scandump: c102_scandump { - qcom,dump-size = <0x25900>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x136>; }; c103_scandump: c103_scandump { - qcom,dump-size = <0x25900>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x137>; }; @@ -705,12 +705,12 @@ }; l1_icache102 { - qcom,dump-size = <0x21000>; + qcom,dump-size = <0x15100>; qcom,dump-id = <0x66>; }; l1_icache103 { - qcom,dump-size = <0x21000>; + qcom,dump-size = <0x15100>; qcom,dump-id = <0x67>; }; @@ -745,12 +745,12 @@ }; l1_dcache102 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x86>; }; l1_dcache103 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9100>; qcom,dump-id = <0x87>; }; @@ -815,12 +815,12 @@ }; l2_tlb102 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x6100>; qcom,dump-id = <0x126>; }; l2_tlb103 { - qcom,dump-size = <0x7800>; + qcom,dump-size = <0x6100>; qcom,dump-id = <0x127>; }; From 9f6a29d07945a929a3eeabd15104e61acc526799 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 21 May 2021 13:19:26 +0800 Subject: [PATCH 1568/1809] ARM: dts: msm: include display nodes for pm6125 platform of Holi qrd target Included display platform dtsi nodes for qrd platform. Change-Id: I727692996a88a0a7d939892824ec3c06d7f8748f --- qcom/holi-qrd-pm6125.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index f663af22cfd8..92f333ba00fe 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-qrd-pm6125.dtsi" #include &wcd938x_codec { From 51866c64f1e42e2af015e9ea8d29afd60b1eba63 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Wed, 26 May 2021 09:57:29 +0800 Subject: [PATCH 1569/1809] ARM: dts: msm: Add UFS regulators for qrd holi-pm6125 This change add support for UFS regulators for qrd holi-pm6125 according to the new powergrid. Change-Id: Ib37f6c8290071e62a34bdc7bd046fd9f4cf93499 --- qcom/holi-qrd-pm6125.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 92f333ba00fe..0d9b9e44b70e 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -62,8 +62,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <62900>; vdda-pll-max-microamp = <18300>; @@ -74,15 +74,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; From 385c33fd45844237d1f6d1cb2c2a076b245f72b6 Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Thu, 3 Jun 2021 14:13:08 +0530 Subject: [PATCH 1570/1809] ARM: dts: msm: Add I2C NFC device node for holi pro QRD variant Device node changes required on holi pro describing the GPIO configuration for Nfc controller chip. Modified corresponding Nfc device node for QRD platform. Change-Id: I136c8a39bfe577c44503d79656ee08c8e51b23ab --- qcom/holi-qrd-pm6125.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 0d9b9e44b70e..4da63892a8d3 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -88,6 +88,29 @@ status = "ok"; }; +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &wsa881x_analog_reset_gpio { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; From db18453a439fc7bfd82ef39ecf4fde744416fb17 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 28 May 2021 10:59:54 +0800 Subject: [PATCH 1571/1809] ARM: dts: msm: Add touch for QRD Holi-pm6125 And new touch node for QRD Holi-pm6125 device. Change-Id: I5814485668823e2972cbfcb8ccb2d60e6b6620de --- qcom/holi-qrd-pm6125.dtsi | 62 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 4da63892a8d3..08353392e3d8 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -665,3 +665,65 @@ }; }; }; + +&tlmm { + touch_avdd_default: touch_avdd_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd { + compatible = "regulator-fixed"; + regulator-name = "touch_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 53 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&touch_avdd_default>; + }; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vcc_i2c-supply = <&L9A>; + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; +}; From 6a1978541c160a2f03b06fb9e77a60c354a0f0f9 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Thu, 10 Jun 2021 15:13:49 +0800 Subject: [PATCH 1572/1809] ARM: dts: msm: Add UFS regulators for qrd blair This change add support for UFS regulators for qrd blair. Change-Id: I9e0856e59c326dee56c090e0b99b8b6f0eee0bf5 --- qcom/blair-qrd.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 7d88d673165d..9aff69b88fcd 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -74,8 +74,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <85700>; vdda-pll-max-microamp = <18300>; @@ -86,15 +86,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; From 47ce022489cedd259adfd44853fe11515181ca36 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 10 Jun 2021 14:40:50 +0800 Subject: [PATCH 1573/1809] ARM: dts: msm: include display nodes for Blair qrd This change includes display DT nodes to enable display support on Blair qrd. Change-Id: I62202edccce334d99bef79f2651717739fdb398f --- qcom/blair-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 9aff69b88fcd..b21d0b32f0b2 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include "display/holi-sde-display-qrd-pm6125.dtsi" +#include "display/blair-sde-display-qrd.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include From 995c64b43caddcaa848220df691273d7f0c6951b Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Thu, 10 Jun 2021 15:55:49 +0800 Subject: [PATCH 1574/1809] ARM: dts: msm: Add touch for QRD Blair Add new tree node for touchscreen to support Blair platform. Change-Id: Iacb042bc1897f61d0c6e3cec8941f4bed8437976 --- qcom/blair-qrd.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index b21d0b32f0b2..3dbfc33aad93 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -678,3 +678,49 @@ }; }; }; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vcc_i2c-supply = <&L9A>; + vdd-supply = <&touch_avdd>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; +}; From b57796d9015d9e13f62c47774849d39b185a088b Mon Sep 17 00:00:00 2001 From: xsang Date: Thu, 10 Jun 2021 17:07:44 +0800 Subject: [PATCH 1575/1809] ARM: dts: msm: change vdd supply for WSA Change vdd supply to L9A. Change-Id: I7160af184d97ea341e3ecd21eb310a0ca2190834 --- qcom/blair-qrd.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 3dbfc33aad93..1be3df02eee8 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -22,9 +22,6 @@ &wcd937x_codec { status = "ok"; - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", @@ -37,6 +34,15 @@ cdc-vdd-mic-bias-supply = <>; }; +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + + &sdhc_1 { status = "ok"; From fcd6def32462ee0e12f7247f29b37fdcc11d9608 Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Tue, 1 Jun 2021 10:21:23 +0800 Subject: [PATCH 1576/1809] ARM: dts: msm: Include camera sensor dtsi for blair QRD Include camera sensor dtsi for blair QRD CRs-Fixed: 2958083 External Impact: No. Change-Id: I5d94751e454669c22dc2642cc5374014efeb0c22 --- qcom/blair-qrd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 1be3df02eee8..b43bf1b23542 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -730,3 +730,5 @@ &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; + +#include "camera/blair-camera-sensor-mtp.dtsi" From cd2edb7abd62a2ee8540bcddd9fc21d94a795b86 Mon Sep 17 00:00:00 2001 From: xsang Date: Tue, 1 Jun 2021 10:48:06 +0800 Subject: [PATCH 1577/1809] ARM: dts: msm: Remove unused static supply for holi-pm6125 remove unused static supply for holi-pm6125 at QRD. Change-Id: I757219345aa52f1c68f8fbd022904e2111d4b4c6 --- qcom/holi-qrd-pm6125.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 08353392e3d8..30a10fef5c41 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -7,11 +7,16 @@ #include &wcd938x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wcd937x_codec { @@ -21,6 +26,14 @@ /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &sdhc_1 { From 38bd708099b3953af0fcf8394111739ae21f32b1 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 14 Jun 2021 16:21:59 +0530 Subject: [PATCH 1578/1809] ARM: dts: msm: Add extcon phandle for usb0 on blair cdp This change adds extcon phandle for usb0 on blair cdp target which is used by pd driver to notify usb disconnect and connect. Change-Id: I743fef112def8dbe958c4a1c228421d5df6092de --- qcom/blair-cdp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 5daf868128c5..4d96032681ca 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -379,6 +379,7 @@ }; &usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; From ac732de368ad70113cd1676c6aeab83f04c2c58c Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 13 Jun 2021 19:06:42 +0530 Subject: [PATCH 1579/1809] ARM: dts: msm: Correct SPMI node name for holi-pm6125 ADC_TM Correct PM6125 SPMI node name used for defining ADC_TM_IIO device for holi-pm6125, to ensure device gets probed. Change-Id: If9e06dab1bcf354dd3bdc9a778837a9d3f589e56 --- qcom/holi-pmic-overlay-pm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index 50e4b105d44f..55d28a9c7adc 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -178,7 +178,7 @@ }; &spmi_bus { - qcom,pm6125@4 { + qcom,pm6125@0 { pm6125_adc_tm_iio: adc_tm@3400 { compatible = "qcom,adc-tm5-iio"; reg = <0x3400>; From a39a251d1616fe404fedfb052a1174815c743feb Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 14 Jun 2021 16:21:59 +0530 Subject: [PATCH 1580/1809] ARM: dts: msm: Add extcon phandle for usb0 on blair cdp This change adds extcon phandle for usb0 on blair cdp target which is used by pd driver to notify usb disconnect and connect. Change-Id: I743fef112def8dbe958c4a1c228421d5df6092de --- qcom/blair-cdp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 5daf868128c5..4d96032681ca 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -379,6 +379,7 @@ }; &usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; From 32efe14dbbe572c1193f4c00a64fba4a7713dba2 Mon Sep 17 00:00:00 2001 From: xsang Date: Tue, 1 Jun 2021 10:48:06 +0800 Subject: [PATCH 1581/1809] ARM: dts: msm: Remove unused static supply for holi-pm6125 remove unused static supply for holi-pm6125 at QRD. Change-Id: I757219345aa52f1c68f8fbd022904e2111d4b4c6 --- qcom/holi-qrd-pm6125.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 120cf574a35a..7ad29879d30e 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -7,11 +7,16 @@ #include &wcd938x_codec { - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &wcd937x_codec { @@ -21,6 +26,14 @@ /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; &sdhc_1 { From e6ba540ac692cf6e885e88d59843839b1414ed6d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 15 Jun 2021 18:09:33 +0800 Subject: [PATCH 1582/1809] ARM: dts: msm: disable mss cti on holi Some clock for mss cti is not enabled from kernel side. so disable it. Change-Id: I90ee22999014d8a5c0867cf2b134e30bb7dfdd9b --- qcom/holi-coresight.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 964ea4bece57..f8a70456182b 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -2431,6 +2431,7 @@ coresight-name = "coresight-cti-mss_q6_cti"; + status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; @@ -2443,6 +2444,7 @@ coresight-name = "coresight-cti-mss_vq6_cti"; + status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; From 2b465e121d6d8a49f83c8693514f6d6ad2aea6b5 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 15 Jun 2021 18:08:56 +0530 Subject: [PATCH 1583/1809] ARM: dts: msm: Give Blair its own MPM pins mapping configuration Currently both Blair and Holi use the same MPM pins mapping configuration as they use the same compatible string. USB PHY has a different GIC IRQ on Blair, so different MPM configuration is required. Change-Id: I83b79ac2711dd0b6cb871529b7a14c3d9a8213f9 --- bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/blair.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index dcce6028e872..a3c194ce837e 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -28,6 +28,7 @@ Properties: "qcom,mpm-gic-sdxnightjar" "qcom,mpm-gic-monaco" "qcom,mpm-gic-qcs405" + "qcom,mpm-gic-blair" - interrupts: Usage: required diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 06aab9467036..cc0b0d9ecf04 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -973,7 +973,7 @@ }; wakegic: wake-gic { - compatible = "qcom,mpm-gic-holi", "qcom,mpm"; + compatible = "qcom,mpm-gic-blair", "qcom,mpm"; interrupts = ; reg = <0x45f01b8 0x1000>, <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ From c5c86b9cc832a372348844a6d81eb18b4bc6d9ce Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Wed, 26 May 2021 09:57:29 +0800 Subject: [PATCH 1584/1809] ARM: dts: msm: Add UFS regulators for qrd holi-pm6125 This change add support for UFS regulators for qrd holi-pm6125 according to the new powergrid. Change-Id: Ib37f6c8290071e62a34bdc7bd046fd9f4cf93499 --- qcom/holi-qrd-pm6125.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 7ad29879d30e..bfa05a5556cf 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -75,8 +75,8 @@ &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; - vdda-phy-supply = <&L18A>; - vdda-pll-supply = <&L22A>; + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; vdda-phy-max-microamp = <62900>; vdda-pll-max-microamp = <18300>; @@ -87,15 +87,15 @@ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; - vcc-supply = <&L7E>; + vcc-supply = <&L24A>; vcc-voltage-level = <2950000 2960000>; vcc-max-microamp = <800000>; - vccq2-supply = <&L12A>; + vccq2-supply = <&L11A>; vccq2-max-microamp = <800000>; vccq2-voltage-level = <1800000 1800000>; - qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-supply = <&L4A>; qcom,vddp-ref-clk-max-microamp = <100>; status = "ok"; From 1f1a8184875bbe340bd4a4e6ece16b1a60dc5618 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 10 Jun 2021 14:40:50 +0800 Subject: [PATCH 1585/1809] ARM: dts: msm: include display nodes for Blair qrd This change includes display DT nodes to enable display support on Blair qrd. Change-Id: I62202edccce334d99bef79f2651717739fdb398f --- qcom/blair-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 9a0a68891cc3..404ad2c0eaf7 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay-pm6125.dtsi" #include "display/holi-sde-display-qrd-pm6125.dtsi" +#include "display/blair-sde-display-qrd.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include From 533d2a243c1a7b51ec51b5468df72593a14a7267 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 16 Jun 2021 10:23:16 +0530 Subject: [PATCH 1586/1809] ARM: dts: msm: Update QG cutoff/empty thresholds for blair/holi-pm6125 Update the QG cutoff and empty values to align with the system design. Primarily change vbat-cutoff to 3.4V as these platforms do not support BoB. Change-Id: I1a09217d3cebab2eb1f66b4a0a54b889a1acab3f --- qcom/blair-cdp.dtsi | 5 +++++ qcom/blair-mtp.dtsi | 6 +++++- qcom/blair-qrd.dtsi | 6 +++++- qcom/holi-cdp-pm6125.dtsi | 5 +++++ qcom/holi-mtp-pm6125.dtsi | 6 +++++- qcom/holi-mtp-usbc-pm6125.dtsi | 6 +++++- qcom/holi-qrd-pm6125.dtsi | 6 +++++- 7 files changed, 35 insertions(+), 5 deletions(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 4d96032681ca..9da96e91e159 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -235,6 +235,11 @@ qcom,hold-soc-while-full; qcom,linearize-soc; qcom,cl-feedback-on; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &soc { diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 57cfbb5efe4b..e56acffa42c9 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -312,9 +312,13 @@ qcom,cl-feedback-on; qcom,tcss-enable; qcom,fvss-enable; - qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; qcom,use-cp-iin-sns; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &pm7250b_vadc { diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 9a0a68891cc3..b67dbe04936d 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -338,9 +338,13 @@ qcom,cl-feedback-on; qcom,tcss-enable; qcom,fvss-enable; - qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; qcom,use-cp-iin-sns; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &pm7250b_charger { diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index fc52a355f145..a55f74033b08 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -237,6 +237,11 @@ qcom,hold-soc-while-full; qcom,linearize-soc; qcom,cl-feedback-on; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &soc { diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d6a0c69ba746..0b91f6abb82d 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -317,9 +317,13 @@ qcom,cl-feedback-on; qcom,tcss-enable; qcom,fvss-enable; - qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; qcom,use-cp-iin-sns; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &pm7250b_vadc { diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 1dc219f16ba2..2aadb8d08d33 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -336,9 +336,13 @@ qcom,cl-feedback-on; qcom,tcss-enable; qcom,fvss-enable; - qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; qcom,use-cp-iin-sns; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; #include "camera/holi-camera-sensor-usbc-pm6125-mtp.dtsi" diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 7ad29879d30e..9eca954836bb 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -340,9 +340,13 @@ qcom,cl-feedback-on; qcom,tcss-enable; qcom,fvss-enable; - qcom,fvss-vbatt-mv = <3300>; qcom,bass-enable; qcom,use-cp-iin-sns; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,vbatt-low-mv = <3500>; + qcom,fvss-vbatt-mv = <3500>; }; &pm7250b_charger { From 47159f5aaf2ec4766d7c6f3f15e2df872fd4f312 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 14 Jun 2021 20:34:09 +0530 Subject: [PATCH 1587/1809] ARM: dts: msm: update ADC channels for holi-pm6125 Delete PMR735A and PMR735B ADC channels from PMK8350's list of ADC channels, and xo_therm on PM6125 VADC, as they are not used for holi-pm6125. Change-Id: Ie2252f9e31236bf794b25bef6250bbd406d327ce --- qcom/holi-pmic-overlay-pm6125.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index 50e4b105d44f..0a0f9f042c06 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -66,6 +66,8 @@ &rfc_cam_therm_default &rear_cam_flash_therm_default>; + /delete-node/ xo_therm; + pa_therm1 { reg = ; label = "pa_therm1"; @@ -232,6 +234,14 @@ /delete-node/ pm8350b_die_temp; /delete-node/ pm8350b_vph_pwr; /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735a_ref_gnd; + /delete-node/ pmr735a_vref_1p25; + /delete-node/ pmr735a_die_temp; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; }; &pmk8350_adc_tm { From e6ae0f5d2fc2545f91f36bbe01810c2561ed830c Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Wed, 9 Jun 2021 16:04:17 +0530 Subject: [PATCH 1588/1809] bindings: input: qcom-hv-haptics: Add "qcom,pm5100-haptics" Add bindings for new compatible "qcom,pm5100-haptics". This compatible is used for PM5100 haptics. Change-Id: I338904950cbbd08590dafb88974396948480c231 --- bindings/input/qcom-hv-haptics.txt | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/bindings/input/qcom-hv-haptics.txt b/bindings/input/qcom-hv-haptics.txt index 805b3baedf70..8f4800b7cc0f 100644 --- a/bindings/input/qcom-hv-haptics.txt +++ b/bindings/input/qcom-hv-haptics.txt @@ -18,13 +18,15 @@ Properties: Value type: Definition: It can be one of following: "qcom,hv-haptics", - "qcom,pm8350b-haptics". + "qcom,pm8350b-haptics", + "qcom,pm5100-haptics". - reg: Usage: required Value type: Definition: Register base for following haptics modules: HAPTICS_CFG, - HAPTICS_PATTERN, HAPTICS_BOOST. + HAPTICS_PATTERN, HAPTICS_BOOST. HAPTICS_BOOST register base + is not applicable for PM5100. - interrupts: Usage: required @@ -76,9 +78,11 @@ Properties: Value type: Definition: Specifies the FIFO empty threshold. The "fifo-empty" IRQ will be triggered when the number of the samples in the FIFO is less - than the threshold. For PM8350B v1, allowed value is 1 - 103 - and the default value is 48. For PM8350B v2, allowed value is - 1 - 639 and the default value is 280. + than the threshold. For PM8350B v1, allowed value is 0 - 104 + in multiple of 4 and the default value is 48. For PM8350B v2, + allowed value is 0 - 640 in multiple of 40 and the default + value is 280. For PM5100, allowed value is 0 - 1024 in multiple + of 32 and the default value is 288. - qcom,use-erm: Usage: optional @@ -91,33 +95,36 @@ Properties: Value type: Definition: The nvmem cell name of the SDAM module where the closed-loop brake calibration settings can be stored. It must be - "hap_cl_brake". + "hap_cl_brake". Not applicable for PM5100. - nvmem-cells: Usage: optional Value type: Definition: Phandle of the nvmem cell to store the closed-loop brake calibration settings. Please refer to nvmem bindings as - described in bindings/nvmem/nvmem.txt. + described in bindings/nvmem/nvmem.txt. Not applicable + for PM5100. - nvmem-names: Usage: optional Value type: Definition: The nvmem device name of the SDAM module used for haptics - configuration. It must be "hap_cfg_sdam". + configuration. It must be "hap_cfg_sdam". Not applicable for + PM5100. - nvmem: Usage: optional Value type: Definition: Phandle of the nvmem device used for haptics configuration. Please refer to nvmem bindings as described in bindings/nvmem/nvmem.txt. + Not applicable for PM5100. - qcom,pbs-client: Usage: optional Value type: Definition: Phandle of the PBS client used for triggering PBS to configure haptics ISC (short circuit current) config during LRA impedance - detection. + detection. Not applicable for PM5100. - qcom,hpwr-supply: Usage: optional From a7cab5cd107ec08b75daf637af78b86a6d9ece48 Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Tue, 1 Jun 2021 10:21:23 +0800 Subject: [PATCH 1589/1809] ARM: dts: msm: Include camera sensor dtsi for blair QRD Include camera sensor dtsi for blair QRD CRs-Fixed: 2958083 External Impact: No. Change-Id: I5d94751e454669c22dc2642cc5374014efeb0c22 --- qcom/blair-qrd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 9a0a68891cc3..c3c5f4fb59b9 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -729,3 +729,5 @@ &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; + +#include "camera/blair-camera-sensor-qrd.dtsi" From f9831016c883b5593a128196f0ec54cbb2902f87 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Sat, 5 Jun 2021 12:07:50 +0530 Subject: [PATCH 1590/1809] ARM: dts: msm: Add support for usb nodes on blair Set usb mode as otg and also add support for dpdm supply, usb charger. Remove the core id as there is only 1 core being used. Change-Id: I9b3dac927bfa0eca09fb1fc783f53c029ca94fb3 --- qcom/blair-usb.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index e5d935f4bcf9..7c707b10f214 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -33,6 +33,8 @@ reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + qcom,usb-charger; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; @@ -56,14 +58,13 @@ tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; + snps,is-utmi-l1-suspend; snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - usb-core-id = <0>; maximum-speed = "super-speed"; - dr_mode = "drd"; + dr_mode = "otg"; }; }; From 3490ad0759ffae48b52377869d9500893e34b9d7 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Mon, 7 Jun 2021 11:52:45 +0530 Subject: [PATCH 1591/1809] ARM: dts: msm: Vote for S5A during wlan operations This change adds regulator handler of S5A which is needed for wlan operations. Change-Id: I3ab3df1b772757e890161cfd39f2fd1044b9ffca --- qcom/blair.dtsi | 1 + qcom/holi-pm6125-overlay.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 06aab9467036..e59644baa8ee 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3741,6 +3741,7 @@ vdd-1.3-rfa-supply = <&L2A>; vdd-3.3-ch1-supply = <&L21A>; vdd-3.3-ch0-supply = <&L23A>; + vdd-smps-supply = <&S5A>; qcom,vdd-cx-mx-config = <640000 640000>; qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 4d9a2a267dfc..9a75187e1932 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -12,6 +12,7 @@ vdd-1.3-rfa-supply = <&L2A>; vdd-3.3-ch1-supply = <&L21A>; vdd-3.3-ch0-supply = <&L23A>; + vdd-smps-supply = <&S5A>; qcom,vdd-cx-mx-config = <640000 640000>; qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; From 71e5af97a7fa9e50740051438a298548e9ab8a09 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Mon, 31 May 2021 15:17:52 +0530 Subject: [PATCH 1592/1809] ARM: dts: msm: Vote for S5A during BT operations This change adds regulator handler of S5A which is needed for BT operations. Change-Id: I80682930806e622edc5afccac2a0bee4496f3170 --- qcom/blair.dtsi | 2 ++ qcom/holi-pm6125-overlay.dtsi | 3 +++ 2 files changed, 5 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 06aab9467036..62600f49b3b8 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3755,11 +3755,13 @@ bluetooth: bt_wcn3990 { compatible = "qcom,wcn3990"; qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-smps-supply = <&S5A>; /* SMPS */ qcom,bt-vdd-io-supply = <&L9A>; /* IO */ qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ + qcom,bt-vdd-smps-config = <984000 984000 1 0>; qcom,bt-vdd-io-config = <1700000 1900000 1 0>; qcom,bt-vdd-core-config = <1304000 1304000 1 0>; qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 4d9a2a267dfc..ddbd276e35f6 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -18,10 +18,13 @@ }; &bluetooth { + qcom,bt-vdd-smps-supply = <&S5A>; /* SMPS */ qcom,bt-vdd-io-supply = <&L9A>; /* IO */ qcom,bt-vdd-core-supply = <&L2A>; /* RFA */ qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ qcom,bt-vdd-xtal-supply = <&L16A>; /* XO */ + + qcom,bt-vdd-smps-config = <984000 984000 1 0>; }; &dispcc { From 7379d578806649fc1c5d8f72479e0625d21e52c9 Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Tue, 18 May 2021 16:54:06 +0800 Subject: [PATCH 1593/1809] ARM: dts: msm: Include camera sensor dtsi for QRD Holi-pm6125 Directly include MTP camera sensor dtsi for QRD Holi-pm6125. MTP and QRD can share the same one. CRs-Fixed: 2956799 External Impact: No. Change-Id: I09d633d8a127965e8a2ddfa8b611dbd8240b5cdb --- qcom/holi-qrd-pm6125.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 7ad29879d30e..0bdd82fe03aa 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -5,6 +5,7 @@ #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-qrd-pm6125.dtsi" #include +#include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { cdc-vdd-rxtx-supply = <&L9A>; @@ -233,6 +234,8 @@ }; }; +#include "camera/holi-camera-sensor-pm6125-mtp.dtsi" + &pm7250b_charger { status = "ok"; #io-channel-cells = <1>; From c5c2180fa8faa8aa11f05b9019541a6fc01effca Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Mon, 7 Jun 2021 15:58:26 +0530 Subject: [PATCH 1594/1809] ARM: dts: msm: Add camera device tree inclusions for Blair camera Include camera device tree nodes to enable camera functionality on Blair target. CRs-Fixed: 2971145 Change-Id: Ibf7273f6f94f32e652bd201425f60a562fb65fe0 --- qcom/blair.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 06aab9467036..2840ca8c47e8 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3350,7 +3350,7 @@ #include "holi-coresight.dtsi" #include "holi-pm.dtsi" #include "holi-vidc.dtsi" -#include "camera/holi-camera.dtsi" +#include "camera/blair-camera.dtsi" #include "holi-thermal.dtsi" #include "holi-qupv3.dtsi" #include "display/blair-sde.dtsi" From 5b209ca1ee902570f4be1bedd32b8d5d7320edfb Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 17 Jun 2021 14:49:38 -0700 Subject: [PATCH 1595/1809] ARM: dts: qcom: Limit PCIe to Gen3 for oculink connects on sdxlemur Force Gen3 as target link speed for oculink connects. Change-Id: I0c4e67bd67f929b5b530cf80eeaf657dc4854ca4 --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index c945092880d4..088efbf1ad3c 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -143,3 +143,7 @@ }; }; }; + +&pcie0 { + qcom,target-link-speed = <3>; +}; From 84177dd036206e281659952ab13c2ddfc452e0d4 Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Mon, 3 May 2021 09:46:55 -0700 Subject: [PATCH 1596/1809] ARM: dts: msm: add ntn3/qps615 pci DT nodes for sdxlemur Update pci DT nodes with virtual end points. Change-Id: I3df0f9a967b15668bdaad858b69b005b0dd72b32 --- qcom/sdxlemur-mtp-cpe.dtsi | 16 ++++++++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 5fb9b8f8c7b4..f6993fafd059 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -94,6 +94,22 @@ /* BDF 2.3.0 */ pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { reg = <0x1800 0x0 0x0 0x0 0x0>; + /* BDF 5.0.0 */ + pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + qcom,iommu-group = <ð0_pci_iommu_group>; + eth0_pci_iommu_group: eth0_pci_iommu_group { + qcom,iommu-dma = "atomic"; + }; + }; + /* BDF 5.0.1 */ + pcie0_bus5_dev0_fn1: pcie0_ntn3_eth1 { + reg = <0x100 0x0 0x0 0x0 0x0>; + qcom,iommu-group = <ð1_pci_iommu_group>; + eth1_pci_iommu_group: eth1_pci_iommu_group { + qcom,iommu-dma = "atomic"; + }; + }; }; }; }; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 42ae590813bb..4335ee88f0f6 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -72,6 +72,14 @@ /* BDF 2.3.0 */ pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { reg = <0x1800 0x0 0x0 0x0 0x0>; + /* BDF 5.0.0 */ + pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + qcom,iommu-group = <ð_pci_iommu_group>; + eth_pci_iommu_group: eth_pci_iommu_group { + qcom,iommu-dma = "atomic"; + }; + }; }; }; }; From bde83ca7f0a14ed72ae207d19b60b2ffbdaa589f Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Wed, 16 Jun 2021 10:28:28 +0530 Subject: [PATCH 1597/1809] ARM: dts: msm: Set proper vddpx supply Set proper vddpx supply in blair cdp, mtp and qrd. Set proper vddpx supply in holi-pm6125 cdp, mtp, usbc-mtp and qrd. Change-Id: Idc36bc1964ca31a43c24263eb8a4f937de9917c3 --- qcom/blair-cdp.dtsi | 2 +- qcom/blair-mtp.dtsi | 2 +- qcom/blair-qrd.dtsi | 2 +- qcom/holi-cdp-pm6125.dtsi | 2 +- qcom/holi-mtp-pm6125.dtsi | 2 +- qcom/holi-mtp-usbc-pm6125.dtsi | 2 +- qcom/holi-qrd-pm6125.dtsi | 5 +---- 7 files changed, 7 insertions(+), 10 deletions(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 4d96032681ca..145fd9db169e 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -26,7 +26,7 @@ &wcd937x_codec { cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 57cfbb5efe4b..e4283e66cf3c 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -24,7 +24,7 @@ &wcd937x_codec { cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 9a0a68891cc3..233e2c596b92 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -22,7 +22,7 @@ &wcd937x_codec { status = "ok"; cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index fc52a355f145..58ffdc3e129a 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -22,7 +22,7 @@ &wcd937x_codec { cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index d6a0c69ba746..c9d2b97e938d 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -22,7 +22,7 @@ &wcd937x_codec { cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 1dc219f16ba2..ab437101649e 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -22,7 +22,7 @@ &wcd937x_codec { cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 7ad29879d30e..7b670dbd0351 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -21,11 +21,8 @@ &wcd937x_codec { status = "ok"; - /delete-property/ cdc-vdd-mic-bias-supply; - /delete-property/ qcom,cdc-vdd-mic-bias-voltage; - /delete-property/ qcom,cdc-vdd-mic-bias-current; cdc-vdd-rxtx-supply = <&L9A>; - cdc-vddio-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; qcom,cdc-static-supplies = "cdc-vdd-rxtx", "cdc-vddpx"; /* From a92db3aaa82d625b4e73247cfbdd82949b8291bb Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 16 Jun 2021 18:23:04 +0800 Subject: [PATCH 1598/1809] ARM: dts: msm: correct l2_cache dump size on blair Correct l2_cache memory dump size on blair. Change-Id: I288543d05c2abfa7f5bad001e25f7ffc8593eabe --- qcom/blair.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index e59644baa8ee..ec8063bd82d5 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -775,12 +775,12 @@ }; l2_cache102 { - qcom,dump-size = <0x90100>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc6>; }; l2_cache103 { - qcom,dump-size = <0x90100>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc7>; }; From 29637f18c441082b2cbdb3892b1be59d40e7677a Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Sat, 12 Jun 2021 14:01:53 +0530 Subject: [PATCH 1599/1809] ARM: dts: msm: Updating ATP platform dtb for blair target Change to update ATP platform dtb to avoid conflicts with other target platforms for blair target. Change-Id: I2a9faa8d4e0e3699c32b8c41d888f38d10770c94 --- qcom/blair-atp.dtsi | 311 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 305 insertions(+), 6 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index f4363bcfac46..0626eec24cc3 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -1,3 +1,11 @@ +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pmic-overlay.dtsi" +#include "display/holi-sde-display-atp.dtsi" +#include "holi-thermal-overlay.dtsi" +#include + &rpm_bus { /* Delete all PM6125 and PMR735a rpm-regulators */ /delete-node/ rpm-regulator-smpa6; @@ -323,11 +331,6 @@ }; }; -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-yupik"; - vdda-phy-max-microamp = <85700>; -}; - #include "pm6350-rpm-regulator.dtsi" #include "pm6150l-rpm-regulator.dtsi" #include "holi-regulators-pm6350.dtsi" @@ -376,7 +379,303 @@ }; }; -#include "holi-atp.dtsi" + + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <325000 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&qupv3_se10_i2c { + status = "disabled"; +}; + +&pm8008_8 { + status = "disabled"; +}; + +&pm8008_9 { + status = "disabled"; +}; + +&pm6150a_amoled { + status = "ok"; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; &qusb_phy0 { vdd-supply = <&L18A>; From 3e6b4d3a631bf5f7c9cd4136f757926705f42d1a Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 15 Jun 2021 13:01:54 +0530 Subject: [PATCH 1600/1809] ARM: dts: msm: Fix resource-name and id for holi-pm6125-regulator Fix resource-name and id for S5A in holi-pm6125-regulator.dtsi. Change-Id: Iee1d105c53808e75826b0068040d75fa1c17d80c --- qcom/holi-regulators-pm6125.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index 519b66a0b9d6..652065155f87 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -374,6 +374,8 @@ &rpm_bus { rpm-regulator-smpa5 { + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; status = "okay"; S5A: pm6125_s5: regulator-s5 { regulator-min-microvolt = <382000>; From 1a58fd7311965334aab351f563ec514865e33e39 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 4 Jun 2021 17:14:21 +0530 Subject: [PATCH 1601/1809] ARM: dts: msm: Add clkreq gpio for PCIe nodes for yupik Add clkreq gpio info to pass to pcie driver to enable/disable its wakeup capability. This is neeeded to wakeup ADSP from L1SS, when PCIe endpoint asserts clkreq gpio from high to low as part of DRV functionality for yupik. Change-Id: I887dab033c77d346ad5dd8b12c34c8cd3abc202c --- qcom/yupik-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 83133d79f313..87937dc4284a 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -37,6 +37,7 @@ perst-gpio = <&tlmm 87 0>; wake-gpio = <&tlmm 89 0>; + qcom,clkreq-gpio = <88>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie0_perst_default &pcie0_clkreq_default @@ -311,6 +312,7 @@ perst-gpio = <&tlmm 2 0>; wake-gpio = <&tlmm 3 0>; + qcom,clkreq-gpio = <79>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_perst_default &pcie1_clkreq_default From f24830cded9ca6d17ac4faf10ea5b826e1680878 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 2 Jun 2021 15:26:14 +0530 Subject: [PATCH 1602/1809] ARM: dts: msm: Add nopmi support for holi-pm6125 and blair Add nopmi support for holi-pm6125 and blair platforms. In addition, correct the name of usb phy used for blair. Change-Id: I06b3e2ea69562d22ec9c01014e37fbfb6019e629 --- qcom/Makefile | 7 +- qcom/blair-atp.dtsi | 4 +- qcom/blair-cdp.dtsi | 3 +- qcom/blair-mtp-nopmi-overlay.dts | 2 + qcom/blair-mtp-nopmi.dts | 2 + qcom/blair-mtp-nopmi.dtsi | 4 +- qcom/blair-mtp-overlay.dts | 6 + qcom/blair-mtp.dts | 6 + qcom/blair-mtp.dtsi | 233 ---------------------- qcom/blair-qrd-nopmi-overlay.dts | 2 + qcom/blair-qrd-nopmi.dts | 2 + qcom/blair-qrd-nopmi.dtsi | 4 +- qcom/blair-qrd-overlay.dts | 6 + qcom/blair-qrd.dts | 6 + qcom/blair-qrd.dtsi | 258 ------------------------ qcom/blair-usb.dtsi | 6 +- qcom/holi-cdp-pm6125.dtsi | 1 + qcom/holi-mtp-pm6125-nopmi-overlay.dts | 14 ++ qcom/holi-mtp-pm6125-nopmi.dts | 6 +- qcom/holi-mtp-pm6125-overlay.dts | 1 + qcom/holi-mtp-pm6125.dts | 1 + qcom/holi-mtp-pm6125.dtsi | 232 ---------------------- qcom/holi-mtp-pm7250b.dtsi | 232 ++++++++++++++++++++++ qcom/holi-mtp-usbc-pm6125.dtsi | 1 + qcom/holi-pm6125-overlay.dtsi | 12 ++ qcom/holi-pm7250b.dtsi | 151 +++++++++++++- qcom/holi-pmic-overlay-pm6125.dtsi | 79 -------- qcom/holi-qrd-pm6125-nopmi-overlay.dts | 15 ++ qcom/holi-qrd-pm6125-nopmi.dts | 14 ++ qcom/holi-qrd-pm6125-overlay.dts | 1 + qcom/holi-qrd-pm6125.dts | 1 + qcom/holi-qrd-pm6125.dtsi | 258 ------------------------ qcom/holi-qrd-pm7250b.dtsi | 264 +++++++++++++++++++++++++ qcom/holi-thermal-overlay-pm6125.dtsi | 78 -------- 34 files changed, 759 insertions(+), 1153 deletions(-) create mode 100644 qcom/holi-mtp-pm7250b.dtsi create mode 100644 qcom/holi-qrd-pm6125-nopmi-overlay.dts create mode 100644 qcom/holi-qrd-pm6125-nopmi.dts create mode 100644 qcom/holi-qrd-pm7250b.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index d2843e1e640f..45654538a8d4 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -106,7 +106,8 @@ dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-cdp-lcd-pm6125-overlay.dtbo \ holi-mtp-usbc-pm6125-overlay.dtbo \ holi-mtp-pm6125-nopmi-overlay.dtbo \ - holi-qrd-pm6125-overlay.dtbo + holi-qrd-pm6125-overlay.dtbo \ + holi-qrd-pm6125-nopmi-overlay.dtbo holi-rumi-overlay.dtbo-base := holi.dtb holi-mtp-overlay.dtbo-base := holi.dtb @@ -121,6 +122,7 @@ holi-cdp-lcd-pm6125-overlay.dtbo-base := holi.dtb holi-mtp-usbc-pm6125-overlay.dtbo-base := holi.dtb holi-mtp-pm6125-nopmi-overlay.dtbo-base := holi.dtb holi-qrd-pm6125-overlay.dtbo-base := holi.dtb +holi-qrd-pm6125-nopmi-overlay.dtbo-base := holi.dtb else dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ @@ -135,7 +137,8 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-cdp-lcd-pm6125.dtb \ holi-mtp-usbc-pm6125.dtb \ holi-mtp-pm6125-nopmi.dtb \ - holi-qrd-pm6125.dtb + holi-qrd-pm6125.dtb \ + holi-qrd-pm6125-nopmi.dtb endif diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 0626eec24cc3..7b8d509b9815 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -622,7 +622,7 @@ }; &pm7250b_charger { - dpdm-supply = <&qusb_phy0>; + dpdm-supply = <&usb2_phy0>; smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; @@ -677,7 +677,7 @@ io-channel-names = "chg_type"; }; -&qusb_phy0 { +&usb2_phy0 { vdd-supply = <&L18A>; vdda18-supply = <&L2A>; vdda33-supply = <&L3A>; diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index c5b6fe5a2a76..a4432d2ea265 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -1,6 +1,7 @@ #include "holi-audio-overlay.dtsi" #include #include +#include "holi-pm7250b.dtsi" #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-cdp-pm6125.dtsi" @@ -336,7 +337,7 @@ #include "camera/blair-camera-sensor-cdp.dtsi" &pm7250b_charger { - dpdm-supply = <&qusb_phy0>; + dpdm-supply = <&usb2_phy0>; smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; diff --git a/qcom/blair-mtp-nopmi-overlay.dts b/qcom/blair-mtp-nopmi-overlay.dts index 45f5b62a29a8..a879373f8d08 100644 --- a/qcom/blair-mtp-nopmi-overlay.dts +++ b/qcom/blair-mtp-nopmi-overlay.dts @@ -8,5 +8,7 @@ compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; qcom,msm-id = <507 0x10000>; qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/blair-mtp-nopmi.dts b/qcom/blair-mtp-nopmi.dts index aa80d9f34851..d6bc812200b8 100644 --- a/qcom/blair-mtp-nopmi.dts +++ b/qcom/blair-mtp-nopmi.dts @@ -7,5 +7,7 @@ model = "Qualcomm Technologies, Inc. Blair MTP NOPMI"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/blair-mtp-nopmi.dtsi b/qcom/blair-mtp-nopmi.dtsi index 336d7a250678..a00189357ba1 100644 --- a/qcom/blair-mtp-nopmi.dtsi +++ b/qcom/blair-mtp-nopmi.dtsi @@ -1,2 +1,2 @@ -/ { -}; +#include "blair-mtp.dtsi" + diff --git a/qcom/blair-mtp-overlay.dts b/qcom/blair-mtp-overlay.dts index 7f1464083f57..624cb3f025ec 100644 --- a/qcom/blair-mtp-overlay.dts +++ b/qcom/blair-mtp-overlay.dts @@ -2,11 +2,17 @@ /plugin/; #include "blair-mtp.dtsi" +#include "holi-mtp-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. Blair MTP"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; qcom,msm-id = <507 0x10000>; qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; }; +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blair-mtp.dts b/qcom/blair-mtp.dts index b02097f25f9d..6806d92ab64b 100644 --- a/qcom/blair-mtp.dts +++ b/qcom/blair-mtp.dts @@ -2,10 +2,16 @@ #include "blair.dtsi" #include "blair-mtp.dtsi" +#include "holi-mtp-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. Blair MTP"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; }; +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 6285b1ce213e..72c09ebd187a 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -4,7 +4,6 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" -#include #include "display/blair-sde-display-mtp.dtsi" @@ -150,13 +149,6 @@ linux,can-disable; }; }; - - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-alium-3600mah.dtsi" - #include "qg-batterydata-atl466271_3300mAh.dtsi" - #include "qg-batterydata-atl436186020H_3780mAh.dtsi" - }; }; &soc { @@ -207,230 +199,5 @@ }; }; -&pm7250b_charger { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, - <&pm7250b_vadc ADC5_USB_IN_I>, - <&pm7250b_vadc ADC5_CHG_TEMP>, - <&pm7250b_vadc ADC5_DIE_TEMP>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_SBUx>, - <&pm7250b_vadc ADC5_VPH_PWR>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, - <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, - <&pm7250b_qg PSY_IIO_TEMP>, - <&pm7250b_qg PSY_IIO_CAPACITY>, - <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, - <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, - <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, - <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, - <&pm7250b_qg PSY_IIO_CC_SOC>, - <&pm7250b_qg PSY_IIO_CURRENT_NOW>, - <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL>, - <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, - <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, - <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, - <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage", - "skin_temp", - "resistance_id", - "voltage_now", - "temp", - "capacity", - "voltage_ocv", - "voltage_avg", - "debug_battery", - "real_capacity", - "cc_soc", - "current_now", - "voltage_max", - "charge_full", - "charge_counter", - "cycle_count", - "charge_full_design", - "time_to_full_now", - "cp_parallel_mode", - "cp_parallel_output_mode", - "cp_min_icl", - "cp_switcher_en", - "cp_enable", - "cp_ilim", - "cp_die_temp"; - qcom,battery-data = <&mtp_batterydata>; - qcom,sec-charger-config = <1>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,suspend-input-on-debug-batt; - qcom,fcc-stepping-enable; - qcom,fcc-step-delay-ms = <100>; - qcom,fcc-step-size-ua = <100000>; - qcom,smb-internal-pull-kohm = <0>; - qcom,en-skin-therm-mitigation; - qcom,hvdcp3-standalone-config; -}; - -&pm7250b_qg { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, - <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, - <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, - <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, - <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; - io-channel-names = "batt-therm", - "batt-id", - "input_current_limited", - "recharge_soc", - "force_recharge", - "charge_done", - "cp_charging_enabled"; - qcom,battery-data = <&mtp_batterydata>; - qcom,qg-iterm-ma = <150>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; - qcom,tcss-enable; - qcom,fvss-enable; - qcom,bass-enable; - qcom,use-cp-iin-sns; - qcom,vbatt-cutoff-mv = <3400>; - qcom,vbatt-empty-mv = <3200>; - qcom,vbatt-empty-cold-mv = <3100>; - qcom,vbatt-low-mv = <3500>; - qcom,fvss-vbatt-mv = <3500>; -}; - -&pm7250b_vadc { - smb1390_therm@e { - qcom,scale-fn-type = ; - }; -}; - -&pm7250b_gpios { - smb_stat { - smb_stat_default: smb_stat_default { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = <0>; - }; - }; -}; - -&qupv3_se10_i2c { - status = "ok"; - #include "smb1394.dtsi" -}; - -&smb1394 { - interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1394"; - pinctrl-names = "default"; - qcom,enable-toggle-stat; - pinctrl-0 = <&smb_stat_default>; - status = "ok"; -}; - -&smb1394_div2_cp_primary { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, - <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, - <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "die_temp", - "real_type", - "adapter_cc_mode", - "pd_current_max", - "input_current_settled", - "smb_en_mode", - "smb_en_reason"; - qcom,parallel-input-mode = <1>; /* USBIN */ - qcom,parallel-output-mode = <2>; /* VBAT */ - status = "ok"; -}; - #include "camera/blair-camera-sensor-mtp.dtsi" -&pm7250b_charger { - dpdm-supply = <&qusb_phy0>; - - smb5_vbus: qcom,smb5-vbus { - regulator-name = "smb5-vbus"; - }; - - smb5_vconn: qcom,smb5-vconn { - regulator-name = "smb5-vconn"; - }; -}; - -&pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; - vbus-supply = <&smb5_vbus>; - vconn-supply = <&smb5_vconn>; - - #io-channel-cells = <1>; - io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, - <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, - <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, - <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, - <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, - <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_PR_SWAP>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_MODE>, - <&pm7250b_charger PSY_IIO_PE_START>; - io-channel-names = "pd_active", - "typec_cc_orientation", - "connector_type", - "typec_power_role", - "pd_usb_suspend_supported", - "typec_src_rp", - "pd_in_hard_reset", - "pr_current_max", - "pr_swap", - "pd_voltage_min", - "pd_voltage_max", - "real_type", - "typec_mode", - "pe_start"; -}; - -&usb0 { - extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; - - #io-channel-cells = <1>; - io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; - io-channel-names = "chg_type"; -}; - - diff --git a/qcom/blair-qrd-nopmi-overlay.dts b/qcom/blair-qrd-nopmi-overlay.dts index 744a11f3e773..242b301e2408 100644 --- a/qcom/blair-qrd-nopmi-overlay.dts +++ b/qcom/blair-qrd-nopmi-overlay.dts @@ -8,5 +8,7 @@ compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; qcom,msm-id = <507 0x10000>; qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/blair-qrd-nopmi.dts b/qcom/blair-qrd-nopmi.dts index f09f4f93d5de..b4cf4fdeb04c 100644 --- a/qcom/blair-qrd-nopmi.dts +++ b/qcom/blair-qrd-nopmi.dts @@ -7,5 +7,7 @@ model = "Qualcomm Technologies, Inc. Blair QRD NOPMI"; compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/blair-qrd-nopmi.dtsi b/qcom/blair-qrd-nopmi.dtsi index 336d7a250678..23729e5a518c 100644 --- a/qcom/blair-qrd-nopmi.dtsi +++ b/qcom/blair-qrd-nopmi.dtsi @@ -1,2 +1,2 @@ -/ { -}; +#include "blair-qrd.dtsi" + diff --git a/qcom/blair-qrd-overlay.dts b/qcom/blair-qrd-overlay.dts index 04955e482053..57c75c1c53cd 100644 --- a/qcom/blair-qrd-overlay.dts +++ b/qcom/blair-qrd-overlay.dts @@ -2,11 +2,17 @@ /plugin/; #include "blair-qrd.dtsi" +#include "holi-qrd-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. Blair QRD"; compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; qcom,msm-id = <507 0x10000>; qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; }; +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blair-qrd.dts b/qcom/blair-qrd.dts index b0bc35a9f0bb..3e1602501c4b 100644 --- a/qcom/blair-qrd.dts +++ b/qcom/blair-qrd.dts @@ -2,10 +2,16 @@ #include "blair.dtsi" #include "blair-qrd.dtsi" +#include "holi-qrd-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. Blair QRD"; compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; }; +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index fe3a584509fb..3927faa3efee 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -5,7 +5,6 @@ #include "display/holi-sde-display-qrd-pm6125.dtsi" #include "display/blair-sde-display-qrd.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" -#include &wcd938x_codec { cdc-vdd-rxtx-supply = <&L9A>; @@ -224,238 +223,6 @@ linux,can-disable; }; }; - - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl436186020H_3780mAh.dtsi" - #include "qg-batterydata-atl466271_3300mAh.dtsi" - }; -}; - -&pm7250b_charger { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, - <&pm7250b_vadc ADC5_USB_IN_I>, - <&pm7250b_vadc ADC5_CHG_TEMP>, - <&pm7250b_vadc ADC5_DIE_TEMP>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_SBUx>, - <&pm7250b_vadc ADC5_VPH_PWR>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, - <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, - <&pm7250b_qg PSY_IIO_TEMP>, - <&pm7250b_qg PSY_IIO_CAPACITY>, - <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, - <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, - <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, - <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, - <&pm7250b_qg PSY_IIO_CC_SOC>, - <&pm7250b_qg PSY_IIO_CURRENT_NOW>, - <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL>, - <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, - <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, - <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, - <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage", - "skin_temp", - "resistance_id", - "voltage_now", - "temp", - "capacity", - "voltage_ocv", - "voltage_avg", - "debug_battery", - "real_capacity", - "cc_soc", - "current_now", - "voltage_max", - "charge_full", - "charge_counter", - "cycle_count", - "charge_full_design", - "time_to_full_now", - "cp_parallel_mode", - "cp_parallel_output_mode", - "cp_min_icl", - "cp_switcher_en", - "cp_enable", - "cp_ilim", - "cp_die_temp"; - qcom,battery-data = <&qrd_batterydata>; - qcom,sec-charger-config = <1>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,suspend-input-on-debug-batt; - qcom,fcc-stepping-enable; - qcom,fcc-step-delay-ms = <100>; - qcom,fcc-step-size-ua = <100000>; - qcom,smb-internal-pull-kohm = <0>; - qcom,en-skin-therm-mitigation; - qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 - 7500000 7000000 6500000 6000000 5500000 5000000 4500000 - 4000000 3500000 3000000 2500000 2000000 1500000 1000000 - 500000>; -}; - -&pm7250b_qg { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, - <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, - <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, - <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, - <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; - io-channel-names = "batt-therm", - "batt-id", - "input_current_limited", - "recharge_soc", - "force_recharge", - "charge_done", - "cp_charging_enabled"; - qcom,qg-iterm-ma = <150>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; - qcom,tcss-enable; - qcom,fvss-enable; - qcom,bass-enable; - qcom,use-cp-iin-sns; - qcom,vbatt-cutoff-mv = <3400>; - qcom,vbatt-empty-mv = <3200>; - qcom,vbatt-empty-cold-mv = <3100>; - qcom,vbatt-low-mv = <3500>; - qcom,fvss-vbatt-mv = <3500>; -}; - -&pm7250b_charger { - dpdm-supply = <&qusb_phy0>; - - smb5_vbus: qcom,smb5-vbus { - regulator-name = "smb5-vbus"; - }; - - smb5_vconn: qcom,smb5-vconn { - regulator-name = "smb5-vconn"; - }; -}; - -&pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; - vbus-supply = <&smb5_vbus>; - vconn-supply = <&smb5_vconn>; - - #io-channel-cells = <1>; - io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, - <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, - <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, - <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, - <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, - <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_PR_SWAP>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_MODE>, - <&pm7250b_charger PSY_IIO_PE_START>; - io-channel-names = "pd_active", - "typec_cc_orientation", - "connector_type", - "typec_power_role", - "pd_usb_suspend_supported", - "typec_src_rp", - "pd_in_hard_reset", - "pr_current_max", - "pr_swap", - "pd_voltage_min", - "pd_voltage_max", - "real_type", - "typec_mode", - "pe_start"; -}; - -&usb0 { - extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; - - #io-channel-cells = <1>; - io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; - io-channel-names = "chg_type"; -}; - -&pm7250b_vadc { - smb1390_therm@e { - qcom,scale-fn-type = ; - }; -}; - -&pm7250b_gpios { - smb_stat { - smb_stat_default: smb_stat_default { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = <0>; - }; - }; -}; - -&qupv3_se10_i2c { - status = "ok"; - #include "smb1394.dtsi" -}; - -&smb1394 { - interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1394"; - pinctrl-names = "default"; - qcom,enable-toggle-stat; - pinctrl-0 = <&smb_stat_default>; - status = "ok"; -}; - -&smb1394_div2_cp_primary { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, - <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, - <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "die_temp", - "real_type", - "adapter_cc_mode", - "pd_current_max", - "input_current_settled", - "smb_en_mode", - "smb_en_reason"; - qcom,parallel-input-mode = <1>; /* USBIN */ - qcom,parallel-output-mode = <2>; /* VBAT */ - status = "ok"; }; &thermal_zones { @@ -574,31 +341,6 @@ trip = <&cx_trip>; cooling-device = <&modem_skin 3 3>; }; - - battery-cdev0 { - trip = <&battery_trip0>; - cooling-device = <&pm7250b_charger 6 6>; - }; - - battery-cdev1 { - trip = <&battery_trip1>; - cooling-device = <&pm7250b_charger 10 10>; - }; - - battery-cdev2 { - trip = <&battery_trip2>; - cooling-device = <&pm7250b_charger 14 14>; - }; - - battery-cdev3 { - trip = <&battery_trip3>; - cooling-device = <&pm7250b_charger 16 16>; - }; - - battery-cdev4 { - trip = <&battery_trip4>; - cooling-device = <&pm7250b_charger 18 18>; - }; }; }; diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index 7c707b10f214..4b36ba02fd8c 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -33,7 +33,7 @@ reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; - dpdm-supply = <&qusb_phy0>; + dpdm-supply = <&usb2_phy0>; qcom,usb-charger; qcom,core-clk-rate = <133333333>; @@ -54,7 +54,7 @@ reg = <0x4e00000 0xcd00>; interrupt-parent = <&intc>; interrupts = ; - usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; @@ -69,7 +69,7 @@ }; /* Primary USB port related QUSB2 PHY */ - qusb_phy0: qusb@162b000 { + usb2_phy0: hsphy@162b000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x162B000 0x114>, <0x0162A000 0x1000>; diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 28c2db11d99c..7106307562cd 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -1,6 +1,7 @@ #include "holi-audio-overlay.dtsi" #include #include +#include "holi-pm7250b.dtsi" #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-cdp-pm6125.dtsi" diff --git a/qcom/holi-mtp-pm6125-nopmi-overlay.dts b/qcom/holi-mtp-pm6125-nopmi-overlay.dts index 71fe2b7f1a8a..2a8758d4c7fe 100644 --- a/qcom/holi-mtp-pm6125-nopmi-overlay.dts +++ b/qcom/holi-mtp-pm6125-nopmi-overlay.dts @@ -1 +1,15 @@ /dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi MTP PM6125 NOPMI"; + compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/holi-mtp-pm6125-nopmi.dts b/qcom/holi-mtp-pm6125-nopmi.dts index ceaba4bf503e..8a247f3d5aaf 100644 --- a/qcom/holi-mtp-pm6125-nopmi.dts +++ b/qcom/holi-mtp-pm6125-nopmi.dts @@ -1,13 +1,15 @@ /dts-v1/; #include "holi.dtsi" -#include "holi-mtp-pm6125-nopmi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm6125.dtsi" / { model = "Qualcomm Technologies, Inc. Holi MTP PM6125 NOPMI"; compatible = "qcom,holi-mtp", "qcom,holi", "qcom,mtp"; qcom,board-id = <8 0>; qcom,pmic-id-size = <4>; - qcom,pmic-id = <0x2D 0x0 0x00 0x0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/holi-mtp-pm6125-overlay.dts b/qcom/holi-mtp-pm6125-overlay.dts index 4bd5809d06ac..d87ee2930b5d 100644 --- a/qcom/holi-mtp-pm6125-overlay.dts +++ b/qcom/holi-mtp-pm6125-overlay.dts @@ -3,6 +3,7 @@ #include "holi-pm6125-overlay.dtsi" #include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm7250b.dtsi" #include "holi-mtp-pm6125.dtsi" / { diff --git a/qcom/holi-mtp-pm6125.dts b/qcom/holi-mtp-pm6125.dts index 80145038a5ec..1cd2ecb4b406 100644 --- a/qcom/holi-mtp-pm6125.dts +++ b/qcom/holi-mtp-pm6125.dts @@ -3,6 +3,7 @@ #include "holi.dtsi" #include "holi-pm6125-overlay.dtsi" #include "holi-regulators-pm6125.dtsi" +#include "holi-mtp-pm7250b.dtsi" #include "holi-mtp-pm6125.dtsi" / { diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index f83f70ec3187..8dbc3454e44b 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -4,7 +4,6 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" -#include #include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { @@ -149,13 +148,6 @@ }; }; - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-alium-3600mah.dtsi" - #include "qg-batterydata-atl466271_3300mAh.dtsi" - #include "qg-batterydata-atl436186020H_3780mAh.dtsi" - }; - cx_ipeak_lm: cx_ipeak@3ed000 { #size-cells = <1>; compatible = "qcom,cx-ipeak-v2"; @@ -212,228 +204,4 @@ }; }; -&pm7250b_charger { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, - <&pm7250b_vadc ADC5_USB_IN_I>, - <&pm7250b_vadc ADC5_CHG_TEMP>, - <&pm7250b_vadc ADC5_DIE_TEMP>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_SBUx>, - <&pm7250b_vadc ADC5_VPH_PWR>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, - <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, - <&pm7250b_qg PSY_IIO_TEMP>, - <&pm7250b_qg PSY_IIO_CAPACITY>, - <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, - <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, - <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, - <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, - <&pm7250b_qg PSY_IIO_CC_SOC>, - <&pm7250b_qg PSY_IIO_CURRENT_NOW>, - <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL>, - <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, - <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, - <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, - <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage", - "skin_temp", - "resistance_id", - "voltage_now", - "temp", - "capacity", - "voltage_ocv", - "voltage_avg", - "debug_battery", - "real_capacity", - "cc_soc", - "current_now", - "voltage_max", - "charge_full", - "charge_counter", - "cycle_count", - "charge_full_design", - "time_to_full_now", - "cp_parallel_mode", - "cp_parallel_output_mode", - "cp_min_icl", - "cp_switcher_en", - "cp_enable", - "cp_ilim", - "cp_die_temp"; - qcom,battery-data = <&mtp_batterydata>; - qcom,sec-charger-config = <1>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,suspend-input-on-debug-batt; - qcom,fcc-stepping-enable; - qcom,fcc-step-delay-ms = <100>; - qcom,fcc-step-size-ua = <100000>; - qcom,smb-internal-pull-kohm = <0>; - qcom,en-skin-therm-mitigation; - qcom,hvdcp3-standalone-config; -}; - -&pm7250b_qg { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, - <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, - <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, - <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, - <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; - io-channel-names = "batt-therm", - "batt-id", - "input_current_limited", - "recharge_soc", - "force_recharge", - "charge_done", - "cp_charging_enabled"; - qcom,battery-data = <&mtp_batterydata>; - qcom,qg-iterm-ma = <150>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; - qcom,tcss-enable; - qcom,fvss-enable; - qcom,bass-enable; - qcom,use-cp-iin-sns; - qcom,vbatt-cutoff-mv = <3400>; - qcom,vbatt-empty-mv = <3200>; - qcom,vbatt-empty-cold-mv = <3100>; - qcom,vbatt-low-mv = <3500>; - qcom,fvss-vbatt-mv = <3500>; -}; - -&pm7250b_vadc { - smb1390_therm@e { - qcom,scale-fn-type = ; - }; -}; - -&pm7250b_gpios { - smb_stat { - smb_stat_default: smb_stat_default { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = <0>; - }; - }; -}; - -&qupv3_se10_i2c { - status = "ok"; - #include "smb1394.dtsi" -}; - -&smb1394 { - interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1394"; - pinctrl-names = "default"; - qcom,enable-toggle-stat; - pinctrl-0 = <&smb_stat_default>; - status = "ok"; -}; - -&smb1394_div2_cp_primary { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, - <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, - <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "die_temp", - "real_type", - "adapter_cc_mode", - "pd_current_max", - "input_current_settled", - "smb_en_mode", - "smb_en_reason"; - qcom,parallel-input-mode = <1>; /* USBIN */ - qcom,parallel-output-mode = <2>; /* VBAT */ - status = "ok"; -}; - #include "camera/holi-camera-sensor-pm6125-mtp.dtsi" - -&pm7250b_charger { - dpdm-supply = <&qusb_phy0>; - - smb5_vbus: qcom,smb5-vbus { - regulator-name = "smb5-vbus"; - }; - - smb5_vconn: qcom,smb5-vconn { - regulator-name = "smb5-vconn"; - }; -}; - -&pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; - vbus-supply = <&smb5_vbus>; - vconn-supply = <&smb5_vconn>; - - #io-channel-cells = <1>; - io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, - <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, - <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, - <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, - <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, - <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_PR_SWAP>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_MODE>, - <&pm7250b_charger PSY_IIO_PE_START>; - io-channel-names = "pd_active", - "typec_cc_orientation", - "connector_type", - "typec_power_role", - "pd_usb_suspend_supported", - "typec_src_rp", - "pd_in_hard_reset", - "pr_current_max", - "pr_swap", - "pd_voltage_min", - "pd_voltage_max", - "real_type", - "typec_mode", - "pe_start"; -}; - -&usb0 { - extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; - - #io-channel-cells = <1>; - io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; - io-channel-names = "chg_type"; -}; diff --git a/qcom/holi-mtp-pm7250b.dtsi b/qcom/holi-mtp-pm7250b.dtsi new file mode 100644 index 000000000000..e93422af635e --- /dev/null +++ b/qcom/holi-mtp-pm7250b.dtsi @@ -0,0 +1,232 @@ +#include +#include +#include "holi-pm7250b.dtsi" + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index f63bbc3aab21..78268f0c4837 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -1,6 +1,7 @@ #include "holi-audio-overlay.dtsi" #include #include +#include "holi-pm7250b.dtsi" #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 23fabe466f75..c16a7a01358d 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -67,3 +67,15 @@ vdd_lpi_cx-supply = <&L1A_LEVEL>; vdd_lpi_mx-supply = <&L17A_LEVEL>; }; + +&qusb_phy0 { + vdd-supply = <&L7A>; + vdda18-supply = <&L10A>; + vdda33-supply = <&L7E>; + refgen-supply = <&L4A>; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&L18A>; + core-supply = <&L4A>; +}; diff --git a/qcom/holi-pm7250b.dtsi b/qcom/holi-pm7250b.dtsi index 71fe2b7f1a8a..0ac745bb9032 100644 --- a/qcom/holi-pm7250b.dtsi +++ b/qcom/holi-pm7250b.dtsi @@ -1 +1,150 @@ -/dts-v1/; +#include +#include "pm7250b.dtsi" + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + /* Channel nodes */ + charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b_tz { + cooling-maps { + battery_cdev0 { + trip = <&pm7250b_trip0>; + cooling-device = + <&pm7250b_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + battery_cdev1 { + trip = <&pm7250b_trip1>; + cooling-device = + <&pm7250b_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + lbat0_cpu6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat0_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + lbat1_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat1_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + lbat2_cpu6 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat2_cpu7 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; +}; diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index e9999ade5618..78a61af2db8f 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -1,8 +1,6 @@ #include #include -#include -#include "pm7250b.dtsi" #include "pm6125.dtsi" #include "pmr735a.dtsi" @@ -22,42 +20,6 @@ }; }; -&pm7250b_vadc { - charger_skin_therm { - reg = ; - label = "charger_skin_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - conn_therm { - reg = ; - label = "conn_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; -}; - -&pm7250b_adc_tm { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; - - /* Channel nodes */ - charger_skin_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - conn_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - &pm6125_vadc { pinctrl-names = "default"; pinctrl-0 = < @@ -256,36 +218,6 @@ }; &thermal_zones { - chg-skin-therm-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; - wake-capable-sensor; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - conn-therm-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; - wake-capable-sensor; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - sdm-skin-therm-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -507,14 +439,3 @@ }; }; -&qusb_phy0 { - vdd-supply = <&L7A>; - vdda18-supply = <&L10A>; - vdda33-supply = <&L7E>; - refgen-supply = <&L4A>; -}; - -&usb_qmp_dp_phy { - vdd-supply = <&L18A>; - core-supply = <&L4A>; -}; diff --git a/qcom/holi-qrd-pm6125-nopmi-overlay.dts b/qcom/holi-qrd-pm6125-nopmi-overlay.dts new file mode 100644 index 000000000000..dbe9c8157115 --- /dev/null +++ b/qcom/holi-qrd-pm6125-nopmi-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi QRD PM6125 NOPMI"; + compatible = "qcom,holi-qrd", "qcom,holi", "qcom,qrd"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <0xb 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/holi-qrd-pm6125-nopmi.dts b/qcom/holi-qrd-pm6125-nopmi.dts new file mode 100644 index 000000000000..1a5cfb08078a --- /dev/null +++ b/qcom/holi-qrd-pm6125-nopmi.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-pm6125-overlay.dtsi" +#include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm6125.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi QRD PM6125 NOPMI"; + compatible = "qcom,holi-qrd", "qcom,holi", "qcom,qrd"; + qcom,board-id = <0xb 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/holi-qrd-pm6125-overlay.dts b/qcom/holi-qrd-pm6125-overlay.dts index afdb8ec9f9f0..892b4b9cd0f3 100644 --- a/qcom/holi-qrd-pm6125-overlay.dts +++ b/qcom/holi-qrd-pm6125-overlay.dts @@ -3,6 +3,7 @@ #include "holi-pm6125-overlay.dtsi" #include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm7250b.dtsi" #include "holi-qrd-pm6125.dtsi" / { diff --git a/qcom/holi-qrd-pm6125.dts b/qcom/holi-qrd-pm6125.dts index 35a00d66eb1c..35b34e7636fa 100644 --- a/qcom/holi-qrd-pm6125.dts +++ b/qcom/holi-qrd-pm6125.dts @@ -3,6 +3,7 @@ #include "holi.dtsi" #include "holi-pm6125-overlay.dtsi" #include "holi-regulators-pm6125.dtsi" +#include "holi-qrd-pm7250b.dtsi" #include "holi-qrd-pm6125.dtsi" / { diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index d53f5f26f3a2..0bd1d18cc474 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -4,7 +4,6 @@ #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-qrd-pm6125.dtsi" -#include #include "camera/holi-camera-pm6125-overlay.dtsi" &wcd938x_codec { @@ -217,12 +216,6 @@ }; }; - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl436186020H_3780mAh.dtsi" - #include "qg-batterydata-atl466271_3300mAh.dtsi" - }; - cx_ipeak_lm: cx_ipeak@3ed000 { #size-cells = <1>; compatible = "qcom,cx-ipeak-v2"; @@ -233,232 +226,6 @@ #include "camera/holi-camera-sensor-pm6125-mtp.dtsi" -&pm7250b_charger { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, - <&pm7250b_vadc ADC5_USB_IN_I>, - <&pm7250b_vadc ADC5_CHG_TEMP>, - <&pm7250b_vadc ADC5_DIE_TEMP>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_SBUx>, - <&pm7250b_vadc ADC5_VPH_PWR>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, - <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, - <&pm7250b_qg PSY_IIO_TEMP>, - <&pm7250b_qg PSY_IIO_CAPACITY>, - <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, - <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, - <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, - <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, - <&pm7250b_qg PSY_IIO_CC_SOC>, - <&pm7250b_qg PSY_IIO_CURRENT_NOW>, - <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL>, - <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, - <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, - <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, - <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, - <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, - <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage", - "skin_temp", - "resistance_id", - "voltage_now", - "temp", - "capacity", - "voltage_ocv", - "voltage_avg", - "debug_battery", - "real_capacity", - "cc_soc", - "current_now", - "voltage_max", - "charge_full", - "charge_counter", - "cycle_count", - "charge_full_design", - "time_to_full_now", - "cp_parallel_mode", - "cp_parallel_output_mode", - "cp_min_icl", - "cp_switcher_en", - "cp_enable", - "cp_ilim", - "cp_die_temp"; - qcom,battery-data = <&qrd_batterydata>; - qcom,sec-charger-config = <1>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,suspend-input-on-debug-batt; - qcom,fcc-stepping-enable; - qcom,fcc-step-delay-ms = <100>; - qcom,fcc-step-size-ua = <100000>; - qcom,smb-internal-pull-kohm = <0>; - qcom,en-skin-therm-mitigation; - qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 - 7500000 7000000 6500000 6000000 5500000 5000000 4500000 - 4000000 3500000 3000000 2500000 2000000 1500000 1000000 - 500000>; -}; - -&pm7250b_qg { - status = "ok"; - #io-channel-cells = <1>; - io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, - <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, - <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, - <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, - <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>, - <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; - io-channel-names = "batt-therm", - "batt-id", - "input_current_limited", - "recharge_soc", - "force_recharge", - "charge_done", - "cp_charging_enabled"; - qcom,qg-iterm-ma = <150>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; - qcom,tcss-enable; - qcom,fvss-enable; - qcom,bass-enable; - qcom,use-cp-iin-sns; - qcom,vbatt-cutoff-mv = <3400>; - qcom,vbatt-empty-mv = <3200>; - qcom,vbatt-empty-cold-mv = <3100>; - qcom,vbatt-low-mv = <3500>; - qcom,fvss-vbatt-mv = <3500>; -}; - -&pm7250b_charger { - dpdm-supply = <&qusb_phy0>; - - smb5_vbus: qcom,smb5-vbus { - regulator-name = "smb5-vbus"; - }; - - smb5_vconn: qcom,smb5-vconn { - regulator-name = "smb5-vconn"; - }; -}; - -&pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; - vbus-supply = <&smb5_vbus>; - vconn-supply = <&smb5_vconn>; - - #io-channel-cells = <1>; - io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, - <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, - <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, - <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, - <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, - <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_PR_SWAP>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, - <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_TYPEC_MODE>, - <&pm7250b_charger PSY_IIO_PE_START>; - io-channel-names = "pd_active", - "typec_cc_orientation", - "connector_type", - "typec_power_role", - "pd_usb_suspend_supported", - "typec_src_rp", - "pd_in_hard_reset", - "pr_current_max", - "pr_swap", - "pd_voltage_min", - "pd_voltage_max", - "real_type", - "typec_mode", - "pe_start"; -}; - -&usb0 { - extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; - - #io-channel-cells = <1>; - io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; - io-channel-names = "chg_type"; -}; - -&pm7250b_vadc { - smb1390_therm@e { - qcom,scale-fn-type = ; - }; -}; - -&pm7250b_gpios { - smb_stat { - smb_stat_default: smb_stat_default { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = <0>; - }; - }; -}; - -&qupv3_se10_i2c { - status = "ok"; - #include "smb1394.dtsi" -}; - -&smb1394 { - interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&spmi_bus>; - interrupt-names = "smb1394"; - pinctrl-names = "default"; - qcom,enable-toggle-stat; - pinctrl-0 = <&smb_stat_default>; - status = "ok"; -}; - -&smb1394_div2_cp_primary { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, - <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, - <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, - <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, - <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, - <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, - <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "die_temp", - "real_type", - "adapter_cc_mode", - "pd_current_max", - "input_current_settled", - "smb_en_mode", - "smb_en_reason"; - qcom,parallel-input-mode = <1>; /* USBIN */ - qcom,parallel-output-mode = <2>; /* VBAT */ - status = "ok"; -}; - &thermal_zones { quiet-therm-step { polling-delay-passive = <2000>; @@ -575,31 +342,6 @@ trip = <&cx_trip>; cooling-device = <&modem_skin 3 3>; }; - - battery-cdev0 { - trip = <&battery_trip0>; - cooling-device = <&pm7250b_charger 6 6>; - }; - - battery-cdev1 { - trip = <&battery_trip1>; - cooling-device = <&pm7250b_charger 10 10>; - }; - - battery-cdev2 { - trip = <&battery_trip2>; - cooling-device = <&pm7250b_charger 14 14>; - }; - - battery-cdev3 { - trip = <&battery_trip3>; - cooling-device = <&pm7250b_charger 16 16>; - }; - - battery-cdev4 { - trip = <&battery_trip4>; - cooling-device = <&pm7250b_charger 18 18>; - }; }; }; diff --git a/qcom/holi-qrd-pm7250b.dtsi b/qcom/holi-qrd-pm7250b.dtsi new file mode 100644 index 000000000000..7c1b6c9e66e5 --- /dev/null +++ b/qcom/holi-qrd-pm7250b.dtsi @@ -0,0 +1,264 @@ +#include +#include +#include "holi-pm7250b.dtsi" + +&soc { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1394_div2_cp_primary PSY_IIO_MIN_ICL>, + <&smb1394_div2_cp_primary PSY_IIO_CP_SWITCHER_EN>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ILIM>, + <&smb1394_div2_cp_primary PSY_IIO_CP_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 5000000 4500000 + 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 500000>; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1394_div2_cp_primary PSY_IIO_CP_ENABLE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1394"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&thermal_zones { + quiet-therm-step { + cooling-maps { + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; +}; diff --git a/qcom/holi-thermal-overlay-pm6125.dtsi b/qcom/holi-thermal-overlay-pm6125.dtsi index 7dd3277d4899..d69e8756cd0e 100644 --- a/qcom/holi-thermal-overlay-pm6125.dtsi +++ b/qcom/holi-thermal-overlay-pm6125.dtsi @@ -4,43 +4,7 @@ #cooling-cells = <2>; }; -&pm7250b_charger { - #cooling-cells = <2>; -}; - &thermal_zones { - socd { - cooling-maps { - socd_cpu6 { - trip = <&socd_trip>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - socd_cpu7 { - trip = <&socd_trip>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; - - pm7250b_tz { - cooling-maps { - battery_cdev0 { - trip = <&pm7250b_trip0>; - cooling-device = - <&pm7250b_charger (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; - }; - - battery_cdev1 { - trip = <&pm7250b_trip1>; - cooling-device = - <&pm7250b_charger THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - pm6125_tz { cooling-maps { trip0_cpu6 { @@ -89,46 +53,4 @@ }; }; }; - - pm7250b-bcl-lvl0 { - cooling-maps { - lbat0_cpu6 { - trip = <&b_bcl_lvl0>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - lbat0_cpu7 { - trip = <&b_bcl_lvl0>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; - - pm7250b-bcl-lvl1 { - cooling-maps { - lbat1_cpu6 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - lbat1_cpu7 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; - - pm7250b-bcl-lvl2 { - cooling-maps { - lbat2_cpu6 { - trip = <&b_bcl_lvl2>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - lbat2_cpu7 { - trip = <&b_bcl_lvl2>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; }; From a9c3e39b9e1fd6c8e22784617f002d502426b520 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 21 Jun 2021 10:30:03 -0700 Subject: [PATCH 1603/1809] ARM: dts: msm: Add device trees for sdxlemur + IPQ8074 Add device trees for sdxlemur + IPQ8074 modem variants. Change-Id: If0e2012181ffc26fc56fda51d27a4a6c94eba7e2 --- qcom/Makefile | 2 + qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dts | 12 +++++ qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 65 ++++++++++++++++++++++++ qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts | 12 +++++ 4 files changed, 91 insertions(+) create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dts create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi create mode 100644 qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts diff --git a/qcom/Makefile b/qcom/Makefile index d2843e1e640f..de2479fa0a2d 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -410,6 +410,7 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp-mbb-emmc-512mb.dtb \ sdxlemur-mtp-mbb-ntn3-pcie.dtb \ sdxlemur-mtp-mbb-pcie-ep.dtb \ + sdxlemur-mtp-mbb-pcie-ep-ipq.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-rcm-pcie-ep.dtb \ @@ -420,6 +421,7 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-v2-mtp-mbb-emmc.dtb \ sdxlemur-v2-mtp-mbb-ntn3-pcie.dtb \ sdxlemur-v2-mtp-mbb-pcie-ep.dtb \ + sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dtb \ sdxlemur-v2-mtp-mbb-pcie-rc-ep.dtb \ sdxlemur-v2-rcm-pcie-ep.dtb \ sdxlemur-v2-rcm-rc.dtb diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dts new file mode 100644 index 000000000000..54b101cea42d --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0xB010008 0x20B>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi new file mode 100644 index 000000000000..20bd6389e01c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -0,0 +1,65 @@ +#include "sdxlemur-mtp.dtsi" + +&soc { + +}; + +&chosen { + bootargs = "reboot=w"; +}; + +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; + +&mhi_device { + status = "ok"; +}; + +&mhi_net_device { + status = "ok"; +}; + +&ipa_eth_group1 { + qcom,iommu-dma = "bypass"; +}; + +&ipa_hw { + qcom,use-ipa-in-mhi-mode; + ipa_smmu_ap { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_wlan { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_uc { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_11ad { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_eth { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_eth1 { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_wlan1 { + qcom,iommu-dma = "bypass"; + }; + +}; + +&usb { + qcom,iommu-dma = "bypass"; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts new file mode 100644 index 000000000000..e638af1217be --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0xB020008 0x20B>; +}; From 3a5cd4a508caa2caa5c1dec72b9f48f91049a649 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Thu, 10 Jun 2021 23:20:20 +0530 Subject: [PATCH 1604/1809] ARM: dts: msm: Add support for usb nodes on blair Modify interrupt numbers for hs phy irq as per ipcat. Modify override sequence of hsphy as per hpg. Add interconnect data for the USB DT node and bus votes for NOM and SVS. Add pm-qos-latency node as well. Change-Id: I722c16a3ba785a77c909401b6d11c36b46b057ff --- qcom/blair-usb.dtsi | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index 4b36ba02fd8c..e7c3998a0513 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -17,8 +17,10 @@ interrupts = , , - ; - interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + , + ; + interrupt-names = "pwr_event_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, @@ -38,7 +40,23 @@ qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3_0 &bimc SLAVE_EBI>, + <&system_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ @@ -87,9 +105,9 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = - <0xe6 0x6c /* override_x0 */ - 0x0b 0x70 /* override_x1 */ - 0x17 0x74>; /* override x2 */ + <0x61 0x6c /* override_x0 */ + 0x43 0x70 /* override_x1 */ + 0x2e 0x74>; /* override x2 */ }; /* Primary USB port related QMP USB DP Combo PHY */ From 65f6ef486eb13ed43ee4d611a1a3178511bcf1ce Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 22 Jun 2021 20:09:35 +0530 Subject: [PATCH 1605/1809] ARM: dts: msm: Replace regulator value for vdd-pdphy-supply on blair This change replaces previous value of regulator of vdd-pdphy-supply node with corrrect value of regulator for blair and holi-pm6125 according to the powergrid. Change-Id: Ibba19bac485b61e226b039bdb001bffadf8d202f --- qcom/blair-atp.dtsi | 2 +- qcom/blair-cdp.dtsi | 2 +- qcom/holi-cdp-pm6125.dtsi | 2 +- qcom/holi-mtp-pm7250b.dtsi | 2 +- qcom/holi-mtp-usbc-pm6125.dtsi | 2 +- qcom/holi-qrd-pm7250b.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 7b8d509b9815..eed6ca1e6178 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -634,7 +634,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index a4432d2ea265..d8e853f82690 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -349,7 +349,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 7106307562cd..b4d9e00176d3 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -327,7 +327,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-mtp-pm7250b.dtsi b/qcom/holi-mtp-pm7250b.dtsi index e93422af635e..16aeaca4630c 100644 --- a/qcom/holi-mtp-pm7250b.dtsi +++ b/qcom/holi-mtp-pm7250b.dtsi @@ -188,7 +188,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 78268f0c4837..5c5e3d98e7aa 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -415,7 +415,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-qrd-pm7250b.dtsi b/qcom/holi-qrd-pm7250b.dtsi index 7c1b6c9e66e5..6ba5d069e30a 100644 --- a/qcom/holi-qrd-pm7250b.dtsi +++ b/qcom/holi-qrd-pm7250b.dtsi @@ -135,7 +135,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; From 226a3bef6f6262807c52d80b6f54e544be187be6 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 9 Jun 2021 17:22:39 -0700 Subject: [PATCH 1606/1809] ARM: dts: msm: Add device trees for sdxlemur M.2, Pine variants Add device tree files for sdxlemur M.2 and Pine variants. Change-Id: I589260df8477116a1715d3482dbdb4017e4e1367 --- qcom/Makefile | 5 +++++ qcom/sdxlemur-mtp-cpe-pine1x.dts | 13 ++++++++++++ qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 4 ++++ qcom/sdxlemur-mtp-cpe-pine2x.dts | 13 ++++++++++++ qcom/sdxlemur-mtp-cpe-pine2x.dtsi | 4 ++++ qcom/sdxlemur-mtp-mbb-m2-ep.dts | 13 ++++++++++++ qcom/sdxlemur-mtp-mbb-m2-ep.dtsi | 35 +++++++++++++++++++++++++++++++ qcom/sdxlemur-rcm-rc-pine1x.dts | 13 ++++++++++++ qcom/sdxlemur-rcm-rc-pine1x.dtsi | 4 ++++ qcom/sdxlemur-rcm-rc-pine2x.dts | 13 ++++++++++++ qcom/sdxlemur-rcm-rc-pine2x.dtsi | 4 ++++ 11 files changed, 121 insertions(+) create mode 100644 qcom/sdxlemur-mtp-cpe-pine1x.dts create mode 100644 qcom/sdxlemur-mtp-cpe-pine1x.dtsi create mode 100644 qcom/sdxlemur-mtp-cpe-pine2x.dts create mode 100644 qcom/sdxlemur-mtp-cpe-pine2x.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-m2-ep.dts create mode 100644 qcom/sdxlemur-mtp-mbb-m2-ep.dtsi create mode 100644 qcom/sdxlemur-rcm-rc-pine1x.dts create mode 100644 qcom/sdxlemur-rcm-rc-pine1x.dtsi create mode 100644 qcom/sdxlemur-rcm-rc-pine2x.dts create mode 100644 qcom/sdxlemur-rcm-rc-pine2x.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index d2843e1e640f..9566c435587a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -406,14 +406,19 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-mtp-cpe.dtb \ + sdxlemur-mtp-cpe-pine1x.dtb \ + sdxlemur-mtp-cpe-pine2x.dtb \ sdxlemur-mtp-mbb-emmc.dtb \ sdxlemur-mtp-mbb-emmc-512mb.dtb \ sdxlemur-mtp-mbb-ntn3-pcie.dtb \ sdxlemur-mtp-mbb-pcie-ep.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ + sdxlemur-mtp-mbb-m2-ep.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-rcm-pcie-ep.dtb \ sdxlemur-rcm-rc.dtb \ + sdxlemur-rcm-rc-pine1x.dtb \ + sdxlemur-rcm-rc-pine2x.dtb \ sdxlemur-v2-cdp.dtb \ sdxlemur-v2-mtp-mbb.dtb \ sdxlemur-v2-mtp-cpe.dtb \ diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dts b/qcom/sdxlemur-mtp-cpe-pine1x.dts new file mode 100644 index 000000000000..641531bb3ea2 --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-pine1x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 1x Pine"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x9010008 0x309>; +}; diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi new file mode 100644 index 000000000000..a7373e1f2622 --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -0,0 +1,4 @@ + +&soc { + +}; diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dts b/qcom/sdxlemur-mtp-cpe-pine2x.dts new file mode 100644 index 000000000000..e8a4eaa2005a --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-pine2x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 2x Pine"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0xA010008 0x30A>; +}; diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi new file mode 100644 index 000000000000..a7373e1f2622 --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi @@ -0,0 +1,4 @@ + +&soc { + +}; diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep.dts b/qcom/sdxlemur-mtp-mbb-m2-ep.dts new file mode 100644 index 000000000000..07688f87358c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-m2-ep.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-m2-ep.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB M2 EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x8010008 0x308>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi b/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi new file mode 100644 index 000000000000..eb895911da7c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi @@ -0,0 +1,35 @@ + +&soc { + +}; + +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + qcom,devfreq,freq-table = <50000000 192000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; diff --git a/qcom/sdxlemur-rcm-rc-pine1x.dts b/qcom/sdxlemur-rcm-rc-pine1x.dts new file mode 100644 index 000000000000..03579aab2b7e --- /dev/null +++ b/qcom/sdxlemur-rcm-rc-pine1x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-rcm-rc-pine1x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex 1x Pine"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x2010015 0x302>; +}; diff --git a/qcom/sdxlemur-rcm-rc-pine1x.dtsi b/qcom/sdxlemur-rcm-rc-pine1x.dtsi new file mode 100644 index 000000000000..a7373e1f2622 --- /dev/null +++ b/qcom/sdxlemur-rcm-rc-pine1x.dtsi @@ -0,0 +1,4 @@ + +&soc { + +}; diff --git a/qcom/sdxlemur-rcm-rc-pine2x.dts b/qcom/sdxlemur-rcm-rc-pine2x.dts new file mode 100644 index 000000000000..a56e2c446c65 --- /dev/null +++ b/qcom/sdxlemur-rcm-rc-pine2x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-rcm-rc-pine2x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex 2x Pine"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x3010015 0x303>; +}; diff --git a/qcom/sdxlemur-rcm-rc-pine2x.dtsi b/qcom/sdxlemur-rcm-rc-pine2x.dtsi new file mode 100644 index 000000000000..a7373e1f2622 --- /dev/null +++ b/qcom/sdxlemur-rcm-rc-pine2x.dtsi @@ -0,0 +1,4 @@ + +&soc { + +}; From 5413419c74890b3cb9537768bc21663b8fc86a11 Mon Sep 17 00:00:00 2001 From: Manoharan Vijaya Raghavan Date: Mon, 21 Jun 2021 09:42:18 +0530 Subject: [PATCH 1607/1809] dt-bindings: net: qrtr: Add MHI Device transport bindings The QRTR MHI DEV driver acts as a transport driver for a device that is configured as a pcie endpoint. Document the bindings for this qrtr transport. commit dt-bindings: net: qrtr: Add MHI Device transport bindings (a5dbed3f467c79). Change-Id: I03a27877b74ba11a60f68c81e43d3c29db346e36 --- bindings/net/qrtr-mhi-dev.txt | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 bindings/net/qrtr-mhi-dev.txt diff --git a/bindings/net/qrtr-mhi-dev.txt b/bindings/net/qrtr-mhi-dev.txt new file mode 100644 index 000000000000..9d15e9d6fe9f --- /dev/null +++ b/bindings/net/qrtr-mhi-dev.txt @@ -0,0 +1,30 @@ +QTI QRTR MHI Dev transport binding + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,qrtr-mhi-dev" + +- qcom,net-id: + Usage: optional + Value type: + Definition: indicates what subnet this transport belongs to. Should be + passed into the qrtr core logic to determine if forwarding + is needed on this endpoint. + +- qcom,low-latency: + Usage: optional + Value type: + Definition: indicates whether this transport receiving thread needs to + be set to realtime priority for enhanced performance. + += EXAMPLE +The following example represents the qrtr mhi dev transport node on a device +configured as a pcie endpoint and needs to forward data from the host to a +modem co-processor. + + qcom,mhi_dev_qrtr { + compatible = "qcom,qrtr-mhi-dev"; + qcom,net-id = <3>; + qcom,low-latency; + }; From efeb41aceca7059c4dd59b51a2148482f9cf35dc Mon Sep 17 00:00:00 2001 From: Manoharan Vijaya Raghavan Date: Thu, 24 Jun 2021 16:57:34 +0530 Subject: [PATCH 1608/1809] ARM: dts: msm: Add QRTR MHI DEV device for sdxlemur Add the QRTR MHI DEV transport to enable communication over pcie from the device to the host. Change-Id: I8333e3d84e129bed5c88b53f9219dadfa18b61e5 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a130619ee521..cb7e2ddd9888 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -797,6 +797,11 @@ }; }; + qcom,mhi_dev_qrtr { + compatible = "qcom,qrtr-mhi-dev"; + qcom,net-id = <3>; + }; + qcom,glinkpkt { compatible = "qcom,glinkpkt"; From fba2fdb4a1233577d885af2496d610a308962989 Mon Sep 17 00:00:00 2001 From: Sayantan Majumder Date: Thu, 10 Jun 2021 20:58:33 -0700 Subject: [PATCH 1609/1809] Revert "ARM: dts: msm: Add video support for KODIAC-IOT target" This reverts commit 5beba6a9ccf12610dfad815eb33009b29ce7b7c0. Change-Id: I85287c591cf689e3811289acf45f3d030c3add13 --- bindings/media/video/msm-vidc.txt | 2 +- qcom/yupik-iot.dtsi | 7 ------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 603d035bc852..354e1f376c54 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -15,7 +15,7 @@ Required properties: - "qcom,sm6150-vidc" : Invokes driver specific data for SA6155. - "qcom,scuba-vidc" : Invokes driver specific data for SCUBA. - "qcom,monaco-vidc" : Invokes driver specific data for MONACO. - - "qcom,qcm6490-vidc" : Invokes driver specific data for YUPIK-IOT. + Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL - reg : offset and length of the register set for the device. diff --git a/qcom/yupik-iot.dtsi b/qcom/yupik-iot.dtsi index bbe7eca0a22d..f069e51e512b 100644 --- a/qcom/yupik-iot.dtsi +++ b/qcom/yupik-iot.dtsi @@ -6,13 +6,6 @@ qcom,msm-id = <497 0x10000>; }; -&soc { - msm_vidc: qcom,vidc { - compatible = "qcom,msm-vidc", "qcom,qcm6490-vidc"; - status = "ok"; - }; -}; - &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, From 1e6ff726318c46fd8717ade912232154041f43e0 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 28 Jun 2021 12:57:26 +0530 Subject: [PATCH 1610/1809] ARM: dts: msm: Disable NAP power feature for blair GPU There is no major power benefit with the GPU NAP feature. Hence disable it to avoid frequent state transitions. Change-Id: I7fa50d26db95f70699e4fe2381bca0b537b2a5aa --- qcom/blair.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 32c9b20fb91e..ad9bd57ac690 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3438,6 +3438,7 @@ &msm_gpu { qcom,chipid = <0x06010901>; vdd-parent-supply = <&S8A_LEVEL>; + qcom,no-nap; /delete-node/qcom,gpu-pwrlevel-bins; From dd31c83ad7c3cbe228739f75ce9c936ff06c5469 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Thu, 10 Jun 2021 12:24:45 +0530 Subject: [PATCH 1611/1809] ARM: dts: msm: Enable cxipeak support for BLAIR Enable cxipeak cooling device node for BLAIR and holi-pm6125 variant. Change-Id: I2f9f7d146724b2f937c5cb83d798385787f81de1 --- qcom/blair.dtsi | 4 ++++ qcom/holi-thermal-overlay-pm6125.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 32c9b20fb91e..21eecd0cc0e4 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3768,6 +3768,10 @@ qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; }; + + cxip-cdev@3ed000 { + status = "ok"; + }; }; #include "msm-rdbg.dtsi" diff --git a/qcom/holi-thermal-overlay-pm6125.dtsi b/qcom/holi-thermal-overlay-pm6125.dtsi index d69e8756cd0e..9a9608ce8138 100644 --- a/qcom/holi-thermal-overlay-pm6125.dtsi +++ b/qcom/holi-thermal-overlay-pm6125.dtsi @@ -4,6 +4,10 @@ #cooling-cells = <2>; }; +&cxip_cdev { + status = "ok"; +}; + &thermal_zones { pm6125_tz { cooling-maps { From 29d6899f3d9d003eae0079fb6c2c99283ca00550 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Thu, 24 Jun 2021 19:21:01 +0800 Subject: [PATCH 1612/1809] ARM: dts: msm: Add a new property for Blair touch Add a new property for Blair QRD touch. Change-Id: I3322339fd5868ec5a953fdeb93274ddea476e7de --- qcom/blair-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index d49e3fe5464c..51704ee5fa36 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -461,6 +461,7 @@ focaltech,irq-gpio = <&tlmm 22 0x2008>; focaltech,max-touch-number = <5>; focaltech,display-coords = <0 0 1080 2340>; + focaltech,power-always-on; vcc_i2c-supply = <&L9A>; vdd-supply = <&touch_avdd>; From 8e22b3c2371d078cdf37261092fe808f2a1ab04b Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 21 Jun 2021 00:22:54 +0530 Subject: [PATCH 1613/1809] ARM: dts: msm: Add support for mpm interrupts on blair Add support for mpm interrupts on blair. These interrupts are mapped to corresponding mpm pins and are needed for wakeup events in case of xo shutdown. Change-Id: I28806e252a243461a25b74a5b230d0ca4db3eb43 --- qcom/blair-usb.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index e7c3998a0513..ca58a3fe8b05 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -15,10 +15,10 @@ #size-cells = <1>; ranges; - interrupts = , - , - , - ; + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 93 IRQ_TYPE_EDGE_RISING>, + <&wakegic 94 IRQ_TYPE_EDGE_RISING>; interrupt-names = "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; From 46d76ccc92a9b6fe69426fa8687d56ea6139a7bb Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 16 Jun 2021 18:23:04 +0800 Subject: [PATCH 1614/1809] ARM: dts: msm: correct l2_cache dump size on blair Correct l2_cache memory dump size on blair. Change-Id: I288543d05c2abfa7f5bad001e25f7ffc8593eabe --- qcom/blair.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c894e2a21202..b6e8479516be 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -775,12 +775,12 @@ }; l2_cache102 { - qcom,dump-size = <0x90100>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc6>; }; l2_cache103 { - qcom,dump-size = <0x90100>; + qcom,dump-size = <0x48100>; qcom,dump-id = <0xc7>; }; From 75dc7e84281a50c320103fb647449b5c5416dd9c Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 22 Jun 2021 20:09:35 +0530 Subject: [PATCH 1615/1809] ARM: dts: msm: Replace regulator value for vdd-pdphy-supply on blair This change replaces previous value of regulator of vdd-pdphy-supply node with corrrect value of regulator for blair and holi-pm6125 according to the powergrid. Change-Id: Ibba19bac485b61e226b039bdb001bffadf8d202f --- qcom/blair-atp.dtsi | 2 +- qcom/blair-cdp.dtsi | 2 +- qcom/holi-cdp-pm6125.dtsi | 2 +- qcom/holi-mtp-pm7250b.dtsi | 2 +- qcom/holi-mtp-usbc-pm6125.dtsi | 2 +- qcom/holi-qrd-pm7250b.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 7b8d509b9815..eed6ca1e6178 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -634,7 +634,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index a4432d2ea265..d8e853f82690 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -349,7 +349,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 7106307562cd..b4d9e00176d3 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -327,7 +327,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-mtp-pm7250b.dtsi b/qcom/holi-mtp-pm7250b.dtsi index e93422af635e..16aeaca4630c 100644 --- a/qcom/holi-mtp-pm7250b.dtsi +++ b/qcom/holi-mtp-pm7250b.dtsi @@ -188,7 +188,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 78268f0c4837..5c5e3d98e7aa 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -415,7 +415,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; diff --git a/qcom/holi-qrd-pm7250b.dtsi b/qcom/holi-qrd-pm7250b.dtsi index 7c1b6c9e66e5..6ba5d069e30a 100644 --- a/qcom/holi-qrd-pm7250b.dtsi +++ b/qcom/holi-qrd-pm7250b.dtsi @@ -135,7 +135,7 @@ }; &pm7250b_pdphy { - vdd-pdphy-supply = <&L3A>; + vdd-pdphy-supply = <&L7E>; vbus-supply = <&smb5_vbus>; vconn-supply = <&smb5_vconn>; From bbfeb2952a94caf57dd8dd3775604ae86f93adc1 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 15 Jun 2021 18:08:56 +0530 Subject: [PATCH 1616/1809] ARM: dts: msm: Give Blair its own MPM pins mapping configuration Currently both Blair and Holi use the same MPM pins mapping configuration as they use the same compatible string. USB PHY has a different GIC IRQ on Blair, so different MPM configuration is required. Change-Id: I83b79ac2711dd0b6cb871529b7a14c3d9a8213f9 --- bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/blair.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index dcce6028e872..a3c194ce837e 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -28,6 +28,7 @@ Properties: "qcom,mpm-gic-sdxnightjar" "qcom,mpm-gic-monaco" "qcom,mpm-gic-qcs405" + "qcom,mpm-gic-blair" - interrupts: Usage: required diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c894e2a21202..a314de993d86 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -973,7 +973,7 @@ }; wakegic: wake-gic { - compatible = "qcom,mpm-gic-holi", "qcom,mpm"; + compatible = "qcom,mpm-gic-blair", "qcom,mpm"; interrupts = ; reg = <0x45f01b8 0x1000>, <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ From 870dd65d4e6acb3da708ba0a38a3892962c6f9fa Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 21 Jun 2021 00:22:54 +0530 Subject: [PATCH 1617/1809] ARM: dts: msm: Add support for mpm interrupts on blair Add support for mpm interrupts on blair. These interrupts are mapped to corresponding mpm pins and are needed for wakeup events in case of xo shutdown. Change-Id: I28806e252a243461a25b74a5b230d0ca4db3eb43 --- qcom/blair-usb.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index 4b36ba02fd8c..acf6bfd2962b 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -15,10 +15,12 @@ #size-cells = <1>; ranges; - interrupts = , - , - ; - interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 93 IRQ_TYPE_EDGE_RISING>, + <&wakegic 94 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, From ae680eebea6966db291389e2fb1b268b03289073 Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Tue, 1 Jun 2021 10:21:23 +0800 Subject: [PATCH 1618/1809] ARM: dts: msm: Include camera sensor dtsi for blair QRD Include camera sensor dtsi for blair QRD CRs-Fixed: 2958083 External Impact: No. Change-Id: Iab5458dc1ddf6ca0cf6e041b5fa2c04625481123 --- qcom/blair-qrd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 3927faa3efee..d49e3fe5464c 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -476,3 +476,5 @@ &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; + +#include "camera/blair-camera-sensor-qrd.dtsi" From 6f86729bdf65f1c28e1ba78bcf6607db039485b9 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 28 Jun 2021 00:15:43 +0530 Subject: [PATCH 1619/1809] ARM: dts: msm: Add skin and mmw thermal config for YUPIK Add skin and mmw thermal zone config rules for YUPIK as per recommondation. Change-Id: Iec03b991ab1036afa742e18bed622058aaab6616 --- qcom/yupik-qrd.dtsi | 180 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 159 insertions(+), 21 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 55329158acf7..20f36edecfff 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -273,20 +273,20 @@ (QMI_MODEM_INST_ID+QMI_PA)>; trips { sub6_pa1_trip0: sub6-pa1-trip0 { - temperature = <43000>; + temperature = <46000>; hysteresis = <4000>; type = "passive"; }; sub6_pa1_trip1: sub6-pa1-trip1 { - temperature = <45000>; + temperature = <47000>; hysteresis = <4000>; type = "passive"; }; sub6_pa1_trip2: sub6-pa1-trip2 { - temperature = <55000>; - hysteresis = <5000>; + temperature = <57000>; + hysteresis = <4000>; type = "passive"; }; }; @@ -317,20 +317,20 @@ (QMI_MODEM_INST_ID+QMI_PA_1)>; trips { sub6_pa2_trip0: sub6-pa2-trip0 { - temperature = <42000>; + temperature = <46000>; hysteresis = <4000>; type = "passive"; }; sub6_pa2_trip1: sub6-pa2-trip1 { - temperature = <44000>; + temperature = <47000>; hysteresis = <4000>; type = "passive"; }; sub6_pa2_trip2: sub6-pa2-trip2 { - temperature = <55000>; - hysteresis = <5000>; + temperature = <57000>; + hysteresis = <4000>; type = "passive"; }; }; @@ -360,30 +360,24 @@ thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; trips { - quiet_skin_trip0: quiet-skin-trip0 { - temperature = <43000>; - hysteresis = <4000>; - type = "passive"; - }; - quiet_batt_trip0: quiet-batt-trip0 { temperature = <44000>; hysteresis = <2000>; type = "passive"; }; - quiet_skin_trip1: quiet-skin-trip1 { - temperature = <45000>; - hysteresis = <4000>; - type = "passive"; - }; - quiet_batt_trip1: quiet-batt-trip1 { temperature = <46000>; hysteresis = <2000>; type = "passive"; }; + quiet_skin_trip0: quiet-skin-trip0 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + quiet_batt_trip2: quiet-batt-trip2 { temperature = <48000>; hysteresis = <2000>; @@ -396,6 +390,12 @@ type = "passive"; }; + quiet_skin_trip1: quiet-skin-trip1 { + temperature = <49000>; + hysteresis = <4000>; + type = "passive"; + }; + quiet_apc_trip: quiet-apc-trip { temperature = <50000>; hysteresis = <0>; @@ -419,6 +419,12 @@ hysteresis = <5000>; type = "passive"; }; + + quiet_skin_trip2: quiet-skin-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; }; cooling-maps { @@ -464,7 +470,7 @@ }; skin-cdev2 { - trip = <&quiet_cx_trip>; + trip = <&quiet_skin_trip2>; cooling-device = <&modem_skin 3 3>; }; @@ -489,6 +495,138 @@ }; }; }; + + modem-mmw-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + mmw_pa1_trip0: mmw-pa1-trip0 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip1: mmw-pa1-trip1 { + temperature = <51000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip2: mmw-pa1-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin1_cdev0 { + trip = <&mmw_pa1_trip0>; + cooling-device = <&modem_mmw_skin1 1 1>; + }; + + mmw_skin1_cdev1 { + trip = <&mmw_pa1_trip1>; + cooling-device = <&modem_mmw_skin1 2 2>; + }; + + mmw_skin1_cdev2 { + trip = <&mmw_pa1_trip2>; + cooling-device = <&modem_mmw_skin1 3 3>; + }; + }; + }; + + modem-mmw-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + mmw_pa2_trip0: mmw-pa2-trip0 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip1: mmw-pa2-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip2: mmw-pa2-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin2_cdev0 { + trip = <&mmw_pa2_trip0>; + cooling-device = <&modem_mmw_skin2 1 1>; + }; + + mmw_skin2_cdev1 { + trip = <&mmw_pa2_trip1>; + cooling-device = <&modem_mmw_skin2 2 2>; + }; + + mmw_skin2_cdev2 { + trip = <&mmw_pa2_trip2>; + cooling-device = <&modem_mmw_skin2 3 3>; + }; + }; + }; + + modem-mmw-pa3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + mmw_pa3_trip0: mmw-pa3-trip0 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip1: mmw-pa3-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip2: mmw-pa3-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin0_cdev0 { + trip = <&mmw_pa3_trip0>; + cooling-device = <&modem_mmw_skin0 1 1>; + }; + + mmw_skin0_cdev1 { + trip = <&mmw_pa3_trip1>; + cooling-device = <&modem_mmw_skin0 2 2>; + }; + + mmw_skin0_cdev2 { + trip = <&mmw_pa3_trip2>; + cooling-device = <&modem_mmw_skin0 3 3>; + }; + }; + }; }; &apps_rsc { From a47936adaf0709e75b46ef0e90a86eb0574351e2 Mon Sep 17 00:00:00 2001 From: Madhur Rawat Date: Wed, 16 Jun 2021 12:22:09 +0530 Subject: [PATCH 1620/1809] ARM: dts: msm: Update dcc registers for blair Add and update dcc debug registers for blair Change-Id: I45bcb6535cc9beef9e53a3cae5bd7d5a44cb175c --- qcom/blair.dtsi | 205 ++++++++++++++++++++---------------------------- 1 file changed, 85 insertions(+), 120 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c209dc1303c2..661933481c21 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1810,7 +1810,6 @@ , , , - , , , , @@ -1820,7 +1819,6 @@ , , , - , , , , @@ -2005,57 +2003,41 @@ , , , - , - , + + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , - , + , , - , - , - , - , + , + , + , , - , - , + , , - , - , + , , - , + , + , + , , , - , , - , - , , - , - , , - , , , , @@ -2064,102 +2046,85 @@ , , , - , - , - , - , - , , - , - , - , - , - , - , - , - , - , - , , , - , - , - , , , , , , , - , - , - , - , - , - , - , - , - , - , - , - , - , , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; From f6536b1d6a52af7e944c5196c7dca39618ccd213 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 29 Jun 2021 12:02:00 +0530 Subject: [PATCH 1621/1809] ARM: dts: msm: Add disable L1 quirk in HS mode for blair Some platforms do not support l1 in HS mode and therefore need to disable this feature through dt. This change adds quirk snps,usb2_l1_disable in order to avoid this. Change-Id: I5f06fed7e3f70d22d7f5099611f647b042d38d17 --- qcom/blair-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index ca58a3fe8b05..2f1a6b58e2ef 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -77,6 +77,7 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,is-utmi-l1-suspend; + snps,usb2-l1-disable; snps,dis_u2_susphy_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; From f46e48f2da69931f00be63865a543801f806ac51 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 29 Jun 2021 11:03:15 -0700 Subject: [PATCH 1622/1809] dt-bindings: Add optional EUD parameter for interrupt mask The EUD driver defaults to using INT1 as the interrupt mask for the apps processor. However, on modem, this interrupt does not serve the apps processor, so add a new optional device tree binding which can specify the offset of the interrupt mask used for the apps processor and override the default. Change-Id: Id73336dcf737945effc254d3179bbfe354a5026b --- bindings/soc/qcom/qcom,msm-eud.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/soc/qcom/qcom,msm-eud.yaml b/bindings/soc/qcom/qcom,msm-eud.yaml index 743604ae6577..c61501ffb51a 100644 --- a/bindings/soc/qcom/qcom,msm-eud.yaml +++ b/bindings/soc/qcom/qcom,msm-eud.yaml @@ -40,6 +40,11 @@ properties: Value type: Definition: Must be "eud_irq" + interrupt-mask: + Usage: optional + Value type: + Definition: offset of the interrupt mask for apps if not INT1 + reg-names: Usage: optional Value type: From ea27d6f0cb4c4b8f17da36324fb5d8826d356cef Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 29 Jun 2021 11:04:58 -0700 Subject: [PATCH 1623/1809] ARM: dts: msm: Add interrupt mask offset for EUD for sdxlemur The EUD driver defaults to using INT1 for its interrupt mask. However, on sdxlemur, this interrupt does not serve the apps processor, so add the offset of the interrupt mask to the device tree entry for EUD on sdxlemur. Change-Id: I48e36cfead5f3b47ae97f4088cd019994654309e --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a130619ee521..a2908fa370f1 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -412,6 +412,7 @@ interrupt-names = "eud_irq"; interrupt-parent = <&pdc>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-mask = <0x30>; reg = <0xff0000 0x2000>, <0xff2000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; From c68f3e7b33137a21b3186091548b04d18e706b66 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 10 Jun 2021 16:37:54 +0530 Subject: [PATCH 1624/1809] Revert "ARM: dts: msm: Add UFS ICE HW controlled clock for yupik" This reverts commit b97920307196dc2c1c17e16eda49d7c19389693e. Dynamic clk gating requires to be disabled post Auto Hibernate to avoid ice clk gating by dcg. Change-Id: I7684ce7b6c314132616e4826d9d14cc438514e81 --- qcom/yupik.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 55dc0da899a5..779cd92d2f55 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -2895,7 +2895,6 @@ "iface_clk", "core_clk_unipro", "core_clk_ice", - "core_clk_ice_hw_ctl", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", @@ -2906,7 +2905,6 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, @@ -2917,7 +2915,6 @@ <0 0>, <75000000 300000000>, <75000000 300000000>, - <75000000 300000000>, <0 0>, <0 0>, <0 0>, From 068c4de2994b07b34d6c0567ce54ca8c19013305 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 29 Jun 2021 21:14:03 +0530 Subject: [PATCH 1625/1809] ARM: dts: msm: Update spmi debugfs nodes for yupik with PM7250B Update spmi and glink debugfs nodes for yupik with PM7250B with correct SIDs used for PM7250B. Change-Id: I2a6c49a6fd1ed563d9a85b4b23041085562a0e30 --- qcom/yupik-idp-pm7250b.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/yupik-idp-pm7250b.dtsi b/qcom/yupik-idp-pm7250b.dtsi index 50169462583e..f7ca8842dab9 100644 --- a/qcom/yupik-idp-pm7250b.dtsi +++ b/qcom/yupik-idp-pm7250b.dtsi @@ -32,6 +32,42 @@ }; }; +&spmi_debug_bus { + qcom,pm8350b-debug@3 { + status = "disabled"; + }; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7250b-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&spmi_glink_debug { + spmi@0 { + qcom,pm8350b-debug@3 { + status = "disabled"; + }; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + qcom,can-sleep; + }; + }; +}; + &qupv3_se9_i2c { status = "ok"; qcom,clk-freq-out = <1000000>; From c9374253685c704b005cf10c99e7417bd8c7afee Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 19 Mar 2021 17:16:44 +0800 Subject: [PATCH 1626/1809] ARM: dts: msm: Enable QPIC display for sdxlemur Enable QPIC display for sdxlemur. Change-Id: Ifc44e77d350a41f82d5b1f4aa97adc882668b260 --- qcom/sdxlemur-mtp-mbb.dts | 1 + qcom/sdxlemur-pinctrl.dtsi | 133 +++++++++++++++++++++++++++++++++++++ 2 files changed, 134 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index 2068bdaee56f..3cd714502b6b 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -6,6 +6,7 @@ #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" +#include "display/sdxlemur-qpic-display.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index d638723e2a75..60534b7cb2bb 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -1210,6 +1210,139 @@ }; }; }; + + qpic_cs_active: qpic_cs_active { + mux { + pins = "gpio90"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio90"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_cs_sleep: qpic_cs_sleep { + mux { + pins = "gpio90"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_te_active: qpic_te_active { + mux { + pins = "gpio84"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio84"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_te_sleep: qpic_te_sleep { + mux { + pins = "gpio84"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio84"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_rs_active: qpic_rs_active { + mux { + pins = "gpio85"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio85"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_rs_sleep: qpic_rs_sleep { + mux { + pins = "gpio85"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_ad_active: qpic_ad_active { + mux { + pins = "gpio89"; + function = "ebi2_a"; + }; + + config { + pins = "gpio89"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_ad_sleep: qpic_ad_sleep { + mux { + pins = "gpio89"; + function = "ebi2_a"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + qpic_bl_active: qpic_bl_active { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + output-high; + }; + }; + + qpic_bl_sleep: qpic_bl_sleep { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + output-low; + }; + }; + wcd9xxx_intr { wcd_intr_default: wcd_intr_default { mux { From 857ecdfb96925b09ea8c48f350c3633b11ac4a64 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Fri, 18 Jun 2021 20:11:29 +0530 Subject: [PATCH 1627/1809] ARM: dts: msm: Add disable L1 quirk in HS mode for sdxnightjar Some platforms do not support L1 in HS mode and therefore need to disable this feature through dt. This change adds quirk snps,usb2_l1_disable in order to avoid this. Change-Id: Ifcafdfc51cc294d07e08192d96185cb772f06c5f --- qcom/sdxnightjar-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index f5ea811a1b1a..22299c20d4b3 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -65,6 +65,7 @@ snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,bus-suspend-enable; + snps,usb2-l1-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; xhci-imod-value = <4000>; From 29a434c807f353959bcb1d5d9cd043ede58b52b3 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 10 Jun 2021 20:36:22 +0530 Subject: [PATCH 1628/1809] ARM: dts: msm: Add FnR stats support flag for holi target Holi target dont support FnR stats. Add entry to specify. Change-Id: I64298cc8f84ed9a3a6b03860aa9148676b1e4db7 --- bindings/platform/msm/ipa.txt | 2 ++ qcom/holi.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index a39d3d334f1e..15fbddc0dc9a 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -141,6 +141,8 @@ memory allocation over a PCIe bridge is supported or not in this target. - qcom,bw-monitor-supported: Boolean context flag to indicate BW monitor feature support. +- qcom,fnr-stats-not-supported: Boolean context flag to indicate FnR stats query support + is present or not for the target. IPA pipe sub nodes (A2 static pipes configurations): diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 5e70324b441b..9d12ad9d5210 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -3254,6 +3254,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-endp-delay-wa; + qcom,fnr-stats-not-supported; qcom,tx-wrapper-cache-max-size = <400>; clock-names = "core_clk"; clocks = <&rpmcc RPM_SMD_IPA_CLK>; From 2f99d94eb9137d6141c3c5159e6a8fd07d144119 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 5 Jul 2021 16:42:32 +0530 Subject: [PATCH 1629/1809] ARM: dts: msm: Correct #address-cells property for PM6125 Correct #address-cells property for SPMI SID 1 of PM6125 to ensure module addresses under it can be read correctly. Change-Id: I5380640c061715be34f6afc24925d117b51e0b32 --- qcom/pm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index 0d412a640202..28ac8c196c2e 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -132,7 +132,7 @@ qcom,pm6125@1 { compatible ="qcom,spmi-pmic"; reg = <0x1 0x0>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; pm6125_pwm: qcom,pwms@b300 { From b53b6145d062da26010ad2819472febe6569a7b1 Mon Sep 17 00:00:00 2001 From: Madhur Rawat Date: Fri, 2 Jul 2021 08:21:35 +0530 Subject: [PATCH 1630/1809] ARM: dts: msm: Add APPS_APM_STATUS register for blair Add APSS_APM_STATUS dcc debug register list for blair Change-Id: I31d38cfd77d440691308db73a1df56b81c93c20c --- qcom/blair.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 661933481c21..3d0bf3c62134 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1684,6 +1684,7 @@ , , , + , , , , @@ -1983,6 +1984,7 @@ , , , + , , , , From c1da1df3eef131c63d0f85b81c8acaa1c22cfce9 Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Wed, 7 Jul 2021 15:45:52 +0800 Subject: [PATCH 1631/1809] ARM: dts: msm: rename sound card for QRD blair Rename sound card to pick proper acdb files for QRD blair. Change-Id: I0840d0665a23e3098d3f81b32fedf33799488303 --- qcom/blair-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 51704ee5fa36..197fa0514ef7 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -148,7 +148,7 @@ }; &holi_snd { - qcom,model = "holi-qrd-snd-card"; + qcom,model = "holi-qrdsku1-snd-card"; qcom,sku-model = "holi-qrdsku1-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; From a7fbbfd10bae0537b7d6f19a89502fca0b9d3f13 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Thu, 27 May 2021 21:43:19 +0530 Subject: [PATCH 1632/1809] ARM: dts: msm: Update BCL thermal mitigation config for HOLI Update BCL thermal zone config with cdsp, gpu and modem cooling devices for HOLI and its variants. Change-Id: Iba8fa54af0948543527b4de0acc87cac0348be60 --- qcom/holi-pm7250b.dtsi | 39 ++++++++++++----- qcom/holi-thermal-overlay.dtsi | 80 ++++++++++++++++++++++++---------- 2 files changed, 86 insertions(+), 33 deletions(-) diff --git a/qcom/holi-pm7250b.dtsi b/qcom/holi-pm7250b.dtsi index 0ac745bb9032..8b63e946a9d3 100644 --- a/qcom/holi-pm7250b.dtsi +++ b/qcom/holi-pm7250b.dtsi @@ -108,6 +108,11 @@ pm7250b-bcl-lvl0 { cooling-maps { + lbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + lbat0_cpu6 { trip = <&b_bcl_lvl0>; cooling-device = <&cpu6_isolate 1 1>; @@ -117,33 +122,45 @@ trip = <&b_bcl_lvl0>; cooling-device = <&cpu7_isolate 1 1>; }; + + lbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; pm7250b-bcl-lvl1 { cooling-maps { - lbat1_cpu6 { + lbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - lbat1_cpu7 { + lbat_cdsp1 { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + lbat0_cpu4 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + lbat0_cpu5 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu5_isolate 1 1>; }; }; }; pm7250b-bcl-lvl2 { cooling-maps { - lbat2_cpu6 { + lbat_cdsp2 { trip = <&b_bcl_lvl2>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - lbat2_cpu7 { - trip = <&b_bcl_lvl2>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; }; }; diff --git a/qcom/holi-thermal-overlay.dtsi b/qcom/holi-thermal-overlay.dtsi index 1eaf50bcf0f6..70e256fa143a 100644 --- a/qcom/holi-thermal-overlay.dtsi +++ b/qcom/holi-thermal-overlay.dtsi @@ -149,6 +149,11 @@ pm7250b-bcl-lvl0 { cooling-maps { + lbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + lbat0_cpu6 { trip = <&b_bcl_lvl0>; cooling-device = <&cpu6_isolate 1 1>; @@ -158,33 +163,45 @@ trip = <&b_bcl_lvl0>; cooling-device = <&cpu7_isolate 1 1>; }; + + lbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; pm7250b-bcl-lvl1 { cooling-maps { - lbat1_cpu6 { + lbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - lbat1_cpu7 { + lbat_cdsp1 { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + lbat0_cpu4 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + lbat0_cpu5 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu5_isolate 1 1>; }; }; }; pm7250b-bcl-lvl2 { cooling-maps { - lbat2_cpu6 { + lbat_cdsp2 { trip = <&b_bcl_lvl2>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - lbat2_cpu7 { - trip = <&b_bcl_lvl2>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; }; }; @@ -192,6 +209,11 @@ pm6150l-bcl-lvl0 { disable-thermal-zone; cooling-maps { + vph_modem { + trip = <&l_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + vph_cpu6 { trip = <&l_bcl_lvl0>; cooling-device = <&cpu6_isolate 1 1>; @@ -201,20 +223,38 @@ trip = <&l_bcl_lvl0>; cooling-device = <&cpu7_isolate 1 1>; }; + + vph_cdsp0 { + trip = <&l_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + }; }; pm6150l-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&l_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - vph_cpu7 { + vph_cdsp1 { trip = <&l_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + lbat0_cpu4 { + trip = <&l_bcl_lvl1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + lbat0_cpu5 { + trip = <&l_bcl_lvl1>; + cooling-device = <&cpu5_isolate 1 1>; }; }; }; @@ -222,14 +262,10 @@ pm6150l-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_cdsp2 { trip = <&l_bcl_lvl2>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&l_bcl_lvl2>; - cooling-device = <&cpu7_isolate 1 1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; }; }; From ab9794285baab803628bead3a15d5bd568d63d7b Mon Sep 17 00:00:00 2001 From: Paul Zhang Date: Mon, 28 Jun 2021 15:59:47 +0800 Subject: [PATCH 1633/1809] ARM: dts: msm: set need unvote flag 0 Don't unvote the cnss regulator. Change-Id: Icbd4d8012a213c4e048ab1b06a900226a8e0e9fe --- qcom/sdxlemur-cnss.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi index 5fe1c865efd8..8b2973d86491 100644 --- a/qcom/sdxlemur-cnss.dtsi +++ b/qcom/sdxlemur-cnss.dtsi @@ -32,11 +32,11 @@ cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S7B>; - qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>; + qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 0>; vdd-wlan-rfa1-supply = <&S4B>; - qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>; + qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 0>; vdd-wlan-rfa2-supply = <&S2B>; - qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 0>; interconnects = <&system_noc MASTER_PCIE_0 &system_noc SLAVE_SNOC_MEM_NOC_GC>, From f65991268da16447f49bf62aa8ff4999c1ec352c Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 30 Jun 2021 08:51:37 +0530 Subject: [PATCH 1634/1809] ARM: dts: msm: Add support to sync charger/qg probe with vadc Observing probe defer and other related error to happen when Charger or QG tries to probe before vadc. Fix this by adding a dependency in DT for these drivers with "*-supply". Change-Id: Ic4a7917a7aa84503dc9dcb8bc789768552077106 --- qcom/pm7250b.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 32d662ff76df..e423f53fd9eb 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -22,6 +22,7 @@ pm7250b_charger: qcom,qpnp-smb5 { compatible = "qcom,pm7250b-smb5"; + depends-on-supply = <&pm7250b_vadc>; #address-cells = <1>; #size-cells = <0>; #cooling-cells = <2>; @@ -181,6 +182,7 @@ pm7250b_qg: qpnp,qg { compatible = "qcom,pm7250b-qg"; + depends-on-supply = <&pm7250b_vadc>; #address-cells = <1>; #size-cells = <0>; From 110c94ddb9611bc1c721459d545ad24f0fd3884d Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Jul 2021 15:01:19 +0530 Subject: [PATCH 1635/1809] ARM: dts: msm: Update mode threshold current of L6C of yupik Update mode threshold current of LDO6C of yupik to match the threshold value expected by the client for HPM. Change-Id: I60536af368d124eca816067471ed53bce7abf453 --- qcom/yupik-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index ea18346f0255..d3964932dad7 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -656,7 +656,7 @@ qcom,supported-modes = ; - qcom,mode-threshold-currents = <0 30000>; + qcom,mode-threshold-currents = <0 10000>; L6C: pm8350c_l6: regulator-pm8350c-l6 { regulator-name = "pm8350c_l6"; From 14573bff001afbb07f7f71eab01e760fc81c5a0d Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Tue, 6 Jul 2021 16:25:56 -0700 Subject: [PATCH 1636/1809] ARM: dts: msm: update clk tput threshold for IPA on Olympic Update IPA clock throughput thresholds to support higher IPA port corner frequencies. Change-Id: Ib44d42b42b8b279d894ca3eab9a3ac6592965c99 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 2719ca3df417..34c1746cd49f 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1228,7 +1228,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <2000 4000 8000>; + qcom,throughput-threshold = <3000 5000 10000>; qcom,scaling-exceptions = <>; ipa_smmu_ap: ipa_smmu_ap { From 74e0970bda6dbb37763e99d36854fcb4304331d5 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 30 Jun 2021 16:58:06 +0800 Subject: [PATCH 1637/1809] ARM: dts: msm: Add wdog bite IRQ for pil modem Add wdog interrupt for pil modem. Change-Id: I3cca2467edcadf66228d8604d014b564e1b36458 --- qcom/sdxnightjar.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index cc2624d83507..b15152a754e5 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -194,13 +194,15 @@ qcom,reset-clk; qcom,sequential-fw-load; - interrupts-extended = <&modem_smp2p_in 0 0>, + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 3 0>, <&modem_smp2p_in 7 0>; - interrupt-names = "qcom,err-fatal", + interrupt-names = "qcom,wdog", + "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", From f051948bd61fab4af01808fcb6f6b946aea44de6 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Wed, 7 Jul 2021 11:35:24 +0530 Subject: [PATCH 1638/1809] ARM: dts: msm: Mark PMIC QUPs as critical clock devices for BLAIR To prevent deadlocks between the clock and regulator frameworks, the QUP clocks used by I2C-connected PMICs must be enabled all the time and not registered with the clock framework. Skipping the registration short-circuits the I2C device's clock calls such that they return success before grabbing the clock locks. Achieve this behavior by setting GCC's qcom,critical-devices property. Change-Id: Idf812aa1df3a21670b8e9c262548cbf5f528e41b --- qcom/holi-pmic-overlay-pm6125.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index 78a61af2db8f..dcc5af29e2da 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -330,6 +330,14 @@ }; }; +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se10_i2c>; +}; + &qupv3_se10_i2c { #address-cells = <1>; #size-cells = <0>; From 45cf36cb63eb297be0b909cd28aae26da6b48472 Mon Sep 17 00:00:00 2001 From: Abhishek Chauhan Date: Mon, 24 May 2021 14:35:53 -0700 Subject: [PATCH 1639/1809] ARM: dts: msm: add ntn3 ipa pcie changes Update IPA iossv2 pcie configuration changes. Change-Id: I22536d8ab315dcb968a331d468aedb4e5aab81a9 --- qcom/sdxlemur-mtp-cpe.dtsi | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index f6993fafd059..38cdf380631b 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -32,6 +32,48 @@ enable-active-high; regulator-enable-ramp-delay = <2400>; }; + + ioss_qps615_rx: qps615_rx@eth { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <128>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_qps615_tx: qps615_tx@eth { + qcom,dir-tx; + qcom,ring-size = <512>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_qps615_eth0: qps615@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_qps615_rx>, + <&ioss_qps615_tx>; + }; + + ioss_qps615_eth1: qps615@eth1 { + qcom,name = "eth1"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_qps615_rx>, + <&ioss_qps615_tx>; + }; }; &i2c_5 { @@ -94,6 +136,19 @@ /* BDF 2.3.0 */ pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { reg = <0x1800 0x0 0x0 0x0 0x0>; + qps615_eth0,qps615_eth0@pcie0_rp { + reg = <0x0 0x0 0x0 0x0 0x0>; + + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = <&ioss_qps615_eth0>; + + /* ipa shares this group */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + }; /* BDF 5.0.0 */ pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 { reg = <0x0 0x0 0x0 0x0 0x0>; @@ -102,6 +157,20 @@ qcom,iommu-dma = "atomic"; }; }; + + qps615_eth1,qps615_eth1@pcie0_rp { + reg = <0x100 0x0 0x0 0x0 0x0>; + + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = <&ioss_qps615_eth1>; + + /* ipa shares this group */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + }; /* BDF 5.0.1 */ pcie0_bus5_dev0_fn1: pcie0_ntn3_eth1 { reg = <0x100 0x0 0x0 0x0 0x0>; From 86aa906b994d662650f98167fc272d2dc4fee809 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 7 Jul 2021 19:00:41 +0530 Subject: [PATCH 1640/1809] ARM: dts: qcom: enable cx ipeak lm separately for blair and holi-pm6125 Enable cx ipeak lm device driver separately for blair and holi-pm6125 targets based on latest devicetree configurations. Change-Id: I3326ac8760d5eef3d6e6ff118c4c8a1e3e52c659 --- qcom/blair.dtsi | 7 +++++++ qcom/holi-cdp-pm6125.dtsi | 7 ------- qcom/holi-mtp-pm6125.dtsi | 7 ------- qcom/holi-mtp-usbc-pm6125.dtsi | 7 ------- qcom/holi-pm6125-overlay.dtsi | 9 +++++++++ qcom/holi-qrd-pm6125.dtsi | 7 ------- 6 files changed, 16 insertions(+), 28 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 3d0bf3c62134..7045fbe738d1 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3304,6 +3304,13 @@ "gpu_gaming_bin", "feat_conf9"; }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; }; #include "holi-gpu.dtsi" diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index b4d9e00176d3..2e4ba4a22a34 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -149,13 +149,6 @@ linux,can-disable; }; }; - - cx_ipeak_lm: cx_ipeak@3ed000 { - #size-cells = <1>; - compatible = "qcom,cx-ipeak-v2"; - reg = <0x3ed000 0xe010>; - status = "ok"; - }; }; &pm7250b_charger { diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index 8dbc3454e44b..edad542ffecb 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -147,13 +147,6 @@ linux,can-disable; }; }; - - cx_ipeak_lm: cx_ipeak@3ed000 { - #size-cells = <1>; - compatible = "qcom,cx-ipeak-v2"; - reg = <0x3ed000 0xe010>; - status = "ok"; - }; }; &soc { diff --git a/qcom/holi-mtp-usbc-pm6125.dtsi b/qcom/holi-mtp-usbc-pm6125.dtsi index 5c5e3d98e7aa..f7b435b4c8a3 100644 --- a/qcom/holi-mtp-usbc-pm6125.dtsi +++ b/qcom/holi-mtp-usbc-pm6125.dtsi @@ -175,13 +175,6 @@ #include "qg-batterydata-atl466271_3300mAh.dtsi" #include "qg-batterydata-atl436186020H_3780mAh.dtsi" }; - - cx_ipeak_lm: cx_ipeak@3ed000 { - #size-cells = <1>; - compatible = "qcom,cx-ipeak-v2"; - reg = <0x3ed000 0xe010>; - status = "ok"; - }; }; &soc { diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index c16a7a01358d..6796be2e1610 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -79,3 +79,12 @@ vdd-supply = <&L18A>; core-supply = <&L4A>; }; + +&soc { + cx_ipeak_lm: cx_ipeak@3ed000 { + #size-cells = <1>; + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe010>; + status = "ok"; + }; +}; diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index 0bd1d18cc474..cff39e63c86e 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -215,13 +215,6 @@ linux,can-disable; }; }; - - cx_ipeak_lm: cx_ipeak@3ed000 { - #size-cells = <1>; - compatible = "qcom,cx-ipeak-v2"; - reg = <0x3ed000 0xe010>; - status = "ok"; - }; }; #include "camera/holi-camera-sensor-pm6125-mtp.dtsi" From c4277163ded3ff267b426a14eba9c48e8a7b20e3 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 6 Jul 2021 13:31:20 -0700 Subject: [PATCH 1641/1809] ARM: dts: msm: Add device tree for M.2 USB mode on sdxlemur Add device tree files for M.2 USB mode on sdxlemur. Change-Id: Ia52cea241defd4d2459bad90807c59eea79e0ad7 --- qcom/Makefile | 1 + qcom/sdxlemur-mtp-mbb-m2-ep-usb.dts | 13 ++++++++ qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi | 47 ++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 qcom/sdxlemur-mtp-mbb-m2-ep-usb.dts create mode 100644 qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index f0b24c10af42..0e4c4c177b6a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -418,6 +418,7 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-mtp-mbb-pcie-ep-ipq.dtb \ sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ sdxlemur-mtp-mbb-m2-ep.dtb \ + sdxlemur-mtp-mbb-m2-ep-usb.dtb \ sdxlemur-mtp-mbb.dtb \ sdxlemur-rcm-pcie-ep.dtb \ sdxlemur-rcm-rc.dtb \ diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dts b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dts new file mode 100644 index 000000000000..1287fb52188f --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-m2-ep-usb.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB M2 EP USB"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x10010008 0x310>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi new file mode 100644 index 000000000000..2970aac94d16 --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi @@ -0,0 +1,47 @@ + +&soc { + +}; + +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + qcom,devfreq,freq-table = <50000000 192000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; + +&pcie_ep { + status = "disabled"; +}; + +&mhi_device { + status = "disabled"; +}; + +&mhi_net_device { + status = "disabled"; +}; From 758b5b2b111405ad09c510995e8c56802cf48a5a Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Wed, 23 Jun 2021 12:00:25 -0700 Subject: [PATCH 1642/1809] Revert "ARM: dts: msm: Set qcom,rmnet_in_use_tcm_mem with RMNET composition" This reverts commit e6a51215e99a9904204cb1683dbe6fd0027528f6. Change-Id: I0fb75abfd13064fe28af5962196a2171f0648cd1 --- qcom/sdxlemur-usb.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 1b9631e0101c..d63d20923ae4 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -287,7 +287,6 @@ qcom,pid = <0x9067>; qcom,composition = "mass_storage.0,gsi.rmnet|mass_storage.1,gsi.mbim"; qcom,bmAttributes = <0xa0>; - qcom,rmnet_in_use_tcm_mem; }; composition5 { From 171ece287aea72f8df509378d667179e84e0b9eb Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 29 Jun 2021 16:49:06 +0530 Subject: [PATCH 1643/1809] ARM: dts: msm: Modify ss phy initialization sequence on sdxnightjar Modify ss phy initialization sequence on sdxnightjar according to HPG. Change-Id: I02d46ed95145bd168f2fa799fbf0a5205ed6528a --- qcom/sdxnightjar-usb.dtsi | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index 22299c20d4b3..c10cb263fc59 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -147,12 +147,12 @@ qcom,qmp-phy-init-seq = <0xac 0x14 0x00 0x34 0x08 0x00 0x174 0x30 0x00 - 0x3c 0x06 0x00 - 0xb4 0x00 0x00 - 0xb8 0x08 0x00 - 0x194 0x06 0x3e8 + 0x70 0x0f 0x00 0x19c 0x01 0x00 0x178 0x00 0x00 + 0x194 0x06 0x3e8 + 0x48 0x0f 0x00 + 0x3c 0x02 0x00 0xd0 0x82 0x00 0xdc 0x55 0x00 0xe0 0x55 0x00 @@ -161,12 +161,9 @@ 0x84 0x16 0x00 0x90 0x28 0x00 0x108 0x80 0x00 - 0x10c 0x00 0x00 - 0x184 0x0a 0x00 0x4c 0x15 0x00 0x50 0x34 0x00 0x54 0x00 0x00 - 0xc8 0x00 0x00 0x18c 0x00 0x00 0xcc 0x00 0x00 0x128 0x00 0x00 @@ -178,26 +175,20 @@ 0x18 0x00 0x00 0x24 0xde 0x00 0x28 0x07 0x00 - 0x48 0x0f 0x00 - 0x70 0x0f 0x00 - 0x100 0x80 0x00 - 0x440 0x0b 0x00 + 0x41c 0x06 0x00 0x4d8 0x02 0x00 - 0x4dc 0x6c 0x00 - 0x4e0 0xbb 0x00 + 0x4dc 0x4c 0x00 + 0x4e0 0xb8 0x00 0x508 0x77 0x00 0x50c 0x80 0x00 0x514 0x03 0x00 0x51c 0x16 0x00 - 0x448 0x75 0x00 - 0x454 0x00 0x00 - 0x40c 0x0a 0x00 - 0x41c 0x06 0x00 - 0x510 0x00 0x00 + 0x510 0x0c 0x00 0x268 0x45 0x00 0x2ac 0x12 0x00 0x294 0x06 0x00 - 0x254 0x00 0x00 + 0x824 0x15 0x00 + 0x828 0x0e 0x00 0x8c8 0x83 0x00 0x8c4 0x02 0x00 0x8cc 0x09 0x00 @@ -206,9 +197,7 @@ 0x880 0xd1 0x00 0x884 0x1f 0x00 0x888 0x47 0x00 - 0x80c 0x9f 0x00 - 0x824 0x17 0x00 - 0x828 0x0f 0x00 + 0x864 0x1b 0x00 0x8b8 0x75 0x00 0x8bc 0x13 0x00 0x8b0 0x86 0x00 From 3e7a1e3edd62d7beb53b59bf0b333cd0f7308145 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Tue, 29 Jun 2021 12:02:00 +0530 Subject: [PATCH 1644/1809] ARM: dts: msm: Add disable L1 quirk in HS mode for blair Some platforms do not support l1 in HS mode and therefore need to disable this feature through dt. This change adds quirk snps,usb2_l1_disable in order to avoid this. Change-Id: I5f06fed7e3f70d22d7f5099611f647b042d38d17 --- qcom/blair-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index ca58a3fe8b05..2f1a6b58e2ef 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -77,6 +77,7 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,is-utmi-l1-suspend; + snps,usb2-l1-disable; snps,dis_u2_susphy_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; From 263aeeef03e976079bdef5fd97487e6d4656811e Mon Sep 17 00:00:00 2001 From: Madhur Rawat Date: Wed, 16 Jun 2021 12:22:09 +0530 Subject: [PATCH 1645/1809] ARM: dts: msm: Update dcc registers for blair Add and update dcc debug registers for blair Change-Id: I45bcb6535cc9beef9e53a3cae5bd7d5a44cb175c --- qcom/blair.dtsi | 205 ++++++++++++++++++++---------------------------- 1 file changed, 85 insertions(+), 120 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c209dc1303c2..661933481c21 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1810,7 +1810,6 @@ , , , - , , , , @@ -1820,7 +1819,6 @@ , , , - , , , , @@ -2005,57 +2003,41 @@ , , , - , - , + + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , + , , - , - , - , + , , - , - , - , - , + , + , + , , - , - , + , , - , - , + , , - , + , + , + , , , - , , - , - , , - , - , , - , , , , @@ -2064,102 +2046,85 @@ , , , - , - , - , - , - , , - , - , - , - , - , - , - , - , - , - , , , - , - , - , , , , , , , - , - , - , - , - , - , - , - , - , - , - , - , - , , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; From 1031401a3ffce750a91040318936f607ab9ec02c Mon Sep 17 00:00:00 2001 From: Madhur Rawat Date: Fri, 2 Jul 2021 08:21:35 +0530 Subject: [PATCH 1646/1809] ARM: dts: msm: Add APPS_APM_STATUS register for blair Add APSS_APM_STATUS dcc debug register list for blair Change-Id: I31d38cfd77d440691308db73a1df56b81c93c20c --- qcom/blair.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index c209dc1303c2..d9abcc1bb9f5 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1684,6 +1684,7 @@ , , , + , , , , @@ -1985,6 +1986,7 @@ , , , + , , , , From 9b7f310fb36213c7da583455aa1475664213ce59 Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Fri, 9 Jul 2021 19:41:19 +0530 Subject: [PATCH 1647/1809] ARM: dts: msm: Enable cxipeak support for blair Enable cxipeak cooling device node for blair and holi-pm6125 variant. Change-Id: Ib75a06f0619af0f749a95f5d275d16faa73579de --- qcom/blair.dtsi | 5 +++++ qcom/holi-pm6125-overlay.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 7045fbe738d1..5999b56e868b 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3749,4 +3749,9 @@ }; }; +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; + qcom,clock-freq-threshold = <300000000>; +}; + #include "msm-rdbg.dtsi" diff --git a/qcom/holi-pm6125-overlay.dtsi b/qcom/holi-pm6125-overlay.dtsi index 6796be2e1610..ec6396f8c291 100644 --- a/qcom/holi-pm6125-overlay.dtsi +++ b/qcom/holi-pm6125-overlay.dtsi @@ -68,6 +68,11 @@ vdd_lpi_mx-supply = <&L17A_LEVEL>; }; +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; + qcom,clock-freq-threshold = <300000000>; +}; + &qusb_phy0 { vdd-supply = <&L7A>; vdda18-supply = <&L10A>; From d02c277821590f984d25b5b0b7f6c2daa9401551 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 29 Jun 2021 16:41:46 +0530 Subject: [PATCH 1648/1809] dt-bindings: iio: qcom,spmi-vadc: Add SW-calibrated ADC bindings Add bindings for SW-calibrated ADC used on PMR735A/PMR735B on targets which don't have PMK8350 running in master mode. Change-Id: I753b3caf1e52ac9920a9df32cbef465277409700 --- bindings/iio/adc/qcom,spmi-vadc.txt | 60 ++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/bindings/iio/adc/qcom,spmi-vadc.txt b/bindings/iio/adc/qcom,spmi-vadc.txt index 975907257ad6..b242cb777b44 100644 --- a/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/bindings/iio/adc/qcom,spmi-vadc.txt @@ -11,12 +11,13 @@ VADC node: Usage: required Value type: Definition: Should contain "qcom,spmi-vadc". - Should contain "qcom,spmi-adc5-gen3" for PMIC5 Gen3 ADC driver. - Should contain "qcom,spmi-adc7" for PMIC7 ADC driver. - Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. - Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. + Should contain "qcom,spmi-adc5-gen3" for PMIC5 Gen3 ADC. + Should contain "qcom,spmi-adc7" for PMIC7 ADC. + Should contain "qcom,spmi-adc5" for PMIC5 ADC. + Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC. Should contain "qcom,pms405-adc" for PMS405 PMIC - Should contain "qcom,spmi-adc5-lite" for PMIC5 ADC-lite driver. + Should contain "qcom,spmi-adc5-lite" for PMIC5 ADC-lite. + Should contain "qcom,spmi-adc7-sw-calib" for PMIC7 SW-calibrated ADC. - reg: Usage: required Value type: @@ -108,6 +109,19 @@ Channel node properties: If property is not found, channel will be calibrated with 0V and 1.25V reference channels, also known as absolute calibration. +- qcom,no-cal: + Usage: optional + Value type: + Definition: Channel calibration type. + - For compatible property "qcom,spmi-adc7-sw-calib", if this property + is specified for a channel, VADC will not use any reference channels + for that channel's calibration. It is needed for the three calibration + channels alone (ADC7_REF_GND, ADC7_1P25VREF and ADC7_VREF_VADC), + mutually exclusive with ratiometric calibration and not meant for any + other compatible property. If property is not found, channel will be + calibrated with 0.625V and 1.25V reference channels, also known as + absolute calibration. + - qcom,hw-settle-time: Usage: optional Value type: @@ -187,6 +201,11 @@ configuration nodes should be defined: VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, VADC_GND_REF and VADC_VDD_VADC. +For compatible property "qcom,spmi-adc7-sw-calib" following channels, also +known as reference point channels, are used for result calibration and their +channel configuration nodes should be defined: +ADC7_REF_GND, ADC7_1P25VREF and ADC7_VREF_VADC. + Example1: #include @@ -265,3 +284,34 @@ Example2: io-channels = <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>; io-channel-names = "vph_pwr"; }; + +Example3: + +#include +#include +/* ... */ + + /* VADC node */ + pmr735a_vadc: vadc@3600 { + compatible = "qcom,spmi-adc7-sw-calib"; + reg = <0x3600>, <0x3900>; + reg-names = "adc5-sw-calib-pbs-base", "adc5-sw-calib-cmn-base"; + interrupts = <0x4 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + /* IIO client node */ + pmr735a_tz { + io-channels = <&pmr735a_vadc ADC7_DIE_TEMP>; + io-channel-names = "thermal"; + }; From a3559a04a4563f131391dca2d0f141960e3965f8 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 15 Jul 2021 21:47:46 +0530 Subject: [PATCH 1649/1809] ARM: dts: msm: add ADC device instance for PMR735A on holi-pm6125 Add a SW-calibrated ADC instance for PMR735A on holi-pm6125 which can be used if there is a requirement to read any ADC channels on PMR735A. Change-Id: I8bff473ca2605a3601283865138dabf0589b903e --- qcom/holi-pmic-overlay-pm6125.dtsi | 46 ++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index dcc5af29e2da..cb7c64fc36ce 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -20,6 +20,52 @@ }; }; +&spmi_bus { + qcom,pmr735a@4 { + /* Example configuration to enable PMR735A VADC in standalone mode */ + pmr735a_vadc: vadc@3600 { + compatible = "qcom,spmi-adc7-sw-calib"; + reg = <0x3600>, <0x3900>; + reg-names = "adc5-sw-calib-pbs-base", "adc5-sw-calib-cmn-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + + /* PMR735a Channel nodes */ + pmr735a_ref_gnd { + reg = ; + label = "pmr735a_ref_gnd"; + qcom,pre-scaling = <1 1>; + qcom,no-cal; + }; + + pmr735a_vref_1p25 { + reg = ; + label = "pmr735a_vref_1p25"; + qcom,pre-scaling = <1 1>; + qcom,no-cal; + }; + + pmr735a_vref_vdd { + reg = ; + label = "pmr735a_vref_vdd"; + qcom,pre-scaling = <1 1>; + qcom,no-cal; + }; + + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; +}; + &pm6125_vadc { pinctrl-names = "default"; pinctrl-0 = < From 1ea164368316ea9088f744cb6b7442e4e6562b4b Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Tue, 13 Jul 2021 14:14:47 -0700 Subject: [PATCH 1650/1809] ARM: dts: msm: enable LAN RX NAPI Enable LAN RX NAPI. Change-Id: Ic6a9939ba6d60118a47a2386e0651b3d5199eb98 --- qcom/sdxlemur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 34c1746cd49f..04703f9206a3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1196,6 +1196,7 @@ qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; + qcom,lan-rx-napi; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; From 3b225e348f0ffe50dde8f7425fede1da9a22dc2c Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Thu, 22 Jul 2021 15:33:05 +0530 Subject: [PATCH 1651/1809] ARM: dts: msm: Add support of 608Mhz GPU FMAX for yupik Enable 608Mhz FMAX for yupik GPU as per speed bin requirement. Change-Id: I480d419ece2fa6b10e51f05e262e4f67a51122a8 --- qcom/yupik-gpu.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 6f028de05ae4..2161abdca3f9 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -465,6 +465,78 @@ qcom,acd-level = <0x882F5FFD>; }; }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <129>; + qcom,initial-pwrlevel = <3>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; + }; + }; }; }; From ee3ddee121f42f8d4b3edfca5d8c3202d40905cb Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 6 Jan 2021 12:55:46 +0530 Subject: [PATCH 1652/1809] dt-bindings: pcie: Notify client for config space access issues Notify the client driver to recover for EP config space access issues. Change-Id: I5567dbbdf58575954fb7caea05df2a3102825dc3 --- bindings/pci/pci-msm.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index cb4ff4a0e36b..e80245821de0 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -407,6 +407,11 @@ interconnects: Usage: optional Value type: Definition: Skip enumeration for the list of 32-bit BDFs. +- qcom,config-recovery: + Usage: optional + Value type : + Definition: Enable to notify the client driver for recovery when + config space is not accessible ============== Root port node From fdb842bf06d487428da22688fc4da7c641af7b0e Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Mon, 26 Jul 2021 20:01:56 +0530 Subject: [PATCH 1653/1809] ARM: dts: msm: Adding updated PHY tune parameters for blair Adding updated phy tune parameters for blair. This will ensure that qrd and mtp both have same phy tuning values. Change-Id: If286cc916c33a024ed53b04fd2aa153f7fbbc63c --- qcom/blair-usb.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index e7c3998a0513..346fb1f7a6b9 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -105,9 +105,9 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = - <0x61 0x6c /* override_x0 */ - 0x43 0x70 /* override_x1 */ - 0x2e 0x74>; /* override x2 */ + <0xa6 0x6c /* override_x0 */ + 0x85 0x70 /* override_x1 */ + 0x16 0x74>; /* override x2 */ }; /* Primary USB port related QMP USB DP Combo PHY */ From 78223268670d675e4e63331665ee313f5803b8a9 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 7 Jul 2021 14:49:43 +0530 Subject: [PATCH 1654/1809] ARM: dts: msm: disable masking MSI interrupts at EP side Disable masking MSI interrupts at EP side. Change-Id: I4c7fb61890f65345a39ba81e34b90b9c0c5acc99 --- qcom/lahaina-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 51682b0aa0a8..6a3423927bc4 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -118,6 +118,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,msi_mask_disable; qcom,pcie-phy-ver = <10100>; qcom,phy-status-offset = <0x214>; From 93171f995ad7c773bfb737e4ffe87e7a7e776da9 Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Tue, 27 Jul 2021 12:23:07 -0700 Subject: [PATCH 1655/1809] ARM: dts: msm: disable ipa-uc-holb-monitor Disabling ipa-uc-holb monitoring. Change-Id: If3c7cdebcfe5cbb05b713394825a0a653e2a6c60 --- qcom/sdxlemur.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 04703f9206a3..588178e1fd55 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1192,10 +1192,6 @@ qcom,ipa-endp-delay-wa-v2; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; - qcom,ipa-uc-holb-monitor; - qcom,ipa-holb-monitor-poll-period = <5>; - qcom,ipa-holb-monitor-max-cnt-wlan = <10>; - qcom,ipa-holb-monitor-max-cnt-usb = <10>; qcom,lan-rx-napi; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From 35c22d7176fff5ff992af1feb175dd5ade43fd83 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 23 Jul 2021 17:12:05 +0530 Subject: [PATCH 1656/1809] ARM: dts: msm: Disable Skin config rules for BLAIR Disable Skin config rules of quiet-ther,pa-therm0 and xo-therm based on latest recommendations. Change-Id: I8f78f4fcd3619c38260b73bfaada01853e0cb47f --- qcom/blair-qrd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 197fa0514ef7..bf529a34ca78 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -231,6 +231,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + disable-thermal-zone; trips { battery_trip0: battery-trip0 { temperature = <42000>; @@ -349,6 +350,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + disable-thermal-zone; trips { modem_trip0: modem-trip0 { temperature = <46000>; @@ -392,6 +394,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + disable-thermal-zone; trips { modem_pa_fr1_trip0: modem-pa-fr1-trip0 { temperature = <45000>; From 81013387d44664b5a546ebab9de8ff9330df310f Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Fri, 23 Jul 2021 01:36:22 +0530 Subject: [PATCH 1657/1809] ARM: dts: msm: Enable link recovery for config space access fail Enable link recovery by notifying client driver when config space read/write fails. Change-Id: I6286b3c2e9b677c1b0de2c6e89fe7c434d355443 --- qcom/lahaina-pcie.dtsi | 1 + qcom/shima-pcie.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 6a3423927bc4..086469300bb1 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -119,6 +119,7 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; qcom,msi_mask_disable; + qcom,config-recovery; qcom,pcie-phy-ver = <10100>; qcom,phy-status-offset = <0x214>; diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 4f9b6aef51ab..171c1d5a7d73 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -115,6 +115,7 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; qcom,msi_mask_disable; + qcom,config-recovery; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; From 8ec0007f4bc9a8b0c2ab084b26855b947e30d23e Mon Sep 17 00:00:00 2001 From: l Date: Fri, 4 Jun 2021 13:09:18 -0700 Subject: [PATCH 1658/1809] ARM: dts: msm: Add pm-qos-latency dt node for sdxlemur Add pm-qos-latency which ensures that cpu is used to its full capability,there by increasing ADB throughput. Change-Id: I28284ca1425795987d89c39bf8ab6d7bfee5884d --- qcom/sdxlemur-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d63d20923ae4..a80512eb8688 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -55,6 +55,7 @@ <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3>; qcom,default-bus-vote = <2>; /* use svs bus voting */ + qcom,pm-qos-latency = <44>; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; From 8468d1782bd89688e9ee4f84b62aa32398e16360 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 29 Jul 2021 18:00:39 +0530 Subject: [PATCH 1659/1809] ARM: dts: msm: Enable display on Blair ATP platform The Blair ATP is using Holi ATP board, so the display power supplies will be the same as Holi target. Enable display on the Blair ATP platform. Change-Id: I05502301d4d7f456198729517be6660f82937ab8 --- qcom/blair-atp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index eed6ca1e6178..c8aa78a9917e 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay.dtsi" #include "display/holi-sde-display-atp.dtsi" +#include "display/blair-sde-display-atp.dtsi" #include "holi-thermal-overlay.dtsi" #include @@ -707,6 +708,10 @@ qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ }; +&mdss_dsi0 { + vdda-1p2-supply = <&L22A>; +}; + &mdss_dsi_phy0 { vdda-0p9-supply = <&S5A_LEVEL>; }; From 933555c182cece8330d04b4fc61a94f8a23d759e Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Tue, 27 Jul 2021 11:07:24 -0700 Subject: [PATCH 1660/1809] ARM: dts: msm: Change cpu frequency for V2 hardware make changes to cpu frequency table for V2 hardware. Change-Id: Ic8d75a2236d679e491fb3832d6246f1bfdc6d12a --- qcom/sdxlemur-v2.dtsi | 16 ++++++++++++++++ qcom/sdxlemur.dtsi | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 75a7ba50ca15..3740fd2d468c 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -149,3 +149,19 @@ qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; + +&cpufreq { + qcom,cpufreq-table = + < 345600 >, + < 576000 >, + < 1094400 >, + < 1708800 >; +}; + +&cpu0_cpu_ddr_tbl { + qcom,core-dev-table = + < 345600 MHZ_TO_MBPS( 300, 4) >, + < 576000 MHZ_TO_MBPS( 768, 4) >, + < 1440000 MHZ_TO_MBPS(1555, 4) >, + < 1708800 MHZ_TO_MBPS(2092, 4) >; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 04703f9206a3..368cc8737138 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -236,7 +236,7 @@ interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; - qcom,msm-cpufreq { + cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clocks = <&apsscc APCS_MUX_CLK>; clock-names = "cpu0_clk"; From 73def4b85eedbd059eff81853394746153aeaae5 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 7 Jul 2021 16:56:46 +0530 Subject: [PATCH 1661/1809] ARM: dts: msm: Update USB2 core frequency for yupik Update USB2 core frequencies to be voted while USB2 is active for yupik. Change-Id: Ic17bfd0cc9a776f0a2c60eee5192d92dd9796b5c --- qcom/yupik-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index f4afd58dcfad..5879a26da5b9 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -335,7 +335,8 @@ resets = <&gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <60000000>; + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <60000000>; qcom,num-gsi-evt-buffs = <0x3>; qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = From 8a7751e140d65c6948cfb1785e971aa768db7081 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 19 May 2021 23:27:57 +0530 Subject: [PATCH 1662/1809] ARM: dts: qcom: Add modem mitigation for bcl violation in lahaina Add modem level 3 mitigation for bcl level 0 violation based on latest recommendation for lahaina. Increase passive delay for bcl thermal zones to delay clearing bcl mitigation. Change-Id: I50e7935c53511e5c47826a4252cfebd0e346c1f8 --- qcom/lahaina-thermal-overlay.dtsi | 50 ++++++++++++++++++------------- qcom/pm8350b.dtsi | 6 ++-- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index ce48bd0436ae..441b337bedcb 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -36,6 +36,16 @@ pm8350b-bcl-lvl0 { cooling-maps { + vbat_modem_l3 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + vbat_cpu4 { trip = <&b_bcl_lvl0>; cooling-device = <&cpu4_isolate 1 1>; @@ -46,11 +56,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vbat_cdsp0 { trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -60,6 +65,11 @@ pm8350b-bcl-lvl1 { cooling-maps { + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + vbat_cpu6 { trip = <&b_bcl_lvl1>; cooling-device = <&cpu6_isolate 1 1>; @@ -70,11 +80,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vbat_cdsp1 { trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; @@ -101,6 +106,16 @@ pm8350c-bcl-lvl0 { disable-thermal-zone; cooling-maps { + vph_modem_l3 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + vph_cpu4 { trip = <&c_bcl_lvl0>; cooling-device = <&cpu4_isolate 1 1>; @@ -111,11 +126,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { - trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vph_cdsp0 { trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -126,6 +136,11 @@ pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + vph_cpu6 { trip = <&c_bcl_lvl1>; cooling-device = <&cpu6_isolate 1 1>; @@ -136,11 +151,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vph_cdsp1 { trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index f92738d71ad5..84578c7d4384 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -279,7 +279,7 @@ }; pm8350b-bcl-lvl0 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 5>; @@ -294,7 +294,7 @@ }; pm8350b-bcl-lvl1 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 6>; @@ -309,7 +309,7 @@ }; pm8350b-bcl-lvl2 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 7>; From 882bdcd2146f6904c873bc7291012fb464538d77 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Tue, 13 Jul 2021 13:17:39 +0530 Subject: [PATCH 1663/1809] ARM: dts: msm: updated memory map v1 for blair Updated memory map for holi inline with v1. Change-Id: I58dbd276f3e8e45463de10adb8c3835f31f939f4 --- qcom/blair.dtsi | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 5999b56e868b..9a52582dbfe3 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -283,12 +283,7 @@ xbl_aop_mem: xbl_aop_mem@80700000 { no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; + reg = <0x0 0x80700000 0x0 0x100000>; }; reserved_xbl_uefi: reserved_xbl_uefi@80880000 { @@ -318,37 +313,32 @@ pil_adsp_mem: adsp@86700000 { no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; + reg = <0x0 0x86700000 0x0 0x2000000>; }; - pil_cdsp_mem: cdsp@88f00000 { + pil_cdsp_mem: cdsp@88700000 { no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; + reg = <0x0 0x88700000 0x0 0x1e00000>; }; - pil_camera_mem: camera@8ad00000 { + pil_video_mem: video@8a500000 { no-map; - reg = <0x0 0x8ad00000 0x0 0x500000>; + reg = <0x0 0x8a500000 0x0 0x500000>; }; - pil_video_mem: video@8b200000 { + pil_ipa_fw_mem: ipa_fw@8aa00000 { no-map; - reg = <0x0 0x8b200000 0x0 0x500000>; + reg = <0x0 0x8aa00000 0x0 0x10000>; }; - pil_ipa_fw_mem: ipa_fw@8b700000 { + pil_ipa_gsi_mem: ipa_gsi@8aa10000 { no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; + reg = <0x0 0x8aa10000 0x0 0xa000>; }; - pil_ipa_gsi_mem: ipa_gsi@8b710000 { + pil_gpu_micro_code_mem: gpu_micro_code@8aa1a000 { no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; + reg = <0x0 0x8aa1a000 0x0 0x2000>; }; pil_mpss_wlan_mem: mpss_wlan@8b800000 { From 9ebfa4ae99663f52a880ea6c44b9b3a5b04bde2f Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Thu, 29 Jul 2021 19:45:37 +0800 Subject: [PATCH 1664/1809] dt-bindings: Add awinic vendor name Add awinic vendor name in vendor prefix file. Change-Id: Ie8bc544c436a83f5ae89af1a02976ad4b679f118 --- bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index 89869deb520d..ea30a1c4882b 100644 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -1055,6 +1055,8 @@ patternProperties: description: ZTE Corp. "^zyxel,.*": description: ZyXEL Communications Corp. + "^awinic,.*": + description: Shanghai Awinic Electronic Technology Co., LTD. # Normal property name match without a comma # These should catch all node/property names without a prefix From 106b72aae376e2b4e827ff470fb8b75ad7896958 Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Thu, 3 Jun 2021 16:31:36 +0800 Subject: [PATCH 1665/1809] dt-bindings: leds: Add bindings for AW2016 LED device Add bingings for AW2016 LED driver. Change-Id: I9f062b081fe1ca1e99c01ff49e47dd2e2f5f0bcc --- NOTICE | 40 ++++++++++ bindings/leds/leds-aw2016.txt | 136 ++++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 NOTICE create mode 100644 bindings/leds/leds-aw2016.txt diff --git a/NOTICE b/NOTICE new file mode 100644 index 000000000000..0ba0e14857d8 --- /dev/null +++ b/NOTICE @@ -0,0 +1,40 @@ +This NOTICE file contains certain notices of software components included +with the software that Qualcomm Technologies, Inc. ("Qualcomm Technologies") is required to +provide you. Notwithstanding anything in the notices in this file, your use +of these software components together with the Qualcomm Technologies software (Qualcomm Technologies +software hereinafter referred to as "Software") is subject to the terms of +your license from Qualcomm Technologies. Compliance with all copyright laws and software +license agreements included in the notice section of this file are the +responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, +trademarks, copyrights, or other intellectual property. + +Copyright (c) 2021 Qualcomm Technologies, Inc. All rights reserved. +Qualcomm is a registered trademark and registered service mark of +QUALCOMM Incorporated. All other trademarks and service marks are the +property of their respective owners. +________________________________________ +NOTICES +________________________________________ +/* + * Copyright (C) 2008 Shanghai awinic technology co.,ltd. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS + * IN THE SOFTWARE. + */ diff --git a/bindings/leds/leds-aw2016.txt b/bindings/leds/leds-aw2016.txt new file mode 100644 index 000000000000..de2c921c31be --- /dev/null +++ b/bindings/leds/leds-aw2016.txt @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2008 Shanghai awinic technology co.,ltd. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS + * IN THE SOFTWARE. + */ + +Awinic. AW2016 LED + +AW2016 LED device supports 3 LED channels and the driver +register each channel as a single LED class device and +exports interfaces to update brightness, set timer trigger +and enable HW based blink functionalities. + +- compatible + Usage: required + Value type: + Definition: Must be "awinic,aw2016_led" + +- reg + Usage: required + Value type: + Definition: The 7-bit I2C address for AW2016 chip. + +Properties for child properties: +- awinic,name + Usage: required + Value type: + Definition: Name of the LED which will be register as the LED class + device name. + +- awinic,id + Usage: required + Value type: + Definition: It represents the LED hardware channel index. The valid + values are: 0, 1, 2. + +- awinic,imax + Usage: required + Value type: + Definition: The setting of the maximum current for the given LED channel, + the valid values are: 0, 1, 2, 3, and the corresponding current + setting are: 15mA, 30mA, 5mA, 10mA. + +- awinic,led-current + Usage: required + Value type: + Definition: The setting of the current when the LED channel is enabled. + +- awinic,max-brightness + Usage: required + Value type: + Definition: The maximum brightness value for the LED class device. + +- awinic,rise-time-ms + Usage: required + Value type + Definition: The duration of the led ramping from 0 to maximum brightness + when breath function is enabled. + +- awinic,hold-time-ms + Usage: required + Value type: + Definition: The duration of the led staying at the maximum brightness + when breath function is enabled. + +- awinic,fall-time-ms + Usage: required + Value type: + Definition: The duration of the led ramping down from maximum brightness + to 0 when breath function is enabled. + +- awinic,off-time-ms + Usage: required + Value type: + Definition: The duration of the led staying at 0 brightness when breath + function is enabled. + +Example: + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + }; + From de0584030836059df34f6289efc5f65b26718f31 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Thu, 24 Jun 2021 09:31:48 +0530 Subject: [PATCH 1666/1809] ARM: dts: msm: updating modem_tj mitigation for LAHAINA Remove modem_tj mitigation from cx_pe rule for LAHAINA. Change-Id: If889f43b5dbbf61278df717d1c6ec3a08a812cc1 --- qcom/lahaina-thermal.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 69d4886a81f6..4fadb7a87f45 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -1471,11 +1471,6 @@ cooling-device = <&cdsp_sw 3 3>; }; - cx_pe_cdev_4 { - trip = <&cx_pe_config4>; - cooling-device = <&modem_tj 1 1>; - }; - cx_pe_cdev_5 { trip = <&cx_pe_config5>; cooling-device = <&cdsp_sw 4 4>; From 3fe0d44ee929a1c44d3f3ca098eb739d97b2f56b Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Wed, 4 Aug 2021 17:42:34 +0800 Subject: [PATCH 1667/1809] ARM: dts: msm: Align sdxlemur BT config with sdxprairie Align sdxlemur bluetooth config with sdxprairie. CRs-Fixed: 3007327 Change-Id: I318059860a6204333726479ce3c525784daede07 --- qcom/sdxlemur-bluetooth.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/qcom/sdxlemur-bluetooth.dtsi b/qcom/sdxlemur-bluetooth.dtsi index 51252f8a9a3c..600583f15bb3 100644 --- a/qcom/sdxlemur-bluetooth.dtsi +++ b/qcom/sdxlemur-bluetooth.dtsi @@ -25,9 +25,7 @@ clock-names = "ref3_clk"; qcom,bt-vdd-aon-supply = <&S7B>; - qcom,bt-vdd-aon-config = <1012000 1012000 0 0>; - qcom,bt-vdd-io-supply = <&L6B>; - qcom,bt-vdd-io-config = <1800000 1800000 0 0>; + qcom,bt-vdd-aon-config = <1012000 1012000 0 1>; }; }; From f8bf9eef4a7e75d5cc188eed164aca0e467a59b5 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Wed, 4 Aug 2021 13:41:14 +0530 Subject: [PATCH 1668/1809] ARM: dts: msm: qcom: Fix proxy-supply for blair regulator nodes Fix proxy-supply for blair regulator nodes while at it also explicitly enable regulator-resource node for it. Change-Id: I64bfdad102e00d8e177f7e439223746cf7ed02eb --- qcom/blair-atp.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index eed6ca1e6178..e59e642779ef 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -354,6 +354,7 @@ /* Enable mx_cdev for PM6350 */ rpm-regulator-smpa5 { + proxy-supply = <&S5A_LEVEL>; regulator-s5-level { status = "okay"; }; @@ -373,10 +374,44 @@ /* Enable mx_cdev for PM6150A */ rpm-regulator-smpe1 { + regulator-s1-level { + status = "okay"; + }; + + regulator-s1-floor-level { + status = "okay"; + }; + + regulator-s1-level-ao { + status = "okay"; + }; + cx-cdev-lvl { status = "okay"; }; }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa1 { + regulator-l1-level { + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + proxy-supply = <&pm6350_l3>; + }; + + rpm-regulator-ldoa8 { + proxy-supply = <&pm6350_l8>; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa17 { + regulator-l17-level { + status = "okay"; + }; + }; }; From 99fcf7c526d20e6eb57724978a31d7a00241cf1e Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Sun, 8 Aug 2021 23:32:40 +0530 Subject: [PATCH 1669/1809] ARM: dts: msm: Ignore SSR failure for wpss Add ignore_ssr_failure flag for wpss on Yupik platform. Change-Id: I4bf032157c3c3586cb3cac4e5dea56c30633471e --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 779cd92d2f55..458ae1fc0cb8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -4248,6 +4248,7 @@ qcom,smem-id = <626>; qcom,signal-aop; qcom,complete-ramdump; + qcom,ignore-ssr-failure; /* Inputs from wpss */ interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, From 87c3cdb4c0243dfd23ba182f9f23a16b7d1d76e1 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 29 Jul 2021 18:00:39 +0530 Subject: [PATCH 1670/1809] ARM: dts: msm: Enable display on Blair ATP platform The Blair ATP is using Holi ATP board, so the display power supplies will be the same as Holi target. Enable display on the Blair ATP platform. Change-Id: I05502301d4d7f456198729517be6660f82937ab8 --- qcom/blair-atp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index eed6ca1e6178..c8aa78a9917e 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -3,6 +3,7 @@ #include #include "holi-pmic-overlay.dtsi" #include "display/holi-sde-display-atp.dtsi" +#include "display/blair-sde-display-atp.dtsi" #include "holi-thermal-overlay.dtsi" #include @@ -707,6 +708,10 @@ qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ }; +&mdss_dsi0 { + vdda-1p2-supply = <&L22A>; +}; + &mdss_dsi_phy0 { vdda-0p9-supply = <&S5A_LEVEL>; }; From eb092f64d948fca10b7375d05c278cf1b0634825 Mon Sep 17 00:00:00 2001 From: Niranjan Reddy Dumbala Date: Thu, 5 Aug 2021 13:03:54 +0530 Subject: [PATCH 1671/1809] ARM: dts: msm: Updating MTP-USBC platform dtb for blair target Updating nodes for MTP-USBC platform. Change-Id: I8454516d87029f1071905a230604b4df2a259599 --- qcom/blair-mtp-usbc.dtsi | 222 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 221 insertions(+), 1 deletion(-) diff --git a/qcom/blair-mtp-usbc.dtsi b/qcom/blair-mtp-usbc.dtsi index 336d7a250678..1722849a48fa 100644 --- a/qcom/blair-mtp-usbc.dtsi +++ b/qcom/blair-mtp-usbc.dtsi @@ -1,2 +1,222 @@ -/ { +#include "holi-audio-overlay.dtsi" +#include +#include +#include "holi-pm7250b.dtsi" +#include "holi-pmic-overlay-pm6125.dtsi" +#include "holi-thermal-overlay-pm6125.dtsi" +#include "display/holi-sde-display-mtp-pm6125.dtsi" +#include "display/blair-sde-display-mtp.dtsi" +#include + +&wcd938x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddio-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddio"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; }; + +&wcd937x_codec { + cdc-vdd-rxtx-supply = <&L9A>; + cdc-vddpx-supply = <&L9A>; + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vddpx"; + /* + * Overriding cdc-vdd-mic-bias-supply to dummy value + * to avoid compilation errors as BOB is not definied + * for pm6125 + */ + cdc-vdd-mic-bias-supply = <>; +}; + +&qupv3_se10_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + io-channels = <&pm7250b_charger PSY_IIO_TYPEC_ACCESSORY_MODE>; + io-channel-names = "typec_mode"; + qcom,use-power-supply = <1>; + }; +}; + +&holi_snd { + qcom,model = "holi-usbc-snd-card"; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + fsa4480-i2c-handle = <&fsa4480>; +}; + +&wsa881x_i2c_e { + cdc-vdd-1p8-supply = <&L9A>; +}; + +&wsa881x_i2c_f { + cdc-vdd-1p8-supply = <&L9A>; +}; + +/* Dummy LDO reference */ +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-yupik"; + + vdda-phy-supply = <&L7A>; + vdda-pll-supply = <&L4A>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L11A>; + vccq2-max-microamp = <800000>; + vccq2-voltage-level = <1800000 1800000>; + + qcom,vddp-ref-clk-supply = <&L4A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L9A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&soc { + touch_avdd: touch_avdd_stub { + /* + * Touch eLDO controlled by gpio#53 is always ON. + * Using dummy regulator. + */ + compatible = "qcom,stub-regulator"; + regulator-name = "touch_avdd_stub"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L9A>; + avdd-supply = <&touch_avdd>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; +}; + +#include "camera/blair-camera-sensor-mtp.dtsi" + From 715fbfe3a9d6198eb599fa50dcf4d5c87e07d8d4 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 9 Aug 2021 13:23:24 +0800 Subject: [PATCH 1672/1809] ARM: dts: msm: add tzpu_ctx dump entry Add tzpu_ctx dump entry on sdxlemur. Change-Id: I7eda6191beb41312924290eafe3a1a91af92f048 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d5b5ac3d11ff..f85e155caf95 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -292,6 +292,11 @@ qcom,dump-id = <0x102>; }; + tzpu_ctx0 { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x00>; + }; + misc_data { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe8>; From 42bb7e97d7ea2789bfa2eeedb09b55c31fe4ec85 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 10 Aug 2021 11:00:07 +0530 Subject: [PATCH 1673/1809] ARM: dts: msm: Add changes to support ATP on blair Add changes to support ATP on blair. Change-Id: I4e39ec243f4909262779f0568fe083454f2a059d --- qcom/blair-atp-overlay.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/qcom/blair-atp-overlay.dts b/qcom/blair-atp-overlay.dts index c96b78ec4330..c002a611a76b 100644 --- a/qcom/blair-atp-overlay.dts +++ b/qcom/blair-atp-overlay.dts @@ -9,3 +9,36 @@ qcom,msm-id = <507 0x10000>; qcom,board-id = <33 0>; }; + +&wsa881x_i2c_e { + status = "disabled"; +}; + +&wsa881x_i2c_44 { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&holi_snd { + qcom,wcd-disabled = <1>; + qcom,audio-routing = + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK"; +}; From 4697ee62eb68432fb99cf3ed260314119680cef8 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 11 Aug 2021 20:46:40 +0530 Subject: [PATCH 1674/1809] ARM: dts: msm: Add cx_misc register map for yupik GPU Adding cx_misc register range for yupik gpu to enable snapshot collection for cx misc registers. Change-Id: Iab19a2cbb816554b283cab1410b68b17e3ada5a4 --- qcom/yupik-gpu.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 2161abdca3f9..c6542a40b826 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -22,10 +22,12 @@ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>, <0x0636000 0x1000>; + <0x06900000 0x80000>, <0x0636000 0x1000>, + <0x3d9e000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx", "rdpm_mx"; + "isense_cntl", "qdss_gfx", "rdpm_mx", + "cx_misc"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; From c5edef21a4589314006469309b3696906af49390 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 28 Jul 2021 19:35:31 +0530 Subject: [PATCH 1675/1809] ARM: dts: msm: Restore SDCC registers once Resuming from CX/XO Defines the restore-after-cx-collapse property for MMC driver. This basically lets the driver know that software needs to save the SDCC register contents before the CX/XO event and restore the SDCC register contents after coming out of CX/XO event. Sdxlemur is not supporting retention of CX PC hence this change is needed. Change-Id: Id7808813509fb2ee0ce3469c6e04e787b466994b --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index ea6d71dc8fb3..8cb257865dfd 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -14,6 +14,7 @@ reg = <0x08804000 0x1000>, <0x08805000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; + qcom,restore-after-cx-collapse; mmc-ddr-1_8v; mmc-hs200-1_8v; From 7104102b1d6cce9d121f9de75cce17675e0bf8a8 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 12 Aug 2021 10:36:48 +0530 Subject: [PATCH 1676/1809] ARM: dts: msm: qcom: Update refgen node for blair-atp platform Update refgen node for Blair-ATP platform. Change-Id: Ifbae95a5df56f96b5856d3861a9d10ec3aa5a8b3 --- qcom/blair-atp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index cce9220e5081..63b20ca98532 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -790,3 +790,9 @@ vdd_lpi_cx-supply = <&L1A_LEVEL>; vdd_lpi_mx-supply = <&L17A_LEVEL>; }; + +&refgen { + compatible = "qcom,refgen-kona-regulator"; + reg = <0x162F000 0x84>; +}; + From d462fea9a0d95f93fa4f1623c055f4e367d997c2 Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Thu, 12 Aug 2021 15:06:59 +0530 Subject: [PATCH 1677/1809] ARM: dts: msm: Add disable u1 quirk and u2 quirk for blair U1 and U2 are intermediate low power states. If host side and device side u1 and u2 is supported then host sends a bus reset signal when usb bus is idle which causes usb disconnect and connect. This effects many automation runs as adb will be disconencted and reconnected. Hence, disable u1, u2 on blair to solve this. Change-Id: I3436b8e758976362919e199ddfad6b1ad659c152 --- qcom/blair-usb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index 2f1a6b58e2ef..e82efe422c23 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -78,6 +78,8 @@ snps,disable-clk-gating; snps,is-utmi-l1-suspend; snps,usb2-l1-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; From e2202e0a90783f3796a1d029aa0d64a6283406ae Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Fri, 18 Jun 2021 21:11:59 +0800 Subject: [PATCH 1678/1809] ARM: dts: msm: Add AW2016 LED device nodes for Holi-m6125 platforms Add AW2016 RGB LED device nodes to expose the class LED devices for userspace to control them. Change-Id: I97f7e4ba13d44ddbf7634149e89f8087f0ddee98 --- qcom/holi-cdp-pm6125.dtsi | 44 +++++++++++++++++++++++++++++++++++++++ qcom/holi-mtp-pm6125.dtsi | 44 +++++++++++++++++++++++++++++++++++++++ qcom/holi-qrd-pm6125.dtsi | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) diff --git a/qcom/holi-cdp-pm6125.dtsi b/qcom/holi-cdp-pm6125.dtsi index 2e4ba4a22a34..a8ca8f0cf404 100644 --- a/qcom/holi-cdp-pm6125.dtsi +++ b/qcom/holi-cdp-pm6125.dtsi @@ -362,3 +362,47 @@ io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; io-channel-names = "chg_type"; }; + +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; diff --git a/qcom/holi-mtp-pm6125.dtsi b/qcom/holi-mtp-pm6125.dtsi index edad542ffecb..b4695eeaa4db 100644 --- a/qcom/holi-mtp-pm6125.dtsi +++ b/qcom/holi-mtp-pm6125.dtsi @@ -197,4 +197,48 @@ }; }; +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + #include "camera/holi-camera-sensor-pm6125-mtp.dtsi" diff --git a/qcom/holi-qrd-pm6125.dtsi b/qcom/holi-qrd-pm6125.dtsi index cff39e63c86e..ccd6905fb025 100644 --- a/qcom/holi-qrd-pm6125.dtsi +++ b/qcom/holi-qrd-pm6125.dtsi @@ -219,6 +219,50 @@ #include "camera/holi-camera-sensor-pm6125-mtp.dtsi" +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + &thermal_zones { quiet-therm-step { polling-delay-passive = <2000>; From e9fac2703e73f13dbd76d74386ef3d8822b0fda8 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 13 Aug 2021 16:07:51 +0530 Subject: [PATCH 1679/1809] ARM: dts: msm: Add changes for blair USBC target Add changes for blair USBC target. Change-Id: I9ec4153f03b0c797c0afe1038aad8fe0d2c98fe3 --- qcom/blair-mtp-usbc-overlay.dts | 35 +++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/blair-mtp-usbc-overlay.dts b/qcom/blair-mtp-usbc-overlay.dts index f5161de1eb9b..32fd182f64d7 100644 --- a/qcom/blair-mtp-usbc-overlay.dts +++ b/qcom/blair-mtp-usbc-overlay.dts @@ -10,4 +10,39 @@ qcom,board-id = <8 1>; }; +&swr0 { + qcom,is_wcd937x = <0>; +}; +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd938x_tx_slave { + status = "ok"; +}; + +&wcd938x_rx_slave { + status = "ok"; +}; + +&wcd938x_codec { + status = "ok"; +}; + +&holi_snd { + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&wsa881x_i2c_e>, + <&wsa881x_i2c_f>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "wsa-codec0", + "wsa-codec1"; +}; From 20219f645718b32fe5882e293e0583a56721064d Mon Sep 17 00:00:00 2001 From: Bavyasritha Alahari Date: Sun, 15 Aug 2021 20:27:51 +0530 Subject: [PATCH 1680/1809] ARM: dts: msm: Add qos silver cores to device tree Add qos silver cores to device tree for adaptive QOS Change-Id: I0c07bd0a637fc8463fb474d4f51482e59750cc46 --- qcom/blair.dtsi | 1 + qcom/holi.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 9a52582dbfe3..fadf8c541a3c 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -2329,6 +2329,7 @@ msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1 2 3 4 5>; qcom,qos-latency-us = <70>; qcom,qos-maxhold-ms = <20>; }; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 9d12ad9d5210..cd8d005b93f2 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2381,6 +2381,7 @@ msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1 2 3 4 5>; qcom,qos-latency-us = <70>; qcom,qos-maxhold-ms = <20>; }; From b335a2255b8469227ea995fa6e64002b0227e9c9 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 16 Aug 2021 12:04:11 +0530 Subject: [PATCH 1681/1809] ARM: dts: msm: Skip BW vote for PM8008 used I2C SE node Enable flag "qcom,leica-used-i2c" to skip BW vote for PM8008 used I2C instance to prevent deadlock condition between regulator and clocks framework. Change-Id: Ie4746f615f2f348c0aa19c77ebe6313986bbda32 --- qcom/holi-pmic-overlay-pm6125.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index cb7c64fc36ce..444bc36e322a 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -389,6 +389,7 @@ #size-cells = <0>; status = "ok"; + qcom,leica-used-i2c; pm8008_8: qcom,pm8008@8 { compatible = "qcom,i2c-pmic"; reg = <0x8>; From f53dfeb7143cba1cb155367b9f4bd4ef913c5827 Mon Sep 17 00:00:00 2001 From: Skylar Chang Date: Mon, 16 Aug 2021 15:27:54 -0700 Subject: [PATCH 1682/1809] ARM: dts: msm: change wdi3 holb timeout Change wdi3 holb timeout values to 15 for 2.4g and 31 for 5g/6g. Change-Id: I8535b2f2ff3ce3320d128538d810c374e026ef82 --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f85e155caf95..ece25094a193 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1192,8 +1192,8 @@ qcom,arm-smmu; qcom,smmu-fast-map; qcom,ipa-wdi3-over-gsi; - qcom,ipa-wdi3-holb-2g = <8>; - qcom,ipa-wdi3-holb-5g = <15>; + qcom,ipa-wdi3-holb-2g = <15>; + qcom,ipa-wdi3-holb-5g = <31>; qcom,ipa-endp-delay-wa-v2; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; From e4d50b9b85941d3856c02cc2581c3866ff73e67c Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Wed, 18 Aug 2021 21:26:56 +0800 Subject: [PATCH 1683/1809] ARM: dts: msm: add AW2016 LED device nodes for blair platforms Add AW2016 RGB LED device nodes to expose the class LED devices for userspace to control them. Change-Id: Ia80c6e42c89036fb0c53469ca130e606ad0485fe --- qcom/blair-cdp.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ qcom/blair-mtp.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ qcom/blair-qrd.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index d8e853f82690..3a04bd70fe5f 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -392,4 +392,46 @@ io-channel-names = "chg_type"; }; +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; diff --git a/qcom/blair-mtp.dtsi b/qcom/blair-mtp.dtsi index 72c09ebd187a..e0be9363207f 100644 --- a/qcom/blair-mtp.dtsi +++ b/qcom/blair-mtp.dtsi @@ -199,5 +199,49 @@ }; }; +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + #include "camera/blair-camera-sensor-mtp.dtsi" diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index bf529a34ca78..15ac3ac8c135 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -481,4 +481,48 @@ }; }; +&qupv3_se10_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + #include "camera/blair-camera-sensor-qrd.dtsi" From 91add08f05c6ebabbae80aaf2538997e6acc574e Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Wed, 11 Aug 2021 14:24:59 +0530 Subject: [PATCH 1684/1809] ARM: dts: msm: Remove unused smps regulator This change removes unused smps regulator for blair atp platform. Change-Id: I1d64fe3ae8865e12f8a21c222f34c36421c4425d --- qcom/blair-atp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 63b20ca98532..f0e0e0cab6be 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -737,6 +737,7 @@ }; &bluetooth { + qcom,bt-vdd-smps-supply = <>; /* SMPS */ qcom,bt-vdd-io-supply = <&L11A>; /* IO */ qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ From 2af43096ff400db7b6c93123afb1e5bf1fd68ba2 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Wed, 11 Aug 2021 14:24:59 +0530 Subject: [PATCH 1685/1809] ARM: dts: msm: Remove unused smps regulator This change removes unused smps regulator for blair atp platform. Change-Id: I1d64fe3ae8865e12f8a21c222f34c36421c4425d --- qcom/blair-atp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index 63b20ca98532..f0e0e0cab6be 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -737,6 +737,7 @@ }; &bluetooth { + qcom,bt-vdd-smps-supply = <>; /* SMPS */ qcom,bt-vdd-io-supply = <&L11A>; /* IO */ qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ From 4d414f50f2a3d0253b36bb822dda0551ead655e3 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 24 Aug 2021 13:09:25 +0530 Subject: [PATCH 1686/1809] ARM: dts: qcom: Update hvx and skin config rules for BLAIR Update Skin and HVX sensor rules for Blair as per latest recommendations. Change-Id: I14c17c552ff472eb427bb7864102d394ccade50a --- qcom/blair-qrd.dtsi | 54 +++++++++++++++++++++++++-------------------- qcom/blair.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 81 insertions(+), 25 deletions(-) diff --git a/qcom/blair-qrd.dtsi b/qcom/blair-qrd.dtsi index 15ac3ac8c135..028860d2a94c 100644 --- a/qcom/blair-qrd.dtsi +++ b/qcom/blair-qrd.dtsi @@ -231,7 +231,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; - disable-thermal-zone; + trips { battery_trip0: battery-trip0 { temperature = <42000>; @@ -246,7 +246,7 @@ }; gold_trip: gold-trip { - temperature = <43000>; + temperature = <46000>; hysteresis = <0>; type = "passive"; }; @@ -263,12 +263,6 @@ type = "passive"; }; - silver_trip: silver-trip { - temperature = <45000>; - hysteresis = <0>; - type = "passive"; - }; - battery_trip2: battery-trip2 { temperature = <46000>; hysteresis = <2000>; @@ -287,6 +281,18 @@ type = "passive"; }; + gpu_trip: gpu-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + silver_trip: silver-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + cx_trip: cx-trip { temperature = <55000>; hysteresis = <5000>; @@ -301,46 +307,46 @@ }; gpu-cdev0 { - trip = <&modem_skin_trip1>; + trip = <&gpu_trip>; /* throttle to 650000000Hz */ - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) - (THERMAL_MAX_LIMIT-4)>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; }; gpu-cdev1 { trip = <&cx_trip>; - /* throttle to 565000000Hz */ - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) - (THERMAL_MAX_LIMIT-3)>; + /* throttle to 390000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; }; silver-cdev { trip = <&silver_trip>; - /* throttle to 1478400KHz */ - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + /* throttle to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT (THERMAL_MAX_LIMIT-6)>; }; gold-cdev { trip = <&gold_trip>; - /* throttle to 1536000KHz */ - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) - (THERMAL_MAX_LIMIT-5)>; + /* throttle to 1516800KHz */ + cooling-device = <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; }; modem-skin-cdev0 { trip = <&modem_skin_trip0>; - cooling-device = <&modem_skin 1 1>; + cooling-device = <&modem_pa 1 1>; }; modem-skin-cdev1 { trip = <&modem_skin_trip1>; - cooling-device = <&modem_skin 2 2>; + cooling-device = <&modem_pa 2 2>; }; modem-skin-cdev2 { trip = <&cx_trip>; - cooling-device = <&modem_skin 3 3>; + cooling-device = <&modem_pa 3 3>; }; }; }; @@ -350,7 +356,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; - disable-thermal-zone; + trips { modem_trip0: modem-trip0 { temperature = <46000>; @@ -394,7 +400,7 @@ polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; - disable-thermal-zone; + trips { modem_pa_fr1_trip0: modem-pa-fr1-trip0 { temperature = <45000>; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index fadf8c541a3c..48af98cc21f4 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3736,7 +3736,57 @@ }; cxip-cdev@3ed000 { - status = "ok"; + status = "disabled"; + }; +}; + +&thermal_zones { + /delete-node/ q6-hvx-step; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + + trips { + q6_hvx_trip0: q6-hvx-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_cx_mon: q6-hvx-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + q6-hvx-cdev0 { + trip = <&q6_hvx_trip0>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + q6-hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + /* throttle to 390000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + q6-hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + q6-hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; }; }; From 3d07862d3928bf9208ada5a328140c6c60172ced Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 5 Aug 2021 10:49:05 +0530 Subject: [PATCH 1687/1809] ARM: dts: msm: Rename L1 disable property to align with driver Rename snps,usb2_l1_disable to snps,usb2-gadget-lpm-disable since driver code for disabling L1 was changed and renamed to snps,usb2-gadget-lpm-disable in order to align with upstream. Change-Id: I7e41a041a3c563c2a2048968ace3615518ce80de --- bindings/usb/dwc3.txt | 3 +++ qcom/sdxnightjar-usb.dtsi | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/bindings/usb/dwc3.txt b/bindings/usb/dwc3.txt index 943123999123..d9963a22b1e0 100644 --- a/bindings/usb/dwc3.txt +++ b/bindings/usb/dwc3.txt @@ -81,6 +81,9 @@ Optional properties: before attempting a U3 exit handshake. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n + - snps,usb2-gadget-lpm-disable: Indicate if we don't want to enable USB2 HW + LPM for gadget mode. This is a boolean type property when set the + disable will be true. - snps,hird-threshold: HIRD threshold - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi index c10cb263fc59..8ecf7008ec32 100644 --- a/qcom/sdxnightjar-usb.dtsi +++ b/qcom/sdxnightjar-usb.dtsi @@ -65,7 +65,7 @@ snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,bus-suspend-enable; - snps,usb2-l1-disable; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; xhci-imod-value = <4000>; From 38707df4bfde73ef09dfb2a0d407c842b3197ddd Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Wed, 25 Aug 2021 18:17:48 +0530 Subject: [PATCH 1688/1809] ARM: dts: qcom: Move all WLAN configs out of sdxlemur-mtp-cpe.dtsi sdxlemur-mtp-cpe.dtsi is included in sdxlemur-mtp-cpe.dts as well as sdxlemur-mtp-cpe-pine1x.dts. WLAN configs present in sdxlemur-mtp-cpe.dtsi is not applicable for sdxlemur-mtp-cpe-pine1x.dts. Move all WLAN specific configurations from sdxlemur-mtp-cpe.dtsi to a new file sdxlemur-mtp-cpe-hsp.dtsi and include this file in sdxlemur-mtp-cpe.dts only. Change-Id: I245662cf6b23dcb3b5c5fc5ce2ac61783b801cdc --- qcom/sdxlemur-mtp-cpe-hsp.dtsi | 41 ++++++++++++++++++++++++++++++++++ qcom/sdxlemur-mtp-cpe.dts | 1 + qcom/sdxlemur-mtp-cpe.dtsi | 36 ----------------------------- 3 files changed, 42 insertions(+), 36 deletions(-) create mode 100644 qcom/sdxlemur-mtp-cpe-hsp.dtsi diff --git a/qcom/sdxlemur-mtp-cpe-hsp.dtsi b/qcom/sdxlemur-mtp-cpe-hsp.dtsi new file mode 100644 index 000000000000..d9969be2f7be --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe-hsp.dtsi @@ -0,0 +1,41 @@ +#include "sdxlemur-cnss.dtsi" + +&pcie0 { + qcom,boot-option = <0x1>; +}; + +&pcie0_bus2_dev2_fn0 { + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&wlan { + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; +}; diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index b5417a3ea95c..3942c230e2bd 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-hsp.dtsi" #include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 38cdf380631b..4679c7bc2f2a 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -91,7 +91,6 @@ &pcie0 { - qcom,boot-option = <0x1>; pcie-i2c-phandle = <&i2c_5>; vreg-3p3-supply = <&aqr_vreg>; @@ -123,14 +122,6 @@ /* BDF 2.2.0 */ pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 { reg = <0x1000 0x0 0x0 0x0 0x0>; - cnss_pci0: cnss_pci0 { - reg = <0 0 0 0 0>; - qcom,iommu-group = <&cnss_pci_iommu_group>; - memory-region = <&cnss_wlan_mem>; - - #address-cells = <1>; - #size-cells = <1>; - }; }; /* BDF 2.3.0 */ @@ -182,30 +173,3 @@ }; }; }; - -#include "sdxlemur-cnss.dtsi" - -&wlan { - mhi_events { - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <1>; - mhi,priority = <0>; - mhi,brstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <0>; - mhi,msi = <2>; - mhi,priority = <1>; - mhi,brstmode = <2>; - }; - - mhi_event@2 { - status = "disabled"; - }; - }; -}; From bf06dc0e285c9e5617a8e114fe0d466865adf86e Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Wed, 25 Aug 2021 18:34:38 +0530 Subject: [PATCH 1689/1809] ARM: dts: qcom: Add Support for QCN9000 for MTP CPE Add the following changes to support QCN9000 in MTP CPE 1x Pine platform: 1. Add sdxlemur-qcn9000.dtsi to have all QCN9000 related configs. 2. Add memory reservation of 2x52 MB for 2 QCN9000 in sdxlemur-qcn9000.dtsi but in disabled state. 3. Enable reserved memory for 1 QCN9000 in sdxlemur-mtp-cpe-pine1x.dtsi. 4. Add wifi node with all QCN9000 related configs. 5. Enable pcie0_bus2_dev1_fn0 node with QCN9000 memory configs. 6. Enable GPIO 102 to power on QCN9000. Change-Id: Ieaa7e6fb567581f6d82ae6edfc2f664adf3ef4cc --- bindings/cnss/cnss-wlan.txt | 1 + qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 43 ++- qcom/sdxlemur-qcn9000.dtsi | 590 ++++++++++++++++++++++++++++++ 3 files changed, 633 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-qcn9000.dtsi diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 284ef3b1d350..0309934b1cda 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -17,6 +17,7 @@ Required properties: "qcom,cnss-qca6390" for QCA6390 device "qcom,cnss-qca6490" for QCA6490 device "qcom,cnss-wcn7850" for WCN7850 device + "qcom,cnss-qcn9000" for QCN9000 device "qcom,cnss-qca-converged" for converged QCA devices - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications - vdd-wlan-supply: phandle to the regulator device tree node diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index a7373e1f2622..22600ce00a35 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -1,4 +1,45 @@ +#include "sdxlemur-qcn9000.dtsi" + &soc { - + pine_vreg: pine_vreg { + compatible = "regulator-fixed"; + regulator-name = "pine_vreg"; + gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-enable-ramp-delay = <200000>; + }; +}; + +&ntn3_vreg { + vin-supply = <&pine_vreg>; +}; + +&pcie0 { + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; +}; + +&pcie0_bus2_dev1_fn0 { + cnss_pci1: cnss_pci1 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&qcn9000_pci_iommu_group_0>; + memory-region = <&qcn9000_0_mem>; + qrtr_instance_id = <0x0>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&wifi0 { + status = "ok"; +}; + +&qcn9000_0_mem { + status = "ok"; }; diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi new file mode 100644 index 000000000000..98ab99e0af31 --- /dev/null +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -0,0 +1,590 @@ + +&reserved_memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcn9000_0_mem: qcn9000_0_mem { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x3400000>; + status = "disabled"; + }; + + qcn9000_1_mem: qcn9000_1_mem { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x3400000>; + status = "disabled"; + }; +}; + +&soc { + wifi0: qcom,cnss-qcn9000@a0000000 { + status = "disabled"; + compatible = "qcom,cnss-qcn9000"; + memory-region = <&qcn9000_0_mem>; + qcom,wlan-ramdump-dynamic = <0x400000>; + qrtr_node_id = <0x0>; + qca,auto-restart; + tgt-mem-mode = <0x1>; + board_id = <0xa4>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + }; + }; + }; + + wifi1: qcom,cnss-qcn9000@b0000000 { + status = "disabled"; + compatible = "qcom,cnss-qcn9000"; + memory-region = <&qcn9000_1_mem>; + qcom,wlan-ramdump-dynamic = <0x400000>; + qrtr_node_id = <0x0>; + qca,auto-restart; + tgt-mem-mode = <0x1>; + board_id = <0xa4>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + }; + }; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + #address-cells = <1>; + #size-cells = <1>; + + qcn9000_pci_iommu_group_0: qcn9000_pci_iommu_group_0 { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + + qcn9000_pci_iommu_group_1: qcn9000_pci_iommu_group_1 { + qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + }; +}; + +&reserved_memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcn9000_0_mem: qcn9000_0_mem { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x3400000>; + status = "disabled"; + }; + + qcn9000_1_mem: qcn9000_1_mem { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x3400000>; + status = "disabled"; + }; +}; + +&soc { + wifi0: qcom,cnss-qcn9000@a0000000 { + status = "disabled"; + compatible = "qcom,cnss-qcn9000"; + memory-region = <&qcn9000_0_mem>; + qcom,wlan-ramdump-dynamic = <0x400000>; + qrtr_node_id = <0x0>; + qca,auto-restart; + tgt-mem-mode = <0x1>; + board_id = <0xa4>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + }; + }; + }; + + wifi1: qcom,cnss-qcn9000@b0000000 { + status = "disabled"; + compatible = "qcom,cnss-qcn9000"; + memory-region = <&qcn9000_1_mem>; + qcom,wlan-ramdump-dynamic = <0x400000>; + qrtr_node_id = <0x0>; + qca,auto-restart; + tgt-mem-mode = <0x1>; + board_id = <0xa4>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + status = "disabled"; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + }; + }; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + #address-cells = <1>; + #size-cells = <1>; + + qcn9000_pci_iommu_group_0: qcn9000_pci_iommu_group_0 { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + + qcn9000_pci_iommu_group_1: qcn9000_pci_iommu_group_1 { + qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + }; +}; From 48300671610974198e095dd3d36ad40dc6366d6e Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 25 Aug 2021 20:40:45 +0530 Subject: [PATCH 1690/1809] ARM: dts: msm: Rename L1 disable property for blair Rename snps,usb2_l1_disable to snps,usb2-gadget-lpm-disable since driver code for disabling L1 was changed and renamed to snps,usb2-gadget-lpm-disable in order to align with upstream. Change-Id: Ic95baa810ac4da004e83e8a2b25bbfbcd74350df --- qcom/blair-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair-usb.dtsi b/qcom/blair-usb.dtsi index 0d0ffb1dfa08..294ee0a83548 100644 --- a/qcom/blair-usb.dtsi +++ b/qcom/blair-usb.dtsi @@ -77,7 +77,7 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,is-utmi-l1-suspend; - snps,usb2-l1-disable; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; From 55dacb76a1411ab80a97e466ba6fe4c172ba0df1 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 26 Aug 2021 09:59:37 +0530 Subject: [PATCH 1691/1809] ARM: dts: msm: Enable SMMU S1 support for eMMC on sdxlemur Enable SMMU S1 support for eMMC on sdxlemur. Change-Id: I5473d469dd54924cc0cf3d0168187bd8876e05dd --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-m2-ep.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 8cb257865dfd..6a400fbe2c40 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -22,6 +22,11 @@ non-removable; supports-cqe; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x40000000 0x8000000>; + qcom,iommu-geometry = <0x40000000 0x8000000>; + vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 570000>; diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi index 2970aac94d16..afe8e580bc60 100644 --- a/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi +++ b/qcom/sdxlemur-mtp-mbb-m2-ep-usb.dtsi @@ -14,6 +14,11 @@ non-removable; supports-cqe; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x40000000 0x8000000>; + qcom,iommu-geometry = <0x40000000 0x8000000>; + vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 570000>; diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi b/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi index eb895911da7c..3921a6176a7c 100644 --- a/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-m2-ep.dtsi @@ -14,6 +14,11 @@ non-removable; supports-cqe; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x40000000 0x8000000>; + qcom,iommu-geometry = <0x40000000 0x8000000>; + vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <0 570000>; From 0fb064f1f0f6da3c17310b696ff94b19d010d2d5 Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Tue, 10 Aug 2021 16:08:36 +0530 Subject: [PATCH 1692/1809] ARM: dts: msm: NTN3 De-emphasis values update CPE Change is to pass the values to be updated for de-empasis on NTN3 CPE. Change-Id: Ia7b5761a1229b77d9d71203388a61c99ff244957 --- qcom/sdxlemur-mtp-cpe.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 38cdf380631b..32f107c6dacd 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -86,6 +86,15 @@ ep-reset-reg = <0x801210>; ep-reset-gpio-mask = <0xf>; dump-regs = <0x801330 0x801350 0x801370>; + reg_update = <0x82c030 0x1 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x2 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x8 + 0x828000 0x1 + 0x82bd00 0x8>; }; }; From bf94c9f0f41f5c01713ea2264cd4b3311a142b7c Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Thu, 26 Aug 2021 18:29:34 +0530 Subject: [PATCH 1693/1809] ARM: dts: qcom: PCIe to Gen3 for NTN3 CPE Pine1x Change speed to Gen3 for CPE NTN3 switch devices on CPE Pine 1x platform. Change-Id: I53c538468ad379a9c6046cba32241e9376724bb1 --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 22600ce00a35..4f653deecd4d 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -36,6 +36,22 @@ }; }; +&pcie_i2c_ctrl { + reg_update = <0x82c030 0x1 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x2 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x8 + 0x828000 0x1 + 0x82bd00 0x8 + 0x82c01c 0x10 + 0x82c030 0xf + 0x828000 0xf + 0x82b268 0x2>; +}; + &wifi0 { status = "ok"; }; From ee63b78dc085edfa8563a0ba22fcc342eb8dfb81 Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Mon, 30 Aug 2021 11:47:55 -0700 Subject: [PATCH 1694/1809] ARM: dts: msm: Pin config for AQR and Napa INTN_WOL Enable pin control for qps615 that is necessary to configure the SDX65 GPIO pins for Wake on LAN support. Change-Id: Ic5d6d76677e195fc3dec7780d99b5cf50718b8b1 --- qcom/sdxlemur-mtp-cpe.dtsi | 6 ++++++ qcom/sdxlemur-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index d6e2e5f91010..266d6df33c5c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -139,6 +139,9 @@ qps615_eth0,qps615_eth0@pcie0_rp { reg = <0x0 0x0 0x0 0x0 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + compatible = "qcom,ioss-v2-device"; qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; @@ -161,6 +164,9 @@ qps615_eth1,qps615_eth1@pcie0_rp { reg = <0x100 0x0 0x0 0x0 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&napa_intn_wol_sig>; + compatible = "qcom,ioss-v2-device"; qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth1>; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 60534b7cb2bb..4f5fb3392076 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -1699,5 +1699,33 @@ }; }; }; + + qps615_intn_wol { + aqr_intn_wol_sig: aqr_intn_wol_sig { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + input-enable; + bias-disable; + }; + }; + + napa_intn_wol_sig: napa_intn_wol_sig { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + input-enable; + bias-disable; + }; + }; + }; }; }; From 81cd59810bee7a90a0fa0101ba2ffb7dd7ed9816 Mon Sep 17 00:00:00 2001 From: Eliad Ben Yishay Date: Thu, 15 Jul 2021 14:17:16 +0300 Subject: [PATCH 1695/1809] ARM: dts: msm: Add dual NIC IPA support Adding second ethernet client ipa smmu mapping Change-Id: I1f0e6203b393aacf470aac3b0b28ba4e47d77377 Acked-by: Eliad Ben Yishay --- qcom/sdxlemur.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index ece25094a193..28c93114d8e3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1164,10 +1164,16 @@ }; ipa_eth_group1: ipa_eth_group1 { - qcom,iommu-dma-addr-pool = <0x80000000 0x0fe20000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x07f00000>; qcom,iommu-dma = "atomic"; }; + ipa_eth_group2: ipa_eth_group2 { + qcom,iommu-dma-addr-pool = <0x87f10000 0x07f00000>; + qcom,iommu-dma = "atomic"; + }; + + ipa_hw: qcom,ipa@03e00000 { compatible = "qcom,ipa"; mboxes = <&qmp_aop 0>; @@ -1268,7 +1274,8 @@ ipa_smmu_eth1: ipa_smmu_eth1 { compatible = "qcom,ipa-smmu-eth1-cb"; iommus = <&apps_smmu 0x5E4 0x0>; - qcom,iommu-dma = "atomic"; + qcom,shared-cb; + qcom,iommu-group = <&ipa_eth_group2>; }; ipa_smmu_wlan1: ipa_smmu_wlan1 { From 3ebe568edb16223e74dcfc0fbbea9f1e565017ca Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Fri, 13 Aug 2021 13:42:11 +0530 Subject: [PATCH 1696/1809] ARM: dts: msm: qcom: Add pm7250b support for Blair-MTP-USBC platform Add pm7250b support for Blair-MTP-USBC platform. Change-Id: I49357ecb0c2ddcc3d2e6da9c6b7a677f278bc797 --- qcom/blair-mtp-usbc-overlay.dts | 5 +++++ qcom/blair-mtp-usbc.dts | 5 +++++ qcom/blair-mtp-usbc.dtsi | 1 - 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/blair-mtp-usbc-overlay.dts b/qcom/blair-mtp-usbc-overlay.dts index 32fd182f64d7..d6477987dbeb 100644 --- a/qcom/blair-mtp-usbc-overlay.dts +++ b/qcom/blair-mtp-usbc-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "blair-mtp-usbc.dtsi" +#include "holi-mtp-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. Blair MTP USBC audio"; @@ -26,6 +27,10 @@ status = "disabled"; }; +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; + &wcd938x_tx_slave { status = "ok"; }; diff --git a/qcom/blair-mtp-usbc.dts b/qcom/blair-mtp-usbc.dts index c68cd7fefd93..b69c98426a97 100644 --- a/qcom/blair-mtp-usbc.dts +++ b/qcom/blair-mtp-usbc.dts @@ -2,9 +2,14 @@ #include "blair.dtsi" #include "blair-mtp-usbc.dtsi" +#include "holi-mtp-pm7250b.dtsi" / { model = "Qualcomm Technologies, Inc. BLAIR MTP USBC audio"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; qcom,board-id = <8 1>; }; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blair-mtp-usbc.dtsi b/qcom/blair-mtp-usbc.dtsi index 1722849a48fa..47a4f94d596c 100644 --- a/qcom/blair-mtp-usbc.dtsi +++ b/qcom/blair-mtp-usbc.dtsi @@ -1,7 +1,6 @@ #include "holi-audio-overlay.dtsi" #include #include -#include "holi-pm7250b.dtsi" #include "holi-pmic-overlay-pm6125.dtsi" #include "holi-thermal-overlay-pm6125.dtsi" #include "display/holi-sde-display-mtp-pm6125.dtsi" From 2da93d1f34b82ff17aa856d65c054d27b73b77d5 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Thu, 17 Jun 2021 17:26:10 +0530 Subject: [PATCH 1697/1809] bindings: arm: msm: Add documentation for sdx ipc driver This is a snapshot of the sdx ipc driverdriver as of msm-4.14 commit a5650700 ("drivers: qcom: sdx_ext_ipc: keep wakeup irq always on"). Change-Id: I27eb35b33284be8c221cd873323a488101a2f5e8 --- bindings/arm/msm/sdx-ext-ipc.txt | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 bindings/arm/msm/sdx-ext-ipc.txt diff --git a/bindings/arm/msm/sdx-ext-ipc.txt b/bindings/arm/msm/sdx-ext-ipc.txt new file mode 100644 index 000000000000..76b230ed8b41 --- /dev/null +++ b/bindings/arm/msm/sdx-ext-ipc.txt @@ -0,0 +1,34 @@ +Modem chipset attached to Application processor + +Modem chipset can be connected to an external apss processor. The control +channel between the two chipsets consists of gpios that can relay the +state of one subsytem to another. Modem can indicate different events +(bootup/crash etc.) to AP and can get the same information from AP. + +Required Properties: +- compatible: "qcom,sdx-ext-ipc". + +Optional named gpio properties: +- qcom,status-out-gpio: gpio to indicate the boot status to remote processor. + +- qcom,status-in-gpio: gpio for remote processor to indicate the boot status. + +- qcom,status-out2-gpio: gpio to indicate to remote processor that it is in + E911 call or doing firmware upgrade. + +- qcom,default-policy-nop: Set default policy from PANIC to NOP. + +- qcom,wakeup-gpio-out: gpio to wakeup remote AP or modem. + +- qcom,wakeup-gpio-in: input gpio to receive wakeup signal from remote AP or + modem. + +Example: + sdx_ext_ipc: qcom,sdx_ext_ipc { + compatible = "qcom,sdx-ext-ipc"; + qcom,status-in-gpio = <&tlmm 64 0x00>; + qcom,status-out-gpio = <&tlmm 63 0x00>; + qcom,status-out2-gpio = <&tlmm 66 0x00>; + qcom,wakeup-gpio-in = <&tlmm 67 0x00>; + qcom,wakeup-gpio-out = <&tlmm 68 0x00>; + }; From fdba5e3f1dad1a99f8a79ae80b9c0b5fbb9bf4f2 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 27 Jul 2021 17:11:39 +0530 Subject: [PATCH 1698/1809] ARM: dts: qcom: Add device tree entry for sdx ipc driver Add device tree entry for sdx ipc driver listing gpios needed to communicate with APQ. Change-Id: I4511c6e020e268e67542929fb7d9809e22971391 --- qcom/sdxlemur.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index ece25094a193..447ea0b775f8 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1427,6 +1427,13 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; }; + + sdx_ext_ipc: qcom,sdx_ext_ipc { + compatible = "qcom,sdx-ext-ipc"; + qcom,status-in-gpio = <&tlmm 65 0x00>; + qcom,status-out-gpio = <&tlmm 44 0x00>; + qcom,status-out2-gpio = <&tlmm 45 0x00>; + }; }; #include "sdxlemur-pinctrl.dtsi" From 5aa3493295a019a4c1a051d799c769843167347f Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Wed, 1 Sep 2021 11:09:06 +0530 Subject: [PATCH 1699/1809] ARM: dts: qcom: Add ipq807x_attach property for IPQ807x host ipq807x_attach property is needed to distinguish between IPQ807x and other hosts. Change-Id: Ied55a2d22d1f5df0f396044b6982ee342af59155 --- qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi index 20bd6389e01c..85f31d088a85 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -63,3 +63,7 @@ &usb { qcom,iommu-dma = "bypass"; }; + +&sdx_ext_ipc { + ipq807x_attach = <1>; +}; From 292701def4689e717c65c4483b07def19e76462c Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Wed, 25 Aug 2021 17:53:29 +0300 Subject: [PATCH 1700/1809] ARM: dts: msm: enable reg dump collection Enable reg dump collection. Change-Id: I38e13d1e0d7d88fe95d3f5affcd9d8ec99b00c07 Acked-by: Nadav Levintov --- qcom/sdxlemur.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index ece25094a193..ba44fb22b846 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1184,6 +1184,7 @@ qcom,ipa-hw-mode = <0>; qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; + qcom,entire-ipa-block-size = <0x200000>; qcom,use-ipa-tethering-bridge; qcom,use-tput-estmation-pipe; qcom,mhi-event-ring-id-limits = <9 15>; /* start and end */ @@ -1197,6 +1198,9 @@ qcom,ipa-endp-delay-wa-v2; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; qcom,lan-rx-napi; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From ef467db970a3a785e153f43570317fcf25ad0172 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Thu, 2 Sep 2021 02:11:25 -0700 Subject: [PATCH 1701/1809] ARM: dts: msm: Fix EP PCIe perst pinctrl settings on sdxlemur Fix EP PCIe perst pinctrl settings on sdxlemur. Change-Id: I24872499a73706e9711bcaea37fa38ae15901fa7 --- qcom/sdxlemur-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 4f5fb3392076..d75d1297b4cc 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -288,6 +288,11 @@ pcie_ep_perst_default: pcie_ep_perst_default { mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { pins = "gpio57"; drive-strength = <2>; bias-pull-down; From 83138d60bd304cc9464ad4021554b93e776d7fe9 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 17 Aug 2021 15:40:02 +0530 Subject: [PATCH 1702/1809] ARM: dts: msm: remove qcom,power-always-on dt property Remove the qcom,power-always-on dt property for the holi, shima, yupik and lahaina targets as its support is removed from driver. Change-Id: Ia35844b02bb2e4da7d36ef7b7f260c34da4fc861 --- bindings/iommu/arm,smmu.txt | 7 ------- qcom/msm-arm-smmu-holi.dtsi | 1 - qcom/msm-arm-smmu-lahaina.dtsi | 1 - qcom/msm-arm-smmu-shima.dtsi | 1 - qcom/msm-arm-smmu-yupik.dtsi | 1 - 5 files changed, 11 deletions(-) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 29e79cddee88..9e3e515e4e96 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -182,13 +182,6 @@ conditions. that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). -- qcom,power-always-on: - Boolean property which indicates that votes for power - resources (i.e. regulators, clocks, buses) should - always be maintained. This is required when the latency - for the SMMU's operation is greatly increased by adding and - removing votes for power resources. - ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index b5011e9e547b..b8e6c719af6c 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -7,7 +7,6 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; - qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index 862492a73ce7..edadc0b0293c 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -15,7 +15,6 @@ #address-cells = <1>; ranges; dma-coherent; - qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cc_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index f5ce12811ba4..69a7044155d4 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -15,7 +15,6 @@ #address-cells = <1>; ranges; dma-coherent; - qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index de5f1e65b6f5..833995eda61c 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -15,7 +15,6 @@ #address-cells = <1>; ranges; dma-coherent; - qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, From 555600cc23faf3709e664d989ac11620c55d1ed9 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 2 Sep 2021 16:01:28 +0530 Subject: [PATCH 1703/1809] ARM: dts: msm: Add keepalive flag for QUP for Blair/Holi Add keep-alive flag for QUP node to keep a minimal vote (19.2MHz) for QUP clocks in active state. Change-Id: Iee15a810eae3ba161dc883a049585470b6858e2a --- qcom/blair.dtsi | 1 + qcom/holi.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 48af98cc21f4..ea1fbcdd046c 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1000,6 +1000,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index cd8d005b93f2..fdf4ef506bb9 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1013,6 +1013,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; From 5f93aa5dae1bdb6a1442a199d6f30a6821e4ee6a Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 3 Sep 2021 14:36:47 +0530 Subject: [PATCH 1704/1809] ARM: dts: msm: Restore SDCC registers once Resuming from CX/XO Defines the restore-after-cx-collapse property for SDCC controller. This basically lets the driver know that software needs to save the SDCC register contents before the CX/XO event and restore the SDCC register contents after coming out of CX/XO event. SDCC controller is not supporting retention of CX PC hence this change is needed. Change-Id: I719e7de2143edc457e706a66279bde816296ec73 --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 1 - qcom/sdxlemur.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 6a400fbe2c40..b86320708b1f 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -14,7 +14,6 @@ reg = <0x08804000 0x1000>, <0x08805000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; - qcom,restore-after-cx-collapse; mmc-ddr-1_8v; mmc-hs200-1_8v; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 28c93114d8e3..12f065e72085 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -580,6 +580,7 @@ clock-names = "core", "iface"; bus-width = <4>; + qcom,restore-after-cx-collapse; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; From 6353e4f77fba3a5b3c13ea8350410d18ee8a6024 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 1 Sep 2021 15:29:50 +0530 Subject: [PATCH 1705/1809] ARM: dts: msm: Remove separate DT for digital mics for Yupik Remove separate DT support for digital mics for Yupik, YupikP and Yupik LTE on IDPS. Change-Id: Ic2b527efa014078bcd13279d9570dcfc6be41166 --- qcom/Makefile | 6 ------ qcom/yupik-idps-digital-mics-overlay.dts | 11 ----------- qcom/yupik-idps-digital-mics.dts | 10 ---------- qcom/yupik-idps-digital-mics.dtsi | 4 ---- qcom/yupikp-idps-digital-mics-overlay.dts | 11 ----------- qcom/yupikp-idps-digital-mics.dts | 10 ---------- qcom/yupikp-idps-digital-mics.dtsi | 1 - 7 files changed, 53 deletions(-) delete mode 100644 qcom/yupik-idps-digital-mics-overlay.dts delete mode 100644 qcom/yupik-idps-digital-mics.dts delete mode 100644 qcom/yupik-idps-digital-mics.dtsi delete mode 100644 qcom/yupikp-idps-digital-mics-overlay.dts delete mode 100644 qcom/yupikp-idps-digital-mics.dts delete mode 100644 qcom/yupikp-idps-digital-mics.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 0e4c4c177b6a..c556c7a8e8dc 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -204,13 +204,11 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-idp-overlay.dtbo \ yupik-atp-overlay.dtbo \ yupik-qrd-overlay.dtbo \ - yupik-idps-digital-mics-overlay.dtbo \ yupik-idps-amoled-overlay.dtbo \ yupik-idp-pm7250b-overlay.dtbo \ yupikp-idp-overlay.dtbo \ yupikp-atp-overlay.dtbo \ yupikp-qrd-overlay.dtbo \ - yupikp-idps-digital-mics-overlay.dtbo \ yupikp-idps-amoled-overlay.dtbo \ yupik-iot-idp-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ @@ -226,13 +224,11 @@ yupik-rumi-overlay.dtbo-base := yupik.dtb yupik-idp-overlay.dtbo-base := yupik.dtb yupik-atp-overlay.dtbo-base := yupik.dtb yupik-qrd-overlay.dtbo-base := yupik.dtb -yupik-idps-digital-mics-overlay.dtbo-base := yupik.dtb yupik-idps-amoled-overlay.dtbo-base := yupik.dtb yupik-idp-pm7250b-overlay.dtbo-base := yupik.dtb yupikp-idp-overlay.dtbo-base := yupikp.dtb yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb -yupikp-idps-digital-mics-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb @@ -247,13 +243,11 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ yupik-atp.dtb \ yupik-qrd.dtb \ - yupik-idps-digital-mics.dtb \ yupik-idps-amoled.dtb \ yupik-idp-pm7250b.dtb \ yupikp-idp.dtb \ yupikp-atp.dtb \ yupikp-qrd.dtb \ - yupikp-idps-digital-mics.dtb \ yupikp-idps-amoled.dtb \ yupik-iot-idp.dtb \ yupik-iot-qrd.dtb \ diff --git a/qcom/yupik-idps-digital-mics-overlay.dts b/qcom/yupik-idps-digital-mics-overlay.dts deleted file mode 100644 index 4f1b65e661ff..000000000000 --- a/qcom/yupik-idps-digital-mics-overlay.dts +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "yupik-idps-digital-mics.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Yupik IDPS + DIGITAL MICS"; - compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - qcom,msm-id = <475 0x10000>, <515 0x10000>; - qcom,board-id = <34 1>; -}; diff --git a/qcom/yupik-idps-digital-mics.dts b/qcom/yupik-idps-digital-mics.dts deleted file mode 100644 index 0adab7cdd2c4..000000000000 --- a/qcom/yupik-idps-digital-mics.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "yupik.dtsi" -#include "yupik-idps-digital-mics.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Yupik IDPS + DIGITAL MICS"; - compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - qcom,board-id = <34 1>; -}; diff --git a/qcom/yupik-idps-digital-mics.dtsi b/qcom/yupik-idps-digital-mics.dtsi deleted file mode 100644 index 885e5af51402..000000000000 --- a/qcom/yupik-idps-digital-mics.dtsi +++ /dev/null @@ -1,4 +0,0 @@ -#include "yupik-idp.dtsi" - -&soc { -}; diff --git a/qcom/yupikp-idps-digital-mics-overlay.dts b/qcom/yupikp-idps-digital-mics-overlay.dts deleted file mode 100644 index ede5df06f0b6..000000000000 --- a/qcom/yupikp-idps-digital-mics-overlay.dts +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "yupikp-idps-digital-mics.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. YupikP IDPS + DIGITAL MICS"; - compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; - qcom,msm-id = <499 0x10000>; - qcom,board-id = <34 1>; -}; diff --git a/qcom/yupikp-idps-digital-mics.dts b/qcom/yupikp-idps-digital-mics.dts deleted file mode 100644 index d798a6a6a2d0..000000000000 --- a/qcom/yupikp-idps-digital-mics.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "yupikp.dtsi" -#include "yupikp-idps-digital-mics.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. YupikP IDPS + DIGITAL MICS"; - compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; - qcom,board-id = <34 1>; -}; diff --git a/qcom/yupikp-idps-digital-mics.dtsi b/qcom/yupikp-idps-digital-mics.dtsi deleted file mode 100644 index 12c906256483..000000000000 --- a/qcom/yupikp-idps-digital-mics.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "yupik-idps-digital-mics.dtsi" From baaceca46e4dc9fd140c765251a4c8941886f204 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 1 Sep 2021 15:36:25 +0530 Subject: [PATCH 1706/1809] ARM: dts: msm: Add support for HSP for Yupik Add device tree support for HSP for Yupik, YupikP and Yupik LTE platform. Change-Id: Ie51b2c20afb0e5ae824d1948f85da8437fe7928e --- qcom/Makefile | 6 ++++++ qcom/yupik-hsp.dts | 9 +++++++++ qcom/yupik-hsp.dtsi | 3 +++ qcom/yupik-idp-hsp-overlay.dts | 11 +++++++++++ qcom/yupik-idp-hsp.dts | 10 ++++++++++ qcom/yupik-idp-hsp.dtsi | 4 ++++ qcom/yupikp-hsp.dts | 9 +++++++++ qcom/yupikp-hsp.dtsi | 3 +++ qcom/yupikp-idp-hsp-overlay.dts | 11 +++++++++++ qcom/yupikp-idp-hsp.dts | 10 ++++++++++ qcom/yupikp-idp-hsp.dtsi | 2 ++ 11 files changed, 78 insertions(+) create mode 100644 qcom/yupik-hsp.dts create mode 100644 qcom/yupik-hsp.dtsi create mode 100644 qcom/yupik-idp-hsp-overlay.dts create mode 100644 qcom/yupik-idp-hsp.dts create mode 100644 qcom/yupik-idp-hsp.dtsi create mode 100644 qcom/yupikp-hsp.dts create mode 100644 qcom/yupikp-hsp.dtsi create mode 100644 qcom/yupikp-idp-hsp-overlay.dts create mode 100644 qcom/yupikp-idp-hsp.dts create mode 100644 qcom/yupikp-idp-hsp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index c556c7a8e8dc..5e0161ebb276 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -206,10 +206,12 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-qrd-overlay.dtbo \ yupik-idps-amoled-overlay.dtbo \ yupik-idp-pm7250b-overlay.dtbo \ + yupik-idp-hsp-overlay.dtbo \ yupikp-idp-overlay.dtbo \ yupikp-atp-overlay.dtbo \ yupikp-qrd-overlay.dtbo \ yupikp-idps-amoled-overlay.dtbo \ + yupikp-idp-hsp-overlay.dtbo \ yupik-iot-idp-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ yupik-iot-hsp-overlay.dtbo \ @@ -226,10 +228,12 @@ yupik-atp-overlay.dtbo-base := yupik.dtb yupik-qrd-overlay.dtbo-base := yupik.dtb yupik-idps-amoled-overlay.dtbo-base := yupik.dtb yupik-idp-pm7250b-overlay.dtbo-base := yupik.dtb +yupik-idp-hsp-overlay.dtbo-base := yupik-hsp.dtb yupikp-idp-overlay.dtbo-base := yupikp.dtb yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb +yupikp-idp-hsp-overlay.dtbo-base := yupikp-hsp.dtb yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb @@ -245,10 +249,12 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-qrd.dtb \ yupik-idps-amoled.dtb \ yupik-idp-pm7250b.dtb \ + yupik-idp-hsp.dtb \ yupikp-idp.dtb \ yupikp-atp.dtb \ yupikp-qrd.dtb \ yupikp-idps-amoled.dtb \ + yupikp-idp-hsp.dtb \ yupik-iot-idp.dtb \ yupik-iot-qrd.dtb \ yupik-iot-hsp.dtb \ diff --git a/qcom/yupik-hsp.dts b/qcom/yupik-hsp.dts new file mode 100644 index 000000000000..da97abe6dc64 --- /dev/null +++ b/qcom/yupik-hsp.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupik-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP HSP + SoC"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <0 1>; +}; diff --git a/qcom/yupik-hsp.dtsi b/qcom/yupik-hsp.dtsi new file mode 100644 index 000000000000..662c0725b7ae --- /dev/null +++ b/qcom/yupik-hsp.dtsi @@ -0,0 +1,3 @@ +#include "yupik.dtsi" +/ { +}; diff --git a/qcom/yupik-idp-hsp-overlay.dts b/qcom/yupik-idp-hsp-overlay.dts new file mode 100644 index 000000000000..f0dfb995e4a4 --- /dev/null +++ b/qcom/yupik-idp-hsp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-idp-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP + HSP"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,msm-id = <475 0x10000>, <515 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-idp-hsp.dts b/qcom/yupik-idp-hsp.dts new file mode 100644 index 000000000000..4ab8c6224e2c --- /dev/null +++ b/qcom/yupik-idp-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-hsp.dtsi" +#include "yupik-idp-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IDP + HSP"; + compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-idp-hsp.dtsi b/qcom/yupik-idp-hsp.dtsi new file mode 100644 index 000000000000..885e5af51402 --- /dev/null +++ b/qcom/yupik-idp-hsp.dtsi @@ -0,0 +1,4 @@ +#include "yupik-idp.dtsi" + +&soc { +}; diff --git a/qcom/yupikp-hsp.dts b/qcom/yupikp-hsp.dts new file mode 100644 index 000000000000..4d0392c3605f --- /dev/null +++ b/qcom/yupikp-hsp.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupikp-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDP HSP + SoC"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,board-id = <0 1>; +}; diff --git a/qcom/yupikp-hsp.dtsi b/qcom/yupikp-hsp.dtsi new file mode 100644 index 000000000000..0bbe35be28d2 --- /dev/null +++ b/qcom/yupikp-hsp.dtsi @@ -0,0 +1,3 @@ +#include "yupikp.dtsi" +/ { +}; diff --git a/qcom/yupikp-idp-hsp-overlay.dts b/qcom/yupikp-idp-hsp-overlay.dts new file mode 100644 index 000000000000..44bc8f59298f --- /dev/null +++ b/qcom/yupikp-idp-hsp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-idp-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDP + HSP"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,msm-id = <499 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-idp-hsp.dts b/qcom/yupikp-idp-hsp.dts new file mode 100644 index 000000000000..bee755e4726d --- /dev/null +++ b/qcom/yupikp-idp-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-hsp.dtsi" +#include "yupikp-idp-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IDP + HSP"; + compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-idp-hsp.dtsi b/qcom/yupikp-idp-hsp.dtsi new file mode 100644 index 000000000000..eb5f4b6d646a --- /dev/null +++ b/qcom/yupikp-idp-hsp.dtsi @@ -0,0 +1,2 @@ +#include "yupik-idp-hsp.dtsi" + From 2a6f0a620fab373030e15d63003cba1c2934008b Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Mon, 6 Sep 2021 10:15:20 +0530 Subject: [PATCH 1707/1809] ARM: dts: qcom: Add IPA register for QCN9000 Add IPA SMMU register name and address for QCN9000 in sdxlemur. Change-Id: Ifcf4ce6fe78342aeb889f10f276625fd9293bd3e --- qcom/sdxlemur-qcn9000.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index 98ab99e0af31..7f9e5b0799ea 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -27,6 +27,8 @@ wifi0: qcom,cnss-qcn9000@a0000000 { status = "disabled"; compatible = "qcom,cnss-qcn9000"; + reg = <0xc0000000 0x10000>; + reg-names = "smmu_iova_ipa"; memory-region = <&qcn9000_0_mem>; qcom,wlan-ramdump-dynamic = <0x400000>; qrtr_node_id = <0x0>; @@ -149,6 +151,8 @@ wifi1: qcom,cnss-qcn9000@b0000000 { status = "disabled"; compatible = "qcom,cnss-qcn9000"; + reg = <0xd0000000 0x10000>; + reg-names = "smmu_iova_ipa"; memory-region = <&qcn9000_1_mem>; qcom,wlan-ramdump-dynamic = <0x400000>; qrtr_node_id = <0x0>; From 726ff832d382768bc033e1cfd9f53091289c5295 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Fri, 3 Sep 2021 18:19:44 +0530 Subject: [PATCH 1708/1809] ARM: dts: msm: Add CNSS DT Node for HSP support Add CNSS DT node and enable other nodes for HSP support in Yupik MCC. Change-Id: Ica348afd9cf3a9973b187171485d0f0518662a60 --- qcom/yupik-hsp.dtsi | 23 ++++++++++++ qcom/yupik-idp-hsp-overlay.dts | 1 + qcom/yupik-idp-hsp.dtsi | 62 +++++++++++++++++++++++++++++++++ qcom/yupikp-idp-hsp-overlay.dts | 1 + 4 files changed, 87 insertions(+) diff --git a/qcom/yupik-hsp.dtsi b/qcom/yupik-hsp.dtsi index 662c0725b7ae..cc8df8e0eb0f 100644 --- a/qcom/yupik-hsp.dtsi +++ b/qcom/yupik-hsp.dtsi @@ -1,3 +1,26 @@ #include "yupik.dtsi" / { }; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk"; + + /delete-property/ protected-clocks; +}; + +&gcc_pcie_0_gdsc { + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + status = "ok"; +}; + +&gcc_usb30_sec_gdsc { + status = "ok"; +}; diff --git a/qcom/yupik-idp-hsp-overlay.dts b/qcom/yupik-idp-hsp-overlay.dts index f0dfb995e4a4..0b78f806c06b 100644 --- a/qcom/yupik-idp-hsp-overlay.dts +++ b/qcom/yupik-idp-hsp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupik-idp-hsp.dtsi" / { diff --git a/qcom/yupik-idp-hsp.dtsi b/qcom/yupik-idp-hsp.dtsi index 885e5af51402..2bcd7f793027 100644 --- a/qcom/yupik-idp-hsp.dtsi +++ b/qcom/yupik-idp-hsp.dtsi @@ -1,4 +1,66 @@ #include "yupik-idp.dtsi" +#include "qcx6490-cnss.dtsi" + +&wlan { + qcom,same-dt-multi-dev; +}; + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie1 { + status = "ok"; + qcom,boot-option = <0x0>; + qcom,ep-gpio = <&tlmm 19 0>; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default + &pcie1_ep_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default + &pcie1_ep_default>; +}; + +&pcie1_msi { + status = "ok"; +}; + +&pm7325_gpios { + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio8"; + function = "normal"; + output-low; + power-source = <0>; /* 1.8V input supply */ + }; + }; +}; &soc { + usb2_vbus_boost_reg: usb2_vbus_boost_reg { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpios = <&pm7325_gpios 8 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; +}; + +&usb1 { + vbus_dwc3-supply = <&usb2_vbus_boost_reg>; + qcom,default-mode-none; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; }; diff --git a/qcom/yupikp-idp-hsp-overlay.dts b/qcom/yupikp-idp-hsp-overlay.dts index 44bc8f59298f..da2b428bc2ed 100644 --- a/qcom/yupikp-idp-hsp-overlay.dts +++ b/qcom/yupikp-idp-hsp-overlay.dts @@ -1,6 +1,7 @@ /dts-v1/; /plugin/; +#include #include "yupikp-idp-hsp.dtsi" / { From 090a78fc7cfc95fb38238d6b5c898c8d6ef62982 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Fri, 23 Jul 2021 16:50:37 +0530 Subject: [PATCH 1709/1809] ARM: dts: msm: Add gpu-models property for yupik gpu Add gpu-models support for yupik gpu to specify different gpu model names and vulkan device IDs. Change-Id: Ie6340e55bc29f964a5058e77ced02ece764f4c89 --- qcom/yupik-gpu.dtsi | 24 ++++++++++++++++++++++-- qcom/yupik.dtsi | 5 +++++ 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c6542a40b826..c8a93bd66ed6 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -57,8 +57,8 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; - nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; - nvmem-cell-names = "speed_bin", "gaming_bin"; + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin", "gpu_model"; qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; @@ -119,6 +119,26 @@ }; }; + qcom,gpu-models { + #address-cells = <1>; + #size-cells = <0>; + compatible="qcom,gpu-models"; + + qcom,gpu-model@0 { + compatible="qcom,adreno-gpu-a643"; + qcom,gpu-model-id = <172>; + qcom,gpu-model = "Adreno643v1"; + qcom,vk-device-id = <0x06030501>; + }; + + qcom,gpu-model@1 { + compatible="qcom,adreno-gpu-a643"; + qcom,gpu-model-id = <190>; + qcom,gpu-model = "Adreno643v1"; + qcom,vk-device-id = <0x06030501>; + }; + }; + qcom,gpu-mempools { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 458ae1fc0cb8..e0e6a00dbd12 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -5047,6 +5047,11 @@ bits = <5 1>; }; + gpu_model_bin: gpu_model_bin@1e9 { + reg = <0x1e9 0x2>; + bits = <5 8>; + }; + feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; From 480fb60ae0f805841dd5267ce67ffa844aa17e45 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Tue, 7 Sep 2021 22:04:09 +0530 Subject: [PATCH 1710/1809] ARM: dts: msm: Add HSP property in CNSS DT Node Add TCS CMD and other required DT property in CNSS node Yupik HSP IDP device tree. Change-Id: I010ea657cc5cd236165156e4032c65f0f1947228 --- qcom/yupik-idp-hsp.dtsi | 60 ++++++----------------------------------- 1 file changed, 8 insertions(+), 52 deletions(-) diff --git a/qcom/yupik-idp-hsp.dtsi b/qcom/yupik-idp-hsp.dtsi index 2bcd7f793027..b510f487a94b 100644 --- a/qcom/yupik-idp-hsp.dtsi +++ b/qcom/yupik-idp-hsp.dtsi @@ -2,7 +2,15 @@ #include "qcx6490-cnss.dtsi" &wlan { + reg = <0xb0000000 0x10000>, + <0xb2e5510 0x5c0>; + reg-names = "smmu_iova_ipa", "tcs_cmd"; qcom,same-dt-multi-dev; + qcom,sw-ctrl-gpio = <&tlmm 86 0>; + use-pm-domain; + cnss-enable-self-recovery; + /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ + qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; }; &pcie0 { @@ -12,55 +20,3 @@ &pcie0_msi { status = "ok"; }; - -&pcie1 { - status = "ok"; - qcom,boot-option = <0x0>; - qcom,ep-gpio = <&tlmm 19 0>; - pinctrl-0 = <&pcie1_perst_default - &pcie1_clkreq_default - &pcie1_wake_default - &pcie1_ep_default>; - pinctrl-1 = <&pcie1_perst_default - &pcie1_clkreq_sleep - &pcie1_wake_default - &pcie1_ep_default>; -}; - -&pcie1_msi { - status = "ok"; -}; - -&pm7325_gpios { - usb2_vbus_boost { - usb2_vbus_boost_default: usb2_vbus_boost_default { - pins = "gpio8"; - function = "normal"; - output-low; - power-source = <0>; /* 1.8V input supply */ - }; - }; -}; - -&soc { - usb2_vbus_boost_reg: usb2_vbus_boost_reg { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus_boost_vreg"; - startup-delay-us = <4000>; - enable-active-high; - gpios = <&pm7325_gpios 8 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_boost_default>; - }; -}; - -&usb1 { - vbus_dwc3-supply = <&usb2_vbus_boost_reg>; - qcom,default-mode-none; - status = "ok"; -}; - -&usb2_phy1 { - status = "ok"; -}; From 33b05c303b8860bbf4972370474ee1b243e8a447 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 1 Sep 2021 21:26:44 +0530 Subject: [PATCH 1711/1809] dt-bindings: thermal: Add support to scale ibat current range to bcl driver Add support to scale ibat current for greater than default max supported ranges using range factor provided from nvmem. Change-Id: I63cc53cdba021300839695e9378fc320d57b2840 --- bindings/thermal/qcom-bcl-pmic5.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/bindings/thermal/qcom-bcl-pmic5.txt b/bindings/thermal/qcom-bcl-pmic5.txt index be9e2e0dcde5..6849dc7f1e11 100644 --- a/bindings/thermal/qcom-bcl-pmic5.txt +++ b/bindings/thermal/qcom-bcl-pmic5.txt @@ -41,6 +41,20 @@ Optional Parameters: current monitoring(CCM) hardware for battery current monitor. +- nvmem-cells: + Value type: + Definition: phandle pointing to a nvmem-cells node representing the + sdam registers that has information of ibat scaling range + factor.When defined, the bcl driver will use it to + scale ibat current greater than default supported range. + +- nvmem-cell-names: + Value type: + Definition: Specifies the given nvmem cell name as defined in + sdam node. + Documentation/devicetree/bindings/nvmem/nvmem.txt and also + example below. + Example: bcl@4200 { compatible = "qcom,bcl-v5"; @@ -51,4 +65,6 @@ Example: "bcl-lvl1"; qcom,pmic7-threshold; qcom,ibat-ccm-hw-support; + nvmem-cells = <&adc_scaling>; + nvmem-cell-names = "adc_scaling"; }; From 0700011aad2a4bf85c9da87bbeb8c767cc73a5e7 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sat, 28 Aug 2021 00:53:56 +0530 Subject: [PATCH 1712/1809] ARM: dts: qcom: Add support to read ibat_external_range from nvmem for yupik Add nvmem property cells to support ibat range factor reading. Change-Id: I6c400221325b98c1af066999200874b6643d6e36 --- qcom/yupik-pm7250b-thermal-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik-pm7250b-thermal-overlay.dtsi b/qcom/yupik-pm7250b-thermal-overlay.dtsi index b8096d2db3e9..359b1e081b24 100644 --- a/qcom/yupik-pm7250b-thermal-overlay.dtsi +++ b/qcom/yupik-pm7250b-thermal-overlay.dtsi @@ -8,6 +8,11 @@ #cooling-cells = <2>; }; +&pm7250b_bcl { + nvmem-cells = <&adc_scaling>; + nvmem-cell-names = "adc_scaling"; +}; + &thermal_zones { socd { cooling-maps { From 3aac9d7878e6fdf37be7e7cb1e76147b1ba91624 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 8 Sep 2021 15:39:51 +0530 Subject: [PATCH 1713/1809] ARM: dts: msm: Remove support for PCIE1 and USB3_SEC clocks on YUPIK HSP Remove support for PCIE1, USB3_SEC clocks and GDSC's as they are not required for YUPIK HSP attach. Change-Id: I1c4bfe0e5e7191bad8cd678bb14417b5ffae426e --- qcom/yupik-hsp.dtsi | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/qcom/yupik-hsp.dtsi b/qcom/yupik-hsp.dtsi index cc8df8e0eb0f..dc628b037acf 100644 --- a/qcom/yupik-hsp.dtsi +++ b/qcom/yupik-hsp.dtsi @@ -5,22 +5,26 @@ &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, - <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>; + <&pcie_0_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", - "pcie_0_pipe_clk", "pcie_1_pipe_clk"; + "pcie_0_pipe_clk"; - /delete-property/ protected-clocks; + protected-clocks = , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + ; }; &gcc_pcie_0_gdsc { status = "ok"; }; - -&gcc_pcie_1_gdsc { - status = "ok"; -}; - -&gcc_usb30_sec_gdsc { - status = "ok"; -}; From 94c343342ee0a2b6f496fd378780f9f8100604f9 Mon Sep 17 00:00:00 2001 From: Skylar Chang Date: Wed, 8 Sep 2021 16:12:56 -0700 Subject: [PATCH 1714/1809] ARM: dts: msm: put ipa_eth_group1 in bypass mode Putting ipa_eth_group1 in bypass in pcie mhi mode. Change-Id: I70bd90ee3e251d2bfad0c4d5a35181e596587c9f --- qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 4 ++++ qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi index 85f31d088a85..e5e92cbeabee 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -28,6 +28,10 @@ qcom,iommu-dma = "bypass"; }; +&ipa_eth_group2 { + qcom,iommu-dma = "bypass"; +}; + &ipa_hw { qcom,use-ipa-in-mhi-mode; ipa_smmu_ap { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 20bd6389e01c..969705c8f1dd 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -28,6 +28,10 @@ qcom,iommu-dma = "bypass"; }; +&ipa_eth_group2 { + qcom,iommu-dma = "bypass"; +}; + &ipa_hw { qcom,use-ipa-in-mhi-mode; ipa_smmu_ap { From 50332afde5bebe6bbc03aa3d4c2afec9e4abaad0 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Wed, 8 Sep 2021 13:09:46 +0530 Subject: [PATCH 1715/1809] ARM: dts: msm: Add support for HSP BT SoC This change adds support for HSP BT SoC. Change-Id: Iaa47b93ee5d1a07bdfa70f1069a027d2322d85b8 --- qcom/yupik-hsp.dtsi | 4 ++++ qcom/yupik-idp-hsp.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/yupik-hsp.dtsi b/qcom/yupik-hsp.dtsi index cc8df8e0eb0f..34bd251212eb 100644 --- a/qcom/yupik-hsp.dtsi +++ b/qcom/yupik-hsp.dtsi @@ -24,3 +24,7 @@ &gcc_usb30_sec_gdsc { status = "ok"; }; + +&bluetooth { + compatible = "qcom,qca6490"; +}; diff --git a/qcom/yupik-idp-hsp.dtsi b/qcom/yupik-idp-hsp.dtsi index 2bcd7f793027..e047e2326b18 100644 --- a/qcom/yupik-idp-hsp.dtsi +++ b/qcom/yupik-idp-hsp.dtsi @@ -64,3 +64,7 @@ &usb2_phy1 { status = "ok"; }; + +&bluetooth { + compatible = "qcom,qca6490"; +}; From e63430b0e110afb4b3afda8e796a38718494895e Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 20 Aug 2021 10:01:17 +0530 Subject: [PATCH 1716/1809] ARM: dts: msm: add nvmem cell for PMK8350 SDAM23 adc scaling Add a nvmem cell for adc scaling within PMK8350 SDAM127 for yupik. This is used by clients to read the type of ADC scaling used for ibat. Change-Id: I1978fcf5ca18dd878da20bdacaf7d8d3c643d199 --- qcom/pmk8350.dtsi | 7 +++++++ qcom/yupik-idp-pm7250b.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi index c8727dd690ee..2657e03b557f 100644 --- a/qcom/pmk8350.dtsi +++ b/qcom/pmk8350.dtsi @@ -226,6 +226,13 @@ reg = <0x8500>; }; + pmk8350_sdam_23: sdam@8600 { + compatible = "qcom,spmi-sdam"; + reg = <0x8600>; + #address-cells = <1>; + #size-cells = <1>; + }; + pmk8350_sdam_46: sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; diff --git a/qcom/yupik-idp-pm7250b.dtsi b/qcom/yupik-idp-pm7250b.dtsi index f7ca8842dab9..cc4a9865b4f9 100644 --- a/qcom/yupik-idp-pm7250b.dtsi +++ b/qcom/yupik-idp-pm7250b.dtsi @@ -148,6 +148,13 @@ reg = <9 SPMI_USID>; }; +&pmk8350_sdam_23 { + adc_scaling: scaling@bf { + reg = <0xbf 0x1>; + bits = <0 2>; + }; +}; + &pm7250b_vadc { interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; From 40526282ad5be26ee0ac1b5e491d69394f760159 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 26 Aug 2021 14:55:05 +0530 Subject: [PATCH 1717/1809] ARM: dts: msm: Prevent PM8008 LPM usage for all targets PMIC PM8008 LDOs do not support low power mode (LPM). If configured for LPM, these LDOs continue to operate in normal power mode (NPM) with the same quiescent current but a reduced over-current protection (OCP) threshold, which can result in OCP triggering. Fix all PM8008 LDOs to use normal power mode (NPM) alone to avoid this. Change-Id: I2c8961eaba0677768da09aeba577a32810c1d50f --- qcom/holi-pmic-overlay-pm6125.dtsi | 14 +++++++------- qcom/holi-pmic-overlay.dtsi | 14 +++++++------- qcom/lahaina-pmic-overlay.dtsi | 18 ++++++++++++++---- qcom/pm8008.dtsi | 14 +++++++------- qcom/scuba-iot.dtsi | 14 +++++++------- qcom/shima-pmic-overlay.dtsi | 18 ++++++++++++++---- qcom/yupik-pmic-overlay.dtsi | 18 ++++++++++++++---- 7 files changed, 70 insertions(+), 40 deletions(-) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index 444bc36e322a..cf4d9588b4c1 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -434,7 +434,7 @@ regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; qcom,min-dropout-voltage = <56000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -443,7 +443,7 @@ regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <96000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -452,7 +452,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <168000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -461,7 +461,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <136000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -470,7 +470,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <240000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4400 { @@ -479,7 +479,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1900000>; qcom,min-dropout-voltage = <48000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4400 { @@ -488,7 +488,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <96000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 4909413fd031..ded1ffc05851 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -463,7 +463,7 @@ regulator-min-microvolt = <528000>; regulator-max-microvolt = <1200000>; qcom,min-dropout-voltage = <120000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -472,7 +472,7 @@ regulator-min-microvolt = <528000>; regulator-max-microvolt = <1056000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -481,7 +481,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <192000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -490,7 +490,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2880000>; qcom,min-dropout-voltage = <160000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -499,7 +499,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <296000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4400 { @@ -508,7 +508,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1800000>; qcom,min-dropout-voltage = <72000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4400 { @@ -517,7 +517,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <112000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 43cdb6d6a80a..abfcdaaed6a5 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -106,7 +106,7 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1104000>; qcom,min-dropout-voltage = <224000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2I: pm8008i_l2: regulator@4100 { @@ -115,7 +115,7 @@ regulator-min-microvolt = <944000>; regulator-max-microvolt = <1152000>; qcom,min-dropout-voltage = <150000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3I: pm8008i_l3: regulator@4200 { @@ -124,6 +124,7 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; L4I: pm8008i_l4: regulator@4300 { @@ -132,6 +133,7 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <2904000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; L5I: pm8008i_l5: regulator@4400 { @@ -140,6 +142,7 @@ regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1800000>; qcom,min-dropout-voltage = <70000>; + qcom,hpm-min-load = <0>; }; L6I: pm8008i_l6: regulator@4500 { @@ -148,6 +151,7 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <2904000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; L7I: pm8008i_l7: regulator@4600 { @@ -156,6 +160,7 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; }; }; @@ -208,7 +213,7 @@ regulator-min-microvolt = <944000>; regulator-max-microvolt = <1152000>; qcom,min-dropout-voltage = <100000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2J: pm8008j_l2: regulator@4100 { @@ -217,7 +222,7 @@ regulator-min-microvolt = <944000>; regulator-max-microvolt = <1056000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3J: pm8008j_l3: regulator@4200 { @@ -226,6 +231,7 @@ regulator-min-microvolt = <1728000>; regulator-max-microvolt = <1800000>; qcom,min-dropout-voltage = <70000>; + qcom,hpm-min-load = <0>; }; L4J: pm8008j_l4: regulator@4300 { @@ -234,6 +240,7 @@ regulator-min-microvolt = <1728000>; regulator-max-microvolt = <1800000>; qcom,min-dropout-voltage = <70000>; + qcom,hpm-min-load = <0>; }; L5J: pm8008j_l5: regulator@4400 { @@ -242,6 +249,7 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <2904000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; L6J: pm8008j_l6: regulator@4500 { @@ -250,6 +258,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; L7J: pm8008j_l7: regulator@4600 { @@ -258,6 +267,7 @@ regulator-min-microvolt = <2808000>; regulator-max-microvolt = <3600000>; qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/pm8008.dtsi b/qcom/pm8008.dtsi index 07c8824e2c70..f4fc4e884ed2 100644 --- a/qcom/pm8008.dtsi +++ b/qcom/pm8008.dtsi @@ -67,7 +67,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1504000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -76,7 +76,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1504000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -85,7 +85,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -94,7 +94,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -103,7 +103,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4400 { @@ -112,7 +112,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4400 { @@ -121,7 +121,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 0c3a88a00323..1745280ef456 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1125,7 +1125,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1256000>; qcom,min-dropout-voltage = <75000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -1134,7 +1134,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1144000>; qcom,min-dropout-voltage = <187500>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -1143,7 +1143,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -1152,7 +1152,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -1161,7 +1161,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4500 { @@ -1170,7 +1170,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4600 { @@ -1179,7 +1179,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <1656000>; regulator-max-microvolt = <1896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index f9a6b808d651..0a676acdeb7b 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -403,7 +403,7 @@ regulator-min-microvolt = <224000>; regulator-max-microvolt = <1200000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2I: pm8008i_l2: regulator@4100 { @@ -412,7 +412,7 @@ regulator-min-microvolt = <264000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <184000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3I: pm8008i_l3: regulator@4200 { @@ -421,6 +421,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <96000>; + qcom,hpm-min-load = <0>; }; L4I: pm8008i_l4: regulator@4300 { @@ -429,6 +430,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <88000>; + qcom,hpm-min-load = <0>; }; L5I: pm8008i_l5: regulator@4400 { @@ -437,6 +439,7 @@ regulator-min-microvolt = <1544000>; regulator-max-microvolt = <1900000>; qcom,min-dropout-voltage = <152000>; + qcom,hpm-min-load = <0>; }; L6I: pm8008i_l6: regulator@4500 { @@ -445,6 +448,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; }; L7I: pm8008i_l7: regulator@4600 { @@ -453,6 +457,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <0>; }; }; }; @@ -505,7 +510,7 @@ regulator-min-microvolt = <288000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <160000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2J: pm8008j_l2: regulator@4100 { @@ -514,7 +519,7 @@ regulator-min-microvolt = <448000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <0>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3J: pm8008j_l3: regulator@4200 { @@ -523,6 +528,7 @@ regulator-min-microvolt = <1592000>; regulator-max-microvolt = <1950000>; qcom,min-dropout-voltage = <56000>; + qcom,hpm-min-load = <0>; }; L4J: pm8008j_l4: regulator@4300 { @@ -531,6 +537,7 @@ regulator-min-microvolt = <1504000>; regulator-max-microvolt = <3544000>; qcom,min-dropout-voltage = <0>; + qcom,hpm-min-load = <0>; }; L5J: pm8008j_l5: regulator@4400 { @@ -539,6 +546,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <104000>; + qcom,hpm-min-load = <0>; }; L6J: pm8008j_l6: regulator@4500 { @@ -547,6 +555,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <0>; + qcom,hpm-min-load = <0>; }; L7J: pm8008j_l7: regulator@4600 { @@ -555,6 +564,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; qcom,min-dropout-voltage = <0>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index 4ba57dd658b0..deb80ed30977 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -302,7 +302,7 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; qcom,min-dropout-voltage = <160000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2I: pm8008i_l2: regulator@4100 { @@ -311,7 +311,7 @@ regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <128000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3I: pm8008i_l3: regulator@4200 { @@ -320,6 +320,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <144000>; + qcom,hpm-min-load = <0>; }; L4I: pm8008i_l4: regulator@4300 { @@ -328,6 +329,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; }; L5I: pm8008i_l5: regulator@4400 { @@ -336,6 +338,7 @@ regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; qcom,min-dropout-voltage = <136000>; + qcom,hpm-min-load = <0>; }; L6I: pm8008i_l6: regulator@4500 { @@ -344,6 +347,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; }; L7I: pm8008i_l7: regulator@4600 { @@ -352,6 +356,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3000000>; qcom,min-dropout-voltage = <312000>; + qcom,hpm-min-load = <0>; }; }; }; @@ -404,7 +409,7 @@ regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <96000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L2J: pm8008j_l2: regulator@4100 { @@ -413,7 +418,7 @@ regulator-min-microvolt = <950000>; regulator-max-microvolt = <1250000>; qcom,min-dropout-voltage = <24000>; - qcom,hpm-min-load = <30000>; + qcom,hpm-min-load = <0>; }; L3J: pm8008j_l3: regulator@4200 { @@ -422,6 +427,7 @@ regulator-min-microvolt = <1460000>; regulator-max-microvolt = <1800000>; qcom,min-dropout-voltage = <224000>; + qcom,hpm-min-load = <0>; }; L4J: pm8008j_l4: regulator@4300 { @@ -430,6 +436,7 @@ regulator-min-microvolt = <1504000>; regulator-max-microvolt = <1600000>; qcom,min-dropout-voltage = <0>; + qcom,hpm-min-load = <0>; }; L5J: pm8008j_l5: regulator@4400 { @@ -438,6 +445,7 @@ regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2900000>; qcom,min-dropout-voltage = <104000>; + qcom,hpm-min-load = <0>; }; L6J: pm8008j_l6: regulator@4500 { @@ -446,6 +454,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; qcom,min-dropout-voltage = <112000>; + qcom,hpm-min-load = <0>; }; L7J: pm8008j_l7: regulator@4600 { @@ -454,6 +463,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; qcom,min-dropout-voltage = <96000>; + qcom,hpm-min-load = <0>; }; }; }; From c0246d6bf99a99e2e6a34ea500e2fe4bb5aaa1b4 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 2 Sep 2021 16:01:28 +0530 Subject: [PATCH 1718/1809] ARM: dts: msm: Add keepalive flag for QUP for Blair/Holi Add keep-alive flag for QUP node to keep a minimal vote (19.2MHz) for QUP clocks in active state. Change-Id: Iee15a810eae3ba161dc883a049585470b6858e2a --- qcom/blair.dtsi | 1 + qcom/holi.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index 48af98cc21f4..ea1fbcdd046c 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -1000,6 +1000,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index cd8d005b93f2..fdf4ef506bb9 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1013,6 +1013,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; From e306e9fc0d9283bd8361fdd2f82e6e17a7fce63b Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 16 Aug 2021 12:04:11 +0530 Subject: [PATCH 1719/1809] ARM: dts: msm: Skip BW vote for PM8008 used I2C SE node Enable flag "qcom,leica-used-i2c" to skip BW vote for PM8008 used I2C instance to prevent deadlock condition between regulator and clocks framework. Change-Id: Ie4746f615f2f348c0aa19c77ebe6313986bbda32 --- qcom/holi-pmic-overlay-pm6125.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index cb7c64fc36ce..444bc36e322a 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -389,6 +389,7 @@ #size-cells = <0>; status = "ok"; + qcom,leica-used-i2c; pm8008_8: qcom,pm8008@8 { compatible = "qcom,i2c-pmic"; reg = <0x8>; From ac78504d6365090879016dbc33468284c5052b05 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Mon, 13 Sep 2021 16:56:35 -0700 Subject: [PATCH 1720/1809] ARM: dts: msm: Disable L1 mode on sdxlemur ep variants Some sdxlemur ep variants run in HS only mode and enabling L1 is leading to instability in terms of enumeration failures. Disable L1 mode to avoid this. Change-Id: I06157fce096e594b82f4c333fceb13ca3107a6df --- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index 20bd6389e01c..39675d1fddbc 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -62,4 +62,7 @@ &usb { qcom,iommu-dma = "bypass"; + dwc3@a600000 { + snps,usb2-gadget-lpm-disable; + }; }; From 331c03ae238dfdb2aa8f517d9cce0b3f94a1298c Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Mon, 13 Sep 2021 16:42:41 +0800 Subject: [PATCH 1721/1809] ARM: dts: msm: Enable bluetooth for v2 sdxlemur Enable bluetooth for v2 sdxlemur. CRs-Fixed: 3034997 Change-Id: Ibc0a0e66a05e272875938764c987ef25cd6f58cb --- qcom/sdxlemur-v2-cdp.dts | 1 + qcom/sdxlemur-v2-mtp-mbb-emmc.dts | 1 + qcom/sdxlemur-v2-mtp-mbb.dts | 1 + qcom/sdxlemur-v2-mtp.dts | 1 + qcom/sdxlemur-v2-rcm-rc.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/qcom/sdxlemur-v2-cdp.dts b/qcom/sdxlemur-v2-cdp.dts index 56d5029dbfc3..769730839959 100644 --- a/qcom/sdxlemur-v2-cdp.dts +++ b/qcom/sdxlemur-v2-cdp.dts @@ -5,6 +5,7 @@ #include "sdxlemur-1024mb.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-cdp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP V2"; diff --git a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts index 9c559e9e1743..633ca94dcd73 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts @@ -5,6 +5,7 @@ #include "sdxlemur-1024mb.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC V2"; diff --git a/qcom/sdxlemur-v2-mtp-mbb.dts b/qcom/sdxlemur-v2-mtp-mbb.dts index de0389ed4adc..0dc789e85177 100644 --- a/qcom/sdxlemur-v2-mtp-mbb.dts +++ b/qcom/sdxlemur-v2-mtp-mbb.dts @@ -5,6 +5,7 @@ #include "sdxlemur-1024mb.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB V2"; diff --git a/qcom/sdxlemur-v2-mtp.dts b/qcom/sdxlemur-v2-mtp.dts index 21a9acca41ee..cac68602ccf4 100644 --- a/qcom/sdxlemur-v2-mtp.dts +++ b/qcom/sdxlemur-v2-mtp.dts @@ -5,6 +5,7 @@ #include "sdxlemur-1024mb.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP V2"; diff --git a/qcom/sdxlemur-v2-rcm-rc.dts b/qcom/sdxlemur-v2-rcm-rc.dts index 8bac601d1b38..5f66a7bfd927 100644 --- a/qcom/sdxlemur-v2-rcm-rc.dts +++ b/qcom/sdxlemur-v2-rcm-rc.dts @@ -5,6 +5,7 @@ #include "sdxlemur-1024mb.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-cdp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex V2"; From 179cd890edba080610e529cbaf83183dad245170 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Tue, 14 Sep 2021 17:47:16 +0530 Subject: [PATCH 1722/1809] ARM: dts: qcom: Remove redundant entries in sdxlemur-qcn9000.dtsi Redundant entries for wifi nodes, reserved-memory and pcie0_rp are defined in sdxlemur-qcn9000.dtsi. Remove the redundant entries as they are not required. Change-Id: Idb3e4f1a34d220076b5c797616d96d9bfa82f6c5 --- qcom/sdxlemur-qcn9000.dtsi | 295 ------------------------------------- 1 file changed, 295 deletions(-) diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index 7f9e5b0799ea..868bf6bec76c 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -297,298 +297,3 @@ }; }; }; - -&reserved_memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - qcn9000_0_mem: qcn9000_0_mem { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x3400000>; - status = "disabled"; - }; - - qcn9000_1_mem: qcn9000_1_mem { - compatible = "shared-dma-pool"; - alloc-ranges = <0x00000000 0xffffffff>; - reusable; - alignment = <0x400000>; - size = <0x3400000>; - status = "disabled"; - }; -}; - -&soc { - wifi0: qcom,cnss-qcn9000@a0000000 { - status = "disabled"; - compatible = "qcom,cnss-qcn9000"; - memory-region = <&qcn9000_0_mem>; - qcom,wlan-ramdump-dynamic = <0x400000>; - qrtr_node_id = <0x0>; - qca,auto-restart; - tgt-mem-mode = <0x1>; - board_id = <0xa4>; - - mhi,max-channels = <30>; - mhi,timeout = <10000>; - - mhi_channels { - #address-cells = <1>; - #size-cells = <0>; - - mhi_chan@0 { - reg = <0>; - label = "LOOPBACK"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@1 { - reg = <1>; - label = "LOOPBACK"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@4 { - reg = <4>; - label = "DIAG"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@5 { - reg = <5>; - label = "DIAG"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@20 { - reg = <20>; - label = "IPCR"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <1>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - mhi,auto-start; - }; - - mhi_chan@21 { - reg = <21>; - label = "IPCR"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - mhi,auto-queue; - mhi,auto-start; - }; - }; - - mhi_events { - #address-cells = <1>; - #size-cells = <0>; - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <1>; - mhi,priority = <0>; - mhi,brstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <0>; - mhi,msi = <2>; - mhi,priority = <1>; - mhi,brstmode = <2>; - }; - - mhi_event@2 { - status = "disabled"; - }; - }; - - mhi_devices { - #address-cells = <1>; - #size-cells = <0>; - mhi_qrtr { - mhi,chan = "IPCR"; - qcom,net-id = <0>; - }; - }; - }; - - wifi1: qcom,cnss-qcn9000@b0000000 { - status = "disabled"; - compatible = "qcom,cnss-qcn9000"; - memory-region = <&qcn9000_1_mem>; - qcom,wlan-ramdump-dynamic = <0x400000>; - qrtr_node_id = <0x0>; - qca,auto-restart; - tgt-mem-mode = <0x1>; - board_id = <0xa4>; - - mhi,max-channels = <30>; - mhi,timeout = <10000>; - - mhi_channels { - #address-cells = <1>; - #size-cells = <0>; - - mhi_chan@0 { - reg = <0>; - label = "LOOPBACK"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@1 { - reg = <1>; - label = "LOOPBACK"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@4 { - reg = <4>; - label = "DIAG"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@5 { - reg = <5>; - label = "DIAG"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - }; - - mhi_chan@20 { - reg = <20>; - label = "IPCR"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <1>; - mhi,data-type = <1>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - mhi,auto-start; - }; - - mhi_chan@21 { - reg = <21>; - label = "IPCR"; - mhi,num-elements = <32>; - mhi,event-ring = <1>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x14>; - mhi,auto-queue; - mhi,auto-start; - }; - }; - - mhi_events { - #address-cells = <1>; - #size-cells = <0>; - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <1>; - mhi,priority = <0>; - mhi,brstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <0>; - mhi,msi = <2>; - mhi,priority = <1>; - mhi,brstmode = <2>; - }; - - mhi_event@2 { - status = "disabled"; - }; - }; - - mhi_devices { - #address-cells = <1>; - #size-cells = <0>; - mhi_qrtr { - mhi,chan = "IPCR"; - qcom,net-id = <0>; - }; - }; - }; -}; - -&pcie0_rp { - #address-cells = <5>; - #size-cells = <0>; - - cnss_pci: cnss_pci { - reg = <0 0 0 0 0>; - #address-cells = <1>; - #size-cells = <1>; - - qcn9000_pci_iommu_group_0: qcn9000_pci_iommu_group_0 { - qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; - qcom,iommu-dma = "fastmap"; - qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", - "non-fatal"; - }; - - qcn9000_pci_iommu_group_1: qcn9000_pci_iommu_group_1 { - qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>; - qcom,iommu-dma = "fastmap"; - qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", - "non-fatal"; - }; - }; -}; From a1bcd20b8053784c807f326cb673062032b31d2e Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Tue, 14 Sep 2021 13:24:57 -0700 Subject: [PATCH 1723/1809] ARM: dts: msm: WoL IRQ support for AQR and Napa PHYs Add interrupt properties to configure the WoL interrupt lines that are connected to GPIO103 and GPIO81 on SDX65 from AQR PHY and Napa PHY, respectively. Change-Id: I8a2ce294b094c10ab93f1b21723549faff8f8c3a --- qcom/sdxlemur-mtp-cpe.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 266d6df33c5c..3daca4e6d64c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -146,6 +146,9 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; + interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; @@ -171,6 +174,9 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth1>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; From f0b8a9d204e211fd4eb88b9f88355f0376d2390f Mon Sep 17 00:00:00 2001 From: Sandeepkumar Yenugula Date: Wed, 18 Aug 2021 12:42:58 +0530 Subject: [PATCH 1724/1809] ARM: dts: msm: Add pm7250b dts variant for yupik iot Add pm7250b dts support for yupik iot. Change-Id: I610974ea62e20f4fa02a486d1a8c3f99f2e64dd4 --- qcom/Makefile | 12 ++++++++++++ qcom/yupik-iot-hsp-pm7250b-overlay.dts | 11 +++++++++++ qcom/yupik-iot-hsp-pm7250b.dts | 10 ++++++++++ qcom/yupik-iot-hsp-pm7250b.dtsi | 1 + qcom/yupik-iot-idp-pm7250b-overlay.dts | 11 +++++++++++ qcom/yupik-iot-idp-pm7250b.dts | 10 ++++++++++ qcom/yupik-iot-idp-pm7250b.dtsi | 1 + qcom/yupikp-iot-hsp-pm7250b-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-hsp-pm7250b.dts | 10 ++++++++++ qcom/yupikp-iot-hsp-pm7250b.dtsi | 1 + qcom/yupikp-iot-idp-pm7250b-overlay.dts | 11 +++++++++++ qcom/yupikp-iot-idp-pm7250b.dts | 10 ++++++++++ qcom/yupikp-iot-idp-pm7250b.dtsi | 1 + 13 files changed, 100 insertions(+) create mode 100644 qcom/yupik-iot-hsp-pm7250b-overlay.dts create mode 100644 qcom/yupik-iot-hsp-pm7250b.dts create mode 100644 qcom/yupik-iot-hsp-pm7250b.dtsi create mode 100644 qcom/yupik-iot-idp-pm7250b-overlay.dts create mode 100644 qcom/yupik-iot-idp-pm7250b.dts create mode 100644 qcom/yupik-iot-idp-pm7250b.dtsi create mode 100644 qcom/yupikp-iot-hsp-pm7250b-overlay.dts create mode 100644 qcom/yupikp-iot-hsp-pm7250b.dts create mode 100644 qcom/yupikp-iot-hsp-pm7250b.dtsi create mode 100644 qcom/yupikp-iot-idp-pm7250b-overlay.dts create mode 100644 qcom/yupikp-iot-idp-pm7250b.dts create mode 100644 qcom/yupikp-iot-idp-pm7250b.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 5e0161ebb276..bb62dc1d4f59 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -213,12 +213,16 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupikp-idps-amoled-overlay.dtbo \ yupikp-idp-hsp-overlay.dtbo \ yupik-iot-idp-overlay.dtbo \ + yupik-iot-idp-pm7250b-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ yupik-iot-hsp-overlay.dtbo \ + yupik-iot-hsp-pm7250b-overlay.dtbo \ yupik-iot-idps-amoled-overlay.dtbo \ yupikp-iot-idp-overlay.dtbo \ + yupikp-iot-idp-pm7250b-overlay.dtbo \ yupikp-iot-qrd-overlay.dtbo \ yupikp-iot-hsp-overlay.dtbo \ + yupikp-iot-hsp-pm7250b-overlay.dtbo \ yupikp-iot-idps-amoled-overlay.dtbo @@ -235,12 +239,16 @@ yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb yupikp-idp-hsp-overlay.dtbo-base := yupikp-hsp.dtb yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb +yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb +yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb +yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb +yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ @@ -256,12 +264,16 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupikp-idps-amoled.dtb \ yupikp-idp-hsp.dtb \ yupik-iot-idp.dtb \ + yupik-iot-idp-pm7250b.dtb \ yupik-iot-qrd.dtb \ yupik-iot-hsp.dtb \ yupik-iot-idps-amoled.dtb \ yupikp-iot-idp.dtb \ + yupikp-iot-idp-pm7250b.dtb \ yupikp-iot-qrd.dtb \ yupikp-iot-hsp.dtb \ + yupik-iot-hsp-pm7250b.dtb \ + yupikp-iot-hsp-pm7250b.dtb \ yupikp-iot-idps-amoled.dtb endif diff --git a/qcom/yupik-iot-hsp-pm7250b-overlay.dts b/qcom/yupik-iot-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..13601736b210 --- /dev/null +++ b/qcom/yupik-iot-hsp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IOT HSP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-iot-hsp-pm7250b.dts b/qcom/yupik-iot-hsp-pm7250b.dts new file mode 100644 index 000000000000..e45c59ae88d3 --- /dev/null +++ b/qcom/yupik-iot-hsp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IOT HSP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupik-iot-hsp-pm7250b.dtsi b/qcom/yupik-iot-hsp-pm7250b.dtsi new file mode 100644 index 000000000000..b1d6a3003180 --- /dev/null +++ b/qcom/yupik-iot-hsp-pm7250b.dtsi @@ -0,0 +1 @@ +#include "yupik-iot-idp-pm7250b.dtsi" diff --git a/qcom/yupik-iot-idp-pm7250b-overlay.dts b/qcom/yupik-iot-idp-pm7250b-overlay.dts new file mode 100644 index 000000000000..30427232e379 --- /dev/null +++ b/qcom/yupik-iot-idp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IOT IDP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-iot-idp-pm7250b.dts b/qcom/yupik-iot-idp-pm7250b.dts new file mode 100644 index 000000000000..02b9e75ec6ef --- /dev/null +++ b/qcom/yupik-iot-idp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupik-iot.dtsi" +#include "yupik-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IOT IDP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupik-iot-idp-pm7250b.dtsi b/qcom/yupik-iot-idp-pm7250b.dtsi new file mode 100644 index 000000000000..3d7faf4c3695 --- /dev/null +++ b/qcom/yupik-iot-idp-pm7250b.dtsi @@ -0,0 +1 @@ +#include "yupik-idp-pm7250b.dtsi" diff --git a/qcom/yupikp-iot-hsp-pm7250b-overlay.dts b/qcom/yupikp-iot-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..657d8bcd6537 --- /dev/null +++ b/qcom/yupikp-iot-hsp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IOT HSP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-iot-hsp-pm7250b.dts b/qcom/yupikp-iot-hsp-pm7250b.dts new file mode 100644 index 000000000000..1ebf928ea380 --- /dev/null +++ b/qcom/yupikp-iot-hsp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" +#include "yupikp-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IOT HSP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/yupikp-iot-hsp-pm7250b.dtsi b/qcom/yupikp-iot-hsp-pm7250b.dtsi new file mode 100644 index 000000000000..06877e6b4c19 --- /dev/null +++ b/qcom/yupikp-iot-hsp-pm7250b.dtsi @@ -0,0 +1 @@ +#include "yupik-iot-hsp-pm7250b.dtsi" diff --git a/qcom/yupikp-iot-idp-pm7250b-overlay.dts b/qcom/yupikp-iot-idp-pm7250b-overlay.dts new file mode 100644 index 000000000000..9b6f4f250fef --- /dev/null +++ b/qcom/yupikp-iot-idp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupikp-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IOT IDP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-iot-idp-pm7250b.dts b/qcom/yupikp-iot-idp-pm7250b.dts new file mode 100644 index 000000000000..250910551c11 --- /dev/null +++ b/qcom/yupikp-iot-idp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "yupikp-iot.dtsi" +#include "yupikp-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IOT IDP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/yupikp-iot-idp-pm7250b.dtsi b/qcom/yupikp-iot-idp-pm7250b.dtsi new file mode 100644 index 000000000000..b1d6a3003180 --- /dev/null +++ b/qcom/yupikp-iot-idp-pm7250b.dtsi @@ -0,0 +1 @@ +#include "yupik-iot-idp-pm7250b.dtsi" From 3c35317d06f5660059387c73975917c30fa34489 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 18 Aug 2021 18:52:25 +0530 Subject: [PATCH 1725/1809] ARM: dts: msm: Add GPU revision for Yupik A643 target Add compatible string for a643 GPU. Change-Id: I5f1478b591208de4df58b6754dfde8f50c22eb7b --- bindings/gpu/adreno.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index e828d5e1439d..9161b8075a6e 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -8,6 +8,7 @@ Required properties: Must include "qcom,adreno-gpu-a619-holi" for Holi target. Must include "qcom,adreno-gpu-a642" for Shima target. Must include "qcom,adreno-gpu-a642l" for Yupik target. + Must include "qcom,adreno-gpu-a643" for Yupik a643 target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. From 4316231b3fb272416ea26d2e87e9838d7f1d88bd Mon Sep 17 00:00:00 2001 From: Karthik Rudrapatna Date: Wed, 28 Jul 2021 12:10:56 -0700 Subject: [PATCH 1726/1809] ARM: dts: msm: Enable separate IPA instance ID and IOMMU group for Napa Added instance id & ipa_eth_group2 IOMMU group for Napa to support Dual NIC feature. Change-Id: I6fed914f054231b7fdb7a0bc6844b272be4916b4 --- qcom/sdxlemur-mtp-cpe.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 3daca4e6d64c..6515ea3928bd 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -68,7 +68,7 @@ ioss_qps615_eth1: qps615@eth1 { qcom,name = "eth1"; - qcom,ioss_instance = <0>; + qcom,ioss_instance = <1>; qcom,ioss_channels = <&ioss_qps615_rx>, @@ -178,7 +178,7 @@ interrupt-names = "wol_irq"; /* ipa shares this group */ - qcom,iommu-group = <&ipa_eth_group1>; + qcom,iommu-group = <&ipa_eth_group2>; #address-cells = <1>; #size-cells = <1>; From 06c95fccecc9eceb666480d7e8ee92790f8d9b6a Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Thu, 29 Jul 2021 18:00:59 -0700 Subject: [PATCH 1727/1809] ARM: dts: msm: add ntn3 ipa pcie changes for MBB Update IPA iossv2 pcie configuration changes. Change-Id: I18759aa2b9bfb7087744d22f376ee018412f05ff --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 4335ee88f0f6..68b6c30f9859 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -22,6 +22,38 @@ regulator-enable-ramp-delay = <2400>; }; + ioss_qps615_rx: qps615_rx@eth { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <128>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_qps615_tx: qps615_tx@eth { + qcom,dir-tx; + qcom,ring-size = <512>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_qps615_eth0: qps615@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_qps615_rx>, + <&ioss_qps615_tx>; + }; }; &i2c_3 { @@ -72,6 +104,19 @@ /* BDF 2.3.0 */ pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 { reg = <0x1800 0x0 0x0 0x0 0x0>; + qps615_eth0,qps615_eth0@pcie0_rp { + reg = <0x0 0x0 0x0 0x0 0x0>; + + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = <&ioss_qps615_eth0>; + + /* ipa shares this group */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + }; /* BDF 5.0.0 */ pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 { reg = <0x0 0x0 0x0 0x0 0x0>; From 09301e3a937b18b7ba71f24b86f56a5c6453c20a Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Wed, 15 Sep 2021 14:42:19 -0700 Subject: [PATCH 1728/1809] ARM: dts: msm: WoL IRQ support for AQR Add interrupt property to configure the WoL interrupt line connected to GPIO103 from AQR PHY for MBB platforms. Change-Id: I902832cc1b924d442351f80f73d148853acd3651 --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 68b6c30f9859..a1782da1890d 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -114,6 +114,9 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; + interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + #address-cells = <1>; #size-cells = <1>; }; From 19c8eec9487f6fac18e627804ba38aeed554c369 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Mon, 20 Sep 2021 11:30:24 -0700 Subject: [PATCH 1729/1809] ARM: dts: msm: Update CPU frequencies for sdxlemur v2 Update CPU frequencies to align with v2 timing closure. Change-Id: I0893fad31fc4929b62b8b169c562e93fecf595a7 --- qcom/sdxlemur-v2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 3740fd2d468c..43abbcc5540c 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -150,6 +150,14 @@ qcom,iommu-dma = "fastmap"; }; +&apsscc { + qcom,speed0-bin-v0 = + < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + < 576000000 RPMH_REGULATOR_LEVEL_SVS>, + < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, + < 1804800000 RPMH_REGULATOR_LEVEL_TURBO>; +}; + &cpufreq { qcom,cpufreq-table = < 345600 >, From b4aaf04cf22bd13859743664c1eec2513830b6f2 Mon Sep 17 00:00:00 2001 From: Karthik Rudrapatna Date: Mon, 23 Aug 2021 12:48:32 -0700 Subject: [PATCH 1730/1809] ARM: dts: msm: Separating AQR & Napa Ring descriptions Separated AQR & NAPA Ring descriptions for DUAL NIC support. Change-Id: If03eed546b9a12c6a15ac058076b762ef1e260f8 --- qcom/sdxlemur-mtp-cpe.dtsi | 40 ++++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 6515ea3928bd..234157134e2f 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -33,11 +33,11 @@ regulator-enable-ramp-delay = <2400>; }; - ioss_qps615_rx: qps615_rx@eth { + ioss_aqr_rx: qps615_rx@eth0 { qcom,dir-rx; qcom,rx-filter-ip; - qcom,ring-size = <128>; + qcom,ring-size = <1023>; qcom,buff-size = <2048>; qcom,mod-count-min = <64>; @@ -46,9 +46,33 @@ qcom,mod-usecs-max = <60>; }; - ioss_qps615_tx: qps615_tx@eth { + ioss_aqr_tx: qps615_tx@eth0 { qcom,dir-tx; - qcom,ring-size = <512>; + qcom,ring-size = <1023>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_napa_rx: qps615_rx@eth1 { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <127>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_napa_tx: qps615_tx@eth1 { + qcom,dir-tx; + qcom,ring-size = <511>; qcom,buff-size = <2048>; qcom,mod-count-min = <64>; @@ -62,8 +86,8 @@ qcom,ioss_instance = <0>; qcom,ioss_channels = - <&ioss_qps615_rx>, - <&ioss_qps615_tx>; + <&ioss_aqr_rx>, + <&ioss_aqr_tx>; }; ioss_qps615_eth1: qps615@eth1 { @@ -71,8 +95,8 @@ qcom,ioss_instance = <1>; qcom,ioss_channels = - <&ioss_qps615_rx>, - <&ioss_qps615_tx>; + <&ioss_napa_rx>, + <&ioss_napa_tx>; }; }; From 92c516bd0a5a96ea776d4e1e9953b67337200e7c Mon Sep 17 00:00:00 2001 From: chunquan Date: Fri, 24 Sep 2021 15:47:32 +0800 Subject: [PATCH 1731/1809] ARM: dts: msm: disable LAN RX NAPI Disable lan-rx-napi which use in ipa. IPA will not use napi_poll to fetch rx pkt. Change-Id: Ie15e871bbe1a198a076b41db32a65447572ce37b CRs-Fixed: 3029455 --- qcom/sdxlemur.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c6f4217a2bba..002dafe500d7 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1208,7 +1208,6 @@ qcom,register-collection-on-crash; qcom,testbus-collection-on-crash; qcom,non-tn-collection-on-crash; - qcom,lan-rx-napi; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; From 031c62802be47a7cf9f58bbd315c4d0c50a103c7 Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Thu, 23 Sep 2021 17:57:26 +0530 Subject: [PATCH 1732/1809] ARM: dts: qcom: Enable link enumeration via perst 1. Start link enumeration only after the perst de-assertion interrupt is received by the device, instead of enumeration in the probe function 2. Enabled no-m0-timeout, to make device not timeout waiting for M0. Change-Id: I4b96fcf87482b6fc6595743b78541e1c7820c013 --- qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi index e5e92cbeabee..b9cfadf6bab5 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -14,10 +14,12 @@ &pcie_ep { status = "ok"; + qcom,pcie-perst-enum; }; &mhi_device { status = "ok"; + qcom,no-m0-timeout; }; &mhi_net_device { From 583ee807800fd8e951a3304d8265cde1cf145cdf Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Mon, 20 Sep 2021 16:46:01 -0700 Subject: [PATCH 1733/1809] ARM: dts: msm: PHY supply DTSI properties Add PHY regulator supply properties for AQR and QCA. Change-Id: I966511b3679c6b9a7bc77c798d3e6c6a53c34c83 --- qcom/sdxlemur-mtp-cpe.dtsi | 2 ++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 234157134e2f..f11bc20e85c8 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -175,6 +175,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; + phy-supply = <&aqr_vreg>; #address-cells = <1>; #size-cells = <1>; @@ -203,6 +204,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group2>; + phy-supply = <&qca_vreg>; #address-cells = <1>; #size-cells = <1>; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index a1782da1890d..a6e249a6eac5 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -113,6 +113,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; + phy-supply = <&aqr_vreg>; interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; From 970394b4d4d343b679a943bf81b0dc8770bbe7f7 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Tue, 14 Sep 2021 11:49:54 -0700 Subject: [PATCH 1734/1809] ARM: dts: msm: PCIe turn-on of NTN3 regulator Rename all occurrences of NTN3 regulator as QPS615. Turn on of QPS615 regulator by PCIe and also replace depedency of AQR regulator on QCA regulator with QPS615 regulator. Change-Id: I6962b57d8f1cfbb15473b21a93dc5d559464015e --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 +- qcom/sdxlemur-mtp-cpe.dtsi | 10 +++++----- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 4f653deecd4d..e36aaf6e9f08 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -13,7 +13,7 @@ }; }; -&ntn3_vreg { +&qps615_vreg { vin-supply = <&pine_vreg>; }; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index f11bc20e85c8..8ea6f8dc0a18 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp.dtsi" &soc { - ntn3_vreg: ntn3_vreg { + qps615_vreg: qps615_vreg { compatible = "regulator-fixed"; - regulator-name = "ntn3_vreg"; + regulator-name = "qps615_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "qca_vreg"; gpio = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vin-supply = <&ntn3_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; @@ -26,7 +26,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&qca_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -126,7 +126,7 @@ &pcie0 { pcie-i2c-phandle = <&i2c_5>; - vreg-3p3-supply = <&aqr_vreg>; + vreg-3p3-supply = <&qps615_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index a6e249a6eac5..82f04a95b4d6 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp-mbb.dtsi" &soc { - ntn3_vreg: ntn3_vreg { + qps615_vreg: qps615_vreg { compatible = "regulator-fixed"; - regulator-name = "ntn3_vreg"; + regulator-name = "qps615_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&ntn3_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -72,7 +72,7 @@ qcom,filtered-bdfs = <0x02080000>; - vreg-3p3-supply = <&aqr_vreg>; + vreg-3p3-supply = <&qps615_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, From 55484e035730d2dcf53e90879768024950c62179 Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Mon, 20 Sep 2021 17:12:27 -0700 Subject: [PATCH 1735/1809] ARM: dts: msm: Pin config for AQR on MBB Make a pin control for eth0 on AQR PHY for MBB platforms. This pinctrl is necessary to configure the GPIO pin on SDX65 for WoL interrupts. Change-Id: I0c65b02bd7a85aa14fa20391a9007b0a6e40e655 --- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index a6e249a6eac5..004fbbf42322 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -118,6 +118,9 @@ interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + #address-cells = <1>; #size-cells = <1>; }; From 4f48e10b380ffc4404680400afbec6171810268e Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 27 Sep 2021 14:19:28 +0530 Subject: [PATCH 1736/1809] dt-bindings: input: qpnp-power-on: Add qcom,log-kpd-event description Add support 'qcom,log-kpd-event' property which when enabled causes KPDPWR status to be logged during driver INIT and runtime when key is pressed. Change-Id: Ie8a8068cc8faefdbe678b4e7d11cac179faf01dd --- bindings/input/qpnp-power-on.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt index b9bb2bfea1ae..2db6719b2c54 100644 --- a/bindings/input/qpnp-power-on.txt +++ b/bindings/input/qpnp-power-on.txt @@ -129,6 +129,8 @@ Optional properties: - qcom,use-legacy-hard-reset-offset Boolean property to support legacy hard-reset offset of the PON_RB_SPARE register for some (PON gen2) platforms. +- qcom,log-kpd-event: Boolean property to enable logging of KPDPWR status + during driver INIT and runtime when key is pressed. Optional Sub-nodes: - qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features From 570a6d1c71f10a1e0074e0dd88dbb1a32654eeaf Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 27 Sep 2021 13:57:20 +0530 Subject: [PATCH 1737/1809] ARM: dts: msm: Enable KPDPWR status logging Enable KPDPWR status logging for holi-pm6125 and blair platforms. Change-Id: I68f0db9943f879a0347ec5a1aa57dd0cf5a7b05a --- qcom/holi-pmic-overlay-pm6125.dtsi | 3 +++ qcom/pm6125.dtsi | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi index cf4d9588b4c1..1e7a198c34a1 100644 --- a/qcom/holi-pmic-overlay-pm6125.dtsi +++ b/qcom/holi-pmic-overlay-pm6125.dtsi @@ -494,3 +494,6 @@ }; }; +&pm6125_pon { + qcom,log-kpd-event; +}; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index 28ac8c196c2e..fb71fa0fd284 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -17,7 +17,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,power-on@800 { + pm6125_pon: qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; reg = <0x800>; interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, From 36e816f460b53ca4138546becf5ff37c8d4414f4 Mon Sep 17 00:00:00 2001 From: Jianmin Zhu Date: Mon, 27 Sep 2021 17:47:20 +0800 Subject: [PATCH 1738/1809] ARM: dts: qcom: Set default_gen_speed as gen3 for sdx65 Set pcie default_gen_speed as gen3 for sdx65. Disable device initiated BW scaling in sdxlemur-cnss.dtsi, then host can set pcie linkspeed as gen3, ignore gen2 request from hsp firmware event:MHI_ER_BW_SCALE_ELEMENT_TYPE. Change-Id: Ib0ecfdf68098decb5448ee692b63ef8ff52eacdc CRs-Fixed: 3044666 --- bindings/cnss/cnss-wlan.txt | 1 + qcom/sdxlemur-cnss.dtsi | 8 ++------ qcom/sdxlemur-mtp-cpe-hsp.dtsi | 25 ------------------------- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 25 ------------------------- 4 files changed, 3 insertions(+), 56 deletions(-) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 0309934b1cda..7be180ac82b5 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -92,6 +92,7 @@ Optional properties: regulator used in internal power amplifier for QCA6490 - cnss-enable-self-recovery: Boolean property to enable self recovery when recovery is trigeered with reason link down. + - default_gen_speed: U32 property to specify pcie default gen speed. - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO enable to resolve PMU power up issues. Provide BT GPIO using this config param. diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi index 8b2973d86491..776a7d66f1b3 100644 --- a/qcom/sdxlemur-cnss.dtsi +++ b/qcom/sdxlemur-cnss.dtsi @@ -30,6 +30,7 @@ use-pm-domain; cnss-enable-self-recovery; + default_gen_speed = <3>; vdd-wlan-aon-supply = <&S7B>; qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 0>; @@ -169,12 +170,7 @@ }; mhi_event@2 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <0>; - mhi,priority = <2>; - mhi,brstmode = <2>; - mhi,data-type = <3>; + status = "disabled"; }; }; diff --git a/qcom/sdxlemur-mtp-cpe-hsp.dtsi b/qcom/sdxlemur-mtp-cpe-hsp.dtsi index d9969be2f7be..e8ba2208d897 100644 --- a/qcom/sdxlemur-mtp-cpe-hsp.dtsi +++ b/qcom/sdxlemur-mtp-cpe-hsp.dtsi @@ -14,28 +14,3 @@ #size-cells = <1>; }; }; - -&wlan { - mhi_events { - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <1>; - mhi,priority = <0>; - mhi,brstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <0>; - mhi,msi = <2>; - mhi,priority = <1>; - mhi,brstmode = <2>; - }; - - mhi_event@2 { - status = "disabled"; - }; - }; -}; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 004fbbf42322..c5230d9ff666 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -135,28 +135,3 @@ }; }; }; - -&wlan { - mhi_events { - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <0>; - mhi,msi = <1>; - mhi,priority = <0>; - mhi,brstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <0>; - mhi,msi = <2>; - mhi,priority = <1>; - mhi,brstmode = <2>; - }; - - mhi_event@2 { - status = "disabled"; - }; - }; -}; From 0e25e390aecae528eb1e9d12328f8098cc96a9ad Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 27 Sep 2021 17:31:41 +0530 Subject: [PATCH 1739/1809] ARM: dts: msm: Update compatible for HSP on Yupik Update compatible for Yupik and YupikP SoC device tree with HSP support. Change-Id: Ie6012bdf607fa1167527a43a5d649d624193f8d6 --- qcom/yupik-hsp.dts | 2 +- qcom/yupikp-hsp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-hsp.dts b/qcom/yupik-hsp.dts index da97abe6dc64..74b8ca2b9e73 100644 --- a/qcom/yupik-hsp.dts +++ b/qcom/yupik-hsp.dts @@ -4,6 +4,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDP HSP + SoC"; - compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; + compatible = "qcom,yupik"; qcom,board-id = <0 1>; }; diff --git a/qcom/yupikp-hsp.dts b/qcom/yupikp-hsp.dts index 4d0392c3605f..798f668af4b8 100644 --- a/qcom/yupikp-hsp.dts +++ b/qcom/yupikp-hsp.dts @@ -4,6 +4,6 @@ / { model = "Qualcomm Technologies, Inc. YupikP IDP HSP + SoC"; - compatible = "qcom,yupikp-idp", "qcom,yupikp", "qcom,idp"; + compatible = "qcom,yupikp"; qcom,board-id = <0 1>; }; From 1b4ba11834d3ee18d5bab89a80d7be5c5c7a57e2 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Fri, 1 Oct 2021 12:06:35 -0700 Subject: [PATCH 1740/1809] ARM: dts: msm: PHY reset GPIO properties Add DTSI properties to control PHY reset of PHY attaches to NTN3 switch. Change-Id: Ia8da0c8143f79d598f80dc9197ce3110caef5a3a --- qcom/sdxlemur-mtp-cpe.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index f11bc20e85c8..d6538b5fe5a9 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -167,6 +167,7 @@ pinctrl-0 = <&aqr_intn_wol_sig>; compatible = "qcom,ioss-v2-device"; + qcom,phy-rst-gpio = <0>; qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; @@ -196,6 +197,7 @@ pinctrl-0 = <&napa_intn_wol_sig>; compatible = "qcom,ioss-v2-device"; + qcom,phy-rst-gpio = <1>; qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth1>; From c7b6ffddc6ef821048803906f489f10d7b24d2f5 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 10 Aug 2021 12:53:56 +0530 Subject: [PATCH 1741/1809] ARM: dts: qcom: Add separate cpu dai for mi2s rx and tx Add separate cpu dai for mi2s rx and tx. Change-Id: I4ca4783a507fb1953ede55e8b640b0df285f9609 --- bindings/sound/qcom-audio-dev.txt | 113 ++++++++++++++++++++++-------- qcom/direwolf-vm-audio.dtsi | 14 ++-- qcom/holi-audio.dtsi | 8 ++- qcom/lahaina-audio.dtsi | 13 +++- qcom/msm-audio-lpass.dtsi | 66 ++++++++++++----- qcom/sa6155-audio.dtsi | 17 +++-- qcom/sa8155-audio.dtsi | 17 +++-- qcom/sa8155-vm-audio.dtsi | 17 +++-- qcom/scuba-audio.dtsi | 8 ++- qcom/shima-atp.dtsi | 4 +- qcom/shima-audio.dtsi | 13 +++- qcom/shima-idp.dtsi | 4 +- qcom/shima-qrd.dtsi | 4 +- qcom/yupik-audio-overlay.dtsi | 9 ++- qcom/yupik-audio.dtsi | 13 +++- 15 files changed, 227 insertions(+), 93 deletions(-) diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 5c4fd50ae840..e6e028d832d2 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1444,8 +1444,10 @@ Example: "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, @@ -1468,6 +1470,8 @@ Example: asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", @@ -1578,9 +1582,12 @@ Example: "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -1608,7 +1615,10 @@ Example: asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", @@ -1714,9 +1724,12 @@ Example: "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -1748,7 +1761,10 @@ Example: asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", @@ -1857,9 +1873,12 @@ Example: "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -1885,7 +1904,10 @@ Example: <&tx_cdc_dma_6_tx>, <&tx_cdc_dma_7_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", @@ -2147,9 +2169,12 @@ Example: "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_rx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -2176,7 +2201,10 @@ Example: asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", @@ -2300,9 +2328,12 @@ Example: "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_rx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -2334,7 +2365,10 @@ Example: asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", @@ -2444,9 +2478,13 @@ Example: "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -2479,6 +2517,9 @@ Example: "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", @@ -2595,8 +2636,10 @@ Example: "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -2623,6 +2666,8 @@ Example: <&rx_cdc_dma_7_rx>,<&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", @@ -2802,9 +2847,12 @@ Example: "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, @@ -2836,7 +2884,10 @@ Example: asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/direwolf-vm-audio.dtsi b/qcom/direwolf-vm-audio.dtsi index b19586acd6d7..97daaaacacf7 100644 --- a/qcom/direwolf-vm-audio.dtsi +++ b/qcom/direwolf-vm-audio.dtsi @@ -1089,9 +1089,12 @@ "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -1167,7 +1170,10 @@ asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/holi-audio.dtsi b/qcom/holi-audio.dtsi index 4014574b45ee..a0c2b9670d42 100644 --- a/qcom/holi-audio.dtsi +++ b/qcom/holi-audio.dtsi @@ -153,8 +153,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -181,6 +183,8 @@ <&rx_cdc_dma_7_rx>,<&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", diff --git a/qcom/lahaina-audio.dtsi b/qcom/lahaina-audio.dtsi index c891c458f208..8644464838ad 100644 --- a/qcom/lahaina-audio.dtsi +++ b/qcom/lahaina-audio.dtsi @@ -112,9 +112,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -149,6 +153,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", diff --git a/qcom/msm-audio-lpass.dtsi b/qcom/msm-audio-lpass.dtsi index 2b4eb0ef2c15..a8e23ba3eb3d 100644 --- a/qcom/msm-audio-lpass.dtsi +++ b/qcom/msm-audio-lpass.dtsi @@ -91,46 +91,76 @@ msm_dai_mi2s: qcom,msm-dai-mi2s { compatible = "qcom,msm-dai-mi2s"; - dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + dai_mi2s0_rx: qcom,msm-dai-q6-mi2s-prim-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <0>; - qcom,msm-mi2s-rx-lines = <3>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <3>; }; - dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + dai_mi2s0_tx: qcom,msm-dai-q6-mi2s-prim-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <1>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + dai_mi2s1_rx: qcom,msm-dai-q6-mi2s-sec-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <2>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <1>; }; - dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + dai_mi2s1_tx: qcom,msm-dai-q6-mi2s-sec-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <3>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + dai_mi2s2_rx: qcom,msm-dai-q6-mi2s-tert-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <4>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + dai_mi2s2_tx: qcom,msm-dai-q6-mi2s-tert-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <5>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <3>; + }; + + dai_mi2s3_rx: qcom,msm-dai-q6-mi2s-quat-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s3_tx: qcom,msm-dai-q6-mi2s-quat-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <7>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s4_rx: qcom,msm-dai-q6-mi2s-quin-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <8>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s4_tx: qcom,msm-dai-q6-mi2s-quin-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <9>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s5_rx: qcom,msm-dai-q6-mi2s-senary-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <10>; + qcom,msm-mi2s-lines = <0>; + }; + + dai_mi2s5_tx: qcom,msm-dai-q6-mi2s-senary-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <11>; + qcom,msm-mi2s-lines = <3>; }; }; diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index 8e1aa63d8e9f..dc01de783b2b 100644 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -517,9 +517,12 @@ qcom,msm-dai-q6 { "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -553,9 +556,11 @@ qcom,msm-dai-q6 { <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, <&dai_quin_tdm_tx_7>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", + "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", + "msm-dai-q6-mi2s.5", "msm-dai-q6-mi2s.6", + "msm-dai-q6-mi2s.7", "msm-dai-q6-mi2s.8", + "msm-dai-q6-mi2s.9", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/sa8155-audio.dtsi b/qcom/sa8155-audio.dtsi index e93ab89508e5..fc606616f3ec 100644 --- a/qcom/sa8155-audio.dtsi +++ b/qcom/sa8155-audio.dtsi @@ -513,9 +513,12 @@ qcom,msm-dai-q6 { "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -549,9 +552,11 @@ qcom,msm-dai-q6 { <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, <&dai_quin_tdm_tx_7>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", + "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", + "msm-dai-q6-mi2s.5", "msm-dai-q6-mi2s.6", + "msm-dai-q6-mi2s.7", "msm-dai-q6-mi2s.8", + "msm-dai-q6-mi2s.9", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi index 0db1f18be5a0..1b2feda9b10d 100644 --- a/qcom/sa8155-vm-audio.dtsi +++ b/qcom/sa8155-vm-audio.dtsi @@ -469,9 +469,12 @@ "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -505,9 +508,11 @@ <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, <&dai_quin_tdm_tx_7>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", + "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", + "msm-dai-q6-mi2s.5", "msm-dai-q6-mi2s.6", + "msm-dai-q6-mi2s.7", "msm-dai-q6-mi2s.8", + "msm-dai-q6-mi2s.9", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/scuba-audio.dtsi b/qcom/scuba-audio.dtsi index bd1b4870f5e7..3413dfeaa15a 100644 --- a/qcom/scuba-audio.dtsi +++ b/qcom/scuba-audio.dtsi @@ -100,8 +100,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -128,6 +130,8 @@ <&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", diff --git a/qcom/shima-atp.dtsi b/qcom/shima-atp.dtsi index 3fc75973a822..f94b6882afa8 100644 --- a/qcom/shima-atp.dtsi +++ b/qcom/shima-atp.dtsi @@ -199,8 +199,8 @@ }; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/shima-audio.dtsi b/qcom/shima-audio.dtsi index 10ee18cc06de..5fd0a1fa60db 100644 --- a/qcom/shima-audio.dtsi +++ b/qcom/shima-audio.dtsi @@ -180,9 +180,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -217,6 +221,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 728936ec43b3..0b0623b7f2b3 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -223,8 +223,8 @@ }; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 926f4c272a16..1621cfee40db 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -467,8 +467,8 @@ <&bolero>; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index c3de58d5aa40..8a69b60a5f3f 100644 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -488,9 +488,12 @@ }; }; -&dai_mi2s1 { - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s1_rx { + qcom,msm-mi2s-lines = <0>; +}; + +&dai_mi2s1_tx { + qcom,msm-mi2s-lines = <1>; }; &adsp_loader { diff --git a/qcom/yupik-audio.dtsi b/qcom/yupik-audio.dtsi index 6800853aaaf6..865416bd4f7e 100644 --- a/qcom/yupik-audio.dtsi +++ b/qcom/yupik-audio.dtsi @@ -180,9 +180,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -217,6 +221,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", From 307bf650a1be43153e8c2384ba58e3fe4baf79da Mon Sep 17 00:00:00 2001 From: Anvesh Salveru Date: Wed, 15 Sep 2021 16:56:50 +0530 Subject: [PATCH 1742/1809] ARM: dts: msm: Update smmu s1 mask on sdxlemur V2 Update smmu s1 smr mask for bslp uart, i2c, spi on sdxlemur V2. Change-Id: If71e920441f0e68bdcbe0ee05af3d46096648c03 --- qcom/sdxlemur-v2.dtsi | 54 +++++++++++++++---------------------------- 1 file changed, 18 insertions(+), 36 deletions(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 43abbcc5540c..fab47d03133a 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -7,144 +7,126 @@ }; &i2c_1 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_2 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_3 { - iommus = <&apps_smmu 0x14c 0x0>, - <&apps_smmu 0x14d 0x0>; + iommus = <&apps_smmu 0x14c 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_4 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_5 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_6 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_7 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_1 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_2 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_3 { - iommus = <&apps_smmu 0x14c 0x0>, - <&apps_smmu 0x14d 0x0>; + iommus = <&apps_smmu 0x14c 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_4 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart1a_hs { - iommus = <&apps_smmu 0x140 0x0>, - <&apps_smmu 0x141 0x0>; + iommus = <&apps_smmu 0x140 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart1b_hs { - iommus = <&apps_smmu 0x140 0x0>, - <&apps_smmu 0x141 0x0>; + iommus = <&apps_smmu 0x140 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart2a_hs { - iommus = <&apps_smmu 0x142 0x0>, - <&apps_smmu 0x143 0x0>; + iommus = <&apps_smmu 0x142 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart2b_hs { - iommus = <&apps_smmu 0x142 0x0>, - <&apps_smmu 0x143 0x0>; + iommus = <&apps_smmu 0x142 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart3_hs { - iommus = <&apps_smmu 0x144 0x0>, - <&apps_smmu 0x145 0x0>; + iommus = <&apps_smmu 0x144 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart4a_hs { - iommus = <&apps_smmu 0x146 0x0>, - <&apps_smmu 0x147 0x0>; + iommus = <&apps_smmu 0x146 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart4b_hs { - iommus = <&apps_smmu 0x146 0x0>, - <&apps_smmu 0x147 0x0>; + iommus = <&apps_smmu 0x146 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; From 38bd963cd003e8de07a24daeb5821dda926c25a1 Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Fri, 8 Oct 2021 12:09:26 +0800 Subject: [PATCH 1743/1809] ARM: dts: msm: Remove BT property bt-sw-ctrl-gpio for sdxlemur Remove BT property bt-sw-ctrl-gpio. CRs-Fixed: 3007327 Change-Id: I64912f37dba5bffa66846735e92205985bf6dac7 --- qcom/sdxlemur-bluetooth.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxlemur-bluetooth.dtsi b/qcom/sdxlemur-bluetooth.dtsi index 600583f15bb3..e8dccf6a6089 100644 --- a/qcom/sdxlemur-bluetooth.dtsi +++ b/qcom/sdxlemur-bluetooth.dtsi @@ -19,7 +19,6 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_en_default>; qcom,bt-reset-gpio = <&pmx65_gpios 15 0>; /* BT_EN */ - qcom,bt-sw-ctrl-gpio = <&pmx65_gpios 2 0>; /* SW_CTRL */ clocks = <&rpmhcc RPMH_RF_CLK3>; clock-names = "ref3_clk"; From 44addf5fdbc5ac1d1f5d28bab89f3200b6266bb3 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 16 Sep 2021 10:29:54 +0530 Subject: [PATCH 1744/1809] ARM: dts: qcom: Disabling dt node for sdx ipc driver Disabling entry for sdx ipc driver, and enabling it for platform specific device tree. Change-Id: Ia73183d2d554767ddda0ca56d7d618fcd845d203 --- qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 1 + qcom/sdxlemur.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi index b9cfadf6bab5..445c95bfce1c 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -72,4 +72,5 @@ &sdx_ext_ipc { ipq807x_attach = <1>; + status = "ok"; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 002dafe500d7..26a8d9a42cf0 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1444,6 +1444,7 @@ qcom,status-in-gpio = <&tlmm 65 0x00>; qcom,status-out-gpio = <&tlmm 44 0x00>; qcom,status-out2-gpio = <&tlmm 45 0x00>; + status = "disabled"; }; }; From 0afda9e69275e2976fec78351ceae71461d617fc Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Fri, 8 Oct 2021 16:36:25 +0530 Subject: [PATCH 1745/1809] ARM: dts: msm: Update of EP PCIe PHY settings to V1.08 for sdxlemur Update of EP PCIe PHY setting to version V1.08 based on hardware recommendation for sdxlemur as per HSR. Change-Id: I9ce400f5a621e8693be2d67e00516434d1871224 --- qcom/sdxlemur.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 002dafe500d7..a097921c9834 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -978,7 +978,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0308>; qcom,pcie-link-speed = <4>; - qcom,pcie-phy-ver = <6>; + qcom,pcie-phy-ver = <8>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; @@ -1018,7 +1018,7 @@ 0x1168 0x0a 0x0 0x116c 0x04 0x0 0x119c 0x88 0x0 - 0x1174 0x20 0x0 + 0x1174 0x60 0x0 0x11a0 0x14 0x0 0x11a8 0x0f 0x0 0x0220 0x16 0x0 @@ -1123,6 +1123,7 @@ 0x1370 0x2e 0x0 0x155c 0x2e 0x0 0x1484 0x08 0x0 + 0x1388 0xaa 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; From 50d1dbe31d29e3bf32b76a00bdfb7032aaa27e96 Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Fri, 8 Oct 2021 17:43:13 +0530 Subject: [PATCH 1746/1809] ARM: dts: msm: Update of RC PCIe PHY settings to V1.08 for sdxlemur Update of RC PCIe PHY setting to version V1.08 based on hardware recommendation for sdxlemur as per HSR. Change-Id: I73f97619b31fd6a1002b62017f0454a721b4b5d1 --- qcom/sdxlemur-pcie.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index cdfb037da0ba..56b030f1335a 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -116,7 +116,7 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,pcie-phy-ver = <1102>; + qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; @@ -159,7 +159,7 @@ 0x1168 0x0a 0x0 0x116c 0x04 0x0 0x119c 0x88 0x0 - 0x1174 0x20 0x0 + 0x1174 0x60 0x0 0x117c 0x06 0x0 0x11a0 0x14 0x0 0x11a8 0x0f 0x0 @@ -266,6 +266,8 @@ 0x1584 0x28 0x0 0x1370 0x2e 0x0 0x155c 0x2e 0x0 + 0x140c 0x1d 0x0 + 0x1388 0xaa 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; From 412e9d21b75f71002529bd07f2f1bc7642d65cd2 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Thu, 16 Sep 2021 12:32:40 -0700 Subject: [PATCH 1747/1809] ARM: dts: msm: Bump up cpu frequency Bump up cpu frequency to 1.8Ghz for sdxlemur v2. Change-Id: I21c4326de98b2e51299c1ba115f9e6e4ec1af532 --- qcom/sdxlemur-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 43abbcc5540c..b2dfa1461582 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -163,7 +163,7 @@ < 345600 >, < 576000 >, < 1094400 >, - < 1708800 >; + < 1804800 >; }; &cpu0_cpu_ddr_tbl { From 958f32d824bd2f7acd7d7b928b3c1ebba9c75b17 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Thu, 16 Sep 2021 12:34:14 -0700 Subject: [PATCH 1748/1809] ARM: dts: msm: Modify cpufreq to ddrfreq table Modify cpu frequency to ddr frequency table to account for change in maximum cpu frequency. Change-Id: I5c9f1586b5b578582a6af612d09359049ca2a13f --- qcom/sdxlemur-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index b2dfa1461582..1c6ee31e5799 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -171,5 +171,5 @@ < 345600 MHZ_TO_MBPS( 300, 4) >, < 576000 MHZ_TO_MBPS( 768, 4) >, < 1440000 MHZ_TO_MBPS(1555, 4) >, - < 1708800 MHZ_TO_MBPS(2092, 4) >; + < 1804800 MHZ_TO_MBPS(2092, 4) >; }; From 3ff57e6d335861a5f5e4c3686bbd319d9d49b6f2 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 10 Sep 2021 16:00:26 -0700 Subject: [PATCH 1749/1809] ARM: dts: msm: Revise V2 dts and add sdxlemur lite soc id Revise the V2 dts files to match V1 CDTs and add sdxlemur lite soc id to the V2 dtsi file. Change-Id: I4af8330b83be34defa51523800e8b0ebc0925d76 --- qcom/sdxlemur-v2-cdp.dts | 2 +- qcom/sdxlemur-v2-mtp-cpe.dts | 3 ++- qcom/sdxlemur-v2-mtp-mbb-emmc.dts | 2 +- qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts | 2 +- qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts | 2 +- qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts | 2 +- qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts | 2 +- qcom/sdxlemur-v2-mtp-mbb.dts | 3 ++- qcom/sdxlemur-v2-mtp.dts | 2 +- qcom/sdxlemur-v2-rcm-pcie-ep.dts | 2 +- qcom/sdxlemur-v2-rcm-rc.dts | 2 +- qcom/sdxlemur-v2.dtsi | 2 +- 12 files changed, 14 insertions(+), 12 deletions(-) diff --git a/qcom/sdxlemur-v2-cdp.dts b/qcom/sdxlemur-v2-cdp.dts index 769730839959..60d4fd8b30c7 100644 --- a/qcom/sdxlemur-v2-cdp.dts +++ b/qcom/sdxlemur-v2-cdp.dts @@ -11,5 +11,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR CDP V2"; compatible = "qcom,sdxlemur-cdp", "qcom,sdxlemur", "qcom,cdp"; - qcom,board-id = <0x20001 0x300>; + qcom,board-id = <0x01 0x300>; }; diff --git a/qcom/sdxlemur-v2-mtp-cpe.dts b/qcom/sdxlemur-v2-mtp-cpe.dts index f8670b646394..ac9e17a8d7f6 100644 --- a/qcom/sdxlemur-v2-mtp-cpe.dts +++ b/qcom/sdxlemur-v2-mtp-cpe.dts @@ -2,6 +2,7 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-hsp.dtsi" #include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" @@ -10,5 +11,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x6020008 0x306>; + qcom,board-id = <0x6010008 0x306>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts index 633ca94dcd73..447854dcbb5d 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-emmc.dts @@ -11,5 +11,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x2020108 0x302>; + qcom,board-id = <0x2010108 0x302>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts index 65630ea06a58..463b234bbb4a 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-ntn3-pcie.dts @@ -10,5 +10,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x5020008 0x305>; + qcom,board-id = <0x5010008 0x305>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts index e638af1217be..eed8f4538c10 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0xB020008 0x20B>; + qcom,board-id = <0xB010008 0x20B>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts index 77326071dd86..7c113e5da418 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x4020008 0x204>; + qcom,board-id = <0x4010008 0x204>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts index c5956de09f13..f0d1d2a65218 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-rc-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x3020008 0x203>; + qcom,board-id = <0x3010008 0x203>; }; diff --git a/qcom/sdxlemur-v2-mtp-mbb.dts b/qcom/sdxlemur-v2-mtp-mbb.dts index 0dc789e85177..275d5b25f80a 100644 --- a/qcom/sdxlemur-v2-mtp-mbb.dts +++ b/qcom/sdxlemur-v2-mtp-mbb.dts @@ -6,10 +6,11 @@ #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" #include "sdxlemur-bluetooth.dtsi" +#include "display/sdxlemur-qpic-display.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x2020008 0x302>; + qcom,board-id = <0x2010008 0x302>; }; diff --git a/qcom/sdxlemur-v2-mtp.dts b/qcom/sdxlemur-v2-mtp.dts index cac68602ccf4..467fc0fc7a10 100644 --- a/qcom/sdxlemur-v2-mtp.dts +++ b/qcom/sdxlemur-v2-mtp.dts @@ -11,5 +11,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR MTP V2"; compatible = "qcom,sdxlemur-mtp", "qcom,sdxlemur", "qcom,mtp"; - qcom,board-id = <0x20008 0x300>; + qcom,board-id = <0x08 0x300>; }; diff --git a/qcom/sdxlemur-v2-rcm-pcie-ep.dts b/qcom/sdxlemur-v2-rcm-pcie-ep.dts index b22c1df9690e..c2726331b1a9 100644 --- a/qcom/sdxlemur-v2-rcm-pcie-ep.dts +++ b/qcom/sdxlemur-v2-rcm-pcie-ep.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP V2"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x1020015 0x201>; + qcom,board-id = <0x1010015 0x201>; }; diff --git a/qcom/sdxlemur-v2-rcm-rc.dts b/qcom/sdxlemur-v2-rcm-rc.dts index 5f66a7bfd927..3fea6cbf8473 100644 --- a/qcom/sdxlemur-v2-rcm-rc.dts +++ b/qcom/sdxlemur-v2-rcm-rc.dts @@ -11,5 +11,5 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex V2"; compatible = "qcom,sdxlemur-rcm", "qcom,sdxlemur", "qcom,rcm"; - qcom,board-id = <0x20015 0x300>; + qcom,board-id = <0x10015 0x300>; }; diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index fab47d03133a..0b315bf8c2be 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. SDXLEMUR V2"; compatible = "qcom,sdxlemur"; - qcom,msm-id = <458 0x20000>, <483 0x20000>; + qcom,msm-id = <458 0x20000>, <483 0x20000>, <509 0x20000>; }; &i2c_1 { From 92c58258cb8368631bae7879f2d537b701f5cef6 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 15 Sep 2021 17:26:24 -0700 Subject: [PATCH 1750/1809] ARM: dts: msm: Add pil modem regulator for sdxlemur v2 Add pil modem regulator sdxlemur v2 devices. Change-Id: I918b9294c000e4a2b974ed79390fc77beba0c5eb --- qcom/sdxlemur-v2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 0b315bf8c2be..64a3769973de 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -155,3 +155,7 @@ < 1440000 MHZ_TO_MBPS(1555, 4) >, < 1708800 MHZ_TO_MBPS(2092, 4) >; }; + +&pil_modem { + qcom,vdd_mss-uV-uA = ; +}; From da8dc0863a1015232ae8d5bc678f38fbf54e4eff Mon Sep 17 00:00:00 2001 From: Amarnath Vangala Date: Fri, 8 Oct 2021 18:40:38 +0530 Subject: [PATCH 1751/1809] ARM: dts: msm: correction to the cps related properties CPS feature related poperty payload was incorrectly added. Change to correct the payload as per packing requirement. Change-Id: I21d8f06c508cf08e6ef822fac5d62759a08ae7b6 --- qcom/lahaina-audio-overlay.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index 1b50e92a9651..a74d1ec98d8b 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -377,9 +377,9 @@ qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>; qcom,cps_threshold_levels = <148 168>; - qcom,cps_normal_values = <0x8E 0x8F 0x8F>; - qcom,cps_lower1_values = <0x10 0xD0 0xD0>; - qcom,cps_lower2_values = <0x0F 0x0F 0x18>; + qcom,cps_normal_values = <0x8E003049 0x1000304A 0x0F003472>; + qcom,cps_lower1_values = <0x8F003049 0xD000304A 0x0F003472>; + qcom,cps_lower2_values = <0x8F003049 0xD000304A 0x18003472>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; }; From 7d65d20baecb249ffeb4ab309f50a92d0337ae03 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 21 Sep 2021 15:43:31 -0700 Subject: [PATCH 1752/1809] ARM: dts: msm: Add additional v2 variants for sdxlemur boards Add additional v2 variants for sdxlemur boards. Change-Id: I82c12b878df6ebe70fa5d0420716cd81a68c6abb --- qcom/Makefile | 11 ++++++++++- qcom/sdxlemur-v2-atp.dts | 12 ++++++++++++ qcom/sdxlemur-v2-mtp-cpe-pine1x.dts | 13 +++++++++++++ qcom/sdxlemur-v2-mtp-cpe-pine2x.dts | 13 +++++++++++++ qcom/sdxlemur-v2-mtp-mbb-emmc-512mb.dts | 14 ++++++++++++++ qcom/sdxlemur-v2-mtp-mbb-m2-ep-usb.dts | 13 +++++++++++++ qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts | 13 +++++++++++++ qcom/sdxlemur-v2-rcm-rc-pine1x.dts | 13 +++++++++++++ qcom/sdxlemur-v2-rcm-rc-pine2x.dts | 13 +++++++++++++ 9 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-v2-atp.dts create mode 100644 qcom/sdxlemur-v2-mtp-cpe-pine1x.dts create mode 100644 qcom/sdxlemur-v2-mtp-cpe-pine2x.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-emmc-512mb.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-m2-ep-usb.dts create mode 100644 qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts create mode 100644 qcom/sdxlemur-v2-rcm-rc-pine1x.dts create mode 100644 qcom/sdxlemur-v2-rcm-rc-pine2x.dts diff --git a/qcom/Makefile b/qcom/Makefile index bb62dc1d4f59..d04599bb040e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -445,7 +445,16 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dtb \ sdxlemur-v2-mtp-mbb-pcie-rc-ep.dtb \ sdxlemur-v2-rcm-pcie-ep.dtb \ - sdxlemur-v2-rcm-rc.dtb + sdxlemur-v2-rcm-rc.dtb \ + sdxlemur-v2-atp.dtb \ + sdxlemur-v2-mtp-cpe-pine1x.dtb \ + sdxlemur-v2-mtp-cpe-pine2x.dtb \ + sdxlemur-v2-mtp-mbb-emmc-512mb.dtb \ + sdxlemur-v2-mtp-mbb-m2-ep-usb.dtb \ + sdxlemur-v2-mtp-mbb-m2-ep.dtb \ + sdxlemur-v2-rcm-rc-pine1x.dtb \ + sdxlemur-v2-rcm-rc-pine2x.dtb + ifeq ($(CONFIG_ARCH_SHIMA), y) diff --git a/qcom/sdxlemur-v2-atp.dts b/qcom/sdxlemur-v2-atp.dts new file mode 100644 index 000000000000..4fceb2ef95c5 --- /dev/null +++ b/qcom/sdxlemur-v2-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-atp.dtsi" +#include "sdxlemur-512mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR ATP V2"; + compatible = "qcom,sdxlemur-atp", + "qcom,sdxlemur", "qcom,atp"; + qcom,board-id = <0x010021 0x200>; +}; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts new file mode 100644 index 000000000000..6cb3eca2e5ac --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-pine1x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 1x Pine V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x9010008 0x309>; +}; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts new file mode 100644 index 000000000000..a688c1a627c3 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-pine2x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 2x Pine V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0xA010008 0x30A>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-emmc-512mb.dts b/qcom/sdxlemur-v2-mtp-mbb-emmc-512mb.dts new file mode 100644 index 000000000000..220761d0bb94 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-emmc-512mb.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-emmc.dtsi" +#include "sdxlemur-512mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC 512 MB V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010108 0x202>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-m2-ep-usb.dts b/qcom/sdxlemur-v2-mtp-mbb-m2-ep-usb.dts new file mode 100644 index 000000000000..6180453ec7eb --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-m2-ep-usb.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-m2-ep-usb.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB M2 EP USB V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x10010008 0x310>; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts new file mode 100644 index 000000000000..c67a84f09691 --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-mtp-mbb-m2-ep.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB M2 EP V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x8010008 0x308>; +}; diff --git a/qcom/sdxlemur-v2-rcm-rc-pine1x.dts b/qcom/sdxlemur-v2-rcm-rc-pine1x.dts new file mode 100644 index 000000000000..07de3ae04b90 --- /dev/null +++ b/qcom/sdxlemur-v2-rcm-rc-pine1x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-rcm-rc-pine1x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex 1x Pine V2"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x2010015 0x302>; +}; diff --git a/qcom/sdxlemur-v2-rcm-rc-pine2x.dts b/qcom/sdxlemur-v2-rcm-rc-pine2x.dts new file mode 100644 index 000000000000..54a8cc00ac91 --- /dev/null +++ b/qcom/sdxlemur-v2-rcm-rc-pine2x.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-rcm-rc-pine2x.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex 2x Pine V2"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x3010015 0x303>; +}; From 8d18ee6e387ced013a74f35aaee75b9e8b452f52 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 12 Oct 2021 12:37:45 +0530 Subject: [PATCH 1753/1809] ARM: dts: msm: Correct lpi offset table for holi Correct lpi offset table for holi. Change-Id: Idfbc6286271a4b8cdee2b294a5720e026bf189a4 --- qcom/holi-audio.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-audio.dtsi b/qcom/holi-audio.dtsi index a0c2b9670d42..8b6226720ac4 100644 --- a/qcom/holi-audio.dtsi +++ b/qcom/holi-audio.dtsi @@ -34,7 +34,7 @@ <0x00008000>, <0x00009000>, <0x0000A000>, <0x0000B000>, <0x0000C000>, <0x0000D000>, - <0x0000E000>, <0x0000F0000>, + <0x0000E000>, <0x0000F000>, <0x00010000>, <0x00011000>, <0x00012000>; qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, From e3a51b415817076c662cd831a4205d8549baea0a Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Wed, 6 Oct 2021 16:52:50 +0530 Subject: [PATCH 1754/1809] ARM: dts: qcom: PCIe to Gen3 , DSP2 HSP in Gen2 Change is to make pcie enumeration to happen at gen3. But restrict DSP2, hsp to Gen2. Change-Id: Ibf80dcd49ed7a1093608b73cd674b72eab1fb8fb --- qcom/sdxlemur-mtp-cpe.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index d6538b5fe5a9..a36ab38184af 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -118,7 +118,13 @@ 0x82bd00 0x8 0x82c030 0x8 0x828000 0x1 - 0x82bd00 0x8>; + 0x82bd00 0x8 + 0x82c01c 0x10 + 0x82c030 0xf + 0x828000 0xf + 0x82b268 0x2 + 0x82C02C 0x4 + 0x8249DC 0x0>; }; }; From a67499a8816724cdc7563b63664e751691f1d350 Mon Sep 17 00:00:00 2001 From: Tim Jiang Date: Sun, 26 Sep 2021 15:17:38 +0800 Subject: [PATCH 1755/1809] ARM: dts: msm: Enable bluetooth for sdxlemur mtp cpe Enable bluetooth for sdxlemur mtp cpe. CRs-Fixed: 3042963 Change-Id: Id1d998020bcd589bf97377d816ce2a322ddbda62 --- qcom/sdxlemur-mtp-cpe.dts | 1 + qcom/sdxlemur-v2-mtp-cpe.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 3942c230e2bd..3c8c9ad3028b 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -6,6 +6,7 @@ #include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; diff --git a/qcom/sdxlemur-v2-mtp-cpe.dts b/qcom/sdxlemur-v2-mtp-cpe.dts index ac9e17a8d7f6..43610fa9f3d6 100644 --- a/qcom/sdxlemur-v2-mtp-cpe.dts +++ b/qcom/sdxlemur-v2-mtp-cpe.dts @@ -6,6 +6,7 @@ #include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-audio.dtsi" #include "sdxlemur-mtp-audio-overlay.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE V2"; From 158dca677008f7a3832e9dab681511d60cc3fe5f Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 23 Sep 2021 08:58:42 -0700 Subject: [PATCH 1756/1809] ARM: dts: msm: Set the interrupt moderation interval to 1ms on sdxlemur Modify the interrupt moderation interval to 1ms to bring down the CPU usage on sdxlemur. Change-Id: Ia2ed210f671cf4f708d0a2d217d3f42b487846ae --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a80512eb8688..797872e42152 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -72,7 +72,7 @@ tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; - snps,xhci-imod-value = <4000>; + imod-interval-ns = <1000000>; }; qcom,usbbam@a704000 { From 923617f29bdf3797e0ddf5640e4b2be9d01b2ea5 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Mon, 11 Oct 2021 11:00:20 -0700 Subject: [PATCH 1757/1809] ARM: dts: msm: PHY regulator ramp delays Provide sufficient settling time for AQR and QCA regulators after power on. Change-Id: Ie26c0212397934309eb6d974e95af6b68ac0f778 --- qcom/sdxlemur-mtp-cpe.dtsi | 4 ++-- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index d6538b5fe5a9..7f7a7520c6ea 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -19,7 +19,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; - regulator-enable-ramp-delay = <200000>; + regulator-enable-ramp-delay = <80000>; }; aqr_vreg: aqr_vreg { @@ -30,7 +30,7 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; - regulator-enable-ramp-delay = <2400>; + regulator-enable-ramp-delay = <10000>; }; ioss_aqr_rx: qps615_rx@eth0 { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index c5230d9ff666..300159305475 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -19,7 +19,7 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; - regulator-enable-ramp-delay = <2400>; + regulator-enable-ramp-delay = <10000>; }; ioss_qps615_rx: qps615_rx@eth { From 43808c572165a5a6c663fcc0cf78f24579095717 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 12 Aug 2021 12:57:12 -0700 Subject: [PATCH 1758/1809] ARM: dts: msm: Modify the usb dma address pool on sdxlemur Set the dma address pool to only accommodate the usable address range on sdxlemur. Change-Id: I8934332ee3d0aaf2934c121fef6881b9a9fe85ee --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a80512eb8688..7a9babcf8521 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -8,7 +8,7 @@ iommus = <&apps_smmu 0x1a0 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x40000000 0x5ffe0000>; + qcom,iommu-dma-addr-pool = <0x90000000 0x0ffe0000>; #address-cells = <1>; #size-cells = <1>; ranges; From bf7c4c06d6f84519bdf77b6ed86f3a9d64933297 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Wed, 20 Oct 2021 16:28:41 -0700 Subject: [PATCH 1759/1809] Revert "ARM: dts: msm: PCIe turn-on of NTN3 regulator" This reverts commit c004fe468dc8340cba11f26140d226d26a41f236. Resolve IP non-assignment for AQR. Change-Id: Ie8a596f937d748a000aeafef5a6a688a6db90379 --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 +- qcom/sdxlemur-mtp-cpe.dtsi | 10 +++++----- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index e36aaf6e9f08..4f653deecd4d 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -13,7 +13,7 @@ }; }; -&qps615_vreg { +&ntn3_vreg { vin-supply = <&pine_vreg>; }; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 65bbb9421d06..7f7a7520c6ea 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp.dtsi" &soc { - qps615_vreg: qps615_vreg { + ntn3_vreg: ntn3_vreg { compatible = "regulator-fixed"; - regulator-name = "qps615_vreg"; + regulator-name = "ntn3_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "qca_vreg"; gpio = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vin-supply = <&qps615_vreg>; + vin-supply = <&ntn3_vreg>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; @@ -26,7 +26,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&qps615_vreg>; + vin-supply = <&qca_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -126,7 +126,7 @@ &pcie0 { pcie-i2c-phandle = <&i2c_5>; - vreg-3p3-supply = <&qps615_vreg>; + vreg-3p3-supply = <&aqr_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 207b5583f9a7..300159305475 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp-mbb.dtsi" &soc { - qps615_vreg: qps615_vreg { + ntn3_vreg: ntn3_vreg { compatible = "regulator-fixed"; - regulator-name = "qps615_vreg"; + regulator-name = "ntn3_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&qps615_vreg>; + vin-supply = <&ntn3_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -72,7 +72,7 @@ qcom,filtered-bdfs = <0x02080000>; - vreg-3p3-supply = <&qps615_vreg>; + vreg-3p3-supply = <&aqr_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, From ebb1333a1670d098848038f08600a142aa19976c Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Thu, 16 Sep 2021 12:52:30 +0530 Subject: [PATCH 1760/1809] ARM: dts: msm: Add AQC and R8125 dtsi nodes Create a DTS node for aquantia and r8125 for 1gb device variant. Change-Id: Ibae3fbba75d24dcde47d9f7bf2b80d4e4a082357 --- qcom/sdxlemur-rcm-rc.dtsi | 128 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index a1c20370dd86..71c22a6c7dea 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -15,6 +15,134 @@ qcom,batt-id-range-pct = <15>; #include "qg-batterydata-alium-3600mah.dtsi" }; + + ioss_aqc_eth0_rx: aqc_rx@eth0 { + qcom,dir-rx; + qcom,rx-filter-be; + + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <15>; + qcom,mod-count-max = <25>; + qcom,mod-usecs-min = <64>; + qcom,mod-usecs-max = <128>; + }; + + ioss_aqc_eth0_tx: aqc_tx@eth0 { + qcom,dir-tx; + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <15>; + qcom,mod-count-max = <25>; + qcom,mod-usecs-min = <64>; + qcom,mod-usecs-max = <128>; + }; + + ioss_aqc_eth0: aqc@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_aqc_eth0_rx>, + <&ioss_aqc_eth0_tx>; + }; + + ioss_r8125_eth0_rx: r8125_rx@eth0 { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <1023>; /* Cannot be a power of 2 */ + qcom,buff-size = <2048>; + + qcom,mod-count-min = <32>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_r8125_eth0_tx: r8125_tx@eth0 { + qcom,dir-tx; + qcom,ring-size = <1024>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <32>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_r8125_eth0: r8125@eth0 { + qcom,name = "eth0"; + qcom,ioss_instance = <0>; + + qcom,ioss_channels = + <&ioss_r8125_eth0_rx>, + <&ioss_r8125_eth0_tx>; + }; +}; + +&pcie0_rp { + + aquantia,aqc@pcie0_rp { + reg = <0 0 0 0 0>; + + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + /* ipa shares this group with aqc */ + qcom,iommu-group = <&ipa_eth_group1>; + qcom,ioss_interfaces = + <&ioss_aqc_eth0>; + + #address-cells = <1>; + #size-cells = <1>; + + pci-ids = + "1d6a:0001", + "1d6a:d107", + "1d6a:07b1", + "1d6a:87b1", + "1d6a:d108", + "1d6a:08b1", + "1d6a:88b1", + "1d6a:d109", + "1d6a:09b1", + "1d6a:89b1", + "1d6a:d100", + "1d6a:00b1", + "1d6a:80b1", + "1d6a:11b1", + "1d6a:91b1", + "1d6a:12b1", + "1d6a:92b1", + "1d6a:00c0", + "1d6a:04c0", + "1d6a:12c0", + "1d6a:14c0", + "1d6a:93c0", + "1d6a:94c0"; + + }; + + realtek,rtl8125@pcie0_rp { + reg = <0 0 0 0 0>; + + compatible = "qcom,ioss-v2-device"; + qcom,ioss = <&ioss>; + qcom,ioss_interfaces = <&ioss_r8125_eth0>; + + /* ipa shares this group with rtl */ + qcom,iommu-group = <&ipa_eth_group1>; + + #address-cells = <1>; + #size-cells = <1>; + + pci-ids = + "10ec:8125", + "10ec:3000"; + + }; }; &spmi_debug_bus { From 8eaf5accce42ab6ba06ff27e06fac1d55551e90b Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 26 Aug 2021 10:27:22 +0530 Subject: [PATCH 1761/1809] ARM: dts: msm: Enable USB2/PCIE for yupik iot with pm7250b Enable required USB2/PCIE nodes for yupik iot having HSP attach with pm7250b. Also move enabling USB2/PCIE nodes to dtsi file which is relevant for hsp attach without pm7250b as well. Change-Id: I195043b79ad49dbc0af128854942ad0b14f026c8 --- qcom/yupik-iot-hsp-pm7250b.dtsi | 60 +++++++++++++++++++++++++++++++++ qcom/yupik-iot-hsp.dtsi | 60 +++++++++++++++++++++++++++++++++ qcom/yupik-iot-idp.dtsi | 60 --------------------------------- qcom/yupikp-iot-hsp.dtsi | 60 +++++++++++++++++++++++++++++++++ qcom/yupikp-iot-idp.dtsi | 8 ----- 5 files changed, 180 insertions(+), 68 deletions(-) diff --git a/qcom/yupik-iot-hsp-pm7250b.dtsi b/qcom/yupik-iot-hsp-pm7250b.dtsi index b1d6a3003180..0b54a7a9d9d5 100644 --- a/qcom/yupik-iot-hsp-pm7250b.dtsi +++ b/qcom/yupik-iot-hsp-pm7250b.dtsi @@ -1 +1,61 @@ #include "yupik-iot-idp-pm7250b.dtsi" + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie1 { + status = "ok"; + qcom,boot-option = <0x0>; + qcom,ep-gpio = <&tlmm 19 0>; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default + &pcie1_ep_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default + &pcie1_ep_default>; +}; + +&pcie1_msi { + status = "ok"; +}; + +&pm7325_gpios { + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio8"; + function = "normal"; + output-low; + power-source = <0>; /* 1.8V input supply */ + }; + }; +}; + +&soc { + usb2_vbus_boost_reg: usb2_vbus_boost_reg { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpios = <&pm7325_gpios 8 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; +}; + +&usb1 { + vbus_dwc3-supply = <&usb2_vbus_boost_reg>; + qcom,default-mode-none; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; diff --git a/qcom/yupik-iot-hsp.dtsi b/qcom/yupik-iot-hsp.dtsi index f87450ed785b..7710d5328d21 100644 --- a/qcom/yupik-iot-hsp.dtsi +++ b/qcom/yupik-iot-hsp.dtsi @@ -2,3 +2,63 @@ &soc { }; + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie1 { + status = "ok"; + qcom,boot-option = <0x0>; + qcom,ep-gpio = <&tlmm 19 0>; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default + &pcie1_ep_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default + &pcie1_ep_default>; +}; + +&pcie1_msi { + status = "ok"; +}; + +&pm7325_gpios { + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio8"; + function = "normal"; + output-low; + power-source = <0>; /* 1.8V input supply */ + }; + }; +}; + +&soc { + usb2_vbus_boost_reg: usb2_vbus_boost_reg { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpios = <&pm7325_gpios 8 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; +}; + +&usb1 { + vbus_dwc3-supply = <&usb2_vbus_boost_reg>; + qcom,default-mode-none; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 45b0b4e4718f..31da5af1d4e3 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -1,62 +1,2 @@ #include "yupik-idp.dtsi" #include "qcx6490-cnss.dtsi" - -&pcie0 { - status = "ok"; -}; - -&pcie0_msi { - status = "ok"; -}; - -&pcie1 { - status = "ok"; - qcom,boot-option = <0x0>; - qcom,ep-gpio = <&tlmm 19 0>; - pinctrl-0 = <&pcie1_perst_default - &pcie1_clkreq_default - &pcie1_wake_default - &pcie1_ep_default>; - pinctrl-1 = <&pcie1_perst_default - &pcie1_clkreq_sleep - &pcie1_wake_default - &pcie1_ep_default>; -}; - -&pcie1_msi { - status = "ok"; -}; - -&pm7325_gpios { - usb2_vbus_boost { - usb2_vbus_boost_default: usb2_vbus_boost_default { - pins = "gpio8"; - function = "normal"; - output-low; - power-source = <0>; /* 1.8V input supply */ - }; - }; -}; - -&soc { - usb2_vbus_boost_reg: usb2_vbus_boost_reg { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus_boost_vreg"; - startup-delay-us = <4000>; - enable-active-high; - gpios = <&pm7325_gpios 8 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_boost_default>; - }; -}; - -&usb1 { - vbus_dwc3-supply = <&usb2_vbus_boost_reg>; - qcom,default-mode-none; - status = "ok"; -}; - -&usb2_phy1 { - status = "ok"; -}; diff --git a/qcom/yupikp-iot-hsp.dtsi b/qcom/yupikp-iot-hsp.dtsi index b5ec1077fad6..a334d3bb8abf 100644 --- a/qcom/yupikp-iot-hsp.dtsi +++ b/qcom/yupikp-iot-hsp.dtsi @@ -1 +1,61 @@ #include "yupikp-iot-idp.dtsi" + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie1 { + status = "ok"; + qcom,boot-option = <0x0>; + qcom,ep-gpio = <&tlmm 19 0>; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default + &pcie1_ep_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default + &pcie1_ep_default>; +}; + +&pcie1_msi { + status = "ok"; +}; + +&pm7325_gpios { + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio8"; + function = "normal"; + output-low; + power-source = <0>; /* 1.8V input supply */ + }; + }; +}; + +&soc { + usb2_vbus_boost_reg: usb2_vbus_boost_reg { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpios = <&pm7325_gpios 8 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_boost_default>; + }; +}; + +&usb1 { + vbus_dwc3-supply = <&usb2_vbus_boost_reg>; + qcom,default-mode-none; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi index bc2beeb0b0ff..90377734afa9 100644 --- a/qcom/yupikp-iot-idp.dtsi +++ b/qcom/yupikp-iot-idp.dtsi @@ -1,10 +1,2 @@ #include "yupikp-idp.dtsi" #include "qcx6490-cnss.dtsi" - -&pcie0 { - status = "ok"; -}; - -&pcie0_msi { - status = "ok"; -}; From 569cb7cc221f6208189b34f5e9da5f6c3ed21c09 Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Thu, 21 Oct 2021 12:39:10 +0530 Subject: [PATCH 1762/1809] ARM: dts: msm: Add support for ETH nodes Changes is to support ETH nodes on RCM instead of WLAN Change-Id: I0a425b386ad4d6ad969a3d678675fec5cd9ab875 --- qcom/sdxlemur-rcm-rc.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 71c22a6c7dea..9e4dcf253130 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -3,7 +3,6 @@ #include #include #include -#include "sdxlemur-cnss.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -84,6 +83,8 @@ }; &pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; aquantia,aqc@pcie0_rp { reg = <0 0 0 0 0>; @@ -156,9 +157,9 @@ }; &pcie0 { - qcom,boot-option = <0x1>; qcom,l1-2-th-scale = <2>; /* 1us */ qcom,l1-2-th-value = <70>; + qcom,target-link-speed = <3>; }; &qnand_1 { From af8ec0f97c9f97e555baf6c46b206472e8f0e8e8 Mon Sep 17 00:00:00 2001 From: Ajit Vaishya Date: Thu, 26 Aug 2021 00:51:06 -0700 Subject: [PATCH 1763/1809] ARM: dts: msm: Includes cnss devicetree dtsi file 1) Add HSP(WCN6850) device tree node for Yupik pm7250b IoT platform. 2) Add HSP(WCN6850) device tree node for Yupik QCM and QCS IoT platform. Change-Id: Ic76d94224b7ee6bb5d3c0b9ed10b06f437f9e64c CRs-Fixed: 3066992 --- qcom/yupik-iot-hsp-pm7250b.dtsi | 2 ++ qcom/yupik-iot-hsp.dtsi | 1 + qcom/yupik-iot-idp.dtsi | 1 - qcom/yupikp-iot-hsp.dtsi | 1 + qcom/yupikp-iot-idp.dtsi | 1 - 5 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-iot-hsp-pm7250b.dtsi b/qcom/yupik-iot-hsp-pm7250b.dtsi index 0b54a7a9d9d5..de87bb60607e 100644 --- a/qcom/yupik-iot-hsp-pm7250b.dtsi +++ b/qcom/yupik-iot-hsp-pm7250b.dtsi @@ -1,4 +1,6 @@ +#include #include "yupik-iot-idp-pm7250b.dtsi" +#include "qcx6490-cnss.dtsi" &pcie0 { status = "ok"; diff --git a/qcom/yupik-iot-hsp.dtsi b/qcom/yupik-iot-hsp.dtsi index 7710d5328d21..b4cf6a1a5007 100644 --- a/qcom/yupik-iot-hsp.dtsi +++ b/qcom/yupik-iot-hsp.dtsi @@ -1,4 +1,5 @@ #include "yupik-iot-idp.dtsi" +#include "qcx6490-cnss.dtsi" &soc { }; diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi index 31da5af1d4e3..aeef58f4f289 100644 --- a/qcom/yupik-iot-idp.dtsi +++ b/qcom/yupik-iot-idp.dtsi @@ -1,2 +1 @@ #include "yupik-idp.dtsi" -#include "qcx6490-cnss.dtsi" diff --git a/qcom/yupikp-iot-hsp.dtsi b/qcom/yupikp-iot-hsp.dtsi index a334d3bb8abf..c6691ce617b1 100644 --- a/qcom/yupikp-iot-hsp.dtsi +++ b/qcom/yupikp-iot-hsp.dtsi @@ -1,4 +1,5 @@ #include "yupikp-iot-idp.dtsi" +#include "qcx6490-cnss.dtsi" &pcie0 { status = "ok"; diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi index 90377734afa9..0790cb6d4444 100644 --- a/qcom/yupikp-iot-idp.dtsi +++ b/qcom/yupikp-iot-idp.dtsi @@ -1,2 +1 @@ #include "yupikp-idp.dtsi" -#include "qcx6490-cnss.dtsi" From fc22b7e642b6f60d37bb2efd9fea0df786379c7c Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Wed, 20 Oct 2021 08:29:07 -0700 Subject: [PATCH 1764/1809] ARM: dts: msm: Enable best fit algo on sdxlemur Enable best fit algo for iova allocation on sdxlemur. This helps in reducing fragementation and thus utilizing the iova address space more efficiently. Change-Id: I493765bc64911be9ac8e4a075a3f7c9d302cd9e4 --- bindings/usb/qcom,dwc3.txt | 4 ++++ qcom/sdxlemur-usb.dtsi | 1 + 2 files changed, 5 insertions(+) diff --git a/bindings/usb/qcom,dwc3.txt b/bindings/usb/qcom,dwc3.txt index cb695aa3fba4..9097f1fcadc4 100644 --- a/bindings/usb/qcom,dwc3.txt +++ b/bindings/usb/qcom,dwc3.txt @@ -46,6 +46,10 @@ Optional properties: - qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. Used when dwc3 operates without SSPHY and only HS/FS/LS modes are supported. +- qcom,iommu-best-fit-algo: If present, enables best fit algorithm for iova + allocation. This helps in reducing fragmentation + and utilizing the iova address space more + efficiently. Required child node: A child node must exist to represent the core DWC3 IP block. The name of diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a80512eb8688..92b47263250e 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -13,6 +13,7 @@ #size-cells = <1>; ranges; dma-ranges; + qcom,iommu-best-fit-algo; interrupts-extended = <&pdc 19 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, From 9d3e12d791e9fa900245075fc871b539ec9e105b Mon Sep 17 00:00:00 2001 From: Wu Gao Date: Tue, 26 Oct 2021 04:51:41 +0800 Subject: [PATCH 1765/1809] ARM: dts: msm: Set default_gen_speed to 0 Set default_gen_speed to 0 and avoid to set pcie max link speed for Olympic device when enumeration in progress. Change-Id: Ifd7cf983044e121c6eb651cf936d30a1ea6f9538 CRs-Fixed: 3063162 --- qcom/sdxlemur-cnss.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi index 776a7d66f1b3..469c03a51321 100644 --- a/qcom/sdxlemur-cnss.dtsi +++ b/qcom/sdxlemur-cnss.dtsi @@ -30,7 +30,7 @@ use-pm-domain; cnss-enable-self-recovery; - default_gen_speed = <3>; + default_gen_speed = <0>; vdd-wlan-aon-supply = <&S7B>; qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 0>; From dea23b50987dd958309776a5367338e658697679 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 20 Oct 2021 23:30:54 -0400 Subject: [PATCH 1766/1809] ARM: dts: msm: Add IOSS channels directly under device Move AQC, RTL and QPS615 IOSS channel configurations directly under the device as we implement a one-to-one mapping from ioss device to the real net device object. Change-Id: Iaa7f4184cae9e8c031ccbb433e99adf84e7f9649 --- qcom/sdxlemur-mtp-cpe.dtsi | 10 ++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 10 ++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 10 ++++++++++ 4 files changed, 35 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 449ab4b5aa35..e06546019587 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -177,6 +177,11 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_aqr_rx>, + <&ioss_aqr_tx>; + interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; @@ -207,6 +212,11 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth1>; + qcom,ioss_instance = <1>; + qcom,ioss_channels = + <&ioss_napa_rx>, + <&ioss_napa_tx>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 300159305475..38e857274753 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -111,6 +111,11 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_qps615_rx>, + <&ioss_qps615_tx>; + /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; phy-supply = <&aqr_vreg>; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 088efbf1ad3c..dd7f4ded4c26 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -82,6 +82,11 @@ qcom,ioss_interfaces = <&ioss_aqc_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_aqc_eth0_rx>, + <&ioss_aqc_eth0_tx>; + #address-cells = <1>; #size-cells = <1>; @@ -119,6 +124,11 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_r8125_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_r8125_eth0_rx>, + <&ioss_r8125_eth0_tx>; + /* ipa shares this group with rtl */ qcom,iommu-group = <&ipa_eth_group1>; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 9e4dcf253130..522f510c7ca0 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -96,6 +96,11 @@ qcom,ioss_interfaces = <&ioss_aqc_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_aqc_eth0_rx>, + <&ioss_aqc_eth0_tx>; + #address-cells = <1>; #size-cells = <1>; @@ -133,6 +138,11 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_r8125_eth0>; + qcom,ioss_instance = <0>; + qcom,ioss_channels = + <&ioss_r8125_eth0_rx>, + <&ioss_r8125_eth0_tx>; + /* ipa shares this group with rtl */ qcom,iommu-group = <&ipa_eth_group1>; From b38030d4f3bcb6423814a8c5d688b1e8bd9e03f6 Mon Sep 17 00:00:00 2001 From: Akshaya Damodaran Date: Wed, 27 Oct 2021 16:05:20 -0700 Subject: [PATCH 1767/1809] Revert "Revert "ARM: dts: msm: PCIe turn-on of NTN3 regulator"" This reverts commit 053496255d41d6b92fae0a0a71da40b25efb96f2. Change-Id: Ib26edd26facf36b5f1443f33d25c958ba85c91bb --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 +- qcom/sdxlemur-mtp-cpe.dtsi | 10 +++++----- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 4f653deecd4d..e36aaf6e9f08 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -13,7 +13,7 @@ }; }; -&ntn3_vreg { +&qps615_vreg { vin-supply = <&pine_vreg>; }; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index e06546019587..cc84fe0a4dec 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp.dtsi" &soc { - ntn3_vreg: ntn3_vreg { + qps615_vreg: qps615_vreg { compatible = "regulator-fixed"; - regulator-name = "ntn3_vreg"; + regulator-name = "qps615_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "qca_vreg"; gpio = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vin-supply = <&ntn3_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; @@ -26,7 +26,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&qca_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -132,7 +132,7 @@ &pcie0 { pcie-i2c-phandle = <&i2c_5>; - vreg-3p3-supply = <&aqr_vreg>; + vreg-3p3-supply = <&qps615_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 38e857274753..a1865eadfbbb 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,9 +1,9 @@ #include "sdxlemur-mtp-mbb.dtsi" &soc { - ntn3_vreg: ntn3_vreg { + qps615_vreg: qps615_vreg { compatible = "regulator-fixed"; - regulator-name = "ntn3_vreg"; + regulator-name = "qps615_vreg"; gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -15,7 +15,7 @@ compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; - vin-supply = <&ntn3_vreg>; + vin-supply = <&qps615_vreg>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; enable-active-high; @@ -72,7 +72,7 @@ qcom,filtered-bdfs = <0x02080000>; - vreg-3p3-supply = <&aqr_vreg>; + vreg-3p3-supply = <&qps615_vreg>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, From 2bc34693da4d4693c802c9684720d1e7caa722ef Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Thu, 28 Oct 2021 22:11:28 +0530 Subject: [PATCH 1768/1809] ARM: dts: qcom: Fix qrtr_instance_id and qrtr_node_id for QCN9000 Fix qrtr_instance_id and qrtr_node_id values for QCN9000 nodes in sdxlemur. Change-Id: I45b1fe670411bdbaaa3d8c1459cc951537e9f7b8 --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 +- qcom/sdxlemur-qcn9000.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 4f653deecd4d..6012b6553dc3 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -29,7 +29,7 @@ reg = <0 0 0 0 0>; qcom,iommu-group = <&qcn9000_pci_iommu_group_0>; memory-region = <&qcn9000_0_mem>; - qrtr_instance_id = <0x0>; + qrtr_instance_id = <0x20>; #address-cells = <1>; #size-cells = <1>; diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index 868bf6bec76c..48709022c247 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -31,7 +31,7 @@ reg-names = "smmu_iova_ipa"; memory-region = <&qcn9000_0_mem>; qcom,wlan-ramdump-dynamic = <0x400000>; - qrtr_node_id = <0x0>; + qrtr_node_id = <0x20>; qca,auto-restart; tgt-mem-mode = <0x1>; board_id = <0xa4>; @@ -155,7 +155,7 @@ reg-names = "smmu_iova_ipa"; memory-region = <&qcn9000_1_mem>; qcom,wlan-ramdump-dynamic = <0x400000>; - qrtr_node_id = <0x0>; + qrtr_node_id = <0x21>; qca,auto-restart; tgt-mem-mode = <0x1>; board_id = <0xa4>; From 23c5b5f7b5250317dfa3743f27569d6dcba655aa Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Fri, 29 Oct 2021 16:06:34 -0400 Subject: [PATCH 1769/1809] ARM: dts: msm: Enable WAKE_PHY for AQR113 on sdxlemur Enable WAKE_PHY for AQR113 (QPS615 port 0) with the help of IOSS framework. Change-Id: I7c1269df952e2fd92497ce4ee1ecb25145bbe8e8 --- qcom/sdxlemur-mtp-cpe.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index e06546019587..307044206b80 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -182,6 +182,8 @@ <&ioss_aqr_rx>, <&ioss_aqr_tx>; + qcom,ioss-wol-phy; + interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; From 8095c7854ccbb664e5eb59296c9187b424142965 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Fri, 29 Oct 2021 16:16:29 -0400 Subject: [PATCH 1770/1809] ARM: dts: msm: Enable WOL for QCA8081 on sdxlemur Enable WAKE_PHY & WAKE_MAGIC for Napa (QCA8081) via IOSS framework. Change-Id: I4d9ddf4d67aede2b56408ce6d4d4d2e0e855e696 --- qcom/sdxlemur-mtp-cpe.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 307044206b80..8b95bbea8a4e 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -219,6 +219,9 @@ <&ioss_napa_rx>, <&ioss_napa_tx>; + qcom,ioss-wol-phy; + qcom,ioss-wol-magic; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; From 2917ef67e7bb134fd2c073d4f1e31925628bf963 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Mon, 1 Nov 2021 15:33:30 +0530 Subject: [PATCH 1771/1809] ARM: dts: msm: Ensure PCIe device is not in D3hot during reboot Avoid rebooting device while PCIe device state is in D3hot. Avoid this scenario by bringing the device out of D3hot state. Change-Id: If7a1fdccac294183bbbf28e744420bc2a9b2bbd6 --- bindings/pci/msm_ep_pcie.txt | 2 ++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt index 425bddc9533d..734ab549c880 100644 --- a/bindings/pci/msm_ep_pcie.txt +++ b/bindings/pci/msm_ep_pcie.txt @@ -75,6 +75,8 @@ Optional Properties: - qcom,msm-bus,vectors-KBps - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode. - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset. + - qcom,avoid-reboot-in-d3hot: Ensures device is not in D3hot during + reboot/panic. Example: diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f83839249eba..daf2d7859546 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -986,6 +986,7 @@ qcom,mhi-soc-reset-offset = <0xb01b8>; qcom,aoss-rst-clr; qcom,aux-clk = <0x11>; + qcom,avoid-reboot-in-d3hot; qcom,phy-init = <0x1240 0x01 0x0 0x100c 0x02 0x0 From 52bca8d388b7f7be3402cac40be9f0c3b5112960 Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Mon, 18 Oct 2021 13:34:39 +0530 Subject: [PATCH 1772/1809] ARM: dts: qcom: PCIe REFCLK always on This is a work around to avoid issue in L1ss for CPE platform. Update phy settings to keep REFCLK always on for CPE. Change-Id: Ida378d5b5cdd8bc313640f1df79a9dfe6da064d2 --- qcom/sdxlemur-mtp-cpe.dtsi | 151 +++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 8f4c2a45752b..09e131e26fec 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -133,6 +133,157 @@ pcie-i2c-phandle = <&i2c_5>; vreg-3p3-supply = <&qps615_vreg>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x01 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xde 0x0 + 0x1028 0x07 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x14 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x0a 0x0 + 0x10b0 0x1a 0x0 + 0x10b4 0x14 0x0 + 0x10b8 0x34 0x0 + 0x10bc 0x82 0x0 + 0x10c4 0xd0 0x0 + 0x10cc 0x55 0x0 + 0x10d0 0x55 0x0 + 0x10d4 0x03 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x60 0x0 + 0x117c 0x06 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0364 0xcc 0x0 + 0x0368 0x12 0x0 + 0x036c 0xcc 0x0 + 0x0374 0x4a 0x0 + 0x0378 0x29 0x0 + 0x037c 0xc5 0x0 + 0x0380 0xac 0x0 + 0x0384 0xb6 0x0 + 0x0388 0xc0 0x0 + 0x038c 0x07 0x0 + 0x0390 0xfb 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xc5 0x0 + 0x039c 0xee 0x0 + 0x03a0 0xbf 0x0 + 0x03a4 0xa0 0x0 + 0x03a8 0x81 0x0 + 0x03ac 0xde 0x0 + 0x03b0 0x7f 0x0 + 0x0b64 0xcc 0x0 + 0x0b68 0x12 0x0 + 0x0b6c 0xcc 0x0 + 0x0b74 0x4a 0x0 + 0x0b78 0x29 0x0 + 0x0b7c 0xc5 0x0 + 0x0b80 0xac 0x0 + 0x0b84 0xb6 0x0 + 0x0b88 0xc0 0x0 + 0x0b8c 0x07 0x0 + 0x0b90 0xfb 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xc5 0x0 + 0x0b9c 0xee 0x0 + 0x0ba0 0xbf 0x0 + 0x0ba4 0xa0 0x0 + 0x0ba8 0x81 0x0 + 0x0bac 0xde 0x0 + 0x0bb0 0x7f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x37 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x37 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x141c 0xc1 0x0 + 0x1490 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1420 0x40 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x140c 0x1d 0x0 + 0x1388 0xaa 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, From e6b3e28f9d94b00394d3dba62c2ca7682e08614d Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Mon, 13 Sep 2021 09:55:27 +0530 Subject: [PATCH 1773/1809] ARM: dts: qcom: EP GPIO reset mask update Change is to avoid ethernet PHY coming out of reset during enumeration. This will be taken care by the ethernet driver. Change-Id: I670693682d52a55b424ffefb2cf7a62506cec621 --- qcom/sdxlemur-mtp-cpe.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 09e131e26fec..a15655f5e250 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -108,7 +108,7 @@ reg = <0x77>; gpio-config-reg = <0x801208>; ep-reset-reg = <0x801210>; - ep-reset-gpio-mask = <0xf>; + ep-reset-gpio-mask = <0xc>; dump-regs = <0x801330 0x801350 0x801370>; reg_update = <0x82c030 0x1 0x828000 0x3 From 945ada9cb5e762c37af155a1ffdbe45560f99948 Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 3 Nov 2021 16:11:50 -0700 Subject: [PATCH 1774/1809] ARM: dts: qcom: reduce L4B regulator min voltage to 880 mV for sdxlemur PMX65 LDO 4 (L4B) loads are able to operate successfully with L4B set to 880 mV. Therefore, reduce the L4B minimum constraint voltage to 880 mV. This allows power to be saved when possible. Also reduce the minimum voltage voted by USB and PCIe devices to 880 mV to achieve the desired power savings. Change-Id: Ie9f76e65cac22290e85cfba3b7cf2cea4da3eee3 --- qcom/sdxlemur-pcie.dtsi | 2 +- qcom/sdxlemur-regulators.dtsi | 4 ++-- qcom/sdxlemur-usb.dtsi | 4 ++-- qcom/sdxlemur.dtsi | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 56b030f1335a..05b1db8be5e1 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -51,7 +51,7 @@ vreg-mx-supply = <&VDD_MXA_LEVEL>; qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; - qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + qcom,vreg-0p9-voltage-level = <912000 880000 132000>; qcom,vreg-cx-voltage-level = ; qcom,vreg-mx-voltage-level = ; - regulator-min-microvolt = <912000>; + regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; - qcom,init-voltage = <912000>; + qcom,init-voltage = <880000>; qcom,init-mode = ; }; }; diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 12324c0bf30c..5d337b3be5fe 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -117,7 +117,7 @@ reg-names = "hsusb_phy_base", "eud_enable_reg"; vdd-supply = <&pmx65_l4>; - qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-voltage-level = <0 880000 912000>; vdda18-supply = <&pmx65_l5>; vdda33-supply = <&pmx65_l10>; @@ -138,7 +138,7 @@ "pcs_clamp_enable_reg"; vdd-supply = <&pmx65_l4>; - qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-voltage-level = <0 880000 912000>; qcom,vdd-max-load-uA = <47900>; core-supply = <&pmx65_l1>; qcom,core-max-load-uA = <15000>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f83839249eba..78a4a77dafab 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -943,7 +943,7 @@ vreg-mx-supply = <&VDD_MXA_LEVEL>; qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; - qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + qcom,vreg-0p9-voltage-level = <912000 880000 132000>; qcom,vreg-mx-voltage-level = ; clocks = <&gcc GCC_PCIE_PIPE_CLK>, From 58e057d7c59bdf5d6e335a4967971a522bcfa57f Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Fri, 5 Nov 2021 16:13:14 +0800 Subject: [PATCH 1775/1809] ARM: dts: msm: Enable bluetooth for sdxlemur CPE variants Enable bluetooth for sdxlemur CPE variants. Change-Id: I252fe9425ca1505b55b4e1b1c48bc965a0a14e44 --- qcom/sdxlemur-mtp-cpe-pine1x.dts | 1 + qcom/sdxlemur-mtp-cpe-pine2x.dts | 1 + qcom/sdxlemur-v2-mtp-cpe-pine1x.dts | 1 + qcom/sdxlemur-v2-mtp-cpe-pine2x.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dts b/qcom/sdxlemur-mtp-cpe-pine1x.dts index 641531bb3ea2..7fa9d4a9e077 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dts +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dts @@ -4,6 +4,7 @@ #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine1x.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 1x Pine"; diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dts b/qcom/sdxlemur-mtp-cpe-pine2x.dts index e8a4eaa2005a..705c9b4cb1dd 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dts @@ -4,6 +4,7 @@ #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine2x.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 2x Pine"; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts index 6cb3eca2e5ac..8b0d1e19d836 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts @@ -4,6 +4,7 @@ #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine1x.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 1x Pine V2"; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts index a688c1a627c3..77b04077a9ff 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts @@ -4,6 +4,7 @@ #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine2x.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 2x Pine V2"; From 6204011840f41bd71f9857bccfa7552a3bc67df1 Mon Sep 17 00:00:00 2001 From: Anvesh Salveru Date: Sat, 16 Oct 2021 22:33:48 +0530 Subject: [PATCH 1776/1809] ARM: dts: msm: Enable smmu s1 for blsp bam on sdxlemur V2 Enable smmu s1 for blsp bam DMA engine on sdxlemur V2. Change-Id: I66b47f45832d4ce748d1badae685ed20a0da10c5 --- qcom/sdxlemur-v2.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 510d478826da..f2cadc6e4814 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -6,6 +6,20 @@ qcom,msm-id = <458 0x20000>, <483 0x20000>, <509 0x20000>; }; +/* Overriding the BAM node to enable SMMU S1 support in sdxlemur V2 + * Adding i2c SID's in BAM node, as descriptors buffers for i2c + * usecase are allocated in BAM DMA driver. + */ +&dma_blsp1 { + iommus = <&apps_smmu 0x148 0x1>, + <&apps_smmu 0x14a 0x1>, + <&apps_smmu 0x14c 0x1>, + <&apps_smmu 0x14e 0x1>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; +}; + &i2c_1 { iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; From 46b9d03f05598e349749b7722eef96f3c64e97d1 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Fri, 22 Oct 2021 15:25:12 -0400 Subject: [PATCH 1777/1809] ARM: dts: msm: Remove IOSS interface from AQC, RTL and QPS615 Remove IOSS interface nodes as IOSS can now retrieve channel configuration directly from under the device's node. Change-Id: Iad6bbc977c8d15a3c4fe02bcb50ab7173636ca38 --- qcom/sdxlemur-mtp-cpe.dtsi | 22 ---------------------- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 11 ----------- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 23 ----------------------- qcom/sdxlemur-rcm-rc.dtsi | 23 ----------------------- 4 files changed, 79 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index a15655f5e250..02d2e9564558 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -80,24 +80,6 @@ qcom,mod-usecs-min = <30>; qcom,mod-usecs-max = <60>; }; - - ioss_qps615_eth0: qps615@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_aqr_rx>, - <&ioss_aqr_tx>; - }; - - ioss_qps615_eth1: qps615@eth1 { - qcom,name = "eth1"; - qcom,ioss_instance = <1>; - - qcom,ioss_channels = - <&ioss_napa_rx>, - <&ioss_napa_tx>; - }; }; &i2c_5 { @@ -326,8 +308,6 @@ compatible = "qcom,ioss-v2-device"; qcom,phy-rst-gpio = <0>; qcom,ioss = <&ioss>; - qcom,ioss_interfaces = <&ioss_qps615_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_aqr_rx>, @@ -363,8 +343,6 @@ compatible = "qcom,ioss-v2-device"; qcom,phy-rst-gpio = <1>; qcom,ioss = <&ioss>; - qcom,ioss_interfaces = <&ioss_qps615_eth1>; - qcom,ioss_instance = <1>; qcom,ioss_channels = <&ioss_napa_rx>, diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index a1865eadfbbb..2e80095930bb 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -45,15 +45,6 @@ qcom,mod-usecs-min = <30>; qcom,mod-usecs-max = <60>; }; - - ioss_qps615_eth0: qps615@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_qps615_rx>, - <&ioss_qps615_tx>; - }; }; &i2c_3 { @@ -109,8 +100,6 @@ compatible = "qcom,ioss-v2-device"; qcom,ioss = <&ioss>; - qcom,ioss_interfaces = <&ioss_qps615_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_qps615_rx>, diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index dd7f4ded4c26..6bd0120779cc 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -25,15 +25,6 @@ qcom,mod-usecs-max = <128>; }; - ioss_aqc_eth0: aqc@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_aqc_eth0_rx>, - <&ioss_aqc_eth0_tx>; - }; - ioss_r8125_eth0_rx: r8125_rx@eth0 { qcom,dir-rx; qcom,rx-filter-ip; @@ -57,15 +48,6 @@ qcom,mod-usecs-min = <30>; qcom,mod-usecs-max = <60>; }; - - ioss_r8125_eth0: r8125@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_r8125_eth0_rx>, - <&ioss_r8125_eth0_tx>; - }; }; &pcie0_rp { @@ -79,9 +61,6 @@ qcom,ioss = <&ioss>; /* ipa shares this group with aqc */ qcom,iommu-group = <&ipa_eth_group1>; - qcom,ioss_interfaces = - <&ioss_aqc_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_aqc_eth0_rx>, @@ -122,8 +101,6 @@ compatible = "qcom,ioss-v2-device"; qcom,ioss = <&ioss>; - qcom,ioss_interfaces = <&ioss_r8125_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_r8125_eth0_rx>, diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 522f510c7ca0..e6eb6b48d98e 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -39,15 +39,6 @@ qcom,mod-usecs-max = <128>; }; - ioss_aqc_eth0: aqc@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_aqc_eth0_rx>, - <&ioss_aqc_eth0_tx>; - }; - ioss_r8125_eth0_rx: r8125_rx@eth0 { qcom,dir-rx; qcom,rx-filter-ip; @@ -71,15 +62,6 @@ qcom,mod-usecs-min = <30>; qcom,mod-usecs-max = <60>; }; - - ioss_r8125_eth0: r8125@eth0 { - qcom,name = "eth0"; - qcom,ioss_instance = <0>; - - qcom,ioss_channels = - <&ioss_r8125_eth0_rx>, - <&ioss_r8125_eth0_tx>; - }; }; &pcie0_rp { @@ -93,9 +75,6 @@ qcom,ioss = <&ioss>; /* ipa shares this group with aqc */ qcom,iommu-group = <&ipa_eth_group1>; - qcom,ioss_interfaces = - <&ioss_aqc_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_aqc_eth0_rx>, @@ -136,8 +115,6 @@ compatible = "qcom,ioss-v2-device"; qcom,ioss = <&ioss>; - qcom,ioss_interfaces = <&ioss_r8125_eth0>; - qcom,ioss_instance = <0>; qcom,ioss_channels = <&ioss_r8125_eth0_rx>, From 071cbc2427d691babd76a7cb35653d7abd4b868a Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Thu, 14 Oct 2021 00:36:21 +0530 Subject: [PATCH 1778/1809] ARM: dts: qcom: Update mdm tsens thermal config for sdxlemur Add mdmss-0 sensor config and update proper tsens number for remaining mdm sensors for sdxlemur. Change-Id: I1f64a9b965240848ab7761405c88d2ce63aca7dd --- qcom/sdxlemur-thermal.dtsi | 74 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi index eee39c1d8838..5c9bfecf239a 100644 --- a/qcom/sdxlemur-thermal.dtsi +++ b/qcom/sdxlemur-thermal.dtsi @@ -39,11 +39,79 @@ }; }; - mdmss-1-step { + mdmss-0-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens0 3>; + trips { + mdmss0_config0: mdmss0-config0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + + mdmss0_config2: mdmss0-config2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_lte_dsc 7 7>; + }; + + nr_scg_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_scg_dsc 2 2>; + }; + + nr_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_dsc 4 4>; + }; + + lte_cdev1 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev1 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev1 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss0_config2>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss0_config2>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 4>; trips { mdmss1_config0: mdmss1-config0 { temperature = <95000>; @@ -111,7 +179,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; + thermal-sensors = <&tsens0 5>; trips { mdmss2_config0: mdmss2-config0 { temperature = <95000>; @@ -179,7 +247,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 5>; + thermal-sensors = <&tsens0 6>; trips { mdmss3_config0: mdmss3-config0 { temperature = <95000>; From 9e63447466e30b95fe7919cb440e409d74f2a6b2 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Mon, 25 Oct 2021 15:22:40 +0530 Subject: [PATCH 1779/1809] ARM: dts: msm: update modem qmi sensor name upadte modem qmi sensor name as latest recommendation. Change-Id: Iedddaccb490d2d40cb1292a7c1d6343b693b5598 --- qcom/sdxlemur-thermal-modem.dtsi | 34 +++++++++++--------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/qcom/sdxlemur-thermal-modem.dtsi b/qcom/sdxlemur-thermal-modem.dtsi index 1a06dee942bd..e54074abffd8 100644 --- a/qcom/sdxlemur-thermal-modem.dtsi +++ b/qcom/sdxlemur-thermal-modem.dtsi @@ -42,33 +42,33 @@ #cooling-cells = <2>; }; - pa_sdr0_dsc: pa_sdr0_dsc { - qcom,qmi-dev-name = "pa_sdr0_dsc"; + pa_lte_sdr0_dsc: pa_lte_sdr0_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; #cooling-cells = <2>; }; - pa_sdr1_dsc: pa_sdr1_dsc { - qcom,qmi-dev-name = "pa_sdr1_dsc"; + pa_lte_sdr1_dsc: pa_lte_sdr1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; #cooling-cells = <2>; }; - pa_fr1_sdr0_dsc: pa_fr1_sdr0_dsc { - qcom,qmi-dev-name = "pa_fr1_sdr0_dsc"; + pa_nr_sdr0_dsc: pa_nr_sdr0_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; #cooling-cells = <2>; }; - pa_fr1_sdr1_dsc: pa_fr1_sdr1_dsc { - qcom,qmi-dev-name = "pa_fr1_sdr1_dsc"; + pa_nr_sdr1_dsc: pa_nr_sdr1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; #cooling-cells = <2>; }; - pa_fr1_sdr0_scg_dsc: pa_fr1_sdr0_scg_dsc { - qcom,qmi-dev-name = "pa_fr1_sdr0_scg_dsc"; + pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; #cooling-cells = <2>; }; - pa_fr1_sdr1_scg_dsc: pa_fr1_sdr1_scg_dsc { - qcom,qmi-dev-name = "pa_fr1_sdr1_scg_dsc"; + pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; #cooling-cells = <2>; }; @@ -92,11 +92,6 @@ #cooling-cells = <2>; }; - mmw_ul_throttling_dsc: mmw_ul_throttling_dsc { - qcom,qmi-dev-name = "mmw_ul_throttling_dsc"; - #cooling-cells = <2>; - }; - mmw_ific_dsc: mmw_ific_dsc { qcom,qmi-dev-name = "mmw_ific_dsc"; #cooling-cells = <2>; @@ -107,11 +102,6 @@ #cooling-cells = <2>; }; - wlan_bw: wlan_bw { - qcom,qmi-dev-name = "wlan_bw"; - #cooling-cells = <2>; - }; - modem_vdd: modem_vdd { qcom,qmi-dev-name = "cpuv_restriction_cold"; #cooling-cells = <2>; From 816bb0d981a894452da83c33441dc9faf9994c5f Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Mon, 25 Oct 2021 08:20:29 +0530 Subject: [PATCH 1780/1809] dt-bindings: thermal: Add snapshot of modem cdev dt binding Add snapshot of modem cdev devicetree binding to the devicetree project. Change-Id: I374074937f34967a709d1e7e99caffe3ed01e311 --- bindings/thermal/qti-qmi-cdev.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/bindings/thermal/qti-qmi-cdev.txt b/bindings/thermal/qti-qmi-cdev.txt index d22547641936..de5011e56a60 100644 --- a/bindings/thermal/qti-qmi-cdev.txt +++ b/bindings/thermal/qti-qmi-cdev.txt @@ -73,6 +73,29 @@ Subsystem properties: device, "pa_dsc" -> DSC based pa cooling device, "pa_fr1_dsc" -> DSC based pa cooling device. + "modem_lte_dsc" -> DSC based modem lte cooling device, + "modem_nr_dsc" -> DSC based modem nr cooling device, + "modem_nr_scg_dsc" -> DSC based modem nr scg cooling + device, + "sdr0_lte_dsc" -> DSC based sdr0 lte cooling device, + "sdr1_lte_dsc" -> DSC based sdr1 lte cooling device, + "sdr0_nr_dsc" -> DSC based sdr0 nr cooling device, + "sdr1_nr_dsc" -> DSC based sdr1 nr cooling device, + "pa_lte_sdr0_dsc" -> DSC based pa lte sdr0 cooling + device, + "pa_lte_sdr1_dsc" -> DSC based pa lte sdr1 cooling + device, + "pa_nr_sdr0_dsc" -> DSC based pa nr sdr0 cooling device, + "pa_nr_sdr1_dsc" -> DSC based pa nr sdr1 cooling device, + "pa_nr_sdr0_scg_dsc" -> DSC based pa nr sdr0 scg cooling + device, + "pa_nr_sdr1_scg_dsc" -> DSC based pa nr sdr1 scg cooling + device, + "mmw0_dsc" -> DSC based MMW cooling device0, + "mmw1_dsc" -> DSC based MMW cooling device1, + "mmw2_dsc" -> DSC based MMW cooling device2, + "mmw3_dsc" -> DSC based MMW cooling device3, + "mmw_ific_dsc" -> DSC based MMW IFIC cooling device. -#cooling-cells: Usage: required From 9c080396210b082f33940763a2512299121e46fa Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Thu, 21 Oct 2021 17:39:18 +0530 Subject: [PATCH 1781/1809] ARM: dts: msm: add devfreq-vdd-cdev cooling device and remove gfx-cdev add devfreq-vdd-cedv cooling device in zeroC thermalzone and remove gfx-cdev. Change-Id: Iccba4006d8114531f2bb4284af82e3e942b2b49a --- qcom/holi-regulators-pm6125.dtsi | 14 -------------- qcom/holi-regulators-pm6350.dtsi | 8 -------- qcom/holi-thermal.dtsi | 14 ++++++++++---- 3 files changed, 10 insertions(+), 26 deletions(-) diff --git a/qcom/holi-regulators-pm6125.dtsi b/qcom/holi-regulators-pm6125.dtsi index 652065155f87..e5f25c6397f4 100644 --- a/qcom/holi-regulators-pm6125.dtsi +++ b/qcom/holi-regulators-pm6125.dtsi @@ -74,10 +74,6 @@ regulator-s3-level-ao { status = "disabled"; }; - - gfx-cdev { - status = "disabled"; - }; }; /* Disable mx_cdev for PM6150A */ @@ -434,16 +430,6 @@ ; qcom,use-voltage-level; }; - - gfx_cdev: gfx-cdev { - status = "okay"; - compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&S8A_LEVEL_AO>; - regulator-levels = ; - #cooling-cells = <2>; - }; - }; /* VDD_LPI_CX supply */ diff --git a/qcom/holi-regulators-pm6350.dtsi b/qcom/holi-regulators-pm6350.dtsi index 179cd8900a8f..c0679f636d22 100644 --- a/qcom/holi-regulators-pm6350.dtsi +++ b/qcom/holi-regulators-pm6350.dtsi @@ -50,14 +50,6 @@ ; qcom,use-voltage-level; }; - - gfx_cdev: gfx-cdev { - compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&S3A_LEVEL_AO>; - regulator-levels = ; - #cooling-cells = <2>; - }; }; /* PM6350 L1 - VDD_MX supply */ diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index 958f6b7d74b7..2ba52043e83f 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -72,6 +72,12 @@ #cooling-cells = <2>; status = "disabled"; }; + + devfreq_vdd_cdev: devfreq-vdd-cdev { + compatible = "qcom,devfreq-vdd-cooling-device"; + devfreq = <&msm_gpu>; + #cooling-cells = <2>; + }; }; &rpm_bus { @@ -1167,9 +1173,9 @@ cooling-device = <&mx_cdev 1 1>; }; - gfx_vdd_cdev { + devfreq_vdd_cdev { trip = <&zeroc_0_trip>; - cooling-device = <&gfx_cdev 1 1>; + cooling-device = <&devfreq_vdd_cdev 2 2>; }; adsp_vdd_cdev { @@ -1214,9 +1220,9 @@ cooling-device = <&mx_cdev 1 1>; }; - gfx_vdd_cdev { + devfreq_vdd_cdev { trip = <&zeroc_1_trip>; - cooling-device = <&gfx_cdev 1 1>; + cooling-device = <&devfreq_vdd_cdev 2 2>; }; adsp_vdd_cdev { From 98b681ca15937c3694d5fbe980ffd9456d72800e Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Sun, 31 Oct 2021 11:42:01 +0530 Subject: [PATCH 1782/1809] ARM: dts: msm: remove gfx-cdev for blair remove gfx-cdev for blair. Change-Id: Ib7e793482bc67a43815667edb2acc9a40ddcde5b --- qcom/blair-atp.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/qcom/blair-atp.dtsi b/qcom/blair-atp.dtsi index f0e0e0cab6be..4f1257eed568 100644 --- a/qcom/blair-atp.dtsi +++ b/qcom/blair-atp.dtsi @@ -347,10 +347,6 @@ regulator-s3-level-ao { status = "okay"; }; - - gfx-cdev { - status = "okay"; - }; }; /* Enable mx_cdev for PM6350 */ From 68901f62246e2d3e5fa7ffc4bd5944ce18e7a758 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Wed, 10 Nov 2021 14:55:46 +0530 Subject: [PATCH 1783/1809] ARM: dts: msm: update thermal config for sdxlemur update thermal config for sdxlemux based on latest recommendation. Change-Id: Ia653ada0153fbcc55fdebe794693ddf03c2c563f --- qcom/sdxlemur-thermal.dtsi | 219 +++++++++---------------------------- 1 file changed, 51 insertions(+), 168 deletions(-) diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi index 5c9bfecf239a..5ca372177e6d 100644 --- a/qcom/sdxlemur-thermal.dtsi +++ b/qcom/sdxlemur-thermal.dtsi @@ -23,18 +23,39 @@ thermal-governor = "step_wise"; thermal-sensors = <&tsens0 1>; trips { - cpu_config: active-config0 { + cpu_config0: active-config0 { temperature = <95000>; - hysteresis = <0>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_config1: active-config1 { + temperature = <97000>; + hysteresis = <3000>; + type = "passive"; + }; + + cpu_config2: active-config2 { + temperature = <99000>; + hysteresis = <3000>; type = "passive"; }; }; cooling-maps { - cpu_cdev { - trip = <&cpu_config>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; + cpu_cdev0 { + trip = <&cpu_config0>; + cooling-device = <&CPU0 1 1>; + }; + + cpu_cdev1 { + trip = <&cpu_config1>; + cooling-device = <&CPU0 2 2>; + }; + + cpu_cdev2 { + trip = <&cpu_config2>; + cooling-device = <&CPU0 3 THERMAL_NO_LIMIT>; }; }; }; @@ -46,64 +67,16 @@ thermal-sensors = <&tsens0 3>; trips { mdmss0_config0: mdmss0-config0 { - temperature = <95000>; - hysteresis = <5000>; + temperature = <111000>; + hysteresis = <3000>; type = "passive"; }; mdmss0_config1: mdmss0-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <115000>; + hysteresis = <2000>; type = "passive"; }; - - mdmss0_config2: mdmss0-config2 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - lte_cdev0 { - trip = <&mdmss0_config0>; - cooling-device = <&modem_lte_dsc 7 7>; - }; - - nr_scg_cdev0 { - trip = <&mdmss0_config0>; - cooling-device = <&modem_nr_scg_dsc 2 2>; - }; - - nr_cdev0 { - trip = <&mdmss0_config0>; - cooling-device = <&modem_nr_dsc 4 4>; - }; - - lte_cdev1 { - trip = <&mdmss0_config1>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - nr_scg_cdev1 { - trip = <&mdmss0_config1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; - }; - - nr_cdev1 { - trip = <&mdmss0_config1>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - lte_cdev2 { - trip = <&mdmss0_config2>; - cooling-device = <&modem_lte_dsc 255 255>; - }; - - nr_cdev2 { - trip = <&mdmss0_config2>; - cooling-device = <&modem_nr_dsc 255 255>; - }; }; }; @@ -114,20 +87,14 @@ thermal-sensors = <&tsens0 4>; trips { mdmss1_config0: mdmss1-config0 { - temperature = <95000>; - hysteresis = <5000>; + temperature = <111000>; + hysteresis = <3000>; type = "passive"; }; mdmss1_config1: mdmss1-config1 { - temperature = <100000>; - hysteresis = <5000>; - type = "passive"; - }; - - mdmss1_config2: mdmss1-config2 { - temperature = <105000>; - hysteresis = <5000>; + temperature = <115000>; + hysteresis = <2000>; type = "passive"; }; }; @@ -135,41 +102,26 @@ cooling-maps { lte_cdev0 { trip = <&mdmss1_config0>; - cooling-device = <&modem_lte_dsc 7 7>; + cooling-device = <&modem_lte_dsc 8 8>; }; nr_scg_cdev0 { trip = <&mdmss1_config0>; - cooling-device = <&modem_nr_scg_dsc 2 2>; + cooling-device = <&modem_nr_scg_dsc 10 10>; }; nr_cdev0 { trip = <&mdmss1_config0>; - cooling-device = <&modem_nr_dsc 4 4>; + cooling-device = <&modem_nr_dsc 6 6>; }; lte_cdev1 { trip = <&mdmss1_config1>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - nr_scg_cdev1 { - trip = <&mdmss1_config1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; + cooling-device = <&modem_lte_dsc 255 255>; }; nr_cdev1 { trip = <&mdmss1_config1>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - lte_cdev2 { - trip = <&mdmss1_config2>; - cooling-device = <&modem_lte_dsc 255 255>; - }; - - nr_cdev2 { - trip = <&mdmss1_config2>; cooling-device = <&modem_nr_dsc 255 255>; }; }; @@ -182,64 +134,16 @@ thermal-sensors = <&tsens0 5>; trips { mdmss2_config0: mdmss2-config0 { - temperature = <95000>; - hysteresis = <5000>; + temperature = <111000>; + hysteresis = <3000>; type = "passive"; }; mdmss2_config1: mdmss2-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <115000>; + hysteresis = <2000>; type = "passive"; }; - - mdmss2_config2: mdmss2-config2 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - lte_cdev0 { - trip = <&mdmss2_config0>; - cooling-device = <&modem_lte_dsc 7 7>; - }; - - nr_scg_cdev0 { - trip = <&mdmss2_config0>; - cooling-device = <&modem_nr_scg_dsc 2 2>; - }; - - nr_cdev0 { - trip = <&mdmss2_config0>; - cooling-device = <&modem_nr_dsc 4 4>; - }; - - lte_cdev1 { - trip = <&mdmss2_config1>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - nr_scg_cdev1 { - trip = <&mdmss2_config1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; - }; - - nr_cdev1 { - trip = <&mdmss2_config1>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - lte_cdev2 { - trip = <&mdmss2_config2>; - cooling-device = <&modem_lte_dsc 255 255>; - }; - - nr_cdev2 { - trip = <&mdmss2_config2>; - cooling-device = <&modem_nr_dsc 255 255>; - }; }; }; @@ -250,20 +154,14 @@ thermal-sensors = <&tsens0 6>; trips { mdmss3_config0: mdmss3-config0 { - temperature = <95000>; - hysteresis = <5000>; + temperature = <111000>; + hysteresis = <3000>; type = "passive"; }; mdmss3_config1: mdmss3-config1 { - temperature = <100000>; - hysteresis = <5000>; - type = "passive"; - }; - - mdmss3_config2: mdmss3-config2 { - temperature = <105000>; - hysteresis = <5000>; + temperature = <115000>; + hysteresis = <2000>; type = "passive"; }; }; @@ -271,41 +169,26 @@ cooling-maps { lte_cdev0 { trip = <&mdmss3_config0>; - cooling-device = <&modem_lte_dsc 7 7>; + cooling-device = <&modem_lte_dsc 8 8>; }; nr_scg_cdev0 { trip = <&mdmss3_config0>; - cooling-device = <&modem_nr_scg_dsc 2 2>; + cooling-device = <&modem_nr_scg_dsc 10 10>; }; nr_cdev0 { trip = <&mdmss3_config0>; - cooling-device = <&modem_nr_dsc 4 4>; + cooling-device = <&modem_nr_dsc 6 6>; }; lte_cdev1 { trip = <&mdmss3_config1>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - nr_scg_cdev1 { - trip = <&mdmss3_config1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; + cooling-device = <&modem_lte_dsc 255 255>; }; nr_cdev1 { trip = <&mdmss3_config1>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - lte_cdev2 { - trip = <&mdmss3_config2>; - cooling-device = <&modem_lte_dsc 255 255>; - }; - - nr_cdev2 { - trip = <&mdmss3_config2>; cooling-device = <&modem_nr_dsc 255 255>; }; }; From d393592509b1a3b0913fc60ce8af65694f2df008 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Mon, 25 Oct 2021 08:53:41 +0530 Subject: [PATCH 1784/1809] dt-bindings: thermal: Add snapshot of devfreq-vdd-cdev Add dt-bindings for cooling device which will be used to set minimum operating level for gfx rail using gpu devfreq interface during cold thermal condition. Change-Id: I66116350e0df379556c7caa01658c4ab9d844848 --- bindings/thermal/qcom,devfreq-vdd-cdev.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 bindings/thermal/qcom,devfreq-vdd-cdev.txt diff --git a/bindings/thermal/qcom,devfreq-vdd-cdev.txt b/bindings/thermal/qcom,devfreq-vdd-cdev.txt new file mode 100644 index 000000000000..a3ff787cd185 --- /dev/null +++ b/bindings/thermal/qcom,devfreq-vdd-cdev.txt @@ -0,0 +1,34 @@ +Qualcomm Technologies, Inc. Devfreq Vdd cooling device + +The Devfreq Vdd cooling device, will be used to set minimum +operating level for gfx rail using gpu devfreq interface +during cold thermal condition. This cooling device will be +used with cold temp monitor thermal zone. Whenever cold +temperature triggers, it disables frequencies lower than +the minimum operating level using devfreq opp API's. + +Required Parameters: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,devfreq-vdd-cooling-device" + +- devfreq: + Usage: required + Value type: + Definition: Phandle to the GPU devfreq. This will register the GPU + devfreq as a cooling device with thermal framework. + +- #cooling-cells: + Usage: required + Value type: + Definition: Must be 2. This is required by of-thermal and refer the doc + for more details. + +Example: + + devfreq_vdd_cdev: devfreq-vdd-cdev { + compatible = "qcom,devfreq-vdd-cooling-device"; + devfreq = <&msm_gpu>; + #cooling-cells = <2>; + }; From f4abf0fb248c4ca3a6513100e039d884c9016fb5 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Tue, 22 Jun 2021 10:53:21 +0800 Subject: [PATCH 1785/1809] dt-bindings: subsystem_sleep_stats: Add reg as required property This adds reg as required proerty to subsystem_sleep_stats driver. This driver can support to get soc sleep information. Change-Id: I2f3477265987899f62990d2c5915a79af779f981 --- bindings/arm/msm/subsystem-sleep-stats.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/arm/msm/subsystem-sleep-stats.yaml b/bindings/arm/msm/subsystem-sleep-stats.yaml index 53e038718b83..3e7c8e5fb549 100644 --- a/bindings/arm/msm/subsystem-sleep-stats.yaml +++ b/bindings/arm/msm/subsystem-sleep-stats.yaml @@ -23,9 +23,12 @@ properties: Value type: Definition: Should be "qcom,subsystem-sleep-stats". + reg: + maxItems: 1 example: - | subsystem-sleep-stats { compatible = "qcom,subsystem-sleep-stats"; + reg = <0xc3f0000 0 0x400>; }; From 89717b75ba081876062d9595f577c472f256deb8 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Wed, 17 Nov 2021 14:38:44 +0530 Subject: [PATCH 1786/1809] dt-bindings: subsystem_sleep_stats: reg is optional property This change updates binding document to make compatible property as required and reg as optional. Change-Id: I2ac7205557ab93e0000f53b88af1462fc732f5aa --- bindings/arm/msm/subsystem-sleep-stats.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/arm/msm/subsystem-sleep-stats.yaml b/bindings/arm/msm/subsystem-sleep-stats.yaml index 3e7c8e5fb549..d7a7a80f199e 100644 --- a/bindings/arm/msm/subsystem-sleep-stats.yaml +++ b/bindings/arm/msm/subsystem-sleep-stats.yaml @@ -26,6 +26,9 @@ properties: reg: maxItems: 1 +required: + - compatible + example: - | subsystem-sleep-stats { From 661e4f3603b9d47309fca92aa50ccaf1695aaadd Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Thu, 16 Sep 2021 15:44:53 +0530 Subject: [PATCH 1787/1809] ARM: dts: msm: Enable subsystem_sleep_stats driver for lahaina This change enables subsystem_sleep_stats driver. Change-Id: I2b9ad8b0d0f3e7588e629d6efac9626d49c06e30 --- qcom/lahaina-pm.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-pm.dtsi b/qcom/lahaina-pm.dtsi index 7ed8f6961ada..1918104a5fd2 100644 --- a/qcom/lahaina-pm.dtsi +++ b/qcom/lahaina-pm.dtsi @@ -130,6 +130,11 @@ reg = <0xb221200 0x60>; }; + subsystem-sleep-stats { + compatible = "qcom,subsystem-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; + soc-sleep-stats@c3f0000 { compatible = "qcom,rpmh-sleep-stats"; reg = <0xc3f0000 0x400>; From ecd9e357018a04eb83abac2c0b805d1816993509 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 19 Nov 2021 15:41:49 +0530 Subject: [PATCH 1788/1809] ARM: dts: qcom: add mode control for S8B regulator for yupik PMIC PM8350 SMPS regulator S8B is a parent of several LDO regulators. Barring an application processor mode request, the S8B mode transitions from AUTO to retention when entering AOSS sleep. This can cause brown-outs if any of the child LDOs is drawing significant current. Add mode control support for S8B so that application processor consumers can vote to keep S8B in AUTO mode when needed. This avoids power faults during AOSS sleep. Change-Id: I15473250b44aa1c07a0a7013eb49130e0f016ed4 --- qcom/yupik-regulators.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index d3964932dad7..aabf6d843478 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -46,6 +46,11 @@ rpmh-regulator-smpb8 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb8"; + qcom,regulator-type = "pmic5-hfsmps"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 200000>; S8B: pm7325_s8: regulator-pm7325-s8 { regulator-name = "pm7325_s8"; @@ -53,6 +58,7 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; qcom,init-voltage = <1272000>; + qcom,init-mode = ; }; }; From 26d6b319cda9a09bbd540692eaa93da313f1103d Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 24 Nov 2021 12:02:16 +0530 Subject: [PATCH 1789/1809] ARM: dts: msm: Add additional v2 variant for sdxlemur board Add additional v2 variant for sdxlemur board. Change-Id: I5f1f64b3c54b2b59f5bd5e9b0a50488bd1a0525c --- qcom/Makefile | 3 ++- qcom/sdxlemur-v2-m2-ep-fwa.dts | 14 ++++++++++++++ qcom/sdxlemur-v2-m2-ep-fwa.dtsi | 2 ++ 3 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-v2-m2-ep-fwa.dts create mode 100644 qcom/sdxlemur-v2-m2-ep-fwa.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index d04599bb040e..cfe040cf7742 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -453,7 +453,8 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-v2-mtp-mbb-m2-ep-usb.dtb \ sdxlemur-v2-mtp-mbb-m2-ep.dtb \ sdxlemur-v2-rcm-rc-pine1x.dtb \ - sdxlemur-v2-rcm-rc-pine2x.dtb + sdxlemur-v2-rcm-rc-pine2x.dtb \ + sdxlemur-v2-m2-ep-fwa.dtb diff --git a/qcom/sdxlemur-v2-m2-ep-fwa.dts b/qcom/sdxlemur-v2-m2-ep-fwa.dts new file mode 100644 index 000000000000..79554246b8cb --- /dev/null +++ b/qcom/sdxlemur-v2-m2-ep-fwa.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi" +#include "sdxlemur-mtp-mbb-m2-ep.dtsi" +#include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-v2-m2-ep-fwa.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR M2 EP FWA V2"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x11010008 0x311>; +}; diff --git a/qcom/sdxlemur-v2-m2-ep-fwa.dtsi b/qcom/sdxlemur-v2-m2-ep-fwa.dtsi new file mode 100644 index 000000000000..336d7a250678 --- /dev/null +++ b/qcom/sdxlemur-v2-m2-ep-fwa.dtsi @@ -0,0 +1,2 @@ +/ { +}; From ead5c2e76931879cb6b3562a186c32a17ff87b68 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Fri, 26 Nov 2021 14:44:09 +0530 Subject: [PATCH 1790/1809] ARM: dts: qcom: Enable QCN9000 nodes for sdxlemur-mtp-cpe-pine2x Enable QCN9000 wifi, reserved memory, GPIO and PCIe nodes for sdxlemur-mtp-cpe-pine2x.dtsi. Change-Id: Ife764d2519b94a2b02a6f99f853bab88f5ee8841 --- qcom/sdxlemur-mtp-cpe-pine2x.dtsi | 80 ++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi index a7373e1f2622..2fc2b95bc75d 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi @@ -1,4 +1,82 @@ +#include "sdxlemur-qcn9000.dtsi" &soc { - + pine_vreg: pine_vreg { + compatible = "regulator-fixed"; + regulator-name = "pine_vreg"; + gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-enable-ramp-delay = <200000>; + }; +}; + +&qps615_vreg { + vin-supply = <&pine_vreg>; +}; + +&pcie_i2c_ctrl { + reg_update = <0x82c030 0x1 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x2 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x8 + 0x828000 0x1 + 0x82bd00 0x8 + 0x82c01c 0x10 + 0x82c030 0xf + 0x828000 0xf + 0x82b268 0x2>; +}; + +&pcie0 { + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; +}; + +&pcie0_bus2_dev1_fn0 { + cnss_pci1: cnss_pci1 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&qcn9000_pci_iommu_group_0>; + memory-region = <&qcn9000_0_mem>; + qrtr_instance_id = <0x20>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&pcie0_bus2_dev2_fn0 { + cnss_pci2: cnss_pci2 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&qcn9000_pci_iommu_group_1>; + memory-region = <&qcn9000_1_mem>; + qrtr_instance_id = <0x21>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&wifi0 { + status = "ok"; + board_id = <0xa0>; +}; + +&wifi1 { + status = "ok"; + board_id = <0xa1>; +}; + +&qcn9000_0_mem { + status = "ok"; +}; + +&qcn9000_1_mem { + status = "ok"; }; From ff4a7a9a2e7a479d7c460c94d9ce1aebd745f2da Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Fri, 26 Nov 2021 15:16:10 +0530 Subject: [PATCH 1791/1809] ARM: dts: msm: Add LPM info for menu governor Add LPM info for the menu governor for Blair. Change-Id: Ifc7b162c9f7b2dd11de17963e5bf21a612724b50 --- qcom/blair.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index ea1fbcdd046c..b16c64f920a6 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -63,6 +63,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -86,6 +87,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -103,6 +105,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -120,6 +123,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -138,6 +142,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; @@ -155,6 +160,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; @@ -171,6 +177,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + cpu-idle-states = <&GOLD_PC &GOLD_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; @@ -189,6 +196,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + cpu-idle-states = <&GOLD_PC &GOLD_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; From bc335e4782339fdfdd7a762e2cda7b61e7bab066 Mon Sep 17 00:00:00 2001 From: Karthik Rudrapatna Date: Wed, 1 Dec 2021 23:38:22 -0800 Subject: [PATCH 1792/1809] ARM: dts: msm: Added delay for AQR113 PHY to come of reset Added delay for AQR113 PHY to be in ready state after PHY reset. Change-Id: I90003b155e4567c2a9bed6539f70ec4f7f99b465 --- qcom/sdxlemur-mtp-cpe.dtsi | 2 ++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 02d2e9564558..d7b101a13cc8 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -321,6 +321,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; phy-supply = <&aqr_vreg>; + qcom,phy-rst-delay-us = <221000>; #address-cells = <1>; #size-cells = <1>; @@ -357,6 +358,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group2>; phy-supply = <&qca_vreg>; + qcom,phy-rst-delay-us = <0>; #address-cells = <1>; #size-cells = <1>; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 2e80095930bb..8700d095ec32 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -108,6 +108,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; phy-supply = <&aqr_vreg>; + qcom,phy-rst-delay-us = <221000>; interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; From 443bbdfb4eef35f0cb09c77a4bd1130a7d7c985b Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Fri, 26 Nov 2021 15:16:10 +0530 Subject: [PATCH 1793/1809] ARM: dts: msm: Add LPM info for menu governor Add LPM info for the menu governor for Blair. Change-Id: Ifc7b162c9f7b2dd11de17963e5bf21a612724b50 --- qcom/blair.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index ea1fbcdd046c..b16c64f920a6 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -63,6 +63,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -86,6 +87,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -103,6 +105,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -120,6 +123,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -138,6 +142,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; @@ -155,6 +160,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&SLVR_PC &SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; cpu-release-addr = <0x0 0x50000000>; @@ -171,6 +177,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + cpu-idle-states = <&GOLD_PC &GOLD_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; @@ -189,6 +196,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + cpu-idle-states = <&GOLD_PC &GOLD_RAIL_OFF>; enable-method = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <520>; From cb678add930c936eaf1bfe4a930241b24dc38e11 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 1 Dec 2021 16:02:54 +0800 Subject: [PATCH 1794/1809] ARM: dts: msm: Update the modem size to 102MB Restrict modem to 102MB to free up the user space by another 8MB. Change-Id: I3d5628ef19879a45809a6a60b1977c08e6390e2c --- qcom/sdxnightjar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index b15152a754e5..a4f19d3b600f 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -49,7 +49,7 @@ mss_mem: mss_region@0x88000000 { no-map; - reg = <0x88000000 0x6e00000>; + reg = <0x88000000 0x6600000>; label = "mss_mem"; }; From 877f0ef191e1af7ac3e5a04cdf20f48ddf762e30 Mon Sep 17 00:00:00 2001 From: Karthik Rudrapatna Date: Wed, 8 Dec 2021 07:48:21 -0800 Subject: [PATCH 1795/1809] ARM: dts: msm: Added delay for Napa PHY to come of reset Added delay of 20ms for Napa PHY to be in ready state after PHY reset. Change-Id: I5990f1f63714f5c3684347149a0e80366a3439ea --- qcom/sdxlemur-mtp-cpe.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index d7b101a13cc8..dde1e97716da 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -358,7 +358,7 @@ /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group2>; phy-supply = <&qca_vreg>; - qcom,phy-rst-delay-us = <0>; + qcom,phy-rst-delay-us = <20000>; #address-cells = <1>; #size-cells = <1>; From 392af73fccd2482a029bf34e9373c53f3f6eb488 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Mon, 6 Dec 2021 11:24:30 +0530 Subject: [PATCH 1796/1809] ARM: dts: msm: Enable focaltech touch node for r66451 on Blair CDP This change adds focaltech touch support touch support on Blair CDP. Change-Id: I1e208162c9d9cc68649764b8357e56dcf75b4073 --- qcom/blair-cdp.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qcom/blair-cdp.dtsi b/qcom/blair-cdp.dtsi index 3a04bd70fe5f..25a18cd8d133 100644 --- a/qcom/blair-cdp.dtsi +++ b/qcom/blair-cdp.dtsi @@ -261,7 +261,7 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - qcom,i2c-touch-active="synaptics,tcm-i2c"; + qcom,i2c-touch-active= "synaptics,tcm-i2c"; synaptics_tcm@20 { compatible = "synaptics,tcm-i2c"; @@ -309,6 +309,9 @@ pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; }; novatek@62 { From d0e9c1615e4f46a2fc524762f289fef4824caf68 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 18 Nov 2021 01:42:41 +0530 Subject: [PATCH 1797/1809] ARM: dts: msm: Reducing throughput thresholds For LAN-LAN use cases, there won't be any other peripheral vote and IPA vote will not scale correctly. Make changes to reduce the throughput thresholds. Change-Id: I1efae007aad76aa9e80c7d001fff74bf710d4344 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index daf2d7859546..cea955d07a5d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1242,7 +1242,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <3000 5000 10000>; + qcom,throughput-threshold = <2000 2500 10000>; qcom,scaling-exceptions = <>; ipa_smmu_ap: ipa_smmu_ap { From d7ae73d7359d4c8028218246830b57dda37a5f4a Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 14 Dec 2021 21:23:17 +0530 Subject: [PATCH 1798/1809] ARM: dts: msm: Remove mpm wakeup control capability for yupik This change removes mpm wakeup control capability. Controlling this can override the request by client driver to keep it disabled for certain gpios and may lead to false IRQ seen at GIC for same GPIOs. Change-Id: I6ddfc61e276684c33d2e39ab820c1465d0d1dfb6 --- qcom/yupik-pinctrl.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 9cc831f32f2f..85d64c6d5ce4 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -8,7 +8,6 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qcom,tlmm-mpm-wake-control; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { qupv3_se0_i2c_active: qupv3_se0_i2c_active { From 4b6419564d88208af94c41219fc3ceccf8557407 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 23 Dec 2021 14:03:16 +0530 Subject: [PATCH 1799/1809] ARM: dts: msm: Enable sdx-ext-ipc driver Enable sdx-ext-ipc driver for fwa dts with updated GPIOs. Change-Id: I70591fa2c5992bc5e7ac8704e2870cdd981a6c52 --- qcom/sdxlemur-mtp-mbb-m2-ep.dts | 4 ++++ qcom/sdxlemur-v2-m2-ep-fwa.dts | 7 +++++++ qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-m2-ep.dts b/qcom/sdxlemur-mtp-mbb-m2-ep.dts index 07688f87358c..48447ec9e98d 100644 --- a/qcom/sdxlemur-mtp-mbb-m2-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-m2-ep.dts @@ -11,3 +11,7 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x8010008 0x308>; }; + +&sdx_ext_ipc { + status = "ok"; +}; diff --git a/qcom/sdxlemur-v2-m2-ep-fwa.dts b/qcom/sdxlemur-v2-m2-ep-fwa.dts index 79554246b8cb..54b4378980c0 100644 --- a/qcom/sdxlemur-v2-m2-ep-fwa.dts +++ b/qcom/sdxlemur-v2-m2-ep-fwa.dts @@ -12,3 +12,10 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x11010008 0x311>; }; + +&sdx_ext_ipc { + qcom,status-in-gpio = <&tlmm 12 0x00>; + qcom,status-out-gpio = <&tlmm 13 0x00>; + qcom,status-out2-gpio = <&tlmm 15 0x00>; + status = "ok"; +}; diff --git a/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts b/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts index c67a84f09691..37b1cc8284cd 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-m2-ep.dts @@ -11,3 +11,7 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x8010008 0x308>; }; + +&sdx_ext_ipc { + status = "ok"; +}; From 03956755f3ef15f23420cc37e48c0d70715eab00 Mon Sep 17 00:00:00 2001 From: Raghavendar rao l Date: Mon, 27 Dec 2021 22:57:44 +0530 Subject: [PATCH 1800/1809] ARM: dts: msm: Enable ipa register dump collection Change to enable the ipa register collection from IPA APPS driver. Change-Id: I527fbec6a014d392cc846cacfd618ad3e8d558b4 --- qcom/lahaina.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c940fa425421..d0f145fe829f 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4665,6 +4665,7 @@ qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; + qcom,register-collection-on-crash; clock-names = "core_clk"; clocks = <&clock_rpmh RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; From a240e221b8875beee8870084f074806f8542a6a8 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Mon, 27 Dec 2021 15:47:06 +0800 Subject: [PATCH 1801/1809] ARM: dts: msm: correct SSCTL instance ID for SMP2P shutdown ack from modem Correct SSCTL instance ID to register the SSCTL QMI service. Change-Id: If7b82c8e4ed50df52184972c9eca77e5a53f859d --- qcom/sdxnightjar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi index a4f19d3b600f..c75d57edf105 100644 --- a/qcom/sdxnightjar.dtsi +++ b/qcom/sdxnightjar.dtsi @@ -187,7 +187,7 @@ qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; - qcom,ssctl-instance-id = <0x12>; + qcom,ssctl-instance-id = <0x22>; qcom,override-acc; qcom,qdsp6v61-1-1; memory-region = <&mss_mem>; From da07ad889bd416fb5eae6279e7ed1f585083b1e6 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 30 Dec 2021 13:11:58 +0530 Subject: [PATCH 1802/1809] ARM: dts: msm: Fix ipq attach property for sdx driver Enable ipc driver and move ipq807x_attach property to ep dts only. Change-Id: I65e05063ac9106e68bd96b1c7aa47d24c01885f0 --- qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi | 5 +---- qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts | 5 +++++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi index 445c95bfce1c..a8a6ecc24d35 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep-ipq.dtsi @@ -70,7 +70,4 @@ qcom,iommu-dma = "bypass"; }; -&sdx_ext_ipc { - ipq807x_attach = <1>; - status = "ok"; -}; + diff --git a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts index eed8f4538c10..58375d3d5253 100644 --- a/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts +++ b/qcom/sdxlemur-v2-mtp-mbb-pcie-ep-ipq.dts @@ -10,3 +10,8 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0xB010008 0x20B>; }; + +&sdx_ext_ipc { + ipq807x_attach = <1>; + status = "ok"; +}; From a20646f28a88c6263fb399fed57a42684f0998b8 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Fri, 7 Jan 2022 17:54:52 +0530 Subject: [PATCH 1803/1809] ARM: dts: qcom: Set right IRQ type to MHI interrupt Set right IRQ type property for MHI interrupt, Without this getting below warning during bootup WARNING: drivers/irqchip/irq-gic.c:gic_irq_domain_translate (gic_irq_domain_translate) (irq_create_fwspec_mapping) (irq_create_of_mapping) (of_irq_get) (__platform_get_irq_byname) (platform_get_irq_byname) (mhi_dev_probe). Change-Id: I86b3cb88ebd297d16fa0c6a27e96870845a0077b --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7187570188f5..9f80db1850aa 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1141,7 +1141,7 @@ qcom,mhi-ep-msi = <0>; qcom,mhi-version = <0x1000000>; qcom,use-ipa-software-channel; - interrupts = <0 145 0>; + interrupts = ; interrupt-names = "mhi-device-inta"; qcom,mhi-ifc-id = <0x030817cb>; qcom,mhi-interrupt; From 196f161a3b8b8ba1449e58cbc6ce9d692e6f896b Mon Sep 17 00:00:00 2001 From: Shivali M S Date: Sun, 9 Jan 2022 18:11:27 +0530 Subject: [PATCH 1804/1809] ARM: dts: msm: Updating the PHY version for sdxlemur Update of internal PHY version for sdxlemur. Change-Id: I7645b2f9f6fe0bfafcb1283b50b780bd48f88c30 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7187570188f5..b1e720c7677b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -978,7 +978,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0308>; qcom,pcie-link-speed = <4>; - qcom,pcie-phy-ver = <8>; + qcom,pcie-phy-ver = <7>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; From 60a6dd19524dc45e4f8dc08db1e5c76d1b4bb644 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Thu, 12 Aug 2021 16:49:20 +0530 Subject: [PATCH 1805/1809] ARM: dts: msm: Add BOOT_CONFIG register offset for sdxlemur Add BOOT_CONFIG to support the EDL over PCIe for sdxlemur. Change-Id: Ia33b56d3bbb4e4bf4df1f6ac049b5b85d1938c5a --- qcom/sdxlemur-v2.dtsi | 5 +++++ qcom/sdxlemur.dtsi | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index f2cadc6e4814..2d9f76145127 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -173,3 +173,8 @@ &pil_modem { qcom,vdd_mss-uV-uA = ; }; + + +&dload_mode { + qcom,boot-config-shift = <1 4>; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7187570188f5..84615c9ee0ed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -196,8 +196,11 @@ }; }; - dload_mode { + dload_mode: dload_mode { compatible = "qcom,dload-mode"; + reg = <0x786070 0x4>; + reg-names = "boot-config"; + qcom,boot-config-shift = <1 3>; }; dcc: dcc_v2@117f000 { From 0a173e2445eb1e857f4bba0f371459649d8c7f0d Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 11 Jan 2022 10:55:48 +0530 Subject: [PATCH 1806/1809] bindings: power: reset: Add qcom-dload-mode bindings for SDX65 Add additional devicetree properties to qcom-dload-mode bindings for SDX65. Change-Id: I2671025430538c6f94c0d2a75eb6ff61f3a1b82f --- bindings/power/reset/qcom,dload-mode.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/bindings/power/reset/qcom,dload-mode.yaml b/bindings/power/reset/qcom,dload-mode.yaml index 067d6eb2b032..ce65735c956b 100644 --- a/bindings/power/reset/qcom,dload-mode.yaml +++ b/bindings/power/reset/qcom,dload-mode.yaml @@ -16,6 +16,18 @@ properties: compatible: items: - const: qcom,dload-mode + reg: + Value type: + Definition: The base address and size for reading the proper configuration + related information. + + reg-names: + Value type: string + Definition: The reg name for reading the configurations. + + qcom,boot-config-shift: + Value type: + Definition: The range of bits from low to high. required: - compatible From c8b1a887c8048e6698aa504ad021f1c24ece6bf3 Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Thu, 20 Jan 2022 10:50:24 +0530 Subject: [PATCH 1807/1809] ARM: dts: msm: Limit the PCIe speed to Gen3 for sdxlemur Limit the PCIe speed to Gen3 for sdxlemur Change-Id: Iac2cb2b50a61f038868d0f678b9bcebd047788c1 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 463320b94b03..cc4a9bf5b24d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -977,7 +977,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0308>; - qcom,pcie-link-speed = <4>; + qcom,pcie-link-speed = <3>; qcom,pcie-phy-ver = <7>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; From 2354537e23f501caa7a6775f6b4063f2e5045a95 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Fri, 28 Jan 2022 22:06:03 +0530 Subject: [PATCH 1808/1809] ARM: dts: msm: Disable LPM States for SDXLEMUR + QCN9000 QCN9000 does not supports low power mode. This change disables LPM for SDXLEMUR + QCN9000 variants. Change-Id: I588b96b3cf2479fa098b36a07ce04cba9f04d8a8 --- qcom/sdxlemur-qcn9000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index 48709022c247..d3ec2dcd34c0 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -24,6 +24,11 @@ }; &soc { + /* If QCN9000 is connected, LPM modes are disabled */ + qcom,lpm-levels { + status = "disabled"; + }; + wifi0: qcom,cnss-qcn9000@a0000000 { status = "disabled"; compatible = "qcom,cnss-qcn9000"; From 1070b4ca120c7c33f6d9fd9cf424353b420df701 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 1 Feb 2022 23:52:28 +0530 Subject: [PATCH 1809/1809] ARM: dts: msm: Modify GPIO28 functionality as per pinctrl change This change modifies GPIO28 function from qup11 to qup11_f1 as per the pinctrl driver change. Depends-on CR: 3112278. Change-Id: Ie102cebddaaf6dd6985fabd0b5f43294714a0f8e --- qcom/blair-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair-pinctrl.dtsi b/qcom/blair-pinctrl.dtsi index 9cb472d3e943..5a916a277291 100644 --- a/qcom/blair-pinctrl.dtsi +++ b/qcom/blair-pinctrl.dtsi @@ -337,7 +337,7 @@ qupv3_se7_i2c_active: qupv3_se7_i2c_active { mux { pins = "gpio27", "gpio28"; - function = "qup11"; + function = "qup11_f1"; }; config {