From 35e72953c4f100349fdbfe8c1361aefcb0244ff0 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 1 Mar 2021 17:15:27 +0530 Subject: [PATCH] ARM: dts: msm: Add CX and MX SDPM configuration for YUPIK Add CX SDPM configuration to monitor Camera, Display clocks. Add MX SDPM configuration to monitor Camera, Display clocks. Change-Id: I8c08a41e5d37f8768c661a79967b0e7e3509a489 --- qcom/yupik-thermal.dtsi | 156 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 44d153ae5721..c177df006ec2 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -61,6 +61,40 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <1 4>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <0 2>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &qmi_tmd { @@ -1294,4 +1328,126 @@ }; }; }; + + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_cpu4 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu4_isolate 0 0>; + }; + + mx_pe_cdev_cpu5 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu5_isolate 0 0>; + }; + + mx_pe_cdev_cpu6 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu6_isolate 0 0>; + }; + + mx_pe_cdev_cpu7 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu7_isolate 0 0>; + }; + + mx_pe_cdev_cdsp { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_gpu { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_modem { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config4>; + cooling-device = <&msm_gpu 0 0>; + }; + }; + }; };