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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: [TG3]: Bump driver version and reldate. [TG3]: Skip phy power down on some devices [TG3]: Fix SRAM access during tg3_init_one() [X25]: dte facilities 32 64 ioctl conversion [X25]: allow ITU-T DTE facilities for x25 [X25]: fix kernel error message 64 bit kernel [X25]: ioctl conversion 32 bit user to 64 bit kernel [NET]: socket timestamp 32 bit handler for 64 bit kernel [NET]: allow 32 bit socket ioctl in 64 bit kernel [BLUETOOTH]: Return negative error constant
This commit is contained in:
commit
36177ba655
12 changed files with 366 additions and 31 deletions
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@ -69,8 +69,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.52"
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#define DRV_MODULE_RELDATE "Mar 06, 2006"
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#define DRV_MODULE_VERSION "3.53"
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#define DRV_MODULE_RELDATE "Mar 22, 2006"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -1148,6 +1148,19 @@ static int tg3_halt_cpu(struct tg3 *, u32);
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static int tg3_nvram_lock(struct tg3 *);
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static void tg3_nvram_unlock(struct tg3 *);
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static void tg3_power_down_phy(struct tg3 *tp)
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{
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/* The PHY should not be powered down on some chips because
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* of bugs.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
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(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
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return;
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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}
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static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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{
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u32 misc_host_ctrl;
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@ -1327,8 +1340,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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tg3_power_down_phy(tp);
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}
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}
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@ -9436,12 +9448,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
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return NULL;
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}
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/* Since this function may be called in D3-hot power state during
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* tg3_init_one(), only config cycles are allowed.
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*/
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static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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{
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u32 val;
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u16 pmcsr;
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/* On some early chips the SRAM cannot be accessed in D3hot state,
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* so need make sure we're in D0.
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*/
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pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
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pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
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msleep(1);
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/* Make sure register accesses (indirect or otherwise)
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* will function correctly.
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