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iommu/arm-smmu: Mask TLBI address correctly

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The less said about "~12UL" the better. Oh dear.

We get away with it due to calling constraints that mean IOVAs are
implicitly at least page-aligned to begin with, but still; oh dear.

Change-Id: I8e4ed0ccc1aae76988449895e6f7a9944d429af6
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Git-commit: 353b325047
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
This commit is contained in:
Robin Murphy 2019-08-15 19:37:21 +01:00 • committed by Isaac J. Manjarres
commit 367d9d7d5f
1 changed files with 1 additions and 1 deletions
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2
drivers/iommu/arm-smmu.c
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@ -1186,7 +1186,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) {
iova &= ~12UL;
iova = (iova >> 12) << 12;
iova |= cfg->asid;
do {
writel_relaxed(iova, reg);