From 37bca0ee008fee17956b0b95e77ba3382fea1e93 Mon Sep 17 00:00:00 2001
From: Mukesh Kumar Savaliya <msavaliy@qti.qualcomm.com>
Date: Thu, 19 Dec 2019 18:38:24 +0530
Subject: [PATCH] ARM: dts: msm: Enable s1 in fastmap for QUPv3 drivers on
 lahaina

Enable SMMU s1 stage in fastmap for QUPv3 drivers to reduce the dma
unmap latency caused in ATOMIC map.

Change-Id: I2bf5427112d3074b751ab72734c1fd51fd6e1275
---
 qcom/lahaina-qupv3.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/qcom/lahaina-qupv3.dtsi b/qcom/lahaina-qupv3.dtsi
index 03adf8f0a6e1..dab025c04b98 100644
--- a/qcom/lahaina-qupv3.dtsi
+++ b/qcom/lahaina-qupv3.dtsi
@@ -34,7 +34,7 @@
 			<MASTER_QUP_0 SLAVE_EBI1>;
 		iommus = <&apps_smmu 0x5a3 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
-		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma = "fastmap";
 	};
 
 	/* GPI */
@@ -412,7 +412,7 @@
 			<MASTER_QUP_1 SLAVE_EBI1>;
 		iommus = <&apps_smmu 0x43 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
-		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma = "fastmap";
 	};
 
 	/* GPI */
@@ -739,7 +739,7 @@
 			<MASTER_QUP_2 SLAVE_EBI1>;
 		iommus = <&apps_smmu 0x5e3 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
-		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma = "fastmap";
 	};
 
 	/* GPI */