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Merge "clk: qcom: clk-alpha-pll: Add support for Fabia print registers"

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qctecmdr 2020-04-15 20:35:59 -07:00 • committed by Gerrit - the friendly Code Review server
commit 37d0a368db
2 changed files with 140 additions and 40 deletions
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178
drivers/clk/qcom/clk-alpha-pll.c
View file

@ -93,6 +93,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
},
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_CAL_L_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x14,
@ -114,10 +115,10 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_CONFIG_CTL_U1] = 0x20,
[PLL_OFF_TEST_CTL] = 0x24,
[PLL_OFF_TEST_CTL_U] = 0x28,
[PLL_OFF_TEST_CTL_U1] = 0x2c,
[PLL_OFF_STATUS] = 0x30,
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_ALPHA_VAL] = 0x40,
[PLL_OFF_CAL_VAL] = 0x44,
},
[CLK_ALPHA_PLL_TYPE_LUCID] = {
[PLL_OFF_L_VAL] = 0x04,
@ -215,9 +216,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
#define ZONDA_5LPE_ENABLE_VOTE_RUN BIT(21)
#define TRION_PLL_STANDBY 0x0
#define TRION_PLL_RUN 0x1
#define TRION_PLL_OUT_MASK 0x7
/* FABIA PLL specific settings */
#define FABIA_PLL_CAL_VAL 0x3F
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
@ -843,7 +843,8 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
if (ret)
return 0;
return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
return ((opmode_regval & PLL_OPMODE_RUN) &&
(mode_regval & PLL_OUTCTRL));
}
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
@ -873,7 +874,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
}
/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
@ -881,7 +882,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
/* Enable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
@ -914,12 +915,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
/* Disable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
TRION_PLL_OUT_MASK, 0);
PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
@ -927,33 +928,12 @@ static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 l, frac;
u64 prate = parent_rate;
u32 l, frac, alpha_width = pll_alpha_width(pll);
regmap_read(regmap, PLL_L_VAL(pll), &l);
regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
}
static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long min_freq, max_freq;
u32 l;
u64 a;
rate = alpha_pll_round_rate(rate, *prate,
&l, &a, ALPHA_REG_16BIT_WIDTH);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
static int __zonda_pll_is_enabled(struct clk_alpha_pll *pll,
@ -1497,7 +1477,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_trion_pll_round_rate,
.round_rate = clk_alpha_pll_round_rate,
#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif
@ -1695,14 +1675,24 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, mask;
if (!config) {
pr_err("PLL configuration missing.\n");
return -EINVAL;
}
if (config->l)
regmap_write(regmap, PLL_L_VAL(pll), config->l);
if (config->cal_l)
regmap_write(regmap, PLL_CAL_L_VAL(pll), config->cal_l);
else
regmap_write(regmap, PLL_CAL_L_VAL(pll), FABIA_PLL_CAL_VAL);
if (config->alpha)
regmap_write(regmap, PLL_FRAC(pll), config->alpha);
@ -1710,6 +1700,26 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_write(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
if (config->config_ctl_hi_val)
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
if (config->user_ctl_val)
regmap_write(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
if (config->user_ctl_hi_val)
regmap_write(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
if (config->test_ctl_val)
regmap_write(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
if (config->test_ctl_hi_val)
regmap_write(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
if (config->post_div_mask) {
mask = config->post_div_mask;
val = config->post_div_val;
@ -1720,6 +1730,8 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
PLL_UPDATE_BYPASS);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
return 0;
}
EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
@ -1727,7 +1739,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, opmode_val;
u32 val, l_val, cal_val, opmode_val;
struct regmap *regmap = pll->clkr.regmap;
ret = regmap_read(regmap, PLL_MODE(pll), &val);
@ -1750,6 +1762,24 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
if ((opmode_val & PLL_OPMODE_RUN) && (val & PLL_OUTCTRL))
return 0;
ret = regmap_read(regmap, PLL_L_VAL(pll), &l_val);
if (ret)
return ret;
ret = regmap_read(regmap, PLL_CAL_L_VAL(pll), &cal_val);
if (ret)
return ret;
/* PLL has lost it's L or CAL value, needs reconfiguration */
if (!l_val || !cal_val) {
ret = clk_fabia_pll_configure(pll, regmap, pll->config);
if (ret) {
pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
return ret;
}
pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");
}
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return ret;
@ -1827,15 +1857,27 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, l, alpha_width = pll_alpha_width(pll);
u32 l, cal_val, alpha_width = pll_alpha_width(pll);
u64 a;
unsigned long rrate;
int ret = 0;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
ret = regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), &cal_val);
if (ret)
return ret;
/* PLL has lost it's CAL value, needs reconfiguration */
if (!cal_val) {
ret = clk_fabia_pll_configure(pll, pll->clkr.regmap,
pll->config);
if (ret) {
pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
return ret;
}
pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
clk_hw_get_name(hw));
}
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
/*
@ -1853,6 +1895,60 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
return __clk_alpha_pll_update_latch(pll);
}
static void clk_fabia_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
int size, i, val;
static struct clk_register_data data[] = {
{"PLL_MODE", PLL_OFF_MODE},
{"PLL_L_VAL", PLL_OFF_L_VAL},
{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},
{"PLL_USER_CTL", PLL_OFF_USER_CTL},
{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
{"PLL_STATUS", PLL_OFF_STATUS},
{"PLL_OPMODE", PLL_OFF_OPMODE},
{"PLL_FRAC", PLL_OFF_FRAC},
};
static struct clk_register_data data1[] = {
{"APSS_PLL_VOTE", 0x0},
};
size = ARRAY_SIZE(data);
for (i = 0; i < size; i++) {
regmap_read(pll->clkr.regmap, pll->offset +
pll->regs[data[i].offset], &val);
seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
}
regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],
&val);
if (val & PLL_FSM_ENA) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}
static struct clk_regmap_ops clk_fabia_pll_regmap_ops = {
.list_registers = &clk_fabia_pll_list_registers,
};
static void clk_fabia_pll_init(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
if (!rclk->ops)
rclk->ops = &clk_fabia_pll_regmap_ops;
}
const struct clk_ops clk_alpha_pll_fabia_ops = {
.prepare = clk_prepare_regmap,
.unprepare = clk_unprepare_regmap,
@ -1864,6 +1960,8 @@ const struct clk_ops clk_alpha_pll_fabia_ops = {
.set_rate = alpha_pll_fabia_set_rate,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.debug_init = clk_common_debug_init,
.init = clk_fabia_pll_init,
#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif
@ -1880,6 +1978,8 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.debug_init = clk_common_debug_init,
.init = clk_fabia_pll_init,
#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif

2
drivers/clk/qcom/clk-alpha-pll.h
View file

@ -154,7 +154,7 @@ extern const struct clk_ops clk_trion_pll_postdiv_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);