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ARM: arm-soc device tree changes, part 2
These are mostly new device tree bindings for existing drivers, as well as changes to the device tree source files to add support for those devices, and a couple of new boards, most notably Samsung's Exynos5 based Chromebook. The changes depend on earlier platform specific updates and touch the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUYgjh2CrR//JCVInAQJTvRAAmxaeoI+kQ/pbbRDa/Mnhf+bUmQjvJvx4 uFGYAAi23Txem2Bx6xrfvOo9//ATYSfRxenoSSOtXQucsnrqD0+837Sj2NbO6AB9 MSiFDK4usJtGwSUybkSHNLb2QPBr8XTgmyWVE/sHEw2UtrIToC1n3sxFofFm0guT ReILKsgK0Wjyq5RntnjWOCHNNp6OGqDGvFXlSJqNA7Z6gR/VZy4o0oXS4Sv3TWgF zG7ngSG7/u9FP1IQnMr/SxY1T4QS/bBbAC1YvD/7X30DPHrWKR3/3LfLcsc9TUN2 smTlZQjHdgBbGfVPL7JN0fQwA82HEjNSZKLJ0w9uFjxXgnoKT3znpUpQeuf3dsWm BhEFqN1Rf446S4ft2btBSB2nhX4NTlJ7w6z2F65xgaylgYFsGFTYcpjiOurKe3wF gGsw31DZdcuI4/LjiWbNGRKbMd7HFFLbFDMJ16TFbNcNr+pM3qpoQ6z3uMbfCBSe xFnYr+ESN8F2HXMNLiz3CTqLY+Fi/bHd22n3KuI9qsWws/0KDUrTvFh9Sm3kYji5 QwwLl6PRoeFw8H29e3KrPsKoY/BGYAvrAetnC1o79cDFPLwUyii/1B6WwzC4ynfs K1VhwdVOwnp0sS/a2Pv8sZBpDNI07gwT9P20aiholxgREq2RKNXXVxGGFfK5Qvm9 FG4Vp6EKEQ0= =G60S -----END PGP SIGNATURE----- Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates (part 2) from Arnd Bergmann: "These are mostly new device tree bindings for existing drivers, as well as changes to the device tree source files to add support for those devices, and a couple of new boards, most notably Samsung's Exynos5 based Chromebook. The changes depend on earlier platform specific updates and touch the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci." * tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits) ARM: exynos: dts: cros5250: add EC device ARM: dts: Add sbs-battery for exynos5250-snow ARM: dts: Add i2c-arbitrator bus for exynos5250-snow ARM: dts: add mshc controller node for Exynos4x12 SoCs ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree ARM: davinci: da850-evm: add SPI flash support ARM: davinci: da850: override SPI DT node device name ARM: davinci: da850: add SPI1 DT node spi/davinci: add DT binding documentation spi/davinci: no wildcards in DT compatible property ARM: dts: mvebu: Convert mvebu device tree files to 64 bits ARM: dts: mvebu: introduce internal-regs node ARM: dts: mvebu: Convert all the mvebu files to use the range property ARM: dts: mvebu: move all peripherals inside soc ARM: dts: mvebu: fix cpus section indentation ARM: davinci: da850: add EHRPWM & ECAP DT node ARM/dts: OMAP3: fix pinctrl-single configuration ARM: dts: Add OMAP3430 SDP NOR flash memory binding ARM: dts: Add NOR flash bindings for OMAP2420 H4 ...
This commit is contained in:
commit
38f56f33ca
143 changed files with 7751 additions and 3048 deletions
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@ -776,10 +776,10 @@ rx_dma_failed:
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#if defined(CONFIG_OF)
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static const struct of_device_id davinci_spi_of_match[] = {
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{
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.compatible = "ti,dm644x-spi",
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.compatible = "ti,dm6441-spi",
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},
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{
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.compatible = "ti,da8xx-spi",
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.compatible = "ti,da830-spi",
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.data = (void *)SPI_VERSION_2,
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},
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{ },
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@ -490,21 +490,6 @@ static int mxs_spi_transfer_one(struct spi_master *master,
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return status;
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}
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static bool mxs_ssp_dma_filter(struct dma_chan *chan, void *param)
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{
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struct mxs_ssp *ssp = param;
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if (!mxs_dma_is_apbh(chan))
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return false;
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if (chan->chan_id != ssp->dma_channel)
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return false;
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chan->private = &ssp->dma_data;
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return true;
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}
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static const struct of_device_id mxs_spi_dt_ids[] = {
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{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
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{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
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@ -520,13 +505,12 @@ static int mxs_spi_probe(struct platform_device *pdev)
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struct spi_master *master;
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struct mxs_spi *spi;
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struct mxs_ssp *ssp;
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struct resource *iores, *dmares;
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struct resource *iores;
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struct pinctrl *pinctrl;
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struct clk *clk;
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void __iomem *base;
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int devid, dma_channel, clk_freq;
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int ret = 0, irq_err, irq_dma;
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dma_cap_mask_t mask;
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int devid, clk_freq;
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int ret = 0, irq_err;
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/*
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* Default clock speed for the SPI core. 160MHz seems to
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@ -537,8 +521,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq_err = platform_get_irq(pdev, 0);
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irq_dma = platform_get_irq(pdev, 1);
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if (!iores || irq_err < 0 || irq_dma < 0)
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if (!iores || irq_err < 0)
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return -EINVAL;
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base = devm_ioremap_resource(&pdev->dev, iores);
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@ -553,32 +536,11 @@ static int mxs_spi_probe(struct platform_device *pdev)
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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if (np) {
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devid = (enum mxs_ssp_id) of_id->data;
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/*
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* TODO: This is a temporary solution and should be changed
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* to use generic DMA binding later when the helpers get in.
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*/
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ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
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&dma_channel);
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if (ret) {
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dev_err(&pdev->dev,
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"Failed to get DMA channel\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "clock-frequency",
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&clk_freq);
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if (ret)
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clk_freq = clk_freq_default;
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} else {
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!dmares)
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return -EINVAL;
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devid = pdev->id_entry->driver_data;
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dma_channel = dmares->start;
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devid = (enum mxs_ssp_id) of_id->data;
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ret = of_property_read_u32(np, "clock-frequency",
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&clk_freq);
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if (ret)
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clk_freq = clk_freq_default;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(*spi));
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if (!master)
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@ -597,7 +559,6 @@ static int mxs_spi_probe(struct platform_device *pdev)
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ssp->clk = clk;
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ssp->base = base;
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ssp->devid = devid;
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ssp->dma_channel = dma_channel;
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init_completion(&spi->c);
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@ -606,10 +567,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
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if (ret)
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goto out_master_free;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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ssp->dma_data.chan_irq = irq_dma;
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ssp->dmach = dma_request_channel(mask, mxs_ssp_dma_filter, ssp);
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ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
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if (!ssp->dmach) {
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dev_err(ssp->dev, "Failed to request DMA\n");
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ret = -ENODEV;
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