From 3934ca8ec6fd194497188022cb2eda40df067706 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Thu, 28 Feb 2019 18:58:13 -0800 Subject: [PATCH] clk: qcom: clk-rcg2: Fix QUPV3 DFSR M and N register mode overwrite Move reading of MN counter mode register earlier to source sel to fix overwrite of MN counter mode variable. Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326 Signed-off-by: Vivek Aknurwar --- drivers/clk/qcom/clk-rcg2.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 7230719324e4..5d65e32c4a8c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. */ #include @@ -1243,6 +1243,9 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, if (cfg & mask) f->pre_div = cfg & mask; + mode = cfg & CFG_MODE_MASK; + mode >>= CFG_MODE_SHIFT; + cfg &= CFG_SRC_SEL_MASK; cfg >>= CFG_SRC_SEL_SHIFT; @@ -1255,8 +1258,6 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, } } - mode = cfg & CFG_MODE_MASK; - mode >>= CFG_MODE_SHIFT; if (mode) { mask = BIT(rcg->mnd_width) - 1; regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),