From f28a68723fe4d22130f40ee4fd79821e579de648 Mon Sep 17 00:00:00 2001
From: Anurag Chouhan <achouhan@qti.qualcomm.com>
Date: Mon, 21 Dec 2020 12:13:37 +0530
Subject: [PATCH] ARM: dts: msm: Update CMA region for monaco

. Update CMA memory region
. fix compilation error for monaco-ion.

Change-Id: I66469ae2147c567ce8805dcdc452c8d334b4cbb6
---
 qcom/monaco-ion.dtsi          |  1 +
 qcom/monaco.dtsi              | 24 ++++++++++++++++++++++++
 qcom/msm-arm-smmu-monaco.dtsi |  8 ++++----
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi
index fe3f006d9574..ce1a9e482129 100644
--- a/qcom/monaco-ion.dtsi
+++ b/qcom/monaco-ion.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/arm/msm/msm_ion_ids.h>
 &soc {
 	qcom,ion {
 		compatible = "qcom,msm-ion";
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index 4f480c12f34b..d4a79502b755 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -195,6 +195,30 @@
 			size = <0 0x800000>;
 		};
 
+		qseecom_ta_mem: qseecom_ta_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		secure_display_memory: secure_display_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x5c00000>;
+		};
+
+		adsp_mem: adsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x800000>;
+		};
+
 		/* global autoconfigured region for contiguous allocations */
 		linux,cma {
 			compatible = "shared-dma-pool";
diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi
index 8e6cc4e08ab7..c9e6c47f03df 100644
--- a/qcom/msm-arm-smmu-monaco.dtsi
+++ b/qcom/msm-arm-smmu-monaco.dtsi
@@ -39,7 +39,7 @@
 				/* ALL CBs of GFX: +15 deep PF */
 				<0x0 0x3ff 0x30B>;
 
-		gfx_0_tbu: gfx_0_tbu@0x59c5000 {
+		gfx_0_tbu: gfx_0_tbu@0x59dd000 {
 				compatible = "qcom,qsmmuv500-tbu";
 				reg = <0x59dd000 0x1000>,
 					<0x59da200 0x8>;
@@ -141,7 +141,7 @@
 					/* For nrt TBU +3 deep PF */
 					<0x800 0x3ff 0x103>;
 
-				anoc_1_tbu: anoc_1_tbu@0xc785000 {
+				anoc_1_tbu: anoc_1_tbu@0xc7f5000 {
 					compatible = "qcom,qsmmuv500-tbu";
 					reg = <0xc7f5000 0x1000>,
 						<0xc7f2200 0x8>;
@@ -159,7 +159,7 @@
 						<MASTER_AMPSS_M0 SLAVE_IMEM_CFG 0 1000>;
 				};
 
-				mm_rt_tbu: mm_rt_tbu@0xc789000 {
+				mm_rt_tbu: mm_rt_tbu@0xc7f9000 {
 					compatible = "qcom,qsmmuv500-tbu";
 					reg = <0xc7f9000 0x1000>,
 						<0xc7f2208 0x8>;
@@ -177,7 +177,7 @@
 						<MASTER_MDP_PORT0 SLAVE_SNOC_BIMC_RT 0 1000>;
 				};
 
-				mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
+				mm_nrt_tbu: mm_nrt_tbu@0xc7fd000 {
 					compatible = "qcom,qsmmuv500-tbu";
 					reg = <0xc7fd000 0x1000>,
 						<0xc7f2210 0x8>;