mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 16:16:15 -04:00
Merge "ARM: dts: msm: Add hab and peripherals for sa8155 vm"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
3980a5270b
7 changed files with 913 additions and 6 deletions
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@ -21,7 +21,7 @@
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ranges;
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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linux_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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@ -50,24 +50,34 @@
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firmware: firmware {
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android {
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compatible = "android,firmware";
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boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,boot,system,vendor,dtbo";
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parts = "vbmeta,system,vendor";
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};
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fstab {
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compatible = "android,fstab";
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vendor {
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compatible = "android,vendor";
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dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc";
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dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vendor";
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type = "ext4";
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mnt_flags = "ro,barrier=1,discard";
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fsmgr_flags = "wait";
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fsmgr_flags = "wait,avb";
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status = "ok"
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};
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};
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};
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};
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vdevs {
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compatible = "simple-bus";
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virtio_input_keyboard@1c150000 {
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compatible = "virtio,mmio";
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virtio,wakeup;
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};
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};
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};
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&soc {
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@ -115,7 +125,7 @@
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system_heap: qcom,ion-heap@25 {
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reg = <ION_SYSTEM_HEAP_ID>;
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qcom,ion-heap-type = "SYSTEM";
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qcom,ion-heap-type = "MSM_SYSTEM";
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};
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qcom,ion-heap@27 { /* QSEECOM HEAP */
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@ -131,6 +141,83 @@
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};
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};
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hab: qcom,hab {
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compatible = "qcom,hab";
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vmid = <2>;
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mmidgrp100: mmidgrp100 {
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grp-start-id = <100>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp200: mmidgrp200 {
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grp-start-id = <200>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp300: mmidgrp300 {
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grp-start-id = <300>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp400: mmidgrp400 {
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grp-start-id = <400>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp500: mmidgrp500 {
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grp-start-id = <500>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp600: mmidgrp600 {
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grp-start-id = <600>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp700: mmidgrp700 {
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grp-start-id = <700>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp800: mmidgrp800 {
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grp-start-id = <800>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp900: mmidgrp900 {
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grp-start-id = <900>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp1000: mmidgrp1000 {
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grp-start-id = <1000>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp1100: mmidgrp1100 {
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grp-start-id = <1100>;
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role = "fe";
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remote-vmids = <0>;
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};
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mmidgrp1200: mmidgrp1200 {
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grp-start-id = <1200>;
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role = "fe";
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remote-vmids = <0>;
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};
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};
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qcom,msm-imem@14680000 {
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compatible = "qcom,msm-imem";
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reg = <0x14680000 0x1000>;
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@ -4,3 +4,27 @@
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label = "pmem_shared_mem";
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};
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};
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&usb0 {
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status = "ok"
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};
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&usb2_phy0 {
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status = "ok"
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};
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&qupv3_se13_4uart {
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status = "ok"
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};
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&pcie0_msi {
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status = "ok"
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};
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&pcie0 {
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status = "ok"
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};
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&sdhc_2 {
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status = "ok"
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};
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@ -1,6 +1,30 @@
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&hab {
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vmid = <3>;
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};
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&reserved_memory {
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pmem_shared: pmem_shared_region {
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reg = <0x1 0x2c200000 0x0 0x53e00000>;
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label = "pmem_shared_mem";
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};
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};
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&usb0 {
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status = "ok"
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};
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&usb2_phy0 {
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status = "ok"
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};
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&pcie0_msi {
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status = "ok"
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};
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&pcie0 {
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status = "ok"
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};
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&qupv3_se13_4uart {
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status = "ok"
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};
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@ -1,6 +1,30 @@
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&hab {
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vmid = <3>;
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};
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&reserved_memory {
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pmem_shared: pmem_shared_region {
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reg = <0x1 0x6a500000 0x0 0x51400000>;
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label = "pmem_shared_mem";
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};
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};
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&usb0 {
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status = "ok"
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};
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&usb2_phy0 {
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status = "ok"
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};
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&pcie0_msi {
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status = "ok"
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};
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&pcie0 {
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status = "ok"
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};
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&qupv3_se13_4uart {
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status = "ok"
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};
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272
qcom/sa8155-vm-pcie.dtsi
Normal file
272
qcom/sa8155-vm-pcie.dtsi
Normal file
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@ -0,0 +1,272 @@
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c00000 0x4000>,
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<0x1c06000 0x1000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>,
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<0x60200000 0x100000>,
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<0x60300000 0x3d00000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "io", "bars";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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qcom,phy-sequence = <0x0840 0x03 0x0
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0x0094 0x08 0x0
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0x0154 0x34 0x0
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0x016c 0x08 0x0
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0x0058 0x0f 0x0
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0x00a4 0x42 0x0
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0x0110 0x24 0x0
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0x011c 0x03 0x0
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0x0118 0xb4 0x0
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0x010c 0x02 0x0
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0x01bc 0x11 0x0
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0x00bc 0x82 0x0
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0x00d4 0x03 0x0
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0x00d0 0x55 0x0
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0x00cc 0x55 0x0
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0x00b0 0x1a 0x0
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0x00ac 0x0a 0x0
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0x00c4 0x68 0x0
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0x00e0 0x02 0x0
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0x00dc 0xaa 0x0
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0x00d8 0xab 0x0
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0x00b8 0x34 0x0
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0x00b4 0x14 0x0
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0x0158 0x01 0x0
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0x0074 0x06 0x0
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0x007c 0x16 0x0
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0x0084 0x36 0x0
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0x0078 0x06 0x0
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0x0080 0x16 0x0
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0x0088 0x36 0x0
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0x01b0 0x1e 0x0
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0x01ac 0xb9 0x0
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0x01b8 0x18 0x0
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0x01b4 0x94 0x0
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0x0050 0x07 0x0
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0x0010 0x00 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x029c 0x12 0x0
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0x0284 0x35 0x0
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0x023c 0x11 0x0
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0x051c 0x03 0x0
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0x0518 0x1c 0x0
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0x0524 0x1e 0x0
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0x04e8 0x00 0x0
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0x04ec 0x0e 0x0
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0x04f0 0x4a 0x0
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0x04f4 0x0f 0x0
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0x05b4 0x04 0x0
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0x0434 0x7f 0x0
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0x0444 0x70 0x0
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0x0510 0x17 0x0
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0x04d4 0x54 0x0
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0x04d8 0x07 0x0
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0x0598 0xd4 0x0
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0x059c 0x54 0x0
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0x05a0 0xdb 0x0
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0x05a4 0x3b 0x0
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0x05a8 0x31 0x0
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0x0584 0x24 0x0
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0x0588 0xe4 0x0
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0x058c 0xec 0x0
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0x0590 0x3b 0x0
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0x0594 0x36 0x0
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0x0570 0xff 0x0
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0x0574 0xff 0x0
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0x0578 0xff 0x0
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0x057c 0x7f 0x0
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0x0580 0x66 0x0
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0x04fc 0x00 0x0
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0x04f8 0xc0 0x0
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0x0460 0x30 0x0
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0x0464 0xc0 0x0
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0x05bc 0x0c 0x0
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0x04dc 0x0d 0x0
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0x0408 0x0c 0x0
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0x0414 0x03 0x0
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0x09a4 0x01 0x0
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0x0c90 0x00 0x0
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0x0c40 0x01 0x0
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0x0c48 0x01 0x0
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0x0c50 0x00 0x0
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0x0cbc 0x00 0x0
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0x0ce0 0x58 0x0
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0x0048 0x90 0x0
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0x0c1c 0xc1 0x0
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0x0988 0x88 0x0
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0x0998 0x0b 0x0
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0x08dc 0x0d 0x0
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0x09ec 0x01 0x0
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0x0800 0x00 0x0
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0x0844 0x03 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
|
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&pcie0_perst_default
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&pcie0_wake_default>;
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||||
|
||||
perst-gpio = <&tlmm 35 0>;
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wake-gpio = <&tlmm 37 0>;
|
||||
|
||||
gdsc-vdd-supply = <&pcie_0_gdsc>;
|
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vreg-1p8-supply = <&pm8150_2_l8>;
|
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vreg-0p9-supply = <&pm8150_2_l18>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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||||
|
||||
|
||||
qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;
|
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qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
|
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
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RPMH_REGULATOR_LEVEL_NOM 0>;
|
||||
qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
|
||||
RPMH_REGULATOR_LEVEL_NOM 100000000>;
|
||||
|
||||
qcom,no-l0s-supported;
|
||||
msi-parent = <&pcie0_msi>;
|
||||
qcom,ep-latency = <10>;
|
||||
|
||||
qcom,slv-addr-space-size = <0x4000000>;
|
||||
|
||||
qcom,phy-status-offset = <0x814>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x840>;
|
||||
|
||||
qcom,boot-option = <0x1>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
qcom,pcie-phy-ver = <2110>;
|
||||
qcom,use-19p2mhz-aux-clk;
|
||||
|
||||
qcom,smmu-sid-base = <0x1d80>;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
qcom,core-preset = <0x77777777>;
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
|
||||
<0x100 &apps_smmu 0x1d81 0x1>,
|
||||
<0x200 &apps_smmu 0x1d82 0x1>,
|
||||
<0x300 &apps_smmu 0x1d83 0x1>,
|
||||
<0x400 &apps_smmu 0x1d84 0x1>,
|
||||
<0x500 &apps_smmu 0x1d85 0x1>,
|
||||
<0x600 &apps_smmu 0x1d86 0x1>,
|
||||
<0x700 &apps_smmu 0x1d87 0x1>,
|
||||
<0x800 &apps_smmu 0x1d88 0x1>,
|
||||
<0x900 &apps_smmu 0x1d89 0x1>,
|
||||
<0xa00 &apps_smmu 0x1d8a 0x1>,
|
||||
<0xb00 &apps_smmu 0x1d8b 0x1>,
|
||||
<0xc00 &apps_smmu 0x1d8c 0x1>,
|
||||
<0xd00 &apps_smmu 0x1d8d 0x1>,
|
||||
<0xe00 &apps_smmu 0x1d8e 0x1>,
|
||||
<0xf00 &apps_smmu 0x1d8f 0x1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_CLKREF_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
|
||||
<&gcc GCC_PCIE_PHY_AUX_CLK>;
|
||||
|
||||
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
|
||||
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
|
||||
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
|
||||
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
|
||||
"pcie_tbu_clk", "pcie_phy_refgen_clk",
|
||||
"pcie_phy_aux_clk";
|
||||
|
||||
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_PHY_BCR>;
|
||||
|
||||
reset-names = "pcie_0_core_reset",
|
||||
"pcie_0_phy_reset";
|
||||
|
||||
pcie_rc0: pcie_rc0 {
|
||||
#address-cells = <5>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0 0 0 0>;
|
||||
pci-ids = "17cb:0108";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_msi: qcom,pcie0_msi@17a00040 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x17a00040 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
};
|
||||
351
qcom/sa8155-vm-usb.dtsi
Normal file
351
qcom/sa8155-vm-usb.dtsi
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
|
||||
|
||||
&soc {
|
||||
/* Primary USB port related controller */
|
||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0x0a600000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk", "xo";
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
|
||||
qcom,charging-disabled;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0a600000 0xcd00>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
usb-core-id = <0>;
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
qcom,usbbam@a704000 {
|
||||
compatible = "qcom,usb-bam-msm";
|
||||
reg = <0xa704000 0x17000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
|
||||
qcom,usb-bam-num-pipes = <4>;
|
||||
qcom,disable-clk-gating;
|
||||
qcom,usb-bam-override-threshold = <0x4001>;
|
||||
qcom,usb-bam-max-mbps-highspeed = <400>;
|
||||
qcom,usb-bam-max-mbps-superspeed = <3600>;
|
||||
qcom,reset-bam-on-connect;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
qcom,pipe0 {
|
||||
label = "ssusb-qdss-in-0";
|
||||
qcom,usb-bam-mem-type = <2>;
|
||||
qcom,dir = <1>;
|
||||
qcom,pipe-num = <0>;
|
||||
qcom,peer-bam = <0>;
|
||||
qcom,peer-bam-physical-address = <0x6064000>;
|
||||
qcom,src-bam-pipe-index = <0>;
|
||||
qcom,dst-bam-pipe-index = <0>;
|
||||
qcom,data-fifo-offset = <0x0>;
|
||||
qcom,data-fifo-size = <0x1800>;
|
||||
qcom,descriptor-fifo-offset = <0x1800>;
|
||||
qcom,descriptor-fifo-size = <0x800>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary USB port related High Speed PHY */
|
||||
usb2_phy0: hsphy@88e2000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e2000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&pm8150_1_l5>;
|
||||
vdda18-supply = <&pm8150_1_l12>;
|
||||
vdda33-supply = <&pm8150_1_l2>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&dummycc RPMH_CXO_CLK>;
|
||||
clock-names = "ref_clk_src";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70
|
||||
0x01 0xb0>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2phy_ac_en1_default>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* Secondary USB port related controller */
|
||||
usb1: ssusb@a800000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0x0a800000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0x160 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
qcom,default-mode-host;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk", "xo";
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
|
||||
qcom,charging-disabled;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0a800000 0xcd00>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
snps,ssp-u3-u0-quirk;
|
||||
snps,usb3-u1u2-disable;
|
||||
usb-core-id = <1>;
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "super-speed-plus";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
/* Secondary USB port related High Speed PHY */
|
||||
usb2_phy1: hsphy@88e3000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e3000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&pm8150_1_l5>;
|
||||
vdda18-supply = <&pm8150_1_l12>;
|
||||
vdda33-supply = <&pm8150_1_l2>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&dummycc RPMH_CXO_CLK>;
|
||||
clock-names = "ref_clk_src";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70
|
||||
0x01 0xb0>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2phy_ac_en2_default>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Secondary USB port related QMP PHY */
|
||||
usb_qmp_phy: ssphy@88eb000 {
|
||||
compatible = "qcom,usb-ssphy-qmp-v2";
|
||||
reg = <0x88eb000 0x1000>,
|
||||
<0x088eb88c 0x4>;
|
||||
reg-names = "qmp_phy_base",
|
||||
"pcs_clamp_enable_reg";
|
||||
|
||||
vdd-supply = <&pm8150_1_l5>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
qcom,vdd-max-load-uA = <47000>;
|
||||
core-supply = <&pm8150_2_l8>;
|
||||
qcom,vbus-valid-override;
|
||||
qcom,qmp-phy-init-seq =
|
||||
/* <reg_offset, value, delay> */
|
||||
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
|
||||
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
|
||||
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
|
||||
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
|
||||
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
|
||||
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
|
||||
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
|
||||
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
|
||||
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
|
||||
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
|
||||
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
|
||||
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
|
||||
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
|
||||
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
|
||||
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
|
||||
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0
|
||||
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
|
||||
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
|
||||
USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
|
||||
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
|
||||
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
|
||||
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
|
||||
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
|
||||
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
|
||||
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
|
||||
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0
|
||||
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
|
||||
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
|
||||
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
|
||||
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
|
||||
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
|
||||
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
|
||||
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
|
||||
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
|
||||
USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
|
||||
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
|
||||
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
|
||||
USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
|
||||
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
|
||||
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
|
||||
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
|
||||
0xffffffff 0xffffffff 0x00>;
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<USB3_UNI_PCS_PCS_STATUS1
|
||||
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||||
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||||
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
||||
USB3_UNI_PCS_SW_RESET
|
||||
USB3_UNI_PCS_START_CONTROL>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
||||
<&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||||
"ref_clk", "com_aux_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset", "phy_phy_reset";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,scc-sm8150.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "quin-vm-common.dtsi"
|
||||
|
|
@ -8,10 +10,24 @@
|
|||
model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine";
|
||||
qcom,msm-name = "SA8155 V2";
|
||||
qcom,msm-id = <362 0x20000>;
|
||||
|
||||
aliases {
|
||||
hsuart0 = &qupv3_se13_4uart;
|
||||
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&soc {
|
||||
VDD_CX_LEVEL: VDD_MMCX_LEVEL:
|
||||
S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8150_2_s9_level";
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
apps_smmu: apps-smmu@0x15000000 {
|
||||
compatible = "qcom,qsmmu-v500";
|
||||
reg = <0x15000000 0x100000>,
|
||||
|
|
@ -107,6 +123,80 @@
|
|||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdhc_2: sdhci@8804000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x8804000 0x1000>;
|
||||
reg-names = "hc_mem";
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
|
||||
bus-width = <4>;
|
||||
qcom,restore-after-cx-collapse;
|
||||
|
||||
qcom,msm-bus,name = "sdhc2";
|
||||
qcom,msm-bus,num-cases = <6>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
/* No vote */
|
||||
<0 0>, <0 0>,
|
||||
/* 25 MB/s */
|
||||
<65360 100000>, <100000 100000>,
|
||||
/* 50 MB/s */
|
||||
<130718 200000>, <133320 133320>,
|
||||
/* 100 MB/s */
|
||||
<261438 200000>, <150000 150000>,
|
||||
/* 200 MB/s */
|
||||
<261438 400000>, <300000 300000>,
|
||||
/* Max. bandwidth */
|
||||
<1338562 4096000>, <1338562 4096000>;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
|
||||
|
||||
qcom,devfreq,freq-table = <50000000 201500000>;
|
||||
|
||||
vdd-supply = <&pm8150_1_l17>;
|
||||
qcom,vdd-voltage-level = <2950000 2960000>;
|
||||
qcom,vdd-current-level = <200 800000>;
|
||||
|
||||
vdd-io-supply = <&pm8150_2_l13>;
|
||||
qcom,vdd-io-voltage-level = <1808000 2960000>;
|
||||
qcom,vdd-io-current-level = <200 22000>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_on>;
|
||||
pinctrl-1 = <&sdc2_off>;
|
||||
|
||||
broken-cd;
|
||||
qcom,nonhotplug;
|
||||
status = "disabled";
|
||||
|
||||
qos0 {
|
||||
mask = <0x3f>;
|
||||
vote = <44>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0xc0>;
|
||||
vote = <44>;
|
||||
};
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sm8150-pdc";
|
||||
reg = <0xb220000 0x30000>;
|
||||
qcom,pdc-ranges = <6 486 6>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
®ulator {
|
||||
|
|
@ -194,3 +284,38 @@
|
|||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "sm8150-pinctrl.dtsi"
|
||||
#include "sm8150-slpi-pinctrl.dtsi"
|
||||
#include "sa8155-vm-usb.dtsi"
|
||||
#include "sa8155-vm-pcie.dtsi"
|
||||
#include "sm8150-qupv3.dtsi"
|
||||
#include "sm8150-ssc-qupv3.dtsi"
|
||||
|
||||
&tlmm {
|
||||
/delete-property/ wakeup-parent;
|
||||
};
|
||||
|
||||
&slpi_tlmm {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
||||
&qupv3_2 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
||||
&qupv3_3 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue