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serial: tegra: Fix a mask operation that is always true
commit 3ddb4ce1e6e3bd112778ab93bbd9092f23a878ec upstream.
Currently the expression lsr | UART_LSR_TEMT is always true and
this seems suspect. I believe the intent was to mask lsr with UART_LSR_TEMT
to check that bit, so the expression should be using the & operator
instead. Fix this.
Fixes: b9c2470fb1 ("serial: tegra: flush the RX fifo on frame error")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20210426105514.23268-1-colin.king@canonical.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 1 additions and 1 deletions
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@ -332,7 +332,7 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
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do {
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lsr = tegra_uart_read(tup, UART_LSR);
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if ((lsr | UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
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if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
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break;
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udelay(1);
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} while (--tmout);
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