ARM: SoC driver updates for v5.4

The branch contains driver changes that are tightly
 connected to SoC specific code. Aside from smaller
 cleanups and bug fixes, here is a list of the notable
 changes.
 
 New device drivers:
 
 - The Turris Mox router has a new "moxtet" bus driver
   for its on-board pluggable extension bus. The
   same platform also gains a firmware driver.
 
 - The Samsung Exynos family gains a new Chipid driver
   exporting using the soc device sysfs interface
 
 - A similar socinfo driver for Qualcomm Snapdragon
   chips.
 
 - A firmware driver for the NXP i.MX DSP IPC protocol
   using shared memory and a mailbox
 
 Other changes:
 
 - The i.MX reset controller driver now supports the
   NXP i.MX8MM chip
 
 - Amlogic SoC specific drivers gain support for
   the S905X3 and A311D chips
 
 - A rework of the TI Davinci framebuffer driver to
   allow important cleanups in the platform code
 
 - A couple of device drivers for removed ARM SoC
   platforms are removed. Most of the removals were
   picked up by other maintainers, this contains
   whatever was left.
 
 Signed-off-by: Arnd Bergmann <[email protected]>
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "This contains driver changes that are tightly connected to SoC
  specific code. Aside from smaller cleanups and bug fixes, here is a
  list of the notable changes.

  New device drivers:

   - The Turris Mox router has a new "moxtet" bus driver for its
     on-board pluggable extension bus. The same platform also gains a
     firmware driver.

   - The Samsung Exynos family gains a new Chipid driver exporting using
     the soc device sysfs interface

   - A similar socinfo driver for Qualcomm Snapdragon chips.

   - A firmware driver for the NXP i.MX DSP IPC protocol using shared
     memory and a mailbox

  Other changes:

   - The i.MX reset controller driver now supports the NXP i.MX8MM chip

   - Amlogic SoC specific drivers gain support for the S905X3 and A311D
     chips

   - A rework of the TI Davinci framebuffer driver to allow important
     cleanups in the platform code

   - A couple of device drivers for removed ARM SoC platforms are
     removed. Most of the removals were picked up by other maintainers,
     this contains whatever was left"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
  bus: uniphier-system-bus: use devm_platform_ioremap_resource()
  soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
  dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
  firmware: ti_sci: Allow for device shared and exclusive requests
  bus: imx-weim: remove incorrect __init annotations
  fbdev: remove w90x900/nuc900 platform drivers
  spi: remove w90x900 driver
  net: remove w90p910-ether driver
  net: remove ks8695 driver
  firmware: turris-mox-rwtm: Add sysfs documentation
  firmware: Add Turris Mox rWTM firmware driver
  dt-bindings: firmware: Document cznic,turris-mox-rwtm binding
  bus: moxtet: fix unsigned comparison to less than zero
  bus: moxtet: remove set but not used variable 'dummy'
  ARM: scoop: Use the right include
  dt-bindings: power: add Amlogic Everything-Else power domains bindings
  soc: amlogic: Add support for Everything-Else power domains controller
  fbdev: da8xx: use resource management for dma
  fbdev: da8xx-fb: drop a redundant if
  fbdev: da8xx-fb: use devm_platform_ioremap_resource()
  ...
This commit is contained in:
Linus Torvalds 2019-09-16 15:52:38 -07:00
commit 399eb9b6cb
128 changed files with 5409 additions and 4954 deletions

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@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Constant for device tree bindings for Turris Mox module configuration bus
*
* Copyright (C) 2019 Marek Behun <marek.behun@nic.cz>
*/
#ifndef _DT_BINDINGS_BUS_MOXTET_H
#define _DT_BINDINGS_BUS_MOXTET_H
#define MOXTET_IRQ_PCI 0
#define MOXTET_IRQ_USB3 4
#define MOXTET_IRQ_PERIDOT(n) (8 + (n))
#define MOXTET_IRQ_TOPAZ 12
#endif /* _DT_BINDINGS_BUS_MOXTET_H */

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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
#define _DT_BINDINGS_MESON_G12A_POWER_H
#define PWRC_G12A_VPU_ID 0
#define PWRC_G12A_ETH_ID 1
#endif

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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
#define _DT_BINDINGS_MESON_SM1_POWER_H
#define PWRC_SM1_VPU_ID 0
#define PWRC_SM1_NNA_ID 1
#define PWRC_SM1_USB_ID 2
#define PWRC_SM1_PCIE_ID 3
#define PWRC_SM1_GE2D_ID 4
#define PWRC_SM1_AUDIO_ID 5
#define PWRC_SM1_ETH_ID 6
#endif

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@ -1,56 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
* The full GNU General Public License is included in this distribution
* in the file called COPYING.
*
* BSD LICENSE
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H

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@ -1,56 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
* The full GNU General Public License is included in this distribution
* in the file called COPYING.
*
* BSD LICENSE
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H

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@ -31,33 +31,33 @@
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
#define IMX8MQ_RESET_PCIEPHY 26
#define IMX8MQ_RESET_PCIEPHY_PERST 27
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_DISP_RESET 31
#define IMX8MQ_RESET_GPU_RESET 32
#define IMX8MQ_RESET_VPU_RESET 33
#define IMX8MQ_RESET_PCIEPHY2 34
#define IMX8MQ_RESET_PCIEPHY2_PERST 35
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_DDRC1_PRST 44
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
#define IMX8MQ_RESET_DDRC2_PRST 47
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
#define IMX8MQ_RESET_NUM 50

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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define TI_SCI_PD_EXCLUSIVE 1
#define TI_SCI_PD_SHARED 0
#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */