Allwinner sunxi DT additions for 3.10

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Merge tag 'sunxi-dt-for-3.10' of git://github.com/mripard/linux into next/dt

From Maxime Ripard <maxime.ripard@free-electrons.com>:

Allwinner sunxi DT additions for 3.10

* tag 'sunxi-dt-for-3.10' of git://github.com/mripard/linux:
  arm: sunxi: Add clock definitions for the new clock driver
  ARM: sunxi: dt: Add support for the PineRiver Mini X-plus
  sunxi: a10-cubieboard: Add user LEDs to the device tree
  sunxi: a13-olinuxino: Add user LED to the device tree
  sunxi: dts: Report the pinctrl nodes as gpio-controllers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-03-23 10:59:10 +01:00
commit 39cd0fbe62
6 changed files with 164 additions and 5 deletions

View file

@ -27,6 +27,15 @@
};
soc {
pinctrl@01c20800 {
led_pins_cubieboard: led_pins@0 {
allwinner,pins = "PH20", "PH21";
allwinner,function = "gpio_out";
allwinner,drive = <1>;
allwinner,pull = <0>;
};
};
uart0: uart@01c28000 {
status = "okay";
};
@ -35,4 +44,21 @@
status = "okay";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_cubieboard>;
blue {
label = "cubieboard::blue";
gpios = <&pio 7 21 0>; /* LED1 */
};
green {
label = "cubieboard::green";
gpios = <&pio 7 20 0>; /* LED2 */
linux,default-trigger = "heartbeat";
};
};
};

View file

@ -0,0 +1,32 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun4i-a10.dtsi"
/ {
model = "PineRiver Mini X-Plus";
compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc {
uart0: uart@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};
};

View file

@ -18,11 +18,13 @@
};
soc {
pinctrl@01c20800 {
pio: pinctrl@01c20800 {
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PB22", "PB23";

View file

@ -23,10 +23,30 @@
};
soc {
pinctrl@01c20800 {
led_pins_olinuxino: led_pins@0 {
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
allwinner,drive = <1>;
allwinner,pull = <0>;
};
};
uart1: uart@01c28400 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
power {
gpios = <&pio 6 9 0>;
default-state = "on";
};
};
};

View file

@ -19,11 +19,13 @@
};
soc {
pinctrl@01c20800 {
pio: pinctrl@01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
uart1_pins_a: uart1@0 {
allwinner,pins = "PE10", "PE11";

View file

@ -24,13 +24,90 @@
clocks {
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges;
osc: oscillator {
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
osc24M_fixed: osc24M_fixed {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
};
osc32k: osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
};
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
};
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
};
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
};
/* dummy is pll62 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&dummy>, <&osc32k>;
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};
};
soc {
@ -44,7 +121,7 @@
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc>;
clocks = <&osc24M>;
};
wdt: watchdog@01c20c90 {